2 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
3 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
5 Based on the original rt2800pci.c and rt2800usb.c.
6 Copyright (C) 2009 Ivo van Doorn <IvDoorn@gmail.com>
7 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
8 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
9 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
10 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
11 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
12 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
13 <http://rt2x00.serialmonkey.com>
15 This program is free software; you can redistribute it and/or modify
16 it under the terms of the GNU General Public License as published by
17 the Free Software Foundation; either version 2 of the License, or
18 (at your option) any later version.
20 This program is distributed in the hope that it will be useful,
21 but WITHOUT ANY WARRANTY; without even the implied warranty of
22 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 GNU General Public License for more details.
25 You should have received a copy of the GNU General Public License
26 along with this program; if not, write to the
27 Free Software Foundation, Inc.,
28 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
33 Abstract: rt2800 generic device routines.
36 #include <linux/kernel.h>
37 #include <linux/module.h>
38 #include <linux/slab.h>
41 #if defined(CONFIG_RT2X00_LIB_USB) || defined(CONFIG_RT2X00_LIB_USB_MODULE)
42 #include "rt2x00usb.h"
44 #include "rt2800lib.h"
46 #include "rt2800usb.h"
48 MODULE_AUTHOR("Bartlomiej Zolnierkiewicz");
49 MODULE_DESCRIPTION("rt2800 library");
50 MODULE_LICENSE("GPL");
54 * All access to the CSR registers will go through the methods
55 * rt2800_register_read and rt2800_register_write.
56 * BBP and RF register require indirect register access,
57 * and use the CSR registers BBPCSR and RFCSR to achieve this.
58 * These indirect registers work with busy bits,
59 * and we will try maximal REGISTER_BUSY_COUNT times to access
60 * the register while taking a REGISTER_BUSY_DELAY us delay
61 * between each attampt. When the busy bit is still set at that time,
62 * the access attempt is considered to have failed,
63 * and we will print an error.
64 * The _lock versions must be used if you already hold the csr_mutex
66 #define WAIT_FOR_BBP(__dev, __reg) \
67 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
68 #define WAIT_FOR_RFCSR(__dev, __reg) \
69 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
70 #define WAIT_FOR_RF(__dev, __reg) \
71 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
72 #define WAIT_FOR_MCU(__dev, __reg) \
73 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
74 H2M_MAILBOX_CSR_OWNER, (__reg))
76 static inline bool rt2800_is_305x_soc(struct rt2x00_dev
*rt2x00dev
)
78 /* check for rt2872 on SoC */
79 if (!rt2x00_is_soc(rt2x00dev
) ||
80 !rt2x00_rt(rt2x00dev
, RT2872
))
83 /* we know for sure that these rf chipsets are used on rt305x boards */
84 if (rt2x00_rf(rt2x00dev
, RF3020
) ||
85 rt2x00_rf(rt2x00dev
, RF3021
) ||
86 rt2x00_rf(rt2x00dev
, RF3022
))
89 NOTICE(rt2x00dev
, "Unknown RF chipset on rt305x\n");
93 static void rt2800_bbp_write(struct rt2x00_dev
*rt2x00dev
,
94 const unsigned int word
, const u8 value
)
98 mutex_lock(&rt2x00dev
->csr_mutex
);
101 * Wait until the BBP becomes available, afterwards we
102 * can safely write the new data into the register.
104 if (WAIT_FOR_BBP(rt2x00dev
, ®
)) {
106 rt2x00_set_field32(®
, BBP_CSR_CFG_VALUE
, value
);
107 rt2x00_set_field32(®
, BBP_CSR_CFG_REGNUM
, word
);
108 rt2x00_set_field32(®
, BBP_CSR_CFG_BUSY
, 1);
109 rt2x00_set_field32(®
, BBP_CSR_CFG_READ_CONTROL
, 0);
110 if (rt2x00_is_pci(rt2x00dev
) || rt2x00_is_soc(rt2x00dev
))
111 rt2x00_set_field32(®
, BBP_CSR_CFG_BBP_RW_MODE
, 1);
113 rt2800_register_write_lock(rt2x00dev
, BBP_CSR_CFG
, reg
);
116 mutex_unlock(&rt2x00dev
->csr_mutex
);
119 static void rt2800_bbp_read(struct rt2x00_dev
*rt2x00dev
,
120 const unsigned int word
, u8
*value
)
124 mutex_lock(&rt2x00dev
->csr_mutex
);
127 * Wait until the BBP becomes available, afterwards we
128 * can safely write the read request into the register.
129 * After the data has been written, we wait until hardware
130 * returns the correct value, if at any time the register
131 * doesn't become available in time, reg will be 0xffffffff
132 * which means we return 0xff to the caller.
134 if (WAIT_FOR_BBP(rt2x00dev
, ®
)) {
136 rt2x00_set_field32(®
, BBP_CSR_CFG_REGNUM
, word
);
137 rt2x00_set_field32(®
, BBP_CSR_CFG_BUSY
, 1);
138 rt2x00_set_field32(®
, BBP_CSR_CFG_READ_CONTROL
, 1);
139 if (rt2x00_is_pci(rt2x00dev
) || rt2x00_is_soc(rt2x00dev
))
140 rt2x00_set_field32(®
, BBP_CSR_CFG_BBP_RW_MODE
, 1);
142 rt2800_register_write_lock(rt2x00dev
, BBP_CSR_CFG
, reg
);
144 WAIT_FOR_BBP(rt2x00dev
, ®
);
147 *value
= rt2x00_get_field32(reg
, BBP_CSR_CFG_VALUE
);
149 mutex_unlock(&rt2x00dev
->csr_mutex
);
152 static void rt2800_rfcsr_write(struct rt2x00_dev
*rt2x00dev
,
153 const unsigned int word
, const u8 value
)
157 mutex_lock(&rt2x00dev
->csr_mutex
);
160 * Wait until the RFCSR becomes available, afterwards we
161 * can safely write the new data into the register.
163 if (WAIT_FOR_RFCSR(rt2x00dev
, ®
)) {
165 rt2x00_set_field32(®
, RF_CSR_CFG_DATA
, value
);
166 rt2x00_set_field32(®
, RF_CSR_CFG_REGNUM
, word
);
167 rt2x00_set_field32(®
, RF_CSR_CFG_WRITE
, 1);
168 rt2x00_set_field32(®
, RF_CSR_CFG_BUSY
, 1);
170 rt2800_register_write_lock(rt2x00dev
, RF_CSR_CFG
, reg
);
173 mutex_unlock(&rt2x00dev
->csr_mutex
);
176 static void rt2800_rfcsr_read(struct rt2x00_dev
*rt2x00dev
,
177 const unsigned int word
, u8
*value
)
181 mutex_lock(&rt2x00dev
->csr_mutex
);
184 * Wait until the RFCSR becomes available, afterwards we
185 * can safely write the read request into the register.
186 * After the data has been written, we wait until hardware
187 * returns the correct value, if at any time the register
188 * doesn't become available in time, reg will be 0xffffffff
189 * which means we return 0xff to the caller.
191 if (WAIT_FOR_RFCSR(rt2x00dev
, ®
)) {
193 rt2x00_set_field32(®
, RF_CSR_CFG_REGNUM
, word
);
194 rt2x00_set_field32(®
, RF_CSR_CFG_WRITE
, 0);
195 rt2x00_set_field32(®
, RF_CSR_CFG_BUSY
, 1);
197 rt2800_register_write_lock(rt2x00dev
, RF_CSR_CFG
, reg
);
199 WAIT_FOR_RFCSR(rt2x00dev
, ®
);
202 *value
= rt2x00_get_field32(reg
, RF_CSR_CFG_DATA
);
204 mutex_unlock(&rt2x00dev
->csr_mutex
);
207 static void rt2800_rf_write(struct rt2x00_dev
*rt2x00dev
,
208 const unsigned int word
, const u32 value
)
212 mutex_lock(&rt2x00dev
->csr_mutex
);
215 * Wait until the RF becomes available, afterwards we
216 * can safely write the new data into the register.
218 if (WAIT_FOR_RF(rt2x00dev
, ®
)) {
220 rt2x00_set_field32(®
, RF_CSR_CFG0_REG_VALUE_BW
, value
);
221 rt2x00_set_field32(®
, RF_CSR_CFG0_STANDBYMODE
, 0);
222 rt2x00_set_field32(®
, RF_CSR_CFG0_SEL
, 0);
223 rt2x00_set_field32(®
, RF_CSR_CFG0_BUSY
, 1);
225 rt2800_register_write_lock(rt2x00dev
, RF_CSR_CFG0
, reg
);
226 rt2x00_rf_write(rt2x00dev
, word
, value
);
229 mutex_unlock(&rt2x00dev
->csr_mutex
);
232 void rt2800_mcu_request(struct rt2x00_dev
*rt2x00dev
,
233 const u8 command
, const u8 token
,
234 const u8 arg0
, const u8 arg1
)
239 * SOC devices don't support MCU requests.
241 if (rt2x00_is_soc(rt2x00dev
))
244 mutex_lock(&rt2x00dev
->csr_mutex
);
247 * Wait until the MCU becomes available, afterwards we
248 * can safely write the new data into the register.
250 if (WAIT_FOR_MCU(rt2x00dev
, ®
)) {
251 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_OWNER
, 1);
252 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_CMD_TOKEN
, token
);
253 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_ARG0
, arg0
);
254 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_ARG1
, arg1
);
255 rt2800_register_write_lock(rt2x00dev
, H2M_MAILBOX_CSR
, reg
);
258 rt2x00_set_field32(®
, HOST_CMD_CSR_HOST_COMMAND
, command
);
259 rt2800_register_write_lock(rt2x00dev
, HOST_CMD_CSR
, reg
);
262 mutex_unlock(&rt2x00dev
->csr_mutex
);
264 EXPORT_SYMBOL_GPL(rt2800_mcu_request
);
266 int rt2800_wait_wpdma_ready(struct rt2x00_dev
*rt2x00dev
)
271 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
272 rt2800_register_read(rt2x00dev
, WPDMA_GLO_CFG
, ®
);
273 if (!rt2x00_get_field32(reg
, WPDMA_GLO_CFG_TX_DMA_BUSY
) &&
274 !rt2x00_get_field32(reg
, WPDMA_GLO_CFG_RX_DMA_BUSY
))
280 ERROR(rt2x00dev
, "WPDMA TX/RX busy, aborting.\n");
283 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready
);
285 void rt2800_write_txwi(__le32
*txwi
, struct txentry_desc
*txdesc
)
290 * Initialize TX Info descriptor
292 rt2x00_desc_read(txwi
, 0, &word
);
293 rt2x00_set_field32(&word
, TXWI_W0_FRAG
,
294 test_bit(ENTRY_TXD_MORE_FRAG
, &txdesc
->flags
));
295 rt2x00_set_field32(&word
, TXWI_W0_MIMO_PS
, 0);
296 rt2x00_set_field32(&word
, TXWI_W0_CF_ACK
, 0);
297 rt2x00_set_field32(&word
, TXWI_W0_TS
,
298 test_bit(ENTRY_TXD_REQ_TIMESTAMP
, &txdesc
->flags
));
299 rt2x00_set_field32(&word
, TXWI_W0_AMPDU
,
300 test_bit(ENTRY_TXD_HT_AMPDU
, &txdesc
->flags
));
301 rt2x00_set_field32(&word
, TXWI_W0_MPDU_DENSITY
, txdesc
->mpdu_density
);
302 rt2x00_set_field32(&word
, TXWI_W0_TX_OP
, txdesc
->txop
);
303 rt2x00_set_field32(&word
, TXWI_W0_MCS
, txdesc
->mcs
);
304 rt2x00_set_field32(&word
, TXWI_W0_BW
,
305 test_bit(ENTRY_TXD_HT_BW_40
, &txdesc
->flags
));
306 rt2x00_set_field32(&word
, TXWI_W0_SHORT_GI
,
307 test_bit(ENTRY_TXD_HT_SHORT_GI
, &txdesc
->flags
));
308 rt2x00_set_field32(&word
, TXWI_W0_STBC
, txdesc
->stbc
);
309 rt2x00_set_field32(&word
, TXWI_W0_PHYMODE
, txdesc
->rate_mode
);
310 rt2x00_desc_write(txwi
, 0, word
);
312 rt2x00_desc_read(txwi
, 1, &word
);
313 rt2x00_set_field32(&word
, TXWI_W1_ACK
,
314 test_bit(ENTRY_TXD_ACK
, &txdesc
->flags
));
315 rt2x00_set_field32(&word
, TXWI_W1_NSEQ
,
316 test_bit(ENTRY_TXD_GENERATE_SEQ
, &txdesc
->flags
));
317 rt2x00_set_field32(&word
, TXWI_W1_BW_WIN_SIZE
, txdesc
->ba_size
);
318 rt2x00_set_field32(&word
, TXWI_W1_WIRELESS_CLI_ID
,
319 test_bit(ENTRY_TXD_ENCRYPT
, &txdesc
->flags
) ?
320 txdesc
->key_idx
: 0xff);
321 rt2x00_set_field32(&word
, TXWI_W1_MPDU_TOTAL_BYTE_COUNT
,
323 rt2x00_set_field32(&word
, TXWI_W1_PACKETID
, txdesc
->queue
+ 1);
324 rt2x00_desc_write(txwi
, 1, word
);
327 * Always write 0 to IV/EIV fields, hardware will insert the IV
328 * from the IVEIV register when TXD_W3_WIV is set to 0.
329 * When TXD_W3_WIV is set to 1 it will use the IV data
330 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
331 * crypto entry in the registers should be used to encrypt the frame.
333 _rt2x00_desc_write(txwi
, 2, 0 /* skbdesc->iv[0] */);
334 _rt2x00_desc_write(txwi
, 3, 0 /* skbdesc->iv[1] */);
336 EXPORT_SYMBOL_GPL(rt2800_write_txwi
);
338 void rt2800_process_rxwi(struct sk_buff
*skb
, struct rxdone_entry_desc
*rxdesc
)
340 __le32
*rxwi
= (__le32
*) skb
->data
;
343 rt2x00_desc_read(rxwi
, 0, &word
);
345 rxdesc
->cipher
= rt2x00_get_field32(word
, RXWI_W0_UDF
);
346 rxdesc
->size
= rt2x00_get_field32(word
, RXWI_W0_MPDU_TOTAL_BYTE_COUNT
);
348 rt2x00_desc_read(rxwi
, 1, &word
);
350 if (rt2x00_get_field32(word
, RXWI_W1_SHORT_GI
))
351 rxdesc
->flags
|= RX_FLAG_SHORT_GI
;
353 if (rt2x00_get_field32(word
, RXWI_W1_BW
))
354 rxdesc
->flags
|= RX_FLAG_40MHZ
;
357 * Detect RX rate, always use MCS as signal type.
359 rxdesc
->dev_flags
|= RXDONE_SIGNAL_MCS
;
360 rxdesc
->signal
= rt2x00_get_field32(word
, RXWI_W1_MCS
);
361 rxdesc
->rate_mode
= rt2x00_get_field32(word
, RXWI_W1_PHYMODE
);
364 * Mask of 0x8 bit to remove the short preamble flag.
366 if (rxdesc
->rate_mode
== RATE_MODE_CCK
)
367 rxdesc
->signal
&= ~0x8;
369 rt2x00_desc_read(rxwi
, 2, &word
);
372 (rt2x00_get_field32(word
, RXWI_W2_RSSI0
) +
373 rt2x00_get_field32(word
, RXWI_W2_RSSI1
)) / 2;
376 * Remove RXWI descriptor from start of buffer.
378 skb_pull(skb
, RXWI_DESC_SIZE
);
380 EXPORT_SYMBOL_GPL(rt2800_process_rxwi
);
382 void rt2800_write_beacon(struct queue_entry
*entry
, struct txentry_desc
*txdesc
)
384 struct rt2x00_dev
*rt2x00dev
= entry
->queue
->rt2x00dev
;
385 struct skb_frame_desc
*skbdesc
= get_skb_frame_desc(entry
->skb
);
386 unsigned int beacon_base
;
390 * Disable beaconing while we are reloading the beacon data,
391 * otherwise we might be sending out invalid data.
393 rt2800_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
394 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_GEN
, 0);
395 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
398 * Add space for the TXWI in front of the skb.
400 skb_push(entry
->skb
, TXWI_DESC_SIZE
);
401 memset(entry
->skb
, 0, TXWI_DESC_SIZE
);
404 * Register descriptor details in skb frame descriptor.
406 skbdesc
->flags
|= SKBDESC_DESC_IN_SKB
;
407 skbdesc
->desc
= entry
->skb
->data
;
408 skbdesc
->desc_len
= TXWI_DESC_SIZE
;
411 * Add the TXWI for the beacon to the skb.
413 rt2800_write_txwi((__le32
*)entry
->skb
->data
, txdesc
);
416 * Dump beacon to userspace through debugfs.
418 rt2x00debug_dump_frame(rt2x00dev
, DUMP_FRAME_BEACON
, entry
->skb
);
421 * Write entire beacon with TXWI to register.
423 beacon_base
= HW_BEACON_OFFSET(entry
->entry_idx
);
424 rt2800_register_multiwrite(rt2x00dev
, beacon_base
,
425 entry
->skb
->data
, entry
->skb
->len
);
428 * Enable beaconing again.
430 rt2x00_set_field32(®
, BCN_TIME_CFG_TSF_TICKING
, 1);
431 rt2x00_set_field32(®
, BCN_TIME_CFG_TBTT_ENABLE
, 1);
432 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_GEN
, 1);
433 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
436 * Clean up beacon skb.
438 dev_kfree_skb_any(entry
->skb
);
441 EXPORT_SYMBOL(rt2800_write_beacon
);
443 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
444 const struct rt2x00debug rt2800_rt2x00debug
= {
445 .owner
= THIS_MODULE
,
447 .read
= rt2800_register_read
,
448 .write
= rt2800_register_write
,
449 .flags
= RT2X00DEBUGFS_OFFSET
,
450 .word_base
= CSR_REG_BASE
,
451 .word_size
= sizeof(u32
),
452 .word_count
= CSR_REG_SIZE
/ sizeof(u32
),
455 .read
= rt2x00_eeprom_read
,
456 .write
= rt2x00_eeprom_write
,
457 .word_base
= EEPROM_BASE
,
458 .word_size
= sizeof(u16
),
459 .word_count
= EEPROM_SIZE
/ sizeof(u16
),
462 .read
= rt2800_bbp_read
,
463 .write
= rt2800_bbp_write
,
464 .word_base
= BBP_BASE
,
465 .word_size
= sizeof(u8
),
466 .word_count
= BBP_SIZE
/ sizeof(u8
),
469 .read
= rt2x00_rf_read
,
470 .write
= rt2800_rf_write
,
471 .word_base
= RF_BASE
,
472 .word_size
= sizeof(u32
),
473 .word_count
= RF_SIZE
/ sizeof(u32
),
476 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug
);
477 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
479 int rt2800_rfkill_poll(struct rt2x00_dev
*rt2x00dev
)
483 rt2800_register_read(rt2x00dev
, GPIO_CTRL_CFG
, ®
);
484 return rt2x00_get_field32(reg
, GPIO_CTRL_CFG_BIT2
);
486 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll
);
488 #ifdef CONFIG_RT2X00_LIB_LEDS
489 static void rt2800_brightness_set(struct led_classdev
*led_cdev
,
490 enum led_brightness brightness
)
492 struct rt2x00_led
*led
=
493 container_of(led_cdev
, struct rt2x00_led
, led_dev
);
494 unsigned int enabled
= brightness
!= LED_OFF
;
495 unsigned int bg_mode
=
496 (enabled
&& led
->rt2x00dev
->curr_band
== IEEE80211_BAND_2GHZ
);
497 unsigned int polarity
=
498 rt2x00_get_field16(led
->rt2x00dev
->led_mcu_reg
,
499 EEPROM_FREQ_LED_POLARITY
);
500 unsigned int ledmode
=
501 rt2x00_get_field16(led
->rt2x00dev
->led_mcu_reg
,
502 EEPROM_FREQ_LED_MODE
);
504 if (led
->type
== LED_TYPE_RADIO
) {
505 rt2800_mcu_request(led
->rt2x00dev
, MCU_LED
, 0xff, ledmode
,
507 } else if (led
->type
== LED_TYPE_ASSOC
) {
508 rt2800_mcu_request(led
->rt2x00dev
, MCU_LED
, 0xff, ledmode
,
509 enabled
? (bg_mode
? 0x60 : 0xa0) : 0x20);
510 } else if (led
->type
== LED_TYPE_QUALITY
) {
512 * The brightness is divided into 6 levels (0 - 5),
513 * The specs tell us the following levels:
515 * to determine the level in a simple way we can simply
516 * work with bitshifting:
519 rt2800_mcu_request(led
->rt2x00dev
, MCU_LED_STRENGTH
, 0xff,
520 (1 << brightness
/ (LED_FULL
/ 6)) - 1,
525 static int rt2800_blink_set(struct led_classdev
*led_cdev
,
526 unsigned long *delay_on
, unsigned long *delay_off
)
528 struct rt2x00_led
*led
=
529 container_of(led_cdev
, struct rt2x00_led
, led_dev
);
532 rt2800_register_read(led
->rt2x00dev
, LED_CFG
, ®
);
533 rt2x00_set_field32(®
, LED_CFG_ON_PERIOD
, *delay_on
);
534 rt2x00_set_field32(®
, LED_CFG_OFF_PERIOD
, *delay_off
);
535 rt2800_register_write(led
->rt2x00dev
, LED_CFG
, reg
);
540 static void rt2800_init_led(struct rt2x00_dev
*rt2x00dev
,
541 struct rt2x00_led
*led
, enum led_type type
)
543 led
->rt2x00dev
= rt2x00dev
;
545 led
->led_dev
.brightness_set
= rt2800_brightness_set
;
546 led
->led_dev
.blink_set
= rt2800_blink_set
;
547 led
->flags
= LED_INITIALIZED
;
549 #endif /* CONFIG_RT2X00_LIB_LEDS */
552 * Configuration handlers.
554 static void rt2800_config_wcid_attr(struct rt2x00_dev
*rt2x00dev
,
555 struct rt2x00lib_crypto
*crypto
,
556 struct ieee80211_key_conf
*key
)
558 struct mac_wcid_entry wcid_entry
;
559 struct mac_iveiv_entry iveiv_entry
;
563 offset
= MAC_WCID_ATTR_ENTRY(key
->hw_key_idx
);
565 rt2800_register_read(rt2x00dev
, offset
, ®
);
566 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_KEYTAB
,
567 !!(key
->flags
& IEEE80211_KEY_FLAG_PAIRWISE
));
568 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_CIPHER
,
569 (crypto
->cmd
== SET_KEY
) * crypto
->cipher
);
570 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_BSS_IDX
,
571 (crypto
->cmd
== SET_KEY
) * crypto
->bssidx
);
572 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_RX_WIUDF
, crypto
->cipher
);
573 rt2800_register_write(rt2x00dev
, offset
, reg
);
575 offset
= MAC_IVEIV_ENTRY(key
->hw_key_idx
);
577 memset(&iveiv_entry
, 0, sizeof(iveiv_entry
));
578 if ((crypto
->cipher
== CIPHER_TKIP
) ||
579 (crypto
->cipher
== CIPHER_TKIP_NO_MIC
) ||
580 (crypto
->cipher
== CIPHER_AES
))
581 iveiv_entry
.iv
[3] |= 0x20;
582 iveiv_entry
.iv
[3] |= key
->keyidx
<< 6;
583 rt2800_register_multiwrite(rt2x00dev
, offset
,
584 &iveiv_entry
, sizeof(iveiv_entry
));
586 offset
= MAC_WCID_ENTRY(key
->hw_key_idx
);
588 memset(&wcid_entry
, 0, sizeof(wcid_entry
));
589 if (crypto
->cmd
== SET_KEY
)
590 memcpy(&wcid_entry
, crypto
->address
, ETH_ALEN
);
591 rt2800_register_multiwrite(rt2x00dev
, offset
,
592 &wcid_entry
, sizeof(wcid_entry
));
595 int rt2800_config_shared_key(struct rt2x00_dev
*rt2x00dev
,
596 struct rt2x00lib_crypto
*crypto
,
597 struct ieee80211_key_conf
*key
)
599 struct hw_key_entry key_entry
;
600 struct rt2x00_field32 field
;
604 if (crypto
->cmd
== SET_KEY
) {
605 key
->hw_key_idx
= (4 * crypto
->bssidx
) + key
->keyidx
;
607 memcpy(key_entry
.key
, crypto
->key
,
608 sizeof(key_entry
.key
));
609 memcpy(key_entry
.tx_mic
, crypto
->tx_mic
,
610 sizeof(key_entry
.tx_mic
));
611 memcpy(key_entry
.rx_mic
, crypto
->rx_mic
,
612 sizeof(key_entry
.rx_mic
));
614 offset
= SHARED_KEY_ENTRY(key
->hw_key_idx
);
615 rt2800_register_multiwrite(rt2x00dev
, offset
,
616 &key_entry
, sizeof(key_entry
));
620 * The cipher types are stored over multiple registers
621 * starting with SHARED_KEY_MODE_BASE each word will have
622 * 32 bits and contains the cipher types for 2 bssidx each.
623 * Using the correct defines correctly will cause overhead,
624 * so just calculate the correct offset.
626 field
.bit_offset
= 4 * (key
->hw_key_idx
% 8);
627 field
.bit_mask
= 0x7 << field
.bit_offset
;
629 offset
= SHARED_KEY_MODE_ENTRY(key
->hw_key_idx
/ 8);
631 rt2800_register_read(rt2x00dev
, offset
, ®
);
632 rt2x00_set_field32(®
, field
,
633 (crypto
->cmd
== SET_KEY
) * crypto
->cipher
);
634 rt2800_register_write(rt2x00dev
, offset
, reg
);
637 * Update WCID information
639 rt2800_config_wcid_attr(rt2x00dev
, crypto
, key
);
643 EXPORT_SYMBOL_GPL(rt2800_config_shared_key
);
645 int rt2800_config_pairwise_key(struct rt2x00_dev
*rt2x00dev
,
646 struct rt2x00lib_crypto
*crypto
,
647 struct ieee80211_key_conf
*key
)
649 struct hw_key_entry key_entry
;
652 if (crypto
->cmd
== SET_KEY
) {
654 * 1 pairwise key is possible per AID, this means that the AID
655 * equals our hw_key_idx. Make sure the WCID starts _after_ the
656 * last possible shared key entry.
658 if (crypto
->aid
> (256 - 32))
661 key
->hw_key_idx
= 32 + crypto
->aid
;
663 memcpy(key_entry
.key
, crypto
->key
,
664 sizeof(key_entry
.key
));
665 memcpy(key_entry
.tx_mic
, crypto
->tx_mic
,
666 sizeof(key_entry
.tx_mic
));
667 memcpy(key_entry
.rx_mic
, crypto
->rx_mic
,
668 sizeof(key_entry
.rx_mic
));
670 offset
= PAIRWISE_KEY_ENTRY(key
->hw_key_idx
);
671 rt2800_register_multiwrite(rt2x00dev
, offset
,
672 &key_entry
, sizeof(key_entry
));
676 * Update WCID information
678 rt2800_config_wcid_attr(rt2x00dev
, crypto
, key
);
682 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key
);
684 void rt2800_config_filter(struct rt2x00_dev
*rt2x00dev
,
685 const unsigned int filter_flags
)
690 * Start configuration steps.
691 * Note that the version error will always be dropped
692 * and broadcast frames will always be accepted since
693 * there is no filter for it at this time.
695 rt2800_register_read(rt2x00dev
, RX_FILTER_CFG
, ®
);
696 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CRC_ERROR
,
697 !(filter_flags
& FIF_FCSFAIL
));
698 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_PHY_ERROR
,
699 !(filter_flags
& FIF_PLCPFAIL
));
700 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_NOT_TO_ME
,
701 !(filter_flags
& FIF_PROMISC_IN_BSS
));
702 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_NOT_MY_BSSD
, 0);
703 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_VER_ERROR
, 1);
704 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_MULTICAST
,
705 !(filter_flags
& FIF_ALLMULTI
));
706 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_BROADCAST
, 0);
707 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_DUPLICATE
, 1);
708 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CF_END_ACK
,
709 !(filter_flags
& FIF_CONTROL
));
710 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CF_END
,
711 !(filter_flags
& FIF_CONTROL
));
712 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_ACK
,
713 !(filter_flags
& FIF_CONTROL
));
714 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CTS
,
715 !(filter_flags
& FIF_CONTROL
));
716 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_RTS
,
717 !(filter_flags
& FIF_CONTROL
));
718 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_PSPOLL
,
719 !(filter_flags
& FIF_PSPOLL
));
720 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_BA
, 1);
721 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_BAR
, 0);
722 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CNTL
,
723 !(filter_flags
& FIF_CONTROL
));
724 rt2800_register_write(rt2x00dev
, RX_FILTER_CFG
, reg
);
726 EXPORT_SYMBOL_GPL(rt2800_config_filter
);
728 void rt2800_config_intf(struct rt2x00_dev
*rt2x00dev
, struct rt2x00_intf
*intf
,
729 struct rt2x00intf_conf
*conf
, const unsigned int flags
)
731 unsigned int beacon_base
;
734 if (flags
& CONFIG_UPDATE_TYPE
) {
736 * Clear current synchronisation setup.
737 * For the Beacon base registers we only need to clear
738 * the first byte since that byte contains the VALID and OWNER
739 * bits which (when set to 0) will invalidate the entire beacon.
741 beacon_base
= HW_BEACON_OFFSET(intf
->beacon
->entry_idx
);
742 rt2800_register_write(rt2x00dev
, beacon_base
, 0);
745 * Enable synchronisation.
747 rt2800_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
748 rt2x00_set_field32(®
, BCN_TIME_CFG_TSF_TICKING
, 1);
749 rt2x00_set_field32(®
, BCN_TIME_CFG_TSF_SYNC
, conf
->sync
);
750 rt2x00_set_field32(®
, BCN_TIME_CFG_TBTT_ENABLE
,
751 (conf
->sync
== TSF_SYNC_BEACON
));
752 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
755 if (flags
& CONFIG_UPDATE_MAC
) {
756 reg
= le32_to_cpu(conf
->mac
[1]);
757 rt2x00_set_field32(®
, MAC_ADDR_DW1_UNICAST_TO_ME_MASK
, 0xff);
758 conf
->mac
[1] = cpu_to_le32(reg
);
760 rt2800_register_multiwrite(rt2x00dev
, MAC_ADDR_DW0
,
761 conf
->mac
, sizeof(conf
->mac
));
764 if (flags
& CONFIG_UPDATE_BSSID
) {
765 reg
= le32_to_cpu(conf
->bssid
[1]);
766 rt2x00_set_field32(®
, MAC_BSSID_DW1_BSS_ID_MASK
, 0);
767 rt2x00_set_field32(®
, MAC_BSSID_DW1_BSS_BCN_NUM
, 0);
768 conf
->bssid
[1] = cpu_to_le32(reg
);
770 rt2800_register_multiwrite(rt2x00dev
, MAC_BSSID_DW0
,
771 conf
->bssid
, sizeof(conf
->bssid
));
774 EXPORT_SYMBOL_GPL(rt2800_config_intf
);
776 void rt2800_config_erp(struct rt2x00_dev
*rt2x00dev
, struct rt2x00lib_erp
*erp
)
780 rt2800_register_read(rt2x00dev
, AUTO_RSP_CFG
, ®
);
781 rt2x00_set_field32(®
, AUTO_RSP_CFG_BAC_ACK_POLICY
,
782 !!erp
->short_preamble
);
783 rt2x00_set_field32(®
, AUTO_RSP_CFG_AR_PREAMBLE
,
784 !!erp
->short_preamble
);
785 rt2800_register_write(rt2x00dev
, AUTO_RSP_CFG
, reg
);
787 rt2800_register_read(rt2x00dev
, OFDM_PROT_CFG
, ®
);
788 rt2x00_set_field32(®
, OFDM_PROT_CFG_PROTECT_CTRL
,
789 erp
->cts_protection
? 2 : 0);
790 rt2800_register_write(rt2x00dev
, OFDM_PROT_CFG
, reg
);
792 rt2800_register_write(rt2x00dev
, LEGACY_BASIC_RATE
,
794 rt2800_register_write(rt2x00dev
, HT_BASIC_RATE
, 0x00008003);
796 rt2800_register_read(rt2x00dev
, BKOFF_SLOT_CFG
, ®
);
797 rt2x00_set_field32(®
, BKOFF_SLOT_CFG_SLOT_TIME
, erp
->slot_time
);
798 rt2800_register_write(rt2x00dev
, BKOFF_SLOT_CFG
, reg
);
800 rt2800_register_read(rt2x00dev
, XIFS_TIME_CFG
, ®
);
801 rt2x00_set_field32(®
, XIFS_TIME_CFG_EIFS
, erp
->eifs
);
802 rt2800_register_write(rt2x00dev
, XIFS_TIME_CFG
, reg
);
804 rt2800_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
805 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_INTERVAL
,
806 erp
->beacon_int
* 16);
807 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
809 EXPORT_SYMBOL_GPL(rt2800_config_erp
);
811 void rt2800_config_ant(struct rt2x00_dev
*rt2x00dev
, struct antenna_setup
*ant
)
816 rt2800_bbp_read(rt2x00dev
, 1, &r1
);
817 rt2800_bbp_read(rt2x00dev
, 3, &r3
);
820 * Configure the TX antenna.
822 switch ((int)ant
->tx
) {
824 rt2x00_set_field8(&r1
, BBP1_TX_ANTENNA
, 0);
825 if (rt2x00_is_pci(rt2x00dev
) || rt2x00_is_soc(rt2x00dev
))
826 rt2x00_set_field8(&r3
, BBP3_RX_ANTENNA
, 0);
829 rt2x00_set_field8(&r1
, BBP1_TX_ANTENNA
, 2);
837 * Configure the RX antenna.
839 switch ((int)ant
->rx
) {
841 rt2x00_set_field8(&r3
, BBP3_RX_ANTENNA
, 0);
844 rt2x00_set_field8(&r3
, BBP3_RX_ANTENNA
, 1);
847 rt2x00_set_field8(&r3
, BBP3_RX_ANTENNA
, 2);
851 rt2800_bbp_write(rt2x00dev
, 3, r3
);
852 rt2800_bbp_write(rt2x00dev
, 1, r1
);
854 EXPORT_SYMBOL_GPL(rt2800_config_ant
);
856 static void rt2800_config_lna_gain(struct rt2x00_dev
*rt2x00dev
,
857 struct rt2x00lib_conf
*libconf
)
862 if (libconf
->rf
.channel
<= 14) {
863 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LNA
, &eeprom
);
864 lna_gain
= rt2x00_get_field16(eeprom
, EEPROM_LNA_BG
);
865 } else if (libconf
->rf
.channel
<= 64) {
866 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LNA
, &eeprom
);
867 lna_gain
= rt2x00_get_field16(eeprom
, EEPROM_LNA_A0
);
868 } else if (libconf
->rf
.channel
<= 128) {
869 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_BG2
, &eeprom
);
870 lna_gain
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_BG2_LNA_A1
);
872 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_A2
, &eeprom
);
873 lna_gain
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_A2_LNA_A2
);
876 rt2x00dev
->lna_gain
= lna_gain
;
879 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev
*rt2x00dev
,
880 struct ieee80211_conf
*conf
,
881 struct rf_channel
*rf
,
882 struct channel_info
*info
)
884 rt2x00_set_field32(&rf
->rf4
, RF4_FREQ_OFFSET
, rt2x00dev
->freq_offset
);
886 if (rt2x00dev
->default_ant
.tx
== 1)
887 rt2x00_set_field32(&rf
->rf2
, RF2_ANTENNA_TX1
, 1);
889 if (rt2x00dev
->default_ant
.rx
== 1) {
890 rt2x00_set_field32(&rf
->rf2
, RF2_ANTENNA_RX1
, 1);
891 rt2x00_set_field32(&rf
->rf2
, RF2_ANTENNA_RX2
, 1);
892 } else if (rt2x00dev
->default_ant
.rx
== 2)
893 rt2x00_set_field32(&rf
->rf2
, RF2_ANTENNA_RX2
, 1);
895 if (rf
->channel
> 14) {
897 * When TX power is below 0, we should increase it by 7 to
898 * make it a positive value (Minumum value is -7).
899 * However this means that values between 0 and 7 have
900 * double meaning, and we should set a 7DBm boost flag.
902 rt2x00_set_field32(&rf
->rf3
, RF3_TXPOWER_A_7DBM_BOOST
,
903 (info
->tx_power1
>= 0));
905 if (info
->tx_power1
< 0)
906 info
->tx_power1
+= 7;
908 rt2x00_set_field32(&rf
->rf3
, RF3_TXPOWER_A
,
909 TXPOWER_A_TO_DEV(info
->tx_power1
));
911 rt2x00_set_field32(&rf
->rf4
, RF4_TXPOWER_A_7DBM_BOOST
,
912 (info
->tx_power2
>= 0));
914 if (info
->tx_power2
< 0)
915 info
->tx_power2
+= 7;
917 rt2x00_set_field32(&rf
->rf4
, RF4_TXPOWER_A
,
918 TXPOWER_A_TO_DEV(info
->tx_power2
));
920 rt2x00_set_field32(&rf
->rf3
, RF3_TXPOWER_G
,
921 TXPOWER_G_TO_DEV(info
->tx_power1
));
922 rt2x00_set_field32(&rf
->rf4
, RF4_TXPOWER_G
,
923 TXPOWER_G_TO_DEV(info
->tx_power2
));
926 rt2x00_set_field32(&rf
->rf4
, RF4_HT40
, conf_is_ht40(conf
));
928 rt2800_rf_write(rt2x00dev
, 1, rf
->rf1
);
929 rt2800_rf_write(rt2x00dev
, 2, rf
->rf2
);
930 rt2800_rf_write(rt2x00dev
, 3, rf
->rf3
& ~0x00000004);
931 rt2800_rf_write(rt2x00dev
, 4, rf
->rf4
);
935 rt2800_rf_write(rt2x00dev
, 1, rf
->rf1
);
936 rt2800_rf_write(rt2x00dev
, 2, rf
->rf2
);
937 rt2800_rf_write(rt2x00dev
, 3, rf
->rf3
| 0x00000004);
938 rt2800_rf_write(rt2x00dev
, 4, rf
->rf4
);
942 rt2800_rf_write(rt2x00dev
, 1, rf
->rf1
);
943 rt2800_rf_write(rt2x00dev
, 2, rf
->rf2
);
944 rt2800_rf_write(rt2x00dev
, 3, rf
->rf3
& ~0x00000004);
945 rt2800_rf_write(rt2x00dev
, 4, rf
->rf4
);
948 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev
*rt2x00dev
,
949 struct ieee80211_conf
*conf
,
950 struct rf_channel
*rf
,
951 struct channel_info
*info
)
955 rt2800_rfcsr_write(rt2x00dev
, 2, rf
->rf1
);
956 rt2800_rfcsr_write(rt2x00dev
, 3, rf
->rf3
);
958 rt2800_rfcsr_read(rt2x00dev
, 6, &rfcsr
);
959 rt2x00_set_field8(&rfcsr
, RFCSR6_R1
, rf
->rf2
);
960 rt2800_rfcsr_write(rt2x00dev
, 6, rfcsr
);
962 rt2800_rfcsr_read(rt2x00dev
, 12, &rfcsr
);
963 rt2x00_set_field8(&rfcsr
, RFCSR12_TX_POWER
,
964 TXPOWER_G_TO_DEV(info
->tx_power1
));
965 rt2800_rfcsr_write(rt2x00dev
, 12, rfcsr
);
967 rt2800_rfcsr_read(rt2x00dev
, 13, &rfcsr
);
968 rt2x00_set_field8(&rfcsr
, RFCSR13_TX_POWER
,
969 TXPOWER_G_TO_DEV(info
->tx_power2
));
970 rt2800_rfcsr_write(rt2x00dev
, 13, rfcsr
);
972 rt2800_rfcsr_read(rt2x00dev
, 23, &rfcsr
);
973 rt2x00_set_field8(&rfcsr
, RFCSR23_FREQ_OFFSET
, rt2x00dev
->freq_offset
);
974 rt2800_rfcsr_write(rt2x00dev
, 23, rfcsr
);
976 rt2800_rfcsr_write(rt2x00dev
, 24,
977 rt2x00dev
->calibration
[conf_is_ht40(conf
)]);
979 rt2800_rfcsr_read(rt2x00dev
, 7, &rfcsr
);
980 rt2x00_set_field8(&rfcsr
, RFCSR7_RF_TUNING
, 1);
981 rt2800_rfcsr_write(rt2x00dev
, 7, rfcsr
);
984 static void rt2800_config_channel(struct rt2x00_dev
*rt2x00dev
,
985 struct ieee80211_conf
*conf
,
986 struct rf_channel
*rf
,
987 struct channel_info
*info
)
993 if (rt2x00_rf(rt2x00dev
, RF2020
) ||
994 rt2x00_rf(rt2x00dev
, RF3020
) ||
995 rt2x00_rf(rt2x00dev
, RF3021
) ||
996 rt2x00_rf(rt2x00dev
, RF3022
))
997 rt2800_config_channel_rf3xxx(rt2x00dev
, conf
, rf
, info
);
999 rt2800_config_channel_rf2xxx(rt2x00dev
, conf
, rf
, info
);
1002 * Change BBP settings
1004 rt2800_bbp_write(rt2x00dev
, 62, 0x37 - rt2x00dev
->lna_gain
);
1005 rt2800_bbp_write(rt2x00dev
, 63, 0x37 - rt2x00dev
->lna_gain
);
1006 rt2800_bbp_write(rt2x00dev
, 64, 0x37 - rt2x00dev
->lna_gain
);
1007 rt2800_bbp_write(rt2x00dev
, 86, 0);
1009 if (rf
->channel
<= 14) {
1010 if (test_bit(CONFIG_EXTERNAL_LNA_BG
, &rt2x00dev
->flags
)) {
1011 rt2800_bbp_write(rt2x00dev
, 82, 0x62);
1012 rt2800_bbp_write(rt2x00dev
, 75, 0x46);
1014 rt2800_bbp_write(rt2x00dev
, 82, 0x84);
1015 rt2800_bbp_write(rt2x00dev
, 75, 0x50);
1018 rt2800_bbp_write(rt2x00dev
, 82, 0xf2);
1020 if (test_bit(CONFIG_EXTERNAL_LNA_A
, &rt2x00dev
->flags
))
1021 rt2800_bbp_write(rt2x00dev
, 75, 0x46);
1023 rt2800_bbp_write(rt2x00dev
, 75, 0x50);
1026 rt2800_register_read(rt2x00dev
, TX_BAND_CFG
, ®
);
1027 rt2x00_set_field32(®
, TX_BAND_CFG_HT40_MINUS
, conf_is_ht40_minus(conf
));
1028 rt2x00_set_field32(®
, TX_BAND_CFG_A
, rf
->channel
> 14);
1029 rt2x00_set_field32(®
, TX_BAND_CFG_BG
, rf
->channel
<= 14);
1030 rt2800_register_write(rt2x00dev
, TX_BAND_CFG
, reg
);
1034 /* Turn on unused PA or LNA when not using 1T or 1R */
1035 if (rt2x00dev
->default_ant
.tx
!= 1) {
1036 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_A1_EN
, 1);
1037 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_G1_EN
, 1);
1040 /* Turn on unused PA or LNA when not using 1T or 1R */
1041 if (rt2x00dev
->default_ant
.rx
!= 1) {
1042 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_LNA_PE_A1_EN
, 1);
1043 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_LNA_PE_G1_EN
, 1);
1046 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_LNA_PE_A0_EN
, 1);
1047 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_LNA_PE_G0_EN
, 1);
1048 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_RFTR_EN
, 1);
1049 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_TRSW_EN
, 1);
1050 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_G0_EN
, rf
->channel
<= 14);
1051 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_A0_EN
, rf
->channel
> 14);
1053 rt2800_register_write(rt2x00dev
, TX_PIN_CFG
, tx_pin
);
1055 rt2800_bbp_read(rt2x00dev
, 4, &bbp
);
1056 rt2x00_set_field8(&bbp
, BBP4_BANDWIDTH
, 2 * conf_is_ht40(conf
));
1057 rt2800_bbp_write(rt2x00dev
, 4, bbp
);
1059 rt2800_bbp_read(rt2x00dev
, 3, &bbp
);
1060 rt2x00_set_field8(&bbp
, BBP3_HT40_MINUS
, conf_is_ht40_minus(conf
));
1061 rt2800_bbp_write(rt2x00dev
, 3, bbp
);
1063 if (rt2x00_rt_rev(rt2x00dev
, RT2860
, REV_RT2860C
)) {
1064 if (conf_is_ht40(conf
)) {
1065 rt2800_bbp_write(rt2x00dev
, 69, 0x1a);
1066 rt2800_bbp_write(rt2x00dev
, 70, 0x0a);
1067 rt2800_bbp_write(rt2x00dev
, 73, 0x16);
1069 rt2800_bbp_write(rt2x00dev
, 69, 0x16);
1070 rt2800_bbp_write(rt2x00dev
, 70, 0x08);
1071 rt2800_bbp_write(rt2x00dev
, 73, 0x11);
1078 static void rt2800_config_txpower(struct rt2x00_dev
*rt2x00dev
,
1082 u32 value
= TXPOWER_G_TO_DEV(txpower
);
1085 rt2800_bbp_read(rt2x00dev
, 1, &r1
);
1086 rt2x00_set_field8(®
, BBP1_TX_POWER
, 0);
1087 rt2800_bbp_write(rt2x00dev
, 1, r1
);
1089 rt2800_register_read(rt2x00dev
, TX_PWR_CFG_0
, ®
);
1090 rt2x00_set_field32(®
, TX_PWR_CFG_0_1MBS
, value
);
1091 rt2x00_set_field32(®
, TX_PWR_CFG_0_2MBS
, value
);
1092 rt2x00_set_field32(®
, TX_PWR_CFG_0_55MBS
, value
);
1093 rt2x00_set_field32(®
, TX_PWR_CFG_0_11MBS
, value
);
1094 rt2x00_set_field32(®
, TX_PWR_CFG_0_6MBS
, value
);
1095 rt2x00_set_field32(®
, TX_PWR_CFG_0_9MBS
, value
);
1096 rt2x00_set_field32(®
, TX_PWR_CFG_0_12MBS
, value
);
1097 rt2x00_set_field32(®
, TX_PWR_CFG_0_18MBS
, value
);
1098 rt2800_register_write(rt2x00dev
, TX_PWR_CFG_0
, reg
);
1100 rt2800_register_read(rt2x00dev
, TX_PWR_CFG_1
, ®
);
1101 rt2x00_set_field32(®
, TX_PWR_CFG_1_24MBS
, value
);
1102 rt2x00_set_field32(®
, TX_PWR_CFG_1_36MBS
, value
);
1103 rt2x00_set_field32(®
, TX_PWR_CFG_1_48MBS
, value
);
1104 rt2x00_set_field32(®
, TX_PWR_CFG_1_54MBS
, value
);
1105 rt2x00_set_field32(®
, TX_PWR_CFG_1_MCS0
, value
);
1106 rt2x00_set_field32(®
, TX_PWR_CFG_1_MCS1
, value
);
1107 rt2x00_set_field32(®
, TX_PWR_CFG_1_MCS2
, value
);
1108 rt2x00_set_field32(®
, TX_PWR_CFG_1_MCS3
, value
);
1109 rt2800_register_write(rt2x00dev
, TX_PWR_CFG_1
, reg
);
1111 rt2800_register_read(rt2x00dev
, TX_PWR_CFG_2
, ®
);
1112 rt2x00_set_field32(®
, TX_PWR_CFG_2_MCS4
, value
);
1113 rt2x00_set_field32(®
, TX_PWR_CFG_2_MCS5
, value
);
1114 rt2x00_set_field32(®
, TX_PWR_CFG_2_MCS6
, value
);
1115 rt2x00_set_field32(®
, TX_PWR_CFG_2_MCS7
, value
);
1116 rt2x00_set_field32(®
, TX_PWR_CFG_2_MCS8
, value
);
1117 rt2x00_set_field32(®
, TX_PWR_CFG_2_MCS9
, value
);
1118 rt2x00_set_field32(®
, TX_PWR_CFG_2_MCS10
, value
);
1119 rt2x00_set_field32(®
, TX_PWR_CFG_2_MCS11
, value
);
1120 rt2800_register_write(rt2x00dev
, TX_PWR_CFG_2
, reg
);
1122 rt2800_register_read(rt2x00dev
, TX_PWR_CFG_3
, ®
);
1123 rt2x00_set_field32(®
, TX_PWR_CFG_3_MCS12
, value
);
1124 rt2x00_set_field32(®
, TX_PWR_CFG_3_MCS13
, value
);
1125 rt2x00_set_field32(®
, TX_PWR_CFG_3_MCS14
, value
);
1126 rt2x00_set_field32(®
, TX_PWR_CFG_3_MCS15
, value
);
1127 rt2x00_set_field32(®
, TX_PWR_CFG_3_UKNOWN1
, value
);
1128 rt2x00_set_field32(®
, TX_PWR_CFG_3_UKNOWN2
, value
);
1129 rt2x00_set_field32(®
, TX_PWR_CFG_3_UKNOWN3
, value
);
1130 rt2x00_set_field32(®
, TX_PWR_CFG_3_UKNOWN4
, value
);
1131 rt2800_register_write(rt2x00dev
, TX_PWR_CFG_3
, reg
);
1133 rt2800_register_read(rt2x00dev
, TX_PWR_CFG_4
, ®
);
1134 rt2x00_set_field32(®
, TX_PWR_CFG_4_UKNOWN5
, value
);
1135 rt2x00_set_field32(®
, TX_PWR_CFG_4_UKNOWN6
, value
);
1136 rt2x00_set_field32(®
, TX_PWR_CFG_4_UKNOWN7
, value
);
1137 rt2x00_set_field32(®
, TX_PWR_CFG_4_UKNOWN8
, value
);
1138 rt2800_register_write(rt2x00dev
, TX_PWR_CFG_4
, reg
);
1141 static void rt2800_config_retry_limit(struct rt2x00_dev
*rt2x00dev
,
1142 struct rt2x00lib_conf
*libconf
)
1146 rt2800_register_read(rt2x00dev
, TX_RTY_CFG
, ®
);
1147 rt2x00_set_field32(®
, TX_RTY_CFG_SHORT_RTY_LIMIT
,
1148 libconf
->conf
->short_frame_max_tx_count
);
1149 rt2x00_set_field32(®
, TX_RTY_CFG_LONG_RTY_LIMIT
,
1150 libconf
->conf
->long_frame_max_tx_count
);
1151 rt2800_register_write(rt2x00dev
, TX_RTY_CFG
, reg
);
1154 static void rt2800_config_ps(struct rt2x00_dev
*rt2x00dev
,
1155 struct rt2x00lib_conf
*libconf
)
1157 enum dev_state state
=
1158 (libconf
->conf
->flags
& IEEE80211_CONF_PS
) ?
1159 STATE_SLEEP
: STATE_AWAKE
;
1162 if (state
== STATE_SLEEP
) {
1163 rt2800_register_write(rt2x00dev
, AUTOWAKEUP_CFG
, 0);
1165 rt2800_register_read(rt2x00dev
, AUTOWAKEUP_CFG
, ®
);
1166 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_AUTO_LEAD_TIME
, 5);
1167 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE
,
1168 libconf
->conf
->listen_interval
- 1);
1169 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_AUTOWAKE
, 1);
1170 rt2800_register_write(rt2x00dev
, AUTOWAKEUP_CFG
, reg
);
1172 rt2x00dev
->ops
->lib
->set_device_state(rt2x00dev
, state
);
1174 rt2800_register_read(rt2x00dev
, AUTOWAKEUP_CFG
, ®
);
1175 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_AUTO_LEAD_TIME
, 0);
1176 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE
, 0);
1177 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_AUTOWAKE
, 0);
1178 rt2800_register_write(rt2x00dev
, AUTOWAKEUP_CFG
, reg
);
1180 rt2x00dev
->ops
->lib
->set_device_state(rt2x00dev
, state
);
1184 void rt2800_config(struct rt2x00_dev
*rt2x00dev
,
1185 struct rt2x00lib_conf
*libconf
,
1186 const unsigned int flags
)
1188 /* Always recalculate LNA gain before changing configuration */
1189 rt2800_config_lna_gain(rt2x00dev
, libconf
);
1191 if (flags
& IEEE80211_CONF_CHANGE_CHANNEL
)
1192 rt2800_config_channel(rt2x00dev
, libconf
->conf
,
1193 &libconf
->rf
, &libconf
->channel
);
1194 if (flags
& IEEE80211_CONF_CHANGE_POWER
)
1195 rt2800_config_txpower(rt2x00dev
, libconf
->conf
->power_level
);
1196 if (flags
& IEEE80211_CONF_CHANGE_RETRY_LIMITS
)
1197 rt2800_config_retry_limit(rt2x00dev
, libconf
);
1198 if (flags
& IEEE80211_CONF_CHANGE_PS
)
1199 rt2800_config_ps(rt2x00dev
, libconf
);
1201 EXPORT_SYMBOL_GPL(rt2800_config
);
1206 void rt2800_link_stats(struct rt2x00_dev
*rt2x00dev
, struct link_qual
*qual
)
1211 * Update FCS error count from register.
1213 rt2800_register_read(rt2x00dev
, RX_STA_CNT0
, ®
);
1214 qual
->rx_failed
= rt2x00_get_field32(reg
, RX_STA_CNT0_CRC_ERR
);
1216 EXPORT_SYMBOL_GPL(rt2800_link_stats
);
1218 static u8
rt2800_get_default_vgc(struct rt2x00_dev
*rt2x00dev
)
1220 if (rt2x00dev
->curr_band
== IEEE80211_BAND_2GHZ
) {
1221 if (rt2x00_rt(rt2x00dev
, RT3070
) ||
1222 rt2x00_rt(rt2x00dev
, RT3071
) ||
1223 rt2x00_rt(rt2x00dev
, RT3090
) ||
1224 rt2x00_rt(rt2x00dev
, RT3390
))
1225 return 0x1c + (2 * rt2x00dev
->lna_gain
);
1227 return 0x2e + rt2x00dev
->lna_gain
;
1230 if (!test_bit(CONFIG_CHANNEL_HT40
, &rt2x00dev
->flags
))
1231 return 0x32 + (rt2x00dev
->lna_gain
* 5) / 3;
1233 return 0x3a + (rt2x00dev
->lna_gain
* 5) / 3;
1236 static inline void rt2800_set_vgc(struct rt2x00_dev
*rt2x00dev
,
1237 struct link_qual
*qual
, u8 vgc_level
)
1239 if (qual
->vgc_level
!= vgc_level
) {
1240 rt2800_bbp_write(rt2x00dev
, 66, vgc_level
);
1241 qual
->vgc_level
= vgc_level
;
1242 qual
->vgc_level_reg
= vgc_level
;
1246 void rt2800_reset_tuner(struct rt2x00_dev
*rt2x00dev
, struct link_qual
*qual
)
1248 rt2800_set_vgc(rt2x00dev
, qual
, rt2800_get_default_vgc(rt2x00dev
));
1250 EXPORT_SYMBOL_GPL(rt2800_reset_tuner
);
1252 void rt2800_link_tuner(struct rt2x00_dev
*rt2x00dev
, struct link_qual
*qual
,
1255 if (rt2x00_rt_rev(rt2x00dev
, RT2860
, REV_RT2860C
))
1259 * When RSSI is better then -80 increase VGC level with 0x10
1261 rt2800_set_vgc(rt2x00dev
, qual
,
1262 rt2800_get_default_vgc(rt2x00dev
) +
1263 ((qual
->rssi
> -80) * 0x10));
1265 EXPORT_SYMBOL_GPL(rt2800_link_tuner
);
1268 * Initialization functions.
1270 int rt2800_init_registers(struct rt2x00_dev
*rt2x00dev
)
1276 rt2800_register_read(rt2x00dev
, WPDMA_GLO_CFG
, ®
);
1277 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_TX_DMA
, 0);
1278 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_DMA_BUSY
, 0);
1279 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_RX_DMA
, 0);
1280 rt2x00_set_field32(®
, WPDMA_GLO_CFG_RX_DMA_BUSY
, 0);
1281 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_WRITEBACK_DONE
, 1);
1282 rt2800_register_write(rt2x00dev
, WPDMA_GLO_CFG
, reg
);
1284 if (rt2x00_is_usb(rt2x00dev
)) {
1286 * Wait until BBP and RF are ready.
1288 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
1289 rt2800_register_read(rt2x00dev
, MAC_CSR0
, ®
);
1290 if (reg
&& reg
!= ~0)
1295 if (i
== REGISTER_BUSY_COUNT
) {
1296 ERROR(rt2x00dev
, "Unstable hardware.\n");
1300 rt2800_register_read(rt2x00dev
, PBF_SYS_CTRL
, ®
);
1301 rt2800_register_write(rt2x00dev
, PBF_SYS_CTRL
,
1303 } else if (rt2x00_is_pci(rt2x00dev
) || rt2x00_is_soc(rt2x00dev
)) {
1307 rt2800_register_read(rt2x00dev
, WPDMA_RST_IDX
, ®
);
1308 rt2x00_set_field32(®
, WPDMA_RST_IDX_DTX_IDX0
, 1);
1309 rt2x00_set_field32(®
, WPDMA_RST_IDX_DTX_IDX1
, 1);
1310 rt2x00_set_field32(®
, WPDMA_RST_IDX_DTX_IDX2
, 1);
1311 rt2x00_set_field32(®
, WPDMA_RST_IDX_DTX_IDX3
, 1);
1312 rt2x00_set_field32(®
, WPDMA_RST_IDX_DTX_IDX4
, 1);
1313 rt2x00_set_field32(®
, WPDMA_RST_IDX_DTX_IDX5
, 1);
1314 rt2x00_set_field32(®
, WPDMA_RST_IDX_DRX_IDX0
, 1);
1315 rt2800_register_write(rt2x00dev
, WPDMA_RST_IDX
, reg
);
1317 rt2800_register_write(rt2x00dev
, PBF_SYS_CTRL
, 0x00000e1f);
1318 rt2800_register_write(rt2x00dev
, PBF_SYS_CTRL
, 0x00000e00);
1320 rt2800_register_write(rt2x00dev
, PWR_PIN_CFG
, 0x00000003);
1323 rt2800_register_read(rt2x00dev
, MAC_SYS_CTRL
, ®
);
1324 rt2x00_set_field32(®
, MAC_SYS_CTRL_RESET_CSR
, 1);
1325 rt2x00_set_field32(®
, MAC_SYS_CTRL_RESET_BBP
, 1);
1326 rt2800_register_write(rt2x00dev
, MAC_SYS_CTRL
, reg
);
1328 if (rt2x00_is_usb(rt2x00dev
)) {
1329 rt2800_register_write(rt2x00dev
, USB_DMA_CFG
, 0x00000000);
1330 #if defined(CONFIG_RT2X00_LIB_USB) || defined(CONFIG_RT2X00_LIB_USB_MODULE)
1331 rt2x00usb_vendor_request_sw(rt2x00dev
, USB_DEVICE_MODE
, 0,
1332 USB_MODE_RESET
, REGISTER_TIMEOUT
);
1336 rt2800_register_write(rt2x00dev
, MAC_SYS_CTRL
, 0x00000000);
1338 rt2800_register_read(rt2x00dev
, BCN_OFFSET0
, ®
);
1339 rt2x00_set_field32(®
, BCN_OFFSET0_BCN0
, 0xe0); /* 0x3800 */
1340 rt2x00_set_field32(®
, BCN_OFFSET0_BCN1
, 0xe8); /* 0x3a00 */
1341 rt2x00_set_field32(®
, BCN_OFFSET0_BCN2
, 0xf0); /* 0x3c00 */
1342 rt2x00_set_field32(®
, BCN_OFFSET0_BCN3
, 0xf8); /* 0x3e00 */
1343 rt2800_register_write(rt2x00dev
, BCN_OFFSET0
, reg
);
1345 rt2800_register_read(rt2x00dev
, BCN_OFFSET1
, ®
);
1346 rt2x00_set_field32(®
, BCN_OFFSET1_BCN4
, 0xc8); /* 0x3200 */
1347 rt2x00_set_field32(®
, BCN_OFFSET1_BCN5
, 0xd0); /* 0x3400 */
1348 rt2x00_set_field32(®
, BCN_OFFSET1_BCN6
, 0x77); /* 0x1dc0 */
1349 rt2x00_set_field32(®
, BCN_OFFSET1_BCN7
, 0x6f); /* 0x1bc0 */
1350 rt2800_register_write(rt2x00dev
, BCN_OFFSET1
, reg
);
1352 rt2800_register_write(rt2x00dev
, LEGACY_BASIC_RATE
, 0x0000013f);
1353 rt2800_register_write(rt2x00dev
, HT_BASIC_RATE
, 0x00008003);
1355 rt2800_register_write(rt2x00dev
, MAC_SYS_CTRL
, 0x00000000);
1357 rt2800_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
1358 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_INTERVAL
, 0);
1359 rt2x00_set_field32(®
, BCN_TIME_CFG_TSF_TICKING
, 0);
1360 rt2x00_set_field32(®
, BCN_TIME_CFG_TSF_SYNC
, 0);
1361 rt2x00_set_field32(®
, BCN_TIME_CFG_TBTT_ENABLE
, 0);
1362 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_GEN
, 0);
1363 rt2x00_set_field32(®
, BCN_TIME_CFG_TX_TIME_COMPENSATE
, 0);
1364 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
1366 rt2800_config_filter(rt2x00dev
, FIF_ALLMULTI
);
1368 rt2800_register_read(rt2x00dev
, BKOFF_SLOT_CFG
, ®
);
1369 rt2x00_set_field32(®
, BKOFF_SLOT_CFG_SLOT_TIME
, 9);
1370 rt2x00_set_field32(®
, BKOFF_SLOT_CFG_CC_DELAY_TIME
, 2);
1371 rt2800_register_write(rt2x00dev
, BKOFF_SLOT_CFG
, reg
);
1373 if (rt2x00_rt(rt2x00dev
, RT3071
) ||
1374 rt2x00_rt(rt2x00dev
, RT3090
) ||
1375 rt2x00_rt(rt2x00dev
, RT3390
)) {
1376 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000400);
1377 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00000000);
1378 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3071
, REV_RT3071E
) ||
1379 rt2x00_rt_rev_lt(rt2x00dev
, RT3090
, REV_RT3090E
) ||
1380 rt2x00_rt_rev_lt(rt2x00dev
, RT3390
, REV_RT3390E
)) {
1381 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC
, &eeprom
);
1382 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_DAC_TEST
))
1383 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
,
1386 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
,
1389 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
, 0x00000000);
1391 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
, reg
);
1392 } else if (rt2x00_rt(rt2x00dev
, RT3070
)) {
1393 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000400);
1395 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070F
)) {
1396 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00000000);
1397 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
, 0x0000002c);
1399 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00080606);
1400 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
, 0x00000000);
1403 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000000);
1404 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00080606);
1407 rt2800_register_read(rt2x00dev
, TX_LINK_CFG
, ®
);
1408 rt2x00_set_field32(®
, TX_LINK_CFG_REMOTE_MFB_LIFETIME
, 32);
1409 rt2x00_set_field32(®
, TX_LINK_CFG_MFB_ENABLE
, 0);
1410 rt2x00_set_field32(®
, TX_LINK_CFG_REMOTE_UMFS_ENABLE
, 0);
1411 rt2x00_set_field32(®
, TX_LINK_CFG_TX_MRQ_EN
, 0);
1412 rt2x00_set_field32(®
, TX_LINK_CFG_TX_RDG_EN
, 0);
1413 rt2x00_set_field32(®
, TX_LINK_CFG_TX_CF_ACK_EN
, 1);
1414 rt2x00_set_field32(®
, TX_LINK_CFG_REMOTE_MFB
, 0);
1415 rt2x00_set_field32(®
, TX_LINK_CFG_REMOTE_MFS
, 0);
1416 rt2800_register_write(rt2x00dev
, TX_LINK_CFG
, reg
);
1418 rt2800_register_read(rt2x00dev
, TX_TIMEOUT_CFG
, ®
);
1419 rt2x00_set_field32(®
, TX_TIMEOUT_CFG_MPDU_LIFETIME
, 9);
1420 rt2x00_set_field32(®
, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT
, 32);
1421 rt2x00_set_field32(®
, TX_TIMEOUT_CFG_TX_OP_TIMEOUT
, 10);
1422 rt2800_register_write(rt2x00dev
, TX_TIMEOUT_CFG
, reg
);
1424 rt2800_register_read(rt2x00dev
, MAX_LEN_CFG
, ®
);
1425 rt2x00_set_field32(®
, MAX_LEN_CFG_MAX_MPDU
, AGGREGATION_SIZE
);
1426 if (rt2x00_rt_rev_gte(rt2x00dev
, RT2872
, REV_RT2872E
) ||
1427 rt2x00_rt(rt2x00dev
, RT2883
) ||
1428 rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070E
))
1429 rt2x00_set_field32(®
, MAX_LEN_CFG_MAX_PSDU
, 2);
1431 rt2x00_set_field32(®
, MAX_LEN_CFG_MAX_PSDU
, 1);
1432 rt2x00_set_field32(®
, MAX_LEN_CFG_MIN_PSDU
, 0);
1433 rt2x00_set_field32(®
, MAX_LEN_CFG_MIN_MPDU
, 0);
1434 rt2800_register_write(rt2x00dev
, MAX_LEN_CFG
, reg
);
1436 rt2800_register_read(rt2x00dev
, LED_CFG
, ®
);
1437 rt2x00_set_field32(®
, LED_CFG_ON_PERIOD
, 70);
1438 rt2x00_set_field32(®
, LED_CFG_OFF_PERIOD
, 30);
1439 rt2x00_set_field32(®
, LED_CFG_SLOW_BLINK_PERIOD
, 3);
1440 rt2x00_set_field32(®
, LED_CFG_R_LED_MODE
, 3);
1441 rt2x00_set_field32(®
, LED_CFG_G_LED_MODE
, 3);
1442 rt2x00_set_field32(®
, LED_CFG_Y_LED_MODE
, 3);
1443 rt2x00_set_field32(®
, LED_CFG_LED_POLAR
, 1);
1444 rt2800_register_write(rt2x00dev
, LED_CFG
, reg
);
1446 rt2800_register_write(rt2x00dev
, PBF_MAX_PCNT
, 0x1f3fbf9f);
1448 rt2800_register_read(rt2x00dev
, TX_RTY_CFG
, ®
);
1449 rt2x00_set_field32(®
, TX_RTY_CFG_SHORT_RTY_LIMIT
, 15);
1450 rt2x00_set_field32(®
, TX_RTY_CFG_LONG_RTY_LIMIT
, 31);
1451 rt2x00_set_field32(®
, TX_RTY_CFG_LONG_RTY_THRE
, 2000);
1452 rt2x00_set_field32(®
, TX_RTY_CFG_NON_AGG_RTY_MODE
, 0);
1453 rt2x00_set_field32(®
, TX_RTY_CFG_AGG_RTY_MODE
, 0);
1454 rt2x00_set_field32(®
, TX_RTY_CFG_TX_AUTO_FB_ENABLE
, 1);
1455 rt2800_register_write(rt2x00dev
, TX_RTY_CFG
, reg
);
1457 rt2800_register_read(rt2x00dev
, AUTO_RSP_CFG
, ®
);
1458 rt2x00_set_field32(®
, AUTO_RSP_CFG_AUTORESPONDER
, 1);
1459 rt2x00_set_field32(®
, AUTO_RSP_CFG_BAC_ACK_POLICY
, 1);
1460 rt2x00_set_field32(®
, AUTO_RSP_CFG_CTS_40_MMODE
, 0);
1461 rt2x00_set_field32(®
, AUTO_RSP_CFG_CTS_40_MREF
, 0);
1462 rt2x00_set_field32(®
, AUTO_RSP_CFG_AR_PREAMBLE
, 1);
1463 rt2x00_set_field32(®
, AUTO_RSP_CFG_DUAL_CTS_EN
, 0);
1464 rt2x00_set_field32(®
, AUTO_RSP_CFG_ACK_CTS_PSM_BIT
, 0);
1465 rt2800_register_write(rt2x00dev
, AUTO_RSP_CFG
, reg
);
1467 rt2800_register_read(rt2x00dev
, CCK_PROT_CFG
, ®
);
1468 rt2x00_set_field32(®
, CCK_PROT_CFG_PROTECT_RATE
, 3);
1469 rt2x00_set_field32(®
, CCK_PROT_CFG_PROTECT_CTRL
, 0);
1470 rt2x00_set_field32(®
, CCK_PROT_CFG_PROTECT_NAV
, 1);
1471 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
1472 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
1473 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
1474 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_MM40
, 0);
1475 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
1476 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_GF40
, 0);
1477 rt2x00_set_field32(®
, CCK_PROT_CFG_RTS_TH_EN
, 1);
1478 rt2800_register_write(rt2x00dev
, CCK_PROT_CFG
, reg
);
1480 rt2800_register_read(rt2x00dev
, OFDM_PROT_CFG
, ®
);
1481 rt2x00_set_field32(®
, OFDM_PROT_CFG_PROTECT_RATE
, 3);
1482 rt2x00_set_field32(®
, OFDM_PROT_CFG_PROTECT_CTRL
, 0);
1483 rt2x00_set_field32(®
, OFDM_PROT_CFG_PROTECT_NAV
, 1);
1484 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
1485 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
1486 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
1487 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_MM40
, 0);
1488 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
1489 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_GF40
, 0);
1490 rt2x00_set_field32(®
, OFDM_PROT_CFG_RTS_TH_EN
, 1);
1491 rt2800_register_write(rt2x00dev
, OFDM_PROT_CFG
, reg
);
1493 rt2800_register_read(rt2x00dev
, MM20_PROT_CFG
, ®
);
1494 rt2x00_set_field32(®
, MM20_PROT_CFG_PROTECT_RATE
, 0x4004);
1495 rt2x00_set_field32(®
, MM20_PROT_CFG_PROTECT_CTRL
, 0);
1496 rt2x00_set_field32(®
, MM20_PROT_CFG_PROTECT_NAV
, 1);
1497 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
1498 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
1499 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
1500 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_MM40
, 0);
1501 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
1502 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_GF40
, 0);
1503 rt2x00_set_field32(®
, MM20_PROT_CFG_RTS_TH_EN
, 0);
1504 rt2800_register_write(rt2x00dev
, MM20_PROT_CFG
, reg
);
1506 rt2800_register_read(rt2x00dev
, MM40_PROT_CFG
, ®
);
1507 rt2x00_set_field32(®
, MM40_PROT_CFG_PROTECT_RATE
, 0x4084);
1508 rt2x00_set_field32(®
, MM40_PROT_CFG_PROTECT_CTRL
,
1509 !rt2x00_is_usb(rt2x00dev
));
1510 rt2x00_set_field32(®
, MM40_PROT_CFG_PROTECT_NAV
, 1);
1511 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
1512 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
1513 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
1514 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_MM40
, 1);
1515 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
1516 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_GF40
, 1);
1517 rt2x00_set_field32(®
, MM40_PROT_CFG_RTS_TH_EN
, 0);
1518 rt2800_register_write(rt2x00dev
, MM40_PROT_CFG
, reg
);
1520 rt2800_register_read(rt2x00dev
, GF20_PROT_CFG
, ®
);
1521 rt2x00_set_field32(®
, GF20_PROT_CFG_PROTECT_RATE
, 0x4004);
1522 rt2x00_set_field32(®
, GF20_PROT_CFG_PROTECT_CTRL
, 0);
1523 rt2x00_set_field32(®
, GF20_PROT_CFG_PROTECT_NAV
, 1);
1524 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
1525 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
1526 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
1527 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_MM40
, 0);
1528 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
1529 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_GF40
, 0);
1530 rt2x00_set_field32(®
, GF20_PROT_CFG_RTS_TH_EN
, 0);
1531 rt2800_register_write(rt2x00dev
, GF20_PROT_CFG
, reg
);
1533 rt2800_register_read(rt2x00dev
, GF40_PROT_CFG
, ®
);
1534 rt2x00_set_field32(®
, GF40_PROT_CFG_PROTECT_RATE
, 0x4084);
1535 rt2x00_set_field32(®
, GF40_PROT_CFG_PROTECT_CTRL
, 0);
1536 rt2x00_set_field32(®
, GF40_PROT_CFG_PROTECT_NAV
, 1);
1537 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
1538 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
1539 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
1540 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_MM40
, 1);
1541 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
1542 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_GF40
, 1);
1543 rt2x00_set_field32(®
, GF40_PROT_CFG_RTS_TH_EN
, 0);
1544 rt2800_register_write(rt2x00dev
, GF40_PROT_CFG
, reg
);
1546 if (rt2x00_is_usb(rt2x00dev
)) {
1547 rt2800_register_write(rt2x00dev
, PBF_CFG
, 0xf40006);
1549 rt2800_register_read(rt2x00dev
, WPDMA_GLO_CFG
, ®
);
1550 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_TX_DMA
, 0);
1551 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_DMA_BUSY
, 0);
1552 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_RX_DMA
, 0);
1553 rt2x00_set_field32(®
, WPDMA_GLO_CFG_RX_DMA_BUSY
, 0);
1554 rt2x00_set_field32(®
, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE
, 3);
1555 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_WRITEBACK_DONE
, 0);
1556 rt2x00_set_field32(®
, WPDMA_GLO_CFG_BIG_ENDIAN
, 0);
1557 rt2x00_set_field32(®
, WPDMA_GLO_CFG_RX_HDR_SCATTER
, 0);
1558 rt2x00_set_field32(®
, WPDMA_GLO_CFG_HDR_SEG_LEN
, 0);
1559 rt2800_register_write(rt2x00dev
, WPDMA_GLO_CFG
, reg
);
1562 rt2800_register_write(rt2x00dev
, TXOP_CTRL_CFG
, 0x0000583f);
1563 rt2800_register_write(rt2x00dev
, TXOP_HLDR_ET
, 0x00000002);
1565 rt2800_register_read(rt2x00dev
, TX_RTS_CFG
, ®
);
1566 rt2x00_set_field32(®
, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT
, 32);
1567 rt2x00_set_field32(®
, TX_RTS_CFG_RTS_THRES
,
1568 IEEE80211_MAX_RTS_THRESHOLD
);
1569 rt2x00_set_field32(®
, TX_RTS_CFG_RTS_FBK_EN
, 0);
1570 rt2800_register_write(rt2x00dev
, TX_RTS_CFG
, reg
);
1572 rt2800_register_write(rt2x00dev
, EXP_ACK_TIME
, 0x002400ca);
1575 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
1576 * time should be set to 16. However, the original Ralink driver uses
1577 * 16 for both and indeed using a value of 10 for CCK SIFS results in
1578 * connection problems with 11g + CTS protection. Hence, use the same
1579 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
1581 rt2800_register_read(rt2x00dev
, XIFS_TIME_CFG
, ®
);
1582 rt2x00_set_field32(®
, XIFS_TIME_CFG_CCKM_SIFS_TIME
, 16);
1583 rt2x00_set_field32(®
, XIFS_TIME_CFG_OFDM_SIFS_TIME
, 16);
1584 rt2x00_set_field32(®
, XIFS_TIME_CFG_OFDM_XIFS_TIME
, 4);
1585 rt2x00_set_field32(®
, XIFS_TIME_CFG_EIFS
, 314);
1586 rt2x00_set_field32(®
, XIFS_TIME_CFG_BB_RXEND_ENABLE
, 1);
1587 rt2800_register_write(rt2x00dev
, XIFS_TIME_CFG
, reg
);
1589 rt2800_register_write(rt2x00dev
, PWR_PIN_CFG
, 0x00000003);
1592 * ASIC will keep garbage value after boot, clear encryption keys.
1594 for (i
= 0; i
< 4; i
++)
1595 rt2800_register_write(rt2x00dev
,
1596 SHARED_KEY_MODE_ENTRY(i
), 0);
1598 for (i
= 0; i
< 256; i
++) {
1599 u32 wcid
[2] = { 0xffffffff, 0x00ffffff };
1600 rt2800_register_multiwrite(rt2x00dev
, MAC_WCID_ENTRY(i
),
1601 wcid
, sizeof(wcid
));
1603 rt2800_register_write(rt2x00dev
, MAC_WCID_ATTR_ENTRY(i
), 1);
1604 rt2800_register_write(rt2x00dev
, MAC_IVEIV_ENTRY(i
), 0);
1609 * For the Beacon base registers we only need to clear
1610 * the first byte since that byte contains the VALID and OWNER
1611 * bits which (when set to 0) will invalidate the entire beacon.
1613 rt2800_register_write(rt2x00dev
, HW_BEACON_BASE0
, 0);
1614 rt2800_register_write(rt2x00dev
, HW_BEACON_BASE1
, 0);
1615 rt2800_register_write(rt2x00dev
, HW_BEACON_BASE2
, 0);
1616 rt2800_register_write(rt2x00dev
, HW_BEACON_BASE3
, 0);
1617 rt2800_register_write(rt2x00dev
, HW_BEACON_BASE4
, 0);
1618 rt2800_register_write(rt2x00dev
, HW_BEACON_BASE5
, 0);
1619 rt2800_register_write(rt2x00dev
, HW_BEACON_BASE6
, 0);
1620 rt2800_register_write(rt2x00dev
, HW_BEACON_BASE7
, 0);
1622 if (rt2x00_is_usb(rt2x00dev
)) {
1623 rt2800_register_read(rt2x00dev
, USB_CYC_CFG
, ®
);
1624 rt2x00_set_field32(®
, USB_CYC_CFG_CLOCK_CYCLE
, 30);
1625 rt2800_register_write(rt2x00dev
, USB_CYC_CFG
, reg
);
1628 rt2800_register_read(rt2x00dev
, HT_FBK_CFG0
, ®
);
1629 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS0FBK
, 0);
1630 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS1FBK
, 0);
1631 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS2FBK
, 1);
1632 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS3FBK
, 2);
1633 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS4FBK
, 3);
1634 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS5FBK
, 4);
1635 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS6FBK
, 5);
1636 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS7FBK
, 6);
1637 rt2800_register_write(rt2x00dev
, HT_FBK_CFG0
, reg
);
1639 rt2800_register_read(rt2x00dev
, HT_FBK_CFG1
, ®
);
1640 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS8FBK
, 8);
1641 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS9FBK
, 8);
1642 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS10FBK
, 9);
1643 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS11FBK
, 10);
1644 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS12FBK
, 11);
1645 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS13FBK
, 12);
1646 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS14FBK
, 13);
1647 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS15FBK
, 14);
1648 rt2800_register_write(rt2x00dev
, HT_FBK_CFG1
, reg
);
1650 rt2800_register_read(rt2x00dev
, LG_FBK_CFG0
, ®
);
1651 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS0FBK
, 8);
1652 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS1FBK
, 8);
1653 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS2FBK
, 9);
1654 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS3FBK
, 10);
1655 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS4FBK
, 11);
1656 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS5FBK
, 12);
1657 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS6FBK
, 13);
1658 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS7FBK
, 14);
1659 rt2800_register_write(rt2x00dev
, LG_FBK_CFG0
, reg
);
1661 rt2800_register_read(rt2x00dev
, LG_FBK_CFG1
, ®
);
1662 rt2x00_set_field32(®
, LG_FBK_CFG0_CCKMCS0FBK
, 0);
1663 rt2x00_set_field32(®
, LG_FBK_CFG0_CCKMCS1FBK
, 0);
1664 rt2x00_set_field32(®
, LG_FBK_CFG0_CCKMCS2FBK
, 1);
1665 rt2x00_set_field32(®
, LG_FBK_CFG0_CCKMCS3FBK
, 2);
1666 rt2800_register_write(rt2x00dev
, LG_FBK_CFG1
, reg
);
1669 * We must clear the error counters.
1670 * These registers are cleared on read,
1671 * so we may pass a useless variable to store the value.
1673 rt2800_register_read(rt2x00dev
, RX_STA_CNT0
, ®
);
1674 rt2800_register_read(rt2x00dev
, RX_STA_CNT1
, ®
);
1675 rt2800_register_read(rt2x00dev
, RX_STA_CNT2
, ®
);
1676 rt2800_register_read(rt2x00dev
, TX_STA_CNT0
, ®
);
1677 rt2800_register_read(rt2x00dev
, TX_STA_CNT1
, ®
);
1678 rt2800_register_read(rt2x00dev
, TX_STA_CNT2
, ®
);
1682 EXPORT_SYMBOL_GPL(rt2800_init_registers
);
1684 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev
*rt2x00dev
)
1689 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
1690 rt2800_register_read(rt2x00dev
, MAC_STATUS_CFG
, ®
);
1691 if (!rt2x00_get_field32(reg
, MAC_STATUS_CFG_BBP_RF_BUSY
))
1694 udelay(REGISTER_BUSY_DELAY
);
1697 ERROR(rt2x00dev
, "BBP/RF register access failed, aborting.\n");
1701 static int rt2800_wait_bbp_ready(struct rt2x00_dev
*rt2x00dev
)
1707 * BBP was enabled after firmware was loaded,
1708 * but we need to reactivate it now.
1710 rt2800_register_write(rt2x00dev
, H2M_BBP_AGENT
, 0);
1711 rt2800_register_write(rt2x00dev
, H2M_MAILBOX_CSR
, 0);
1714 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
1715 rt2800_bbp_read(rt2x00dev
, 0, &value
);
1716 if ((value
!= 0xff) && (value
!= 0x00))
1718 udelay(REGISTER_BUSY_DELAY
);
1721 ERROR(rt2x00dev
, "BBP register access failed, aborting.\n");
1725 int rt2800_init_bbp(struct rt2x00_dev
*rt2x00dev
)
1732 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev
) ||
1733 rt2800_wait_bbp_ready(rt2x00dev
)))
1736 if (rt2800_is_305x_soc(rt2x00dev
))
1737 rt2800_bbp_write(rt2x00dev
, 31, 0x08);
1739 rt2800_bbp_write(rt2x00dev
, 65, 0x2c);
1740 rt2800_bbp_write(rt2x00dev
, 66, 0x38);
1742 if (rt2x00_rt_rev(rt2x00dev
, RT2860
, REV_RT2860C
)) {
1743 rt2800_bbp_write(rt2x00dev
, 69, 0x16);
1744 rt2800_bbp_write(rt2x00dev
, 73, 0x12);
1746 rt2800_bbp_write(rt2x00dev
, 69, 0x12);
1747 rt2800_bbp_write(rt2x00dev
, 73, 0x10);
1750 rt2800_bbp_write(rt2x00dev
, 70, 0x0a);
1752 if (rt2x00_rt(rt2x00dev
, RT3070
) ||
1753 rt2x00_rt(rt2x00dev
, RT3071
) ||
1754 rt2x00_rt(rt2x00dev
, RT3090
) ||
1755 rt2x00_rt(rt2x00dev
, RT3390
)) {
1756 rt2800_bbp_write(rt2x00dev
, 79, 0x13);
1757 rt2800_bbp_write(rt2x00dev
, 80, 0x05);
1758 rt2800_bbp_write(rt2x00dev
, 81, 0x33);
1759 } else if (rt2800_is_305x_soc(rt2x00dev
)) {
1760 rt2800_bbp_write(rt2x00dev
, 78, 0x0e);
1761 rt2800_bbp_write(rt2x00dev
, 80, 0x08);
1763 rt2800_bbp_write(rt2x00dev
, 81, 0x37);
1766 rt2800_bbp_write(rt2x00dev
, 82, 0x62);
1767 rt2800_bbp_write(rt2x00dev
, 83, 0x6a);
1769 if (rt2x00_rt_rev(rt2x00dev
, RT2860
, REV_RT2860D
))
1770 rt2800_bbp_write(rt2x00dev
, 84, 0x19);
1772 rt2800_bbp_write(rt2x00dev
, 84, 0x99);
1774 rt2800_bbp_write(rt2x00dev
, 86, 0x00);
1775 rt2800_bbp_write(rt2x00dev
, 91, 0x04);
1776 rt2800_bbp_write(rt2x00dev
, 92, 0x00);
1778 if (rt2x00_rt_rev_gte(rt2x00dev
, RT3070
, REV_RT3070F
) ||
1779 rt2x00_rt_rev_gte(rt2x00dev
, RT3071
, REV_RT3071E
) ||
1780 rt2x00_rt_rev_gte(rt2x00dev
, RT3090
, REV_RT3090E
) ||
1781 rt2x00_rt_rev_gte(rt2x00dev
, RT3390
, REV_RT3390E
) ||
1782 rt2800_is_305x_soc(rt2x00dev
))
1783 rt2800_bbp_write(rt2x00dev
, 103, 0xc0);
1785 rt2800_bbp_write(rt2x00dev
, 103, 0x00);
1787 if (rt2800_is_305x_soc(rt2x00dev
))
1788 rt2800_bbp_write(rt2x00dev
, 105, 0x01);
1790 rt2800_bbp_write(rt2x00dev
, 105, 0x05);
1791 rt2800_bbp_write(rt2x00dev
, 106, 0x35);
1793 if (rt2x00_rt(rt2x00dev
, RT3071
) ||
1794 rt2x00_rt(rt2x00dev
, RT3090
) ||
1795 rt2x00_rt(rt2x00dev
, RT3390
)) {
1796 rt2800_bbp_read(rt2x00dev
, 138, &value
);
1798 rt2x00_eeprom_read(rt2x00dev
, EEPROM_ANTENNA
, &eeprom
);
1799 if (rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_TXPATH
) == 1)
1801 if (rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_RXPATH
) == 1)
1804 rt2800_bbp_write(rt2x00dev
, 138, value
);
1808 for (i
= 0; i
< EEPROM_BBP_SIZE
; i
++) {
1809 rt2x00_eeprom_read(rt2x00dev
, EEPROM_BBP_START
+ i
, &eeprom
);
1811 if (eeprom
!= 0xffff && eeprom
!= 0x0000) {
1812 reg_id
= rt2x00_get_field16(eeprom
, EEPROM_BBP_REG_ID
);
1813 value
= rt2x00_get_field16(eeprom
, EEPROM_BBP_VALUE
);
1814 rt2800_bbp_write(rt2x00dev
, reg_id
, value
);
1820 EXPORT_SYMBOL_GPL(rt2800_init_bbp
);
1822 static u8
rt2800_init_rx_filter(struct rt2x00_dev
*rt2x00dev
,
1823 bool bw40
, u8 rfcsr24
, u8 filter_target
)
1832 rt2800_rfcsr_write(rt2x00dev
, 24, rfcsr24
);
1834 rt2800_bbp_read(rt2x00dev
, 4, &bbp
);
1835 rt2x00_set_field8(&bbp
, BBP4_BANDWIDTH
, 2 * bw40
);
1836 rt2800_bbp_write(rt2x00dev
, 4, bbp
);
1838 rt2800_rfcsr_read(rt2x00dev
, 22, &rfcsr
);
1839 rt2x00_set_field8(&rfcsr
, RFCSR22_BASEBAND_LOOPBACK
, 1);
1840 rt2800_rfcsr_write(rt2x00dev
, 22, rfcsr
);
1843 * Set power & frequency of passband test tone
1845 rt2800_bbp_write(rt2x00dev
, 24, 0);
1847 for (i
= 0; i
< 100; i
++) {
1848 rt2800_bbp_write(rt2x00dev
, 25, 0x90);
1851 rt2800_bbp_read(rt2x00dev
, 55, &passband
);
1857 * Set power & frequency of stopband test tone
1859 rt2800_bbp_write(rt2x00dev
, 24, 0x06);
1861 for (i
= 0; i
< 100; i
++) {
1862 rt2800_bbp_write(rt2x00dev
, 25, 0x90);
1865 rt2800_bbp_read(rt2x00dev
, 55, &stopband
);
1867 if ((passband
- stopband
) <= filter_target
) {
1869 overtuned
+= ((passband
- stopband
) == filter_target
);
1873 rt2800_rfcsr_write(rt2x00dev
, 24, rfcsr24
);
1876 rfcsr24
-= !!overtuned
;
1878 rt2800_rfcsr_write(rt2x00dev
, 24, rfcsr24
);
1882 int rt2800_init_rfcsr(struct rt2x00_dev
*rt2x00dev
)
1889 if (!rt2x00_rt(rt2x00dev
, RT3070
) &&
1890 !rt2x00_rt(rt2x00dev
, RT3071
) &&
1891 !rt2x00_rt(rt2x00dev
, RT3090
) &&
1892 !rt2x00_rt(rt2x00dev
, RT3390
) &&
1893 !rt2800_is_305x_soc(rt2x00dev
))
1897 * Init RF calibration.
1899 rt2800_rfcsr_read(rt2x00dev
, 30, &rfcsr
);
1900 rt2x00_set_field8(&rfcsr
, RFCSR30_RF_CALIBRATION
, 1);
1901 rt2800_rfcsr_write(rt2x00dev
, 30, rfcsr
);
1903 rt2x00_set_field8(&rfcsr
, RFCSR30_RF_CALIBRATION
, 0);
1904 rt2800_rfcsr_write(rt2x00dev
, 30, rfcsr
);
1906 if (rt2x00_rt(rt2x00dev
, RT3070
) ||
1907 rt2x00_rt(rt2x00dev
, RT3071
) ||
1908 rt2x00_rt(rt2x00dev
, RT3090
)) {
1909 rt2800_rfcsr_write(rt2x00dev
, 4, 0x40);
1910 rt2800_rfcsr_write(rt2x00dev
, 5, 0x03);
1911 rt2800_rfcsr_write(rt2x00dev
, 6, 0x02);
1912 rt2800_rfcsr_write(rt2x00dev
, 7, 0x70);
1913 rt2800_rfcsr_write(rt2x00dev
, 9, 0x0f);
1914 rt2800_rfcsr_write(rt2x00dev
, 10, 0x41);
1915 rt2800_rfcsr_write(rt2x00dev
, 11, 0x21);
1916 rt2800_rfcsr_write(rt2x00dev
, 12, 0x7b);
1917 rt2800_rfcsr_write(rt2x00dev
, 14, 0x90);
1918 rt2800_rfcsr_write(rt2x00dev
, 15, 0x58);
1919 rt2800_rfcsr_write(rt2x00dev
, 16, 0xb3);
1920 rt2800_rfcsr_write(rt2x00dev
, 17, 0x92);
1921 rt2800_rfcsr_write(rt2x00dev
, 18, 0x2c);
1922 rt2800_rfcsr_write(rt2x00dev
, 19, 0x02);
1923 rt2800_rfcsr_write(rt2x00dev
, 20, 0xba);
1924 rt2800_rfcsr_write(rt2x00dev
, 21, 0xdb);
1925 rt2800_rfcsr_write(rt2x00dev
, 24, 0x16);
1926 rt2800_rfcsr_write(rt2x00dev
, 25, 0x01);
1927 rt2800_rfcsr_write(rt2x00dev
, 29, 0x1f);
1928 } else if (rt2x00_rt(rt2x00dev
, RT3390
)) {
1929 rt2800_rfcsr_write(rt2x00dev
, 0, 0xa0);
1930 rt2800_rfcsr_write(rt2x00dev
, 1, 0xe1);
1931 rt2800_rfcsr_write(rt2x00dev
, 2, 0xf1);
1932 rt2800_rfcsr_write(rt2x00dev
, 3, 0x62);
1933 rt2800_rfcsr_write(rt2x00dev
, 4, 0x40);
1934 rt2800_rfcsr_write(rt2x00dev
, 5, 0x8b);
1935 rt2800_rfcsr_write(rt2x00dev
, 6, 0x42);
1936 rt2800_rfcsr_write(rt2x00dev
, 7, 0x34);
1937 rt2800_rfcsr_write(rt2x00dev
, 8, 0x00);
1938 rt2800_rfcsr_write(rt2x00dev
, 9, 0xc0);
1939 rt2800_rfcsr_write(rt2x00dev
, 10, 0x61);
1940 rt2800_rfcsr_write(rt2x00dev
, 11, 0x21);
1941 rt2800_rfcsr_write(rt2x00dev
, 12, 0x3b);
1942 rt2800_rfcsr_write(rt2x00dev
, 13, 0xe0);
1943 rt2800_rfcsr_write(rt2x00dev
, 14, 0x90);
1944 rt2800_rfcsr_write(rt2x00dev
, 15, 0x53);
1945 rt2800_rfcsr_write(rt2x00dev
, 16, 0xe0);
1946 rt2800_rfcsr_write(rt2x00dev
, 17, 0x94);
1947 rt2800_rfcsr_write(rt2x00dev
, 18, 0x5c);
1948 rt2800_rfcsr_write(rt2x00dev
, 19, 0x4a);
1949 rt2800_rfcsr_write(rt2x00dev
, 20, 0xb2);
1950 rt2800_rfcsr_write(rt2x00dev
, 21, 0xf6);
1951 rt2800_rfcsr_write(rt2x00dev
, 22, 0x00);
1952 rt2800_rfcsr_write(rt2x00dev
, 23, 0x14);
1953 rt2800_rfcsr_write(rt2x00dev
, 24, 0x08);
1954 rt2800_rfcsr_write(rt2x00dev
, 25, 0x3d);
1955 rt2800_rfcsr_write(rt2x00dev
, 26, 0x85);
1956 rt2800_rfcsr_write(rt2x00dev
, 27, 0x00);
1957 rt2800_rfcsr_write(rt2x00dev
, 28, 0x41);
1958 rt2800_rfcsr_write(rt2x00dev
, 29, 0x8f);
1959 rt2800_rfcsr_write(rt2x00dev
, 30, 0x20);
1960 rt2800_rfcsr_write(rt2x00dev
, 31, 0x0f);
1961 } else if (rt2800_is_305x_soc(rt2x00dev
)) {
1962 rt2800_rfcsr_write(rt2x00dev
, 0, 0x50);
1963 rt2800_rfcsr_write(rt2x00dev
, 1, 0x01);
1964 rt2800_rfcsr_write(rt2x00dev
, 2, 0xf7);
1965 rt2800_rfcsr_write(rt2x00dev
, 3, 0x75);
1966 rt2800_rfcsr_write(rt2x00dev
, 4, 0x40);
1967 rt2800_rfcsr_write(rt2x00dev
, 5, 0x03);
1968 rt2800_rfcsr_write(rt2x00dev
, 6, 0x02);
1969 rt2800_rfcsr_write(rt2x00dev
, 7, 0x50);
1970 rt2800_rfcsr_write(rt2x00dev
, 8, 0x39);
1971 rt2800_rfcsr_write(rt2x00dev
, 9, 0x0f);
1972 rt2800_rfcsr_write(rt2x00dev
, 10, 0x60);
1973 rt2800_rfcsr_write(rt2x00dev
, 11, 0x21);
1974 rt2800_rfcsr_write(rt2x00dev
, 12, 0x75);
1975 rt2800_rfcsr_write(rt2x00dev
, 13, 0x75);
1976 rt2800_rfcsr_write(rt2x00dev
, 14, 0x90);
1977 rt2800_rfcsr_write(rt2x00dev
, 15, 0x58);
1978 rt2800_rfcsr_write(rt2x00dev
, 16, 0xb3);
1979 rt2800_rfcsr_write(rt2x00dev
, 17, 0x92);
1980 rt2800_rfcsr_write(rt2x00dev
, 18, 0x2c);
1981 rt2800_rfcsr_write(rt2x00dev
, 19, 0x02);
1982 rt2800_rfcsr_write(rt2x00dev
, 20, 0xba);
1983 rt2800_rfcsr_write(rt2x00dev
, 21, 0xdb);
1984 rt2800_rfcsr_write(rt2x00dev
, 22, 0x00);
1985 rt2800_rfcsr_write(rt2x00dev
, 23, 0x31);
1986 rt2800_rfcsr_write(rt2x00dev
, 24, 0x08);
1987 rt2800_rfcsr_write(rt2x00dev
, 25, 0x01);
1988 rt2800_rfcsr_write(rt2x00dev
, 26, 0x25);
1989 rt2800_rfcsr_write(rt2x00dev
, 27, 0x23);
1990 rt2800_rfcsr_write(rt2x00dev
, 28, 0x13);
1991 rt2800_rfcsr_write(rt2x00dev
, 29, 0x83);
1992 rt2800_rfcsr_write(rt2x00dev
, 30, 0x00);
1993 rt2800_rfcsr_write(rt2x00dev
, 31, 0x00);
1997 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070F
)) {
1998 rt2800_register_read(rt2x00dev
, LDO_CFG0
, ®
);
1999 rt2x00_set_field32(®
, LDO_CFG0_BGSEL
, 1);
2000 rt2x00_set_field32(®
, LDO_CFG0_LDO_CORE_VLEVEL
, 3);
2001 rt2800_register_write(rt2x00dev
, LDO_CFG0
, reg
);
2002 } else if (rt2x00_rt(rt2x00dev
, RT3071
) ||
2003 rt2x00_rt(rt2x00dev
, RT3090
)) {
2004 rt2800_rfcsr_read(rt2x00dev
, 6, &rfcsr
);
2005 rt2x00_set_field8(&rfcsr
, RFCSR6_R2
, 1);
2006 rt2800_rfcsr_write(rt2x00dev
, 6, rfcsr
);
2008 rt2800_rfcsr_write(rt2x00dev
, 31, 0x14);
2010 rt2800_register_read(rt2x00dev
, LDO_CFG0
, ®
);
2011 rt2x00_set_field32(®
, LDO_CFG0_BGSEL
, 1);
2012 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3071
, REV_RT3071E
) ||
2013 rt2x00_rt_rev_lt(rt2x00dev
, RT3090
, REV_RT3090E
)) {
2014 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC
, &eeprom
);
2015 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_DAC_TEST
))
2016 rt2x00_set_field32(®
, LDO_CFG0_LDO_CORE_VLEVEL
, 3);
2018 rt2x00_set_field32(®
, LDO_CFG0_LDO_CORE_VLEVEL
, 0);
2020 rt2800_register_write(rt2x00dev
, LDO_CFG0
, reg
);
2021 } else if (rt2x00_rt(rt2x00dev
, RT3390
)) {
2022 rt2800_register_read(rt2x00dev
, GPIO_SWITCH
, ®
);
2023 rt2x00_set_field32(®
, GPIO_SWITCH_5
, 0);
2024 rt2800_register_write(rt2x00dev
, GPIO_SWITCH
, reg
);
2028 * Set RX Filter calibration for 20MHz and 40MHz
2030 if (rt2x00_rt(rt2x00dev
, RT3070
)) {
2031 rt2x00dev
->calibration
[0] =
2032 rt2800_init_rx_filter(rt2x00dev
, false, 0x07, 0x16);
2033 rt2x00dev
->calibration
[1] =
2034 rt2800_init_rx_filter(rt2x00dev
, true, 0x27, 0x19);
2035 } else if (rt2x00_rt(rt2x00dev
, RT3071
) ||
2036 rt2x00_rt(rt2x00dev
, RT3090
) ||
2037 rt2x00_rt(rt2x00dev
, RT3390
)) {
2038 rt2x00dev
->calibration
[0] =
2039 rt2800_init_rx_filter(rt2x00dev
, false, 0x07, 0x13);
2040 rt2x00dev
->calibration
[1] =
2041 rt2800_init_rx_filter(rt2x00dev
, true, 0x27, 0x15);
2045 * Set back to initial state
2047 rt2800_bbp_write(rt2x00dev
, 24, 0);
2049 rt2800_rfcsr_read(rt2x00dev
, 22, &rfcsr
);
2050 rt2x00_set_field8(&rfcsr
, RFCSR22_BASEBAND_LOOPBACK
, 0);
2051 rt2800_rfcsr_write(rt2x00dev
, 22, rfcsr
);
2054 * set BBP back to BW20
2056 rt2800_bbp_read(rt2x00dev
, 4, &bbp
);
2057 rt2x00_set_field8(&bbp
, BBP4_BANDWIDTH
, 0);
2058 rt2800_bbp_write(rt2x00dev
, 4, bbp
);
2060 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070F
) ||
2061 rt2x00_rt_rev_lt(rt2x00dev
, RT3071
, REV_RT3071E
) ||
2062 rt2x00_rt_rev_lt(rt2x00dev
, RT3090
, REV_RT3090E
) ||
2063 rt2x00_rt_rev_lt(rt2x00dev
, RT3390
, REV_RT3390E
))
2064 rt2800_rfcsr_write(rt2x00dev
, 27, 0x03);
2066 rt2800_register_read(rt2x00dev
, OPT_14_CSR
, ®
);
2067 rt2x00_set_field32(®
, OPT_14_CSR_BIT0
, 1);
2068 rt2800_register_write(rt2x00dev
, OPT_14_CSR
, reg
);
2070 rt2800_rfcsr_read(rt2x00dev
, 17, &rfcsr
);
2071 rt2x00_set_field8(&rfcsr
, RFCSR17_TX_LO1_EN
, 0);
2072 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3071
, REV_RT3071E
) ||
2073 rt2x00_rt_rev_lt(rt2x00dev
, RT3090
, REV_RT3090E
) ||
2074 rt2x00_rt_rev_lt(rt2x00dev
, RT3390
, REV_RT3390E
)) {
2075 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC
, &eeprom
);
2076 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_EXTERNAL_LNA_BG
))
2077 rt2x00_set_field8(&rfcsr
, RFCSR17_R
, 1);
2079 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TXMIXER_GAIN_BG
, &eeprom
);
2080 if (rt2x00_get_field16(eeprom
, EEPROM_TXMIXER_GAIN_BG_VAL
) >= 1)
2081 rt2x00_set_field8(&rfcsr
, RFCSR17_TXMIXER_GAIN
,
2082 rt2x00_get_field16(eeprom
,
2083 EEPROM_TXMIXER_GAIN_BG_VAL
));
2084 rt2800_rfcsr_write(rt2x00dev
, 17, rfcsr
);
2086 if (rt2x00_rt(rt2x00dev
, RT3090
)) {
2087 rt2800_bbp_read(rt2x00dev
, 138, &bbp
);
2089 rt2x00_eeprom_read(rt2x00dev
, EEPROM_ANTENNA
, &eeprom
);
2090 if (rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_RXPATH
) == 1)
2091 rt2x00_set_field8(&bbp
, BBP138_RX_ADC1
, 0);
2092 if (rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_TXPATH
) == 1)
2093 rt2x00_set_field8(&bbp
, BBP138_TX_DAC1
, 1);
2095 rt2800_bbp_write(rt2x00dev
, 138, bbp
);
2098 if (rt2x00_rt(rt2x00dev
, RT3071
) ||
2099 rt2x00_rt(rt2x00dev
, RT3090
) ||
2100 rt2x00_rt(rt2x00dev
, RT3390
)) {
2101 rt2800_rfcsr_read(rt2x00dev
, 1, &rfcsr
);
2102 rt2x00_set_field8(&rfcsr
, RFCSR1_RF_BLOCK_EN
, 1);
2103 rt2x00_set_field8(&rfcsr
, RFCSR1_RX0_PD
, 0);
2104 rt2x00_set_field8(&rfcsr
, RFCSR1_TX0_PD
, 0);
2105 rt2x00_set_field8(&rfcsr
, RFCSR1_RX1_PD
, 1);
2106 rt2x00_set_field8(&rfcsr
, RFCSR1_TX1_PD
, 1);
2107 rt2800_rfcsr_write(rt2x00dev
, 1, rfcsr
);
2109 rt2800_rfcsr_read(rt2x00dev
, 15, &rfcsr
);
2110 rt2x00_set_field8(&rfcsr
, RFCSR15_TX_LO2_EN
, 0);
2111 rt2800_rfcsr_write(rt2x00dev
, 15, rfcsr
);
2113 rt2800_rfcsr_read(rt2x00dev
, 20, &rfcsr
);
2114 rt2x00_set_field8(&rfcsr
, RFCSR20_RX_LO1_EN
, 0);
2115 rt2800_rfcsr_write(rt2x00dev
, 20, rfcsr
);
2117 rt2800_rfcsr_read(rt2x00dev
, 21, &rfcsr
);
2118 rt2x00_set_field8(&rfcsr
, RFCSR21_RX_LO2_EN
, 0);
2119 rt2800_rfcsr_write(rt2x00dev
, 21, rfcsr
);
2122 if (rt2x00_rt(rt2x00dev
, RT3070
) || rt2x00_rt(rt2x00dev
, RT3071
)) {
2123 rt2800_rfcsr_read(rt2x00dev
, 27, &rfcsr
);
2124 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070F
) ||
2125 rt2x00_rt_rev_lt(rt2x00dev
, RT3071
, REV_RT3071E
))
2126 rt2x00_set_field8(&rfcsr
, RFCSR27_R1
, 3);
2128 rt2x00_set_field8(&rfcsr
, RFCSR27_R1
, 0);
2129 rt2x00_set_field8(&rfcsr
, RFCSR27_R2
, 0);
2130 rt2x00_set_field8(&rfcsr
, RFCSR27_R3
, 0);
2131 rt2x00_set_field8(&rfcsr
, RFCSR27_R4
, 0);
2132 rt2800_rfcsr_write(rt2x00dev
, 27, rfcsr
);
2137 EXPORT_SYMBOL_GPL(rt2800_init_rfcsr
);
2139 int rt2800_efuse_detect(struct rt2x00_dev
*rt2x00dev
)
2143 rt2800_register_read(rt2x00dev
, EFUSE_CTRL
, ®
);
2145 return rt2x00_get_field32(reg
, EFUSE_CTRL_PRESENT
);
2147 EXPORT_SYMBOL_GPL(rt2800_efuse_detect
);
2149 static void rt2800_efuse_read(struct rt2x00_dev
*rt2x00dev
, unsigned int i
)
2153 mutex_lock(&rt2x00dev
->csr_mutex
);
2155 rt2800_register_read_lock(rt2x00dev
, EFUSE_CTRL
, ®
);
2156 rt2x00_set_field32(®
, EFUSE_CTRL_ADDRESS_IN
, i
);
2157 rt2x00_set_field32(®
, EFUSE_CTRL_MODE
, 0);
2158 rt2x00_set_field32(®
, EFUSE_CTRL_KICK
, 1);
2159 rt2800_register_write_lock(rt2x00dev
, EFUSE_CTRL
, reg
);
2161 /* Wait until the EEPROM has been loaded */
2162 rt2800_regbusy_read(rt2x00dev
, EFUSE_CTRL
, EFUSE_CTRL_KICK
, ®
);
2164 /* Apparently the data is read from end to start */
2165 rt2800_register_read_lock(rt2x00dev
, EFUSE_DATA3
,
2166 (u32
*)&rt2x00dev
->eeprom
[i
]);
2167 rt2800_register_read_lock(rt2x00dev
, EFUSE_DATA2
,
2168 (u32
*)&rt2x00dev
->eeprom
[i
+ 2]);
2169 rt2800_register_read_lock(rt2x00dev
, EFUSE_DATA1
,
2170 (u32
*)&rt2x00dev
->eeprom
[i
+ 4]);
2171 rt2800_register_read_lock(rt2x00dev
, EFUSE_DATA0
,
2172 (u32
*)&rt2x00dev
->eeprom
[i
+ 6]);
2174 mutex_unlock(&rt2x00dev
->csr_mutex
);
2177 void rt2800_read_eeprom_efuse(struct rt2x00_dev
*rt2x00dev
)
2181 for (i
= 0; i
< EEPROM_SIZE
/ sizeof(u16
); i
+= 8)
2182 rt2800_efuse_read(rt2x00dev
, i
);
2184 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse
);
2186 int rt2800_validate_eeprom(struct rt2x00_dev
*rt2x00dev
)
2190 u8 default_lna_gain
;
2193 * Start validation of the data that has been read.
2195 mac
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_MAC_ADDR_0
);
2196 if (!is_valid_ether_addr(mac
)) {
2197 random_ether_addr(mac
);
2198 EEPROM(rt2x00dev
, "MAC: %pM\n", mac
);
2201 rt2x00_eeprom_read(rt2x00dev
, EEPROM_ANTENNA
, &word
);
2202 if (word
== 0xffff) {
2203 rt2x00_set_field16(&word
, EEPROM_ANTENNA_RXPATH
, 2);
2204 rt2x00_set_field16(&word
, EEPROM_ANTENNA_TXPATH
, 1);
2205 rt2x00_set_field16(&word
, EEPROM_ANTENNA_RF_TYPE
, RF2820
);
2206 rt2x00_eeprom_write(rt2x00dev
, EEPROM_ANTENNA
, word
);
2207 EEPROM(rt2x00dev
, "Antenna: 0x%04x\n", word
);
2208 } else if (rt2x00_rt(rt2x00dev
, RT2860
) ||
2209 rt2x00_rt(rt2x00dev
, RT2872
)) {
2211 * There is a max of 2 RX streams for RT28x0 series
2213 if (rt2x00_get_field16(word
, EEPROM_ANTENNA_RXPATH
) > 2)
2214 rt2x00_set_field16(&word
, EEPROM_ANTENNA_RXPATH
, 2);
2215 rt2x00_eeprom_write(rt2x00dev
, EEPROM_ANTENNA
, word
);
2218 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC
, &word
);
2219 if (word
== 0xffff) {
2220 rt2x00_set_field16(&word
, EEPROM_NIC_HW_RADIO
, 0);
2221 rt2x00_set_field16(&word
, EEPROM_NIC_DYNAMIC_TX_AGC
, 0);
2222 rt2x00_set_field16(&word
, EEPROM_NIC_EXTERNAL_LNA_BG
, 0);
2223 rt2x00_set_field16(&word
, EEPROM_NIC_EXTERNAL_LNA_A
, 0);
2224 rt2x00_set_field16(&word
, EEPROM_NIC_CARDBUS_ACCEL
, 0);
2225 rt2x00_set_field16(&word
, EEPROM_NIC_BW40M_SB_BG
, 0);
2226 rt2x00_set_field16(&word
, EEPROM_NIC_BW40M_SB_A
, 0);
2227 rt2x00_set_field16(&word
, EEPROM_NIC_WPS_PBC
, 0);
2228 rt2x00_set_field16(&word
, EEPROM_NIC_BW40M_BG
, 0);
2229 rt2x00_set_field16(&word
, EEPROM_NIC_BW40M_A
, 0);
2230 rt2x00_eeprom_write(rt2x00dev
, EEPROM_NIC
, word
);
2231 EEPROM(rt2x00dev
, "NIC: 0x%04x\n", word
);
2234 rt2x00_eeprom_read(rt2x00dev
, EEPROM_FREQ
, &word
);
2235 if ((word
& 0x00ff) == 0x00ff) {
2236 rt2x00_set_field16(&word
, EEPROM_FREQ_OFFSET
, 0);
2237 rt2x00_set_field16(&word
, EEPROM_FREQ_LED_MODE
,
2238 LED_MODE_TXRX_ACTIVITY
);
2239 rt2x00_set_field16(&word
, EEPROM_FREQ_LED_POLARITY
, 0);
2240 rt2x00_eeprom_write(rt2x00dev
, EEPROM_FREQ
, word
);
2241 rt2x00_eeprom_write(rt2x00dev
, EEPROM_LED1
, 0x5555);
2242 rt2x00_eeprom_write(rt2x00dev
, EEPROM_LED2
, 0x2221);
2243 rt2x00_eeprom_write(rt2x00dev
, EEPROM_LED3
, 0xa9f8);
2244 EEPROM(rt2x00dev
, "Freq: 0x%04x\n", word
);
2248 * During the LNA validation we are going to use
2249 * lna0 as correct value. Note that EEPROM_LNA
2250 * is never validated.
2252 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LNA
, &word
);
2253 default_lna_gain
= rt2x00_get_field16(word
, EEPROM_LNA_A0
);
2255 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_BG
, &word
);
2256 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_BG_OFFSET0
)) > 10)
2257 rt2x00_set_field16(&word
, EEPROM_RSSI_BG_OFFSET0
, 0);
2258 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_BG_OFFSET1
)) > 10)
2259 rt2x00_set_field16(&word
, EEPROM_RSSI_BG_OFFSET1
, 0);
2260 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_BG
, word
);
2262 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_BG2
, &word
);
2263 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_BG2_OFFSET2
)) > 10)
2264 rt2x00_set_field16(&word
, EEPROM_RSSI_BG2_OFFSET2
, 0);
2265 if (rt2x00_get_field16(word
, EEPROM_RSSI_BG2_LNA_A1
) == 0x00 ||
2266 rt2x00_get_field16(word
, EEPROM_RSSI_BG2_LNA_A1
) == 0xff)
2267 rt2x00_set_field16(&word
, EEPROM_RSSI_BG2_LNA_A1
,
2269 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_BG2
, word
);
2271 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_A
, &word
);
2272 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_A_OFFSET0
)) > 10)
2273 rt2x00_set_field16(&word
, EEPROM_RSSI_A_OFFSET0
, 0);
2274 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_A_OFFSET1
)) > 10)
2275 rt2x00_set_field16(&word
, EEPROM_RSSI_A_OFFSET1
, 0);
2276 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_A
, word
);
2278 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_A2
, &word
);
2279 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_A2_OFFSET2
)) > 10)
2280 rt2x00_set_field16(&word
, EEPROM_RSSI_A2_OFFSET2
, 0);
2281 if (rt2x00_get_field16(word
, EEPROM_RSSI_A2_LNA_A2
) == 0x00 ||
2282 rt2x00_get_field16(word
, EEPROM_RSSI_A2_LNA_A2
) == 0xff)
2283 rt2x00_set_field16(&word
, EEPROM_RSSI_A2_LNA_A2
,
2285 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_A2
, word
);
2289 EXPORT_SYMBOL_GPL(rt2800_validate_eeprom
);
2291 int rt2800_init_eeprom(struct rt2x00_dev
*rt2x00dev
)
2298 * Read EEPROM word for configuration.
2300 rt2x00_eeprom_read(rt2x00dev
, EEPROM_ANTENNA
, &eeprom
);
2303 * Identify RF chipset.
2305 value
= rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_RF_TYPE
);
2306 rt2800_register_read(rt2x00dev
, MAC_CSR0
, ®
);
2308 rt2x00_set_chip(rt2x00dev
, rt2x00_get_field32(reg
, MAC_CSR0_CHIPSET
),
2309 value
, rt2x00_get_field32(reg
, MAC_CSR0_REVISION
));
2311 if (!rt2x00_rt(rt2x00dev
, RT2860
) &&
2312 !rt2x00_rt(rt2x00dev
, RT2872
) &&
2313 !rt2x00_rt(rt2x00dev
, RT2883
) &&
2314 !rt2x00_rt(rt2x00dev
, RT3070
) &&
2315 !rt2x00_rt(rt2x00dev
, RT3071
) &&
2316 !rt2x00_rt(rt2x00dev
, RT3090
) &&
2317 !rt2x00_rt(rt2x00dev
, RT3390
) &&
2318 !rt2x00_rt(rt2x00dev
, RT3572
)) {
2319 ERROR(rt2x00dev
, "Invalid RT chipset detected.\n");
2323 if (!rt2x00_rf(rt2x00dev
, RF2820
) &&
2324 !rt2x00_rf(rt2x00dev
, RF2850
) &&
2325 !rt2x00_rf(rt2x00dev
, RF2720
) &&
2326 !rt2x00_rf(rt2x00dev
, RF2750
) &&
2327 !rt2x00_rf(rt2x00dev
, RF3020
) &&
2328 !rt2x00_rf(rt2x00dev
, RF2020
) &&
2329 !rt2x00_rf(rt2x00dev
, RF3021
) &&
2330 !rt2x00_rf(rt2x00dev
, RF3022
) &&
2331 !rt2x00_rf(rt2x00dev
, RF3052
)) {
2332 ERROR(rt2x00dev
, "Invalid RF chipset detected.\n");
2337 * Identify default antenna configuration.
2339 rt2x00dev
->default_ant
.tx
=
2340 rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_TXPATH
);
2341 rt2x00dev
->default_ant
.rx
=
2342 rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_RXPATH
);
2345 * Read frequency offset and RF programming sequence.
2347 rt2x00_eeprom_read(rt2x00dev
, EEPROM_FREQ
, &eeprom
);
2348 rt2x00dev
->freq_offset
= rt2x00_get_field16(eeprom
, EEPROM_FREQ_OFFSET
);
2351 * Read external LNA informations.
2353 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC
, &eeprom
);
2355 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_EXTERNAL_LNA_A
))
2356 __set_bit(CONFIG_EXTERNAL_LNA_A
, &rt2x00dev
->flags
);
2357 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_EXTERNAL_LNA_BG
))
2358 __set_bit(CONFIG_EXTERNAL_LNA_BG
, &rt2x00dev
->flags
);
2361 * Detect if this device has an hardware controlled radio.
2363 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_HW_RADIO
))
2364 __set_bit(CONFIG_SUPPORT_HW_BUTTON
, &rt2x00dev
->flags
);
2367 * Store led settings, for correct led behaviour.
2369 #ifdef CONFIG_RT2X00_LIB_LEDS
2370 rt2800_init_led(rt2x00dev
, &rt2x00dev
->led_radio
, LED_TYPE_RADIO
);
2371 rt2800_init_led(rt2x00dev
, &rt2x00dev
->led_assoc
, LED_TYPE_ASSOC
);
2372 rt2800_init_led(rt2x00dev
, &rt2x00dev
->led_qual
, LED_TYPE_QUALITY
);
2374 rt2x00_eeprom_read(rt2x00dev
, EEPROM_FREQ
, &rt2x00dev
->led_mcu_reg
);
2375 #endif /* CONFIG_RT2X00_LIB_LEDS */
2379 EXPORT_SYMBOL_GPL(rt2800_init_eeprom
);
2382 * RF value list for rt28xx
2383 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
2385 static const struct rf_channel rf_vals
[] = {
2386 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
2387 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
2388 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
2389 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
2390 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
2391 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
2392 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
2393 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
2394 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
2395 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
2396 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
2397 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
2398 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
2399 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
2401 /* 802.11 UNI / HyperLan 2 */
2402 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
2403 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
2404 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
2405 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
2406 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
2407 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
2408 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
2409 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
2410 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
2411 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
2412 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
2413 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
2415 /* 802.11 HyperLan 2 */
2416 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
2417 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
2418 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
2419 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
2420 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
2421 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
2422 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
2423 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
2424 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
2425 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
2426 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
2427 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
2428 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
2429 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
2430 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
2431 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
2434 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
2435 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
2436 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
2437 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
2438 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
2439 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
2440 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
2441 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
2442 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
2443 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
2444 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
2447 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
2448 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
2449 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
2450 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
2451 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
2452 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
2453 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
2457 * RF value list for rt3xxx
2458 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
2460 static const struct rf_channel rf_vals_3x
[] = {
2476 /* 802.11 UNI / HyperLan 2 */
2490 /* 802.11 HyperLan 2 */
2522 int rt2800_probe_hw_mode(struct rt2x00_dev
*rt2x00dev
)
2524 struct hw_mode_spec
*spec
= &rt2x00dev
->spec
;
2525 struct channel_info
*info
;
2532 * Disable powersaving as default on PCI devices.
2534 if (rt2x00_is_pci(rt2x00dev
) || rt2x00_is_soc(rt2x00dev
))
2535 rt2x00dev
->hw
->wiphy
->flags
&= ~WIPHY_FLAG_PS_ON_BY_DEFAULT
;
2538 * Initialize all hw fields.
2540 rt2x00dev
->hw
->flags
=
2541 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING
|
2542 IEEE80211_HW_SIGNAL_DBM
|
2543 IEEE80211_HW_SUPPORTS_PS
|
2544 IEEE80211_HW_PS_NULLFUNC_STACK
;
2546 SET_IEEE80211_DEV(rt2x00dev
->hw
, rt2x00dev
->dev
);
2547 SET_IEEE80211_PERM_ADDR(rt2x00dev
->hw
,
2548 rt2x00_eeprom_addr(rt2x00dev
,
2549 EEPROM_MAC_ADDR_0
));
2551 rt2x00_eeprom_read(rt2x00dev
, EEPROM_ANTENNA
, &eeprom
);
2554 * Initialize hw_mode information.
2556 spec
->supported_bands
= SUPPORT_BAND_2GHZ
;
2557 spec
->supported_rates
= SUPPORT_RATE_CCK
| SUPPORT_RATE_OFDM
;
2559 if (rt2x00_rf(rt2x00dev
, RF2820
) ||
2560 rt2x00_rf(rt2x00dev
, RF2720
)) {
2561 spec
->num_channels
= 14;
2562 spec
->channels
= rf_vals
;
2563 } else if (rt2x00_rf(rt2x00dev
, RF2850
) ||
2564 rt2x00_rf(rt2x00dev
, RF2750
)) {
2565 spec
->supported_bands
|= SUPPORT_BAND_5GHZ
;
2566 spec
->num_channels
= ARRAY_SIZE(rf_vals
);
2567 spec
->channels
= rf_vals
;
2568 } else if (rt2x00_rf(rt2x00dev
, RF3020
) ||
2569 rt2x00_rf(rt2x00dev
, RF2020
) ||
2570 rt2x00_rf(rt2x00dev
, RF3021
) ||
2571 rt2x00_rf(rt2x00dev
, RF3022
)) {
2572 spec
->num_channels
= 14;
2573 spec
->channels
= rf_vals_3x
;
2574 } else if (rt2x00_rf(rt2x00dev
, RF3052
)) {
2575 spec
->supported_bands
|= SUPPORT_BAND_5GHZ
;
2576 spec
->num_channels
= ARRAY_SIZE(rf_vals_3x
);
2577 spec
->channels
= rf_vals_3x
;
2581 * Initialize HT information.
2583 if (!rt2x00_rf(rt2x00dev
, RF2020
))
2584 spec
->ht
.ht_supported
= true;
2586 spec
->ht
.ht_supported
= false;
2589 * Don't set IEEE80211_HT_CAP_SUP_WIDTH_20_40 for now as it causes
2590 * reception problems with HT40 capable 11n APs
2593 IEEE80211_HT_CAP_GRN_FLD
|
2594 IEEE80211_HT_CAP_SGI_20
|
2595 IEEE80211_HT_CAP_SGI_40
|
2596 IEEE80211_HT_CAP_TX_STBC
|
2597 IEEE80211_HT_CAP_RX_STBC
;
2598 spec
->ht
.ampdu_factor
= 3;
2599 spec
->ht
.ampdu_density
= 4;
2600 spec
->ht
.mcs
.tx_params
=
2601 IEEE80211_HT_MCS_TX_DEFINED
|
2602 IEEE80211_HT_MCS_TX_RX_DIFF
|
2603 ((rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_TXPATH
) - 1) <<
2604 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT
);
2606 switch (rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_RXPATH
)) {
2608 spec
->ht
.mcs
.rx_mask
[2] = 0xff;
2610 spec
->ht
.mcs
.rx_mask
[1] = 0xff;
2612 spec
->ht
.mcs
.rx_mask
[0] = 0xff;
2613 spec
->ht
.mcs
.rx_mask
[4] = 0x1; /* MCS32 */
2618 * Create channel information array
2620 info
= kzalloc(spec
->num_channels
* sizeof(*info
), GFP_KERNEL
);
2624 spec
->channels_info
= info
;
2626 tx_power1
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_BG1
);
2627 tx_power2
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_BG2
);
2629 for (i
= 0; i
< 14; i
++) {
2630 info
[i
].tx_power1
= TXPOWER_G_FROM_DEV(tx_power1
[i
]);
2631 info
[i
].tx_power2
= TXPOWER_G_FROM_DEV(tx_power2
[i
]);
2634 if (spec
->num_channels
> 14) {
2635 tx_power1
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_A1
);
2636 tx_power2
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_A2
);
2638 for (i
= 14; i
< spec
->num_channels
; i
++) {
2639 info
[i
].tx_power1
= TXPOWER_A_FROM_DEV(tx_power1
[i
]);
2640 info
[i
].tx_power2
= TXPOWER_A_FROM_DEV(tx_power2
[i
]);
2646 EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode
);
2649 * IEEE80211 stack callback functions.
2651 static void rt2800_get_tkip_seq(struct ieee80211_hw
*hw
, u8 hw_key_idx
,
2652 u32
*iv32
, u16
*iv16
)
2654 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
2655 struct mac_iveiv_entry iveiv_entry
;
2658 offset
= MAC_IVEIV_ENTRY(hw_key_idx
);
2659 rt2800_register_multiread(rt2x00dev
, offset
,
2660 &iveiv_entry
, sizeof(iveiv_entry
));
2662 memcpy(iv16
, &iveiv_entry
.iv
[0], sizeof(*iv16
));
2663 memcpy(iv32
, &iveiv_entry
.iv
[4], sizeof(*iv32
));
2666 static int rt2800_set_rts_threshold(struct ieee80211_hw
*hw
, u32 value
)
2668 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
2670 bool enabled
= (value
< IEEE80211_MAX_RTS_THRESHOLD
);
2672 rt2800_register_read(rt2x00dev
, TX_RTS_CFG
, ®
);
2673 rt2x00_set_field32(®
, TX_RTS_CFG_RTS_THRES
, value
);
2674 rt2800_register_write(rt2x00dev
, TX_RTS_CFG
, reg
);
2676 rt2800_register_read(rt2x00dev
, CCK_PROT_CFG
, ®
);
2677 rt2x00_set_field32(®
, CCK_PROT_CFG_RTS_TH_EN
, enabled
);
2678 rt2800_register_write(rt2x00dev
, CCK_PROT_CFG
, reg
);
2680 rt2800_register_read(rt2x00dev
, OFDM_PROT_CFG
, ®
);
2681 rt2x00_set_field32(®
, OFDM_PROT_CFG_RTS_TH_EN
, enabled
);
2682 rt2800_register_write(rt2x00dev
, OFDM_PROT_CFG
, reg
);
2684 rt2800_register_read(rt2x00dev
, MM20_PROT_CFG
, ®
);
2685 rt2x00_set_field32(®
, MM20_PROT_CFG_RTS_TH_EN
, enabled
);
2686 rt2800_register_write(rt2x00dev
, MM20_PROT_CFG
, reg
);
2688 rt2800_register_read(rt2x00dev
, MM40_PROT_CFG
, ®
);
2689 rt2x00_set_field32(®
, MM40_PROT_CFG_RTS_TH_EN
, enabled
);
2690 rt2800_register_write(rt2x00dev
, MM40_PROT_CFG
, reg
);
2692 rt2800_register_read(rt2x00dev
, GF20_PROT_CFG
, ®
);
2693 rt2x00_set_field32(®
, GF20_PROT_CFG_RTS_TH_EN
, enabled
);
2694 rt2800_register_write(rt2x00dev
, GF20_PROT_CFG
, reg
);
2696 rt2800_register_read(rt2x00dev
, GF40_PROT_CFG
, ®
);
2697 rt2x00_set_field32(®
, GF40_PROT_CFG_RTS_TH_EN
, enabled
);
2698 rt2800_register_write(rt2x00dev
, GF40_PROT_CFG
, reg
);
2703 static int rt2800_conf_tx(struct ieee80211_hw
*hw
, u16 queue_idx
,
2704 const struct ieee80211_tx_queue_params
*params
)
2706 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
2707 struct data_queue
*queue
;
2708 struct rt2x00_field32 field
;
2714 * First pass the configuration through rt2x00lib, that will
2715 * update the queue settings and validate the input. After that
2716 * we are free to update the registers based on the value
2717 * in the queue parameter.
2719 retval
= rt2x00mac_conf_tx(hw
, queue_idx
, params
);
2724 * We only need to perform additional register initialization
2730 queue
= rt2x00queue_get_queue(rt2x00dev
, queue_idx
);
2732 /* Update WMM TXOP register */
2733 offset
= WMM_TXOP0_CFG
+ (sizeof(u32
) * (!!(queue_idx
& 2)));
2734 field
.bit_offset
= (queue_idx
& 1) * 16;
2735 field
.bit_mask
= 0xffff << field
.bit_offset
;
2737 rt2800_register_read(rt2x00dev
, offset
, ®
);
2738 rt2x00_set_field32(®
, field
, queue
->txop
);
2739 rt2800_register_write(rt2x00dev
, offset
, reg
);
2741 /* Update WMM registers */
2742 field
.bit_offset
= queue_idx
* 4;
2743 field
.bit_mask
= 0xf << field
.bit_offset
;
2745 rt2800_register_read(rt2x00dev
, WMM_AIFSN_CFG
, ®
);
2746 rt2x00_set_field32(®
, field
, queue
->aifs
);
2747 rt2800_register_write(rt2x00dev
, WMM_AIFSN_CFG
, reg
);
2749 rt2800_register_read(rt2x00dev
, WMM_CWMIN_CFG
, ®
);
2750 rt2x00_set_field32(®
, field
, queue
->cw_min
);
2751 rt2800_register_write(rt2x00dev
, WMM_CWMIN_CFG
, reg
);
2753 rt2800_register_read(rt2x00dev
, WMM_CWMAX_CFG
, ®
);
2754 rt2x00_set_field32(®
, field
, queue
->cw_max
);
2755 rt2800_register_write(rt2x00dev
, WMM_CWMAX_CFG
, reg
);
2757 /* Update EDCA registers */
2758 offset
= EDCA_AC0_CFG
+ (sizeof(u32
) * queue_idx
);
2760 rt2800_register_read(rt2x00dev
, offset
, ®
);
2761 rt2x00_set_field32(®
, EDCA_AC0_CFG_TX_OP
, queue
->txop
);
2762 rt2x00_set_field32(®
, EDCA_AC0_CFG_AIFSN
, queue
->aifs
);
2763 rt2x00_set_field32(®
, EDCA_AC0_CFG_CWMIN
, queue
->cw_min
);
2764 rt2x00_set_field32(®
, EDCA_AC0_CFG_CWMAX
, queue
->cw_max
);
2765 rt2800_register_write(rt2x00dev
, offset
, reg
);
2770 static u64
rt2800_get_tsf(struct ieee80211_hw
*hw
)
2772 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
2776 rt2800_register_read(rt2x00dev
, TSF_TIMER_DW1
, ®
);
2777 tsf
= (u64
) rt2x00_get_field32(reg
, TSF_TIMER_DW1_HIGH_WORD
) << 32;
2778 rt2800_register_read(rt2x00dev
, TSF_TIMER_DW0
, ®
);
2779 tsf
|= rt2x00_get_field32(reg
, TSF_TIMER_DW0_LOW_WORD
);
2784 const struct ieee80211_ops rt2800_mac80211_ops
= {
2786 .start
= rt2x00mac_start
,
2787 .stop
= rt2x00mac_stop
,
2788 .add_interface
= rt2x00mac_add_interface
,
2789 .remove_interface
= rt2x00mac_remove_interface
,
2790 .config
= rt2x00mac_config
,
2791 .configure_filter
= rt2x00mac_configure_filter
,
2792 .set_tim
= rt2x00mac_set_tim
,
2793 .set_key
= rt2x00mac_set_key
,
2794 .get_stats
= rt2x00mac_get_stats
,
2795 .get_tkip_seq
= rt2800_get_tkip_seq
,
2796 .set_rts_threshold
= rt2800_set_rts_threshold
,
2797 .bss_info_changed
= rt2x00mac_bss_info_changed
,
2798 .conf_tx
= rt2800_conf_tx
,
2799 .get_tsf
= rt2800_get_tsf
,
2800 .rfkill_poll
= rt2x00mac_rfkill_poll
,
2802 EXPORT_SYMBOL_GPL(rt2800_mac80211_ops
);