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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wirel...
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt2800lib.c
1 /*
2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
3 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
4 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
5 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
6
7 Based on the original rt2800pci.c and rt2800usb.c.
8 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
9 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
10 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
11 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
12 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
13 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
14 <http://rt2x00.serialmonkey.com>
15
16 This program is free software; you can redistribute it and/or modify
17 it under the terms of the GNU General Public License as published by
18 the Free Software Foundation; either version 2 of the License, or
19 (at your option) any later version.
20
21 This program is distributed in the hope that it will be useful,
22 but WITHOUT ANY WARRANTY; without even the implied warranty of
23 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 GNU General Public License for more details.
25
26 You should have received a copy of the GNU General Public License
27 along with this program; if not, write to the
28 Free Software Foundation, Inc.,
29 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32 /*
33 Module: rt2800lib
34 Abstract: rt2800 generic device routines.
35 */
36
37 #include <linux/crc-ccitt.h>
38 #include <linux/kernel.h>
39 #include <linux/module.h>
40 #include <linux/slab.h>
41
42 #include "rt2x00.h"
43 #include "rt2800lib.h"
44 #include "rt2800.h"
45
46 /*
47 * Register access.
48 * All access to the CSR registers will go through the methods
49 * rt2800_register_read and rt2800_register_write.
50 * BBP and RF register require indirect register access,
51 * and use the CSR registers BBPCSR and RFCSR to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
55 * between each attampt. When the busy bit is still set at that time,
56 * the access attempt is considered to have failed,
57 * and we will print an error.
58 * The _lock versions must be used if you already hold the csr_mutex
59 */
60 #define WAIT_FOR_BBP(__dev, __reg) \
61 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
62 #define WAIT_FOR_RFCSR(__dev, __reg) \
63 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
64 #define WAIT_FOR_RF(__dev, __reg) \
65 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
66 #define WAIT_FOR_MCU(__dev, __reg) \
67 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
68 H2M_MAILBOX_CSR_OWNER, (__reg))
69
70 static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
71 {
72 /* check for rt2872 on SoC */
73 if (!rt2x00_is_soc(rt2x00dev) ||
74 !rt2x00_rt(rt2x00dev, RT2872))
75 return false;
76
77 /* we know for sure that these rf chipsets are used on rt305x boards */
78 if (rt2x00_rf(rt2x00dev, RF3020) ||
79 rt2x00_rf(rt2x00dev, RF3021) ||
80 rt2x00_rf(rt2x00dev, RF3022))
81 return true;
82
83 NOTICE(rt2x00dev, "Unknown RF chipset on rt305x\n");
84 return false;
85 }
86
87 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
88 const unsigned int word, const u8 value)
89 {
90 u32 reg;
91
92 mutex_lock(&rt2x00dev->csr_mutex);
93
94 /*
95 * Wait until the BBP becomes available, afterwards we
96 * can safely write the new data into the register.
97 */
98 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
99 reg = 0;
100 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
101 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
102 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
103 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
104 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
105
106 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
107 }
108
109 mutex_unlock(&rt2x00dev->csr_mutex);
110 }
111
112 static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
113 const unsigned int word, u8 *value)
114 {
115 u32 reg;
116
117 mutex_lock(&rt2x00dev->csr_mutex);
118
119 /*
120 * Wait until the BBP becomes available, afterwards we
121 * can safely write the read request into the register.
122 * After the data has been written, we wait until hardware
123 * returns the correct value, if at any time the register
124 * doesn't become available in time, reg will be 0xffffffff
125 * which means we return 0xff to the caller.
126 */
127 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
128 reg = 0;
129 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
130 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
131 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
132 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
133
134 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
135
136 WAIT_FOR_BBP(rt2x00dev, &reg);
137 }
138
139 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
140
141 mutex_unlock(&rt2x00dev->csr_mutex);
142 }
143
144 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
145 const unsigned int word, const u8 value)
146 {
147 u32 reg;
148
149 mutex_lock(&rt2x00dev->csr_mutex);
150
151 /*
152 * Wait until the RFCSR becomes available, afterwards we
153 * can safely write the new data into the register.
154 */
155 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
156 reg = 0;
157 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
158 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
159 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
160 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
161
162 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
163 }
164
165 mutex_unlock(&rt2x00dev->csr_mutex);
166 }
167
168 static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
169 const unsigned int word, u8 *value)
170 {
171 u32 reg;
172
173 mutex_lock(&rt2x00dev->csr_mutex);
174
175 /*
176 * Wait until the RFCSR becomes available, afterwards we
177 * can safely write the read request into the register.
178 * After the data has been written, we wait until hardware
179 * returns the correct value, if at any time the register
180 * doesn't become available in time, reg will be 0xffffffff
181 * which means we return 0xff to the caller.
182 */
183 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
184 reg = 0;
185 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
186 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
187 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
188
189 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
190
191 WAIT_FOR_RFCSR(rt2x00dev, &reg);
192 }
193
194 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
195
196 mutex_unlock(&rt2x00dev->csr_mutex);
197 }
198
199 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
200 const unsigned int word, const u32 value)
201 {
202 u32 reg;
203
204 mutex_lock(&rt2x00dev->csr_mutex);
205
206 /*
207 * Wait until the RF becomes available, afterwards we
208 * can safely write the new data into the register.
209 */
210 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
211 reg = 0;
212 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
213 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
214 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
215 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
216
217 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
218 rt2x00_rf_write(rt2x00dev, word, value);
219 }
220
221 mutex_unlock(&rt2x00dev->csr_mutex);
222 }
223
224 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
225 const u8 command, const u8 token,
226 const u8 arg0, const u8 arg1)
227 {
228 u32 reg;
229
230 /*
231 * SOC devices don't support MCU requests.
232 */
233 if (rt2x00_is_soc(rt2x00dev))
234 return;
235
236 mutex_lock(&rt2x00dev->csr_mutex);
237
238 /*
239 * Wait until the MCU becomes available, afterwards we
240 * can safely write the new data into the register.
241 */
242 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
243 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
244 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
245 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
246 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
247 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
248
249 reg = 0;
250 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
251 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
252 }
253
254 mutex_unlock(&rt2x00dev->csr_mutex);
255 }
256 EXPORT_SYMBOL_GPL(rt2800_mcu_request);
257
258 int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
259 {
260 unsigned int i = 0;
261 u32 reg;
262
263 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
264 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
265 if (reg && reg != ~0)
266 return 0;
267 msleep(1);
268 }
269
270 ERROR(rt2x00dev, "Unstable hardware.\n");
271 return -EBUSY;
272 }
273 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
274
275 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
276 {
277 unsigned int i;
278 u32 reg;
279
280 /*
281 * Some devices are really slow to respond here. Wait a whole second
282 * before timing out.
283 */
284 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
285 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
286 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
287 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
288 return 0;
289
290 msleep(10);
291 }
292
293 ERROR(rt2x00dev, "WPDMA TX/RX busy [0x%08x].\n", reg);
294 return -EACCES;
295 }
296 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
297
298 void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev)
299 {
300 u32 reg;
301
302 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
303 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
304 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
305 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
306 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
307 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
308 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
309 }
310 EXPORT_SYMBOL_GPL(rt2800_disable_wpdma);
311
312 static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
313 {
314 u16 fw_crc;
315 u16 crc;
316
317 /*
318 * The last 2 bytes in the firmware array are the crc checksum itself,
319 * this means that we should never pass those 2 bytes to the crc
320 * algorithm.
321 */
322 fw_crc = (data[len - 2] << 8 | data[len - 1]);
323
324 /*
325 * Use the crc ccitt algorithm.
326 * This will return the same value as the legacy driver which
327 * used bit ordering reversion on the both the firmware bytes
328 * before input input as well as on the final output.
329 * Obviously using crc ccitt directly is much more efficient.
330 */
331 crc = crc_ccitt(~0, data, len - 2);
332
333 /*
334 * There is a small difference between the crc-itu-t + bitrev and
335 * the crc-ccitt crc calculation. In the latter method the 2 bytes
336 * will be swapped, use swab16 to convert the crc to the correct
337 * value.
338 */
339 crc = swab16(crc);
340
341 return fw_crc == crc;
342 }
343
344 int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
345 const u8 *data, const size_t len)
346 {
347 size_t offset = 0;
348 size_t fw_len;
349 bool multiple;
350
351 /*
352 * PCI(e) & SOC devices require firmware with a length
353 * of 8kb. USB devices require firmware files with a length
354 * of 4kb. Certain USB chipsets however require different firmware,
355 * which Ralink only provides attached to the original firmware
356 * file. Thus for USB devices, firmware files have a length
357 * which is a multiple of 4kb.
358 */
359 if (rt2x00_is_usb(rt2x00dev)) {
360 fw_len = 4096;
361 multiple = true;
362 } else {
363 fw_len = 8192;
364 multiple = true;
365 }
366
367 /*
368 * Validate the firmware length
369 */
370 if (len != fw_len && (!multiple || (len % fw_len) != 0))
371 return FW_BAD_LENGTH;
372
373 /*
374 * Check if the chipset requires one of the upper parts
375 * of the firmware.
376 */
377 if (rt2x00_is_usb(rt2x00dev) &&
378 !rt2x00_rt(rt2x00dev, RT2860) &&
379 !rt2x00_rt(rt2x00dev, RT2872) &&
380 !rt2x00_rt(rt2x00dev, RT3070) &&
381 ((len / fw_len) == 1))
382 return FW_BAD_VERSION;
383
384 /*
385 * 8kb firmware files must be checked as if it were
386 * 2 separate firmware files.
387 */
388 while (offset < len) {
389 if (!rt2800_check_firmware_crc(data + offset, fw_len))
390 return FW_BAD_CRC;
391
392 offset += fw_len;
393 }
394
395 return FW_OK;
396 }
397 EXPORT_SYMBOL_GPL(rt2800_check_firmware);
398
399 int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
400 const u8 *data, const size_t len)
401 {
402 unsigned int i;
403 u32 reg;
404
405 /*
406 * If driver doesn't wake up firmware here,
407 * rt2800_load_firmware will hang forever when interface is up again.
408 */
409 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
410
411 /*
412 * Wait for stable hardware.
413 */
414 if (rt2800_wait_csr_ready(rt2x00dev))
415 return -EBUSY;
416
417 if (rt2x00_is_pci(rt2x00dev)) {
418 if (rt2x00_rt(rt2x00dev, RT3572) ||
419 rt2x00_rt(rt2x00dev, RT5390) ||
420 rt2x00_rt(rt2x00dev, RT5392)) {
421 rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);
422 rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
423 rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
424 rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
425 }
426 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
427 }
428
429 rt2800_disable_wpdma(rt2x00dev);
430
431 /*
432 * Write firmware to the device.
433 */
434 rt2800_drv_write_firmware(rt2x00dev, data, len);
435
436 /*
437 * Wait for device to stabilize.
438 */
439 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
440 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
441 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
442 break;
443 msleep(1);
444 }
445
446 if (i == REGISTER_BUSY_COUNT) {
447 ERROR(rt2x00dev, "PBF system register not ready.\n");
448 return -EBUSY;
449 }
450
451 /*
452 * Disable DMA, will be reenabled later when enabling
453 * the radio.
454 */
455 rt2800_disable_wpdma(rt2x00dev);
456
457 /*
458 * Initialize firmware.
459 */
460 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
461 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
462 if (rt2x00_is_usb(rt2x00dev))
463 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
464 msleep(1);
465
466 return 0;
467 }
468 EXPORT_SYMBOL_GPL(rt2800_load_firmware);
469
470 void rt2800_write_tx_data(struct queue_entry *entry,
471 struct txentry_desc *txdesc)
472 {
473 __le32 *txwi = rt2800_drv_get_txwi(entry);
474 u32 word;
475
476 /*
477 * Initialize TX Info descriptor
478 */
479 rt2x00_desc_read(txwi, 0, &word);
480 rt2x00_set_field32(&word, TXWI_W0_FRAG,
481 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
482 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
483 test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
484 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
485 rt2x00_set_field32(&word, TXWI_W0_TS,
486 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
487 rt2x00_set_field32(&word, TXWI_W0_AMPDU,
488 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
489 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
490 txdesc->u.ht.mpdu_density);
491 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
492 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
493 rt2x00_set_field32(&word, TXWI_W0_BW,
494 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
495 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
496 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
497 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
498 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
499 rt2x00_desc_write(txwi, 0, word);
500
501 rt2x00_desc_read(txwi, 1, &word);
502 rt2x00_set_field32(&word, TXWI_W1_ACK,
503 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
504 rt2x00_set_field32(&word, TXWI_W1_NSEQ,
505 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
506 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
507 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
508 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
509 txdesc->key_idx : txdesc->u.ht.wcid);
510 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
511 txdesc->length);
512 rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
513 rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
514 rt2x00_desc_write(txwi, 1, word);
515
516 /*
517 * Always write 0 to IV/EIV fields, hardware will insert the IV
518 * from the IVEIV register when TXD_W3_WIV is set to 0.
519 * When TXD_W3_WIV is set to 1 it will use the IV data
520 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
521 * crypto entry in the registers should be used to encrypt the frame.
522 */
523 _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
524 _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
525 }
526 EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
527
528 static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
529 {
530 s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
531 s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
532 s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
533 u16 eeprom;
534 u8 offset0;
535 u8 offset1;
536 u8 offset2;
537
538 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
539 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
540 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
541 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
542 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
543 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
544 } else {
545 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
546 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
547 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
548 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
549 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
550 }
551
552 /*
553 * Convert the value from the descriptor into the RSSI value
554 * If the value in the descriptor is 0, it is considered invalid
555 * and the default (extremely low) rssi value is assumed
556 */
557 rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
558 rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
559 rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
560
561 /*
562 * mac80211 only accepts a single RSSI value. Calculating the
563 * average doesn't deliver a fair answer either since -60:-60 would
564 * be considered equally good as -50:-70 while the second is the one
565 * which gives less energy...
566 */
567 rssi0 = max(rssi0, rssi1);
568 return (int)max(rssi0, rssi2);
569 }
570
571 void rt2800_process_rxwi(struct queue_entry *entry,
572 struct rxdone_entry_desc *rxdesc)
573 {
574 __le32 *rxwi = (__le32 *) entry->skb->data;
575 u32 word;
576
577 rt2x00_desc_read(rxwi, 0, &word);
578
579 rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
580 rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
581
582 rt2x00_desc_read(rxwi, 1, &word);
583
584 if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
585 rxdesc->flags |= RX_FLAG_SHORT_GI;
586
587 if (rt2x00_get_field32(word, RXWI_W1_BW))
588 rxdesc->flags |= RX_FLAG_40MHZ;
589
590 /*
591 * Detect RX rate, always use MCS as signal type.
592 */
593 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
594 rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
595 rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
596
597 /*
598 * Mask of 0x8 bit to remove the short preamble flag.
599 */
600 if (rxdesc->rate_mode == RATE_MODE_CCK)
601 rxdesc->signal &= ~0x8;
602
603 rt2x00_desc_read(rxwi, 2, &word);
604
605 /*
606 * Convert descriptor AGC value to RSSI value.
607 */
608 rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
609
610 /*
611 * Remove RXWI descriptor from start of buffer.
612 */
613 skb_pull(entry->skb, RXWI_DESC_SIZE);
614 }
615 EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
616
617 void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi)
618 {
619 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
620 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
621 struct txdone_entry_desc txdesc;
622 u32 word;
623 u16 mcs, real_mcs;
624 int aggr, ampdu;
625
626 /*
627 * Obtain the status about this packet.
628 */
629 txdesc.flags = 0;
630 rt2x00_desc_read(txwi, 0, &word);
631
632 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
633 ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
634
635 real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
636 aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
637
638 /*
639 * If a frame was meant to be sent as a single non-aggregated MPDU
640 * but ended up in an aggregate the used tx rate doesn't correlate
641 * with the one specified in the TXWI as the whole aggregate is sent
642 * with the same rate.
643 *
644 * For example: two frames are sent to rt2x00, the first one sets
645 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
646 * and requests MCS15. If the hw aggregates both frames into one
647 * AMDPU the tx status for both frames will contain MCS7 although
648 * the frame was sent successfully.
649 *
650 * Hence, replace the requested rate with the real tx rate to not
651 * confuse the rate control algortihm by providing clearly wrong
652 * data.
653 */
654 if (unlikely(aggr == 1 && ampdu == 0 && real_mcs != mcs)) {
655 skbdesc->tx_rate_idx = real_mcs;
656 mcs = real_mcs;
657 }
658
659 if (aggr == 1 || ampdu == 1)
660 __set_bit(TXDONE_AMPDU, &txdesc.flags);
661
662 /*
663 * Ralink has a retry mechanism using a global fallback
664 * table. We setup this fallback table to try the immediate
665 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
666 * always contains the MCS used for the last transmission, be
667 * it successful or not.
668 */
669 if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
670 /*
671 * Transmission succeeded. The number of retries is
672 * mcs - real_mcs
673 */
674 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
675 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
676 } else {
677 /*
678 * Transmission failed. The number of retries is
679 * always 7 in this case (for a total number of 8
680 * frames sent).
681 */
682 __set_bit(TXDONE_FAILURE, &txdesc.flags);
683 txdesc.retry = rt2x00dev->long_retry;
684 }
685
686 /*
687 * the frame was retried at least once
688 * -> hw used fallback rates
689 */
690 if (txdesc.retry)
691 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
692
693 rt2x00lib_txdone(entry, &txdesc);
694 }
695 EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
696
697 void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
698 {
699 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
700 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
701 unsigned int beacon_base;
702 unsigned int padding_len;
703 u32 orig_reg, reg;
704
705 /*
706 * Disable beaconing while we are reloading the beacon data,
707 * otherwise we might be sending out invalid data.
708 */
709 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
710 orig_reg = reg;
711 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
712 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
713
714 /*
715 * Add space for the TXWI in front of the skb.
716 */
717 memset(skb_push(entry->skb, TXWI_DESC_SIZE), 0, TXWI_DESC_SIZE);
718
719 /*
720 * Register descriptor details in skb frame descriptor.
721 */
722 skbdesc->flags |= SKBDESC_DESC_IN_SKB;
723 skbdesc->desc = entry->skb->data;
724 skbdesc->desc_len = TXWI_DESC_SIZE;
725
726 /*
727 * Add the TXWI for the beacon to the skb.
728 */
729 rt2800_write_tx_data(entry, txdesc);
730
731 /*
732 * Dump beacon to userspace through debugfs.
733 */
734 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
735
736 /*
737 * Write entire beacon with TXWI and padding to register.
738 */
739 padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
740 if (padding_len && skb_pad(entry->skb, padding_len)) {
741 ERROR(rt2x00dev, "Failure padding beacon, aborting\n");
742 /* skb freed by skb_pad() on failure */
743 entry->skb = NULL;
744 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
745 return;
746 }
747
748 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
749 rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
750 entry->skb->len + padding_len);
751
752 /*
753 * Enable beaconing again.
754 */
755 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
756 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
757
758 /*
759 * Clean up beacon skb.
760 */
761 dev_kfree_skb_any(entry->skb);
762 entry->skb = NULL;
763 }
764 EXPORT_SYMBOL_GPL(rt2800_write_beacon);
765
766 static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
767 unsigned int beacon_base)
768 {
769 int i;
770
771 /*
772 * For the Beacon base registers we only need to clear
773 * the whole TXWI which (when set to 0) will invalidate
774 * the entire beacon.
775 */
776 for (i = 0; i < TXWI_DESC_SIZE; i += sizeof(__le32))
777 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
778 }
779
780 void rt2800_clear_beacon(struct queue_entry *entry)
781 {
782 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
783 u32 reg;
784
785 /*
786 * Disable beaconing while we are reloading the beacon data,
787 * otherwise we might be sending out invalid data.
788 */
789 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
790 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
791 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
792
793 /*
794 * Clear beacon.
795 */
796 rt2800_clear_beacon_register(rt2x00dev,
797 HW_BEACON_OFFSET(entry->entry_idx));
798
799 /*
800 * Enabled beaconing again.
801 */
802 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
803 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
804 }
805 EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
806
807 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
808 const struct rt2x00debug rt2800_rt2x00debug = {
809 .owner = THIS_MODULE,
810 .csr = {
811 .read = rt2800_register_read,
812 .write = rt2800_register_write,
813 .flags = RT2X00DEBUGFS_OFFSET,
814 .word_base = CSR_REG_BASE,
815 .word_size = sizeof(u32),
816 .word_count = CSR_REG_SIZE / sizeof(u32),
817 },
818 .eeprom = {
819 .read = rt2x00_eeprom_read,
820 .write = rt2x00_eeprom_write,
821 .word_base = EEPROM_BASE,
822 .word_size = sizeof(u16),
823 .word_count = EEPROM_SIZE / sizeof(u16),
824 },
825 .bbp = {
826 .read = rt2800_bbp_read,
827 .write = rt2800_bbp_write,
828 .word_base = BBP_BASE,
829 .word_size = sizeof(u8),
830 .word_count = BBP_SIZE / sizeof(u8),
831 },
832 .rf = {
833 .read = rt2x00_rf_read,
834 .write = rt2800_rf_write,
835 .word_base = RF_BASE,
836 .word_size = sizeof(u32),
837 .word_count = RF_SIZE / sizeof(u32),
838 },
839 };
840 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
841 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
842
843 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
844 {
845 u32 reg;
846
847 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
848 return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
849 }
850 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
851
852 #ifdef CONFIG_RT2X00_LIB_LEDS
853 static void rt2800_brightness_set(struct led_classdev *led_cdev,
854 enum led_brightness brightness)
855 {
856 struct rt2x00_led *led =
857 container_of(led_cdev, struct rt2x00_led, led_dev);
858 unsigned int enabled = brightness != LED_OFF;
859 unsigned int bg_mode =
860 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
861 unsigned int polarity =
862 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
863 EEPROM_FREQ_LED_POLARITY);
864 unsigned int ledmode =
865 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
866 EEPROM_FREQ_LED_MODE);
867 u32 reg;
868
869 /* Check for SoC (SOC devices don't support MCU requests) */
870 if (rt2x00_is_soc(led->rt2x00dev)) {
871 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
872
873 /* Set LED Polarity */
874 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, polarity);
875
876 /* Set LED Mode */
877 if (led->type == LED_TYPE_RADIO) {
878 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE,
879 enabled ? 3 : 0);
880 } else if (led->type == LED_TYPE_ASSOC) {
881 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE,
882 enabled ? 3 : 0);
883 } else if (led->type == LED_TYPE_QUALITY) {
884 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE,
885 enabled ? 3 : 0);
886 }
887
888 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
889
890 } else {
891 if (led->type == LED_TYPE_RADIO) {
892 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
893 enabled ? 0x20 : 0);
894 } else if (led->type == LED_TYPE_ASSOC) {
895 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
896 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
897 } else if (led->type == LED_TYPE_QUALITY) {
898 /*
899 * The brightness is divided into 6 levels (0 - 5),
900 * The specs tell us the following levels:
901 * 0, 1 ,3, 7, 15, 31
902 * to determine the level in a simple way we can simply
903 * work with bitshifting:
904 * (1 << level) - 1
905 */
906 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
907 (1 << brightness / (LED_FULL / 6)) - 1,
908 polarity);
909 }
910 }
911 }
912
913 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
914 struct rt2x00_led *led, enum led_type type)
915 {
916 led->rt2x00dev = rt2x00dev;
917 led->type = type;
918 led->led_dev.brightness_set = rt2800_brightness_set;
919 led->flags = LED_INITIALIZED;
920 }
921 #endif /* CONFIG_RT2X00_LIB_LEDS */
922
923 /*
924 * Configuration handlers.
925 */
926 static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev,
927 const u8 *address,
928 int wcid)
929 {
930 struct mac_wcid_entry wcid_entry;
931 u32 offset;
932
933 offset = MAC_WCID_ENTRY(wcid);
934
935 memset(&wcid_entry, 0xff, sizeof(wcid_entry));
936 if (address)
937 memcpy(wcid_entry.mac, address, ETH_ALEN);
938
939 rt2800_register_multiwrite(rt2x00dev, offset,
940 &wcid_entry, sizeof(wcid_entry));
941 }
942
943 static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid)
944 {
945 u32 offset;
946 offset = MAC_WCID_ATTR_ENTRY(wcid);
947 rt2800_register_write(rt2x00dev, offset, 0);
948 }
949
950 static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev,
951 int wcid, u32 bssidx)
952 {
953 u32 offset = MAC_WCID_ATTR_ENTRY(wcid);
954 u32 reg;
955
956 /*
957 * The BSS Idx numbers is split in a main value of 3 bits,
958 * and a extended field for adding one additional bit to the value.
959 */
960 rt2800_register_read(rt2x00dev, offset, &reg);
961 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7));
962 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
963 (bssidx & 0x8) >> 3);
964 rt2800_register_write(rt2x00dev, offset, reg);
965 }
966
967 static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev,
968 struct rt2x00lib_crypto *crypto,
969 struct ieee80211_key_conf *key)
970 {
971 struct mac_iveiv_entry iveiv_entry;
972 u32 offset;
973 u32 reg;
974
975 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
976
977 if (crypto->cmd == SET_KEY) {
978 rt2800_register_read(rt2x00dev, offset, &reg);
979 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
980 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
981 /*
982 * Both the cipher as the BSS Idx numbers are split in a main
983 * value of 3 bits, and a extended field for adding one additional
984 * bit to the value.
985 */
986 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
987 (crypto->cipher & 0x7));
988 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
989 (crypto->cipher & 0x8) >> 3);
990 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
991 rt2800_register_write(rt2x00dev, offset, reg);
992 } else {
993 /* Delete the cipher without touching the bssidx */
994 rt2800_register_read(rt2x00dev, offset, &reg);
995 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB, 0);
996 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER, 0);
997 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0);
998 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
999 rt2800_register_write(rt2x00dev, offset, reg);
1000 }
1001
1002 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
1003
1004 memset(&iveiv_entry, 0, sizeof(iveiv_entry));
1005 if ((crypto->cipher == CIPHER_TKIP) ||
1006 (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
1007 (crypto->cipher == CIPHER_AES))
1008 iveiv_entry.iv[3] |= 0x20;
1009 iveiv_entry.iv[3] |= key->keyidx << 6;
1010 rt2800_register_multiwrite(rt2x00dev, offset,
1011 &iveiv_entry, sizeof(iveiv_entry));
1012 }
1013
1014 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1015 struct rt2x00lib_crypto *crypto,
1016 struct ieee80211_key_conf *key)
1017 {
1018 struct hw_key_entry key_entry;
1019 struct rt2x00_field32 field;
1020 u32 offset;
1021 u32 reg;
1022
1023 if (crypto->cmd == SET_KEY) {
1024 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1025
1026 memcpy(key_entry.key, crypto->key,
1027 sizeof(key_entry.key));
1028 memcpy(key_entry.tx_mic, crypto->tx_mic,
1029 sizeof(key_entry.tx_mic));
1030 memcpy(key_entry.rx_mic, crypto->rx_mic,
1031 sizeof(key_entry.rx_mic));
1032
1033 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1034 rt2800_register_multiwrite(rt2x00dev, offset,
1035 &key_entry, sizeof(key_entry));
1036 }
1037
1038 /*
1039 * The cipher types are stored over multiple registers
1040 * starting with SHARED_KEY_MODE_BASE each word will have
1041 * 32 bits and contains the cipher types for 2 bssidx each.
1042 * Using the correct defines correctly will cause overhead,
1043 * so just calculate the correct offset.
1044 */
1045 field.bit_offset = 4 * (key->hw_key_idx % 8);
1046 field.bit_mask = 0x7 << field.bit_offset;
1047
1048 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1049
1050 rt2800_register_read(rt2x00dev, offset, &reg);
1051 rt2x00_set_field32(&reg, field,
1052 (crypto->cmd == SET_KEY) * crypto->cipher);
1053 rt2800_register_write(rt2x00dev, offset, reg);
1054
1055 /*
1056 * Update WCID information
1057 */
1058 rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx);
1059 rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx,
1060 crypto->bssidx);
1061 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1062
1063 return 0;
1064 }
1065 EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1066
1067 static inline int rt2800_find_wcid(struct rt2x00_dev *rt2x00dev)
1068 {
1069 struct mac_wcid_entry wcid_entry;
1070 int idx;
1071 u32 offset;
1072
1073 /*
1074 * Search for the first free WCID entry and return the corresponding
1075 * index.
1076 *
1077 * Make sure the WCID starts _after_ the last possible shared key
1078 * entry (>32).
1079 *
1080 * Since parts of the pairwise key table might be shared with
1081 * the beacon frame buffers 6 & 7 we should only write into the
1082 * first 222 entries.
1083 */
1084 for (idx = 33; idx <= 222; idx++) {
1085 offset = MAC_WCID_ENTRY(idx);
1086 rt2800_register_multiread(rt2x00dev, offset, &wcid_entry,
1087 sizeof(wcid_entry));
1088 if (is_broadcast_ether_addr(wcid_entry.mac))
1089 return idx;
1090 }
1091
1092 /*
1093 * Use -1 to indicate that we don't have any more space in the WCID
1094 * table.
1095 */
1096 return -1;
1097 }
1098
1099 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1100 struct rt2x00lib_crypto *crypto,
1101 struct ieee80211_key_conf *key)
1102 {
1103 struct hw_key_entry key_entry;
1104 u32 offset;
1105
1106 if (crypto->cmd == SET_KEY) {
1107 /*
1108 * Allow key configuration only for STAs that are
1109 * known by the hw.
1110 */
1111 if (crypto->wcid < 0)
1112 return -ENOSPC;
1113 key->hw_key_idx = crypto->wcid;
1114
1115 memcpy(key_entry.key, crypto->key,
1116 sizeof(key_entry.key));
1117 memcpy(key_entry.tx_mic, crypto->tx_mic,
1118 sizeof(key_entry.tx_mic));
1119 memcpy(key_entry.rx_mic, crypto->rx_mic,
1120 sizeof(key_entry.rx_mic));
1121
1122 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1123 rt2800_register_multiwrite(rt2x00dev, offset,
1124 &key_entry, sizeof(key_entry));
1125 }
1126
1127 /*
1128 * Update WCID information
1129 */
1130 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1131
1132 return 0;
1133 }
1134 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1135
1136 int rt2800_sta_add(struct rt2x00_dev *rt2x00dev, struct ieee80211_vif *vif,
1137 struct ieee80211_sta *sta)
1138 {
1139 int wcid;
1140 struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
1141
1142 /*
1143 * Find next free WCID.
1144 */
1145 wcid = rt2800_find_wcid(rt2x00dev);
1146
1147 /*
1148 * Store selected wcid even if it is invalid so that we can
1149 * later decide if the STA is uploaded into the hw.
1150 */
1151 sta_priv->wcid = wcid;
1152
1153 /*
1154 * No space left in the device, however, we can still communicate
1155 * with the STA -> No error.
1156 */
1157 if (wcid < 0)
1158 return 0;
1159
1160 /*
1161 * Clean up WCID attributes and write STA address to the device.
1162 */
1163 rt2800_delete_wcid_attr(rt2x00dev, wcid);
1164 rt2800_config_wcid(rt2x00dev, sta->addr, wcid);
1165 rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid,
1166 rt2x00lib_get_bssidx(rt2x00dev, vif));
1167 return 0;
1168 }
1169 EXPORT_SYMBOL_GPL(rt2800_sta_add);
1170
1171 int rt2800_sta_remove(struct rt2x00_dev *rt2x00dev, int wcid)
1172 {
1173 /*
1174 * Remove WCID entry, no need to clean the attributes as they will
1175 * get renewed when the WCID is reused.
1176 */
1177 rt2800_config_wcid(rt2x00dev, NULL, wcid);
1178
1179 return 0;
1180 }
1181 EXPORT_SYMBOL_GPL(rt2800_sta_remove);
1182
1183 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1184 const unsigned int filter_flags)
1185 {
1186 u32 reg;
1187
1188 /*
1189 * Start configuration steps.
1190 * Note that the version error will always be dropped
1191 * and broadcast frames will always be accepted since
1192 * there is no filter for it at this time.
1193 */
1194 rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
1195 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1196 !(filter_flags & FIF_FCSFAIL));
1197 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1198 !(filter_flags & FIF_PLCPFAIL));
1199 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1200 !(filter_flags & FIF_PROMISC_IN_BSS));
1201 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1202 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1203 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1204 !(filter_flags & FIF_ALLMULTI));
1205 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1206 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1207 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1208 !(filter_flags & FIF_CONTROL));
1209 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1210 !(filter_flags & FIF_CONTROL));
1211 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1212 !(filter_flags & FIF_CONTROL));
1213 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1214 !(filter_flags & FIF_CONTROL));
1215 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1216 !(filter_flags & FIF_CONTROL));
1217 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1218 !(filter_flags & FIF_PSPOLL));
1219 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA,
1220 !(filter_flags & FIF_CONTROL));
1221 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR,
1222 !(filter_flags & FIF_CONTROL));
1223 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1224 !(filter_flags & FIF_CONTROL));
1225 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1226 }
1227 EXPORT_SYMBOL_GPL(rt2800_config_filter);
1228
1229 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1230 struct rt2x00intf_conf *conf, const unsigned int flags)
1231 {
1232 u32 reg;
1233 bool update_bssid = false;
1234
1235 if (flags & CONFIG_UPDATE_TYPE) {
1236 /*
1237 * Enable synchronisation.
1238 */
1239 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1240 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
1241 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1242
1243 if (conf->sync == TSF_SYNC_AP_NONE) {
1244 /*
1245 * Tune beacon queue transmit parameters for AP mode
1246 */
1247 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1248 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 0);
1249 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 1);
1250 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1251 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 0);
1252 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1253 } else {
1254 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1255 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 4);
1256 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 2);
1257 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1258 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 16);
1259 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1260 }
1261 }
1262
1263 if (flags & CONFIG_UPDATE_MAC) {
1264 if (flags & CONFIG_UPDATE_TYPE &&
1265 conf->sync == TSF_SYNC_AP_NONE) {
1266 /*
1267 * The BSSID register has to be set to our own mac
1268 * address in AP mode.
1269 */
1270 memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1271 update_bssid = true;
1272 }
1273
1274 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1275 reg = le32_to_cpu(conf->mac[1]);
1276 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1277 conf->mac[1] = cpu_to_le32(reg);
1278 }
1279
1280 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1281 conf->mac, sizeof(conf->mac));
1282 }
1283
1284 if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
1285 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1286 reg = le32_to_cpu(conf->bssid[1]);
1287 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1288 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
1289 conf->bssid[1] = cpu_to_le32(reg);
1290 }
1291
1292 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1293 conf->bssid, sizeof(conf->bssid));
1294 }
1295 }
1296 EXPORT_SYMBOL_GPL(rt2800_config_intf);
1297
1298 static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1299 struct rt2x00lib_erp *erp)
1300 {
1301 bool any_sta_nongf = !!(erp->ht_opmode &
1302 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1303 u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1304 u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1305 u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1306 u32 reg;
1307
1308 /* default protection rate for HT20: OFDM 24M */
1309 mm20_rate = gf20_rate = 0x4004;
1310
1311 /* default protection rate for HT40: duplicate OFDM 24M */
1312 mm40_rate = gf40_rate = 0x4084;
1313
1314 switch (protection) {
1315 case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1316 /*
1317 * All STAs in this BSS are HT20/40 but there might be
1318 * STAs not supporting greenfield mode.
1319 * => Disable protection for HT transmissions.
1320 */
1321 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1322
1323 break;
1324 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1325 /*
1326 * All STAs in this BSS are HT20 or HT20/40 but there
1327 * might be STAs not supporting greenfield mode.
1328 * => Protect all HT40 transmissions.
1329 */
1330 mm20_mode = gf20_mode = 0;
1331 mm40_mode = gf40_mode = 2;
1332
1333 break;
1334 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1335 /*
1336 * Nonmember protection:
1337 * According to 802.11n we _should_ protect all
1338 * HT transmissions (but we don't have to).
1339 *
1340 * But if cts_protection is enabled we _shall_ protect
1341 * all HT transmissions using a CCK rate.
1342 *
1343 * And if any station is non GF we _shall_ protect
1344 * GF transmissions.
1345 *
1346 * We decide to protect everything
1347 * -> fall through to mixed mode.
1348 */
1349 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1350 /*
1351 * Legacy STAs are present
1352 * => Protect all HT transmissions.
1353 */
1354 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2;
1355
1356 /*
1357 * If erp protection is needed we have to protect HT
1358 * transmissions with CCK 11M long preamble.
1359 */
1360 if (erp->cts_protection) {
1361 /* don't duplicate RTS/CTS in CCK mode */
1362 mm20_rate = mm40_rate = 0x0003;
1363 gf20_rate = gf40_rate = 0x0003;
1364 }
1365 break;
1366 }
1367
1368 /* check for STAs not supporting greenfield mode */
1369 if (any_sta_nongf)
1370 gf20_mode = gf40_mode = 2;
1371
1372 /* Update HT protection config */
1373 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1374 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1375 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1376 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1377
1378 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1379 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1380 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1381 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1382
1383 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1384 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1385 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1386 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1387
1388 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1389 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1390 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1391 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1392 }
1393
1394 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1395 u32 changed)
1396 {
1397 u32 reg;
1398
1399 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1400 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1401 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
1402 !!erp->short_preamble);
1403 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1404 !!erp->short_preamble);
1405 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1406 }
1407
1408 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1409 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1410 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1411 erp->cts_protection ? 2 : 0);
1412 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1413 }
1414
1415 if (changed & BSS_CHANGED_BASIC_RATES) {
1416 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1417 erp->basic_rates);
1418 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1419 }
1420
1421 if (changed & BSS_CHANGED_ERP_SLOT) {
1422 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1423 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
1424 erp->slot_time);
1425 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1426
1427 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1428 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1429 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1430 }
1431
1432 if (changed & BSS_CHANGED_BEACON_INT) {
1433 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1434 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1435 erp->beacon_int * 16);
1436 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1437 }
1438
1439 if (changed & BSS_CHANGED_HT)
1440 rt2800_config_ht_opmode(rt2x00dev, erp);
1441 }
1442 EXPORT_SYMBOL_GPL(rt2800_config_erp);
1443
1444 static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev)
1445 {
1446 u32 reg;
1447 u16 eeprom;
1448 u8 led_ctrl, led_g_mode, led_r_mode;
1449
1450 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
1451 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
1452 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 1);
1453 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 1);
1454 } else {
1455 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 0);
1456 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 0);
1457 }
1458 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
1459
1460 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1461 led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0;
1462 led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3;
1463 if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) ||
1464 led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) {
1465 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1466 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE);
1467 if (led_ctrl == 0 || led_ctrl > 0x40) {
1468 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, led_g_mode);
1469 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, led_r_mode);
1470 rt2800_register_write(rt2x00dev, LED_CFG, reg);
1471 } else {
1472 rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff,
1473 (led_g_mode << 2) | led_r_mode, 1);
1474 }
1475 }
1476 }
1477
1478 static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
1479 enum antenna ant)
1480 {
1481 u32 reg;
1482 u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
1483 u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
1484
1485 if (rt2x00_is_pci(rt2x00dev)) {
1486 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
1487 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
1488 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
1489 } else if (rt2x00_is_usb(rt2x00dev))
1490 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
1491 eesk_pin, 0);
1492
1493 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
1494 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT3, 0);
1495 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, gpio_bit3);
1496 rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
1497 }
1498
1499 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1500 {
1501 u8 r1;
1502 u8 r3;
1503 u16 eeprom;
1504
1505 rt2800_bbp_read(rt2x00dev, 1, &r1);
1506 rt2800_bbp_read(rt2x00dev, 3, &r3);
1507
1508 if (rt2x00_rt(rt2x00dev, RT3572) &&
1509 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1510 rt2800_config_3572bt_ant(rt2x00dev);
1511
1512 /*
1513 * Configure the TX antenna.
1514 */
1515 switch (ant->tx_chain_num) {
1516 case 1:
1517 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1518 break;
1519 case 2:
1520 if (rt2x00_rt(rt2x00dev, RT3572) &&
1521 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1522 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1);
1523 else
1524 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1525 break;
1526 case 3:
1527 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1528 break;
1529 }
1530
1531 /*
1532 * Configure the RX antenna.
1533 */
1534 switch (ant->rx_chain_num) {
1535 case 1:
1536 if (rt2x00_rt(rt2x00dev, RT3070) ||
1537 rt2x00_rt(rt2x00dev, RT3090) ||
1538 rt2x00_rt(rt2x00dev, RT3390)) {
1539 rt2x00_eeprom_read(rt2x00dev,
1540 EEPROM_NIC_CONF1, &eeprom);
1541 if (rt2x00_get_field16(eeprom,
1542 EEPROM_NIC_CONF1_ANT_DIVERSITY))
1543 rt2800_set_ant_diversity(rt2x00dev,
1544 rt2x00dev->default_ant.rx);
1545 }
1546 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1547 break;
1548 case 2:
1549 if (rt2x00_rt(rt2x00dev, RT3572) &&
1550 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1551 rt2x00_set_field8(&r3, BBP3_RX_ADC, 1);
1552 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA,
1553 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
1554 rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B);
1555 } else {
1556 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1557 }
1558 break;
1559 case 3:
1560 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1561 break;
1562 }
1563
1564 rt2800_bbp_write(rt2x00dev, 3, r3);
1565 rt2800_bbp_write(rt2x00dev, 1, r1);
1566 }
1567 EXPORT_SYMBOL_GPL(rt2800_config_ant);
1568
1569 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1570 struct rt2x00lib_conf *libconf)
1571 {
1572 u16 eeprom;
1573 short lna_gain;
1574
1575 if (libconf->rf.channel <= 14) {
1576 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1577 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1578 } else if (libconf->rf.channel <= 64) {
1579 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1580 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1581 } else if (libconf->rf.channel <= 128) {
1582 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1583 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
1584 } else {
1585 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1586 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
1587 }
1588
1589 rt2x00dev->lna_gain = lna_gain;
1590 }
1591
1592 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1593 struct ieee80211_conf *conf,
1594 struct rf_channel *rf,
1595 struct channel_info *info)
1596 {
1597 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1598
1599 if (rt2x00dev->default_ant.tx_chain_num == 1)
1600 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1601
1602 if (rt2x00dev->default_ant.rx_chain_num == 1) {
1603 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1604 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1605 } else if (rt2x00dev->default_ant.rx_chain_num == 2)
1606 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1607
1608 if (rf->channel > 14) {
1609 /*
1610 * When TX power is below 0, we should increase it by 7 to
1611 * make it a positive value (Minimum value is -7).
1612 * However this means that values between 0 and 7 have
1613 * double meaning, and we should set a 7DBm boost flag.
1614 */
1615 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
1616 (info->default_power1 >= 0));
1617
1618 if (info->default_power1 < 0)
1619 info->default_power1 += 7;
1620
1621 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
1622
1623 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
1624 (info->default_power2 >= 0));
1625
1626 if (info->default_power2 < 0)
1627 info->default_power2 += 7;
1628
1629 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
1630 } else {
1631 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
1632 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
1633 }
1634
1635 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1636
1637 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1638 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1639 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1640 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1641
1642 udelay(200);
1643
1644 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1645 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1646 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1647 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1648
1649 udelay(200);
1650
1651 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1652 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1653 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1654 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1655 }
1656
1657 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1658 struct ieee80211_conf *conf,
1659 struct rf_channel *rf,
1660 struct channel_info *info)
1661 {
1662 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1663 u8 rfcsr, calib_tx, calib_rx;
1664
1665 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1666
1667 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
1668 rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3);
1669 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
1670
1671 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1672 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
1673 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1674
1675 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1676 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
1677 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1678
1679 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1680 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
1681 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1682
1683 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1684 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
1685 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
1686 if (rt2x00_rt(rt2x00dev, RT3390)) {
1687 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
1688 rt2x00dev->default_ant.rx_chain_num == 1);
1689 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
1690 rt2x00dev->default_ant.tx_chain_num == 1);
1691 } else {
1692 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
1693 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
1694 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
1695 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
1696
1697 switch (rt2x00dev->default_ant.tx_chain_num) {
1698 case 1:
1699 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
1700 /* fall through */
1701 case 2:
1702 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1703 break;
1704 }
1705
1706 switch (rt2x00dev->default_ant.rx_chain_num) {
1707 case 1:
1708 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
1709 /* fall through */
1710 case 2:
1711 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1712 break;
1713 }
1714 }
1715 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1716
1717 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1718 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1719 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1720 msleep(1);
1721 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1722 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1723
1724 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1725 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1726 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1727
1728 if (rt2x00_rt(rt2x00dev, RT3390)) {
1729 calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f;
1730 calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f;
1731 } else {
1732 if (conf_is_ht40(conf)) {
1733 calib_tx = drv_data->calibration_bw40;
1734 calib_rx = drv_data->calibration_bw40;
1735 } else {
1736 calib_tx = drv_data->calibration_bw20;
1737 calib_rx = drv_data->calibration_bw20;
1738 }
1739 }
1740
1741 rt2800_rfcsr_read(rt2x00dev, 24, &rfcsr);
1742 rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx);
1743 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr);
1744
1745 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
1746 rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx);
1747 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
1748
1749 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1750 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
1751 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1752
1753 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1754 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1755 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1756 msleep(1);
1757 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1758 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1759 }
1760
1761 static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
1762 struct ieee80211_conf *conf,
1763 struct rf_channel *rf,
1764 struct channel_info *info)
1765 {
1766 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1767 u8 rfcsr;
1768 u32 reg;
1769
1770 if (rf->channel <= 14) {
1771 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
1772 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
1773 } else {
1774 rt2800_bbp_write(rt2x00dev, 25, 0x09);
1775 rt2800_bbp_write(rt2x00dev, 26, 0xff);
1776 }
1777
1778 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1779 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
1780
1781 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1782 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
1783 if (rf->channel <= 14)
1784 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2);
1785 else
1786 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1);
1787 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1788
1789 rt2800_rfcsr_read(rt2x00dev, 5, &rfcsr);
1790 if (rf->channel <= 14)
1791 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1);
1792 else
1793 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2);
1794 rt2800_rfcsr_write(rt2x00dev, 5, rfcsr);
1795
1796 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1797 if (rf->channel <= 14) {
1798 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3);
1799 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
1800 info->default_power1);
1801 } else {
1802 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7);
1803 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
1804 (info->default_power1 & 0x3) |
1805 ((info->default_power1 & 0xC) << 1));
1806 }
1807 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1808
1809 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1810 if (rf->channel <= 14) {
1811 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3);
1812 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
1813 info->default_power2);
1814 } else {
1815 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7);
1816 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
1817 (info->default_power2 & 0x3) |
1818 ((info->default_power2 & 0xC) << 1));
1819 }
1820 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1821
1822 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1823 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
1824 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
1825 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
1826 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
1827 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
1828 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
1829 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1830 if (rf->channel <= 14) {
1831 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
1832 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
1833 }
1834 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1835 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1836 } else {
1837 switch (rt2x00dev->default_ant.tx_chain_num) {
1838 case 1:
1839 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
1840 case 2:
1841 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1842 break;
1843 }
1844
1845 switch (rt2x00dev->default_ant.rx_chain_num) {
1846 case 1:
1847 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
1848 case 2:
1849 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1850 break;
1851 }
1852 }
1853 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1854
1855 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1856 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1857 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1858
1859 if (conf_is_ht40(conf)) {
1860 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40);
1861 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40);
1862 } else {
1863 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20);
1864 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20);
1865 }
1866
1867 if (rf->channel <= 14) {
1868 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
1869 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
1870 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
1871 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
1872 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
1873 rfcsr = 0x4c;
1874 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
1875 drv_data->txmixer_gain_24g);
1876 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
1877 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
1878 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
1879 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
1880 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
1881 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
1882 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
1883 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
1884 } else {
1885 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1886 rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1);
1887 rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0);
1888 rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1);
1889 rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0);
1890 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1891 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
1892 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
1893 rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
1894 rt2800_rfcsr_write(rt2x00dev, 15, 0x43);
1895 rfcsr = 0x7a;
1896 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
1897 drv_data->txmixer_gain_5g);
1898 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
1899 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
1900 if (rf->channel <= 64) {
1901 rt2800_rfcsr_write(rt2x00dev, 19, 0xb7);
1902 rt2800_rfcsr_write(rt2x00dev, 20, 0xf6);
1903 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
1904 } else if (rf->channel <= 128) {
1905 rt2800_rfcsr_write(rt2x00dev, 19, 0x74);
1906 rt2800_rfcsr_write(rt2x00dev, 20, 0xf4);
1907 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1908 } else {
1909 rt2800_rfcsr_write(rt2x00dev, 19, 0x72);
1910 rt2800_rfcsr_write(rt2x00dev, 20, 0xf3);
1911 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1912 }
1913 rt2800_rfcsr_write(rt2x00dev, 26, 0x87);
1914 rt2800_rfcsr_write(rt2x00dev, 27, 0x01);
1915 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f);
1916 }
1917
1918 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
1919 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT7, 0);
1920 if (rf->channel <= 14)
1921 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT7, 1);
1922 else
1923 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT7, 0);
1924 rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
1925
1926 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1927 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
1928 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1929 }
1930
1931 #define RT5390_POWER_BOUND 0x27
1932 #define RT5390_FREQ_OFFSET_BOUND 0x5f
1933
1934 static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
1935 struct ieee80211_conf *conf,
1936 struct rf_channel *rf,
1937 struct channel_info *info)
1938 {
1939 u8 rfcsr;
1940
1941 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
1942 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
1943 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
1944 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
1945 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
1946
1947 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
1948 if (info->default_power1 > RT5390_POWER_BOUND)
1949 rt2x00_set_field8(&rfcsr, RFCSR49_TX, RT5390_POWER_BOUND);
1950 else
1951 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
1952 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
1953
1954 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1955 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
1956 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
1957 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
1958 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
1959 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1960
1961 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
1962 if (rt2x00dev->freq_offset > RT5390_FREQ_OFFSET_BOUND)
1963 rt2x00_set_field8(&rfcsr, RFCSR17_CODE,
1964 RT5390_FREQ_OFFSET_BOUND);
1965 else
1966 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
1967 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
1968
1969 if (rf->channel <= 14) {
1970 int idx = rf->channel-1;
1971
1972 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1973 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
1974 /* r55/r59 value array of channel 1~14 */
1975 static const char r55_bt_rev[] = {0x83, 0x83,
1976 0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
1977 0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
1978 static const char r59_bt_rev[] = {0x0e, 0x0e,
1979 0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
1980 0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
1981
1982 rt2800_rfcsr_write(rt2x00dev, 55,
1983 r55_bt_rev[idx]);
1984 rt2800_rfcsr_write(rt2x00dev, 59,
1985 r59_bt_rev[idx]);
1986 } else {
1987 static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
1988 0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
1989 0x88, 0x88, 0x86, 0x85, 0x84};
1990
1991 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
1992 }
1993 } else {
1994 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
1995 static const char r55_nonbt_rev[] = {0x23, 0x23,
1996 0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
1997 0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
1998 static const char r59_nonbt_rev[] = {0x07, 0x07,
1999 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
2000 0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
2001
2002 rt2800_rfcsr_write(rt2x00dev, 55,
2003 r55_nonbt_rev[idx]);
2004 rt2800_rfcsr_write(rt2x00dev, 59,
2005 r59_nonbt_rev[idx]);
2006 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
2007 rt2x00_rt(rt2x00dev, RT5392)) {
2008 static const char r59_non_bt[] = {0x8f, 0x8f,
2009 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
2010 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
2011
2012 rt2800_rfcsr_write(rt2x00dev, 59,
2013 r59_non_bt[idx]);
2014 }
2015 }
2016 }
2017
2018 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2019 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0);
2020 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0);
2021 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2022
2023 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2024 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2025 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2026 }
2027
2028 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
2029 struct ieee80211_conf *conf,
2030 struct rf_channel *rf,
2031 struct channel_info *info)
2032 {
2033 u32 reg;
2034 unsigned int tx_pin;
2035 u8 bbp;
2036
2037 if (rf->channel <= 14) {
2038 info->default_power1 = TXPOWER_G_TO_DEV(info->default_power1);
2039 info->default_power2 = TXPOWER_G_TO_DEV(info->default_power2);
2040 } else {
2041 info->default_power1 = TXPOWER_A_TO_DEV(info->default_power1);
2042 info->default_power2 = TXPOWER_A_TO_DEV(info->default_power2);
2043 }
2044
2045 switch (rt2x00dev->chip.rf) {
2046 case RF2020:
2047 case RF3020:
2048 case RF3021:
2049 case RF3022:
2050 case RF3320:
2051 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
2052 break;
2053 case RF3052:
2054 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);
2055 break;
2056 case RF5370:
2057 case RF5372:
2058 case RF5390:
2059 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
2060 break;
2061 default:
2062 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
2063 }
2064
2065 /*
2066 * Change BBP settings
2067 */
2068 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
2069 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
2070 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
2071 rt2800_bbp_write(rt2x00dev, 86, 0);
2072
2073 if (rf->channel <= 14) {
2074 if (!rt2x00_rt(rt2x00dev, RT5390) &&
2075 !rt2x00_rt(rt2x00dev, RT5392)) {
2076 if (test_bit(CAPABILITY_EXTERNAL_LNA_BG,
2077 &rt2x00dev->cap_flags)) {
2078 rt2800_bbp_write(rt2x00dev, 82, 0x62);
2079 rt2800_bbp_write(rt2x00dev, 75, 0x46);
2080 } else {
2081 rt2800_bbp_write(rt2x00dev, 82, 0x84);
2082 rt2800_bbp_write(rt2x00dev, 75, 0x50);
2083 }
2084 }
2085 } else {
2086 if (rt2x00_rt(rt2x00dev, RT3572))
2087 rt2800_bbp_write(rt2x00dev, 82, 0x94);
2088 else
2089 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
2090
2091 if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags))
2092 rt2800_bbp_write(rt2x00dev, 75, 0x46);
2093 else
2094 rt2800_bbp_write(rt2x00dev, 75, 0x50);
2095 }
2096
2097 rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
2098 rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
2099 rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
2100 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
2101 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
2102
2103 if (rt2x00_rt(rt2x00dev, RT3572))
2104 rt2800_rfcsr_write(rt2x00dev, 8, 0);
2105
2106 tx_pin = 0;
2107
2108 /* Turn on unused PA or LNA when not using 1T or 1R */
2109 if (rt2x00dev->default_ant.tx_chain_num == 2) {
2110 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN,
2111 rf->channel > 14);
2112 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN,
2113 rf->channel <= 14);
2114 }
2115
2116 /* Turn on unused PA or LNA when not using 1T or 1R */
2117 if (rt2x00dev->default_ant.rx_chain_num == 2) {
2118 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
2119 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
2120 }
2121
2122 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
2123 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
2124 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
2125 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
2126 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
2127 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
2128 else
2129 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN,
2130 rf->channel <= 14);
2131 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
2132
2133 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
2134
2135 if (rt2x00_rt(rt2x00dev, RT3572))
2136 rt2800_rfcsr_write(rt2x00dev, 8, 0x80);
2137
2138 rt2800_bbp_read(rt2x00dev, 4, &bbp);
2139 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
2140 rt2800_bbp_write(rt2x00dev, 4, bbp);
2141
2142 rt2800_bbp_read(rt2x00dev, 3, &bbp);
2143 rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
2144 rt2800_bbp_write(rt2x00dev, 3, bbp);
2145
2146 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
2147 if (conf_is_ht40(conf)) {
2148 rt2800_bbp_write(rt2x00dev, 69, 0x1a);
2149 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
2150 rt2800_bbp_write(rt2x00dev, 73, 0x16);
2151 } else {
2152 rt2800_bbp_write(rt2x00dev, 69, 0x16);
2153 rt2800_bbp_write(rt2x00dev, 70, 0x08);
2154 rt2800_bbp_write(rt2x00dev, 73, 0x11);
2155 }
2156 }
2157
2158 msleep(1);
2159
2160 /*
2161 * Clear channel statistic counters
2162 */
2163 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg);
2164 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg);
2165 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
2166 }
2167
2168 static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
2169 {
2170 u8 tssi_bounds[9];
2171 u8 current_tssi;
2172 u16 eeprom;
2173 u8 step;
2174 int i;
2175
2176 /*
2177 * Read TSSI boundaries for temperature compensation from
2178 * the EEPROM.
2179 *
2180 * Array idx 0 1 2 3 4 5 6 7 8
2181 * Matching Delta value -4 -3 -2 -1 0 +1 +2 +3 +4
2182 * Example TSSI bounds 0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
2183 */
2184 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
2185 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1, &eeprom);
2186 tssi_bounds[0] = rt2x00_get_field16(eeprom,
2187 EEPROM_TSSI_BOUND_BG1_MINUS4);
2188 tssi_bounds[1] = rt2x00_get_field16(eeprom,
2189 EEPROM_TSSI_BOUND_BG1_MINUS3);
2190
2191 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2, &eeprom);
2192 tssi_bounds[2] = rt2x00_get_field16(eeprom,
2193 EEPROM_TSSI_BOUND_BG2_MINUS2);
2194 tssi_bounds[3] = rt2x00_get_field16(eeprom,
2195 EEPROM_TSSI_BOUND_BG2_MINUS1);
2196
2197 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3, &eeprom);
2198 tssi_bounds[4] = rt2x00_get_field16(eeprom,
2199 EEPROM_TSSI_BOUND_BG3_REF);
2200 tssi_bounds[5] = rt2x00_get_field16(eeprom,
2201 EEPROM_TSSI_BOUND_BG3_PLUS1);
2202
2203 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4, &eeprom);
2204 tssi_bounds[6] = rt2x00_get_field16(eeprom,
2205 EEPROM_TSSI_BOUND_BG4_PLUS2);
2206 tssi_bounds[7] = rt2x00_get_field16(eeprom,
2207 EEPROM_TSSI_BOUND_BG4_PLUS3);
2208
2209 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5, &eeprom);
2210 tssi_bounds[8] = rt2x00_get_field16(eeprom,
2211 EEPROM_TSSI_BOUND_BG5_PLUS4);
2212
2213 step = rt2x00_get_field16(eeprom,
2214 EEPROM_TSSI_BOUND_BG5_AGC_STEP);
2215 } else {
2216 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1, &eeprom);
2217 tssi_bounds[0] = rt2x00_get_field16(eeprom,
2218 EEPROM_TSSI_BOUND_A1_MINUS4);
2219 tssi_bounds[1] = rt2x00_get_field16(eeprom,
2220 EEPROM_TSSI_BOUND_A1_MINUS3);
2221
2222 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2, &eeprom);
2223 tssi_bounds[2] = rt2x00_get_field16(eeprom,
2224 EEPROM_TSSI_BOUND_A2_MINUS2);
2225 tssi_bounds[3] = rt2x00_get_field16(eeprom,
2226 EEPROM_TSSI_BOUND_A2_MINUS1);
2227
2228 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3, &eeprom);
2229 tssi_bounds[4] = rt2x00_get_field16(eeprom,
2230 EEPROM_TSSI_BOUND_A3_REF);
2231 tssi_bounds[5] = rt2x00_get_field16(eeprom,
2232 EEPROM_TSSI_BOUND_A3_PLUS1);
2233
2234 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4, &eeprom);
2235 tssi_bounds[6] = rt2x00_get_field16(eeprom,
2236 EEPROM_TSSI_BOUND_A4_PLUS2);
2237 tssi_bounds[7] = rt2x00_get_field16(eeprom,
2238 EEPROM_TSSI_BOUND_A4_PLUS3);
2239
2240 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5, &eeprom);
2241 tssi_bounds[8] = rt2x00_get_field16(eeprom,
2242 EEPROM_TSSI_BOUND_A5_PLUS4);
2243
2244 step = rt2x00_get_field16(eeprom,
2245 EEPROM_TSSI_BOUND_A5_AGC_STEP);
2246 }
2247
2248 /*
2249 * Check if temperature compensation is supported.
2250 */
2251 if (tssi_bounds[4] == 0xff)
2252 return 0;
2253
2254 /*
2255 * Read current TSSI (BBP 49).
2256 */
2257 rt2800_bbp_read(rt2x00dev, 49, &current_tssi);
2258
2259 /*
2260 * Compare TSSI value (BBP49) with the compensation boundaries
2261 * from the EEPROM and increase or decrease tx power.
2262 */
2263 for (i = 0; i <= 3; i++) {
2264 if (current_tssi > tssi_bounds[i])
2265 break;
2266 }
2267
2268 if (i == 4) {
2269 for (i = 8; i >= 5; i--) {
2270 if (current_tssi < tssi_bounds[i])
2271 break;
2272 }
2273 }
2274
2275 return (i - 4) * step;
2276 }
2277
2278 static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
2279 enum ieee80211_band band)
2280 {
2281 u16 eeprom;
2282 u8 comp_en;
2283 u8 comp_type;
2284 int comp_value = 0;
2285
2286 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom);
2287
2288 /*
2289 * HT40 compensation not required.
2290 */
2291 if (eeprom == 0xffff ||
2292 !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
2293 return 0;
2294
2295 if (band == IEEE80211_BAND_2GHZ) {
2296 comp_en = rt2x00_get_field16(eeprom,
2297 EEPROM_TXPOWER_DELTA_ENABLE_2G);
2298 if (comp_en) {
2299 comp_type = rt2x00_get_field16(eeprom,
2300 EEPROM_TXPOWER_DELTA_TYPE_2G);
2301 comp_value = rt2x00_get_field16(eeprom,
2302 EEPROM_TXPOWER_DELTA_VALUE_2G);
2303 if (!comp_type)
2304 comp_value = -comp_value;
2305 }
2306 } else {
2307 comp_en = rt2x00_get_field16(eeprom,
2308 EEPROM_TXPOWER_DELTA_ENABLE_5G);
2309 if (comp_en) {
2310 comp_type = rt2x00_get_field16(eeprom,
2311 EEPROM_TXPOWER_DELTA_TYPE_5G);
2312 comp_value = rt2x00_get_field16(eeprom,
2313 EEPROM_TXPOWER_DELTA_VALUE_5G);
2314 if (!comp_type)
2315 comp_value = -comp_value;
2316 }
2317 }
2318
2319 return comp_value;
2320 }
2321
2322 static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
2323 enum ieee80211_band band, int power_level,
2324 u8 txpower, int delta)
2325 {
2326 u32 reg;
2327 u16 eeprom;
2328 u8 criterion;
2329 u8 eirp_txpower;
2330 u8 eirp_txpower_criterion;
2331 u8 reg_limit;
2332
2333 if (!((band == IEEE80211_BAND_5GHZ) && is_rate_b))
2334 return txpower;
2335
2336 if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags)) {
2337 /*
2338 * Check if eirp txpower exceed txpower_limit.
2339 * We use OFDM 6M as criterion and its eirp txpower
2340 * is stored at EEPROM_EIRP_MAX_TX_POWER.
2341 * .11b data rate need add additional 4dbm
2342 * when calculating eirp txpower.
2343 */
2344 rt2800_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
2345 criterion = rt2x00_get_field32(reg, TX_PWR_CFG_0_6MBS);
2346
2347 rt2x00_eeprom_read(rt2x00dev,
2348 EEPROM_EIRP_MAX_TX_POWER, &eeprom);
2349
2350 if (band == IEEE80211_BAND_2GHZ)
2351 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
2352 EEPROM_EIRP_MAX_TX_POWER_2GHZ);
2353 else
2354 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
2355 EEPROM_EIRP_MAX_TX_POWER_5GHZ);
2356
2357 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
2358 (is_rate_b ? 4 : 0) + delta;
2359
2360 reg_limit = (eirp_txpower > power_level) ?
2361 (eirp_txpower - power_level) : 0;
2362 } else
2363 reg_limit = 0;
2364
2365 return txpower + delta - reg_limit;
2366 }
2367
2368 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
2369 enum ieee80211_band band,
2370 int power_level)
2371 {
2372 u8 txpower;
2373 u16 eeprom;
2374 int i, is_rate_b;
2375 u32 reg;
2376 u8 r1;
2377 u32 offset;
2378 int delta;
2379
2380 /*
2381 * Calculate HT40 compensation delta
2382 */
2383 delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
2384
2385 /*
2386 * calculate temperature compensation delta
2387 */
2388 delta += rt2800_get_gain_calibration_delta(rt2x00dev);
2389
2390 /*
2391 * set to normal bbp tx power control mode: +/- 0dBm
2392 */
2393 rt2800_bbp_read(rt2x00dev, 1, &r1);
2394 rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, 0);
2395 rt2800_bbp_write(rt2x00dev, 1, r1);
2396 offset = TX_PWR_CFG_0;
2397
2398 for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
2399 /* just to be safe */
2400 if (offset > TX_PWR_CFG_4)
2401 break;
2402
2403 rt2800_register_read(rt2x00dev, offset, &reg);
2404
2405 /* read the next four txpower values */
2406 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i,
2407 &eeprom);
2408
2409 is_rate_b = i ? 0 : 1;
2410 /*
2411 * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
2412 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
2413 * TX_PWR_CFG_4: unknown
2414 */
2415 txpower = rt2x00_get_field16(eeprom,
2416 EEPROM_TXPOWER_BYRATE_RATE0);
2417 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2418 power_level, txpower, delta);
2419 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
2420
2421 /*
2422 * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
2423 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
2424 * TX_PWR_CFG_4: unknown
2425 */
2426 txpower = rt2x00_get_field16(eeprom,
2427 EEPROM_TXPOWER_BYRATE_RATE1);
2428 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2429 power_level, txpower, delta);
2430 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
2431
2432 /*
2433 * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
2434 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14,
2435 * TX_PWR_CFG_4: unknown
2436 */
2437 txpower = rt2x00_get_field16(eeprom,
2438 EEPROM_TXPOWER_BYRATE_RATE2);
2439 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2440 power_level, txpower, delta);
2441 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
2442
2443 /*
2444 * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
2445 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15,
2446 * TX_PWR_CFG_4: unknown
2447 */
2448 txpower = rt2x00_get_field16(eeprom,
2449 EEPROM_TXPOWER_BYRATE_RATE3);
2450 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2451 power_level, txpower, delta);
2452 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
2453
2454 /* read the next four txpower values */
2455 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i + 1,
2456 &eeprom);
2457
2458 is_rate_b = 0;
2459 /*
2460 * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
2461 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
2462 * TX_PWR_CFG_4: unknown
2463 */
2464 txpower = rt2x00_get_field16(eeprom,
2465 EEPROM_TXPOWER_BYRATE_RATE0);
2466 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2467 power_level, txpower, delta);
2468 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
2469
2470 /*
2471 * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
2472 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
2473 * TX_PWR_CFG_4: unknown
2474 */
2475 txpower = rt2x00_get_field16(eeprom,
2476 EEPROM_TXPOWER_BYRATE_RATE1);
2477 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2478 power_level, txpower, delta);
2479 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
2480
2481 /*
2482 * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
2483 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
2484 * TX_PWR_CFG_4: unknown
2485 */
2486 txpower = rt2x00_get_field16(eeprom,
2487 EEPROM_TXPOWER_BYRATE_RATE2);
2488 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2489 power_level, txpower, delta);
2490 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
2491
2492 /*
2493 * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
2494 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
2495 * TX_PWR_CFG_4: unknown
2496 */
2497 txpower = rt2x00_get_field16(eeprom,
2498 EEPROM_TXPOWER_BYRATE_RATE3);
2499 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2500 power_level, txpower, delta);
2501 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
2502
2503 rt2800_register_write(rt2x00dev, offset, reg);
2504
2505 /* next TX_PWR_CFG register */
2506 offset += 4;
2507 }
2508 }
2509
2510 void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
2511 {
2512 rt2800_config_txpower(rt2x00dev, rt2x00dev->curr_band,
2513 rt2x00dev->tx_power);
2514 }
2515 EXPORT_SYMBOL_GPL(rt2800_gain_calibration);
2516
2517 void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev)
2518 {
2519 u32 tx_pin;
2520 u8 rfcsr;
2521
2522 /*
2523 * A voltage-controlled oscillator(VCO) is an electronic oscillator
2524 * designed to be controlled in oscillation frequency by a voltage
2525 * input. Maybe the temperature will affect the frequency of
2526 * oscillation to be shifted. The VCO calibration will be called
2527 * periodically to adjust the frequency to be precision.
2528 */
2529
2530 rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
2531 tx_pin &= TX_PIN_CFG_PA_PE_DISABLE;
2532 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
2533
2534 switch (rt2x00dev->chip.rf) {
2535 case RF2020:
2536 case RF3020:
2537 case RF3021:
2538 case RF3022:
2539 case RF3320:
2540 case RF3052:
2541 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
2542 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
2543 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2544 break;
2545 case RF5370:
2546 case RF5372:
2547 case RF5390:
2548 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2549 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2550 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2551 break;
2552 default:
2553 return;
2554 }
2555
2556 mdelay(1);
2557
2558 rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
2559 if (rt2x00dev->rf_channel <= 14) {
2560 switch (rt2x00dev->default_ant.tx_chain_num) {
2561 case 3:
2562 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1);
2563 /* fall through */
2564 case 2:
2565 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
2566 /* fall through */
2567 case 1:
2568 default:
2569 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
2570 break;
2571 }
2572 } else {
2573 switch (rt2x00dev->default_ant.tx_chain_num) {
2574 case 3:
2575 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1);
2576 /* fall through */
2577 case 2:
2578 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
2579 /* fall through */
2580 case 1:
2581 default:
2582 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1);
2583 break;
2584 }
2585 }
2586 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
2587
2588 }
2589 EXPORT_SYMBOL_GPL(rt2800_vco_calibration);
2590
2591 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
2592 struct rt2x00lib_conf *libconf)
2593 {
2594 u32 reg;
2595
2596 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
2597 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
2598 libconf->conf->short_frame_max_tx_count);
2599 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
2600 libconf->conf->long_frame_max_tx_count);
2601 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
2602 }
2603
2604 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
2605 struct rt2x00lib_conf *libconf)
2606 {
2607 enum dev_state state =
2608 (libconf->conf->flags & IEEE80211_CONF_PS) ?
2609 STATE_SLEEP : STATE_AWAKE;
2610 u32 reg;
2611
2612 if (state == STATE_SLEEP) {
2613 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
2614
2615 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
2616 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
2617 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
2618 libconf->conf->listen_interval - 1);
2619 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
2620 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
2621
2622 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
2623 } else {
2624 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
2625 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
2626 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
2627 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
2628 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
2629
2630 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
2631 }
2632 }
2633
2634 void rt2800_config(struct rt2x00_dev *rt2x00dev,
2635 struct rt2x00lib_conf *libconf,
2636 const unsigned int flags)
2637 {
2638 /* Always recalculate LNA gain before changing configuration */
2639 rt2800_config_lna_gain(rt2x00dev, libconf);
2640
2641 if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
2642 rt2800_config_channel(rt2x00dev, libconf->conf,
2643 &libconf->rf, &libconf->channel);
2644 rt2800_config_txpower(rt2x00dev, libconf->conf->channel->band,
2645 libconf->conf->power_level);
2646 }
2647 if (flags & IEEE80211_CONF_CHANGE_POWER)
2648 rt2800_config_txpower(rt2x00dev, libconf->conf->channel->band,
2649 libconf->conf->power_level);
2650 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
2651 rt2800_config_retry_limit(rt2x00dev, libconf);
2652 if (flags & IEEE80211_CONF_CHANGE_PS)
2653 rt2800_config_ps(rt2x00dev, libconf);
2654 }
2655 EXPORT_SYMBOL_GPL(rt2800_config);
2656
2657 /*
2658 * Link tuning
2659 */
2660 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
2661 {
2662 u32 reg;
2663
2664 /*
2665 * Update FCS error count from register.
2666 */
2667 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
2668 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
2669 }
2670 EXPORT_SYMBOL_GPL(rt2800_link_stats);
2671
2672 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
2673 {
2674 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
2675 if (rt2x00_rt(rt2x00dev, RT3070) ||
2676 rt2x00_rt(rt2x00dev, RT3071) ||
2677 rt2x00_rt(rt2x00dev, RT3090) ||
2678 rt2x00_rt(rt2x00dev, RT3390) ||
2679 rt2x00_rt(rt2x00dev, RT5390) ||
2680 rt2x00_rt(rt2x00dev, RT5392))
2681 return 0x1c + (2 * rt2x00dev->lna_gain);
2682 else
2683 return 0x2e + rt2x00dev->lna_gain;
2684 }
2685
2686 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
2687 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
2688 else
2689 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
2690 }
2691
2692 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
2693 struct link_qual *qual, u8 vgc_level)
2694 {
2695 if (qual->vgc_level != vgc_level) {
2696 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
2697 qual->vgc_level = vgc_level;
2698 qual->vgc_level_reg = vgc_level;
2699 }
2700 }
2701
2702 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
2703 {
2704 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
2705 }
2706 EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
2707
2708 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
2709 const u32 count)
2710 {
2711 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
2712 return;
2713
2714 /*
2715 * When RSSI is better then -80 increase VGC level with 0x10
2716 */
2717 rt2800_set_vgc(rt2x00dev, qual,
2718 rt2800_get_default_vgc(rt2x00dev) +
2719 ((qual->rssi > -80) * 0x10));
2720 }
2721 EXPORT_SYMBOL_GPL(rt2800_link_tuner);
2722
2723 /*
2724 * Initialization functions.
2725 */
2726 static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
2727 {
2728 u32 reg;
2729 u16 eeprom;
2730 unsigned int i;
2731 int ret;
2732
2733 rt2800_disable_wpdma(rt2x00dev);
2734
2735 ret = rt2800_drv_init_registers(rt2x00dev);
2736 if (ret)
2737 return ret;
2738
2739 rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
2740 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
2741 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
2742 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
2743 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
2744 rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
2745
2746 rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
2747 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
2748 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
2749 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
2750 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
2751 rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
2752
2753 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
2754 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
2755
2756 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
2757
2758 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2759 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
2760 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
2761 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
2762 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
2763 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
2764 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
2765 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2766
2767 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
2768
2769 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
2770 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
2771 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
2772 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
2773
2774 if (rt2x00_rt(rt2x00dev, RT3071) ||
2775 rt2x00_rt(rt2x00dev, RT3090) ||
2776 rt2x00_rt(rt2x00dev, RT3390)) {
2777 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2778 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
2779 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
2780 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2781 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
2782 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
2783 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
2784 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
2785 0x0000002c);
2786 else
2787 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
2788 0x0000000f);
2789 } else {
2790 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
2791 }
2792 } else if (rt2x00_rt(rt2x00dev, RT3070)) {
2793 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2794
2795 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
2796 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
2797 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
2798 } else {
2799 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2800 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
2801 }
2802 } else if (rt2800_is_305x_soc(rt2x00dev)) {
2803 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2804 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
2805 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
2806 } else if (rt2x00_rt(rt2x00dev, RT3572)) {
2807 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2808 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2809 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
2810 rt2x00_rt(rt2x00dev, RT5392)) {
2811 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
2812 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2813 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
2814 } else {
2815 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
2816 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2817 }
2818
2819 rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
2820 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
2821 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
2822 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
2823 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
2824 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
2825 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
2826 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
2827 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
2828 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
2829
2830 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
2831 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
2832 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
2833 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
2834 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
2835
2836 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
2837 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
2838 if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
2839 rt2x00_rt(rt2x00dev, RT2883) ||
2840 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
2841 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
2842 else
2843 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
2844 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
2845 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
2846 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
2847
2848 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
2849 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
2850 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
2851 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
2852 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
2853 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
2854 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
2855 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
2856 rt2800_register_write(rt2x00dev, LED_CFG, reg);
2857
2858 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
2859
2860 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
2861 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
2862 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
2863 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
2864 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
2865 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
2866 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
2867 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
2868
2869 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
2870 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
2871 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
2872 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
2873 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
2874 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
2875 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
2876 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
2877 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
2878
2879 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2880 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
2881 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
2882 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
2883 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2884 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2885 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2886 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2887 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2888 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2889 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
2890 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2891
2892 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2893 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
2894 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
2895 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
2896 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2897 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2898 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2899 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2900 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2901 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2902 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
2903 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2904
2905 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2906 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
2907 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
2908 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
2909 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2910 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2911 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2912 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2913 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2914 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2915 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
2916 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2917
2918 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2919 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
2920 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
2921 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
2922 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2923 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2924 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2925 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
2926 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2927 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
2928 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
2929 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2930
2931 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2932 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
2933 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
2934 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
2935 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2936 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2937 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2938 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2939 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2940 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2941 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
2942 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2943
2944 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2945 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
2946 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
2947 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
2948 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2949 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2950 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2951 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
2952 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2953 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
2954 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
2955 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2956
2957 if (rt2x00_is_usb(rt2x00dev)) {
2958 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
2959
2960 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2961 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2962 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2963 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2964 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2965 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
2966 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
2967 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
2968 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
2969 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
2970 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2971 }
2972
2973 /*
2974 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
2975 * although it is reserved.
2976 */
2977 rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, &reg);
2978 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
2979 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
2980 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
2981 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
2982 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
2983 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
2984 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
2985 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
2986 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
2987 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
2988 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
2989
2990 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
2991
2992 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2993 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
2994 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
2995 IEEE80211_MAX_RTS_THRESHOLD);
2996 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
2997 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
2998
2999 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
3000
3001 /*
3002 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
3003 * time should be set to 16. However, the original Ralink driver uses
3004 * 16 for both and indeed using a value of 10 for CCK SIFS results in
3005 * connection problems with 11g + CTS protection. Hence, use the same
3006 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
3007 */
3008 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
3009 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
3010 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
3011 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
3012 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
3013 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
3014 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
3015
3016 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
3017
3018 /*
3019 * ASIC will keep garbage value after boot, clear encryption keys.
3020 */
3021 for (i = 0; i < 4; i++)
3022 rt2800_register_write(rt2x00dev,
3023 SHARED_KEY_MODE_ENTRY(i), 0);
3024
3025 for (i = 0; i < 256; i++) {
3026 rt2800_config_wcid(rt2x00dev, NULL, i);
3027 rt2800_delete_wcid_attr(rt2x00dev, i);
3028 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
3029 }
3030
3031 /*
3032 * Clear all beacons
3033 */
3034 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE0);
3035 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE1);
3036 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE2);
3037 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE3);
3038 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE4);
3039 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE5);
3040 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE6);
3041 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE7);
3042
3043 if (rt2x00_is_usb(rt2x00dev)) {
3044 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
3045 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
3046 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
3047 } else if (rt2x00_is_pcie(rt2x00dev)) {
3048 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
3049 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
3050 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
3051 }
3052
3053 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
3054 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
3055 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
3056 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
3057 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
3058 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
3059 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
3060 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
3061 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
3062 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
3063
3064 rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
3065 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
3066 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
3067 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
3068 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
3069 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
3070 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
3071 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
3072 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
3073 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
3074
3075 rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
3076 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
3077 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
3078 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
3079 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
3080 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
3081 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
3082 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
3083 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
3084 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
3085
3086 rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
3087 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
3088 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
3089 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
3090 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
3091 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
3092
3093 /*
3094 * Do not force the BA window size, we use the TXWI to set it
3095 */
3096 rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, &reg);
3097 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
3098 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
3099 rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
3100
3101 /*
3102 * We must clear the error counters.
3103 * These registers are cleared on read,
3104 * so we may pass a useless variable to store the value.
3105 */
3106 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
3107 rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
3108 rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
3109 rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
3110 rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
3111 rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
3112
3113 /*
3114 * Setup leadtime for pre tbtt interrupt to 6ms
3115 */
3116 rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
3117 rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
3118 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
3119
3120 /*
3121 * Set up channel statistics timer
3122 */
3123 rt2800_register_read(rt2x00dev, CH_TIME_CFG, &reg);
3124 rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
3125 rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
3126 rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
3127 rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
3128 rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
3129 rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
3130
3131 return 0;
3132 }
3133
3134 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
3135 {
3136 unsigned int i;
3137 u32 reg;
3138
3139 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
3140 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
3141 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
3142 return 0;
3143
3144 udelay(REGISTER_BUSY_DELAY);
3145 }
3146
3147 ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
3148 return -EACCES;
3149 }
3150
3151 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
3152 {
3153 unsigned int i;
3154 u8 value;
3155
3156 /*
3157 * BBP was enabled after firmware was loaded,
3158 * but we need to reactivate it now.
3159 */
3160 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
3161 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
3162 msleep(1);
3163
3164 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
3165 rt2800_bbp_read(rt2x00dev, 0, &value);
3166 if ((value != 0xff) && (value != 0x00))
3167 return 0;
3168 udelay(REGISTER_BUSY_DELAY);
3169 }
3170
3171 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
3172 return -EACCES;
3173 }
3174
3175 static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
3176 {
3177 unsigned int i;
3178 u16 eeprom;
3179 u8 reg_id;
3180 u8 value;
3181
3182 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
3183 rt2800_wait_bbp_ready(rt2x00dev)))
3184 return -EACCES;
3185
3186 if (rt2x00_rt(rt2x00dev, RT5390) ||
3187 rt2x00_rt(rt2x00dev, RT5392)) {
3188 rt2800_bbp_read(rt2x00dev, 4, &value);
3189 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
3190 rt2800_bbp_write(rt2x00dev, 4, value);
3191 }
3192
3193 if (rt2800_is_305x_soc(rt2x00dev) ||
3194 rt2x00_rt(rt2x00dev, RT3572) ||
3195 rt2x00_rt(rt2x00dev, RT5390) ||
3196 rt2x00_rt(rt2x00dev, RT5392))
3197 rt2800_bbp_write(rt2x00dev, 31, 0x08);
3198
3199 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
3200 rt2800_bbp_write(rt2x00dev, 66, 0x38);
3201
3202 if (rt2x00_rt(rt2x00dev, RT5390) ||
3203 rt2x00_rt(rt2x00dev, RT5392))
3204 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
3205
3206 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
3207 rt2800_bbp_write(rt2x00dev, 69, 0x16);
3208 rt2800_bbp_write(rt2x00dev, 73, 0x12);
3209 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
3210 rt2x00_rt(rt2x00dev, RT5392)) {
3211 rt2800_bbp_write(rt2x00dev, 69, 0x12);
3212 rt2800_bbp_write(rt2x00dev, 73, 0x13);
3213 rt2800_bbp_write(rt2x00dev, 75, 0x46);
3214 rt2800_bbp_write(rt2x00dev, 76, 0x28);
3215 rt2800_bbp_write(rt2x00dev, 77, 0x59);
3216 } else {
3217 rt2800_bbp_write(rt2x00dev, 69, 0x12);
3218 rt2800_bbp_write(rt2x00dev, 73, 0x10);
3219 }
3220
3221 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
3222
3223 if (rt2x00_rt(rt2x00dev, RT3070) ||
3224 rt2x00_rt(rt2x00dev, RT3071) ||
3225 rt2x00_rt(rt2x00dev, RT3090) ||
3226 rt2x00_rt(rt2x00dev, RT3390) ||
3227 rt2x00_rt(rt2x00dev, RT3572) ||
3228 rt2x00_rt(rt2x00dev, RT5390) ||
3229 rt2x00_rt(rt2x00dev, RT5392)) {
3230 rt2800_bbp_write(rt2x00dev, 79, 0x13);
3231 rt2800_bbp_write(rt2x00dev, 80, 0x05);
3232 rt2800_bbp_write(rt2x00dev, 81, 0x33);
3233 } else if (rt2800_is_305x_soc(rt2x00dev)) {
3234 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
3235 rt2800_bbp_write(rt2x00dev, 80, 0x08);
3236 } else {
3237 rt2800_bbp_write(rt2x00dev, 81, 0x37);
3238 }
3239
3240 rt2800_bbp_write(rt2x00dev, 82, 0x62);
3241 if (rt2x00_rt(rt2x00dev, RT5390) ||
3242 rt2x00_rt(rt2x00dev, RT5392))
3243 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
3244 else
3245 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3246
3247 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
3248 rt2800_bbp_write(rt2x00dev, 84, 0x19);
3249 else if (rt2x00_rt(rt2x00dev, RT5390) ||
3250 rt2x00_rt(rt2x00dev, RT5392))
3251 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
3252 else
3253 rt2800_bbp_write(rt2x00dev, 84, 0x99);
3254
3255 if (rt2x00_rt(rt2x00dev, RT5390) ||
3256 rt2x00_rt(rt2x00dev, RT5392))
3257 rt2800_bbp_write(rt2x00dev, 86, 0x38);
3258 else
3259 rt2800_bbp_write(rt2x00dev, 86, 0x00);
3260
3261 if (rt2x00_rt(rt2x00dev, RT5392))
3262 rt2800_bbp_write(rt2x00dev, 88, 0x90);
3263
3264 rt2800_bbp_write(rt2x00dev, 91, 0x04);
3265
3266 if (rt2x00_rt(rt2x00dev, RT5390) ||
3267 rt2x00_rt(rt2x00dev, RT5392))
3268 rt2800_bbp_write(rt2x00dev, 92, 0x02);
3269 else
3270 rt2800_bbp_write(rt2x00dev, 92, 0x00);
3271
3272 if (rt2x00_rt(rt2x00dev, RT5392)) {
3273 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
3274 rt2800_bbp_write(rt2x00dev, 98, 0x12);
3275 }
3276
3277 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
3278 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
3279 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
3280 rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
3281 rt2x00_rt(rt2x00dev, RT3572) ||
3282 rt2x00_rt(rt2x00dev, RT5390) ||
3283 rt2x00_rt(rt2x00dev, RT5392) ||
3284 rt2800_is_305x_soc(rt2x00dev))
3285 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
3286 else
3287 rt2800_bbp_write(rt2x00dev, 103, 0x00);
3288
3289 if (rt2x00_rt(rt2x00dev, RT5390) ||
3290 rt2x00_rt(rt2x00dev, RT5392))
3291 rt2800_bbp_write(rt2x00dev, 104, 0x92);
3292
3293 if (rt2800_is_305x_soc(rt2x00dev))
3294 rt2800_bbp_write(rt2x00dev, 105, 0x01);
3295 else if (rt2x00_rt(rt2x00dev, RT5390) ||
3296 rt2x00_rt(rt2x00dev, RT5392))
3297 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
3298 else
3299 rt2800_bbp_write(rt2x00dev, 105, 0x05);
3300
3301 if (rt2x00_rt(rt2x00dev, RT5390))
3302 rt2800_bbp_write(rt2x00dev, 106, 0x03);
3303 else if (rt2x00_rt(rt2x00dev, RT5392))
3304 rt2800_bbp_write(rt2x00dev, 106, 0x12);
3305 else
3306 rt2800_bbp_write(rt2x00dev, 106, 0x35);
3307
3308 if (rt2x00_rt(rt2x00dev, RT5390) ||
3309 rt2x00_rt(rt2x00dev, RT5392))
3310 rt2800_bbp_write(rt2x00dev, 128, 0x12);
3311
3312 if (rt2x00_rt(rt2x00dev, RT5392)) {
3313 rt2800_bbp_write(rt2x00dev, 134, 0xd0);
3314 rt2800_bbp_write(rt2x00dev, 135, 0xf6);
3315 }
3316
3317 if (rt2x00_rt(rt2x00dev, RT3071) ||
3318 rt2x00_rt(rt2x00dev, RT3090) ||
3319 rt2x00_rt(rt2x00dev, RT3390) ||
3320 rt2x00_rt(rt2x00dev, RT3572) ||
3321 rt2x00_rt(rt2x00dev, RT5390) ||
3322 rt2x00_rt(rt2x00dev, RT5392)) {
3323 rt2800_bbp_read(rt2x00dev, 138, &value);
3324
3325 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
3326 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
3327 value |= 0x20;
3328 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
3329 value &= ~0x02;
3330
3331 rt2800_bbp_write(rt2x00dev, 138, value);
3332 }
3333
3334 if (rt2x00_rt(rt2x00dev, RT5390) ||
3335 rt2x00_rt(rt2x00dev, RT5392)) {
3336 int ant, div_mode;
3337
3338 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3339 div_mode = rt2x00_get_field16(eeprom,
3340 EEPROM_NIC_CONF1_ANT_DIVERSITY);
3341 ant = (div_mode == 3) ? 1 : 0;
3342
3343 /* check if this is a Bluetooth combo card */
3344 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
3345 u32 reg;
3346
3347 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
3348 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT3, 0);
3349 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT6, 0);
3350 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, 0);
3351 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT6, 0);
3352 if (ant == 0)
3353 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, 1);
3354 else if (ant == 1)
3355 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT6, 1);
3356 rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
3357 }
3358
3359 rt2800_bbp_read(rt2x00dev, 152, &value);
3360 if (ant == 0)
3361 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
3362 else
3363 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
3364 rt2800_bbp_write(rt2x00dev, 152, value);
3365
3366 /* Init frequency calibration */
3367 rt2800_bbp_write(rt2x00dev, 142, 1);
3368 rt2800_bbp_write(rt2x00dev, 143, 57);
3369 }
3370
3371 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
3372 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
3373
3374 if (eeprom != 0xffff && eeprom != 0x0000) {
3375 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
3376 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
3377 rt2800_bbp_write(rt2x00dev, reg_id, value);
3378 }
3379 }
3380
3381 return 0;
3382 }
3383
3384 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
3385 bool bw40, u8 rfcsr24, u8 filter_target)
3386 {
3387 unsigned int i;
3388 u8 bbp;
3389 u8 rfcsr;
3390 u8 passband;
3391 u8 stopband;
3392 u8 overtuned = 0;
3393
3394 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
3395
3396 rt2800_bbp_read(rt2x00dev, 4, &bbp);
3397 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
3398 rt2800_bbp_write(rt2x00dev, 4, bbp);
3399
3400 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
3401 rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
3402 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
3403
3404 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
3405 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
3406 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
3407
3408 /*
3409 * Set power & frequency of passband test tone
3410 */
3411 rt2800_bbp_write(rt2x00dev, 24, 0);
3412
3413 for (i = 0; i < 100; i++) {
3414 rt2800_bbp_write(rt2x00dev, 25, 0x90);
3415 msleep(1);
3416
3417 rt2800_bbp_read(rt2x00dev, 55, &passband);
3418 if (passband)
3419 break;
3420 }
3421
3422 /*
3423 * Set power & frequency of stopband test tone
3424 */
3425 rt2800_bbp_write(rt2x00dev, 24, 0x06);
3426
3427 for (i = 0; i < 100; i++) {
3428 rt2800_bbp_write(rt2x00dev, 25, 0x90);
3429 msleep(1);
3430
3431 rt2800_bbp_read(rt2x00dev, 55, &stopband);
3432
3433 if ((passband - stopband) <= filter_target) {
3434 rfcsr24++;
3435 overtuned += ((passband - stopband) == filter_target);
3436 } else
3437 break;
3438
3439 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
3440 }
3441
3442 rfcsr24 -= !!overtuned;
3443
3444 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
3445 return rfcsr24;
3446 }
3447
3448 static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
3449 {
3450 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
3451 u8 rfcsr;
3452 u8 bbp;
3453 u32 reg;
3454 u16 eeprom;
3455
3456 if (!rt2x00_rt(rt2x00dev, RT3070) &&
3457 !rt2x00_rt(rt2x00dev, RT3071) &&
3458 !rt2x00_rt(rt2x00dev, RT3090) &&
3459 !rt2x00_rt(rt2x00dev, RT3390) &&
3460 !rt2x00_rt(rt2x00dev, RT3572) &&
3461 !rt2x00_rt(rt2x00dev, RT5390) &&
3462 !rt2x00_rt(rt2x00dev, RT5392) &&
3463 !rt2800_is_305x_soc(rt2x00dev))
3464 return 0;
3465
3466 /*
3467 * Init RF calibration.
3468 */
3469 if (rt2x00_rt(rt2x00dev, RT5390) ||
3470 rt2x00_rt(rt2x00dev, RT5392)) {
3471 rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
3472 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
3473 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
3474 msleep(1);
3475 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 0);
3476 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
3477 } else {
3478 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
3479 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
3480 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3481 msleep(1);
3482 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
3483 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3484 }
3485
3486 if (rt2x00_rt(rt2x00dev, RT3070) ||
3487 rt2x00_rt(rt2x00dev, RT3071) ||
3488 rt2x00_rt(rt2x00dev, RT3090)) {
3489 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
3490 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
3491 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
3492 rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
3493 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
3494 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
3495 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
3496 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
3497 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
3498 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
3499 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
3500 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
3501 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
3502 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
3503 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
3504 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
3505 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
3506 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
3507 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
3508 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
3509 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
3510 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
3511 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
3512 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
3513 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
3514 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
3515 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
3516 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
3517 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
3518 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
3519 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
3520 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
3521 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
3522 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
3523 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
3524 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
3525 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
3526 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
3527 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
3528 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
3529 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
3530 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
3531 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
3532 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
3533 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
3534 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
3535 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
3536 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
3537 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
3538 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
3539 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
3540 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
3541 } else if (rt2x00_rt(rt2x00dev, RT3572)) {
3542 rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
3543 rt2800_rfcsr_write(rt2x00dev, 1, 0x81);
3544 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
3545 rt2800_rfcsr_write(rt2x00dev, 3, 0x02);
3546 rt2800_rfcsr_write(rt2x00dev, 4, 0x4c);
3547 rt2800_rfcsr_write(rt2x00dev, 5, 0x05);
3548 rt2800_rfcsr_write(rt2x00dev, 6, 0x4a);
3549 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
3550 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
3551 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
3552 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
3553 rt2800_rfcsr_write(rt2x00dev, 12, 0x70);
3554 rt2800_rfcsr_write(rt2x00dev, 13, 0x65);
3555 rt2800_rfcsr_write(rt2x00dev, 14, 0xa0);
3556 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
3557 rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
3558 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
3559 rt2800_rfcsr_write(rt2x00dev, 18, 0xac);
3560 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
3561 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
3562 rt2800_rfcsr_write(rt2x00dev, 21, 0xd0);
3563 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
3564 rt2800_rfcsr_write(rt2x00dev, 23, 0x3c);
3565 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
3566 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
3567 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
3568 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
3569 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
3570 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
3571 rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
3572 rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
3573 } else if (rt2800_is_305x_soc(rt2x00dev)) {
3574 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
3575 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
3576 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
3577 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
3578 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
3579 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
3580 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
3581 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
3582 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
3583 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
3584 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
3585 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
3586 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
3587 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
3588 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
3589 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
3590 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
3591 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
3592 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
3593 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
3594 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
3595 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
3596 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
3597 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
3598 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
3599 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
3600 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
3601 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
3602 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
3603 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
3604 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
3605 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
3606 return 0;
3607 } else if (rt2x00_rt(rt2x00dev, RT5390)) {
3608 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
3609 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
3610 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
3611 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
3612 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3613 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
3614 else
3615 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
3616 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
3617 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
3618 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
3619 rt2800_rfcsr_write(rt2x00dev, 12, 0xc6);
3620 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
3621 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
3622 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
3623 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
3624 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
3625 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
3626
3627 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
3628 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
3629 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
3630 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
3631 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
3632 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3633 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
3634 else
3635 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
3636 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
3637 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
3638 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
3639 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
3640
3641 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
3642 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
3643 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
3644 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
3645 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
3646 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
3647 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
3648 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
3649 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
3650 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
3651
3652 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3653 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
3654 else
3655 rt2800_rfcsr_write(rt2x00dev, 40, 0x4b);
3656 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
3657 rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
3658 rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
3659 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
3660 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
3661 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3662 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
3663 else
3664 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
3665 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
3666 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
3667 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
3668
3669 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
3670 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3671 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
3672 else
3673 rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
3674 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
3675 rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
3676 rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
3677 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
3678 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
3679 rt2800_rfcsr_write(rt2x00dev, 59, 0x63);
3680
3681 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
3682 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3683 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
3684 else
3685 rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
3686 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
3687 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
3688 } else if (rt2x00_rt(rt2x00dev, RT5392)) {
3689 rt2800_rfcsr_write(rt2x00dev, 1, 0x17);
3690 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
3691 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
3692 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
3693 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
3694 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
3695 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
3696 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
3697 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
3698 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
3699 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
3700 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
3701 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
3702 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
3703 rt2800_rfcsr_write(rt2x00dev, 19, 0x4d);
3704 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
3705 rt2800_rfcsr_write(rt2x00dev, 21, 0x8d);
3706 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
3707 rt2800_rfcsr_write(rt2x00dev, 23, 0x0b);
3708 rt2800_rfcsr_write(rt2x00dev, 24, 0x44);
3709 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
3710 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
3711 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
3712 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
3713 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
3714 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
3715 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
3716 rt2800_rfcsr_write(rt2x00dev, 32, 0x20);
3717 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
3718 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
3719 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
3720 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
3721 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
3722 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
3723 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
3724 rt2800_rfcsr_write(rt2x00dev, 40, 0x0f);
3725 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
3726 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
3727 rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
3728 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
3729 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
3730 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
3731 rt2800_rfcsr_write(rt2x00dev, 47, 0x0c);
3732 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
3733 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
3734 rt2800_rfcsr_write(rt2x00dev, 50, 0x94);
3735 rt2800_rfcsr_write(rt2x00dev, 51, 0x3a);
3736 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
3737 rt2800_rfcsr_write(rt2x00dev, 53, 0x44);
3738 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
3739 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
3740 rt2800_rfcsr_write(rt2x00dev, 56, 0xa1);
3741 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
3742 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
3743 rt2800_rfcsr_write(rt2x00dev, 59, 0x07);
3744 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
3745 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
3746 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
3747 rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
3748 }
3749
3750 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
3751 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3752 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
3753 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
3754 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
3755 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
3756 rt2x00_rt(rt2x00dev, RT3090)) {
3757 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
3758
3759 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
3760 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
3761 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
3762
3763 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3764 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
3765 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
3766 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
3767 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3768 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
3769 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
3770 else
3771 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
3772 }
3773 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
3774
3775 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
3776 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
3777 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
3778 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
3779 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
3780 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
3781 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
3782 } else if (rt2x00_rt(rt2x00dev, RT3572)) {
3783 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
3784 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
3785 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
3786
3787 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3788 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
3789 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
3790 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
3791 msleep(1);
3792 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3793 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
3794 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
3795 }
3796
3797 /*
3798 * Set RX Filter calibration for 20MHz and 40MHz
3799 */
3800 if (rt2x00_rt(rt2x00dev, RT3070)) {
3801 drv_data->calibration_bw20 =
3802 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
3803 drv_data->calibration_bw40 =
3804 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
3805 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
3806 rt2x00_rt(rt2x00dev, RT3090) ||
3807 rt2x00_rt(rt2x00dev, RT3390) ||
3808 rt2x00_rt(rt2x00dev, RT3572)) {
3809 drv_data->calibration_bw20 =
3810 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
3811 drv_data->calibration_bw40 =
3812 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
3813 }
3814
3815 /*
3816 * Save BBP 25 & 26 values for later use in channel switching
3817 */
3818 rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25);
3819 rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26);
3820
3821 if (!rt2x00_rt(rt2x00dev, RT5390) &&
3822 !rt2x00_rt(rt2x00dev, RT5392)) {
3823 /*
3824 * Set back to initial state
3825 */
3826 rt2800_bbp_write(rt2x00dev, 24, 0);
3827
3828 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
3829 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
3830 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
3831
3832 /*
3833 * Set BBP back to BW20
3834 */
3835 rt2800_bbp_read(rt2x00dev, 4, &bbp);
3836 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
3837 rt2800_bbp_write(rt2x00dev, 4, bbp);
3838 }
3839
3840 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
3841 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
3842 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
3843 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
3844 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
3845
3846 rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
3847 rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
3848 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
3849
3850 if (!rt2x00_rt(rt2x00dev, RT5390) &&
3851 !rt2x00_rt(rt2x00dev, RT5392)) {
3852 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
3853 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
3854 if (rt2x00_rt(rt2x00dev, RT3070) ||
3855 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
3856 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
3857 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
3858 if (!test_bit(CAPABILITY_EXTERNAL_LNA_BG,
3859 &rt2x00dev->cap_flags))
3860 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
3861 }
3862 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
3863 drv_data->txmixer_gain_24g);
3864 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
3865 }
3866
3867 if (rt2x00_rt(rt2x00dev, RT3090)) {
3868 rt2800_bbp_read(rt2x00dev, 138, &bbp);
3869
3870 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
3871 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
3872 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
3873 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
3874 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
3875 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
3876
3877 rt2800_bbp_write(rt2x00dev, 138, bbp);
3878 }
3879
3880 if (rt2x00_rt(rt2x00dev, RT3071) ||
3881 rt2x00_rt(rt2x00dev, RT3090) ||
3882 rt2x00_rt(rt2x00dev, RT3390)) {
3883 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
3884 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
3885 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
3886 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
3887 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
3888 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
3889 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3890
3891 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
3892 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
3893 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
3894
3895 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
3896 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
3897 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
3898
3899 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
3900 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
3901 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
3902 }
3903
3904 if (rt2x00_rt(rt2x00dev, RT3070)) {
3905 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
3906 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
3907 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
3908 else
3909 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
3910 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
3911 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
3912 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
3913 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
3914 }
3915
3916 if (rt2x00_rt(rt2x00dev, RT5390) ||
3917 rt2x00_rt(rt2x00dev, RT5392)) {
3918 rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr);
3919 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
3920 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
3921
3922 rt2800_rfcsr_read(rt2x00dev, 39, &rfcsr);
3923 rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
3924 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
3925
3926 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
3927 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
3928 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3929 }
3930
3931 return 0;
3932 }
3933
3934 int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
3935 {
3936 u32 reg;
3937 u16 word;
3938
3939 /*
3940 * Initialize all registers.
3941 */
3942 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
3943 rt2800_init_registers(rt2x00dev) ||
3944 rt2800_init_bbp(rt2x00dev) ||
3945 rt2800_init_rfcsr(rt2x00dev)))
3946 return -EIO;
3947
3948 /*
3949 * Send signal to firmware during boot time.
3950 */
3951 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
3952
3953 if (rt2x00_is_usb(rt2x00dev) &&
3954 (rt2x00_rt(rt2x00dev, RT3070) ||
3955 rt2x00_rt(rt2x00dev, RT3071) ||
3956 rt2x00_rt(rt2x00dev, RT3572))) {
3957 udelay(200);
3958 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
3959 udelay(10);
3960 }
3961
3962 /*
3963 * Enable RX.
3964 */
3965 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
3966 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
3967 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
3968 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
3969
3970 udelay(50);
3971
3972 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
3973 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
3974 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
3975 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
3976 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
3977 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
3978
3979 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
3980 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
3981 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
3982 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
3983
3984 /*
3985 * Initialize LED control
3986 */
3987 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word);
3988 rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
3989 word & 0xff, (word >> 8) & 0xff);
3990
3991 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word);
3992 rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
3993 word & 0xff, (word >> 8) & 0xff);
3994
3995 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word);
3996 rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
3997 word & 0xff, (word >> 8) & 0xff);
3998
3999 return 0;
4000 }
4001 EXPORT_SYMBOL_GPL(rt2800_enable_radio);
4002
4003 void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
4004 {
4005 u32 reg;
4006
4007 rt2800_disable_wpdma(rt2x00dev);
4008
4009 /* Wait for DMA, ignore error */
4010 rt2800_wait_wpdma_ready(rt2x00dev);
4011
4012 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
4013 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
4014 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
4015 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
4016 }
4017 EXPORT_SYMBOL_GPL(rt2800_disable_radio);
4018
4019 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
4020 {
4021 u32 reg;
4022
4023 rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
4024
4025 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
4026 }
4027 EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
4028
4029 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
4030 {
4031 u32 reg;
4032
4033 mutex_lock(&rt2x00dev->csr_mutex);
4034
4035 rt2800_register_read_lock(rt2x00dev, EFUSE_CTRL, &reg);
4036 rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
4037 rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
4038 rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
4039 rt2800_register_write_lock(rt2x00dev, EFUSE_CTRL, reg);
4040
4041 /* Wait until the EEPROM has been loaded */
4042 rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg);
4043
4044 /* Apparently the data is read from end to start */
4045 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA3, &reg);
4046 /* The returned value is in CPU order, but eeprom is le */
4047 *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg);
4048 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA2, &reg);
4049 *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg);
4050 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA1, &reg);
4051 *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg);
4052 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA0, &reg);
4053 *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg);
4054
4055 mutex_unlock(&rt2x00dev->csr_mutex);
4056 }
4057
4058 void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
4059 {
4060 unsigned int i;
4061
4062 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
4063 rt2800_efuse_read(rt2x00dev, i);
4064 }
4065 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
4066
4067 int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
4068 {
4069 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
4070 u16 word;
4071 u8 *mac;
4072 u8 default_lna_gain;
4073
4074 /*
4075 * Start validation of the data that has been read.
4076 */
4077 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
4078 if (!is_valid_ether_addr(mac)) {
4079 random_ether_addr(mac);
4080 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
4081 }
4082
4083 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word);
4084 if (word == 0xffff) {
4085 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
4086 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
4087 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
4088 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
4089 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
4090 } else if (rt2x00_rt(rt2x00dev, RT2860) ||
4091 rt2x00_rt(rt2x00dev, RT2872)) {
4092 /*
4093 * There is a max of 2 RX streams for RT28x0 series
4094 */
4095 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
4096 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
4097 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
4098 }
4099
4100 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
4101 if (word == 0xffff) {
4102 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
4103 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
4104 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
4105 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
4106 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
4107 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
4108 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
4109 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
4110 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
4111 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
4112 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
4113 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
4114 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
4115 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
4116 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
4117 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
4118 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
4119 }
4120
4121 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
4122 if ((word & 0x00ff) == 0x00ff) {
4123 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
4124 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
4125 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
4126 }
4127 if ((word & 0xff00) == 0xff00) {
4128 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
4129 LED_MODE_TXRX_ACTIVITY);
4130 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
4131 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
4132 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
4133 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
4134 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
4135 EEPROM(rt2x00dev, "Led Mode: 0x%04x\n", word);
4136 }
4137
4138 /*
4139 * During the LNA validation we are going to use
4140 * lna0 as correct value. Note that EEPROM_LNA
4141 * is never validated.
4142 */
4143 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
4144 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
4145
4146 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
4147 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
4148 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
4149 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
4150 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
4151 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
4152
4153 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &word);
4154 if ((word & 0x00ff) != 0x00ff) {
4155 drv_data->txmixer_gain_24g =
4156 rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL);
4157 } else {
4158 drv_data->txmixer_gain_24g = 0;
4159 }
4160
4161 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
4162 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
4163 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
4164 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
4165 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
4166 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
4167 default_lna_gain);
4168 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
4169
4170 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A, &word);
4171 if ((word & 0x00ff) != 0x00ff) {
4172 drv_data->txmixer_gain_5g =
4173 rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL);
4174 } else {
4175 drv_data->txmixer_gain_5g = 0;
4176 }
4177
4178 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
4179 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
4180 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
4181 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
4182 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
4183 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
4184
4185 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
4186 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
4187 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
4188 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
4189 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
4190 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
4191 default_lna_gain);
4192 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
4193
4194 return 0;
4195 }
4196 EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
4197
4198 int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
4199 {
4200 u32 reg;
4201 u16 value;
4202 u16 eeprom;
4203
4204 /*
4205 * Read EEPROM word for configuration.
4206 */
4207 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
4208
4209 /*
4210 * Identify RF chipset by EEPROM value
4211 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
4212 * RT53xx: defined in "EEPROM_CHIP_ID" field
4213 */
4214 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
4215 if (rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5390 ||
4216 rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5392)
4217 rt2x00_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &value);
4218 else
4219 value = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
4220
4221 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
4222 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
4223
4224 switch (rt2x00dev->chip.rt) {
4225 case RT2860:
4226 case RT2872:
4227 case RT2883:
4228 case RT3070:
4229 case RT3071:
4230 case RT3090:
4231 case RT3390:
4232 case RT3572:
4233 case RT5390:
4234 case RT5392:
4235 break;
4236 default:
4237 ERROR(rt2x00dev, "Invalid RT chipset 0x%04x detected.\n", rt2x00dev->chip.rt);
4238 return -ENODEV;
4239 }
4240
4241 switch (rt2x00dev->chip.rf) {
4242 case RF2820:
4243 case RF2850:
4244 case RF2720:
4245 case RF2750:
4246 case RF3020:
4247 case RF2020:
4248 case RF3021:
4249 case RF3022:
4250 case RF3052:
4251 case RF3320:
4252 case RF5370:
4253 case RF5372:
4254 case RF5390:
4255 break;
4256 default:
4257 ERROR(rt2x00dev, "Invalid RF chipset 0x%04x detected.\n",
4258 rt2x00dev->chip.rf);
4259 return -ENODEV;
4260 }
4261
4262 /*
4263 * Identify default antenna configuration.
4264 */
4265 rt2x00dev->default_ant.tx_chain_num =
4266 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
4267 rt2x00dev->default_ant.rx_chain_num =
4268 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
4269
4270 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
4271
4272 if (rt2x00_rt(rt2x00dev, RT3070) ||
4273 rt2x00_rt(rt2x00dev, RT3090) ||
4274 rt2x00_rt(rt2x00dev, RT3390)) {
4275 value = rt2x00_get_field16(eeprom,
4276 EEPROM_NIC_CONF1_ANT_DIVERSITY);
4277 switch (value) {
4278 case 0:
4279 case 1:
4280 case 2:
4281 rt2x00dev->default_ant.tx = ANTENNA_A;
4282 rt2x00dev->default_ant.rx = ANTENNA_A;
4283 break;
4284 case 3:
4285 rt2x00dev->default_ant.tx = ANTENNA_A;
4286 rt2x00dev->default_ant.rx = ANTENNA_B;
4287 break;
4288 }
4289 } else {
4290 rt2x00dev->default_ant.tx = ANTENNA_A;
4291 rt2x00dev->default_ant.rx = ANTENNA_A;
4292 }
4293
4294 /*
4295 * Determine external LNA informations.
4296 */
4297 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
4298 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
4299 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
4300 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
4301
4302 /*
4303 * Detect if this device has an hardware controlled radio.
4304 */
4305 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
4306 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
4307
4308 /*
4309 * Detect if this device has Bluetooth co-existence.
4310 */
4311 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST))
4312 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags);
4313
4314 /*
4315 * Read frequency offset and RF programming sequence.
4316 */
4317 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
4318 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
4319
4320 /*
4321 * Store led settings, for correct led behaviour.
4322 */
4323 #ifdef CONFIG_RT2X00_LIB_LEDS
4324 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
4325 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
4326 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
4327
4328 rt2x00dev->led_mcu_reg = eeprom;
4329 #endif /* CONFIG_RT2X00_LIB_LEDS */
4330
4331 /*
4332 * Check if support EIRP tx power limit feature.
4333 */
4334 rt2x00_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom);
4335
4336 if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
4337 EIRP_MAX_TX_POWER_LIMIT)
4338 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
4339
4340 return 0;
4341 }
4342 EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
4343
4344 /*
4345 * RF value list for rt28xx
4346 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
4347 */
4348 static const struct rf_channel rf_vals[] = {
4349 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
4350 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
4351 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
4352 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
4353 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
4354 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
4355 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
4356 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
4357 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
4358 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
4359 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
4360 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
4361 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
4362 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
4363
4364 /* 802.11 UNI / HyperLan 2 */
4365 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
4366 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
4367 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
4368 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
4369 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
4370 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
4371 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
4372 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
4373 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
4374 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
4375 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
4376 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
4377
4378 /* 802.11 HyperLan 2 */
4379 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
4380 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
4381 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
4382 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
4383 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
4384 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
4385 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
4386 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
4387 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
4388 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
4389 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
4390 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
4391 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
4392 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
4393 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
4394 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
4395
4396 /* 802.11 UNII */
4397 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
4398 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
4399 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
4400 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
4401 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
4402 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
4403 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
4404 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
4405 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
4406 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
4407 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
4408
4409 /* 802.11 Japan */
4410 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
4411 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
4412 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
4413 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
4414 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
4415 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
4416 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
4417 };
4418
4419 /*
4420 * RF value list for rt3xxx
4421 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
4422 */
4423 static const struct rf_channel rf_vals_3x[] = {
4424 {1, 241, 2, 2 },
4425 {2, 241, 2, 7 },
4426 {3, 242, 2, 2 },
4427 {4, 242, 2, 7 },
4428 {5, 243, 2, 2 },
4429 {6, 243, 2, 7 },
4430 {7, 244, 2, 2 },
4431 {8, 244, 2, 7 },
4432 {9, 245, 2, 2 },
4433 {10, 245, 2, 7 },
4434 {11, 246, 2, 2 },
4435 {12, 246, 2, 7 },
4436 {13, 247, 2, 2 },
4437 {14, 248, 2, 4 },
4438
4439 /* 802.11 UNI / HyperLan 2 */
4440 {36, 0x56, 0, 4},
4441 {38, 0x56, 0, 6},
4442 {40, 0x56, 0, 8},
4443 {44, 0x57, 0, 0},
4444 {46, 0x57, 0, 2},
4445 {48, 0x57, 0, 4},
4446 {52, 0x57, 0, 8},
4447 {54, 0x57, 0, 10},
4448 {56, 0x58, 0, 0},
4449 {60, 0x58, 0, 4},
4450 {62, 0x58, 0, 6},
4451 {64, 0x58, 0, 8},
4452
4453 /* 802.11 HyperLan 2 */
4454 {100, 0x5b, 0, 8},
4455 {102, 0x5b, 0, 10},
4456 {104, 0x5c, 0, 0},
4457 {108, 0x5c, 0, 4},
4458 {110, 0x5c, 0, 6},
4459 {112, 0x5c, 0, 8},
4460 {116, 0x5d, 0, 0},
4461 {118, 0x5d, 0, 2},
4462 {120, 0x5d, 0, 4},
4463 {124, 0x5d, 0, 8},
4464 {126, 0x5d, 0, 10},
4465 {128, 0x5e, 0, 0},
4466 {132, 0x5e, 0, 4},
4467 {134, 0x5e, 0, 6},
4468 {136, 0x5e, 0, 8},
4469 {140, 0x5f, 0, 0},
4470
4471 /* 802.11 UNII */
4472 {149, 0x5f, 0, 9},
4473 {151, 0x5f, 0, 11},
4474 {153, 0x60, 0, 1},
4475 {157, 0x60, 0, 5},
4476 {159, 0x60, 0, 7},
4477 {161, 0x60, 0, 9},
4478 {165, 0x61, 0, 1},
4479 {167, 0x61, 0, 3},
4480 {169, 0x61, 0, 5},
4481 {171, 0x61, 0, 7},
4482 {173, 0x61, 0, 9},
4483 };
4484
4485 int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
4486 {
4487 struct hw_mode_spec *spec = &rt2x00dev->spec;
4488 struct channel_info *info;
4489 char *default_power1;
4490 char *default_power2;
4491 unsigned int i;
4492 u16 eeprom;
4493
4494 /*
4495 * Disable powersaving as default on PCI devices.
4496 */
4497 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
4498 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
4499
4500 /*
4501 * Initialize all hw fields.
4502 */
4503 rt2x00dev->hw->flags =
4504 IEEE80211_HW_SIGNAL_DBM |
4505 IEEE80211_HW_SUPPORTS_PS |
4506 IEEE80211_HW_PS_NULLFUNC_STACK |
4507 IEEE80211_HW_AMPDU_AGGREGATION |
4508 IEEE80211_HW_REPORTS_TX_ACK_STATUS;
4509
4510 /*
4511 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
4512 * unless we are capable of sending the buffered frames out after the
4513 * DTIM transmission using rt2x00lib_beacondone. This will send out
4514 * multicast and broadcast traffic immediately instead of buffering it
4515 * infinitly and thus dropping it after some time.
4516 */
4517 if (!rt2x00_is_usb(rt2x00dev))
4518 rt2x00dev->hw->flags |=
4519 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
4520
4521 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
4522 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
4523 rt2x00_eeprom_addr(rt2x00dev,
4524 EEPROM_MAC_ADDR_0));
4525
4526 /*
4527 * As rt2800 has a global fallback table we cannot specify
4528 * more then one tx rate per frame but since the hw will
4529 * try several rates (based on the fallback table) we should
4530 * initialize max_report_rates to the maximum number of rates
4531 * we are going to try. Otherwise mac80211 will truncate our
4532 * reported tx rates and the rc algortihm will end up with
4533 * incorrect data.
4534 */
4535 rt2x00dev->hw->max_rates = 1;
4536 rt2x00dev->hw->max_report_rates = 7;
4537 rt2x00dev->hw->max_rate_tries = 1;
4538
4539 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
4540
4541 /*
4542 * Initialize hw_mode information.
4543 */
4544 spec->supported_bands = SUPPORT_BAND_2GHZ;
4545 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
4546
4547 if (rt2x00_rf(rt2x00dev, RF2820) ||
4548 rt2x00_rf(rt2x00dev, RF2720)) {
4549 spec->num_channels = 14;
4550 spec->channels = rf_vals;
4551 } else if (rt2x00_rf(rt2x00dev, RF2850) ||
4552 rt2x00_rf(rt2x00dev, RF2750)) {
4553 spec->supported_bands |= SUPPORT_BAND_5GHZ;
4554 spec->num_channels = ARRAY_SIZE(rf_vals);
4555 spec->channels = rf_vals;
4556 } else if (rt2x00_rf(rt2x00dev, RF3020) ||
4557 rt2x00_rf(rt2x00dev, RF2020) ||
4558 rt2x00_rf(rt2x00dev, RF3021) ||
4559 rt2x00_rf(rt2x00dev, RF3022) ||
4560 rt2x00_rf(rt2x00dev, RF3320) ||
4561 rt2x00_rf(rt2x00dev, RF5370) ||
4562 rt2x00_rf(rt2x00dev, RF5372) ||
4563 rt2x00_rf(rt2x00dev, RF5390)) {
4564 spec->num_channels = 14;
4565 spec->channels = rf_vals_3x;
4566 } else if (rt2x00_rf(rt2x00dev, RF3052)) {
4567 spec->supported_bands |= SUPPORT_BAND_5GHZ;
4568 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
4569 spec->channels = rf_vals_3x;
4570 }
4571
4572 /*
4573 * Initialize HT information.
4574 */
4575 if (!rt2x00_rf(rt2x00dev, RF2020))
4576 spec->ht.ht_supported = true;
4577 else
4578 spec->ht.ht_supported = false;
4579
4580 spec->ht.cap =
4581 IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
4582 IEEE80211_HT_CAP_GRN_FLD |
4583 IEEE80211_HT_CAP_SGI_20 |
4584 IEEE80211_HT_CAP_SGI_40;
4585
4586 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) >= 2)
4587 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
4588
4589 spec->ht.cap |=
4590 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) <<
4591 IEEE80211_HT_CAP_RX_STBC_SHIFT;
4592
4593 spec->ht.ampdu_factor = 3;
4594 spec->ht.ampdu_density = 4;
4595 spec->ht.mcs.tx_params =
4596 IEEE80211_HT_MCS_TX_DEFINED |
4597 IEEE80211_HT_MCS_TX_RX_DIFF |
4598 ((rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) - 1) <<
4599 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
4600
4601 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH)) {
4602 case 3:
4603 spec->ht.mcs.rx_mask[2] = 0xff;
4604 case 2:
4605 spec->ht.mcs.rx_mask[1] = 0xff;
4606 case 1:
4607 spec->ht.mcs.rx_mask[0] = 0xff;
4608 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
4609 break;
4610 }
4611
4612 /*
4613 * Create channel information array
4614 */
4615 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
4616 if (!info)
4617 return -ENOMEM;
4618
4619 spec->channels_info = info;
4620
4621 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
4622 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
4623
4624 for (i = 0; i < 14; i++) {
4625 info[i].default_power1 = default_power1[i];
4626 info[i].default_power2 = default_power2[i];
4627 }
4628
4629 if (spec->num_channels > 14) {
4630 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
4631 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
4632
4633 for (i = 14; i < spec->num_channels; i++) {
4634 info[i].default_power1 = default_power1[i];
4635 info[i].default_power2 = default_power2[i];
4636 }
4637 }
4638
4639 switch (rt2x00dev->chip.rf) {
4640 case RF2020:
4641 case RF3020:
4642 case RF3021:
4643 case RF3022:
4644 case RF3320:
4645 case RF3052:
4646 case RF5370:
4647 case RF5372:
4648 case RF5390:
4649 __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags);
4650 break;
4651 }
4652
4653 return 0;
4654 }
4655 EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode);
4656
4657 /*
4658 * IEEE80211 stack callback functions.
4659 */
4660 void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
4661 u16 *iv16)
4662 {
4663 struct rt2x00_dev *rt2x00dev = hw->priv;
4664 struct mac_iveiv_entry iveiv_entry;
4665 u32 offset;
4666
4667 offset = MAC_IVEIV_ENTRY(hw_key_idx);
4668 rt2800_register_multiread(rt2x00dev, offset,
4669 &iveiv_entry, sizeof(iveiv_entry));
4670
4671 memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
4672 memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
4673 }
4674 EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
4675
4676 int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
4677 {
4678 struct rt2x00_dev *rt2x00dev = hw->priv;
4679 u32 reg;
4680 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
4681
4682 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
4683 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
4684 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
4685
4686 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
4687 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
4688 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
4689
4690 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
4691 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
4692 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
4693
4694 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
4695 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
4696 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
4697
4698 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
4699 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
4700 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
4701
4702 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
4703 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
4704 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
4705
4706 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
4707 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
4708 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
4709
4710 return 0;
4711 }
4712 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
4713
4714 int rt2800_conf_tx(struct ieee80211_hw *hw,
4715 struct ieee80211_vif *vif, u16 queue_idx,
4716 const struct ieee80211_tx_queue_params *params)
4717 {
4718 struct rt2x00_dev *rt2x00dev = hw->priv;
4719 struct data_queue *queue;
4720 struct rt2x00_field32 field;
4721 int retval;
4722 u32 reg;
4723 u32 offset;
4724
4725 /*
4726 * First pass the configuration through rt2x00lib, that will
4727 * update the queue settings and validate the input. After that
4728 * we are free to update the registers based on the value
4729 * in the queue parameter.
4730 */
4731 retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params);
4732 if (retval)
4733 return retval;
4734
4735 /*
4736 * We only need to perform additional register initialization
4737 * for WMM queues/
4738 */
4739 if (queue_idx >= 4)
4740 return 0;
4741
4742 queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
4743
4744 /* Update WMM TXOP register */
4745 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
4746 field.bit_offset = (queue_idx & 1) * 16;
4747 field.bit_mask = 0xffff << field.bit_offset;
4748
4749 rt2800_register_read(rt2x00dev, offset, &reg);
4750 rt2x00_set_field32(&reg, field, queue->txop);
4751 rt2800_register_write(rt2x00dev, offset, reg);
4752
4753 /* Update WMM registers */
4754 field.bit_offset = queue_idx * 4;
4755 field.bit_mask = 0xf << field.bit_offset;
4756
4757 rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
4758 rt2x00_set_field32(&reg, field, queue->aifs);
4759 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
4760
4761 rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
4762 rt2x00_set_field32(&reg, field, queue->cw_min);
4763 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
4764
4765 rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
4766 rt2x00_set_field32(&reg, field, queue->cw_max);
4767 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
4768
4769 /* Update EDCA registers */
4770 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
4771
4772 rt2800_register_read(rt2x00dev, offset, &reg);
4773 rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
4774 rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
4775 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
4776 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
4777 rt2800_register_write(rt2x00dev, offset, reg);
4778
4779 return 0;
4780 }
4781 EXPORT_SYMBOL_GPL(rt2800_conf_tx);
4782
4783 u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
4784 {
4785 struct rt2x00_dev *rt2x00dev = hw->priv;
4786 u64 tsf;
4787 u32 reg;
4788
4789 rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
4790 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
4791 rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
4792 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
4793
4794 return tsf;
4795 }
4796 EXPORT_SYMBOL_GPL(rt2800_get_tsf);
4797
4798 int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
4799 enum ieee80211_ampdu_mlme_action action,
4800 struct ieee80211_sta *sta, u16 tid, u16 *ssn,
4801 u8 buf_size)
4802 {
4803 struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv;
4804 int ret = 0;
4805
4806 /*
4807 * Don't allow aggregation for stations the hardware isn't aware
4808 * of because tx status reports for frames to an unknown station
4809 * always contain wcid=255 and thus we can't distinguish between
4810 * multiple stations which leads to unwanted situations when the
4811 * hw reorders frames due to aggregation.
4812 */
4813 if (sta_priv->wcid < 0)
4814 return 1;
4815
4816 switch (action) {
4817 case IEEE80211_AMPDU_RX_START:
4818 case IEEE80211_AMPDU_RX_STOP:
4819 /*
4820 * The hw itself takes care of setting up BlockAck mechanisms.
4821 * So, we only have to allow mac80211 to nagotiate a BlockAck
4822 * agreement. Once that is done, the hw will BlockAck incoming
4823 * AMPDUs without further setup.
4824 */
4825 break;
4826 case IEEE80211_AMPDU_TX_START:
4827 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
4828 break;
4829 case IEEE80211_AMPDU_TX_STOP:
4830 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
4831 break;
4832 case IEEE80211_AMPDU_TX_OPERATIONAL:
4833 break;
4834 default:
4835 WARNING((struct rt2x00_dev *)hw->priv, "Unknown AMPDU action\n");
4836 }
4837
4838 return ret;
4839 }
4840 EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
4841
4842 int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
4843 struct survey_info *survey)
4844 {
4845 struct rt2x00_dev *rt2x00dev = hw->priv;
4846 struct ieee80211_conf *conf = &hw->conf;
4847 u32 idle, busy, busy_ext;
4848
4849 if (idx != 0)
4850 return -ENOENT;
4851
4852 survey->channel = conf->channel;
4853
4854 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle);
4855 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy);
4856 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext);
4857
4858 if (idle || busy) {
4859 survey->filled = SURVEY_INFO_CHANNEL_TIME |
4860 SURVEY_INFO_CHANNEL_TIME_BUSY |
4861 SURVEY_INFO_CHANNEL_TIME_EXT_BUSY;
4862
4863 survey->channel_time = (idle + busy) / 1000;
4864 survey->channel_time_busy = busy / 1000;
4865 survey->channel_time_ext_busy = busy_ext / 1000;
4866 }
4867
4868 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
4869 survey->filled |= SURVEY_INFO_IN_USE;
4870
4871 return 0;
4872
4873 }
4874 EXPORT_SYMBOL_GPL(rt2800_get_survey);
4875
4876 MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
4877 MODULE_VERSION(DRV_VERSION);
4878 MODULE_DESCRIPTION("Ralink RT2800 library");
4879 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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