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Merge branch 'for-airlied' of git://people.freedesktop.org/~danvet/drm-intel into...
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt2800lib.c
1 /*
2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
3 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
4 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
5 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
6
7 Based on the original rt2800pci.c and rt2800usb.c.
8 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
9 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
10 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
11 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
12 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
13 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
14 <http://rt2x00.serialmonkey.com>
15
16 This program is free software; you can redistribute it and/or modify
17 it under the terms of the GNU General Public License as published by
18 the Free Software Foundation; either version 2 of the License, or
19 (at your option) any later version.
20
21 This program is distributed in the hope that it will be useful,
22 but WITHOUT ANY WARRANTY; without even the implied warranty of
23 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 GNU General Public License for more details.
25
26 You should have received a copy of the GNU General Public License
27 along with this program; if not, write to the
28 Free Software Foundation, Inc.,
29 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32 /*
33 Module: rt2800lib
34 Abstract: rt2800 generic device routines.
35 */
36
37 #include <linux/crc-ccitt.h>
38 #include <linux/kernel.h>
39 #include <linux/module.h>
40 #include <linux/slab.h>
41
42 #include "rt2x00.h"
43 #include "rt2800lib.h"
44 #include "rt2800.h"
45
46 /*
47 * Register access.
48 * All access to the CSR registers will go through the methods
49 * rt2800_register_read and rt2800_register_write.
50 * BBP and RF register require indirect register access,
51 * and use the CSR registers BBPCSR and RFCSR to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
55 * between each attampt. When the busy bit is still set at that time,
56 * the access attempt is considered to have failed,
57 * and we will print an error.
58 * The _lock versions must be used if you already hold the csr_mutex
59 */
60 #define WAIT_FOR_BBP(__dev, __reg) \
61 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
62 #define WAIT_FOR_RFCSR(__dev, __reg) \
63 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
64 #define WAIT_FOR_RF(__dev, __reg) \
65 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
66 #define WAIT_FOR_MCU(__dev, __reg) \
67 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
68 H2M_MAILBOX_CSR_OWNER, (__reg))
69
70 static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
71 {
72 /* check for rt2872 on SoC */
73 if (!rt2x00_is_soc(rt2x00dev) ||
74 !rt2x00_rt(rt2x00dev, RT2872))
75 return false;
76
77 /* we know for sure that these rf chipsets are used on rt305x boards */
78 if (rt2x00_rf(rt2x00dev, RF3020) ||
79 rt2x00_rf(rt2x00dev, RF3021) ||
80 rt2x00_rf(rt2x00dev, RF3022))
81 return true;
82
83 NOTICE(rt2x00dev, "Unknown RF chipset on rt305x\n");
84 return false;
85 }
86
87 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
88 const unsigned int word, const u8 value)
89 {
90 u32 reg;
91
92 mutex_lock(&rt2x00dev->csr_mutex);
93
94 /*
95 * Wait until the BBP becomes available, afterwards we
96 * can safely write the new data into the register.
97 */
98 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
99 reg = 0;
100 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
101 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
102 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
103 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
104 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
105
106 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
107 }
108
109 mutex_unlock(&rt2x00dev->csr_mutex);
110 }
111
112 static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
113 const unsigned int word, u8 *value)
114 {
115 u32 reg;
116
117 mutex_lock(&rt2x00dev->csr_mutex);
118
119 /*
120 * Wait until the BBP becomes available, afterwards we
121 * can safely write the read request into the register.
122 * After the data has been written, we wait until hardware
123 * returns the correct value, if at any time the register
124 * doesn't become available in time, reg will be 0xffffffff
125 * which means we return 0xff to the caller.
126 */
127 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
128 reg = 0;
129 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
130 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
131 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
132 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
133
134 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
135
136 WAIT_FOR_BBP(rt2x00dev, &reg);
137 }
138
139 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
140
141 mutex_unlock(&rt2x00dev->csr_mutex);
142 }
143
144 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
145 const unsigned int word, const u8 value)
146 {
147 u32 reg;
148
149 mutex_lock(&rt2x00dev->csr_mutex);
150
151 /*
152 * Wait until the RFCSR becomes available, afterwards we
153 * can safely write the new data into the register.
154 */
155 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
156 reg = 0;
157 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
158 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
159 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
160 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
161
162 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
163 }
164
165 mutex_unlock(&rt2x00dev->csr_mutex);
166 }
167
168 static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
169 const unsigned int word, u8 *value)
170 {
171 u32 reg;
172
173 mutex_lock(&rt2x00dev->csr_mutex);
174
175 /*
176 * Wait until the RFCSR becomes available, afterwards we
177 * can safely write the read request into the register.
178 * After the data has been written, we wait until hardware
179 * returns the correct value, if at any time the register
180 * doesn't become available in time, reg will be 0xffffffff
181 * which means we return 0xff to the caller.
182 */
183 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
184 reg = 0;
185 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
186 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
187 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
188
189 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
190
191 WAIT_FOR_RFCSR(rt2x00dev, &reg);
192 }
193
194 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
195
196 mutex_unlock(&rt2x00dev->csr_mutex);
197 }
198
199 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
200 const unsigned int word, const u32 value)
201 {
202 u32 reg;
203
204 mutex_lock(&rt2x00dev->csr_mutex);
205
206 /*
207 * Wait until the RF becomes available, afterwards we
208 * can safely write the new data into the register.
209 */
210 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
211 reg = 0;
212 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
213 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
214 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
215 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
216
217 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
218 rt2x00_rf_write(rt2x00dev, word, value);
219 }
220
221 mutex_unlock(&rt2x00dev->csr_mutex);
222 }
223
224 static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev)
225 {
226 u32 reg;
227 int i, count;
228
229 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
230 if (rt2x00_get_field32(reg, WLAN_EN))
231 return 0;
232
233 rt2x00_set_field32(&reg, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff);
234 rt2x00_set_field32(&reg, FRC_WL_ANT_SET, 1);
235 rt2x00_set_field32(&reg, WLAN_CLK_EN, 0);
236 rt2x00_set_field32(&reg, WLAN_EN, 1);
237 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
238
239 udelay(REGISTER_BUSY_DELAY);
240
241 count = 0;
242 do {
243 /*
244 * Check PLL_LD & XTAL_RDY.
245 */
246 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
247 rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
248 if (rt2x00_get_field32(reg, PLL_LD) &&
249 rt2x00_get_field32(reg, XTAL_RDY))
250 break;
251 udelay(REGISTER_BUSY_DELAY);
252 }
253
254 if (i >= REGISTER_BUSY_COUNT) {
255
256 if (count >= 10)
257 return -EIO;
258
259 rt2800_register_write(rt2x00dev, 0x58, 0x018);
260 udelay(REGISTER_BUSY_DELAY);
261 rt2800_register_write(rt2x00dev, 0x58, 0x418);
262 udelay(REGISTER_BUSY_DELAY);
263 rt2800_register_write(rt2x00dev, 0x58, 0x618);
264 udelay(REGISTER_BUSY_DELAY);
265 count++;
266 } else {
267 count = 0;
268 }
269
270 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
271 rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 0);
272 rt2x00_set_field32(&reg, WLAN_CLK_EN, 1);
273 rt2x00_set_field32(&reg, WLAN_RESET, 1);
274 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
275 udelay(10);
276 rt2x00_set_field32(&reg, WLAN_RESET, 0);
277 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
278 udelay(10);
279 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, 0x7fffffff);
280 } while (count != 0);
281
282 return 0;
283 }
284
285 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
286 const u8 command, const u8 token,
287 const u8 arg0, const u8 arg1)
288 {
289 u32 reg;
290
291 /*
292 * SOC devices don't support MCU requests.
293 */
294 if (rt2x00_is_soc(rt2x00dev))
295 return;
296
297 mutex_lock(&rt2x00dev->csr_mutex);
298
299 /*
300 * Wait until the MCU becomes available, afterwards we
301 * can safely write the new data into the register.
302 */
303 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
304 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
305 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
306 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
307 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
308 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
309
310 reg = 0;
311 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
312 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
313 }
314
315 mutex_unlock(&rt2x00dev->csr_mutex);
316 }
317 EXPORT_SYMBOL_GPL(rt2800_mcu_request);
318
319 int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
320 {
321 unsigned int i = 0;
322 u32 reg;
323
324 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
325 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
326 if (reg && reg != ~0)
327 return 0;
328 msleep(1);
329 }
330
331 ERROR(rt2x00dev, "Unstable hardware.\n");
332 return -EBUSY;
333 }
334 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
335
336 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
337 {
338 unsigned int i;
339 u32 reg;
340
341 /*
342 * Some devices are really slow to respond here. Wait a whole second
343 * before timing out.
344 */
345 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
346 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
347 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
348 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
349 return 0;
350
351 msleep(10);
352 }
353
354 ERROR(rt2x00dev, "WPDMA TX/RX busy [0x%08x].\n", reg);
355 return -EACCES;
356 }
357 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
358
359 void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev)
360 {
361 u32 reg;
362
363 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
364 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
365 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
366 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
367 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
368 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
369 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
370 }
371 EXPORT_SYMBOL_GPL(rt2800_disable_wpdma);
372
373 static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
374 {
375 u16 fw_crc;
376 u16 crc;
377
378 /*
379 * The last 2 bytes in the firmware array are the crc checksum itself,
380 * this means that we should never pass those 2 bytes to the crc
381 * algorithm.
382 */
383 fw_crc = (data[len - 2] << 8 | data[len - 1]);
384
385 /*
386 * Use the crc ccitt algorithm.
387 * This will return the same value as the legacy driver which
388 * used bit ordering reversion on the both the firmware bytes
389 * before input input as well as on the final output.
390 * Obviously using crc ccitt directly is much more efficient.
391 */
392 crc = crc_ccitt(~0, data, len - 2);
393
394 /*
395 * There is a small difference between the crc-itu-t + bitrev and
396 * the crc-ccitt crc calculation. In the latter method the 2 bytes
397 * will be swapped, use swab16 to convert the crc to the correct
398 * value.
399 */
400 crc = swab16(crc);
401
402 return fw_crc == crc;
403 }
404
405 int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
406 const u8 *data, const size_t len)
407 {
408 size_t offset = 0;
409 size_t fw_len;
410 bool multiple;
411
412 /*
413 * PCI(e) & SOC devices require firmware with a length
414 * of 8kb. USB devices require firmware files with a length
415 * of 4kb. Certain USB chipsets however require different firmware,
416 * which Ralink only provides attached to the original firmware
417 * file. Thus for USB devices, firmware files have a length
418 * which is a multiple of 4kb. The firmware for rt3290 chip also
419 * have a length which is a multiple of 4kb.
420 */
421 if (rt2x00_is_usb(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3290))
422 fw_len = 4096;
423 else
424 fw_len = 8192;
425
426 multiple = true;
427 /*
428 * Validate the firmware length
429 */
430 if (len != fw_len && (!multiple || (len % fw_len) != 0))
431 return FW_BAD_LENGTH;
432
433 /*
434 * Check if the chipset requires one of the upper parts
435 * of the firmware.
436 */
437 if (rt2x00_is_usb(rt2x00dev) &&
438 !rt2x00_rt(rt2x00dev, RT2860) &&
439 !rt2x00_rt(rt2x00dev, RT2872) &&
440 !rt2x00_rt(rt2x00dev, RT3070) &&
441 ((len / fw_len) == 1))
442 return FW_BAD_VERSION;
443
444 /*
445 * 8kb firmware files must be checked as if it were
446 * 2 separate firmware files.
447 */
448 while (offset < len) {
449 if (!rt2800_check_firmware_crc(data + offset, fw_len))
450 return FW_BAD_CRC;
451
452 offset += fw_len;
453 }
454
455 return FW_OK;
456 }
457 EXPORT_SYMBOL_GPL(rt2800_check_firmware);
458
459 int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
460 const u8 *data, const size_t len)
461 {
462 unsigned int i;
463 u32 reg;
464 int retval;
465
466 if (rt2x00_rt(rt2x00dev, RT3290)) {
467 retval = rt2800_enable_wlan_rt3290(rt2x00dev);
468 if (retval)
469 return -EBUSY;
470 }
471
472 /*
473 * If driver doesn't wake up firmware here,
474 * rt2800_load_firmware will hang forever when interface is up again.
475 */
476 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
477
478 /*
479 * Wait for stable hardware.
480 */
481 if (rt2800_wait_csr_ready(rt2x00dev))
482 return -EBUSY;
483
484 if (rt2x00_is_pci(rt2x00dev)) {
485 if (rt2x00_rt(rt2x00dev, RT3290) ||
486 rt2x00_rt(rt2x00dev, RT3572) ||
487 rt2x00_rt(rt2x00dev, RT5390) ||
488 rt2x00_rt(rt2x00dev, RT5392)) {
489 rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);
490 rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
491 rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
492 rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
493 }
494 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
495 }
496
497 rt2800_disable_wpdma(rt2x00dev);
498
499 /*
500 * Write firmware to the device.
501 */
502 rt2800_drv_write_firmware(rt2x00dev, data, len);
503
504 /*
505 * Wait for device to stabilize.
506 */
507 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
508 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
509 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
510 break;
511 msleep(1);
512 }
513
514 if (i == REGISTER_BUSY_COUNT) {
515 ERROR(rt2x00dev, "PBF system register not ready.\n");
516 return -EBUSY;
517 }
518
519 /*
520 * Disable DMA, will be reenabled later when enabling
521 * the radio.
522 */
523 rt2800_disable_wpdma(rt2x00dev);
524
525 /*
526 * Initialize firmware.
527 */
528 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
529 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
530 if (rt2x00_is_usb(rt2x00dev))
531 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
532 msleep(1);
533
534 return 0;
535 }
536 EXPORT_SYMBOL_GPL(rt2800_load_firmware);
537
538 void rt2800_write_tx_data(struct queue_entry *entry,
539 struct txentry_desc *txdesc)
540 {
541 __le32 *txwi = rt2800_drv_get_txwi(entry);
542 u32 word;
543
544 /*
545 * Initialize TX Info descriptor
546 */
547 rt2x00_desc_read(txwi, 0, &word);
548 rt2x00_set_field32(&word, TXWI_W0_FRAG,
549 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
550 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
551 test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
552 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
553 rt2x00_set_field32(&word, TXWI_W0_TS,
554 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
555 rt2x00_set_field32(&word, TXWI_W0_AMPDU,
556 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
557 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
558 txdesc->u.ht.mpdu_density);
559 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
560 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
561 rt2x00_set_field32(&word, TXWI_W0_BW,
562 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
563 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
564 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
565 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
566 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
567 rt2x00_desc_write(txwi, 0, word);
568
569 rt2x00_desc_read(txwi, 1, &word);
570 rt2x00_set_field32(&word, TXWI_W1_ACK,
571 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
572 rt2x00_set_field32(&word, TXWI_W1_NSEQ,
573 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
574 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
575 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
576 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
577 txdesc->key_idx : txdesc->u.ht.wcid);
578 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
579 txdesc->length);
580 rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
581 rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
582 rt2x00_desc_write(txwi, 1, word);
583
584 /*
585 * Always write 0 to IV/EIV fields, hardware will insert the IV
586 * from the IVEIV register when TXD_W3_WIV is set to 0.
587 * When TXD_W3_WIV is set to 1 it will use the IV data
588 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
589 * crypto entry in the registers should be used to encrypt the frame.
590 */
591 _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
592 _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
593 }
594 EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
595
596 static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
597 {
598 s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
599 s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
600 s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
601 u16 eeprom;
602 u8 offset0;
603 u8 offset1;
604 u8 offset2;
605
606 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
607 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
608 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
609 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
610 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
611 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
612 } else {
613 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
614 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
615 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
616 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
617 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
618 }
619
620 /*
621 * Convert the value from the descriptor into the RSSI value
622 * If the value in the descriptor is 0, it is considered invalid
623 * and the default (extremely low) rssi value is assumed
624 */
625 rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
626 rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
627 rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
628
629 /*
630 * mac80211 only accepts a single RSSI value. Calculating the
631 * average doesn't deliver a fair answer either since -60:-60 would
632 * be considered equally good as -50:-70 while the second is the one
633 * which gives less energy...
634 */
635 rssi0 = max(rssi0, rssi1);
636 return (int)max(rssi0, rssi2);
637 }
638
639 void rt2800_process_rxwi(struct queue_entry *entry,
640 struct rxdone_entry_desc *rxdesc)
641 {
642 __le32 *rxwi = (__le32 *) entry->skb->data;
643 u32 word;
644
645 rt2x00_desc_read(rxwi, 0, &word);
646
647 rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
648 rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
649
650 rt2x00_desc_read(rxwi, 1, &word);
651
652 if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
653 rxdesc->flags |= RX_FLAG_SHORT_GI;
654
655 if (rt2x00_get_field32(word, RXWI_W1_BW))
656 rxdesc->flags |= RX_FLAG_40MHZ;
657
658 /*
659 * Detect RX rate, always use MCS as signal type.
660 */
661 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
662 rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
663 rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
664
665 /*
666 * Mask of 0x8 bit to remove the short preamble flag.
667 */
668 if (rxdesc->rate_mode == RATE_MODE_CCK)
669 rxdesc->signal &= ~0x8;
670
671 rt2x00_desc_read(rxwi, 2, &word);
672
673 /*
674 * Convert descriptor AGC value to RSSI value.
675 */
676 rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
677
678 /*
679 * Remove RXWI descriptor from start of buffer.
680 */
681 skb_pull(entry->skb, RXWI_DESC_SIZE);
682 }
683 EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
684
685 void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi)
686 {
687 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
688 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
689 struct txdone_entry_desc txdesc;
690 u32 word;
691 u16 mcs, real_mcs;
692 int aggr, ampdu;
693
694 /*
695 * Obtain the status about this packet.
696 */
697 txdesc.flags = 0;
698 rt2x00_desc_read(txwi, 0, &word);
699
700 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
701 ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
702
703 real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
704 aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
705
706 /*
707 * If a frame was meant to be sent as a single non-aggregated MPDU
708 * but ended up in an aggregate the used tx rate doesn't correlate
709 * with the one specified in the TXWI as the whole aggregate is sent
710 * with the same rate.
711 *
712 * For example: two frames are sent to rt2x00, the first one sets
713 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
714 * and requests MCS15. If the hw aggregates both frames into one
715 * AMDPU the tx status for both frames will contain MCS7 although
716 * the frame was sent successfully.
717 *
718 * Hence, replace the requested rate with the real tx rate to not
719 * confuse the rate control algortihm by providing clearly wrong
720 * data.
721 */
722 if (unlikely(aggr == 1 && ampdu == 0 && real_mcs != mcs)) {
723 skbdesc->tx_rate_idx = real_mcs;
724 mcs = real_mcs;
725 }
726
727 if (aggr == 1 || ampdu == 1)
728 __set_bit(TXDONE_AMPDU, &txdesc.flags);
729
730 /*
731 * Ralink has a retry mechanism using a global fallback
732 * table. We setup this fallback table to try the immediate
733 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
734 * always contains the MCS used for the last transmission, be
735 * it successful or not.
736 */
737 if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
738 /*
739 * Transmission succeeded. The number of retries is
740 * mcs - real_mcs
741 */
742 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
743 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
744 } else {
745 /*
746 * Transmission failed. The number of retries is
747 * always 7 in this case (for a total number of 8
748 * frames sent).
749 */
750 __set_bit(TXDONE_FAILURE, &txdesc.flags);
751 txdesc.retry = rt2x00dev->long_retry;
752 }
753
754 /*
755 * the frame was retried at least once
756 * -> hw used fallback rates
757 */
758 if (txdesc.retry)
759 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
760
761 rt2x00lib_txdone(entry, &txdesc);
762 }
763 EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
764
765 void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
766 {
767 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
768 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
769 unsigned int beacon_base;
770 unsigned int padding_len;
771 u32 orig_reg, reg;
772
773 /*
774 * Disable beaconing while we are reloading the beacon data,
775 * otherwise we might be sending out invalid data.
776 */
777 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
778 orig_reg = reg;
779 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
780 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
781
782 /*
783 * Add space for the TXWI in front of the skb.
784 */
785 memset(skb_push(entry->skb, TXWI_DESC_SIZE), 0, TXWI_DESC_SIZE);
786
787 /*
788 * Register descriptor details in skb frame descriptor.
789 */
790 skbdesc->flags |= SKBDESC_DESC_IN_SKB;
791 skbdesc->desc = entry->skb->data;
792 skbdesc->desc_len = TXWI_DESC_SIZE;
793
794 /*
795 * Add the TXWI for the beacon to the skb.
796 */
797 rt2800_write_tx_data(entry, txdesc);
798
799 /*
800 * Dump beacon to userspace through debugfs.
801 */
802 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
803
804 /*
805 * Write entire beacon with TXWI and padding to register.
806 */
807 padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
808 if (padding_len && skb_pad(entry->skb, padding_len)) {
809 ERROR(rt2x00dev, "Failure padding beacon, aborting\n");
810 /* skb freed by skb_pad() on failure */
811 entry->skb = NULL;
812 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
813 return;
814 }
815
816 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
817 rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
818 entry->skb->len + padding_len);
819
820 /*
821 * Enable beaconing again.
822 */
823 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
824 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
825
826 /*
827 * Clean up beacon skb.
828 */
829 dev_kfree_skb_any(entry->skb);
830 entry->skb = NULL;
831 }
832 EXPORT_SYMBOL_GPL(rt2800_write_beacon);
833
834 static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
835 unsigned int beacon_base)
836 {
837 int i;
838
839 /*
840 * For the Beacon base registers we only need to clear
841 * the whole TXWI which (when set to 0) will invalidate
842 * the entire beacon.
843 */
844 for (i = 0; i < TXWI_DESC_SIZE; i += sizeof(__le32))
845 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
846 }
847
848 void rt2800_clear_beacon(struct queue_entry *entry)
849 {
850 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
851 u32 reg;
852
853 /*
854 * Disable beaconing while we are reloading the beacon data,
855 * otherwise we might be sending out invalid data.
856 */
857 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
858 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
859 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
860
861 /*
862 * Clear beacon.
863 */
864 rt2800_clear_beacon_register(rt2x00dev,
865 HW_BEACON_OFFSET(entry->entry_idx));
866
867 /*
868 * Enabled beaconing again.
869 */
870 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
871 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
872 }
873 EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
874
875 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
876 const struct rt2x00debug rt2800_rt2x00debug = {
877 .owner = THIS_MODULE,
878 .csr = {
879 .read = rt2800_register_read,
880 .write = rt2800_register_write,
881 .flags = RT2X00DEBUGFS_OFFSET,
882 .word_base = CSR_REG_BASE,
883 .word_size = sizeof(u32),
884 .word_count = CSR_REG_SIZE / sizeof(u32),
885 },
886 .eeprom = {
887 .read = rt2x00_eeprom_read,
888 .write = rt2x00_eeprom_write,
889 .word_base = EEPROM_BASE,
890 .word_size = sizeof(u16),
891 .word_count = EEPROM_SIZE / sizeof(u16),
892 },
893 .bbp = {
894 .read = rt2800_bbp_read,
895 .write = rt2800_bbp_write,
896 .word_base = BBP_BASE,
897 .word_size = sizeof(u8),
898 .word_count = BBP_SIZE / sizeof(u8),
899 },
900 .rf = {
901 .read = rt2x00_rf_read,
902 .write = rt2800_rf_write,
903 .word_base = RF_BASE,
904 .word_size = sizeof(u32),
905 .word_count = RF_SIZE / sizeof(u32),
906 },
907 .rfcsr = {
908 .read = rt2800_rfcsr_read,
909 .write = rt2800_rfcsr_write,
910 .word_base = RFCSR_BASE,
911 .word_size = sizeof(u8),
912 .word_count = RFCSR_SIZE / sizeof(u8),
913 },
914 };
915 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
916 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
917
918 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
919 {
920 u32 reg;
921
922 if (rt2x00_rt(rt2x00dev, RT3290)) {
923 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
924 return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0);
925 } else {
926 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
927 return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
928 }
929 }
930 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
931
932 #ifdef CONFIG_RT2X00_LIB_LEDS
933 static void rt2800_brightness_set(struct led_classdev *led_cdev,
934 enum led_brightness brightness)
935 {
936 struct rt2x00_led *led =
937 container_of(led_cdev, struct rt2x00_led, led_dev);
938 unsigned int enabled = brightness != LED_OFF;
939 unsigned int bg_mode =
940 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
941 unsigned int polarity =
942 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
943 EEPROM_FREQ_LED_POLARITY);
944 unsigned int ledmode =
945 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
946 EEPROM_FREQ_LED_MODE);
947 u32 reg;
948
949 /* Check for SoC (SOC devices don't support MCU requests) */
950 if (rt2x00_is_soc(led->rt2x00dev)) {
951 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
952
953 /* Set LED Polarity */
954 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, polarity);
955
956 /* Set LED Mode */
957 if (led->type == LED_TYPE_RADIO) {
958 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE,
959 enabled ? 3 : 0);
960 } else if (led->type == LED_TYPE_ASSOC) {
961 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE,
962 enabled ? 3 : 0);
963 } else if (led->type == LED_TYPE_QUALITY) {
964 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE,
965 enabled ? 3 : 0);
966 }
967
968 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
969
970 } else {
971 if (led->type == LED_TYPE_RADIO) {
972 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
973 enabled ? 0x20 : 0);
974 } else if (led->type == LED_TYPE_ASSOC) {
975 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
976 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
977 } else if (led->type == LED_TYPE_QUALITY) {
978 /*
979 * The brightness is divided into 6 levels (0 - 5),
980 * The specs tell us the following levels:
981 * 0, 1 ,3, 7, 15, 31
982 * to determine the level in a simple way we can simply
983 * work with bitshifting:
984 * (1 << level) - 1
985 */
986 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
987 (1 << brightness / (LED_FULL / 6)) - 1,
988 polarity);
989 }
990 }
991 }
992
993 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
994 struct rt2x00_led *led, enum led_type type)
995 {
996 led->rt2x00dev = rt2x00dev;
997 led->type = type;
998 led->led_dev.brightness_set = rt2800_brightness_set;
999 led->flags = LED_INITIALIZED;
1000 }
1001 #endif /* CONFIG_RT2X00_LIB_LEDS */
1002
1003 /*
1004 * Configuration handlers.
1005 */
1006 static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev,
1007 const u8 *address,
1008 int wcid)
1009 {
1010 struct mac_wcid_entry wcid_entry;
1011 u32 offset;
1012
1013 offset = MAC_WCID_ENTRY(wcid);
1014
1015 memset(&wcid_entry, 0xff, sizeof(wcid_entry));
1016 if (address)
1017 memcpy(wcid_entry.mac, address, ETH_ALEN);
1018
1019 rt2800_register_multiwrite(rt2x00dev, offset,
1020 &wcid_entry, sizeof(wcid_entry));
1021 }
1022
1023 static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid)
1024 {
1025 u32 offset;
1026 offset = MAC_WCID_ATTR_ENTRY(wcid);
1027 rt2800_register_write(rt2x00dev, offset, 0);
1028 }
1029
1030 static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev,
1031 int wcid, u32 bssidx)
1032 {
1033 u32 offset = MAC_WCID_ATTR_ENTRY(wcid);
1034 u32 reg;
1035
1036 /*
1037 * The BSS Idx numbers is split in a main value of 3 bits,
1038 * and a extended field for adding one additional bit to the value.
1039 */
1040 rt2800_register_read(rt2x00dev, offset, &reg);
1041 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7));
1042 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
1043 (bssidx & 0x8) >> 3);
1044 rt2800_register_write(rt2x00dev, offset, reg);
1045 }
1046
1047 static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev,
1048 struct rt2x00lib_crypto *crypto,
1049 struct ieee80211_key_conf *key)
1050 {
1051 struct mac_iveiv_entry iveiv_entry;
1052 u32 offset;
1053 u32 reg;
1054
1055 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
1056
1057 if (crypto->cmd == SET_KEY) {
1058 rt2800_register_read(rt2x00dev, offset, &reg);
1059 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
1060 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
1061 /*
1062 * Both the cipher as the BSS Idx numbers are split in a main
1063 * value of 3 bits, and a extended field for adding one additional
1064 * bit to the value.
1065 */
1066 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
1067 (crypto->cipher & 0x7));
1068 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
1069 (crypto->cipher & 0x8) >> 3);
1070 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
1071 rt2800_register_write(rt2x00dev, offset, reg);
1072 } else {
1073 /* Delete the cipher without touching the bssidx */
1074 rt2800_register_read(rt2x00dev, offset, &reg);
1075 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB, 0);
1076 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER, 0);
1077 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0);
1078 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
1079 rt2800_register_write(rt2x00dev, offset, reg);
1080 }
1081
1082 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
1083
1084 memset(&iveiv_entry, 0, sizeof(iveiv_entry));
1085 if ((crypto->cipher == CIPHER_TKIP) ||
1086 (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
1087 (crypto->cipher == CIPHER_AES))
1088 iveiv_entry.iv[3] |= 0x20;
1089 iveiv_entry.iv[3] |= key->keyidx << 6;
1090 rt2800_register_multiwrite(rt2x00dev, offset,
1091 &iveiv_entry, sizeof(iveiv_entry));
1092 }
1093
1094 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1095 struct rt2x00lib_crypto *crypto,
1096 struct ieee80211_key_conf *key)
1097 {
1098 struct hw_key_entry key_entry;
1099 struct rt2x00_field32 field;
1100 u32 offset;
1101 u32 reg;
1102
1103 if (crypto->cmd == SET_KEY) {
1104 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1105
1106 memcpy(key_entry.key, crypto->key,
1107 sizeof(key_entry.key));
1108 memcpy(key_entry.tx_mic, crypto->tx_mic,
1109 sizeof(key_entry.tx_mic));
1110 memcpy(key_entry.rx_mic, crypto->rx_mic,
1111 sizeof(key_entry.rx_mic));
1112
1113 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1114 rt2800_register_multiwrite(rt2x00dev, offset,
1115 &key_entry, sizeof(key_entry));
1116 }
1117
1118 /*
1119 * The cipher types are stored over multiple registers
1120 * starting with SHARED_KEY_MODE_BASE each word will have
1121 * 32 bits and contains the cipher types for 2 bssidx each.
1122 * Using the correct defines correctly will cause overhead,
1123 * so just calculate the correct offset.
1124 */
1125 field.bit_offset = 4 * (key->hw_key_idx % 8);
1126 field.bit_mask = 0x7 << field.bit_offset;
1127
1128 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1129
1130 rt2800_register_read(rt2x00dev, offset, &reg);
1131 rt2x00_set_field32(&reg, field,
1132 (crypto->cmd == SET_KEY) * crypto->cipher);
1133 rt2800_register_write(rt2x00dev, offset, reg);
1134
1135 /*
1136 * Update WCID information
1137 */
1138 rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx);
1139 rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx,
1140 crypto->bssidx);
1141 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1142
1143 return 0;
1144 }
1145 EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1146
1147 static inline int rt2800_find_wcid(struct rt2x00_dev *rt2x00dev)
1148 {
1149 struct mac_wcid_entry wcid_entry;
1150 int idx;
1151 u32 offset;
1152
1153 /*
1154 * Search for the first free WCID entry and return the corresponding
1155 * index.
1156 *
1157 * Make sure the WCID starts _after_ the last possible shared key
1158 * entry (>32).
1159 *
1160 * Since parts of the pairwise key table might be shared with
1161 * the beacon frame buffers 6 & 7 we should only write into the
1162 * first 222 entries.
1163 */
1164 for (idx = 33; idx <= 222; idx++) {
1165 offset = MAC_WCID_ENTRY(idx);
1166 rt2800_register_multiread(rt2x00dev, offset, &wcid_entry,
1167 sizeof(wcid_entry));
1168 if (is_broadcast_ether_addr(wcid_entry.mac))
1169 return idx;
1170 }
1171
1172 /*
1173 * Use -1 to indicate that we don't have any more space in the WCID
1174 * table.
1175 */
1176 return -1;
1177 }
1178
1179 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1180 struct rt2x00lib_crypto *crypto,
1181 struct ieee80211_key_conf *key)
1182 {
1183 struct hw_key_entry key_entry;
1184 u32 offset;
1185
1186 if (crypto->cmd == SET_KEY) {
1187 /*
1188 * Allow key configuration only for STAs that are
1189 * known by the hw.
1190 */
1191 if (crypto->wcid < 0)
1192 return -ENOSPC;
1193 key->hw_key_idx = crypto->wcid;
1194
1195 memcpy(key_entry.key, crypto->key,
1196 sizeof(key_entry.key));
1197 memcpy(key_entry.tx_mic, crypto->tx_mic,
1198 sizeof(key_entry.tx_mic));
1199 memcpy(key_entry.rx_mic, crypto->rx_mic,
1200 sizeof(key_entry.rx_mic));
1201
1202 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1203 rt2800_register_multiwrite(rt2x00dev, offset,
1204 &key_entry, sizeof(key_entry));
1205 }
1206
1207 /*
1208 * Update WCID information
1209 */
1210 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1211
1212 return 0;
1213 }
1214 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1215
1216 int rt2800_sta_add(struct rt2x00_dev *rt2x00dev, struct ieee80211_vif *vif,
1217 struct ieee80211_sta *sta)
1218 {
1219 int wcid;
1220 struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
1221
1222 /*
1223 * Find next free WCID.
1224 */
1225 wcid = rt2800_find_wcid(rt2x00dev);
1226
1227 /*
1228 * Store selected wcid even if it is invalid so that we can
1229 * later decide if the STA is uploaded into the hw.
1230 */
1231 sta_priv->wcid = wcid;
1232
1233 /*
1234 * No space left in the device, however, we can still communicate
1235 * with the STA -> No error.
1236 */
1237 if (wcid < 0)
1238 return 0;
1239
1240 /*
1241 * Clean up WCID attributes and write STA address to the device.
1242 */
1243 rt2800_delete_wcid_attr(rt2x00dev, wcid);
1244 rt2800_config_wcid(rt2x00dev, sta->addr, wcid);
1245 rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid,
1246 rt2x00lib_get_bssidx(rt2x00dev, vif));
1247 return 0;
1248 }
1249 EXPORT_SYMBOL_GPL(rt2800_sta_add);
1250
1251 int rt2800_sta_remove(struct rt2x00_dev *rt2x00dev, int wcid)
1252 {
1253 /*
1254 * Remove WCID entry, no need to clean the attributes as they will
1255 * get renewed when the WCID is reused.
1256 */
1257 rt2800_config_wcid(rt2x00dev, NULL, wcid);
1258
1259 return 0;
1260 }
1261 EXPORT_SYMBOL_GPL(rt2800_sta_remove);
1262
1263 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1264 const unsigned int filter_flags)
1265 {
1266 u32 reg;
1267
1268 /*
1269 * Start configuration steps.
1270 * Note that the version error will always be dropped
1271 * and broadcast frames will always be accepted since
1272 * there is no filter for it at this time.
1273 */
1274 rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
1275 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1276 !(filter_flags & FIF_FCSFAIL));
1277 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1278 !(filter_flags & FIF_PLCPFAIL));
1279 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1280 !(filter_flags & FIF_PROMISC_IN_BSS));
1281 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1282 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1283 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1284 !(filter_flags & FIF_ALLMULTI));
1285 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1286 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1287 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1288 !(filter_flags & FIF_CONTROL));
1289 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1290 !(filter_flags & FIF_CONTROL));
1291 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1292 !(filter_flags & FIF_CONTROL));
1293 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1294 !(filter_flags & FIF_CONTROL));
1295 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1296 !(filter_flags & FIF_CONTROL));
1297 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1298 !(filter_flags & FIF_PSPOLL));
1299 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA,
1300 !(filter_flags & FIF_CONTROL));
1301 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR,
1302 !(filter_flags & FIF_CONTROL));
1303 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1304 !(filter_flags & FIF_CONTROL));
1305 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1306 }
1307 EXPORT_SYMBOL_GPL(rt2800_config_filter);
1308
1309 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1310 struct rt2x00intf_conf *conf, const unsigned int flags)
1311 {
1312 u32 reg;
1313 bool update_bssid = false;
1314
1315 if (flags & CONFIG_UPDATE_TYPE) {
1316 /*
1317 * Enable synchronisation.
1318 */
1319 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1320 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
1321 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1322
1323 if (conf->sync == TSF_SYNC_AP_NONE) {
1324 /*
1325 * Tune beacon queue transmit parameters for AP mode
1326 */
1327 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1328 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 0);
1329 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 1);
1330 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1331 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 0);
1332 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1333 } else {
1334 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1335 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 4);
1336 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 2);
1337 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1338 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 16);
1339 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1340 }
1341 }
1342
1343 if (flags & CONFIG_UPDATE_MAC) {
1344 if (flags & CONFIG_UPDATE_TYPE &&
1345 conf->sync == TSF_SYNC_AP_NONE) {
1346 /*
1347 * The BSSID register has to be set to our own mac
1348 * address in AP mode.
1349 */
1350 memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1351 update_bssid = true;
1352 }
1353
1354 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1355 reg = le32_to_cpu(conf->mac[1]);
1356 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1357 conf->mac[1] = cpu_to_le32(reg);
1358 }
1359
1360 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1361 conf->mac, sizeof(conf->mac));
1362 }
1363
1364 if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
1365 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1366 reg = le32_to_cpu(conf->bssid[1]);
1367 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1368 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
1369 conf->bssid[1] = cpu_to_le32(reg);
1370 }
1371
1372 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1373 conf->bssid, sizeof(conf->bssid));
1374 }
1375 }
1376 EXPORT_SYMBOL_GPL(rt2800_config_intf);
1377
1378 static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1379 struct rt2x00lib_erp *erp)
1380 {
1381 bool any_sta_nongf = !!(erp->ht_opmode &
1382 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1383 u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1384 u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1385 u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1386 u32 reg;
1387
1388 /* default protection rate for HT20: OFDM 24M */
1389 mm20_rate = gf20_rate = 0x4004;
1390
1391 /* default protection rate for HT40: duplicate OFDM 24M */
1392 mm40_rate = gf40_rate = 0x4084;
1393
1394 switch (protection) {
1395 case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1396 /*
1397 * All STAs in this BSS are HT20/40 but there might be
1398 * STAs not supporting greenfield mode.
1399 * => Disable protection for HT transmissions.
1400 */
1401 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1402
1403 break;
1404 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1405 /*
1406 * All STAs in this BSS are HT20 or HT20/40 but there
1407 * might be STAs not supporting greenfield mode.
1408 * => Protect all HT40 transmissions.
1409 */
1410 mm20_mode = gf20_mode = 0;
1411 mm40_mode = gf40_mode = 2;
1412
1413 break;
1414 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1415 /*
1416 * Nonmember protection:
1417 * According to 802.11n we _should_ protect all
1418 * HT transmissions (but we don't have to).
1419 *
1420 * But if cts_protection is enabled we _shall_ protect
1421 * all HT transmissions using a CCK rate.
1422 *
1423 * And if any station is non GF we _shall_ protect
1424 * GF transmissions.
1425 *
1426 * We decide to protect everything
1427 * -> fall through to mixed mode.
1428 */
1429 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1430 /*
1431 * Legacy STAs are present
1432 * => Protect all HT transmissions.
1433 */
1434 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2;
1435
1436 /*
1437 * If erp protection is needed we have to protect HT
1438 * transmissions with CCK 11M long preamble.
1439 */
1440 if (erp->cts_protection) {
1441 /* don't duplicate RTS/CTS in CCK mode */
1442 mm20_rate = mm40_rate = 0x0003;
1443 gf20_rate = gf40_rate = 0x0003;
1444 }
1445 break;
1446 }
1447
1448 /* check for STAs not supporting greenfield mode */
1449 if (any_sta_nongf)
1450 gf20_mode = gf40_mode = 2;
1451
1452 /* Update HT protection config */
1453 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1454 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1455 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1456 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1457
1458 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1459 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1460 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1461 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1462
1463 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1464 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1465 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1466 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1467
1468 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1469 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1470 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1471 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1472 }
1473
1474 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1475 u32 changed)
1476 {
1477 u32 reg;
1478
1479 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1480 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1481 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
1482 !!erp->short_preamble);
1483 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1484 !!erp->short_preamble);
1485 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1486 }
1487
1488 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1489 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1490 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1491 erp->cts_protection ? 2 : 0);
1492 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1493 }
1494
1495 if (changed & BSS_CHANGED_BASIC_RATES) {
1496 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1497 erp->basic_rates);
1498 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1499 }
1500
1501 if (changed & BSS_CHANGED_ERP_SLOT) {
1502 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1503 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
1504 erp->slot_time);
1505 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1506
1507 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1508 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1509 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1510 }
1511
1512 if (changed & BSS_CHANGED_BEACON_INT) {
1513 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1514 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1515 erp->beacon_int * 16);
1516 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1517 }
1518
1519 if (changed & BSS_CHANGED_HT)
1520 rt2800_config_ht_opmode(rt2x00dev, erp);
1521 }
1522 EXPORT_SYMBOL_GPL(rt2800_config_erp);
1523
1524 static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev)
1525 {
1526 u32 reg;
1527 u16 eeprom;
1528 u8 led_ctrl, led_g_mode, led_r_mode;
1529
1530 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
1531 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
1532 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 1);
1533 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 1);
1534 } else {
1535 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 0);
1536 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 0);
1537 }
1538 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
1539
1540 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1541 led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0;
1542 led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3;
1543 if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) ||
1544 led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) {
1545 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1546 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE);
1547 if (led_ctrl == 0 || led_ctrl > 0x40) {
1548 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, led_g_mode);
1549 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, led_r_mode);
1550 rt2800_register_write(rt2x00dev, LED_CFG, reg);
1551 } else {
1552 rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff,
1553 (led_g_mode << 2) | led_r_mode, 1);
1554 }
1555 }
1556 }
1557
1558 static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
1559 enum antenna ant)
1560 {
1561 u32 reg;
1562 u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
1563 u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
1564
1565 if (rt2x00_is_pci(rt2x00dev)) {
1566 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
1567 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
1568 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
1569 } else if (rt2x00_is_usb(rt2x00dev))
1570 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
1571 eesk_pin, 0);
1572
1573 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
1574 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT3, 0);
1575 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, gpio_bit3);
1576 rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
1577 }
1578
1579 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1580 {
1581 u8 r1;
1582 u8 r3;
1583 u16 eeprom;
1584
1585 rt2800_bbp_read(rt2x00dev, 1, &r1);
1586 rt2800_bbp_read(rt2x00dev, 3, &r3);
1587
1588 if (rt2x00_rt(rt2x00dev, RT3572) &&
1589 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1590 rt2800_config_3572bt_ant(rt2x00dev);
1591
1592 /*
1593 * Configure the TX antenna.
1594 */
1595 switch (ant->tx_chain_num) {
1596 case 1:
1597 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1598 break;
1599 case 2:
1600 if (rt2x00_rt(rt2x00dev, RT3572) &&
1601 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1602 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1);
1603 else
1604 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1605 break;
1606 case 3:
1607 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1608 break;
1609 }
1610
1611 /*
1612 * Configure the RX antenna.
1613 */
1614 switch (ant->rx_chain_num) {
1615 case 1:
1616 if (rt2x00_rt(rt2x00dev, RT3070) ||
1617 rt2x00_rt(rt2x00dev, RT3090) ||
1618 rt2x00_rt(rt2x00dev, RT3390)) {
1619 rt2x00_eeprom_read(rt2x00dev,
1620 EEPROM_NIC_CONF1, &eeprom);
1621 if (rt2x00_get_field16(eeprom,
1622 EEPROM_NIC_CONF1_ANT_DIVERSITY))
1623 rt2800_set_ant_diversity(rt2x00dev,
1624 rt2x00dev->default_ant.rx);
1625 }
1626 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1627 break;
1628 case 2:
1629 if (rt2x00_rt(rt2x00dev, RT3572) &&
1630 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1631 rt2x00_set_field8(&r3, BBP3_RX_ADC, 1);
1632 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA,
1633 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
1634 rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B);
1635 } else {
1636 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1637 }
1638 break;
1639 case 3:
1640 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1641 break;
1642 }
1643
1644 rt2800_bbp_write(rt2x00dev, 3, r3);
1645 rt2800_bbp_write(rt2x00dev, 1, r1);
1646 }
1647 EXPORT_SYMBOL_GPL(rt2800_config_ant);
1648
1649 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1650 struct rt2x00lib_conf *libconf)
1651 {
1652 u16 eeprom;
1653 short lna_gain;
1654
1655 if (libconf->rf.channel <= 14) {
1656 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1657 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1658 } else if (libconf->rf.channel <= 64) {
1659 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1660 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1661 } else if (libconf->rf.channel <= 128) {
1662 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1663 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
1664 } else {
1665 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1666 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
1667 }
1668
1669 rt2x00dev->lna_gain = lna_gain;
1670 }
1671
1672 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1673 struct ieee80211_conf *conf,
1674 struct rf_channel *rf,
1675 struct channel_info *info)
1676 {
1677 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1678
1679 if (rt2x00dev->default_ant.tx_chain_num == 1)
1680 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1681
1682 if (rt2x00dev->default_ant.rx_chain_num == 1) {
1683 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1684 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1685 } else if (rt2x00dev->default_ant.rx_chain_num == 2)
1686 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1687
1688 if (rf->channel > 14) {
1689 /*
1690 * When TX power is below 0, we should increase it by 7 to
1691 * make it a positive value (Minimum value is -7).
1692 * However this means that values between 0 and 7 have
1693 * double meaning, and we should set a 7DBm boost flag.
1694 */
1695 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
1696 (info->default_power1 >= 0));
1697
1698 if (info->default_power1 < 0)
1699 info->default_power1 += 7;
1700
1701 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
1702
1703 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
1704 (info->default_power2 >= 0));
1705
1706 if (info->default_power2 < 0)
1707 info->default_power2 += 7;
1708
1709 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
1710 } else {
1711 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
1712 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
1713 }
1714
1715 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1716
1717 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1718 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1719 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1720 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1721
1722 udelay(200);
1723
1724 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1725 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1726 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1727 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1728
1729 udelay(200);
1730
1731 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1732 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1733 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1734 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1735 }
1736
1737 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1738 struct ieee80211_conf *conf,
1739 struct rf_channel *rf,
1740 struct channel_info *info)
1741 {
1742 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1743 u8 rfcsr, calib_tx, calib_rx;
1744
1745 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1746
1747 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
1748 rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3);
1749 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
1750
1751 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1752 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
1753 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1754
1755 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1756 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
1757 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1758
1759 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1760 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
1761 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1762
1763 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1764 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
1765 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
1766 if (rt2x00_rt(rt2x00dev, RT3390)) {
1767 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
1768 rt2x00dev->default_ant.rx_chain_num == 1);
1769 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
1770 rt2x00dev->default_ant.tx_chain_num == 1);
1771 } else {
1772 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
1773 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
1774 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
1775 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
1776
1777 switch (rt2x00dev->default_ant.tx_chain_num) {
1778 case 1:
1779 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
1780 /* fall through */
1781 case 2:
1782 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1783 break;
1784 }
1785
1786 switch (rt2x00dev->default_ant.rx_chain_num) {
1787 case 1:
1788 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
1789 /* fall through */
1790 case 2:
1791 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1792 break;
1793 }
1794 }
1795 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1796
1797 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1798 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1799 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1800 msleep(1);
1801 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1802 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1803
1804 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1805 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1806 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1807
1808 if (rt2x00_rt(rt2x00dev, RT3390)) {
1809 calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f;
1810 calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f;
1811 } else {
1812 if (conf_is_ht40(conf)) {
1813 calib_tx = drv_data->calibration_bw40;
1814 calib_rx = drv_data->calibration_bw40;
1815 } else {
1816 calib_tx = drv_data->calibration_bw20;
1817 calib_rx = drv_data->calibration_bw20;
1818 }
1819 }
1820
1821 rt2800_rfcsr_read(rt2x00dev, 24, &rfcsr);
1822 rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx);
1823 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr);
1824
1825 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
1826 rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx);
1827 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
1828
1829 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1830 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
1831 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1832
1833 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1834 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1835 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1836 msleep(1);
1837 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1838 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1839 }
1840
1841 static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
1842 struct ieee80211_conf *conf,
1843 struct rf_channel *rf,
1844 struct channel_info *info)
1845 {
1846 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1847 u8 rfcsr;
1848 u32 reg;
1849
1850 if (rf->channel <= 14) {
1851 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
1852 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
1853 } else {
1854 rt2800_bbp_write(rt2x00dev, 25, 0x09);
1855 rt2800_bbp_write(rt2x00dev, 26, 0xff);
1856 }
1857
1858 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1859 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
1860
1861 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1862 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
1863 if (rf->channel <= 14)
1864 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2);
1865 else
1866 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1);
1867 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1868
1869 rt2800_rfcsr_read(rt2x00dev, 5, &rfcsr);
1870 if (rf->channel <= 14)
1871 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1);
1872 else
1873 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2);
1874 rt2800_rfcsr_write(rt2x00dev, 5, rfcsr);
1875
1876 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1877 if (rf->channel <= 14) {
1878 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3);
1879 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
1880 info->default_power1);
1881 } else {
1882 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7);
1883 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
1884 (info->default_power1 & 0x3) |
1885 ((info->default_power1 & 0xC) << 1));
1886 }
1887 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1888
1889 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1890 if (rf->channel <= 14) {
1891 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3);
1892 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
1893 info->default_power2);
1894 } else {
1895 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7);
1896 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
1897 (info->default_power2 & 0x3) |
1898 ((info->default_power2 & 0xC) << 1));
1899 }
1900 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1901
1902 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1903 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
1904 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
1905 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
1906 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
1907 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
1908 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
1909 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1910 if (rf->channel <= 14) {
1911 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
1912 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
1913 }
1914 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1915 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1916 } else {
1917 switch (rt2x00dev->default_ant.tx_chain_num) {
1918 case 1:
1919 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
1920 case 2:
1921 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1922 break;
1923 }
1924
1925 switch (rt2x00dev->default_ant.rx_chain_num) {
1926 case 1:
1927 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
1928 case 2:
1929 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1930 break;
1931 }
1932 }
1933 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1934
1935 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1936 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1937 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1938
1939 if (conf_is_ht40(conf)) {
1940 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40);
1941 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40);
1942 } else {
1943 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20);
1944 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20);
1945 }
1946
1947 if (rf->channel <= 14) {
1948 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
1949 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
1950 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
1951 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
1952 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
1953 rfcsr = 0x4c;
1954 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
1955 drv_data->txmixer_gain_24g);
1956 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
1957 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
1958 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
1959 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
1960 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
1961 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
1962 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
1963 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
1964 } else {
1965 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1966 rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1);
1967 rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0);
1968 rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1);
1969 rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0);
1970 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1971 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
1972 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
1973 rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
1974 rt2800_rfcsr_write(rt2x00dev, 15, 0x43);
1975 rfcsr = 0x7a;
1976 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
1977 drv_data->txmixer_gain_5g);
1978 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
1979 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
1980 if (rf->channel <= 64) {
1981 rt2800_rfcsr_write(rt2x00dev, 19, 0xb7);
1982 rt2800_rfcsr_write(rt2x00dev, 20, 0xf6);
1983 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
1984 } else if (rf->channel <= 128) {
1985 rt2800_rfcsr_write(rt2x00dev, 19, 0x74);
1986 rt2800_rfcsr_write(rt2x00dev, 20, 0xf4);
1987 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1988 } else {
1989 rt2800_rfcsr_write(rt2x00dev, 19, 0x72);
1990 rt2800_rfcsr_write(rt2x00dev, 20, 0xf3);
1991 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1992 }
1993 rt2800_rfcsr_write(rt2x00dev, 26, 0x87);
1994 rt2800_rfcsr_write(rt2x00dev, 27, 0x01);
1995 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f);
1996 }
1997
1998 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
1999 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT7, 0);
2000 if (rf->channel <= 14)
2001 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT7, 1);
2002 else
2003 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT7, 0);
2004 rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
2005
2006 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
2007 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
2008 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2009 }
2010
2011 #define POWER_BOUND 0x27
2012 #define FREQ_OFFSET_BOUND 0x5f
2013
2014 static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev,
2015 struct ieee80211_conf *conf,
2016 struct rf_channel *rf,
2017 struct channel_info *info)
2018 {
2019 u8 rfcsr;
2020
2021 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2022 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2023 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2024 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2025 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2026
2027 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2028 if (info->default_power1 > POWER_BOUND)
2029 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
2030 else
2031 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2032 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2033
2034 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
2035 if (rt2x00dev->freq_offset > FREQ_OFFSET_BOUND)
2036 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, FREQ_OFFSET_BOUND);
2037 else
2038 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
2039 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2040
2041 if (rf->channel <= 14) {
2042 if (rf->channel == 6)
2043 rt2800_bbp_write(rt2x00dev, 68, 0x0c);
2044 else
2045 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
2046
2047 if (rf->channel >= 1 && rf->channel <= 6)
2048 rt2800_bbp_write(rt2x00dev, 59, 0x0f);
2049 else if (rf->channel >= 7 && rf->channel <= 11)
2050 rt2800_bbp_write(rt2x00dev, 59, 0x0e);
2051 else if (rf->channel >= 12 && rf->channel <= 14)
2052 rt2800_bbp_write(rt2x00dev, 59, 0x0d);
2053 }
2054 }
2055
2056 static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
2057 struct ieee80211_conf *conf,
2058 struct rf_channel *rf,
2059 struct channel_info *info)
2060 {
2061 u8 rfcsr;
2062
2063 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2064 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2065 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2066 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2067 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2068
2069 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2070 if (info->default_power1 > POWER_BOUND)
2071 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
2072 else
2073 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2074 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2075
2076 if (rt2x00_rt(rt2x00dev, RT5392)) {
2077 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
2078 if (info->default_power1 > POWER_BOUND)
2079 rt2x00_set_field8(&rfcsr, RFCSR50_TX, POWER_BOUND);
2080 else
2081 rt2x00_set_field8(&rfcsr, RFCSR50_TX,
2082 info->default_power2);
2083 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2084 }
2085
2086 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2087 if (rt2x00_rt(rt2x00dev, RT5392)) {
2088 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2089 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2090 }
2091 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2092 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2093 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2094 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2095 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2096
2097 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
2098 if (rt2x00dev->freq_offset > FREQ_OFFSET_BOUND)
2099 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, FREQ_OFFSET_BOUND);
2100 else
2101 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
2102 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2103
2104 if (rf->channel <= 14) {
2105 int idx = rf->channel-1;
2106
2107 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
2108 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2109 /* r55/r59 value array of channel 1~14 */
2110 static const char r55_bt_rev[] = {0x83, 0x83,
2111 0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
2112 0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
2113 static const char r59_bt_rev[] = {0x0e, 0x0e,
2114 0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
2115 0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
2116
2117 rt2800_rfcsr_write(rt2x00dev, 55,
2118 r55_bt_rev[idx]);
2119 rt2800_rfcsr_write(rt2x00dev, 59,
2120 r59_bt_rev[idx]);
2121 } else {
2122 static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
2123 0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
2124 0x88, 0x88, 0x86, 0x85, 0x84};
2125
2126 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
2127 }
2128 } else {
2129 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2130 static const char r55_nonbt_rev[] = {0x23, 0x23,
2131 0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
2132 0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
2133 static const char r59_nonbt_rev[] = {0x07, 0x07,
2134 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
2135 0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
2136
2137 rt2800_rfcsr_write(rt2x00dev, 55,
2138 r55_nonbt_rev[idx]);
2139 rt2800_rfcsr_write(rt2x00dev, 59,
2140 r59_nonbt_rev[idx]);
2141 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
2142 rt2x00_rt(rt2x00dev, RT5392)) {
2143 static const char r59_non_bt[] = {0x8f, 0x8f,
2144 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
2145 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
2146
2147 rt2800_rfcsr_write(rt2x00dev, 59,
2148 r59_non_bt[idx]);
2149 }
2150 }
2151 }
2152 }
2153
2154 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
2155 struct ieee80211_conf *conf,
2156 struct rf_channel *rf,
2157 struct channel_info *info)
2158 {
2159 u32 reg;
2160 unsigned int tx_pin;
2161 u8 bbp, rfcsr;
2162
2163 if (rf->channel <= 14) {
2164 info->default_power1 = TXPOWER_G_TO_DEV(info->default_power1);
2165 info->default_power2 = TXPOWER_G_TO_DEV(info->default_power2);
2166 } else {
2167 info->default_power1 = TXPOWER_A_TO_DEV(info->default_power1);
2168 info->default_power2 = TXPOWER_A_TO_DEV(info->default_power2);
2169 }
2170
2171 switch (rt2x00dev->chip.rf) {
2172 case RF2020:
2173 case RF3020:
2174 case RF3021:
2175 case RF3022:
2176 case RF3320:
2177 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
2178 break;
2179 case RF3052:
2180 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);
2181 break;
2182 case RF3290:
2183 rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info);
2184 break;
2185 case RF5360:
2186 case RF5370:
2187 case RF5372:
2188 case RF5390:
2189 case RF5392:
2190 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
2191 break;
2192 default:
2193 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
2194 }
2195
2196 if (rt2x00_rf(rt2x00dev, RF3290) ||
2197 rt2x00_rf(rt2x00dev, RF5360) ||
2198 rt2x00_rf(rt2x00dev, RF5370) ||
2199 rt2x00_rf(rt2x00dev, RF5372) ||
2200 rt2x00_rf(rt2x00dev, RF5390) ||
2201 rt2x00_rf(rt2x00dev, RF5392)) {
2202 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2203 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0);
2204 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0);
2205 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2206
2207 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2208 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2209 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2210 }
2211
2212 /*
2213 * Change BBP settings
2214 */
2215 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
2216 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
2217 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
2218 rt2800_bbp_write(rt2x00dev, 86, 0);
2219
2220 if (rf->channel <= 14) {
2221 if (!rt2x00_rt(rt2x00dev, RT5390) &&
2222 !rt2x00_rt(rt2x00dev, RT5392)) {
2223 if (test_bit(CAPABILITY_EXTERNAL_LNA_BG,
2224 &rt2x00dev->cap_flags)) {
2225 rt2800_bbp_write(rt2x00dev, 82, 0x62);
2226 rt2800_bbp_write(rt2x00dev, 75, 0x46);
2227 } else {
2228 rt2800_bbp_write(rt2x00dev, 82, 0x84);
2229 rt2800_bbp_write(rt2x00dev, 75, 0x50);
2230 }
2231 }
2232 } else {
2233 if (rt2x00_rt(rt2x00dev, RT3572))
2234 rt2800_bbp_write(rt2x00dev, 82, 0x94);
2235 else
2236 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
2237
2238 if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags))
2239 rt2800_bbp_write(rt2x00dev, 75, 0x46);
2240 else
2241 rt2800_bbp_write(rt2x00dev, 75, 0x50);
2242 }
2243
2244 rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
2245 rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
2246 rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
2247 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
2248 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
2249
2250 if (rt2x00_rt(rt2x00dev, RT3572))
2251 rt2800_rfcsr_write(rt2x00dev, 8, 0);
2252
2253 tx_pin = 0;
2254
2255 /* Turn on unused PA or LNA when not using 1T or 1R */
2256 if (rt2x00dev->default_ant.tx_chain_num == 2) {
2257 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN,
2258 rf->channel > 14);
2259 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN,
2260 rf->channel <= 14);
2261 }
2262
2263 /* Turn on unused PA or LNA when not using 1T or 1R */
2264 if (rt2x00dev->default_ant.rx_chain_num == 2) {
2265 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
2266 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
2267 }
2268
2269 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
2270 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
2271 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
2272 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
2273 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
2274 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
2275 else
2276 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN,
2277 rf->channel <= 14);
2278 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
2279
2280 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
2281
2282 if (rt2x00_rt(rt2x00dev, RT3572))
2283 rt2800_rfcsr_write(rt2x00dev, 8, 0x80);
2284
2285 rt2800_bbp_read(rt2x00dev, 4, &bbp);
2286 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
2287 rt2800_bbp_write(rt2x00dev, 4, bbp);
2288
2289 rt2800_bbp_read(rt2x00dev, 3, &bbp);
2290 rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
2291 rt2800_bbp_write(rt2x00dev, 3, bbp);
2292
2293 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
2294 if (conf_is_ht40(conf)) {
2295 rt2800_bbp_write(rt2x00dev, 69, 0x1a);
2296 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
2297 rt2800_bbp_write(rt2x00dev, 73, 0x16);
2298 } else {
2299 rt2800_bbp_write(rt2x00dev, 69, 0x16);
2300 rt2800_bbp_write(rt2x00dev, 70, 0x08);
2301 rt2800_bbp_write(rt2x00dev, 73, 0x11);
2302 }
2303 }
2304
2305 msleep(1);
2306
2307 /*
2308 * Clear channel statistic counters
2309 */
2310 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg);
2311 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg);
2312 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
2313 }
2314
2315 static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
2316 {
2317 u8 tssi_bounds[9];
2318 u8 current_tssi;
2319 u16 eeprom;
2320 u8 step;
2321 int i;
2322
2323 /*
2324 * Read TSSI boundaries for temperature compensation from
2325 * the EEPROM.
2326 *
2327 * Array idx 0 1 2 3 4 5 6 7 8
2328 * Matching Delta value -4 -3 -2 -1 0 +1 +2 +3 +4
2329 * Example TSSI bounds 0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
2330 */
2331 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
2332 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1, &eeprom);
2333 tssi_bounds[0] = rt2x00_get_field16(eeprom,
2334 EEPROM_TSSI_BOUND_BG1_MINUS4);
2335 tssi_bounds[1] = rt2x00_get_field16(eeprom,
2336 EEPROM_TSSI_BOUND_BG1_MINUS3);
2337
2338 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2, &eeprom);
2339 tssi_bounds[2] = rt2x00_get_field16(eeprom,
2340 EEPROM_TSSI_BOUND_BG2_MINUS2);
2341 tssi_bounds[3] = rt2x00_get_field16(eeprom,
2342 EEPROM_TSSI_BOUND_BG2_MINUS1);
2343
2344 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3, &eeprom);
2345 tssi_bounds[4] = rt2x00_get_field16(eeprom,
2346 EEPROM_TSSI_BOUND_BG3_REF);
2347 tssi_bounds[5] = rt2x00_get_field16(eeprom,
2348 EEPROM_TSSI_BOUND_BG3_PLUS1);
2349
2350 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4, &eeprom);
2351 tssi_bounds[6] = rt2x00_get_field16(eeprom,
2352 EEPROM_TSSI_BOUND_BG4_PLUS2);
2353 tssi_bounds[7] = rt2x00_get_field16(eeprom,
2354 EEPROM_TSSI_BOUND_BG4_PLUS3);
2355
2356 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5, &eeprom);
2357 tssi_bounds[8] = rt2x00_get_field16(eeprom,
2358 EEPROM_TSSI_BOUND_BG5_PLUS4);
2359
2360 step = rt2x00_get_field16(eeprom,
2361 EEPROM_TSSI_BOUND_BG5_AGC_STEP);
2362 } else {
2363 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1, &eeprom);
2364 tssi_bounds[0] = rt2x00_get_field16(eeprom,
2365 EEPROM_TSSI_BOUND_A1_MINUS4);
2366 tssi_bounds[1] = rt2x00_get_field16(eeprom,
2367 EEPROM_TSSI_BOUND_A1_MINUS3);
2368
2369 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2, &eeprom);
2370 tssi_bounds[2] = rt2x00_get_field16(eeprom,
2371 EEPROM_TSSI_BOUND_A2_MINUS2);
2372 tssi_bounds[3] = rt2x00_get_field16(eeprom,
2373 EEPROM_TSSI_BOUND_A2_MINUS1);
2374
2375 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3, &eeprom);
2376 tssi_bounds[4] = rt2x00_get_field16(eeprom,
2377 EEPROM_TSSI_BOUND_A3_REF);
2378 tssi_bounds[5] = rt2x00_get_field16(eeprom,
2379 EEPROM_TSSI_BOUND_A3_PLUS1);
2380
2381 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4, &eeprom);
2382 tssi_bounds[6] = rt2x00_get_field16(eeprom,
2383 EEPROM_TSSI_BOUND_A4_PLUS2);
2384 tssi_bounds[7] = rt2x00_get_field16(eeprom,
2385 EEPROM_TSSI_BOUND_A4_PLUS3);
2386
2387 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5, &eeprom);
2388 tssi_bounds[8] = rt2x00_get_field16(eeprom,
2389 EEPROM_TSSI_BOUND_A5_PLUS4);
2390
2391 step = rt2x00_get_field16(eeprom,
2392 EEPROM_TSSI_BOUND_A5_AGC_STEP);
2393 }
2394
2395 /*
2396 * Check if temperature compensation is supported.
2397 */
2398 if (tssi_bounds[4] == 0xff)
2399 return 0;
2400
2401 /*
2402 * Read current TSSI (BBP 49).
2403 */
2404 rt2800_bbp_read(rt2x00dev, 49, &current_tssi);
2405
2406 /*
2407 * Compare TSSI value (BBP49) with the compensation boundaries
2408 * from the EEPROM and increase or decrease tx power.
2409 */
2410 for (i = 0; i <= 3; i++) {
2411 if (current_tssi > tssi_bounds[i])
2412 break;
2413 }
2414
2415 if (i == 4) {
2416 for (i = 8; i >= 5; i--) {
2417 if (current_tssi < tssi_bounds[i])
2418 break;
2419 }
2420 }
2421
2422 return (i - 4) * step;
2423 }
2424
2425 static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
2426 enum ieee80211_band band)
2427 {
2428 u16 eeprom;
2429 u8 comp_en;
2430 u8 comp_type;
2431 int comp_value = 0;
2432
2433 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom);
2434
2435 /*
2436 * HT40 compensation not required.
2437 */
2438 if (eeprom == 0xffff ||
2439 !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
2440 return 0;
2441
2442 if (band == IEEE80211_BAND_2GHZ) {
2443 comp_en = rt2x00_get_field16(eeprom,
2444 EEPROM_TXPOWER_DELTA_ENABLE_2G);
2445 if (comp_en) {
2446 comp_type = rt2x00_get_field16(eeprom,
2447 EEPROM_TXPOWER_DELTA_TYPE_2G);
2448 comp_value = rt2x00_get_field16(eeprom,
2449 EEPROM_TXPOWER_DELTA_VALUE_2G);
2450 if (!comp_type)
2451 comp_value = -comp_value;
2452 }
2453 } else {
2454 comp_en = rt2x00_get_field16(eeprom,
2455 EEPROM_TXPOWER_DELTA_ENABLE_5G);
2456 if (comp_en) {
2457 comp_type = rt2x00_get_field16(eeprom,
2458 EEPROM_TXPOWER_DELTA_TYPE_5G);
2459 comp_value = rt2x00_get_field16(eeprom,
2460 EEPROM_TXPOWER_DELTA_VALUE_5G);
2461 if (!comp_type)
2462 comp_value = -comp_value;
2463 }
2464 }
2465
2466 return comp_value;
2467 }
2468
2469 static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
2470 enum ieee80211_band band, int power_level,
2471 u8 txpower, int delta)
2472 {
2473 u32 reg;
2474 u16 eeprom;
2475 u8 criterion;
2476 u8 eirp_txpower;
2477 u8 eirp_txpower_criterion;
2478 u8 reg_limit;
2479
2480 if (!((band == IEEE80211_BAND_5GHZ) && is_rate_b))
2481 return txpower;
2482
2483 if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags)) {
2484 /*
2485 * Check if eirp txpower exceed txpower_limit.
2486 * We use OFDM 6M as criterion and its eirp txpower
2487 * is stored at EEPROM_EIRP_MAX_TX_POWER.
2488 * .11b data rate need add additional 4dbm
2489 * when calculating eirp txpower.
2490 */
2491 rt2800_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
2492 criterion = rt2x00_get_field32(reg, TX_PWR_CFG_0_6MBS);
2493
2494 rt2x00_eeprom_read(rt2x00dev,
2495 EEPROM_EIRP_MAX_TX_POWER, &eeprom);
2496
2497 if (band == IEEE80211_BAND_2GHZ)
2498 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
2499 EEPROM_EIRP_MAX_TX_POWER_2GHZ);
2500 else
2501 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
2502 EEPROM_EIRP_MAX_TX_POWER_5GHZ);
2503
2504 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
2505 (is_rate_b ? 4 : 0) + delta;
2506
2507 reg_limit = (eirp_txpower > power_level) ?
2508 (eirp_txpower - power_level) : 0;
2509 } else
2510 reg_limit = 0;
2511
2512 return txpower + delta - reg_limit;
2513 }
2514
2515 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
2516 enum ieee80211_band band,
2517 int power_level)
2518 {
2519 u8 txpower;
2520 u16 eeprom;
2521 int i, is_rate_b;
2522 u32 reg;
2523 u8 r1;
2524 u32 offset;
2525 int delta;
2526
2527 /*
2528 * Calculate HT40 compensation delta
2529 */
2530 delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
2531
2532 /*
2533 * calculate temperature compensation delta
2534 */
2535 delta += rt2800_get_gain_calibration_delta(rt2x00dev);
2536
2537 /*
2538 * set to normal bbp tx power control mode: +/- 0dBm
2539 */
2540 rt2800_bbp_read(rt2x00dev, 1, &r1);
2541 rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, 0);
2542 rt2800_bbp_write(rt2x00dev, 1, r1);
2543 offset = TX_PWR_CFG_0;
2544
2545 for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
2546 /* just to be safe */
2547 if (offset > TX_PWR_CFG_4)
2548 break;
2549
2550 rt2800_register_read(rt2x00dev, offset, &reg);
2551
2552 /* read the next four txpower values */
2553 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i,
2554 &eeprom);
2555
2556 is_rate_b = i ? 0 : 1;
2557 /*
2558 * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
2559 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
2560 * TX_PWR_CFG_4: unknown
2561 */
2562 txpower = rt2x00_get_field16(eeprom,
2563 EEPROM_TXPOWER_BYRATE_RATE0);
2564 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2565 power_level, txpower, delta);
2566 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
2567
2568 /*
2569 * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
2570 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
2571 * TX_PWR_CFG_4: unknown
2572 */
2573 txpower = rt2x00_get_field16(eeprom,
2574 EEPROM_TXPOWER_BYRATE_RATE1);
2575 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2576 power_level, txpower, delta);
2577 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
2578
2579 /*
2580 * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
2581 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14,
2582 * TX_PWR_CFG_4: unknown
2583 */
2584 txpower = rt2x00_get_field16(eeprom,
2585 EEPROM_TXPOWER_BYRATE_RATE2);
2586 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2587 power_level, txpower, delta);
2588 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
2589
2590 /*
2591 * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
2592 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15,
2593 * TX_PWR_CFG_4: unknown
2594 */
2595 txpower = rt2x00_get_field16(eeprom,
2596 EEPROM_TXPOWER_BYRATE_RATE3);
2597 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2598 power_level, txpower, delta);
2599 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
2600
2601 /* read the next four txpower values */
2602 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i + 1,
2603 &eeprom);
2604
2605 is_rate_b = 0;
2606 /*
2607 * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
2608 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
2609 * TX_PWR_CFG_4: unknown
2610 */
2611 txpower = rt2x00_get_field16(eeprom,
2612 EEPROM_TXPOWER_BYRATE_RATE0);
2613 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2614 power_level, txpower, delta);
2615 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
2616
2617 /*
2618 * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
2619 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
2620 * TX_PWR_CFG_4: unknown
2621 */
2622 txpower = rt2x00_get_field16(eeprom,
2623 EEPROM_TXPOWER_BYRATE_RATE1);
2624 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2625 power_level, txpower, delta);
2626 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
2627
2628 /*
2629 * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
2630 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
2631 * TX_PWR_CFG_4: unknown
2632 */
2633 txpower = rt2x00_get_field16(eeprom,
2634 EEPROM_TXPOWER_BYRATE_RATE2);
2635 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2636 power_level, txpower, delta);
2637 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
2638
2639 /*
2640 * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
2641 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
2642 * TX_PWR_CFG_4: unknown
2643 */
2644 txpower = rt2x00_get_field16(eeprom,
2645 EEPROM_TXPOWER_BYRATE_RATE3);
2646 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2647 power_level, txpower, delta);
2648 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
2649
2650 rt2800_register_write(rt2x00dev, offset, reg);
2651
2652 /* next TX_PWR_CFG register */
2653 offset += 4;
2654 }
2655 }
2656
2657 void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
2658 {
2659 rt2800_config_txpower(rt2x00dev, rt2x00dev->curr_band,
2660 rt2x00dev->tx_power);
2661 }
2662 EXPORT_SYMBOL_GPL(rt2800_gain_calibration);
2663
2664 void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev)
2665 {
2666 u32 tx_pin;
2667 u8 rfcsr;
2668
2669 /*
2670 * A voltage-controlled oscillator(VCO) is an electronic oscillator
2671 * designed to be controlled in oscillation frequency by a voltage
2672 * input. Maybe the temperature will affect the frequency of
2673 * oscillation to be shifted. The VCO calibration will be called
2674 * periodically to adjust the frequency to be precision.
2675 */
2676
2677 rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
2678 tx_pin &= TX_PIN_CFG_PA_PE_DISABLE;
2679 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
2680
2681 switch (rt2x00dev->chip.rf) {
2682 case RF2020:
2683 case RF3020:
2684 case RF3021:
2685 case RF3022:
2686 case RF3320:
2687 case RF3052:
2688 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
2689 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
2690 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2691 break;
2692 case RF3290:
2693 case RF5360:
2694 case RF5370:
2695 case RF5372:
2696 case RF5390:
2697 case RF5392:
2698 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2699 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2700 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2701 break;
2702 default:
2703 return;
2704 }
2705
2706 mdelay(1);
2707
2708 rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
2709 if (rt2x00dev->rf_channel <= 14) {
2710 switch (rt2x00dev->default_ant.tx_chain_num) {
2711 case 3:
2712 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1);
2713 /* fall through */
2714 case 2:
2715 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
2716 /* fall through */
2717 case 1:
2718 default:
2719 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
2720 break;
2721 }
2722 } else {
2723 switch (rt2x00dev->default_ant.tx_chain_num) {
2724 case 3:
2725 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1);
2726 /* fall through */
2727 case 2:
2728 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
2729 /* fall through */
2730 case 1:
2731 default:
2732 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1);
2733 break;
2734 }
2735 }
2736 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
2737
2738 }
2739 EXPORT_SYMBOL_GPL(rt2800_vco_calibration);
2740
2741 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
2742 struct rt2x00lib_conf *libconf)
2743 {
2744 u32 reg;
2745
2746 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
2747 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
2748 libconf->conf->short_frame_max_tx_count);
2749 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
2750 libconf->conf->long_frame_max_tx_count);
2751 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
2752 }
2753
2754 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
2755 struct rt2x00lib_conf *libconf)
2756 {
2757 enum dev_state state =
2758 (libconf->conf->flags & IEEE80211_CONF_PS) ?
2759 STATE_SLEEP : STATE_AWAKE;
2760 u32 reg;
2761
2762 if (state == STATE_SLEEP) {
2763 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
2764
2765 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
2766 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
2767 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
2768 libconf->conf->listen_interval - 1);
2769 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
2770 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
2771
2772 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
2773 } else {
2774 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
2775 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
2776 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
2777 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
2778 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
2779
2780 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
2781 }
2782 }
2783
2784 void rt2800_config(struct rt2x00_dev *rt2x00dev,
2785 struct rt2x00lib_conf *libconf,
2786 const unsigned int flags)
2787 {
2788 /* Always recalculate LNA gain before changing configuration */
2789 rt2800_config_lna_gain(rt2x00dev, libconf);
2790
2791 if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
2792 rt2800_config_channel(rt2x00dev, libconf->conf,
2793 &libconf->rf, &libconf->channel);
2794 rt2800_config_txpower(rt2x00dev, libconf->conf->channel->band,
2795 libconf->conf->power_level);
2796 }
2797 if (flags & IEEE80211_CONF_CHANGE_POWER)
2798 rt2800_config_txpower(rt2x00dev, libconf->conf->channel->band,
2799 libconf->conf->power_level);
2800 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
2801 rt2800_config_retry_limit(rt2x00dev, libconf);
2802 if (flags & IEEE80211_CONF_CHANGE_PS)
2803 rt2800_config_ps(rt2x00dev, libconf);
2804 }
2805 EXPORT_SYMBOL_GPL(rt2800_config);
2806
2807 /*
2808 * Link tuning
2809 */
2810 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
2811 {
2812 u32 reg;
2813
2814 /*
2815 * Update FCS error count from register.
2816 */
2817 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
2818 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
2819 }
2820 EXPORT_SYMBOL_GPL(rt2800_link_stats);
2821
2822 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
2823 {
2824 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
2825 if (rt2x00_rt(rt2x00dev, RT3070) ||
2826 rt2x00_rt(rt2x00dev, RT3071) ||
2827 rt2x00_rt(rt2x00dev, RT3090) ||
2828 rt2x00_rt(rt2x00dev, RT3290) ||
2829 rt2x00_rt(rt2x00dev, RT3390) ||
2830 rt2x00_rt(rt2x00dev, RT5390) ||
2831 rt2x00_rt(rt2x00dev, RT5392))
2832 return 0x1c + (2 * rt2x00dev->lna_gain);
2833 else
2834 return 0x2e + rt2x00dev->lna_gain;
2835 }
2836
2837 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
2838 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
2839 else
2840 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
2841 }
2842
2843 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
2844 struct link_qual *qual, u8 vgc_level)
2845 {
2846 if (qual->vgc_level != vgc_level) {
2847 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
2848 qual->vgc_level = vgc_level;
2849 qual->vgc_level_reg = vgc_level;
2850 }
2851 }
2852
2853 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
2854 {
2855 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
2856 }
2857 EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
2858
2859 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
2860 const u32 count)
2861 {
2862 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
2863 return;
2864
2865 /*
2866 * When RSSI is better then -80 increase VGC level with 0x10
2867 */
2868 rt2800_set_vgc(rt2x00dev, qual,
2869 rt2800_get_default_vgc(rt2x00dev) +
2870 ((qual->rssi > -80) * 0x10));
2871 }
2872 EXPORT_SYMBOL_GPL(rt2800_link_tuner);
2873
2874 /*
2875 * Initialization functions.
2876 */
2877 static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
2878 {
2879 u32 reg;
2880 u16 eeprom;
2881 unsigned int i;
2882 int ret;
2883
2884 rt2800_disable_wpdma(rt2x00dev);
2885
2886 ret = rt2800_drv_init_registers(rt2x00dev);
2887 if (ret)
2888 return ret;
2889
2890 rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
2891 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
2892 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
2893 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
2894 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
2895 rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
2896
2897 rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
2898 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
2899 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
2900 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
2901 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
2902 rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
2903
2904 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
2905 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
2906
2907 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
2908
2909 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2910 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
2911 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
2912 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
2913 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
2914 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
2915 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
2916 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2917
2918 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
2919
2920 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
2921 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
2922 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
2923 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
2924
2925 if (rt2x00_rt(rt2x00dev, RT3290)) {
2926 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
2927 if (rt2x00_get_field32(reg, WLAN_EN) == 1) {
2928 rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 1);
2929 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
2930 }
2931
2932 rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
2933 if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) {
2934 rt2x00_set_field32(&reg, LDO0_EN, 1);
2935 rt2x00_set_field32(&reg, LDO_BGSEL, 3);
2936 rt2800_register_write(rt2x00dev, CMB_CTRL, reg);
2937 }
2938
2939 rt2800_register_read(rt2x00dev, OSC_CTRL, &reg);
2940 rt2x00_set_field32(&reg, OSC_ROSC_EN, 1);
2941 rt2x00_set_field32(&reg, OSC_CAL_REQ, 1);
2942 rt2x00_set_field32(&reg, OSC_REF_CYCLE, 0x27);
2943 rt2800_register_write(rt2x00dev, OSC_CTRL, reg);
2944
2945 rt2800_register_read(rt2x00dev, COEX_CFG0, &reg);
2946 rt2x00_set_field32(&reg, COEX_CFG_ANT, 0x5e);
2947 rt2800_register_write(rt2x00dev, COEX_CFG0, reg);
2948
2949 rt2800_register_read(rt2x00dev, COEX_CFG2, &reg);
2950 rt2x00_set_field32(&reg, BT_COEX_CFG1, 0x00);
2951 rt2x00_set_field32(&reg, BT_COEX_CFG0, 0x17);
2952 rt2x00_set_field32(&reg, WL_COEX_CFG1, 0x93);
2953 rt2x00_set_field32(&reg, WL_COEX_CFG0, 0x7f);
2954 rt2800_register_write(rt2x00dev, COEX_CFG2, reg);
2955
2956 rt2800_register_read(rt2x00dev, PLL_CTRL, &reg);
2957 rt2x00_set_field32(&reg, PLL_CONTROL, 1);
2958 rt2800_register_write(rt2x00dev, PLL_CTRL, reg);
2959 }
2960
2961 if (rt2x00_rt(rt2x00dev, RT3071) ||
2962 rt2x00_rt(rt2x00dev, RT3090) ||
2963 rt2x00_rt(rt2x00dev, RT3290) ||
2964 rt2x00_rt(rt2x00dev, RT3390)) {
2965
2966 if (rt2x00_rt(rt2x00dev, RT3290))
2967 rt2800_register_write(rt2x00dev, TX_SW_CFG0,
2968 0x00000404);
2969 else
2970 rt2800_register_write(rt2x00dev, TX_SW_CFG0,
2971 0x00000400);
2972
2973 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
2974 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
2975 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2976 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
2977 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
2978 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
2979 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
2980 0x0000002c);
2981 else
2982 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
2983 0x0000000f);
2984 } else {
2985 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
2986 }
2987 } else if (rt2x00_rt(rt2x00dev, RT3070)) {
2988 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2989
2990 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
2991 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
2992 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
2993 } else {
2994 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2995 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
2996 }
2997 } else if (rt2800_is_305x_soc(rt2x00dev)) {
2998 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2999 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
3000 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
3001 } else if (rt2x00_rt(rt2x00dev, RT3572)) {
3002 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
3003 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
3004 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
3005 rt2x00_rt(rt2x00dev, RT5392)) {
3006 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
3007 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
3008 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
3009 } else {
3010 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
3011 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
3012 }
3013
3014 rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
3015 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
3016 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
3017 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
3018 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
3019 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
3020 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
3021 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
3022 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
3023 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
3024
3025 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
3026 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
3027 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
3028 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
3029 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
3030
3031 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
3032 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
3033 if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
3034 rt2x00_rt(rt2x00dev, RT2883) ||
3035 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
3036 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
3037 else
3038 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
3039 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
3040 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
3041 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
3042
3043 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
3044 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
3045 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
3046 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
3047 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
3048 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
3049 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
3050 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
3051 rt2800_register_write(rt2x00dev, LED_CFG, reg);
3052
3053 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
3054
3055 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
3056 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
3057 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
3058 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
3059 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
3060 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
3061 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
3062 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
3063
3064 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
3065 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
3066 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
3067 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
3068 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
3069 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
3070 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
3071 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
3072 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
3073
3074 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
3075 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
3076 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
3077 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
3078 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3079 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3080 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3081 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
3082 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3083 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
3084 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
3085 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
3086
3087 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
3088 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
3089 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
3090 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
3091 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3092 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3093 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3094 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
3095 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3096 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
3097 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
3098 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
3099
3100 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
3101 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
3102 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
3103 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
3104 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3105 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3106 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3107 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
3108 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3109 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
3110 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
3111 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
3112
3113 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
3114 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
3115 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
3116 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
3117 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3118 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3119 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3120 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
3121 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3122 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
3123 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
3124 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
3125
3126 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
3127 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
3128 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
3129 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
3130 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3131 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3132 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3133 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
3134 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3135 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
3136 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
3137 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
3138
3139 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
3140 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
3141 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
3142 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
3143 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3144 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3145 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3146 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
3147 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3148 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
3149 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
3150 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
3151
3152 if (rt2x00_is_usb(rt2x00dev)) {
3153 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
3154
3155 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
3156 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
3157 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
3158 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
3159 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
3160 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
3161 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
3162 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
3163 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
3164 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
3165 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
3166 }
3167
3168 /*
3169 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
3170 * although it is reserved.
3171 */
3172 rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, &reg);
3173 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
3174 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
3175 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
3176 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
3177 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
3178 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
3179 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
3180 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
3181 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
3182 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
3183 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
3184
3185 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
3186
3187 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
3188 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
3189 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
3190 IEEE80211_MAX_RTS_THRESHOLD);
3191 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
3192 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
3193
3194 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
3195
3196 /*
3197 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
3198 * time should be set to 16. However, the original Ralink driver uses
3199 * 16 for both and indeed using a value of 10 for CCK SIFS results in
3200 * connection problems with 11g + CTS protection. Hence, use the same
3201 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
3202 */
3203 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
3204 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
3205 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
3206 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
3207 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
3208 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
3209 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
3210
3211 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
3212
3213 /*
3214 * ASIC will keep garbage value after boot, clear encryption keys.
3215 */
3216 for (i = 0; i < 4; i++)
3217 rt2800_register_write(rt2x00dev,
3218 SHARED_KEY_MODE_ENTRY(i), 0);
3219
3220 for (i = 0; i < 256; i++) {
3221 rt2800_config_wcid(rt2x00dev, NULL, i);
3222 rt2800_delete_wcid_attr(rt2x00dev, i);
3223 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
3224 }
3225
3226 /*
3227 * Clear all beacons
3228 */
3229 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE0);
3230 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE1);
3231 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE2);
3232 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE3);
3233 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE4);
3234 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE5);
3235 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE6);
3236 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE7);
3237
3238 if (rt2x00_is_usb(rt2x00dev)) {
3239 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
3240 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
3241 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
3242 } else if (rt2x00_is_pcie(rt2x00dev)) {
3243 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
3244 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
3245 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
3246 }
3247
3248 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
3249 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
3250 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
3251 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
3252 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
3253 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
3254 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
3255 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
3256 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
3257 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
3258
3259 rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
3260 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
3261 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
3262 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
3263 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
3264 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
3265 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
3266 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
3267 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
3268 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
3269
3270 rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
3271 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
3272 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
3273 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
3274 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
3275 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
3276 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
3277 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
3278 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
3279 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
3280
3281 rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
3282 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
3283 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
3284 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
3285 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
3286 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
3287
3288 /*
3289 * Do not force the BA window size, we use the TXWI to set it
3290 */
3291 rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, &reg);
3292 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
3293 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
3294 rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
3295
3296 /*
3297 * We must clear the error counters.
3298 * These registers are cleared on read,
3299 * so we may pass a useless variable to store the value.
3300 */
3301 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
3302 rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
3303 rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
3304 rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
3305 rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
3306 rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
3307
3308 /*
3309 * Setup leadtime for pre tbtt interrupt to 6ms
3310 */
3311 rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
3312 rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
3313 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
3314
3315 /*
3316 * Set up channel statistics timer
3317 */
3318 rt2800_register_read(rt2x00dev, CH_TIME_CFG, &reg);
3319 rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
3320 rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
3321 rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
3322 rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
3323 rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
3324 rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
3325
3326 return 0;
3327 }
3328
3329 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
3330 {
3331 unsigned int i;
3332 u32 reg;
3333
3334 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
3335 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
3336 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
3337 return 0;
3338
3339 udelay(REGISTER_BUSY_DELAY);
3340 }
3341
3342 ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
3343 return -EACCES;
3344 }
3345
3346 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
3347 {
3348 unsigned int i;
3349 u8 value;
3350
3351 /*
3352 * BBP was enabled after firmware was loaded,
3353 * but we need to reactivate it now.
3354 */
3355 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
3356 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
3357 msleep(1);
3358
3359 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
3360 rt2800_bbp_read(rt2x00dev, 0, &value);
3361 if ((value != 0xff) && (value != 0x00))
3362 return 0;
3363 udelay(REGISTER_BUSY_DELAY);
3364 }
3365
3366 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
3367 return -EACCES;
3368 }
3369
3370 static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
3371 {
3372 unsigned int i;
3373 u16 eeprom;
3374 u8 reg_id;
3375 u8 value;
3376
3377 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
3378 rt2800_wait_bbp_ready(rt2x00dev)))
3379 return -EACCES;
3380
3381 if (rt2x00_rt(rt2x00dev, RT3290) ||
3382 rt2x00_rt(rt2x00dev, RT5390) ||
3383 rt2x00_rt(rt2x00dev, RT5392)) {
3384 rt2800_bbp_read(rt2x00dev, 4, &value);
3385 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
3386 rt2800_bbp_write(rt2x00dev, 4, value);
3387 }
3388
3389 if (rt2800_is_305x_soc(rt2x00dev) ||
3390 rt2x00_rt(rt2x00dev, RT3290) ||
3391 rt2x00_rt(rt2x00dev, RT3572) ||
3392 rt2x00_rt(rt2x00dev, RT5390) ||
3393 rt2x00_rt(rt2x00dev, RT5392))
3394 rt2800_bbp_write(rt2x00dev, 31, 0x08);
3395
3396 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
3397 rt2800_bbp_write(rt2x00dev, 66, 0x38);
3398
3399 if (rt2x00_rt(rt2x00dev, RT3290) ||
3400 rt2x00_rt(rt2x00dev, RT5390) ||
3401 rt2x00_rt(rt2x00dev, RT5392))
3402 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
3403
3404 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
3405 rt2800_bbp_write(rt2x00dev, 69, 0x16);
3406 rt2800_bbp_write(rt2x00dev, 73, 0x12);
3407 } else if (rt2x00_rt(rt2x00dev, RT3290) ||
3408 rt2x00_rt(rt2x00dev, RT5390) ||
3409 rt2x00_rt(rt2x00dev, RT5392)) {
3410 rt2800_bbp_write(rt2x00dev, 69, 0x12);
3411 rt2800_bbp_write(rt2x00dev, 73, 0x13);
3412 rt2800_bbp_write(rt2x00dev, 75, 0x46);
3413 rt2800_bbp_write(rt2x00dev, 76, 0x28);
3414
3415 if (rt2x00_rt(rt2x00dev, RT3290))
3416 rt2800_bbp_write(rt2x00dev, 77, 0x58);
3417 else
3418 rt2800_bbp_write(rt2x00dev, 77, 0x59);
3419 } else {
3420 rt2800_bbp_write(rt2x00dev, 69, 0x12);
3421 rt2800_bbp_write(rt2x00dev, 73, 0x10);
3422 }
3423
3424 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
3425
3426 if (rt2x00_rt(rt2x00dev, RT3070) ||
3427 rt2x00_rt(rt2x00dev, RT3071) ||
3428 rt2x00_rt(rt2x00dev, RT3090) ||
3429 rt2x00_rt(rt2x00dev, RT3390) ||
3430 rt2x00_rt(rt2x00dev, RT3572) ||
3431 rt2x00_rt(rt2x00dev, RT5390) ||
3432 rt2x00_rt(rt2x00dev, RT5392)) {
3433 rt2800_bbp_write(rt2x00dev, 79, 0x13);
3434 rt2800_bbp_write(rt2x00dev, 80, 0x05);
3435 rt2800_bbp_write(rt2x00dev, 81, 0x33);
3436 } else if (rt2800_is_305x_soc(rt2x00dev)) {
3437 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
3438 rt2800_bbp_write(rt2x00dev, 80, 0x08);
3439 } else {
3440 rt2800_bbp_write(rt2x00dev, 81, 0x37);
3441 }
3442
3443 if (rt2x00_rt(rt2x00dev, RT3290)) {
3444 rt2800_bbp_write(rt2x00dev, 74, 0x0b);
3445 rt2800_bbp_write(rt2x00dev, 79, 0x18);
3446 rt2800_bbp_write(rt2x00dev, 80, 0x09);
3447 rt2800_bbp_write(rt2x00dev, 81, 0x33);
3448 }
3449
3450 rt2800_bbp_write(rt2x00dev, 82, 0x62);
3451 if (rt2x00_rt(rt2x00dev, RT3290) ||
3452 rt2x00_rt(rt2x00dev, RT5390) ||
3453 rt2x00_rt(rt2x00dev, RT5392))
3454 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
3455 else
3456 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3457
3458 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
3459 rt2800_bbp_write(rt2x00dev, 84, 0x19);
3460 else if (rt2x00_rt(rt2x00dev, RT3290) ||
3461 rt2x00_rt(rt2x00dev, RT5390) ||
3462 rt2x00_rt(rt2x00dev, RT5392))
3463 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
3464 else
3465 rt2800_bbp_write(rt2x00dev, 84, 0x99);
3466
3467 if (rt2x00_rt(rt2x00dev, RT3290) ||
3468 rt2x00_rt(rt2x00dev, RT5390) ||
3469 rt2x00_rt(rt2x00dev, RT5392))
3470 rt2800_bbp_write(rt2x00dev, 86, 0x38);
3471 else
3472 rt2800_bbp_write(rt2x00dev, 86, 0x00);
3473
3474 if (rt2x00_rt(rt2x00dev, RT5392))
3475 rt2800_bbp_write(rt2x00dev, 88, 0x90);
3476
3477 rt2800_bbp_write(rt2x00dev, 91, 0x04);
3478
3479 if (rt2x00_rt(rt2x00dev, RT3290) ||
3480 rt2x00_rt(rt2x00dev, RT5390) ||
3481 rt2x00_rt(rt2x00dev, RT5392))
3482 rt2800_bbp_write(rt2x00dev, 92, 0x02);
3483 else
3484 rt2800_bbp_write(rt2x00dev, 92, 0x00);
3485
3486 if (rt2x00_rt(rt2x00dev, RT5392)) {
3487 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
3488 rt2800_bbp_write(rt2x00dev, 98, 0x12);
3489 }
3490
3491 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
3492 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
3493 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
3494 rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
3495 rt2x00_rt(rt2x00dev, RT3290) ||
3496 rt2x00_rt(rt2x00dev, RT3572) ||
3497 rt2x00_rt(rt2x00dev, RT5390) ||
3498 rt2x00_rt(rt2x00dev, RT5392) ||
3499 rt2800_is_305x_soc(rt2x00dev))
3500 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
3501 else
3502 rt2800_bbp_write(rt2x00dev, 103, 0x00);
3503
3504 if (rt2x00_rt(rt2x00dev, RT3290) ||
3505 rt2x00_rt(rt2x00dev, RT5390) ||
3506 rt2x00_rt(rt2x00dev, RT5392))
3507 rt2800_bbp_write(rt2x00dev, 104, 0x92);
3508
3509 if (rt2800_is_305x_soc(rt2x00dev))
3510 rt2800_bbp_write(rt2x00dev, 105, 0x01);
3511 else if (rt2x00_rt(rt2x00dev, RT3290))
3512 rt2800_bbp_write(rt2x00dev, 105, 0x1c);
3513 else if (rt2x00_rt(rt2x00dev, RT5390) ||
3514 rt2x00_rt(rt2x00dev, RT5392))
3515 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
3516 else
3517 rt2800_bbp_write(rt2x00dev, 105, 0x05);
3518
3519 if (rt2x00_rt(rt2x00dev, RT3290) ||
3520 rt2x00_rt(rt2x00dev, RT5390))
3521 rt2800_bbp_write(rt2x00dev, 106, 0x03);
3522 else if (rt2x00_rt(rt2x00dev, RT5392))
3523 rt2800_bbp_write(rt2x00dev, 106, 0x12);
3524 else
3525 rt2800_bbp_write(rt2x00dev, 106, 0x35);
3526
3527 if (rt2x00_rt(rt2x00dev, RT3290) ||
3528 rt2x00_rt(rt2x00dev, RT5390) ||
3529 rt2x00_rt(rt2x00dev, RT5392))
3530 rt2800_bbp_write(rt2x00dev, 128, 0x12);
3531
3532 if (rt2x00_rt(rt2x00dev, RT5392)) {
3533 rt2800_bbp_write(rt2x00dev, 134, 0xd0);
3534 rt2800_bbp_write(rt2x00dev, 135, 0xf6);
3535 }
3536
3537 if (rt2x00_rt(rt2x00dev, RT3071) ||
3538 rt2x00_rt(rt2x00dev, RT3090) ||
3539 rt2x00_rt(rt2x00dev, RT3390) ||
3540 rt2x00_rt(rt2x00dev, RT3572) ||
3541 rt2x00_rt(rt2x00dev, RT5390) ||
3542 rt2x00_rt(rt2x00dev, RT5392)) {
3543 rt2800_bbp_read(rt2x00dev, 138, &value);
3544
3545 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
3546 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
3547 value |= 0x20;
3548 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
3549 value &= ~0x02;
3550
3551 rt2800_bbp_write(rt2x00dev, 138, value);
3552 }
3553
3554 if (rt2x00_rt(rt2x00dev, RT3290)) {
3555 rt2800_bbp_write(rt2x00dev, 67, 0x24);
3556 rt2800_bbp_write(rt2x00dev, 143, 0x04);
3557 rt2800_bbp_write(rt2x00dev, 142, 0x99);
3558 rt2800_bbp_write(rt2x00dev, 150, 0x30);
3559 rt2800_bbp_write(rt2x00dev, 151, 0x2e);
3560 rt2800_bbp_write(rt2x00dev, 152, 0x20);
3561 rt2800_bbp_write(rt2x00dev, 153, 0x34);
3562 rt2800_bbp_write(rt2x00dev, 154, 0x40);
3563 rt2800_bbp_write(rt2x00dev, 155, 0x3b);
3564 rt2800_bbp_write(rt2x00dev, 253, 0x04);
3565
3566 rt2800_bbp_read(rt2x00dev, 47, &value);
3567 rt2x00_set_field8(&value, BBP47_TSSI_ADC6, 1);
3568 rt2800_bbp_write(rt2x00dev, 47, value);
3569
3570 /* Use 5-bit ADC for Acquisition and 8-bit ADC for data */
3571 rt2800_bbp_read(rt2x00dev, 3, &value);
3572 rt2x00_set_field8(&value, BBP3_ADC_MODE_SWITCH, 1);
3573 rt2x00_set_field8(&value, BBP3_ADC_INIT_MODE, 1);
3574 rt2800_bbp_write(rt2x00dev, 3, value);
3575 }
3576
3577 if (rt2x00_rt(rt2x00dev, RT5390) ||
3578 rt2x00_rt(rt2x00dev, RT5392)) {
3579 int ant, div_mode;
3580
3581 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3582 div_mode = rt2x00_get_field16(eeprom,
3583 EEPROM_NIC_CONF1_ANT_DIVERSITY);
3584 ant = (div_mode == 3) ? 1 : 0;
3585
3586 /* check if this is a Bluetooth combo card */
3587 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
3588 u32 reg;
3589
3590 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
3591 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT3, 0);
3592 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT6, 0);
3593 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, 0);
3594 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT6, 0);
3595 if (ant == 0)
3596 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, 1);
3597 else if (ant == 1)
3598 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT6, 1);
3599 rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
3600 }
3601
3602 /* This chip has hardware antenna diversity*/
3603 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
3604 rt2800_bbp_write(rt2x00dev, 150, 0); /* Disable Antenna Software OFDM */
3605 rt2800_bbp_write(rt2x00dev, 151, 0); /* Disable Antenna Software CCK */
3606 rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */
3607 }
3608
3609 rt2800_bbp_read(rt2x00dev, 152, &value);
3610 if (ant == 0)
3611 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
3612 else
3613 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
3614 rt2800_bbp_write(rt2x00dev, 152, value);
3615
3616 /* Init frequency calibration */
3617 rt2800_bbp_write(rt2x00dev, 142, 1);
3618 rt2800_bbp_write(rt2x00dev, 143, 57);
3619 }
3620
3621 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
3622 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
3623
3624 if (eeprom != 0xffff && eeprom != 0x0000) {
3625 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
3626 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
3627 rt2800_bbp_write(rt2x00dev, reg_id, value);
3628 }
3629 }
3630
3631 return 0;
3632 }
3633
3634 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
3635 bool bw40, u8 rfcsr24, u8 filter_target)
3636 {
3637 unsigned int i;
3638 u8 bbp;
3639 u8 rfcsr;
3640 u8 passband;
3641 u8 stopband;
3642 u8 overtuned = 0;
3643
3644 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
3645
3646 rt2800_bbp_read(rt2x00dev, 4, &bbp);
3647 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
3648 rt2800_bbp_write(rt2x00dev, 4, bbp);
3649
3650 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
3651 rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
3652 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
3653
3654 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
3655 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
3656 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
3657
3658 /*
3659 * Set power & frequency of passband test tone
3660 */
3661 rt2800_bbp_write(rt2x00dev, 24, 0);
3662
3663 for (i = 0; i < 100; i++) {
3664 rt2800_bbp_write(rt2x00dev, 25, 0x90);
3665 msleep(1);
3666
3667 rt2800_bbp_read(rt2x00dev, 55, &passband);
3668 if (passband)
3669 break;
3670 }
3671
3672 /*
3673 * Set power & frequency of stopband test tone
3674 */
3675 rt2800_bbp_write(rt2x00dev, 24, 0x06);
3676
3677 for (i = 0; i < 100; i++) {
3678 rt2800_bbp_write(rt2x00dev, 25, 0x90);
3679 msleep(1);
3680
3681 rt2800_bbp_read(rt2x00dev, 55, &stopband);
3682
3683 if ((passband - stopband) <= filter_target) {
3684 rfcsr24++;
3685 overtuned += ((passband - stopband) == filter_target);
3686 } else
3687 break;
3688
3689 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
3690 }
3691
3692 rfcsr24 -= !!overtuned;
3693
3694 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
3695 return rfcsr24;
3696 }
3697
3698 static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
3699 {
3700 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
3701 u8 rfcsr;
3702 u8 bbp;
3703 u32 reg;
3704 u16 eeprom;
3705
3706 if (!rt2x00_rt(rt2x00dev, RT3070) &&
3707 !rt2x00_rt(rt2x00dev, RT3071) &&
3708 !rt2x00_rt(rt2x00dev, RT3090) &&
3709 !rt2x00_rt(rt2x00dev, RT3290) &&
3710 !rt2x00_rt(rt2x00dev, RT3390) &&
3711 !rt2x00_rt(rt2x00dev, RT3572) &&
3712 !rt2x00_rt(rt2x00dev, RT5390) &&
3713 !rt2x00_rt(rt2x00dev, RT5392) &&
3714 !rt2800_is_305x_soc(rt2x00dev))
3715 return 0;
3716
3717 /*
3718 * Init RF calibration.
3719 */
3720 if (rt2x00_rt(rt2x00dev, RT3290) ||
3721 rt2x00_rt(rt2x00dev, RT5390) ||
3722 rt2x00_rt(rt2x00dev, RT5392)) {
3723 rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
3724 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
3725 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
3726 msleep(1);
3727 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 0);
3728 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
3729 } else {
3730 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
3731 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
3732 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3733 msleep(1);
3734 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
3735 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3736 }
3737
3738 if (rt2x00_rt(rt2x00dev, RT3070) ||
3739 rt2x00_rt(rt2x00dev, RT3071) ||
3740 rt2x00_rt(rt2x00dev, RT3090)) {
3741 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
3742 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
3743 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
3744 rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
3745 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
3746 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
3747 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
3748 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
3749 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
3750 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
3751 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
3752 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
3753 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
3754 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
3755 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
3756 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
3757 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
3758 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
3759 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
3760 } else if (rt2x00_rt(rt2x00dev, RT3290)) {
3761 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
3762 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
3763 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
3764 rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
3765 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
3766 rt2800_rfcsr_write(rt2x00dev, 8, 0xf3);
3767 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
3768 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
3769 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
3770 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
3771 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
3772 rt2800_rfcsr_write(rt2x00dev, 18, 0x02);
3773 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
3774 rt2800_rfcsr_write(rt2x00dev, 25, 0x83);
3775 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
3776 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
3777 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
3778 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
3779 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
3780 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
3781 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
3782 rt2800_rfcsr_write(rt2x00dev, 34, 0x05);
3783 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
3784 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
3785 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
3786 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
3787 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
3788 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
3789 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
3790 rt2800_rfcsr_write(rt2x00dev, 43, 0x7b);
3791 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
3792 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
3793 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
3794 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
3795 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
3796 rt2800_rfcsr_write(rt2x00dev, 49, 0x98);
3797 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
3798 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
3799 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
3800 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
3801 rt2800_rfcsr_write(rt2x00dev, 56, 0x02);
3802 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
3803 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
3804 rt2800_rfcsr_write(rt2x00dev, 59, 0x09);
3805 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
3806 rt2800_rfcsr_write(rt2x00dev, 61, 0xc1);
3807 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
3808 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
3809 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
3810 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
3811 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
3812 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
3813 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
3814 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
3815 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
3816 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
3817 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
3818 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
3819 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
3820 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
3821 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
3822 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
3823 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
3824 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
3825 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
3826 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
3827 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
3828 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
3829 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
3830 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
3831 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
3832 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
3833 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
3834 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
3835 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
3836 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
3837 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
3838 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
3839 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
3840 } else if (rt2x00_rt(rt2x00dev, RT3572)) {
3841 rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
3842 rt2800_rfcsr_write(rt2x00dev, 1, 0x81);
3843 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
3844 rt2800_rfcsr_write(rt2x00dev, 3, 0x02);
3845 rt2800_rfcsr_write(rt2x00dev, 4, 0x4c);
3846 rt2800_rfcsr_write(rt2x00dev, 5, 0x05);
3847 rt2800_rfcsr_write(rt2x00dev, 6, 0x4a);
3848 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
3849 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
3850 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
3851 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
3852 rt2800_rfcsr_write(rt2x00dev, 12, 0x70);
3853 rt2800_rfcsr_write(rt2x00dev, 13, 0x65);
3854 rt2800_rfcsr_write(rt2x00dev, 14, 0xa0);
3855 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
3856 rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
3857 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
3858 rt2800_rfcsr_write(rt2x00dev, 18, 0xac);
3859 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
3860 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
3861 rt2800_rfcsr_write(rt2x00dev, 21, 0xd0);
3862 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
3863 rt2800_rfcsr_write(rt2x00dev, 23, 0x3c);
3864 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
3865 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
3866 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
3867 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
3868 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
3869 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
3870 rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
3871 rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
3872 } else if (rt2800_is_305x_soc(rt2x00dev)) {
3873 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
3874 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
3875 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
3876 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
3877 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
3878 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
3879 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
3880 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
3881 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
3882 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
3883 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
3884 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
3885 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
3886 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
3887 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
3888 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
3889 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
3890 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
3891 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
3892 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
3893 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
3894 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
3895 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
3896 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
3897 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
3898 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
3899 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
3900 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
3901 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
3902 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
3903 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
3904 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
3905 return 0;
3906 } else if (rt2x00_rt(rt2x00dev, RT5390)) {
3907 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
3908 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
3909 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
3910 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
3911 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3912 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
3913 else
3914 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
3915 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
3916 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
3917 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
3918 rt2800_rfcsr_write(rt2x00dev, 12, 0xc6);
3919 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
3920 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
3921 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
3922 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
3923 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
3924 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
3925
3926 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
3927 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
3928 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
3929 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
3930 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
3931 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3932 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
3933 else
3934 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
3935 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
3936 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
3937 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
3938 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
3939
3940 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
3941 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
3942 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
3943 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
3944 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
3945 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
3946 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
3947 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
3948 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
3949 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
3950
3951 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3952 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
3953 else
3954 rt2800_rfcsr_write(rt2x00dev, 40, 0x4b);
3955 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
3956 rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
3957 rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
3958 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
3959 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
3960 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3961 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
3962 else
3963 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
3964 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
3965 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
3966 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
3967
3968 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
3969 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3970 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
3971 else
3972 rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
3973 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
3974 rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
3975 rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
3976 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
3977 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
3978 rt2800_rfcsr_write(rt2x00dev, 59, 0x63);
3979
3980 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
3981 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3982 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
3983 else
3984 rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
3985 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
3986 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
3987 } else if (rt2x00_rt(rt2x00dev, RT5392)) {
3988 rt2800_rfcsr_write(rt2x00dev, 1, 0x17);
3989 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
3990 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
3991 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
3992 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
3993 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
3994 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
3995 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
3996 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
3997 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
3998 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
3999 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
4000 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
4001 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
4002 rt2800_rfcsr_write(rt2x00dev, 19, 0x4d);
4003 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
4004 rt2800_rfcsr_write(rt2x00dev, 21, 0x8d);
4005 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
4006 rt2800_rfcsr_write(rt2x00dev, 23, 0x0b);
4007 rt2800_rfcsr_write(rt2x00dev, 24, 0x44);
4008 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
4009 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
4010 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
4011 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
4012 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
4013 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
4014 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
4015 rt2800_rfcsr_write(rt2x00dev, 32, 0x20);
4016 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
4017 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
4018 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
4019 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
4020 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
4021 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
4022 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
4023 rt2800_rfcsr_write(rt2x00dev, 40, 0x0f);
4024 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
4025 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
4026 rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
4027 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
4028 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
4029 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
4030 rt2800_rfcsr_write(rt2x00dev, 47, 0x0c);
4031 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
4032 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
4033 rt2800_rfcsr_write(rt2x00dev, 50, 0x94);
4034 rt2800_rfcsr_write(rt2x00dev, 51, 0x3a);
4035 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
4036 rt2800_rfcsr_write(rt2x00dev, 53, 0x44);
4037 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
4038 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
4039 rt2800_rfcsr_write(rt2x00dev, 56, 0xa1);
4040 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
4041 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
4042 rt2800_rfcsr_write(rt2x00dev, 59, 0x07);
4043 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
4044 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
4045 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
4046 rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
4047 }
4048
4049 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
4050 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
4051 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
4052 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
4053 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
4054 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
4055 rt2x00_rt(rt2x00dev, RT3090)) {
4056 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
4057
4058 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
4059 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
4060 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
4061
4062 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
4063 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
4064 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
4065 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
4066 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
4067 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
4068 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
4069 else
4070 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
4071 }
4072 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
4073
4074 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
4075 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
4076 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
4077 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
4078 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
4079 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
4080 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
4081 } else if (rt2x00_rt(rt2x00dev, RT3572)) {
4082 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
4083 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
4084 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
4085
4086 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
4087 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
4088 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
4089 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
4090 msleep(1);
4091 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
4092 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
4093 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
4094 }
4095
4096 /*
4097 * Set RX Filter calibration for 20MHz and 40MHz
4098 */
4099 if (rt2x00_rt(rt2x00dev, RT3070)) {
4100 drv_data->calibration_bw20 =
4101 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
4102 drv_data->calibration_bw40 =
4103 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
4104 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
4105 rt2x00_rt(rt2x00dev, RT3090) ||
4106 rt2x00_rt(rt2x00dev, RT3390) ||
4107 rt2x00_rt(rt2x00dev, RT3572)) {
4108 drv_data->calibration_bw20 =
4109 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
4110 drv_data->calibration_bw40 =
4111 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
4112 }
4113
4114 /*
4115 * Save BBP 25 & 26 values for later use in channel switching
4116 */
4117 rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25);
4118 rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26);
4119
4120 if (!rt2x00_rt(rt2x00dev, RT5390) &&
4121 !rt2x00_rt(rt2x00dev, RT5392)) {
4122 /*
4123 * Set back to initial state
4124 */
4125 rt2800_bbp_write(rt2x00dev, 24, 0);
4126
4127 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
4128 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
4129 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
4130
4131 /*
4132 * Set BBP back to BW20
4133 */
4134 rt2800_bbp_read(rt2x00dev, 4, &bbp);
4135 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
4136 rt2800_bbp_write(rt2x00dev, 4, bbp);
4137 }
4138
4139 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
4140 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
4141 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
4142 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
4143 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
4144
4145 rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
4146 rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
4147 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
4148
4149 if (!rt2x00_rt(rt2x00dev, RT5390) &&
4150 !rt2x00_rt(rt2x00dev, RT5392)) {
4151 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
4152 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
4153 if (rt2x00_rt(rt2x00dev, RT3070) ||
4154 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
4155 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
4156 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
4157 if (!test_bit(CAPABILITY_EXTERNAL_LNA_BG,
4158 &rt2x00dev->cap_flags))
4159 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
4160 }
4161 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
4162 drv_data->txmixer_gain_24g);
4163 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
4164 }
4165
4166 if (rt2x00_rt(rt2x00dev, RT3090)) {
4167 rt2800_bbp_read(rt2x00dev, 138, &bbp);
4168
4169 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
4170 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
4171 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
4172 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
4173 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
4174 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
4175
4176 rt2800_bbp_write(rt2x00dev, 138, bbp);
4177 }
4178
4179 if (rt2x00_rt(rt2x00dev, RT3071) ||
4180 rt2x00_rt(rt2x00dev, RT3090) ||
4181 rt2x00_rt(rt2x00dev, RT3390)) {
4182 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
4183 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
4184 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
4185 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
4186 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
4187 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
4188 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
4189
4190 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
4191 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
4192 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
4193
4194 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
4195 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
4196 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
4197
4198 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
4199 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
4200 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
4201 }
4202
4203 if (rt2x00_rt(rt2x00dev, RT3070)) {
4204 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
4205 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
4206 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
4207 else
4208 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
4209 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
4210 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
4211 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
4212 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
4213 }
4214
4215 if (rt2x00_rt(rt2x00dev, RT3290)) {
4216 rt2800_rfcsr_read(rt2x00dev, 29, &rfcsr);
4217 rt2x00_set_field8(&rfcsr, RFCSR29_RSSI_GAIN, 3);
4218 rt2800_rfcsr_write(rt2x00dev, 29, rfcsr);
4219 }
4220
4221 if (rt2x00_rt(rt2x00dev, RT5390) ||
4222 rt2x00_rt(rt2x00dev, RT5392)) {
4223 rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr);
4224 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
4225 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
4226
4227 rt2800_rfcsr_read(rt2x00dev, 39, &rfcsr);
4228 rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
4229 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
4230
4231 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
4232 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
4233 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
4234 }
4235
4236 return 0;
4237 }
4238
4239 int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
4240 {
4241 u32 reg;
4242 u16 word;
4243
4244 /*
4245 * Initialize all registers.
4246 */
4247 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
4248 rt2800_init_registers(rt2x00dev) ||
4249 rt2800_init_bbp(rt2x00dev) ||
4250 rt2800_init_rfcsr(rt2x00dev)))
4251 return -EIO;
4252
4253 /*
4254 * Send signal to firmware during boot time.
4255 */
4256 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
4257
4258 if (rt2x00_is_usb(rt2x00dev) &&
4259 (rt2x00_rt(rt2x00dev, RT3070) ||
4260 rt2x00_rt(rt2x00dev, RT3071) ||
4261 rt2x00_rt(rt2x00dev, RT3572))) {
4262 udelay(200);
4263 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
4264 udelay(10);
4265 }
4266
4267 /*
4268 * Enable RX.
4269 */
4270 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
4271 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
4272 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
4273 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
4274
4275 udelay(50);
4276
4277 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
4278 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
4279 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
4280 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
4281 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
4282 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
4283
4284 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
4285 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
4286 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
4287 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
4288
4289 /*
4290 * Initialize LED control
4291 */
4292 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word);
4293 rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
4294 word & 0xff, (word >> 8) & 0xff);
4295
4296 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word);
4297 rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
4298 word & 0xff, (word >> 8) & 0xff);
4299
4300 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word);
4301 rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
4302 word & 0xff, (word >> 8) & 0xff);
4303
4304 return 0;
4305 }
4306 EXPORT_SYMBOL_GPL(rt2800_enable_radio);
4307
4308 void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
4309 {
4310 u32 reg;
4311
4312 rt2800_disable_wpdma(rt2x00dev);
4313
4314 /* Wait for DMA, ignore error */
4315 rt2800_wait_wpdma_ready(rt2x00dev);
4316
4317 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
4318 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
4319 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
4320 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
4321 }
4322 EXPORT_SYMBOL_GPL(rt2800_disable_radio);
4323
4324 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
4325 {
4326 u32 reg;
4327 u16 efuse_ctrl_reg;
4328
4329 if (rt2x00_rt(rt2x00dev, RT3290))
4330 efuse_ctrl_reg = EFUSE_CTRL_3290;
4331 else
4332 efuse_ctrl_reg = EFUSE_CTRL;
4333
4334 rt2800_register_read(rt2x00dev, efuse_ctrl_reg, &reg);
4335 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
4336 }
4337 EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
4338
4339 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
4340 {
4341 u32 reg;
4342 u16 efuse_ctrl_reg;
4343 u16 efuse_data0_reg;
4344 u16 efuse_data1_reg;
4345 u16 efuse_data2_reg;
4346 u16 efuse_data3_reg;
4347
4348 if (rt2x00_rt(rt2x00dev, RT3290)) {
4349 efuse_ctrl_reg = EFUSE_CTRL_3290;
4350 efuse_data0_reg = EFUSE_DATA0_3290;
4351 efuse_data1_reg = EFUSE_DATA1_3290;
4352 efuse_data2_reg = EFUSE_DATA2_3290;
4353 efuse_data3_reg = EFUSE_DATA3_3290;
4354 } else {
4355 efuse_ctrl_reg = EFUSE_CTRL;
4356 efuse_data0_reg = EFUSE_DATA0;
4357 efuse_data1_reg = EFUSE_DATA1;
4358 efuse_data2_reg = EFUSE_DATA2;
4359 efuse_data3_reg = EFUSE_DATA3;
4360 }
4361 mutex_lock(&rt2x00dev->csr_mutex);
4362
4363 rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg, &reg);
4364 rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
4365 rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
4366 rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
4367 rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg);
4368
4369 /* Wait until the EEPROM has been loaded */
4370 rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, &reg);
4371 /* Apparently the data is read from end to start */
4372 rt2800_register_read_lock(rt2x00dev, efuse_data3_reg, &reg);
4373 /* The returned value is in CPU order, but eeprom is le */
4374 *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg);
4375 rt2800_register_read_lock(rt2x00dev, efuse_data2_reg, &reg);
4376 *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg);
4377 rt2800_register_read_lock(rt2x00dev, efuse_data1_reg, &reg);
4378 *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg);
4379 rt2800_register_read_lock(rt2x00dev, efuse_data0_reg, &reg);
4380 *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg);
4381
4382 mutex_unlock(&rt2x00dev->csr_mutex);
4383 }
4384
4385 void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
4386 {
4387 unsigned int i;
4388
4389 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
4390 rt2800_efuse_read(rt2x00dev, i);
4391 }
4392 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
4393
4394 int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
4395 {
4396 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
4397 u16 word;
4398 u8 *mac;
4399 u8 default_lna_gain;
4400
4401 /*
4402 * Start validation of the data that has been read.
4403 */
4404 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
4405 if (!is_valid_ether_addr(mac)) {
4406 eth_random_addr(mac);
4407 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
4408 }
4409
4410 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word);
4411 if (word == 0xffff) {
4412 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
4413 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
4414 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
4415 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
4416 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
4417 } else if (rt2x00_rt(rt2x00dev, RT2860) ||
4418 rt2x00_rt(rt2x00dev, RT2872)) {
4419 /*
4420 * There is a max of 2 RX streams for RT28x0 series
4421 */
4422 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
4423 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
4424 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
4425 }
4426
4427 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
4428 if (word == 0xffff) {
4429 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
4430 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
4431 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
4432 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
4433 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
4434 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
4435 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
4436 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
4437 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
4438 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
4439 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
4440 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
4441 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
4442 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
4443 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
4444 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
4445 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
4446 }
4447
4448 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
4449 if ((word & 0x00ff) == 0x00ff) {
4450 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
4451 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
4452 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
4453 }
4454 if ((word & 0xff00) == 0xff00) {
4455 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
4456 LED_MODE_TXRX_ACTIVITY);
4457 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
4458 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
4459 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
4460 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
4461 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
4462 EEPROM(rt2x00dev, "Led Mode: 0x%04x\n", word);
4463 }
4464
4465 /*
4466 * During the LNA validation we are going to use
4467 * lna0 as correct value. Note that EEPROM_LNA
4468 * is never validated.
4469 */
4470 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
4471 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
4472
4473 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
4474 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
4475 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
4476 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
4477 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
4478 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
4479
4480 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &word);
4481 if ((word & 0x00ff) != 0x00ff) {
4482 drv_data->txmixer_gain_24g =
4483 rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL);
4484 } else {
4485 drv_data->txmixer_gain_24g = 0;
4486 }
4487
4488 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
4489 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
4490 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
4491 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
4492 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
4493 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
4494 default_lna_gain);
4495 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
4496
4497 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A, &word);
4498 if ((word & 0x00ff) != 0x00ff) {
4499 drv_data->txmixer_gain_5g =
4500 rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL);
4501 } else {
4502 drv_data->txmixer_gain_5g = 0;
4503 }
4504
4505 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
4506 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
4507 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
4508 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
4509 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
4510 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
4511
4512 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
4513 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
4514 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
4515 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
4516 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
4517 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
4518 default_lna_gain);
4519 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
4520
4521 return 0;
4522 }
4523 EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
4524
4525 int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
4526 {
4527 u32 reg;
4528 u16 value;
4529 u16 eeprom;
4530
4531 /*
4532 * Read EEPROM word for configuration.
4533 */
4534 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
4535
4536 /*
4537 * Identify RF chipset by EEPROM value
4538 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
4539 * RT53xx: defined in "EEPROM_CHIP_ID" field
4540 */
4541 if (rt2x00_rt(rt2x00dev, RT3290))
4542 rt2800_register_read(rt2x00dev, MAC_CSR0_3290, &reg);
4543 else
4544 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
4545
4546 if (rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT3290 ||
4547 rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5390 ||
4548 rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5392)
4549 rt2x00_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &value);
4550 else
4551 value = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
4552
4553 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
4554 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
4555
4556 switch (rt2x00dev->chip.rt) {
4557 case RT2860:
4558 case RT2872:
4559 case RT2883:
4560 case RT3070:
4561 case RT3071:
4562 case RT3090:
4563 case RT3290:
4564 case RT3390:
4565 case RT3572:
4566 case RT5390:
4567 case RT5392:
4568 break;
4569 default:
4570 ERROR(rt2x00dev, "Invalid RT chipset 0x%04x detected.\n", rt2x00dev->chip.rt);
4571 return -ENODEV;
4572 }
4573
4574 switch (rt2x00dev->chip.rf) {
4575 case RF2820:
4576 case RF2850:
4577 case RF2720:
4578 case RF2750:
4579 case RF3020:
4580 case RF2020:
4581 case RF3021:
4582 case RF3022:
4583 case RF3052:
4584 case RF3290:
4585 case RF3320:
4586 case RF5360:
4587 case RF5370:
4588 case RF5372:
4589 case RF5390:
4590 case RF5392:
4591 break;
4592 default:
4593 ERROR(rt2x00dev, "Invalid RF chipset 0x%04x detected.\n",
4594 rt2x00dev->chip.rf);
4595 return -ENODEV;
4596 }
4597
4598 /*
4599 * Identify default antenna configuration.
4600 */
4601 rt2x00dev->default_ant.tx_chain_num =
4602 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
4603 rt2x00dev->default_ant.rx_chain_num =
4604 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
4605
4606 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
4607
4608 if (rt2x00_rt(rt2x00dev, RT3070) ||
4609 rt2x00_rt(rt2x00dev, RT3090) ||
4610 rt2x00_rt(rt2x00dev, RT3390)) {
4611 value = rt2x00_get_field16(eeprom,
4612 EEPROM_NIC_CONF1_ANT_DIVERSITY);
4613 switch (value) {
4614 case 0:
4615 case 1:
4616 case 2:
4617 rt2x00dev->default_ant.tx = ANTENNA_A;
4618 rt2x00dev->default_ant.rx = ANTENNA_A;
4619 break;
4620 case 3:
4621 rt2x00dev->default_ant.tx = ANTENNA_A;
4622 rt2x00dev->default_ant.rx = ANTENNA_B;
4623 break;
4624 }
4625 } else {
4626 rt2x00dev->default_ant.tx = ANTENNA_A;
4627 rt2x00dev->default_ant.rx = ANTENNA_A;
4628 }
4629
4630 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
4631 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; /* Unused */
4632 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; /* Unused */
4633 }
4634
4635 /*
4636 * Determine external LNA informations.
4637 */
4638 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
4639 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
4640 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
4641 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
4642
4643 /*
4644 * Detect if this device has an hardware controlled radio.
4645 */
4646 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
4647 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
4648
4649 /*
4650 * Detect if this device has Bluetooth co-existence.
4651 */
4652 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST))
4653 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags);
4654
4655 /*
4656 * Read frequency offset and RF programming sequence.
4657 */
4658 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
4659 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
4660
4661 /*
4662 * Store led settings, for correct led behaviour.
4663 */
4664 #ifdef CONFIG_RT2X00_LIB_LEDS
4665 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
4666 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
4667 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
4668
4669 rt2x00dev->led_mcu_reg = eeprom;
4670 #endif /* CONFIG_RT2X00_LIB_LEDS */
4671
4672 /*
4673 * Check if support EIRP tx power limit feature.
4674 */
4675 rt2x00_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom);
4676
4677 if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
4678 EIRP_MAX_TX_POWER_LIMIT)
4679 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
4680
4681 return 0;
4682 }
4683 EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
4684
4685 /*
4686 * RF value list for rt28xx
4687 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
4688 */
4689 static const struct rf_channel rf_vals[] = {
4690 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
4691 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
4692 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
4693 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
4694 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
4695 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
4696 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
4697 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
4698 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
4699 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
4700 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
4701 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
4702 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
4703 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
4704
4705 /* 802.11 UNI / HyperLan 2 */
4706 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
4707 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
4708 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
4709 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
4710 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
4711 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
4712 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
4713 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
4714 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
4715 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
4716 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
4717 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
4718
4719 /* 802.11 HyperLan 2 */
4720 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
4721 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
4722 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
4723 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
4724 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
4725 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
4726 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
4727 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
4728 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
4729 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
4730 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
4731 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
4732 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
4733 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
4734 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
4735 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
4736
4737 /* 802.11 UNII */
4738 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
4739 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
4740 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
4741 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
4742 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
4743 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
4744 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
4745 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
4746 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
4747 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
4748 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
4749
4750 /* 802.11 Japan */
4751 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
4752 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
4753 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
4754 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
4755 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
4756 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
4757 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
4758 };
4759
4760 /*
4761 * RF value list for rt3xxx
4762 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
4763 */
4764 static const struct rf_channel rf_vals_3x[] = {
4765 {1, 241, 2, 2 },
4766 {2, 241, 2, 7 },
4767 {3, 242, 2, 2 },
4768 {4, 242, 2, 7 },
4769 {5, 243, 2, 2 },
4770 {6, 243, 2, 7 },
4771 {7, 244, 2, 2 },
4772 {8, 244, 2, 7 },
4773 {9, 245, 2, 2 },
4774 {10, 245, 2, 7 },
4775 {11, 246, 2, 2 },
4776 {12, 246, 2, 7 },
4777 {13, 247, 2, 2 },
4778 {14, 248, 2, 4 },
4779
4780 /* 802.11 UNI / HyperLan 2 */
4781 {36, 0x56, 0, 4},
4782 {38, 0x56, 0, 6},
4783 {40, 0x56, 0, 8},
4784 {44, 0x57, 0, 0},
4785 {46, 0x57, 0, 2},
4786 {48, 0x57, 0, 4},
4787 {52, 0x57, 0, 8},
4788 {54, 0x57, 0, 10},
4789 {56, 0x58, 0, 0},
4790 {60, 0x58, 0, 4},
4791 {62, 0x58, 0, 6},
4792 {64, 0x58, 0, 8},
4793
4794 /* 802.11 HyperLan 2 */
4795 {100, 0x5b, 0, 8},
4796 {102, 0x5b, 0, 10},
4797 {104, 0x5c, 0, 0},
4798 {108, 0x5c, 0, 4},
4799 {110, 0x5c, 0, 6},
4800 {112, 0x5c, 0, 8},
4801 {116, 0x5d, 0, 0},
4802 {118, 0x5d, 0, 2},
4803 {120, 0x5d, 0, 4},
4804 {124, 0x5d, 0, 8},
4805 {126, 0x5d, 0, 10},
4806 {128, 0x5e, 0, 0},
4807 {132, 0x5e, 0, 4},
4808 {134, 0x5e, 0, 6},
4809 {136, 0x5e, 0, 8},
4810 {140, 0x5f, 0, 0},
4811
4812 /* 802.11 UNII */
4813 {149, 0x5f, 0, 9},
4814 {151, 0x5f, 0, 11},
4815 {153, 0x60, 0, 1},
4816 {157, 0x60, 0, 5},
4817 {159, 0x60, 0, 7},
4818 {161, 0x60, 0, 9},
4819 {165, 0x61, 0, 1},
4820 {167, 0x61, 0, 3},
4821 {169, 0x61, 0, 5},
4822 {171, 0x61, 0, 7},
4823 {173, 0x61, 0, 9},
4824 };
4825
4826 int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
4827 {
4828 struct hw_mode_spec *spec = &rt2x00dev->spec;
4829 struct channel_info *info;
4830 char *default_power1;
4831 char *default_power2;
4832 unsigned int i;
4833 u16 eeprom;
4834
4835 /*
4836 * Disable powersaving as default on PCI devices.
4837 */
4838 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
4839 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
4840
4841 /*
4842 * Initialize all hw fields.
4843 */
4844 rt2x00dev->hw->flags =
4845 IEEE80211_HW_SIGNAL_DBM |
4846 IEEE80211_HW_SUPPORTS_PS |
4847 IEEE80211_HW_PS_NULLFUNC_STACK |
4848 IEEE80211_HW_AMPDU_AGGREGATION |
4849 IEEE80211_HW_REPORTS_TX_ACK_STATUS;
4850
4851 /*
4852 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
4853 * unless we are capable of sending the buffered frames out after the
4854 * DTIM transmission using rt2x00lib_beacondone. This will send out
4855 * multicast and broadcast traffic immediately instead of buffering it
4856 * infinitly and thus dropping it after some time.
4857 */
4858 if (!rt2x00_is_usb(rt2x00dev))
4859 rt2x00dev->hw->flags |=
4860 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
4861
4862 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
4863 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
4864 rt2x00_eeprom_addr(rt2x00dev,
4865 EEPROM_MAC_ADDR_0));
4866
4867 /*
4868 * As rt2800 has a global fallback table we cannot specify
4869 * more then one tx rate per frame but since the hw will
4870 * try several rates (based on the fallback table) we should
4871 * initialize max_report_rates to the maximum number of rates
4872 * we are going to try. Otherwise mac80211 will truncate our
4873 * reported tx rates and the rc algortihm will end up with
4874 * incorrect data.
4875 */
4876 rt2x00dev->hw->max_rates = 1;
4877 rt2x00dev->hw->max_report_rates = 7;
4878 rt2x00dev->hw->max_rate_tries = 1;
4879
4880 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
4881
4882 /*
4883 * Initialize hw_mode information.
4884 */
4885 spec->supported_bands = SUPPORT_BAND_2GHZ;
4886 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
4887
4888 if (rt2x00_rf(rt2x00dev, RF2820) ||
4889 rt2x00_rf(rt2x00dev, RF2720)) {
4890 spec->num_channels = 14;
4891 spec->channels = rf_vals;
4892 } else if (rt2x00_rf(rt2x00dev, RF2850) ||
4893 rt2x00_rf(rt2x00dev, RF2750)) {
4894 spec->supported_bands |= SUPPORT_BAND_5GHZ;
4895 spec->num_channels = ARRAY_SIZE(rf_vals);
4896 spec->channels = rf_vals;
4897 } else if (rt2x00_rf(rt2x00dev, RF3020) ||
4898 rt2x00_rf(rt2x00dev, RF2020) ||
4899 rt2x00_rf(rt2x00dev, RF3021) ||
4900 rt2x00_rf(rt2x00dev, RF3022) ||
4901 rt2x00_rf(rt2x00dev, RF3290) ||
4902 rt2x00_rf(rt2x00dev, RF3320) ||
4903 rt2x00_rf(rt2x00dev, RF5360) ||
4904 rt2x00_rf(rt2x00dev, RF5370) ||
4905 rt2x00_rf(rt2x00dev, RF5372) ||
4906 rt2x00_rf(rt2x00dev, RF5390) ||
4907 rt2x00_rf(rt2x00dev, RF5392)) {
4908 spec->num_channels = 14;
4909 spec->channels = rf_vals_3x;
4910 } else if (rt2x00_rf(rt2x00dev, RF3052)) {
4911 spec->supported_bands |= SUPPORT_BAND_5GHZ;
4912 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
4913 spec->channels = rf_vals_3x;
4914 }
4915
4916 /*
4917 * Initialize HT information.
4918 */
4919 if (!rt2x00_rf(rt2x00dev, RF2020))
4920 spec->ht.ht_supported = true;
4921 else
4922 spec->ht.ht_supported = false;
4923
4924 spec->ht.cap =
4925 IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
4926 IEEE80211_HT_CAP_GRN_FLD |
4927 IEEE80211_HT_CAP_SGI_20 |
4928 IEEE80211_HT_CAP_SGI_40;
4929
4930 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) >= 2)
4931 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
4932
4933 spec->ht.cap |=
4934 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) <<
4935 IEEE80211_HT_CAP_RX_STBC_SHIFT;
4936
4937 spec->ht.ampdu_factor = 3;
4938 spec->ht.ampdu_density = 4;
4939 spec->ht.mcs.tx_params =
4940 IEEE80211_HT_MCS_TX_DEFINED |
4941 IEEE80211_HT_MCS_TX_RX_DIFF |
4942 ((rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) - 1) <<
4943 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
4944
4945 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH)) {
4946 case 3:
4947 spec->ht.mcs.rx_mask[2] = 0xff;
4948 case 2:
4949 spec->ht.mcs.rx_mask[1] = 0xff;
4950 case 1:
4951 spec->ht.mcs.rx_mask[0] = 0xff;
4952 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
4953 break;
4954 }
4955
4956 /*
4957 * Create channel information array
4958 */
4959 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
4960 if (!info)
4961 return -ENOMEM;
4962
4963 spec->channels_info = info;
4964
4965 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
4966 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
4967
4968 for (i = 0; i < 14; i++) {
4969 info[i].default_power1 = default_power1[i];
4970 info[i].default_power2 = default_power2[i];
4971 }
4972
4973 if (spec->num_channels > 14) {
4974 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
4975 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
4976
4977 for (i = 14; i < spec->num_channels; i++) {
4978 info[i].default_power1 = default_power1[i];
4979 info[i].default_power2 = default_power2[i];
4980 }
4981 }
4982
4983 switch (rt2x00dev->chip.rf) {
4984 case RF2020:
4985 case RF3020:
4986 case RF3021:
4987 case RF3022:
4988 case RF3320:
4989 case RF3052:
4990 case RF3290:
4991 case RF5360:
4992 case RF5370:
4993 case RF5372:
4994 case RF5390:
4995 case RF5392:
4996 __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags);
4997 break;
4998 }
4999
5000 return 0;
5001 }
5002 EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode);
5003
5004 /*
5005 * IEEE80211 stack callback functions.
5006 */
5007 void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
5008 u16 *iv16)
5009 {
5010 struct rt2x00_dev *rt2x00dev = hw->priv;
5011 struct mac_iveiv_entry iveiv_entry;
5012 u32 offset;
5013
5014 offset = MAC_IVEIV_ENTRY(hw_key_idx);
5015 rt2800_register_multiread(rt2x00dev, offset,
5016 &iveiv_entry, sizeof(iveiv_entry));
5017
5018 memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
5019 memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
5020 }
5021 EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
5022
5023 int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
5024 {
5025 struct rt2x00_dev *rt2x00dev = hw->priv;
5026 u32 reg;
5027 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
5028
5029 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
5030 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
5031 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
5032
5033 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
5034 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
5035 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
5036
5037 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
5038 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
5039 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
5040
5041 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
5042 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
5043 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
5044
5045 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
5046 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
5047 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
5048
5049 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
5050 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
5051 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
5052
5053 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
5054 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
5055 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
5056
5057 return 0;
5058 }
5059 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
5060
5061 int rt2800_conf_tx(struct ieee80211_hw *hw,
5062 struct ieee80211_vif *vif, u16 queue_idx,
5063 const struct ieee80211_tx_queue_params *params)
5064 {
5065 struct rt2x00_dev *rt2x00dev = hw->priv;
5066 struct data_queue *queue;
5067 struct rt2x00_field32 field;
5068 int retval;
5069 u32 reg;
5070 u32 offset;
5071
5072 /*
5073 * First pass the configuration through rt2x00lib, that will
5074 * update the queue settings and validate the input. After that
5075 * we are free to update the registers based on the value
5076 * in the queue parameter.
5077 */
5078 retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params);
5079 if (retval)
5080 return retval;
5081
5082 /*
5083 * We only need to perform additional register initialization
5084 * for WMM queues/
5085 */
5086 if (queue_idx >= 4)
5087 return 0;
5088
5089 queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
5090
5091 /* Update WMM TXOP register */
5092 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
5093 field.bit_offset = (queue_idx & 1) * 16;
5094 field.bit_mask = 0xffff << field.bit_offset;
5095
5096 rt2800_register_read(rt2x00dev, offset, &reg);
5097 rt2x00_set_field32(&reg, field, queue->txop);
5098 rt2800_register_write(rt2x00dev, offset, reg);
5099
5100 /* Update WMM registers */
5101 field.bit_offset = queue_idx * 4;
5102 field.bit_mask = 0xf << field.bit_offset;
5103
5104 rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
5105 rt2x00_set_field32(&reg, field, queue->aifs);
5106 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
5107
5108 rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
5109 rt2x00_set_field32(&reg, field, queue->cw_min);
5110 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
5111
5112 rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
5113 rt2x00_set_field32(&reg, field, queue->cw_max);
5114 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
5115
5116 /* Update EDCA registers */
5117 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
5118
5119 rt2800_register_read(rt2x00dev, offset, &reg);
5120 rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
5121 rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
5122 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
5123 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
5124 rt2800_register_write(rt2x00dev, offset, reg);
5125
5126 return 0;
5127 }
5128 EXPORT_SYMBOL_GPL(rt2800_conf_tx);
5129
5130 u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
5131 {
5132 struct rt2x00_dev *rt2x00dev = hw->priv;
5133 u64 tsf;
5134 u32 reg;
5135
5136 rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
5137 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
5138 rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
5139 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
5140
5141 return tsf;
5142 }
5143 EXPORT_SYMBOL_GPL(rt2800_get_tsf);
5144
5145 int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5146 enum ieee80211_ampdu_mlme_action action,
5147 struct ieee80211_sta *sta, u16 tid, u16 *ssn,
5148 u8 buf_size)
5149 {
5150 struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv;
5151 int ret = 0;
5152
5153 /*
5154 * Don't allow aggregation for stations the hardware isn't aware
5155 * of because tx status reports for frames to an unknown station
5156 * always contain wcid=255 and thus we can't distinguish between
5157 * multiple stations which leads to unwanted situations when the
5158 * hw reorders frames due to aggregation.
5159 */
5160 if (sta_priv->wcid < 0)
5161 return 1;
5162
5163 switch (action) {
5164 case IEEE80211_AMPDU_RX_START:
5165 case IEEE80211_AMPDU_RX_STOP:
5166 /*
5167 * The hw itself takes care of setting up BlockAck mechanisms.
5168 * So, we only have to allow mac80211 to nagotiate a BlockAck
5169 * agreement. Once that is done, the hw will BlockAck incoming
5170 * AMPDUs without further setup.
5171 */
5172 break;
5173 case IEEE80211_AMPDU_TX_START:
5174 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
5175 break;
5176 case IEEE80211_AMPDU_TX_STOP:
5177 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
5178 break;
5179 case IEEE80211_AMPDU_TX_OPERATIONAL:
5180 break;
5181 default:
5182 WARNING((struct rt2x00_dev *)hw->priv, "Unknown AMPDU action\n");
5183 }
5184
5185 return ret;
5186 }
5187 EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
5188
5189 int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
5190 struct survey_info *survey)
5191 {
5192 struct rt2x00_dev *rt2x00dev = hw->priv;
5193 struct ieee80211_conf *conf = &hw->conf;
5194 u32 idle, busy, busy_ext;
5195
5196 if (idx != 0)
5197 return -ENOENT;
5198
5199 survey->channel = conf->channel;
5200
5201 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle);
5202 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy);
5203 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext);
5204
5205 if (idle || busy) {
5206 survey->filled = SURVEY_INFO_CHANNEL_TIME |
5207 SURVEY_INFO_CHANNEL_TIME_BUSY |
5208 SURVEY_INFO_CHANNEL_TIME_EXT_BUSY;
5209
5210 survey->channel_time = (idle + busy) / 1000;
5211 survey->channel_time_busy = busy / 1000;
5212 survey->channel_time_ext_busy = busy_ext / 1000;
5213 }
5214
5215 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
5216 survey->filled |= SURVEY_INFO_IN_USE;
5217
5218 return 0;
5219
5220 }
5221 EXPORT_SYMBOL_GPL(rt2800_get_survey);
5222
5223 MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
5224 MODULE_VERSION(DRV_VERSION);
5225 MODULE_DESCRIPTION("Ralink RT2800 library");
5226 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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