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[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt2800lib.c
1 /*
2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
3 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
4 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
5 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
6
7 Based on the original rt2800pci.c and rt2800usb.c.
8 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
9 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
10 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
11 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
12 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
13 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
14 <http://rt2x00.serialmonkey.com>
15
16 This program is free software; you can redistribute it and/or modify
17 it under the terms of the GNU General Public License as published by
18 the Free Software Foundation; either version 2 of the License, or
19 (at your option) any later version.
20
21 This program is distributed in the hope that it will be useful,
22 but WITHOUT ANY WARRANTY; without even the implied warranty of
23 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 GNU General Public License for more details.
25
26 You should have received a copy of the GNU General Public License
27 along with this program; if not, write to the
28 Free Software Foundation, Inc.,
29 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32 /*
33 Module: rt2800lib
34 Abstract: rt2800 generic device routines.
35 */
36
37 #include <linux/crc-ccitt.h>
38 #include <linux/kernel.h>
39 #include <linux/module.h>
40 #include <linux/slab.h>
41
42 #include "rt2x00.h"
43 #include "rt2800lib.h"
44 #include "rt2800.h"
45
46 /*
47 * Register access.
48 * All access to the CSR registers will go through the methods
49 * rt2800_register_read and rt2800_register_write.
50 * BBP and RF register require indirect register access,
51 * and use the CSR registers BBPCSR and RFCSR to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
55 * between each attampt. When the busy bit is still set at that time,
56 * the access attempt is considered to have failed,
57 * and we will print an error.
58 * The _lock versions must be used if you already hold the csr_mutex
59 */
60 #define WAIT_FOR_BBP(__dev, __reg) \
61 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
62 #define WAIT_FOR_RFCSR(__dev, __reg) \
63 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
64 #define WAIT_FOR_RF(__dev, __reg) \
65 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
66 #define WAIT_FOR_MCU(__dev, __reg) \
67 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
68 H2M_MAILBOX_CSR_OWNER, (__reg))
69
70 static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
71 {
72 /* check for rt2872 on SoC */
73 if (!rt2x00_is_soc(rt2x00dev) ||
74 !rt2x00_rt(rt2x00dev, RT2872))
75 return false;
76
77 /* we know for sure that these rf chipsets are used on rt305x boards */
78 if (rt2x00_rf(rt2x00dev, RF3020) ||
79 rt2x00_rf(rt2x00dev, RF3021) ||
80 rt2x00_rf(rt2x00dev, RF3022))
81 return true;
82
83 rt2x00_warn(rt2x00dev, "Unknown RF chipset on rt305x\n");
84 return false;
85 }
86
87 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
88 const unsigned int word, const u8 value)
89 {
90 u32 reg;
91
92 mutex_lock(&rt2x00dev->csr_mutex);
93
94 /*
95 * Wait until the BBP becomes available, afterwards we
96 * can safely write the new data into the register.
97 */
98 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
99 reg = 0;
100 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
101 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
102 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
103 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
104 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
105
106 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
107 }
108
109 mutex_unlock(&rt2x00dev->csr_mutex);
110 }
111
112 static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
113 const unsigned int word, u8 *value)
114 {
115 u32 reg;
116
117 mutex_lock(&rt2x00dev->csr_mutex);
118
119 /*
120 * Wait until the BBP becomes available, afterwards we
121 * can safely write the read request into the register.
122 * After the data has been written, we wait until hardware
123 * returns the correct value, if at any time the register
124 * doesn't become available in time, reg will be 0xffffffff
125 * which means we return 0xff to the caller.
126 */
127 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
128 reg = 0;
129 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
130 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
131 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
132 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
133
134 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
135
136 WAIT_FOR_BBP(rt2x00dev, &reg);
137 }
138
139 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
140
141 mutex_unlock(&rt2x00dev->csr_mutex);
142 }
143
144 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
145 const unsigned int word, const u8 value)
146 {
147 u32 reg;
148
149 mutex_lock(&rt2x00dev->csr_mutex);
150
151 /*
152 * Wait until the RFCSR becomes available, afterwards we
153 * can safely write the new data into the register.
154 */
155 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
156 reg = 0;
157 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
158 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
159 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
160 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
161
162 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
163 }
164
165 mutex_unlock(&rt2x00dev->csr_mutex);
166 }
167
168 static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
169 const unsigned int word, u8 *value)
170 {
171 u32 reg;
172
173 mutex_lock(&rt2x00dev->csr_mutex);
174
175 /*
176 * Wait until the RFCSR becomes available, afterwards we
177 * can safely write the read request into the register.
178 * After the data has been written, we wait until hardware
179 * returns the correct value, if at any time the register
180 * doesn't become available in time, reg will be 0xffffffff
181 * which means we return 0xff to the caller.
182 */
183 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
184 reg = 0;
185 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
186 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
187 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
188
189 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
190
191 WAIT_FOR_RFCSR(rt2x00dev, &reg);
192 }
193
194 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
195
196 mutex_unlock(&rt2x00dev->csr_mutex);
197 }
198
199 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
200 const unsigned int word, const u32 value)
201 {
202 u32 reg;
203
204 mutex_lock(&rt2x00dev->csr_mutex);
205
206 /*
207 * Wait until the RF becomes available, afterwards we
208 * can safely write the new data into the register.
209 */
210 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
211 reg = 0;
212 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
213 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
214 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
215 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
216
217 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
218 rt2x00_rf_write(rt2x00dev, word, value);
219 }
220
221 mutex_unlock(&rt2x00dev->csr_mutex);
222 }
223
224 static const unsigned int rt2800_eeprom_map[EEPROM_WORD_COUNT] = {
225 [EEPROM_CHIP_ID] = 0x0000,
226 [EEPROM_VERSION] = 0x0001,
227 [EEPROM_MAC_ADDR_0] = 0x0002,
228 [EEPROM_MAC_ADDR_1] = 0x0003,
229 [EEPROM_MAC_ADDR_2] = 0x0004,
230 [EEPROM_NIC_CONF0] = 0x001a,
231 [EEPROM_NIC_CONF1] = 0x001b,
232 [EEPROM_FREQ] = 0x001d,
233 [EEPROM_LED_AG_CONF] = 0x001e,
234 [EEPROM_LED_ACT_CONF] = 0x001f,
235 [EEPROM_LED_POLARITY] = 0x0020,
236 [EEPROM_NIC_CONF2] = 0x0021,
237 [EEPROM_LNA] = 0x0022,
238 [EEPROM_RSSI_BG] = 0x0023,
239 [EEPROM_RSSI_BG2] = 0x0024,
240 [EEPROM_TXMIXER_GAIN_BG] = 0x0024, /* overlaps with RSSI_BG2 */
241 [EEPROM_RSSI_A] = 0x0025,
242 [EEPROM_RSSI_A2] = 0x0026,
243 [EEPROM_TXMIXER_GAIN_A] = 0x0026, /* overlaps with RSSI_A2 */
244 [EEPROM_EIRP_MAX_TX_POWER] = 0x0027,
245 [EEPROM_TXPOWER_DELTA] = 0x0028,
246 [EEPROM_TXPOWER_BG1] = 0x0029,
247 [EEPROM_TXPOWER_BG2] = 0x0030,
248 [EEPROM_TSSI_BOUND_BG1] = 0x0037,
249 [EEPROM_TSSI_BOUND_BG2] = 0x0038,
250 [EEPROM_TSSI_BOUND_BG3] = 0x0039,
251 [EEPROM_TSSI_BOUND_BG4] = 0x003a,
252 [EEPROM_TSSI_BOUND_BG5] = 0x003b,
253 [EEPROM_TXPOWER_A1] = 0x003c,
254 [EEPROM_TXPOWER_A2] = 0x0053,
255 [EEPROM_TSSI_BOUND_A1] = 0x006a,
256 [EEPROM_TSSI_BOUND_A2] = 0x006b,
257 [EEPROM_TSSI_BOUND_A3] = 0x006c,
258 [EEPROM_TSSI_BOUND_A4] = 0x006d,
259 [EEPROM_TSSI_BOUND_A5] = 0x006e,
260 [EEPROM_TXPOWER_BYRATE] = 0x006f,
261 [EEPROM_BBP_START] = 0x0078,
262 };
263
264 static const unsigned int rt2800_eeprom_map_ext[EEPROM_WORD_COUNT] = {
265 [EEPROM_CHIP_ID] = 0x0000,
266 [EEPROM_VERSION] = 0x0001,
267 [EEPROM_MAC_ADDR_0] = 0x0002,
268 [EEPROM_MAC_ADDR_1] = 0x0003,
269 [EEPROM_MAC_ADDR_2] = 0x0004,
270 [EEPROM_NIC_CONF0] = 0x001a,
271 [EEPROM_NIC_CONF1] = 0x001b,
272 [EEPROM_NIC_CONF2] = 0x001c,
273 [EEPROM_EIRP_MAX_TX_POWER] = 0x0020,
274 [EEPROM_FREQ] = 0x0022,
275 [EEPROM_LED_AG_CONF] = 0x0023,
276 [EEPROM_LED_ACT_CONF] = 0x0024,
277 [EEPROM_LED_POLARITY] = 0x0025,
278 [EEPROM_LNA] = 0x0026,
279 [EEPROM_EXT_LNA2] = 0x0027,
280 [EEPROM_RSSI_BG] = 0x0028,
281 [EEPROM_TXPOWER_DELTA] = 0x0028, /* Overlaps with RSSI_BG */
282 [EEPROM_RSSI_BG2] = 0x0029,
283 [EEPROM_TXMIXER_GAIN_BG] = 0x0029, /* Overlaps with RSSI_BG2 */
284 [EEPROM_RSSI_A] = 0x002a,
285 [EEPROM_RSSI_A2] = 0x002b,
286 [EEPROM_TXMIXER_GAIN_A] = 0x002b, /* Overlaps with RSSI_A2 */
287 [EEPROM_TXPOWER_BG1] = 0x0030,
288 [EEPROM_TXPOWER_BG2] = 0x0037,
289 [EEPROM_EXT_TXPOWER_BG3] = 0x003e,
290 [EEPROM_TSSI_BOUND_BG1] = 0x0045,
291 [EEPROM_TSSI_BOUND_BG2] = 0x0046,
292 [EEPROM_TSSI_BOUND_BG3] = 0x0047,
293 [EEPROM_TSSI_BOUND_BG4] = 0x0048,
294 [EEPROM_TSSI_BOUND_BG5] = 0x0049,
295 [EEPROM_TXPOWER_A1] = 0x004b,
296 [EEPROM_TXPOWER_A2] = 0x0065,
297 [EEPROM_EXT_TXPOWER_A3] = 0x007f,
298 [EEPROM_TSSI_BOUND_A1] = 0x009a,
299 [EEPROM_TSSI_BOUND_A2] = 0x009b,
300 [EEPROM_TSSI_BOUND_A3] = 0x009c,
301 [EEPROM_TSSI_BOUND_A4] = 0x009d,
302 [EEPROM_TSSI_BOUND_A5] = 0x009e,
303 [EEPROM_TXPOWER_BYRATE] = 0x00a0,
304 };
305
306 static unsigned int rt2800_eeprom_word_index(struct rt2x00_dev *rt2x00dev,
307 const enum rt2800_eeprom_word word)
308 {
309 const unsigned int *map;
310 unsigned int index;
311
312 if (WARN_ONCE(word >= EEPROM_WORD_COUNT,
313 "%s: invalid EEPROM word %d\n",
314 wiphy_name(rt2x00dev->hw->wiphy), word))
315 return 0;
316
317 if (rt2x00_rt(rt2x00dev, RT3593))
318 map = rt2800_eeprom_map_ext;
319 else
320 map = rt2800_eeprom_map;
321
322 index = map[word];
323
324 /* Index 0 is valid only for EEPROM_CHIP_ID.
325 * Otherwise it means that the offset of the
326 * given word is not initialized in the map,
327 * or that the field is not usable on the
328 * actual chipset.
329 */
330 WARN_ONCE(word != EEPROM_CHIP_ID && index == 0,
331 "%s: invalid access of EEPROM word %d\n",
332 wiphy_name(rt2x00dev->hw->wiphy), word);
333
334 return index;
335 }
336
337 static void *rt2800_eeprom_addr(struct rt2x00_dev *rt2x00dev,
338 const enum rt2800_eeprom_word word)
339 {
340 unsigned int index;
341
342 index = rt2800_eeprom_word_index(rt2x00dev, word);
343 return rt2x00_eeprom_addr(rt2x00dev, index);
344 }
345
346 static void rt2800_eeprom_read(struct rt2x00_dev *rt2x00dev,
347 const enum rt2800_eeprom_word word, u16 *data)
348 {
349 unsigned int index;
350
351 index = rt2800_eeprom_word_index(rt2x00dev, word);
352 rt2x00_eeprom_read(rt2x00dev, index, data);
353 }
354
355 static void rt2800_eeprom_write(struct rt2x00_dev *rt2x00dev,
356 const enum rt2800_eeprom_word word, u16 data)
357 {
358 unsigned int index;
359
360 index = rt2800_eeprom_word_index(rt2x00dev, word);
361 rt2x00_eeprom_write(rt2x00dev, index, data);
362 }
363
364 static void rt2800_eeprom_read_from_array(struct rt2x00_dev *rt2x00dev,
365 const enum rt2800_eeprom_word array,
366 unsigned int offset,
367 u16 *data)
368 {
369 unsigned int index;
370
371 index = rt2800_eeprom_word_index(rt2x00dev, array);
372 rt2x00_eeprom_read(rt2x00dev, index + offset, data);
373 }
374
375 static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev)
376 {
377 u32 reg;
378 int i, count;
379
380 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
381 if (rt2x00_get_field32(reg, WLAN_EN))
382 return 0;
383
384 rt2x00_set_field32(&reg, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff);
385 rt2x00_set_field32(&reg, FRC_WL_ANT_SET, 1);
386 rt2x00_set_field32(&reg, WLAN_CLK_EN, 0);
387 rt2x00_set_field32(&reg, WLAN_EN, 1);
388 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
389
390 udelay(REGISTER_BUSY_DELAY);
391
392 count = 0;
393 do {
394 /*
395 * Check PLL_LD & XTAL_RDY.
396 */
397 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
398 rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
399 if (rt2x00_get_field32(reg, PLL_LD) &&
400 rt2x00_get_field32(reg, XTAL_RDY))
401 break;
402 udelay(REGISTER_BUSY_DELAY);
403 }
404
405 if (i >= REGISTER_BUSY_COUNT) {
406
407 if (count >= 10)
408 return -EIO;
409
410 rt2800_register_write(rt2x00dev, 0x58, 0x018);
411 udelay(REGISTER_BUSY_DELAY);
412 rt2800_register_write(rt2x00dev, 0x58, 0x418);
413 udelay(REGISTER_BUSY_DELAY);
414 rt2800_register_write(rt2x00dev, 0x58, 0x618);
415 udelay(REGISTER_BUSY_DELAY);
416 count++;
417 } else {
418 count = 0;
419 }
420
421 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
422 rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 0);
423 rt2x00_set_field32(&reg, WLAN_CLK_EN, 1);
424 rt2x00_set_field32(&reg, WLAN_RESET, 1);
425 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
426 udelay(10);
427 rt2x00_set_field32(&reg, WLAN_RESET, 0);
428 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
429 udelay(10);
430 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, 0x7fffffff);
431 } while (count != 0);
432
433 return 0;
434 }
435
436 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
437 const u8 command, const u8 token,
438 const u8 arg0, const u8 arg1)
439 {
440 u32 reg;
441
442 /*
443 * SOC devices don't support MCU requests.
444 */
445 if (rt2x00_is_soc(rt2x00dev))
446 return;
447
448 mutex_lock(&rt2x00dev->csr_mutex);
449
450 /*
451 * Wait until the MCU becomes available, afterwards we
452 * can safely write the new data into the register.
453 */
454 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
455 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
456 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
457 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
458 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
459 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
460
461 reg = 0;
462 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
463 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
464 }
465
466 mutex_unlock(&rt2x00dev->csr_mutex);
467 }
468 EXPORT_SYMBOL_GPL(rt2800_mcu_request);
469
470 int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
471 {
472 unsigned int i = 0;
473 u32 reg;
474
475 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
476 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
477 if (reg && reg != ~0)
478 return 0;
479 msleep(1);
480 }
481
482 rt2x00_err(rt2x00dev, "Unstable hardware\n");
483 return -EBUSY;
484 }
485 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
486
487 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
488 {
489 unsigned int i;
490 u32 reg;
491
492 /*
493 * Some devices are really slow to respond here. Wait a whole second
494 * before timing out.
495 */
496 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
497 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
498 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
499 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
500 return 0;
501
502 msleep(10);
503 }
504
505 rt2x00_err(rt2x00dev, "WPDMA TX/RX busy [0x%08x]\n", reg);
506 return -EACCES;
507 }
508 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
509
510 void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev)
511 {
512 u32 reg;
513
514 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
515 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
516 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
517 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
518 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
519 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
520 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
521 }
522 EXPORT_SYMBOL_GPL(rt2800_disable_wpdma);
523
524 void rt2800_get_txwi_rxwi_size(struct rt2x00_dev *rt2x00dev,
525 unsigned short *txwi_size,
526 unsigned short *rxwi_size)
527 {
528 switch (rt2x00dev->chip.rt) {
529 case RT3593:
530 *txwi_size = TXWI_DESC_SIZE_4WORDS;
531 *rxwi_size = RXWI_DESC_SIZE_5WORDS;
532 break;
533
534 case RT5592:
535 *txwi_size = TXWI_DESC_SIZE_5WORDS;
536 *rxwi_size = RXWI_DESC_SIZE_6WORDS;
537 break;
538
539 default:
540 *txwi_size = TXWI_DESC_SIZE_4WORDS;
541 *rxwi_size = RXWI_DESC_SIZE_4WORDS;
542 break;
543 }
544 }
545 EXPORT_SYMBOL_GPL(rt2800_get_txwi_rxwi_size);
546
547 static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
548 {
549 u16 fw_crc;
550 u16 crc;
551
552 /*
553 * The last 2 bytes in the firmware array are the crc checksum itself,
554 * this means that we should never pass those 2 bytes to the crc
555 * algorithm.
556 */
557 fw_crc = (data[len - 2] << 8 | data[len - 1]);
558
559 /*
560 * Use the crc ccitt algorithm.
561 * This will return the same value as the legacy driver which
562 * used bit ordering reversion on the both the firmware bytes
563 * before input input as well as on the final output.
564 * Obviously using crc ccitt directly is much more efficient.
565 */
566 crc = crc_ccitt(~0, data, len - 2);
567
568 /*
569 * There is a small difference between the crc-itu-t + bitrev and
570 * the crc-ccitt crc calculation. In the latter method the 2 bytes
571 * will be swapped, use swab16 to convert the crc to the correct
572 * value.
573 */
574 crc = swab16(crc);
575
576 return fw_crc == crc;
577 }
578
579 int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
580 const u8 *data, const size_t len)
581 {
582 size_t offset = 0;
583 size_t fw_len;
584 bool multiple;
585
586 /*
587 * PCI(e) & SOC devices require firmware with a length
588 * of 8kb. USB devices require firmware files with a length
589 * of 4kb. Certain USB chipsets however require different firmware,
590 * which Ralink only provides attached to the original firmware
591 * file. Thus for USB devices, firmware files have a length
592 * which is a multiple of 4kb. The firmware for rt3290 chip also
593 * have a length which is a multiple of 4kb.
594 */
595 if (rt2x00_is_usb(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3290))
596 fw_len = 4096;
597 else
598 fw_len = 8192;
599
600 multiple = true;
601 /*
602 * Validate the firmware length
603 */
604 if (len != fw_len && (!multiple || (len % fw_len) != 0))
605 return FW_BAD_LENGTH;
606
607 /*
608 * Check if the chipset requires one of the upper parts
609 * of the firmware.
610 */
611 if (rt2x00_is_usb(rt2x00dev) &&
612 !rt2x00_rt(rt2x00dev, RT2860) &&
613 !rt2x00_rt(rt2x00dev, RT2872) &&
614 !rt2x00_rt(rt2x00dev, RT3070) &&
615 ((len / fw_len) == 1))
616 return FW_BAD_VERSION;
617
618 /*
619 * 8kb firmware files must be checked as if it were
620 * 2 separate firmware files.
621 */
622 while (offset < len) {
623 if (!rt2800_check_firmware_crc(data + offset, fw_len))
624 return FW_BAD_CRC;
625
626 offset += fw_len;
627 }
628
629 return FW_OK;
630 }
631 EXPORT_SYMBOL_GPL(rt2800_check_firmware);
632
633 int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
634 const u8 *data, const size_t len)
635 {
636 unsigned int i;
637 u32 reg;
638 int retval;
639
640 if (rt2x00_rt(rt2x00dev, RT3290)) {
641 retval = rt2800_enable_wlan_rt3290(rt2x00dev);
642 if (retval)
643 return -EBUSY;
644 }
645
646 /*
647 * If driver doesn't wake up firmware here,
648 * rt2800_load_firmware will hang forever when interface is up again.
649 */
650 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
651
652 /*
653 * Wait for stable hardware.
654 */
655 if (rt2800_wait_csr_ready(rt2x00dev))
656 return -EBUSY;
657
658 if (rt2x00_is_pci(rt2x00dev)) {
659 if (rt2x00_rt(rt2x00dev, RT3290) ||
660 rt2x00_rt(rt2x00dev, RT3572) ||
661 rt2x00_rt(rt2x00dev, RT5390) ||
662 rt2x00_rt(rt2x00dev, RT5392)) {
663 rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);
664 rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
665 rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
666 rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
667 }
668 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
669 }
670
671 rt2800_disable_wpdma(rt2x00dev);
672
673 /*
674 * Write firmware to the device.
675 */
676 rt2800_drv_write_firmware(rt2x00dev, data, len);
677
678 /*
679 * Wait for device to stabilize.
680 */
681 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
682 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
683 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
684 break;
685 msleep(1);
686 }
687
688 if (i == REGISTER_BUSY_COUNT) {
689 rt2x00_err(rt2x00dev, "PBF system register not ready\n");
690 return -EBUSY;
691 }
692
693 /*
694 * Disable DMA, will be reenabled later when enabling
695 * the radio.
696 */
697 rt2800_disable_wpdma(rt2x00dev);
698
699 /*
700 * Initialize firmware.
701 */
702 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
703 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
704 if (rt2x00_is_usb(rt2x00dev)) {
705 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
706 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
707 }
708 msleep(1);
709
710 return 0;
711 }
712 EXPORT_SYMBOL_GPL(rt2800_load_firmware);
713
714 void rt2800_write_tx_data(struct queue_entry *entry,
715 struct txentry_desc *txdesc)
716 {
717 __le32 *txwi = rt2800_drv_get_txwi(entry);
718 u32 word;
719 int i;
720
721 /*
722 * Initialize TX Info descriptor
723 */
724 rt2x00_desc_read(txwi, 0, &word);
725 rt2x00_set_field32(&word, TXWI_W0_FRAG,
726 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
727 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
728 test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
729 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
730 rt2x00_set_field32(&word, TXWI_W0_TS,
731 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
732 rt2x00_set_field32(&word, TXWI_W0_AMPDU,
733 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
734 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
735 txdesc->u.ht.mpdu_density);
736 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
737 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
738 rt2x00_set_field32(&word, TXWI_W0_BW,
739 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
740 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
741 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
742 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
743 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
744 rt2x00_desc_write(txwi, 0, word);
745
746 rt2x00_desc_read(txwi, 1, &word);
747 rt2x00_set_field32(&word, TXWI_W1_ACK,
748 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
749 rt2x00_set_field32(&word, TXWI_W1_NSEQ,
750 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
751 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
752 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
753 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
754 txdesc->key_idx : txdesc->u.ht.wcid);
755 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
756 txdesc->length);
757 rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
758 rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
759 rt2x00_desc_write(txwi, 1, word);
760
761 /*
762 * Always write 0 to IV/EIV fields (word 2 and 3), hardware will insert
763 * the IV from the IVEIV register when TXD_W3_WIV is set to 0.
764 * When TXD_W3_WIV is set to 1 it will use the IV data
765 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
766 * crypto entry in the registers should be used to encrypt the frame.
767 *
768 * Nulify all remaining words as well, we don't know how to program them.
769 */
770 for (i = 2; i < entry->queue->winfo_size / sizeof(__le32); i++)
771 _rt2x00_desc_write(txwi, i, 0);
772 }
773 EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
774
775 static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
776 {
777 s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
778 s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
779 s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
780 u16 eeprom;
781 u8 offset0;
782 u8 offset1;
783 u8 offset2;
784
785 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
786 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
787 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
788 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
789 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
790 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
791 } else {
792 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
793 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
794 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
795 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
796 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
797 }
798
799 /*
800 * Convert the value from the descriptor into the RSSI value
801 * If the value in the descriptor is 0, it is considered invalid
802 * and the default (extremely low) rssi value is assumed
803 */
804 rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
805 rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
806 rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
807
808 /*
809 * mac80211 only accepts a single RSSI value. Calculating the
810 * average doesn't deliver a fair answer either since -60:-60 would
811 * be considered equally good as -50:-70 while the second is the one
812 * which gives less energy...
813 */
814 rssi0 = max(rssi0, rssi1);
815 return (int)max(rssi0, rssi2);
816 }
817
818 void rt2800_process_rxwi(struct queue_entry *entry,
819 struct rxdone_entry_desc *rxdesc)
820 {
821 __le32 *rxwi = (__le32 *) entry->skb->data;
822 u32 word;
823
824 rt2x00_desc_read(rxwi, 0, &word);
825
826 rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
827 rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
828
829 rt2x00_desc_read(rxwi, 1, &word);
830
831 if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
832 rxdesc->flags |= RX_FLAG_SHORT_GI;
833
834 if (rt2x00_get_field32(word, RXWI_W1_BW))
835 rxdesc->flags |= RX_FLAG_40MHZ;
836
837 /*
838 * Detect RX rate, always use MCS as signal type.
839 */
840 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
841 rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
842 rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
843
844 /*
845 * Mask of 0x8 bit to remove the short preamble flag.
846 */
847 if (rxdesc->rate_mode == RATE_MODE_CCK)
848 rxdesc->signal &= ~0x8;
849
850 rt2x00_desc_read(rxwi, 2, &word);
851
852 /*
853 * Convert descriptor AGC value to RSSI value.
854 */
855 rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
856 /*
857 * Remove RXWI descriptor from start of the buffer.
858 */
859 skb_pull(entry->skb, entry->queue->winfo_size);
860 }
861 EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
862
863 void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi)
864 {
865 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
866 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
867 struct txdone_entry_desc txdesc;
868 u32 word;
869 u16 mcs, real_mcs;
870 int aggr, ampdu;
871
872 /*
873 * Obtain the status about this packet.
874 */
875 txdesc.flags = 0;
876 rt2x00_desc_read(txwi, 0, &word);
877
878 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
879 ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
880
881 real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
882 aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
883
884 /*
885 * If a frame was meant to be sent as a single non-aggregated MPDU
886 * but ended up in an aggregate the used tx rate doesn't correlate
887 * with the one specified in the TXWI as the whole aggregate is sent
888 * with the same rate.
889 *
890 * For example: two frames are sent to rt2x00, the first one sets
891 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
892 * and requests MCS15. If the hw aggregates both frames into one
893 * AMDPU the tx status for both frames will contain MCS7 although
894 * the frame was sent successfully.
895 *
896 * Hence, replace the requested rate with the real tx rate to not
897 * confuse the rate control algortihm by providing clearly wrong
898 * data.
899 */
900 if (unlikely(aggr == 1 && ampdu == 0 && real_mcs != mcs)) {
901 skbdesc->tx_rate_idx = real_mcs;
902 mcs = real_mcs;
903 }
904
905 if (aggr == 1 || ampdu == 1)
906 __set_bit(TXDONE_AMPDU, &txdesc.flags);
907
908 /*
909 * Ralink has a retry mechanism using a global fallback
910 * table. We setup this fallback table to try the immediate
911 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
912 * always contains the MCS used for the last transmission, be
913 * it successful or not.
914 */
915 if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
916 /*
917 * Transmission succeeded. The number of retries is
918 * mcs - real_mcs
919 */
920 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
921 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
922 } else {
923 /*
924 * Transmission failed. The number of retries is
925 * always 7 in this case (for a total number of 8
926 * frames sent).
927 */
928 __set_bit(TXDONE_FAILURE, &txdesc.flags);
929 txdesc.retry = rt2x00dev->long_retry;
930 }
931
932 /*
933 * the frame was retried at least once
934 * -> hw used fallback rates
935 */
936 if (txdesc.retry)
937 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
938
939 rt2x00lib_txdone(entry, &txdesc);
940 }
941 EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
942
943 void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
944 {
945 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
946 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
947 unsigned int beacon_base;
948 unsigned int padding_len;
949 u32 orig_reg, reg;
950 const int txwi_desc_size = entry->queue->winfo_size;
951
952 /*
953 * Disable beaconing while we are reloading the beacon data,
954 * otherwise we might be sending out invalid data.
955 */
956 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
957 orig_reg = reg;
958 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
959 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
960
961 /*
962 * Add space for the TXWI in front of the skb.
963 */
964 memset(skb_push(entry->skb, txwi_desc_size), 0, txwi_desc_size);
965
966 /*
967 * Register descriptor details in skb frame descriptor.
968 */
969 skbdesc->flags |= SKBDESC_DESC_IN_SKB;
970 skbdesc->desc = entry->skb->data;
971 skbdesc->desc_len = txwi_desc_size;
972
973 /*
974 * Add the TXWI for the beacon to the skb.
975 */
976 rt2800_write_tx_data(entry, txdesc);
977
978 /*
979 * Dump beacon to userspace through debugfs.
980 */
981 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
982
983 /*
984 * Write entire beacon with TXWI and padding to register.
985 */
986 padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
987 if (padding_len && skb_pad(entry->skb, padding_len)) {
988 rt2x00_err(rt2x00dev, "Failure padding beacon, aborting\n");
989 /* skb freed by skb_pad() on failure */
990 entry->skb = NULL;
991 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
992 return;
993 }
994
995 beacon_base = HW_BEACON_BASE(entry->entry_idx);
996 rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
997 entry->skb->len + padding_len);
998
999 /*
1000 * Enable beaconing again.
1001 */
1002 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
1003 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1004
1005 /*
1006 * Clean up beacon skb.
1007 */
1008 dev_kfree_skb_any(entry->skb);
1009 entry->skb = NULL;
1010 }
1011 EXPORT_SYMBOL_GPL(rt2800_write_beacon);
1012
1013 static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
1014 unsigned int index)
1015 {
1016 int i;
1017 const int txwi_desc_size = rt2x00dev->bcn->winfo_size;
1018 unsigned int beacon_base;
1019
1020 beacon_base = HW_BEACON_BASE(index);
1021
1022 /*
1023 * For the Beacon base registers we only need to clear
1024 * the whole TXWI which (when set to 0) will invalidate
1025 * the entire beacon.
1026 */
1027 for (i = 0; i < txwi_desc_size; i += sizeof(__le32))
1028 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
1029 }
1030
1031 void rt2800_clear_beacon(struct queue_entry *entry)
1032 {
1033 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1034 u32 reg;
1035
1036 /*
1037 * Disable beaconing while we are reloading the beacon data,
1038 * otherwise we might be sending out invalid data.
1039 */
1040 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1041 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1042 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1043
1044 /*
1045 * Clear beacon.
1046 */
1047 rt2800_clear_beacon_register(rt2x00dev, entry->entry_idx);
1048
1049 /*
1050 * Enabled beaconing again.
1051 */
1052 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
1053 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1054 }
1055 EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
1056
1057 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1058 const struct rt2x00debug rt2800_rt2x00debug = {
1059 .owner = THIS_MODULE,
1060 .csr = {
1061 .read = rt2800_register_read,
1062 .write = rt2800_register_write,
1063 .flags = RT2X00DEBUGFS_OFFSET,
1064 .word_base = CSR_REG_BASE,
1065 .word_size = sizeof(u32),
1066 .word_count = CSR_REG_SIZE / sizeof(u32),
1067 },
1068 .eeprom = {
1069 /* NOTE: The local EEPROM access functions can't
1070 * be used here, use the generic versions instead.
1071 */
1072 .read = rt2x00_eeprom_read,
1073 .write = rt2x00_eeprom_write,
1074 .word_base = EEPROM_BASE,
1075 .word_size = sizeof(u16),
1076 .word_count = EEPROM_SIZE / sizeof(u16),
1077 },
1078 .bbp = {
1079 .read = rt2800_bbp_read,
1080 .write = rt2800_bbp_write,
1081 .word_base = BBP_BASE,
1082 .word_size = sizeof(u8),
1083 .word_count = BBP_SIZE / sizeof(u8),
1084 },
1085 .rf = {
1086 .read = rt2x00_rf_read,
1087 .write = rt2800_rf_write,
1088 .word_base = RF_BASE,
1089 .word_size = sizeof(u32),
1090 .word_count = RF_SIZE / sizeof(u32),
1091 },
1092 .rfcsr = {
1093 .read = rt2800_rfcsr_read,
1094 .write = rt2800_rfcsr_write,
1095 .word_base = RFCSR_BASE,
1096 .word_size = sizeof(u8),
1097 .word_count = RFCSR_SIZE / sizeof(u8),
1098 },
1099 };
1100 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
1101 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1102
1103 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
1104 {
1105 u32 reg;
1106
1107 if (rt2x00_rt(rt2x00dev, RT3290)) {
1108 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
1109 return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0);
1110 } else {
1111 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
1112 return rt2x00_get_field32(reg, GPIO_CTRL_VAL2);
1113 }
1114 }
1115 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
1116
1117 #ifdef CONFIG_RT2X00_LIB_LEDS
1118 static void rt2800_brightness_set(struct led_classdev *led_cdev,
1119 enum led_brightness brightness)
1120 {
1121 struct rt2x00_led *led =
1122 container_of(led_cdev, struct rt2x00_led, led_dev);
1123 unsigned int enabled = brightness != LED_OFF;
1124 unsigned int bg_mode =
1125 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
1126 unsigned int polarity =
1127 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
1128 EEPROM_FREQ_LED_POLARITY);
1129 unsigned int ledmode =
1130 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
1131 EEPROM_FREQ_LED_MODE);
1132 u32 reg;
1133
1134 /* Check for SoC (SOC devices don't support MCU requests) */
1135 if (rt2x00_is_soc(led->rt2x00dev)) {
1136 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
1137
1138 /* Set LED Polarity */
1139 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, polarity);
1140
1141 /* Set LED Mode */
1142 if (led->type == LED_TYPE_RADIO) {
1143 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE,
1144 enabled ? 3 : 0);
1145 } else if (led->type == LED_TYPE_ASSOC) {
1146 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE,
1147 enabled ? 3 : 0);
1148 } else if (led->type == LED_TYPE_QUALITY) {
1149 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE,
1150 enabled ? 3 : 0);
1151 }
1152
1153 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
1154
1155 } else {
1156 if (led->type == LED_TYPE_RADIO) {
1157 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1158 enabled ? 0x20 : 0);
1159 } else if (led->type == LED_TYPE_ASSOC) {
1160 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1161 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
1162 } else if (led->type == LED_TYPE_QUALITY) {
1163 /*
1164 * The brightness is divided into 6 levels (0 - 5),
1165 * The specs tell us the following levels:
1166 * 0, 1 ,3, 7, 15, 31
1167 * to determine the level in a simple way we can simply
1168 * work with bitshifting:
1169 * (1 << level) - 1
1170 */
1171 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
1172 (1 << brightness / (LED_FULL / 6)) - 1,
1173 polarity);
1174 }
1175 }
1176 }
1177
1178 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
1179 struct rt2x00_led *led, enum led_type type)
1180 {
1181 led->rt2x00dev = rt2x00dev;
1182 led->type = type;
1183 led->led_dev.brightness_set = rt2800_brightness_set;
1184 led->flags = LED_INITIALIZED;
1185 }
1186 #endif /* CONFIG_RT2X00_LIB_LEDS */
1187
1188 /*
1189 * Configuration handlers.
1190 */
1191 static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev,
1192 const u8 *address,
1193 int wcid)
1194 {
1195 struct mac_wcid_entry wcid_entry;
1196 u32 offset;
1197
1198 offset = MAC_WCID_ENTRY(wcid);
1199
1200 memset(&wcid_entry, 0xff, sizeof(wcid_entry));
1201 if (address)
1202 memcpy(wcid_entry.mac, address, ETH_ALEN);
1203
1204 rt2800_register_multiwrite(rt2x00dev, offset,
1205 &wcid_entry, sizeof(wcid_entry));
1206 }
1207
1208 static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid)
1209 {
1210 u32 offset;
1211 offset = MAC_WCID_ATTR_ENTRY(wcid);
1212 rt2800_register_write(rt2x00dev, offset, 0);
1213 }
1214
1215 static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev,
1216 int wcid, u32 bssidx)
1217 {
1218 u32 offset = MAC_WCID_ATTR_ENTRY(wcid);
1219 u32 reg;
1220
1221 /*
1222 * The BSS Idx numbers is split in a main value of 3 bits,
1223 * and a extended field for adding one additional bit to the value.
1224 */
1225 rt2800_register_read(rt2x00dev, offset, &reg);
1226 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7));
1227 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
1228 (bssidx & 0x8) >> 3);
1229 rt2800_register_write(rt2x00dev, offset, reg);
1230 }
1231
1232 static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev,
1233 struct rt2x00lib_crypto *crypto,
1234 struct ieee80211_key_conf *key)
1235 {
1236 struct mac_iveiv_entry iveiv_entry;
1237 u32 offset;
1238 u32 reg;
1239
1240 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
1241
1242 if (crypto->cmd == SET_KEY) {
1243 rt2800_register_read(rt2x00dev, offset, &reg);
1244 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
1245 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
1246 /*
1247 * Both the cipher as the BSS Idx numbers are split in a main
1248 * value of 3 bits, and a extended field for adding one additional
1249 * bit to the value.
1250 */
1251 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
1252 (crypto->cipher & 0x7));
1253 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
1254 (crypto->cipher & 0x8) >> 3);
1255 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
1256 rt2800_register_write(rt2x00dev, offset, reg);
1257 } else {
1258 /* Delete the cipher without touching the bssidx */
1259 rt2800_register_read(rt2x00dev, offset, &reg);
1260 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB, 0);
1261 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER, 0);
1262 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0);
1263 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
1264 rt2800_register_write(rt2x00dev, offset, reg);
1265 }
1266
1267 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
1268
1269 memset(&iveiv_entry, 0, sizeof(iveiv_entry));
1270 if ((crypto->cipher == CIPHER_TKIP) ||
1271 (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
1272 (crypto->cipher == CIPHER_AES))
1273 iveiv_entry.iv[3] |= 0x20;
1274 iveiv_entry.iv[3] |= key->keyidx << 6;
1275 rt2800_register_multiwrite(rt2x00dev, offset,
1276 &iveiv_entry, sizeof(iveiv_entry));
1277 }
1278
1279 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1280 struct rt2x00lib_crypto *crypto,
1281 struct ieee80211_key_conf *key)
1282 {
1283 struct hw_key_entry key_entry;
1284 struct rt2x00_field32 field;
1285 u32 offset;
1286 u32 reg;
1287
1288 if (crypto->cmd == SET_KEY) {
1289 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1290
1291 memcpy(key_entry.key, crypto->key,
1292 sizeof(key_entry.key));
1293 memcpy(key_entry.tx_mic, crypto->tx_mic,
1294 sizeof(key_entry.tx_mic));
1295 memcpy(key_entry.rx_mic, crypto->rx_mic,
1296 sizeof(key_entry.rx_mic));
1297
1298 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1299 rt2800_register_multiwrite(rt2x00dev, offset,
1300 &key_entry, sizeof(key_entry));
1301 }
1302
1303 /*
1304 * The cipher types are stored over multiple registers
1305 * starting with SHARED_KEY_MODE_BASE each word will have
1306 * 32 bits and contains the cipher types for 2 bssidx each.
1307 * Using the correct defines correctly will cause overhead,
1308 * so just calculate the correct offset.
1309 */
1310 field.bit_offset = 4 * (key->hw_key_idx % 8);
1311 field.bit_mask = 0x7 << field.bit_offset;
1312
1313 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1314
1315 rt2800_register_read(rt2x00dev, offset, &reg);
1316 rt2x00_set_field32(&reg, field,
1317 (crypto->cmd == SET_KEY) * crypto->cipher);
1318 rt2800_register_write(rt2x00dev, offset, reg);
1319
1320 /*
1321 * Update WCID information
1322 */
1323 rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx);
1324 rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx,
1325 crypto->bssidx);
1326 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1327
1328 return 0;
1329 }
1330 EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1331
1332 static inline int rt2800_find_wcid(struct rt2x00_dev *rt2x00dev)
1333 {
1334 struct mac_wcid_entry wcid_entry;
1335 int idx;
1336 u32 offset;
1337
1338 /*
1339 * Search for the first free WCID entry and return the corresponding
1340 * index.
1341 *
1342 * Make sure the WCID starts _after_ the last possible shared key
1343 * entry (>32).
1344 *
1345 * Since parts of the pairwise key table might be shared with
1346 * the beacon frame buffers 6 & 7 we should only write into the
1347 * first 222 entries.
1348 */
1349 for (idx = 33; idx <= 222; idx++) {
1350 offset = MAC_WCID_ENTRY(idx);
1351 rt2800_register_multiread(rt2x00dev, offset, &wcid_entry,
1352 sizeof(wcid_entry));
1353 if (is_broadcast_ether_addr(wcid_entry.mac))
1354 return idx;
1355 }
1356
1357 /*
1358 * Use -1 to indicate that we don't have any more space in the WCID
1359 * table.
1360 */
1361 return -1;
1362 }
1363
1364 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1365 struct rt2x00lib_crypto *crypto,
1366 struct ieee80211_key_conf *key)
1367 {
1368 struct hw_key_entry key_entry;
1369 u32 offset;
1370
1371 if (crypto->cmd == SET_KEY) {
1372 /*
1373 * Allow key configuration only for STAs that are
1374 * known by the hw.
1375 */
1376 if (crypto->wcid < 0)
1377 return -ENOSPC;
1378 key->hw_key_idx = crypto->wcid;
1379
1380 memcpy(key_entry.key, crypto->key,
1381 sizeof(key_entry.key));
1382 memcpy(key_entry.tx_mic, crypto->tx_mic,
1383 sizeof(key_entry.tx_mic));
1384 memcpy(key_entry.rx_mic, crypto->rx_mic,
1385 sizeof(key_entry.rx_mic));
1386
1387 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1388 rt2800_register_multiwrite(rt2x00dev, offset,
1389 &key_entry, sizeof(key_entry));
1390 }
1391
1392 /*
1393 * Update WCID information
1394 */
1395 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1396
1397 return 0;
1398 }
1399 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1400
1401 int rt2800_sta_add(struct rt2x00_dev *rt2x00dev, struct ieee80211_vif *vif,
1402 struct ieee80211_sta *sta)
1403 {
1404 int wcid;
1405 struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
1406
1407 /*
1408 * Find next free WCID.
1409 */
1410 wcid = rt2800_find_wcid(rt2x00dev);
1411
1412 /*
1413 * Store selected wcid even if it is invalid so that we can
1414 * later decide if the STA is uploaded into the hw.
1415 */
1416 sta_priv->wcid = wcid;
1417
1418 /*
1419 * No space left in the device, however, we can still communicate
1420 * with the STA -> No error.
1421 */
1422 if (wcid < 0)
1423 return 0;
1424
1425 /*
1426 * Clean up WCID attributes and write STA address to the device.
1427 */
1428 rt2800_delete_wcid_attr(rt2x00dev, wcid);
1429 rt2800_config_wcid(rt2x00dev, sta->addr, wcid);
1430 rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid,
1431 rt2x00lib_get_bssidx(rt2x00dev, vif));
1432 return 0;
1433 }
1434 EXPORT_SYMBOL_GPL(rt2800_sta_add);
1435
1436 int rt2800_sta_remove(struct rt2x00_dev *rt2x00dev, int wcid)
1437 {
1438 /*
1439 * Remove WCID entry, no need to clean the attributes as they will
1440 * get renewed when the WCID is reused.
1441 */
1442 rt2800_config_wcid(rt2x00dev, NULL, wcid);
1443
1444 return 0;
1445 }
1446 EXPORT_SYMBOL_GPL(rt2800_sta_remove);
1447
1448 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1449 const unsigned int filter_flags)
1450 {
1451 u32 reg;
1452
1453 /*
1454 * Start configuration steps.
1455 * Note that the version error will always be dropped
1456 * and broadcast frames will always be accepted since
1457 * there is no filter for it at this time.
1458 */
1459 rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
1460 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1461 !(filter_flags & FIF_FCSFAIL));
1462 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1463 !(filter_flags & FIF_PLCPFAIL));
1464 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1465 !(filter_flags & FIF_PROMISC_IN_BSS));
1466 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1467 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1468 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1469 !(filter_flags & FIF_ALLMULTI));
1470 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1471 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1472 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1473 !(filter_flags & FIF_CONTROL));
1474 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1475 !(filter_flags & FIF_CONTROL));
1476 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1477 !(filter_flags & FIF_CONTROL));
1478 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1479 !(filter_flags & FIF_CONTROL));
1480 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1481 !(filter_flags & FIF_CONTROL));
1482 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1483 !(filter_flags & FIF_PSPOLL));
1484 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 0);
1485 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR,
1486 !(filter_flags & FIF_CONTROL));
1487 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1488 !(filter_flags & FIF_CONTROL));
1489 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1490 }
1491 EXPORT_SYMBOL_GPL(rt2800_config_filter);
1492
1493 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1494 struct rt2x00intf_conf *conf, const unsigned int flags)
1495 {
1496 u32 reg;
1497 bool update_bssid = false;
1498
1499 if (flags & CONFIG_UPDATE_TYPE) {
1500 /*
1501 * Enable synchronisation.
1502 */
1503 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1504 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
1505 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1506
1507 if (conf->sync == TSF_SYNC_AP_NONE) {
1508 /*
1509 * Tune beacon queue transmit parameters for AP mode
1510 */
1511 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1512 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 0);
1513 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 1);
1514 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1515 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 0);
1516 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1517 } else {
1518 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1519 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 4);
1520 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 2);
1521 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1522 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 16);
1523 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1524 }
1525 }
1526
1527 if (flags & CONFIG_UPDATE_MAC) {
1528 if (flags & CONFIG_UPDATE_TYPE &&
1529 conf->sync == TSF_SYNC_AP_NONE) {
1530 /*
1531 * The BSSID register has to be set to our own mac
1532 * address in AP mode.
1533 */
1534 memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1535 update_bssid = true;
1536 }
1537
1538 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1539 reg = le32_to_cpu(conf->mac[1]);
1540 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1541 conf->mac[1] = cpu_to_le32(reg);
1542 }
1543
1544 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1545 conf->mac, sizeof(conf->mac));
1546 }
1547
1548 if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
1549 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1550 reg = le32_to_cpu(conf->bssid[1]);
1551 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1552 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
1553 conf->bssid[1] = cpu_to_le32(reg);
1554 }
1555
1556 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1557 conf->bssid, sizeof(conf->bssid));
1558 }
1559 }
1560 EXPORT_SYMBOL_GPL(rt2800_config_intf);
1561
1562 static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1563 struct rt2x00lib_erp *erp)
1564 {
1565 bool any_sta_nongf = !!(erp->ht_opmode &
1566 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1567 u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1568 u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1569 u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1570 u32 reg;
1571
1572 /* default protection rate for HT20: OFDM 24M */
1573 mm20_rate = gf20_rate = 0x4004;
1574
1575 /* default protection rate for HT40: duplicate OFDM 24M */
1576 mm40_rate = gf40_rate = 0x4084;
1577
1578 switch (protection) {
1579 case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1580 /*
1581 * All STAs in this BSS are HT20/40 but there might be
1582 * STAs not supporting greenfield mode.
1583 * => Disable protection for HT transmissions.
1584 */
1585 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1586
1587 break;
1588 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1589 /*
1590 * All STAs in this BSS are HT20 or HT20/40 but there
1591 * might be STAs not supporting greenfield mode.
1592 * => Protect all HT40 transmissions.
1593 */
1594 mm20_mode = gf20_mode = 0;
1595 mm40_mode = gf40_mode = 2;
1596
1597 break;
1598 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1599 /*
1600 * Nonmember protection:
1601 * According to 802.11n we _should_ protect all
1602 * HT transmissions (but we don't have to).
1603 *
1604 * But if cts_protection is enabled we _shall_ protect
1605 * all HT transmissions using a CCK rate.
1606 *
1607 * And if any station is non GF we _shall_ protect
1608 * GF transmissions.
1609 *
1610 * We decide to protect everything
1611 * -> fall through to mixed mode.
1612 */
1613 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1614 /*
1615 * Legacy STAs are present
1616 * => Protect all HT transmissions.
1617 */
1618 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2;
1619
1620 /*
1621 * If erp protection is needed we have to protect HT
1622 * transmissions with CCK 11M long preamble.
1623 */
1624 if (erp->cts_protection) {
1625 /* don't duplicate RTS/CTS in CCK mode */
1626 mm20_rate = mm40_rate = 0x0003;
1627 gf20_rate = gf40_rate = 0x0003;
1628 }
1629 break;
1630 }
1631
1632 /* check for STAs not supporting greenfield mode */
1633 if (any_sta_nongf)
1634 gf20_mode = gf40_mode = 2;
1635
1636 /* Update HT protection config */
1637 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1638 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1639 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1640 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1641
1642 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1643 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1644 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1645 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1646
1647 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1648 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1649 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1650 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1651
1652 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1653 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1654 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1655 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1656 }
1657
1658 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1659 u32 changed)
1660 {
1661 u32 reg;
1662
1663 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1664 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1665 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
1666 !!erp->short_preamble);
1667 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1668 !!erp->short_preamble);
1669 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1670 }
1671
1672 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1673 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1674 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1675 erp->cts_protection ? 2 : 0);
1676 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1677 }
1678
1679 if (changed & BSS_CHANGED_BASIC_RATES) {
1680 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1681 erp->basic_rates);
1682 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1683 }
1684
1685 if (changed & BSS_CHANGED_ERP_SLOT) {
1686 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1687 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
1688 erp->slot_time);
1689 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1690
1691 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1692 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1693 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1694 }
1695
1696 if (changed & BSS_CHANGED_BEACON_INT) {
1697 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1698 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1699 erp->beacon_int * 16);
1700 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1701 }
1702
1703 if (changed & BSS_CHANGED_HT)
1704 rt2800_config_ht_opmode(rt2x00dev, erp);
1705 }
1706 EXPORT_SYMBOL_GPL(rt2800_config_erp);
1707
1708 static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev)
1709 {
1710 u32 reg;
1711 u16 eeprom;
1712 u8 led_ctrl, led_g_mode, led_r_mode;
1713
1714 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
1715 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
1716 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 1);
1717 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 1);
1718 } else {
1719 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 0);
1720 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 0);
1721 }
1722 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
1723
1724 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1725 led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0;
1726 led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3;
1727 if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) ||
1728 led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) {
1729 rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1730 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE);
1731 if (led_ctrl == 0 || led_ctrl > 0x40) {
1732 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, led_g_mode);
1733 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, led_r_mode);
1734 rt2800_register_write(rt2x00dev, LED_CFG, reg);
1735 } else {
1736 rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff,
1737 (led_g_mode << 2) | led_r_mode, 1);
1738 }
1739 }
1740 }
1741
1742 static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
1743 enum antenna ant)
1744 {
1745 u32 reg;
1746 u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
1747 u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
1748
1749 if (rt2x00_is_pci(rt2x00dev)) {
1750 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
1751 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
1752 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
1753 } else if (rt2x00_is_usb(rt2x00dev))
1754 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
1755 eesk_pin, 0);
1756
1757 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
1758 rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
1759 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, gpio_bit3);
1760 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
1761 }
1762
1763 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1764 {
1765 u8 r1;
1766 u8 r3;
1767 u16 eeprom;
1768
1769 rt2800_bbp_read(rt2x00dev, 1, &r1);
1770 rt2800_bbp_read(rt2x00dev, 3, &r3);
1771
1772 if (rt2x00_rt(rt2x00dev, RT3572) &&
1773 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1774 rt2800_config_3572bt_ant(rt2x00dev);
1775
1776 /*
1777 * Configure the TX antenna.
1778 */
1779 switch (ant->tx_chain_num) {
1780 case 1:
1781 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1782 break;
1783 case 2:
1784 if (rt2x00_rt(rt2x00dev, RT3572) &&
1785 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1786 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1);
1787 else
1788 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1789 break;
1790 case 3:
1791 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1792 break;
1793 }
1794
1795 /*
1796 * Configure the RX antenna.
1797 */
1798 switch (ant->rx_chain_num) {
1799 case 1:
1800 if (rt2x00_rt(rt2x00dev, RT3070) ||
1801 rt2x00_rt(rt2x00dev, RT3090) ||
1802 rt2x00_rt(rt2x00dev, RT3352) ||
1803 rt2x00_rt(rt2x00dev, RT3390)) {
1804 rt2800_eeprom_read(rt2x00dev,
1805 EEPROM_NIC_CONF1, &eeprom);
1806 if (rt2x00_get_field16(eeprom,
1807 EEPROM_NIC_CONF1_ANT_DIVERSITY))
1808 rt2800_set_ant_diversity(rt2x00dev,
1809 rt2x00dev->default_ant.rx);
1810 }
1811 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1812 break;
1813 case 2:
1814 if (rt2x00_rt(rt2x00dev, RT3572) &&
1815 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1816 rt2x00_set_field8(&r3, BBP3_RX_ADC, 1);
1817 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA,
1818 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
1819 rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B);
1820 } else {
1821 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1822 }
1823 break;
1824 case 3:
1825 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1826 break;
1827 }
1828
1829 rt2800_bbp_write(rt2x00dev, 3, r3);
1830 rt2800_bbp_write(rt2x00dev, 1, r1);
1831
1832 if (rt2x00_rt(rt2x00dev, RT3593)) {
1833 if (ant->rx_chain_num == 1)
1834 rt2800_bbp_write(rt2x00dev, 86, 0x00);
1835 else
1836 rt2800_bbp_write(rt2x00dev, 86, 0x46);
1837 }
1838 }
1839 EXPORT_SYMBOL_GPL(rt2800_config_ant);
1840
1841 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1842 struct rt2x00lib_conf *libconf)
1843 {
1844 u16 eeprom;
1845 short lna_gain;
1846
1847 if (libconf->rf.channel <= 14) {
1848 rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1849 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1850 } else if (libconf->rf.channel <= 64) {
1851 rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1852 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1853 } else if (libconf->rf.channel <= 128) {
1854 if (rt2x00_rt(rt2x00dev, RT3593)) {
1855 rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &eeprom);
1856 lna_gain = rt2x00_get_field16(eeprom,
1857 EEPROM_EXT_LNA2_A1);
1858 } else {
1859 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1860 lna_gain = rt2x00_get_field16(eeprom,
1861 EEPROM_RSSI_BG2_LNA_A1);
1862 }
1863 } else {
1864 if (rt2x00_rt(rt2x00dev, RT3593)) {
1865 rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &eeprom);
1866 lna_gain = rt2x00_get_field16(eeprom,
1867 EEPROM_EXT_LNA2_A2);
1868 } else {
1869 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1870 lna_gain = rt2x00_get_field16(eeprom,
1871 EEPROM_RSSI_A2_LNA_A2);
1872 }
1873 }
1874
1875 rt2x00dev->lna_gain = lna_gain;
1876 }
1877
1878 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1879 struct ieee80211_conf *conf,
1880 struct rf_channel *rf,
1881 struct channel_info *info)
1882 {
1883 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1884
1885 if (rt2x00dev->default_ant.tx_chain_num == 1)
1886 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1887
1888 if (rt2x00dev->default_ant.rx_chain_num == 1) {
1889 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1890 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1891 } else if (rt2x00dev->default_ant.rx_chain_num == 2)
1892 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1893
1894 if (rf->channel > 14) {
1895 /*
1896 * When TX power is below 0, we should increase it by 7 to
1897 * make it a positive value (Minimum value is -7).
1898 * However this means that values between 0 and 7 have
1899 * double meaning, and we should set a 7DBm boost flag.
1900 */
1901 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
1902 (info->default_power1 >= 0));
1903
1904 if (info->default_power1 < 0)
1905 info->default_power1 += 7;
1906
1907 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
1908
1909 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
1910 (info->default_power2 >= 0));
1911
1912 if (info->default_power2 < 0)
1913 info->default_power2 += 7;
1914
1915 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
1916 } else {
1917 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
1918 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
1919 }
1920
1921 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1922
1923 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1924 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1925 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1926 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1927
1928 udelay(200);
1929
1930 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1931 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1932 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1933 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1934
1935 udelay(200);
1936
1937 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1938 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1939 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1940 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1941 }
1942
1943 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1944 struct ieee80211_conf *conf,
1945 struct rf_channel *rf,
1946 struct channel_info *info)
1947 {
1948 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1949 u8 rfcsr, calib_tx, calib_rx;
1950
1951 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1952
1953 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
1954 rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3);
1955 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
1956
1957 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1958 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
1959 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1960
1961 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1962 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
1963 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1964
1965 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1966 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
1967 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1968
1969 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1970 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
1971 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
1972 rt2x00dev->default_ant.rx_chain_num <= 1);
1973 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD,
1974 rt2x00dev->default_ant.rx_chain_num <= 2);
1975 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
1976 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
1977 rt2x00dev->default_ant.tx_chain_num <= 1);
1978 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD,
1979 rt2x00dev->default_ant.tx_chain_num <= 2);
1980 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1981
1982 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1983 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1984 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1985 msleep(1);
1986 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1987 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1988
1989 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1990 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1991 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1992
1993 if (rt2x00_rt(rt2x00dev, RT3390)) {
1994 calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f;
1995 calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f;
1996 } else {
1997 if (conf_is_ht40(conf)) {
1998 calib_tx = drv_data->calibration_bw40;
1999 calib_rx = drv_data->calibration_bw40;
2000 } else {
2001 calib_tx = drv_data->calibration_bw20;
2002 calib_rx = drv_data->calibration_bw20;
2003 }
2004 }
2005
2006 rt2800_rfcsr_read(rt2x00dev, 24, &rfcsr);
2007 rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx);
2008 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr);
2009
2010 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
2011 rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx);
2012 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
2013
2014 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
2015 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
2016 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2017
2018 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2019 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2020 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2021 msleep(1);
2022 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
2023 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2024 }
2025
2026 static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
2027 struct ieee80211_conf *conf,
2028 struct rf_channel *rf,
2029 struct channel_info *info)
2030 {
2031 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2032 u8 rfcsr;
2033 u32 reg;
2034
2035 if (rf->channel <= 14) {
2036 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
2037 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
2038 } else {
2039 rt2800_bbp_write(rt2x00dev, 25, 0x09);
2040 rt2800_bbp_write(rt2x00dev, 26, 0xff);
2041 }
2042
2043 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
2044 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
2045
2046 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
2047 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
2048 if (rf->channel <= 14)
2049 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2);
2050 else
2051 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1);
2052 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2053
2054 rt2800_rfcsr_read(rt2x00dev, 5, &rfcsr);
2055 if (rf->channel <= 14)
2056 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1);
2057 else
2058 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2);
2059 rt2800_rfcsr_write(rt2x00dev, 5, rfcsr);
2060
2061 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
2062 if (rf->channel <= 14) {
2063 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3);
2064 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
2065 info->default_power1);
2066 } else {
2067 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7);
2068 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
2069 (info->default_power1 & 0x3) |
2070 ((info->default_power1 & 0xC) << 1));
2071 }
2072 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2073
2074 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
2075 if (rf->channel <= 14) {
2076 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3);
2077 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
2078 info->default_power2);
2079 } else {
2080 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7);
2081 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
2082 (info->default_power2 & 0x3) |
2083 ((info->default_power2 & 0xC) << 1));
2084 }
2085 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
2086
2087 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2088 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2089 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2090 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2091 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2092 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2093 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2094 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
2095 if (rf->channel <= 14) {
2096 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2097 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2098 }
2099 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2100 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2101 } else {
2102 switch (rt2x00dev->default_ant.tx_chain_num) {
2103 case 1:
2104 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2105 case 2:
2106 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2107 break;
2108 }
2109
2110 switch (rt2x00dev->default_ant.rx_chain_num) {
2111 case 1:
2112 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2113 case 2:
2114 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2115 break;
2116 }
2117 }
2118 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2119
2120 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
2121 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
2122 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2123
2124 if (conf_is_ht40(conf)) {
2125 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40);
2126 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40);
2127 } else {
2128 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20);
2129 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20);
2130 }
2131
2132 if (rf->channel <= 14) {
2133 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
2134 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
2135 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
2136 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
2137 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
2138 rfcsr = 0x4c;
2139 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
2140 drv_data->txmixer_gain_24g);
2141 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
2142 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
2143 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
2144 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
2145 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
2146 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
2147 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
2148 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
2149 } else {
2150 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
2151 rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1);
2152 rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0);
2153 rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1);
2154 rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0);
2155 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2156 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
2157 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
2158 rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
2159 rt2800_rfcsr_write(rt2x00dev, 15, 0x43);
2160 rfcsr = 0x7a;
2161 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
2162 drv_data->txmixer_gain_5g);
2163 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
2164 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
2165 if (rf->channel <= 64) {
2166 rt2800_rfcsr_write(rt2x00dev, 19, 0xb7);
2167 rt2800_rfcsr_write(rt2x00dev, 20, 0xf6);
2168 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
2169 } else if (rf->channel <= 128) {
2170 rt2800_rfcsr_write(rt2x00dev, 19, 0x74);
2171 rt2800_rfcsr_write(rt2x00dev, 20, 0xf4);
2172 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2173 } else {
2174 rt2800_rfcsr_write(rt2x00dev, 19, 0x72);
2175 rt2800_rfcsr_write(rt2x00dev, 20, 0xf3);
2176 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2177 }
2178 rt2800_rfcsr_write(rt2x00dev, 26, 0x87);
2179 rt2800_rfcsr_write(rt2x00dev, 27, 0x01);
2180 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f);
2181 }
2182
2183 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
2184 rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
2185 if (rf->channel <= 14)
2186 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
2187 else
2188 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 0);
2189 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
2190
2191 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
2192 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
2193 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2194 }
2195
2196 static void rt2800_config_channel_rf3053(struct rt2x00_dev *rt2x00dev,
2197 struct ieee80211_conf *conf,
2198 struct rf_channel *rf,
2199 struct channel_info *info)
2200 {
2201 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2202 u8 txrx_agc_fc;
2203 u8 txrx_h20m;
2204 u8 rfcsr;
2205 u8 bbp;
2206 const bool txbf_enabled = false; /* TODO */
2207
2208 /* TODO: use TX{0,1,2}FinePowerControl values from EEPROM */
2209 rt2800_bbp_read(rt2x00dev, 109, &bbp);
2210 rt2x00_set_field8(&bbp, BBP109_TX0_POWER, 0);
2211 rt2x00_set_field8(&bbp, BBP109_TX1_POWER, 0);
2212 rt2800_bbp_write(rt2x00dev, 109, bbp);
2213
2214 rt2800_bbp_read(rt2x00dev, 110, &bbp);
2215 rt2x00_set_field8(&bbp, BBP110_TX2_POWER, 0);
2216 rt2800_bbp_write(rt2x00dev, 110, bbp);
2217
2218 if (rf->channel <= 14) {
2219 /* Restore BBP 25 & 26 for 2.4 GHz */
2220 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
2221 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
2222 } else {
2223 /* Hard code BBP 25 & 26 for 5GHz */
2224
2225 /* Enable IQ Phase correction */
2226 rt2800_bbp_write(rt2x00dev, 25, 0x09);
2227 /* Setup IQ Phase correction value */
2228 rt2800_bbp_write(rt2x00dev, 26, 0xff);
2229 }
2230
2231 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2232 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3 & 0xf);
2233
2234 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2235 rt2x00_set_field8(&rfcsr, RFCSR11_R, (rf->rf2 & 0x3));
2236 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2237
2238 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2239 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_IDOH, 1);
2240 if (rf->channel <= 14)
2241 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 1);
2242 else
2243 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 2);
2244 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2245
2246 rt2800_rfcsr_read(rt2x00dev, 53, &rfcsr);
2247 if (rf->channel <= 14) {
2248 rfcsr = 0;
2249 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER,
2250 info->default_power1 & 0x1f);
2251 } else {
2252 if (rt2x00_is_usb(rt2x00dev))
2253 rfcsr = 0x40;
2254
2255 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER,
2256 ((info->default_power1 & 0x18) << 1) |
2257 (info->default_power1 & 7));
2258 }
2259 rt2800_rfcsr_write(rt2x00dev, 53, rfcsr);
2260
2261 rt2800_rfcsr_read(rt2x00dev, 55, &rfcsr);
2262 if (rf->channel <= 14) {
2263 rfcsr = 0;
2264 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER,
2265 info->default_power2 & 0x1f);
2266 } else {
2267 if (rt2x00_is_usb(rt2x00dev))
2268 rfcsr = 0x40;
2269
2270 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER,
2271 ((info->default_power2 & 0x18) << 1) |
2272 (info->default_power2 & 7));
2273 }
2274 rt2800_rfcsr_write(rt2x00dev, 55, rfcsr);
2275
2276 rt2800_rfcsr_read(rt2x00dev, 54, &rfcsr);
2277 if (rf->channel <= 14) {
2278 rfcsr = 0;
2279 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER,
2280 info->default_power3 & 0x1f);
2281 } else {
2282 if (rt2x00_is_usb(rt2x00dev))
2283 rfcsr = 0x40;
2284
2285 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER,
2286 ((info->default_power3 & 0x18) << 1) |
2287 (info->default_power3 & 7));
2288 }
2289 rt2800_rfcsr_write(rt2x00dev, 54, rfcsr);
2290
2291 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2292 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2293 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2294 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2295 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2296 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2297 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2298 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2299 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2300
2301 switch (rt2x00dev->default_ant.tx_chain_num) {
2302 case 3:
2303 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2304 /* fallthrough */
2305 case 2:
2306 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2307 /* fallthrough */
2308 case 1:
2309 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2310 break;
2311 }
2312
2313 switch (rt2x00dev->default_ant.rx_chain_num) {
2314 case 3:
2315 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2316 /* fallthrough */
2317 case 2:
2318 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2319 /* fallthrough */
2320 case 1:
2321 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2322 break;
2323 }
2324 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2325
2326 /* TODO: frequency calibration? */
2327
2328 if (conf_is_ht40(conf)) {
2329 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw40,
2330 RFCSR24_TX_AGC_FC);
2331 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw40,
2332 RFCSR24_TX_H20M);
2333 } else {
2334 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw20,
2335 RFCSR24_TX_AGC_FC);
2336 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw20,
2337 RFCSR24_TX_H20M);
2338 }
2339
2340 /* NOTE: the reference driver does not writes the new value
2341 * back to RFCSR 32
2342 */
2343 rt2800_rfcsr_read(rt2x00dev, 32, &rfcsr);
2344 rt2x00_set_field8(&rfcsr, RFCSR32_TX_AGC_FC, txrx_agc_fc);
2345
2346 if (rf->channel <= 14)
2347 rfcsr = 0xa0;
2348 else
2349 rfcsr = 0x80;
2350 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
2351
2352 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2353 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, txrx_h20m);
2354 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, txrx_h20m);
2355 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2356
2357 /* Band selection */
2358 rt2800_rfcsr_read(rt2x00dev, 36, &rfcsr);
2359 if (rf->channel <= 14)
2360 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 1);
2361 else
2362 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 0);
2363 rt2800_rfcsr_write(rt2x00dev, 36, rfcsr);
2364
2365 rt2800_rfcsr_read(rt2x00dev, 34, &rfcsr);
2366 if (rf->channel <= 14)
2367 rfcsr = 0x3c;
2368 else
2369 rfcsr = 0x20;
2370 rt2800_rfcsr_write(rt2x00dev, 34, rfcsr);
2371
2372 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
2373 if (rf->channel <= 14)
2374 rfcsr = 0x1a;
2375 else
2376 rfcsr = 0x12;
2377 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2378
2379 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
2380 if (rf->channel >= 1 && rf->channel <= 14)
2381 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1);
2382 else if (rf->channel >= 36 && rf->channel <= 64)
2383 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2);
2384 else if (rf->channel >= 100 && rf->channel <= 128)
2385 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2);
2386 else
2387 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1);
2388 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2389
2390 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2391 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
2392 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2393
2394 rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
2395
2396 if (rf->channel <= 14) {
2397 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
2398 rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
2399 } else {
2400 rt2800_rfcsr_write(rt2x00dev, 10, 0xd8);
2401 rt2800_rfcsr_write(rt2x00dev, 13, 0x23);
2402 }
2403
2404 rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr);
2405 rt2x00_set_field8(&rfcsr, RFCSR51_BITS01, 1);
2406 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
2407
2408 rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr);
2409 if (rf->channel <= 14) {
2410 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 5);
2411 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 3);
2412 } else {
2413 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 4);
2414 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 2);
2415 }
2416 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
2417
2418 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2419 if (rf->channel <= 14)
2420 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 3);
2421 else
2422 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 2);
2423
2424 if (txbf_enabled)
2425 rt2x00_set_field8(&rfcsr, RFCSR49_TX_DIV, 1);
2426
2427 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2428
2429 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
2430 rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO1_EN, 0);
2431 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2432
2433 rt2800_rfcsr_read(rt2x00dev, 57, &rfcsr);
2434 if (rf->channel <= 14)
2435 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x1b);
2436 else
2437 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x0f);
2438 rt2800_rfcsr_write(rt2x00dev, 57, rfcsr);
2439
2440 if (rf->channel <= 14) {
2441 rt2800_rfcsr_write(rt2x00dev, 44, 0x93);
2442 rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
2443 } else {
2444 rt2800_rfcsr_write(rt2x00dev, 44, 0x9b);
2445 rt2800_rfcsr_write(rt2x00dev, 52, 0x05);
2446 }
2447
2448 /* Initiate VCO calibration */
2449 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2450 if (rf->channel <= 14) {
2451 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2452 } else {
2453 rt2x00_set_field8(&rfcsr, RFCSR3_BIT1, 1);
2454 rt2x00_set_field8(&rfcsr, RFCSR3_BIT2, 1);
2455 rt2x00_set_field8(&rfcsr, RFCSR3_BIT3, 1);
2456 rt2x00_set_field8(&rfcsr, RFCSR3_BIT4, 1);
2457 rt2x00_set_field8(&rfcsr, RFCSR3_BIT5, 1);
2458 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2459 }
2460 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2461
2462 if (rf->channel >= 1 && rf->channel <= 14) {
2463 rfcsr = 0x23;
2464 if (txbf_enabled)
2465 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2466 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2467
2468 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
2469 } else if (rf->channel >= 36 && rf->channel <= 64) {
2470 rfcsr = 0x36;
2471 if (txbf_enabled)
2472 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2473 rt2800_rfcsr_write(rt2x00dev, 39, 0x36);
2474
2475 rt2800_rfcsr_write(rt2x00dev, 45, 0xeb);
2476 } else if (rf->channel >= 100 && rf->channel <= 128) {
2477 rfcsr = 0x32;
2478 if (txbf_enabled)
2479 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2480 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2481
2482 rt2800_rfcsr_write(rt2x00dev, 45, 0xb3);
2483 } else {
2484 rfcsr = 0x30;
2485 if (txbf_enabled)
2486 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2487 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2488
2489 rt2800_rfcsr_write(rt2x00dev, 45, 0x9b);
2490 }
2491 }
2492
2493 #define POWER_BOUND 0x27
2494 #define POWER_BOUND_5G 0x2b
2495 #define FREQ_OFFSET_BOUND 0x5f
2496
2497 static void rt2800_adjust_freq_offset(struct rt2x00_dev *rt2x00dev)
2498 {
2499 u8 freq_offset;
2500 u8 rfcsr;
2501
2502 freq_offset = rt2x00_get_field8(rt2x00dev->freq_offset, RFCSR17_CODE);
2503 freq_offset = min_t(u8, freq_offset, FREQ_OFFSET_BOUND);
2504
2505 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
2506 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, freq_offset);
2507 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2508 }
2509
2510 static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev,
2511 struct ieee80211_conf *conf,
2512 struct rf_channel *rf,
2513 struct channel_info *info)
2514 {
2515 u8 rfcsr;
2516
2517 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2518 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2519 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2520 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2521 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2522
2523 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2524 if (info->default_power1 > POWER_BOUND)
2525 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
2526 else
2527 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2528 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2529
2530 rt2800_adjust_freq_offset(rt2x00dev);
2531
2532 if (rf->channel <= 14) {
2533 if (rf->channel == 6)
2534 rt2800_bbp_write(rt2x00dev, 68, 0x0c);
2535 else
2536 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
2537
2538 if (rf->channel >= 1 && rf->channel <= 6)
2539 rt2800_bbp_write(rt2x00dev, 59, 0x0f);
2540 else if (rf->channel >= 7 && rf->channel <= 11)
2541 rt2800_bbp_write(rt2x00dev, 59, 0x0e);
2542 else if (rf->channel >= 12 && rf->channel <= 14)
2543 rt2800_bbp_write(rt2x00dev, 59, 0x0d);
2544 }
2545 }
2546
2547 static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev,
2548 struct ieee80211_conf *conf,
2549 struct rf_channel *rf,
2550 struct channel_info *info)
2551 {
2552 u8 rfcsr;
2553
2554 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2555 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2556
2557 rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
2558 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
2559 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
2560
2561 if (info->default_power1 > POWER_BOUND)
2562 rt2800_rfcsr_write(rt2x00dev, 47, POWER_BOUND);
2563 else
2564 rt2800_rfcsr_write(rt2x00dev, 47, info->default_power1);
2565
2566 if (info->default_power2 > POWER_BOUND)
2567 rt2800_rfcsr_write(rt2x00dev, 48, POWER_BOUND);
2568 else
2569 rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2);
2570
2571 rt2800_adjust_freq_offset(rt2x00dev);
2572
2573 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2574 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2575 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2576
2577 if ( rt2x00dev->default_ant.tx_chain_num == 2 )
2578 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2579 else
2580 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2581
2582 if ( rt2x00dev->default_ant.rx_chain_num == 2 )
2583 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2584 else
2585 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2586
2587 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2588 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2589
2590 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2591
2592 rt2800_rfcsr_write(rt2x00dev, 31, 80);
2593 }
2594
2595 static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
2596 struct ieee80211_conf *conf,
2597 struct rf_channel *rf,
2598 struct channel_info *info)
2599 {
2600 u8 rfcsr;
2601
2602 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2603 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2604 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2605 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2606 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2607
2608 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2609 if (info->default_power1 > POWER_BOUND)
2610 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
2611 else
2612 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2613 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2614
2615 if (rt2x00_rt(rt2x00dev, RT5392)) {
2616 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
2617 if (info->default_power1 > POWER_BOUND)
2618 rt2x00_set_field8(&rfcsr, RFCSR50_TX, POWER_BOUND);
2619 else
2620 rt2x00_set_field8(&rfcsr, RFCSR50_TX,
2621 info->default_power2);
2622 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2623 }
2624
2625 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2626 if (rt2x00_rt(rt2x00dev, RT5392)) {
2627 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2628 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2629 }
2630 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2631 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2632 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2633 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2634 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2635
2636 rt2800_adjust_freq_offset(rt2x00dev);
2637
2638 if (rf->channel <= 14) {
2639 int idx = rf->channel-1;
2640
2641 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
2642 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2643 /* r55/r59 value array of channel 1~14 */
2644 static const char r55_bt_rev[] = {0x83, 0x83,
2645 0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
2646 0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
2647 static const char r59_bt_rev[] = {0x0e, 0x0e,
2648 0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
2649 0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
2650
2651 rt2800_rfcsr_write(rt2x00dev, 55,
2652 r55_bt_rev[idx]);
2653 rt2800_rfcsr_write(rt2x00dev, 59,
2654 r59_bt_rev[idx]);
2655 } else {
2656 static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
2657 0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
2658 0x88, 0x88, 0x86, 0x85, 0x84};
2659
2660 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
2661 }
2662 } else {
2663 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2664 static const char r55_nonbt_rev[] = {0x23, 0x23,
2665 0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
2666 0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
2667 static const char r59_nonbt_rev[] = {0x07, 0x07,
2668 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
2669 0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
2670
2671 rt2800_rfcsr_write(rt2x00dev, 55,
2672 r55_nonbt_rev[idx]);
2673 rt2800_rfcsr_write(rt2x00dev, 59,
2674 r59_nonbt_rev[idx]);
2675 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
2676 rt2x00_rt(rt2x00dev, RT5392)) {
2677 static const char r59_non_bt[] = {0x8f, 0x8f,
2678 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
2679 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
2680
2681 rt2800_rfcsr_write(rt2x00dev, 59,
2682 r59_non_bt[idx]);
2683 }
2684 }
2685 }
2686 }
2687
2688 static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev,
2689 struct ieee80211_conf *conf,
2690 struct rf_channel *rf,
2691 struct channel_info *info)
2692 {
2693 u8 rfcsr, ep_reg;
2694 u32 reg;
2695 int power_bound;
2696
2697 /* TODO */
2698 const bool is_11b = false;
2699 const bool is_type_ep = false;
2700
2701 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
2702 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL,
2703 (rf->channel > 14 || conf_is_ht40(conf)) ? 5 : 0);
2704 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
2705
2706 /* Order of values on rf_channel entry: N, K, mod, R */
2707 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1 & 0xff);
2708
2709 rt2800_rfcsr_read(rt2x00dev, 9, &rfcsr);
2710 rt2x00_set_field8(&rfcsr, RFCSR9_K, rf->rf2 & 0xf);
2711 rt2x00_set_field8(&rfcsr, RFCSR9_N, (rf->rf1 & 0x100) >> 8);
2712 rt2x00_set_field8(&rfcsr, RFCSR9_MOD, ((rf->rf3 - 8) & 0x4) >> 2);
2713 rt2800_rfcsr_write(rt2x00dev, 9, rfcsr);
2714
2715 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2716 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf4 - 1);
2717 rt2x00_set_field8(&rfcsr, RFCSR11_MOD, (rf->rf3 - 8) & 0x3);
2718 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2719
2720 if (rf->channel <= 14) {
2721 rt2800_rfcsr_write(rt2x00dev, 10, 0x90);
2722 /* FIXME: RF11 owerwrite ? */
2723 rt2800_rfcsr_write(rt2x00dev, 11, 0x4A);
2724 rt2800_rfcsr_write(rt2x00dev, 12, 0x52);
2725 rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
2726 rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
2727 rt2800_rfcsr_write(rt2x00dev, 24, 0x4A);
2728 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
2729 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
2730 rt2800_rfcsr_write(rt2x00dev, 36, 0x80);
2731 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
2732 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
2733 rt2800_rfcsr_write(rt2x00dev, 39, 0x1B);
2734 rt2800_rfcsr_write(rt2x00dev, 40, 0x0D);
2735 rt2800_rfcsr_write(rt2x00dev, 41, 0x9B);
2736 rt2800_rfcsr_write(rt2x00dev, 42, 0xD5);
2737 rt2800_rfcsr_write(rt2x00dev, 43, 0x72);
2738 rt2800_rfcsr_write(rt2x00dev, 44, 0x0E);
2739 rt2800_rfcsr_write(rt2x00dev, 45, 0xA2);
2740 rt2800_rfcsr_write(rt2x00dev, 46, 0x6B);
2741 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
2742 rt2800_rfcsr_write(rt2x00dev, 51, 0x3E);
2743 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
2744 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
2745 rt2800_rfcsr_write(rt2x00dev, 56, 0xA1);
2746 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
2747 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
2748 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
2749 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
2750 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
2751
2752 /* TODO RF27 <- tssi */
2753
2754 rfcsr = rf->channel <= 10 ? 0x07 : 0x06;
2755 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2756 rt2800_rfcsr_write(rt2x00dev, 59, rfcsr);
2757
2758 if (is_11b) {
2759 /* CCK */
2760 rt2800_rfcsr_write(rt2x00dev, 31, 0xF8);
2761 rt2800_rfcsr_write(rt2x00dev, 32, 0xC0);
2762 if (is_type_ep)
2763 rt2800_rfcsr_write(rt2x00dev, 55, 0x06);
2764 else
2765 rt2800_rfcsr_write(rt2x00dev, 55, 0x47);
2766 } else {
2767 /* OFDM */
2768 if (is_type_ep)
2769 rt2800_rfcsr_write(rt2x00dev, 55, 0x03);
2770 else
2771 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
2772 }
2773
2774 power_bound = POWER_BOUND;
2775 ep_reg = 0x2;
2776 } else {
2777 rt2800_rfcsr_write(rt2x00dev, 10, 0x97);
2778 /* FIMXE: RF11 overwrite */
2779 rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
2780 rt2800_rfcsr_write(rt2x00dev, 25, 0xBF);
2781 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
2782 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
2783 rt2800_rfcsr_write(rt2x00dev, 37, 0x04);
2784 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
2785 rt2800_rfcsr_write(rt2x00dev, 40, 0x42);
2786 rt2800_rfcsr_write(rt2x00dev, 41, 0xBB);
2787 rt2800_rfcsr_write(rt2x00dev, 42, 0xD7);
2788 rt2800_rfcsr_write(rt2x00dev, 45, 0x41);
2789 rt2800_rfcsr_write(rt2x00dev, 48, 0x00);
2790 rt2800_rfcsr_write(rt2x00dev, 57, 0x77);
2791 rt2800_rfcsr_write(rt2x00dev, 60, 0x05);
2792 rt2800_rfcsr_write(rt2x00dev, 61, 0x01);
2793
2794 /* TODO RF27 <- tssi */
2795
2796 if (rf->channel >= 36 && rf->channel <= 64) {
2797
2798 rt2800_rfcsr_write(rt2x00dev, 12, 0x2E);
2799 rt2800_rfcsr_write(rt2x00dev, 13, 0x22);
2800 rt2800_rfcsr_write(rt2x00dev, 22, 0x60);
2801 rt2800_rfcsr_write(rt2x00dev, 23, 0x7F);
2802 if (rf->channel <= 50)
2803 rt2800_rfcsr_write(rt2x00dev, 24, 0x09);
2804 else if (rf->channel >= 52)
2805 rt2800_rfcsr_write(rt2x00dev, 24, 0x07);
2806 rt2800_rfcsr_write(rt2x00dev, 39, 0x1C);
2807 rt2800_rfcsr_write(rt2x00dev, 43, 0x5B);
2808 rt2800_rfcsr_write(rt2x00dev, 44, 0X40);
2809 rt2800_rfcsr_write(rt2x00dev, 46, 0X00);
2810 rt2800_rfcsr_write(rt2x00dev, 51, 0xFE);
2811 rt2800_rfcsr_write(rt2x00dev, 52, 0x0C);
2812 rt2800_rfcsr_write(rt2x00dev, 54, 0xF8);
2813 if (rf->channel <= 50) {
2814 rt2800_rfcsr_write(rt2x00dev, 55, 0x06),
2815 rt2800_rfcsr_write(rt2x00dev, 56, 0xD3);
2816 } else if (rf->channel >= 52) {
2817 rt2800_rfcsr_write(rt2x00dev, 55, 0x04);
2818 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
2819 }
2820
2821 rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
2822 rt2800_rfcsr_write(rt2x00dev, 59, 0x7F);
2823 rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
2824
2825 } else if (rf->channel >= 100 && rf->channel <= 165) {
2826
2827 rt2800_rfcsr_write(rt2x00dev, 12, 0x0E);
2828 rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
2829 rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
2830 if (rf->channel <= 153) {
2831 rt2800_rfcsr_write(rt2x00dev, 23, 0x3C);
2832 rt2800_rfcsr_write(rt2x00dev, 24, 0x06);
2833 } else if (rf->channel >= 155) {
2834 rt2800_rfcsr_write(rt2x00dev, 23, 0x38);
2835 rt2800_rfcsr_write(rt2x00dev, 24, 0x05);
2836 }
2837 if (rf->channel <= 138) {
2838 rt2800_rfcsr_write(rt2x00dev, 39, 0x1A);
2839 rt2800_rfcsr_write(rt2x00dev, 43, 0x3B);
2840 rt2800_rfcsr_write(rt2x00dev, 44, 0x20);
2841 rt2800_rfcsr_write(rt2x00dev, 46, 0x18);
2842 } else if (rf->channel >= 140) {
2843 rt2800_rfcsr_write(rt2x00dev, 39, 0x18);
2844 rt2800_rfcsr_write(rt2x00dev, 43, 0x1B);
2845 rt2800_rfcsr_write(rt2x00dev, 44, 0x10);
2846 rt2800_rfcsr_write(rt2x00dev, 46, 0X08);
2847 }
2848 if (rf->channel <= 124)
2849 rt2800_rfcsr_write(rt2x00dev, 51, 0xFC);
2850 else if (rf->channel >= 126)
2851 rt2800_rfcsr_write(rt2x00dev, 51, 0xEC);
2852 if (rf->channel <= 138)
2853 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
2854 else if (rf->channel >= 140)
2855 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
2856 rt2800_rfcsr_write(rt2x00dev, 54, 0xEB);
2857 if (rf->channel <= 138)
2858 rt2800_rfcsr_write(rt2x00dev, 55, 0x01);
2859 else if (rf->channel >= 140)
2860 rt2800_rfcsr_write(rt2x00dev, 55, 0x00);
2861 if (rf->channel <= 128)
2862 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
2863 else if (rf->channel >= 130)
2864 rt2800_rfcsr_write(rt2x00dev, 56, 0xAB);
2865 if (rf->channel <= 116)
2866 rt2800_rfcsr_write(rt2x00dev, 58, 0x1D);
2867 else if (rf->channel >= 118)
2868 rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
2869 if (rf->channel <= 138)
2870 rt2800_rfcsr_write(rt2x00dev, 59, 0x3F);
2871 else if (rf->channel >= 140)
2872 rt2800_rfcsr_write(rt2x00dev, 59, 0x7C);
2873 if (rf->channel <= 116)
2874 rt2800_rfcsr_write(rt2x00dev, 62, 0x1D);
2875 else if (rf->channel >= 118)
2876 rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
2877 }
2878
2879 power_bound = POWER_BOUND_5G;
2880 ep_reg = 0x3;
2881 }
2882
2883 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2884 if (info->default_power1 > power_bound)
2885 rt2x00_set_field8(&rfcsr, RFCSR49_TX, power_bound);
2886 else
2887 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2888 if (is_type_ep)
2889 rt2x00_set_field8(&rfcsr, RFCSR49_EP, ep_reg);
2890 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2891
2892 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
2893 if (info->default_power2 > power_bound)
2894 rt2x00_set_field8(&rfcsr, RFCSR50_TX, power_bound);
2895 else
2896 rt2x00_set_field8(&rfcsr, RFCSR50_TX, info->default_power2);
2897 if (is_type_ep)
2898 rt2x00_set_field8(&rfcsr, RFCSR50_EP, ep_reg);
2899 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2900
2901 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2902 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2903 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2904
2905 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD,
2906 rt2x00dev->default_ant.tx_chain_num >= 1);
2907 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
2908 rt2x00dev->default_ant.tx_chain_num == 2);
2909 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2910
2911 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD,
2912 rt2x00dev->default_ant.rx_chain_num >= 1);
2913 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
2914 rt2x00dev->default_ant.rx_chain_num == 2);
2915 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2916
2917 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2918 rt2800_rfcsr_write(rt2x00dev, 6, 0xe4);
2919
2920 if (conf_is_ht40(conf))
2921 rt2800_rfcsr_write(rt2x00dev, 30, 0x16);
2922 else
2923 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
2924
2925 if (!is_11b) {
2926 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
2927 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
2928 }
2929
2930 /* TODO proper frequency adjustment */
2931 rt2800_adjust_freq_offset(rt2x00dev);
2932
2933 /* TODO merge with others */
2934 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2935 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2936 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2937
2938 /* BBP settings */
2939 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
2940 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
2941 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
2942
2943 rt2800_bbp_write(rt2x00dev, 79, (rf->channel <= 14) ? 0x1C : 0x18);
2944 rt2800_bbp_write(rt2x00dev, 80, (rf->channel <= 14) ? 0x0E : 0x08);
2945 rt2800_bbp_write(rt2x00dev, 81, (rf->channel <= 14) ? 0x3A : 0x38);
2946 rt2800_bbp_write(rt2x00dev, 82, (rf->channel <= 14) ? 0x62 : 0x92);
2947
2948 /* GLRT band configuration */
2949 rt2800_bbp_write(rt2x00dev, 195, 128);
2950 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0xE0 : 0xF0);
2951 rt2800_bbp_write(rt2x00dev, 195, 129);
2952 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x1F : 0x1E);
2953 rt2800_bbp_write(rt2x00dev, 195, 130);
2954 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x38 : 0x28);
2955 rt2800_bbp_write(rt2x00dev, 195, 131);
2956 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x32 : 0x20);
2957 rt2800_bbp_write(rt2x00dev, 195, 133);
2958 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x28 : 0x7F);
2959 rt2800_bbp_write(rt2x00dev, 195, 124);
2960 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x19 : 0x7F);
2961 }
2962
2963 static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev *rt2x00dev,
2964 const unsigned int word,
2965 const u8 value)
2966 {
2967 u8 chain, reg;
2968
2969 for (chain = 0; chain < rt2x00dev->default_ant.rx_chain_num; chain++) {
2970 rt2800_bbp_read(rt2x00dev, 27, &reg);
2971 rt2x00_set_field8(&reg, BBP27_RX_CHAIN_SEL, chain);
2972 rt2800_bbp_write(rt2x00dev, 27, reg);
2973
2974 rt2800_bbp_write(rt2x00dev, word, value);
2975 }
2976 }
2977
2978 static void rt2800_iq_calibrate(struct rt2x00_dev *rt2x00dev, int channel)
2979 {
2980 u8 cal;
2981
2982 /* TX0 IQ Gain */
2983 rt2800_bbp_write(rt2x00dev, 158, 0x2c);
2984 if (channel <= 14)
2985 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX0_2G);
2986 else if (channel >= 36 && channel <= 64)
2987 cal = rt2x00_eeprom_byte(rt2x00dev,
2988 EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5G);
2989 else if (channel >= 100 && channel <= 138)
2990 cal = rt2x00_eeprom_byte(rt2x00dev,
2991 EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5G);
2992 else if (channel >= 140 && channel <= 165)
2993 cal = rt2x00_eeprom_byte(rt2x00dev,
2994 EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5G);
2995 else
2996 cal = 0;
2997 rt2800_bbp_write(rt2x00dev, 159, cal);
2998
2999 /* TX0 IQ Phase */
3000 rt2800_bbp_write(rt2x00dev, 158, 0x2d);
3001 if (channel <= 14)
3002 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX0_2G);
3003 else if (channel >= 36 && channel <= 64)
3004 cal = rt2x00_eeprom_byte(rt2x00dev,
3005 EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5G);
3006 else if (channel >= 100 && channel <= 138)
3007 cal = rt2x00_eeprom_byte(rt2x00dev,
3008 EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5G);
3009 else if (channel >= 140 && channel <= 165)
3010 cal = rt2x00_eeprom_byte(rt2x00dev,
3011 EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5G);
3012 else
3013 cal = 0;
3014 rt2800_bbp_write(rt2x00dev, 159, cal);
3015
3016 /* TX1 IQ Gain */
3017 rt2800_bbp_write(rt2x00dev, 158, 0x4a);
3018 if (channel <= 14)
3019 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX1_2G);
3020 else if (channel >= 36 && channel <= 64)
3021 cal = rt2x00_eeprom_byte(rt2x00dev,
3022 EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5G);
3023 else if (channel >= 100 && channel <= 138)
3024 cal = rt2x00_eeprom_byte(rt2x00dev,
3025 EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5G);
3026 else if (channel >= 140 && channel <= 165)
3027 cal = rt2x00_eeprom_byte(rt2x00dev,
3028 EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5G);
3029 else
3030 cal = 0;
3031 rt2800_bbp_write(rt2x00dev, 159, cal);
3032
3033 /* TX1 IQ Phase */
3034 rt2800_bbp_write(rt2x00dev, 158, 0x4b);
3035 if (channel <= 14)
3036 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX1_2G);
3037 else if (channel >= 36 && channel <= 64)
3038 cal = rt2x00_eeprom_byte(rt2x00dev,
3039 EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5G);
3040 else if (channel >= 100 && channel <= 138)
3041 cal = rt2x00_eeprom_byte(rt2x00dev,
3042 EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5G);
3043 else if (channel >= 140 && channel <= 165)
3044 cal = rt2x00_eeprom_byte(rt2x00dev,
3045 EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5G);
3046 else
3047 cal = 0;
3048 rt2800_bbp_write(rt2x00dev, 159, cal);
3049
3050 /* FIXME: possible RX0, RX1 callibration ? */
3051
3052 /* RF IQ compensation control */
3053 rt2800_bbp_write(rt2x00dev, 158, 0x04);
3054 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_RF_IQ_COMPENSATION_CONTROL);
3055 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
3056
3057 /* RF IQ imbalance compensation control */
3058 rt2800_bbp_write(rt2x00dev, 158, 0x03);
3059 cal = rt2x00_eeprom_byte(rt2x00dev,
3060 EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CONTROL);
3061 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
3062 }
3063
3064 static char rt2800_txpower_to_dev(struct rt2x00_dev *rt2x00dev,
3065 unsigned int channel,
3066 char txpower)
3067 {
3068 if (rt2x00_rt(rt2x00dev, RT3593))
3069 txpower = rt2x00_get_field8(txpower, EEPROM_TXPOWER_ALC);
3070
3071 if (channel <= 14)
3072 return clamp_t(char, txpower, MIN_G_TXPOWER, MAX_G_TXPOWER);
3073
3074 if (rt2x00_rt(rt2x00dev, RT3593))
3075 return clamp_t(char, txpower, MIN_A_TXPOWER_3593,
3076 MAX_A_TXPOWER_3593);
3077 else
3078 return clamp_t(char, txpower, MIN_A_TXPOWER, MAX_A_TXPOWER);
3079 }
3080
3081 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
3082 struct ieee80211_conf *conf,
3083 struct rf_channel *rf,
3084 struct channel_info *info)
3085 {
3086 u32 reg;
3087 unsigned int tx_pin;
3088 u8 bbp, rfcsr;
3089
3090 info->default_power1 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
3091 info->default_power1);
3092 info->default_power2 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
3093 info->default_power2);
3094 if (rt2x00dev->default_ant.tx_chain_num > 2)
3095 info->default_power3 =
3096 rt2800_txpower_to_dev(rt2x00dev, rf->channel,
3097 info->default_power3);
3098
3099 switch (rt2x00dev->chip.rf) {
3100 case RF2020:
3101 case RF3020:
3102 case RF3021:
3103 case RF3022:
3104 case RF3320:
3105 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
3106 break;
3107 case RF3052:
3108 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);
3109 break;
3110 case RF3053:
3111 rt2800_config_channel_rf3053(rt2x00dev, conf, rf, info);
3112 break;
3113 case RF3290:
3114 rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info);
3115 break;
3116 case RF3322:
3117 rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info);
3118 break;
3119 case RF5360:
3120 case RF5370:
3121 case RF5372:
3122 case RF5390:
3123 case RF5392:
3124 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
3125 break;
3126 case RF5592:
3127 rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info);
3128 break;
3129 default:
3130 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
3131 }
3132
3133 if (rt2x00_rf(rt2x00dev, RF3290) ||
3134 rt2x00_rf(rt2x00dev, RF3322) ||
3135 rt2x00_rf(rt2x00dev, RF5360) ||
3136 rt2x00_rf(rt2x00dev, RF5370) ||
3137 rt2x00_rf(rt2x00dev, RF5372) ||
3138 rt2x00_rf(rt2x00dev, RF5390) ||
3139 rt2x00_rf(rt2x00dev, RF5392)) {
3140 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
3141 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0);
3142 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0);
3143 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3144
3145 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
3146 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
3147 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
3148 }
3149
3150 /*
3151 * Change BBP settings
3152 */
3153 if (rt2x00_rt(rt2x00dev, RT3352)) {
3154 rt2800_bbp_write(rt2x00dev, 27, 0x0);
3155 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
3156 rt2800_bbp_write(rt2x00dev, 27, 0x20);
3157 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
3158 } else if (rt2x00_rt(rt2x00dev, RT3593)) {
3159 if (rf->channel > 14) {
3160 /* Disable CCK Packet detection on 5GHz */
3161 rt2800_bbp_write(rt2x00dev, 70, 0x00);
3162 } else {
3163 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
3164 }
3165
3166 if (conf_is_ht40(conf))
3167 rt2800_bbp_write(rt2x00dev, 105, 0x04);
3168 else
3169 rt2800_bbp_write(rt2x00dev, 105, 0x34);
3170
3171 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
3172 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
3173 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
3174 rt2800_bbp_write(rt2x00dev, 77, 0x98);
3175 } else {
3176 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
3177 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
3178 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
3179 rt2800_bbp_write(rt2x00dev, 86, 0);
3180 }
3181
3182 if (rf->channel <= 14) {
3183 if (!rt2x00_rt(rt2x00dev, RT5390) &&
3184 !rt2x00_rt(rt2x00dev, RT5392)) {
3185 if (test_bit(CAPABILITY_EXTERNAL_LNA_BG,
3186 &rt2x00dev->cap_flags)) {
3187 rt2800_bbp_write(rt2x00dev, 82, 0x62);
3188 rt2800_bbp_write(rt2x00dev, 75, 0x46);
3189 } else {
3190 if (rt2x00_rt(rt2x00dev, RT3593))
3191 rt2800_bbp_write(rt2x00dev, 82, 0x62);
3192 else
3193 rt2800_bbp_write(rt2x00dev, 82, 0x84);
3194 rt2800_bbp_write(rt2x00dev, 75, 0x50);
3195 }
3196 if (rt2x00_rt(rt2x00dev, RT3593))
3197 rt2800_bbp_write(rt2x00dev, 83, 0x8a);
3198 }
3199
3200 } else {
3201 if (rt2x00_rt(rt2x00dev, RT3572))
3202 rt2800_bbp_write(rt2x00dev, 82, 0x94);
3203 else if (rt2x00_rt(rt2x00dev, RT3593))
3204 rt2800_bbp_write(rt2x00dev, 82, 0x82);
3205 else
3206 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
3207
3208 if (rt2x00_rt(rt2x00dev, RT3593))
3209 rt2800_bbp_write(rt2x00dev, 83, 0x9a);
3210
3211 if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags))
3212 rt2800_bbp_write(rt2x00dev, 75, 0x46);
3213 else
3214 rt2800_bbp_write(rt2x00dev, 75, 0x50);
3215 }
3216
3217 rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
3218 rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
3219 rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
3220 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
3221 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
3222
3223 if (rt2x00_rt(rt2x00dev, RT3572))
3224 rt2800_rfcsr_write(rt2x00dev, 8, 0);
3225
3226 tx_pin = 0;
3227
3228 switch (rt2x00dev->default_ant.tx_chain_num) {
3229 case 3:
3230 /* Turn on tertiary PAs */
3231 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN,
3232 rf->channel > 14);
3233 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN,
3234 rf->channel <= 14);
3235 /* fall-through */
3236 case 2:
3237 /* Turn on secondary PAs */
3238 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN,
3239 rf->channel > 14);
3240 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN,
3241 rf->channel <= 14);
3242 /* fall-through */
3243 case 1:
3244 /* Turn on primary PAs */
3245 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN,
3246 rf->channel > 14);
3247 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
3248 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
3249 else
3250 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN,
3251 rf->channel <= 14);
3252 break;
3253 }
3254
3255 switch (rt2x00dev->default_ant.rx_chain_num) {
3256 case 3:
3257 /* Turn on tertiary LNAs */
3258 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A2_EN, 1);
3259 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G2_EN, 1);
3260 /* fall-through */
3261 case 2:
3262 /* Turn on secondary LNAs */
3263 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
3264 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
3265 /* fall-through */
3266 case 1:
3267 /* Turn on primary LNAs */
3268 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
3269 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
3270 break;
3271 }
3272
3273 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
3274 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
3275
3276 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
3277
3278 if (rt2x00_rt(rt2x00dev, RT3572))
3279 rt2800_rfcsr_write(rt2x00dev, 8, 0x80);
3280
3281 if (rt2x00_rt(rt2x00dev, RT3593)) {
3282 if (rt2x00_is_usb(rt2x00dev)) {
3283 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
3284
3285 /* Band selection. GPIO #8 controls all paths */
3286 rt2x00_set_field32(&reg, GPIO_CTRL_DIR8, 0);
3287 if (rf->channel <= 14)
3288 rt2x00_set_field32(&reg, GPIO_CTRL_VAL8, 1);
3289 else
3290 rt2x00_set_field32(&reg, GPIO_CTRL_VAL8, 0);
3291
3292 rt2x00_set_field32(&reg, GPIO_CTRL_DIR4, 0);
3293 rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
3294
3295 /* LNA PE control.
3296 * GPIO #4 controls PE0 and PE1,
3297 * GPIO #7 controls PE2
3298 */
3299 rt2x00_set_field32(&reg, GPIO_CTRL_VAL4, 1);
3300 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
3301
3302 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
3303 }
3304
3305 /* AGC init */
3306 if (rf->channel <= 14)
3307 reg = 0x1c + 2 * rt2x00dev->lna_gain;
3308 else
3309 reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3);
3310
3311 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
3312
3313 usleep_range(1000, 1500);
3314 }
3315
3316 if (rt2x00_rt(rt2x00dev, RT5592)) {
3317 rt2800_bbp_write(rt2x00dev, 195, 141);
3318 rt2800_bbp_write(rt2x00dev, 196, conf_is_ht40(conf) ? 0x10 : 0x1a);
3319
3320 /* AGC init */
3321 reg = (rf->channel <= 14 ? 0x1c : 0x24) + 2 * rt2x00dev->lna_gain;
3322 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
3323
3324 rt2800_iq_calibrate(rt2x00dev, rf->channel);
3325 }
3326
3327 rt2800_bbp_read(rt2x00dev, 4, &bbp);
3328 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
3329 rt2800_bbp_write(rt2x00dev, 4, bbp);
3330
3331 rt2800_bbp_read(rt2x00dev, 3, &bbp);
3332 rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
3333 rt2800_bbp_write(rt2x00dev, 3, bbp);
3334
3335 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
3336 if (conf_is_ht40(conf)) {
3337 rt2800_bbp_write(rt2x00dev, 69, 0x1a);
3338 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
3339 rt2800_bbp_write(rt2x00dev, 73, 0x16);
3340 } else {
3341 rt2800_bbp_write(rt2x00dev, 69, 0x16);
3342 rt2800_bbp_write(rt2x00dev, 70, 0x08);
3343 rt2800_bbp_write(rt2x00dev, 73, 0x11);
3344 }
3345 }
3346
3347 msleep(1);
3348
3349 /*
3350 * Clear channel statistic counters
3351 */
3352 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg);
3353 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg);
3354 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
3355
3356 /*
3357 * Clear update flag
3358 */
3359 if (rt2x00_rt(rt2x00dev, RT3352)) {
3360 rt2800_bbp_read(rt2x00dev, 49, &bbp);
3361 rt2x00_set_field8(&bbp, BBP49_UPDATE_FLAG, 0);
3362 rt2800_bbp_write(rt2x00dev, 49, bbp);
3363 }
3364 }
3365
3366 static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
3367 {
3368 u8 tssi_bounds[9];
3369 u8 current_tssi;
3370 u16 eeprom;
3371 u8 step;
3372 int i;
3373
3374 /*
3375 * Read TSSI boundaries for temperature compensation from
3376 * the EEPROM.
3377 *
3378 * Array idx 0 1 2 3 4 5 6 7 8
3379 * Matching Delta value -4 -3 -2 -1 0 +1 +2 +3 +4
3380 * Example TSSI bounds 0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
3381 */
3382 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
3383 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1, &eeprom);
3384 tssi_bounds[0] = rt2x00_get_field16(eeprom,
3385 EEPROM_TSSI_BOUND_BG1_MINUS4);
3386 tssi_bounds[1] = rt2x00_get_field16(eeprom,
3387 EEPROM_TSSI_BOUND_BG1_MINUS3);
3388
3389 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2, &eeprom);
3390 tssi_bounds[2] = rt2x00_get_field16(eeprom,
3391 EEPROM_TSSI_BOUND_BG2_MINUS2);
3392 tssi_bounds[3] = rt2x00_get_field16(eeprom,
3393 EEPROM_TSSI_BOUND_BG2_MINUS1);
3394
3395 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3, &eeprom);
3396 tssi_bounds[4] = rt2x00_get_field16(eeprom,
3397 EEPROM_TSSI_BOUND_BG3_REF);
3398 tssi_bounds[5] = rt2x00_get_field16(eeprom,
3399 EEPROM_TSSI_BOUND_BG3_PLUS1);
3400
3401 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4, &eeprom);
3402 tssi_bounds[6] = rt2x00_get_field16(eeprom,
3403 EEPROM_TSSI_BOUND_BG4_PLUS2);
3404 tssi_bounds[7] = rt2x00_get_field16(eeprom,
3405 EEPROM_TSSI_BOUND_BG4_PLUS3);
3406
3407 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5, &eeprom);
3408 tssi_bounds[8] = rt2x00_get_field16(eeprom,
3409 EEPROM_TSSI_BOUND_BG5_PLUS4);
3410
3411 step = rt2x00_get_field16(eeprom,
3412 EEPROM_TSSI_BOUND_BG5_AGC_STEP);
3413 } else {
3414 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1, &eeprom);
3415 tssi_bounds[0] = rt2x00_get_field16(eeprom,
3416 EEPROM_TSSI_BOUND_A1_MINUS4);
3417 tssi_bounds[1] = rt2x00_get_field16(eeprom,
3418 EEPROM_TSSI_BOUND_A1_MINUS3);
3419
3420 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2, &eeprom);
3421 tssi_bounds[2] = rt2x00_get_field16(eeprom,
3422 EEPROM_TSSI_BOUND_A2_MINUS2);
3423 tssi_bounds[3] = rt2x00_get_field16(eeprom,
3424 EEPROM_TSSI_BOUND_A2_MINUS1);
3425
3426 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3, &eeprom);
3427 tssi_bounds[4] = rt2x00_get_field16(eeprom,
3428 EEPROM_TSSI_BOUND_A3_REF);
3429 tssi_bounds[5] = rt2x00_get_field16(eeprom,
3430 EEPROM_TSSI_BOUND_A3_PLUS1);
3431
3432 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4, &eeprom);
3433 tssi_bounds[6] = rt2x00_get_field16(eeprom,
3434 EEPROM_TSSI_BOUND_A4_PLUS2);
3435 tssi_bounds[7] = rt2x00_get_field16(eeprom,
3436 EEPROM_TSSI_BOUND_A4_PLUS3);
3437
3438 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5, &eeprom);
3439 tssi_bounds[8] = rt2x00_get_field16(eeprom,
3440 EEPROM_TSSI_BOUND_A5_PLUS4);
3441
3442 step = rt2x00_get_field16(eeprom,
3443 EEPROM_TSSI_BOUND_A5_AGC_STEP);
3444 }
3445
3446 /*
3447 * Check if temperature compensation is supported.
3448 */
3449 if (tssi_bounds[4] == 0xff || step == 0xff)
3450 return 0;
3451
3452 /*
3453 * Read current TSSI (BBP 49).
3454 */
3455 rt2800_bbp_read(rt2x00dev, 49, &current_tssi);
3456
3457 /*
3458 * Compare TSSI value (BBP49) with the compensation boundaries
3459 * from the EEPROM and increase or decrease tx power.
3460 */
3461 for (i = 0; i <= 3; i++) {
3462 if (current_tssi > tssi_bounds[i])
3463 break;
3464 }
3465
3466 if (i == 4) {
3467 for (i = 8; i >= 5; i--) {
3468 if (current_tssi < tssi_bounds[i])
3469 break;
3470 }
3471 }
3472
3473 return (i - 4) * step;
3474 }
3475
3476 static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
3477 enum ieee80211_band band)
3478 {
3479 u16 eeprom;
3480 u8 comp_en;
3481 u8 comp_type;
3482 int comp_value = 0;
3483
3484 rt2800_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom);
3485
3486 /*
3487 * HT40 compensation not required.
3488 */
3489 if (eeprom == 0xffff ||
3490 !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
3491 return 0;
3492
3493 if (band == IEEE80211_BAND_2GHZ) {
3494 comp_en = rt2x00_get_field16(eeprom,
3495 EEPROM_TXPOWER_DELTA_ENABLE_2G);
3496 if (comp_en) {
3497 comp_type = rt2x00_get_field16(eeprom,
3498 EEPROM_TXPOWER_DELTA_TYPE_2G);
3499 comp_value = rt2x00_get_field16(eeprom,
3500 EEPROM_TXPOWER_DELTA_VALUE_2G);
3501 if (!comp_type)
3502 comp_value = -comp_value;
3503 }
3504 } else {
3505 comp_en = rt2x00_get_field16(eeprom,
3506 EEPROM_TXPOWER_DELTA_ENABLE_5G);
3507 if (comp_en) {
3508 comp_type = rt2x00_get_field16(eeprom,
3509 EEPROM_TXPOWER_DELTA_TYPE_5G);
3510 comp_value = rt2x00_get_field16(eeprom,
3511 EEPROM_TXPOWER_DELTA_VALUE_5G);
3512 if (!comp_type)
3513 comp_value = -comp_value;
3514 }
3515 }
3516
3517 return comp_value;
3518 }
3519
3520 static int rt2800_get_txpower_reg_delta(struct rt2x00_dev *rt2x00dev,
3521 int power_level, int max_power)
3522 {
3523 int delta;
3524
3525 if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags))
3526 return 0;
3527
3528 /*
3529 * XXX: We don't know the maximum transmit power of our hardware since
3530 * the EEPROM doesn't expose it. We only know that we are calibrated
3531 * to 100% tx power.
3532 *
3533 * Hence, we assume the regulatory limit that cfg80211 calulated for
3534 * the current channel is our maximum and if we are requested to lower
3535 * the value we just reduce our tx power accordingly.
3536 */
3537 delta = power_level - max_power;
3538 return min(delta, 0);
3539 }
3540
3541 static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
3542 enum ieee80211_band band, int power_level,
3543 u8 txpower, int delta)
3544 {
3545 u16 eeprom;
3546 u8 criterion;
3547 u8 eirp_txpower;
3548 u8 eirp_txpower_criterion;
3549 u8 reg_limit;
3550
3551 if (rt2x00_rt(rt2x00dev, RT3593))
3552 return min_t(u8, txpower, 0xc);
3553
3554 if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags)) {
3555 /*
3556 * Check if eirp txpower exceed txpower_limit.
3557 * We use OFDM 6M as criterion and its eirp txpower
3558 * is stored at EEPROM_EIRP_MAX_TX_POWER.
3559 * .11b data rate need add additional 4dbm
3560 * when calculating eirp txpower.
3561 */
3562 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3563 1, &eeprom);
3564 criterion = rt2x00_get_field16(eeprom,
3565 EEPROM_TXPOWER_BYRATE_RATE0);
3566
3567 rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER,
3568 &eeprom);
3569
3570 if (band == IEEE80211_BAND_2GHZ)
3571 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
3572 EEPROM_EIRP_MAX_TX_POWER_2GHZ);
3573 else
3574 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
3575 EEPROM_EIRP_MAX_TX_POWER_5GHZ);
3576
3577 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
3578 (is_rate_b ? 4 : 0) + delta;
3579
3580 reg_limit = (eirp_txpower > power_level) ?
3581 (eirp_txpower - power_level) : 0;
3582 } else
3583 reg_limit = 0;
3584
3585 txpower = max(0, txpower + delta - reg_limit);
3586 return min_t(u8, txpower, 0xc);
3587 }
3588
3589
3590 enum {
3591 TX_PWR_CFG_0_IDX,
3592 TX_PWR_CFG_1_IDX,
3593 TX_PWR_CFG_2_IDX,
3594 TX_PWR_CFG_3_IDX,
3595 TX_PWR_CFG_4_IDX,
3596 TX_PWR_CFG_5_IDX,
3597 TX_PWR_CFG_6_IDX,
3598 TX_PWR_CFG_7_IDX,
3599 TX_PWR_CFG_8_IDX,
3600 TX_PWR_CFG_9_IDX,
3601 TX_PWR_CFG_0_EXT_IDX,
3602 TX_PWR_CFG_1_EXT_IDX,
3603 TX_PWR_CFG_2_EXT_IDX,
3604 TX_PWR_CFG_3_EXT_IDX,
3605 TX_PWR_CFG_4_EXT_IDX,
3606 TX_PWR_CFG_IDX_COUNT,
3607 };
3608
3609 static void rt2800_config_txpower_rt3593(struct rt2x00_dev *rt2x00dev,
3610 struct ieee80211_channel *chan,
3611 int power_level)
3612 {
3613 u8 txpower;
3614 u16 eeprom;
3615 u32 regs[TX_PWR_CFG_IDX_COUNT];
3616 unsigned int offset;
3617 enum ieee80211_band band = chan->band;
3618 int delta;
3619 int i;
3620
3621 memset(regs, '\0', sizeof(regs));
3622
3623 /* TODO: adapt TX power reduction from the rt28xx code */
3624
3625 /* calculate temperature compensation delta */
3626 delta = rt2800_get_gain_calibration_delta(rt2x00dev);
3627
3628 if (band == IEEE80211_BAND_5GHZ)
3629 offset = 16;
3630 else
3631 offset = 0;
3632
3633 if (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
3634 offset += 8;
3635
3636 /* read the next four txpower values */
3637 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3638 offset, &eeprom);
3639
3640 /* CCK 1MBS,2MBS */
3641 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3642 txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
3643 txpower, delta);
3644 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3645 TX_PWR_CFG_0_CCK1_CH0, txpower);
3646 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3647 TX_PWR_CFG_0_CCK1_CH1, txpower);
3648 rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
3649 TX_PWR_CFG_0_EXT_CCK1_CH2, txpower);
3650
3651 /* CCK 5.5MBS,11MBS */
3652 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3653 txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
3654 txpower, delta);
3655 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3656 TX_PWR_CFG_0_CCK5_CH0, txpower);
3657 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3658 TX_PWR_CFG_0_CCK5_CH1, txpower);
3659 rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
3660 TX_PWR_CFG_0_EXT_CCK5_CH2, txpower);
3661
3662 /* OFDM 6MBS,9MBS */
3663 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3664 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3665 txpower, delta);
3666 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3667 TX_PWR_CFG_0_OFDM6_CH0, txpower);
3668 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3669 TX_PWR_CFG_0_OFDM6_CH1, txpower);
3670 rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
3671 TX_PWR_CFG_0_EXT_OFDM6_CH2, txpower);
3672
3673 /* OFDM 12MBS,18MBS */
3674 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3675 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3676 txpower, delta);
3677 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3678 TX_PWR_CFG_0_OFDM12_CH0, txpower);
3679 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3680 TX_PWR_CFG_0_OFDM12_CH1, txpower);
3681 rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
3682 TX_PWR_CFG_0_EXT_OFDM12_CH2, txpower);
3683
3684 /* read the next four txpower values */
3685 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3686 offset + 1, &eeprom);
3687
3688 /* OFDM 24MBS,36MBS */
3689 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3690 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3691 txpower, delta);
3692 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3693 TX_PWR_CFG_1_OFDM24_CH0, txpower);
3694 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3695 TX_PWR_CFG_1_OFDM24_CH1, txpower);
3696 rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
3697 TX_PWR_CFG_1_EXT_OFDM24_CH2, txpower);
3698
3699 /* OFDM 48MBS */
3700 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3701 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3702 txpower, delta);
3703 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3704 TX_PWR_CFG_1_OFDM48_CH0, txpower);
3705 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3706 TX_PWR_CFG_1_OFDM48_CH1, txpower);
3707 rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
3708 TX_PWR_CFG_1_EXT_OFDM48_CH2, txpower);
3709
3710 /* OFDM 54MBS */
3711 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3712 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3713 txpower, delta);
3714 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3715 TX_PWR_CFG_7_OFDM54_CH0, txpower);
3716 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3717 TX_PWR_CFG_7_OFDM54_CH1, txpower);
3718 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3719 TX_PWR_CFG_7_OFDM54_CH2, txpower);
3720
3721 /* read the next four txpower values */
3722 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3723 offset + 2, &eeprom);
3724
3725 /* MCS 0,1 */
3726 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3727 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3728 txpower, delta);
3729 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3730 TX_PWR_CFG_1_MCS0_CH0, txpower);
3731 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3732 TX_PWR_CFG_1_MCS0_CH1, txpower);
3733 rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
3734 TX_PWR_CFG_1_EXT_MCS0_CH2, txpower);
3735
3736 /* MCS 2,3 */
3737 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3738 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3739 txpower, delta);
3740 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3741 TX_PWR_CFG_1_MCS2_CH0, txpower);
3742 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3743 TX_PWR_CFG_1_MCS2_CH1, txpower);
3744 rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
3745 TX_PWR_CFG_1_EXT_MCS2_CH2, txpower);
3746
3747 /* MCS 4,5 */
3748 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3749 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3750 txpower, delta);
3751 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3752 TX_PWR_CFG_2_MCS4_CH0, txpower);
3753 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3754 TX_PWR_CFG_2_MCS4_CH1, txpower);
3755 rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
3756 TX_PWR_CFG_2_EXT_MCS4_CH2, txpower);
3757
3758 /* MCS 6 */
3759 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3760 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3761 txpower, delta);
3762 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3763 TX_PWR_CFG_2_MCS6_CH0, txpower);
3764 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3765 TX_PWR_CFG_2_MCS6_CH1, txpower);
3766 rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
3767 TX_PWR_CFG_2_EXT_MCS6_CH2, txpower);
3768
3769 /* read the next four txpower values */
3770 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3771 offset + 3, &eeprom);
3772
3773 /* MCS 7 */
3774 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3775 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3776 txpower, delta);
3777 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3778 TX_PWR_CFG_7_MCS7_CH0, txpower);
3779 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3780 TX_PWR_CFG_7_MCS7_CH1, txpower);
3781 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3782 TX_PWR_CFG_7_MCS7_CH2, txpower);
3783
3784 /* MCS 8,9 */
3785 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3786 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3787 txpower, delta);
3788 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3789 TX_PWR_CFG_2_MCS8_CH0, txpower);
3790 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3791 TX_PWR_CFG_2_MCS8_CH1, txpower);
3792 rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
3793 TX_PWR_CFG_2_EXT_MCS8_CH2, txpower);
3794
3795 /* MCS 10,11 */
3796 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3797 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3798 txpower, delta);
3799 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3800 TX_PWR_CFG_2_MCS10_CH0, txpower);
3801 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3802 TX_PWR_CFG_2_MCS10_CH1, txpower);
3803 rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
3804 TX_PWR_CFG_2_EXT_MCS10_CH2, txpower);
3805
3806 /* MCS 12,13 */
3807 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3808 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3809 txpower, delta);
3810 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3811 TX_PWR_CFG_3_MCS12_CH0, txpower);
3812 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3813 TX_PWR_CFG_3_MCS12_CH1, txpower);
3814 rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
3815 TX_PWR_CFG_3_EXT_MCS12_CH2, txpower);
3816
3817 /* read the next four txpower values */
3818 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3819 offset + 4, &eeprom);
3820
3821 /* MCS 14 */
3822 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3823 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3824 txpower, delta);
3825 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3826 TX_PWR_CFG_3_MCS14_CH0, txpower);
3827 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3828 TX_PWR_CFG_3_MCS14_CH1, txpower);
3829 rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
3830 TX_PWR_CFG_3_EXT_MCS14_CH2, txpower);
3831
3832 /* MCS 15 */
3833 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3834 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3835 txpower, delta);
3836 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3837 TX_PWR_CFG_8_MCS15_CH0, txpower);
3838 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3839 TX_PWR_CFG_8_MCS15_CH1, txpower);
3840 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3841 TX_PWR_CFG_8_MCS15_CH2, txpower);
3842
3843 /* MCS 16,17 */
3844 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3845 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3846 txpower, delta);
3847 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3848 TX_PWR_CFG_5_MCS16_CH0, txpower);
3849 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3850 TX_PWR_CFG_5_MCS16_CH1, txpower);
3851 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3852 TX_PWR_CFG_5_MCS16_CH2, txpower);
3853
3854 /* MCS 18,19 */
3855 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3856 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3857 txpower, delta);
3858 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3859 TX_PWR_CFG_5_MCS18_CH0, txpower);
3860 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3861 TX_PWR_CFG_5_MCS18_CH1, txpower);
3862 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3863 TX_PWR_CFG_5_MCS18_CH2, txpower);
3864
3865 /* read the next four txpower values */
3866 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3867 offset + 5, &eeprom);
3868
3869 /* MCS 20,21 */
3870 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3871 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3872 txpower, delta);
3873 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3874 TX_PWR_CFG_6_MCS20_CH0, txpower);
3875 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3876 TX_PWR_CFG_6_MCS20_CH1, txpower);
3877 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3878 TX_PWR_CFG_6_MCS20_CH2, txpower);
3879
3880 /* MCS 22 */
3881 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3882 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3883 txpower, delta);
3884 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3885 TX_PWR_CFG_6_MCS22_CH0, txpower);
3886 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3887 TX_PWR_CFG_6_MCS22_CH1, txpower);
3888 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3889 TX_PWR_CFG_6_MCS22_CH2, txpower);
3890
3891 /* MCS 23 */
3892 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3893 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3894 txpower, delta);
3895 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3896 TX_PWR_CFG_8_MCS23_CH0, txpower);
3897 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3898 TX_PWR_CFG_8_MCS23_CH1, txpower);
3899 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3900 TX_PWR_CFG_8_MCS23_CH2, txpower);
3901
3902 /* read the next four txpower values */
3903 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3904 offset + 6, &eeprom);
3905
3906 /* STBC, MCS 0,1 */
3907 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3908 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3909 txpower, delta);
3910 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3911 TX_PWR_CFG_3_STBC0_CH0, txpower);
3912 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3913 TX_PWR_CFG_3_STBC0_CH1, txpower);
3914 rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
3915 TX_PWR_CFG_3_EXT_STBC0_CH2, txpower);
3916
3917 /* STBC, MCS 2,3 */
3918 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3919 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3920 txpower, delta);
3921 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3922 TX_PWR_CFG_3_STBC2_CH0, txpower);
3923 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3924 TX_PWR_CFG_3_STBC2_CH1, txpower);
3925 rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
3926 TX_PWR_CFG_3_EXT_STBC2_CH2, txpower);
3927
3928 /* STBC, MCS 4,5 */
3929 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3930 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3931 txpower, delta);
3932 rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE0, txpower);
3933 rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE1, txpower);
3934 rt2x00_set_field32(&regs[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE0,
3935 txpower);
3936
3937 /* STBC, MCS 6 */
3938 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3939 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3940 txpower, delta);
3941 rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE2, txpower);
3942 rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE3, txpower);
3943 rt2x00_set_field32(&regs[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE2,
3944 txpower);
3945
3946 /* read the next four txpower values */
3947 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3948 offset + 7, &eeprom);
3949
3950 /* STBC, MCS 7 */
3951 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3952 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3953 txpower, delta);
3954 rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
3955 TX_PWR_CFG_9_STBC7_CH0, txpower);
3956 rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
3957 TX_PWR_CFG_9_STBC7_CH1, txpower);
3958 rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
3959 TX_PWR_CFG_9_STBC7_CH2, txpower);
3960
3961 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, regs[TX_PWR_CFG_0_IDX]);
3962 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, regs[TX_PWR_CFG_1_IDX]);
3963 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, regs[TX_PWR_CFG_2_IDX]);
3964 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, regs[TX_PWR_CFG_3_IDX]);
3965 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, regs[TX_PWR_CFG_4_IDX]);
3966 rt2800_register_write(rt2x00dev, TX_PWR_CFG_5, regs[TX_PWR_CFG_5_IDX]);
3967 rt2800_register_write(rt2x00dev, TX_PWR_CFG_6, regs[TX_PWR_CFG_6_IDX]);
3968 rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, regs[TX_PWR_CFG_7_IDX]);
3969 rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, regs[TX_PWR_CFG_8_IDX]);
3970 rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, regs[TX_PWR_CFG_9_IDX]);
3971
3972 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0_EXT,
3973 regs[TX_PWR_CFG_0_EXT_IDX]);
3974 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1_EXT,
3975 regs[TX_PWR_CFG_1_EXT_IDX]);
3976 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2_EXT,
3977 regs[TX_PWR_CFG_2_EXT_IDX]);
3978 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3_EXT,
3979 regs[TX_PWR_CFG_3_EXT_IDX]);
3980 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4_EXT,
3981 regs[TX_PWR_CFG_4_EXT_IDX]);
3982
3983 for (i = 0; i < TX_PWR_CFG_IDX_COUNT; i++)
3984 rt2x00_dbg(rt2x00dev,
3985 "band:%cGHz, BW:%c0MHz, TX_PWR_CFG_%d%s = %08lx\n",
3986 (band == IEEE80211_BAND_5GHZ) ? '5' : '2',
3987 (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) ?
3988 '4' : '2',
3989 (i > TX_PWR_CFG_9_IDX) ?
3990 (i - TX_PWR_CFG_9_IDX - 1) : i,
3991 (i > TX_PWR_CFG_9_IDX) ? "_EXT" : "",
3992 (unsigned long) regs[i]);
3993 }
3994
3995 /*
3996 * We configure transmit power using MAC TX_PWR_CFG_{0,...,N} registers and
3997 * BBP R1 register. TX_PWR_CFG_X allow to configure per rate TX power values,
3998 * 4 bits for each rate (tune from 0 to 15 dBm). BBP_R1 controls transmit power
3999 * for all rates, but allow to set only 4 discrete values: -12, -6, 0 and 6 dBm.
4000 * Reference per rate transmit power values are located in the EEPROM at
4001 * EEPROM_TXPOWER_BYRATE offset. We adjust them and BBP R1 settings according to
4002 * current conditions (i.e. band, bandwidth, temperature, user settings).
4003 */
4004 static void rt2800_config_txpower_rt28xx(struct rt2x00_dev *rt2x00dev,
4005 struct ieee80211_channel *chan,
4006 int power_level)
4007 {
4008 u8 txpower, r1;
4009 u16 eeprom;
4010 u32 reg, offset;
4011 int i, is_rate_b, delta, power_ctrl;
4012 enum ieee80211_band band = chan->band;
4013
4014 /*
4015 * Calculate HT40 compensation. For 40MHz we need to add or subtract
4016 * value read from EEPROM (different for 2GHz and for 5GHz).
4017 */
4018 delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
4019
4020 /*
4021 * Calculate temperature compensation. Depends on measurement of current
4022 * TSSI (Transmitter Signal Strength Indication) we know TX power (due
4023 * to temperature or maybe other factors) is smaller or bigger than
4024 * expected. We adjust it, based on TSSI reference and boundaries values
4025 * provided in EEPROM.
4026 */
4027 delta += rt2800_get_gain_calibration_delta(rt2x00dev);
4028
4029 /*
4030 * Decrease power according to user settings, on devices with unknown
4031 * maximum tx power. For other devices we take user power_level into
4032 * consideration on rt2800_compensate_txpower().
4033 */
4034 delta += rt2800_get_txpower_reg_delta(rt2x00dev, power_level,
4035 chan->max_power);
4036
4037 /*
4038 * BBP_R1 controls TX power for all rates, it allow to set the following
4039 * gains -12, -6, 0, +6 dBm by setting values 2, 1, 0, 3 respectively.
4040 *
4041 * TODO: we do not use +6 dBm option to do not increase power beyond
4042 * regulatory limit, however this could be utilized for devices with
4043 * CAPABILITY_POWER_LIMIT.
4044 *
4045 * TODO: add different temperature compensation code for RT3290 & RT5390
4046 * to allow to use BBP_R1 for those chips.
4047 */
4048 if (!rt2x00_rt(rt2x00dev, RT3290) &&
4049 !rt2x00_rt(rt2x00dev, RT5390)) {
4050 rt2800_bbp_read(rt2x00dev, 1, &r1);
4051 if (delta <= -12) {
4052 power_ctrl = 2;
4053 delta += 12;
4054 } else if (delta <= -6) {
4055 power_ctrl = 1;
4056 delta += 6;
4057 } else {
4058 power_ctrl = 0;
4059 }
4060 rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, power_ctrl);
4061 rt2800_bbp_write(rt2x00dev, 1, r1);
4062 }
4063
4064 offset = TX_PWR_CFG_0;
4065
4066 for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
4067 /* just to be safe */
4068 if (offset > TX_PWR_CFG_4)
4069 break;
4070
4071 rt2800_register_read(rt2x00dev, offset, &reg);
4072
4073 /* read the next four txpower values */
4074 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4075 i, &eeprom);
4076
4077 is_rate_b = i ? 0 : 1;
4078 /*
4079 * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
4080 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
4081 * TX_PWR_CFG_4: unknown
4082 */
4083 txpower = rt2x00_get_field16(eeprom,
4084 EEPROM_TXPOWER_BYRATE_RATE0);
4085 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4086 power_level, txpower, delta);
4087 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
4088
4089 /*
4090 * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
4091 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
4092 * TX_PWR_CFG_4: unknown
4093 */
4094 txpower = rt2x00_get_field16(eeprom,
4095 EEPROM_TXPOWER_BYRATE_RATE1);
4096 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4097 power_level, txpower, delta);
4098 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
4099
4100 /*
4101 * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
4102 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14,
4103 * TX_PWR_CFG_4: unknown
4104 */
4105 txpower = rt2x00_get_field16(eeprom,
4106 EEPROM_TXPOWER_BYRATE_RATE2);
4107 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4108 power_level, txpower, delta);
4109 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
4110
4111 /*
4112 * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
4113 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15,
4114 * TX_PWR_CFG_4: unknown
4115 */
4116 txpower = rt2x00_get_field16(eeprom,
4117 EEPROM_TXPOWER_BYRATE_RATE3);
4118 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4119 power_level, txpower, delta);
4120 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
4121
4122 /* read the next four txpower values */
4123 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4124 i + 1, &eeprom);
4125
4126 is_rate_b = 0;
4127 /*
4128 * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
4129 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
4130 * TX_PWR_CFG_4: unknown
4131 */
4132 txpower = rt2x00_get_field16(eeprom,
4133 EEPROM_TXPOWER_BYRATE_RATE0);
4134 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4135 power_level, txpower, delta);
4136 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
4137
4138 /*
4139 * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
4140 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
4141 * TX_PWR_CFG_4: unknown
4142 */
4143 txpower = rt2x00_get_field16(eeprom,
4144 EEPROM_TXPOWER_BYRATE_RATE1);
4145 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4146 power_level, txpower, delta);
4147 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
4148
4149 /*
4150 * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
4151 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
4152 * TX_PWR_CFG_4: unknown
4153 */
4154 txpower = rt2x00_get_field16(eeprom,
4155 EEPROM_TXPOWER_BYRATE_RATE2);
4156 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4157 power_level, txpower, delta);
4158 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
4159
4160 /*
4161 * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
4162 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
4163 * TX_PWR_CFG_4: unknown
4164 */
4165 txpower = rt2x00_get_field16(eeprom,
4166 EEPROM_TXPOWER_BYRATE_RATE3);
4167 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4168 power_level, txpower, delta);
4169 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
4170
4171 rt2800_register_write(rt2x00dev, offset, reg);
4172
4173 /* next TX_PWR_CFG register */
4174 offset += 4;
4175 }
4176 }
4177
4178 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
4179 struct ieee80211_channel *chan,
4180 int power_level)
4181 {
4182 if (rt2x00_rt(rt2x00dev, RT3593))
4183 rt2800_config_txpower_rt3593(rt2x00dev, chan, power_level);
4184 else
4185 rt2800_config_txpower_rt28xx(rt2x00dev, chan, power_level);
4186 }
4187
4188 void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
4189 {
4190 rt2800_config_txpower(rt2x00dev, rt2x00dev->hw->conf.chandef.chan,
4191 rt2x00dev->tx_power);
4192 }
4193 EXPORT_SYMBOL_GPL(rt2800_gain_calibration);
4194
4195 void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev)
4196 {
4197 u32 tx_pin;
4198 u8 rfcsr;
4199
4200 /*
4201 * A voltage-controlled oscillator(VCO) is an electronic oscillator
4202 * designed to be controlled in oscillation frequency by a voltage
4203 * input. Maybe the temperature will affect the frequency of
4204 * oscillation to be shifted. The VCO calibration will be called
4205 * periodically to adjust the frequency to be precision.
4206 */
4207
4208 rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
4209 tx_pin &= TX_PIN_CFG_PA_PE_DISABLE;
4210 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
4211
4212 switch (rt2x00dev->chip.rf) {
4213 case RF2020:
4214 case RF3020:
4215 case RF3021:
4216 case RF3022:
4217 case RF3320:
4218 case RF3052:
4219 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
4220 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
4221 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
4222 break;
4223 case RF3053:
4224 case RF3290:
4225 case RF5360:
4226 case RF5370:
4227 case RF5372:
4228 case RF5390:
4229 case RF5392:
4230 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
4231 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
4232 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
4233 break;
4234 default:
4235 return;
4236 }
4237
4238 mdelay(1);
4239
4240 rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
4241 if (rt2x00dev->rf_channel <= 14) {
4242 switch (rt2x00dev->default_ant.tx_chain_num) {
4243 case 3:
4244 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1);
4245 /* fall through */
4246 case 2:
4247 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
4248 /* fall through */
4249 case 1:
4250 default:
4251 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
4252 break;
4253 }
4254 } else {
4255 switch (rt2x00dev->default_ant.tx_chain_num) {
4256 case 3:
4257 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1);
4258 /* fall through */
4259 case 2:
4260 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
4261 /* fall through */
4262 case 1:
4263 default:
4264 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1);
4265 break;
4266 }
4267 }
4268 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
4269
4270 }
4271 EXPORT_SYMBOL_GPL(rt2800_vco_calibration);
4272
4273 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
4274 struct rt2x00lib_conf *libconf)
4275 {
4276 u32 reg;
4277
4278 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
4279 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
4280 libconf->conf->short_frame_max_tx_count);
4281 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
4282 libconf->conf->long_frame_max_tx_count);
4283 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
4284 }
4285
4286 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
4287 struct rt2x00lib_conf *libconf)
4288 {
4289 enum dev_state state =
4290 (libconf->conf->flags & IEEE80211_CONF_PS) ?
4291 STATE_SLEEP : STATE_AWAKE;
4292 u32 reg;
4293
4294 if (state == STATE_SLEEP) {
4295 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
4296
4297 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
4298 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
4299 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
4300 libconf->conf->listen_interval - 1);
4301 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
4302 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
4303
4304 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
4305 } else {
4306 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
4307 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
4308 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
4309 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
4310 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
4311
4312 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
4313 }
4314 }
4315
4316 void rt2800_config(struct rt2x00_dev *rt2x00dev,
4317 struct rt2x00lib_conf *libconf,
4318 const unsigned int flags)
4319 {
4320 /* Always recalculate LNA gain before changing configuration */
4321 rt2800_config_lna_gain(rt2x00dev, libconf);
4322
4323 if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
4324 rt2800_config_channel(rt2x00dev, libconf->conf,
4325 &libconf->rf, &libconf->channel);
4326 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
4327 libconf->conf->power_level);
4328 }
4329 if (flags & IEEE80211_CONF_CHANGE_POWER)
4330 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
4331 libconf->conf->power_level);
4332 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
4333 rt2800_config_retry_limit(rt2x00dev, libconf);
4334 if (flags & IEEE80211_CONF_CHANGE_PS)
4335 rt2800_config_ps(rt2x00dev, libconf);
4336 }
4337 EXPORT_SYMBOL_GPL(rt2800_config);
4338
4339 /*
4340 * Link tuning
4341 */
4342 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
4343 {
4344 u32 reg;
4345
4346 /*
4347 * Update FCS error count from register.
4348 */
4349 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
4350 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
4351 }
4352 EXPORT_SYMBOL_GPL(rt2800_link_stats);
4353
4354 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
4355 {
4356 u8 vgc;
4357
4358 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
4359 if (rt2x00_rt(rt2x00dev, RT3070) ||
4360 rt2x00_rt(rt2x00dev, RT3071) ||
4361 rt2x00_rt(rt2x00dev, RT3090) ||
4362 rt2x00_rt(rt2x00dev, RT3290) ||
4363 rt2x00_rt(rt2x00dev, RT3390) ||
4364 rt2x00_rt(rt2x00dev, RT3572) ||
4365 rt2x00_rt(rt2x00dev, RT5390) ||
4366 rt2x00_rt(rt2x00dev, RT5392) ||
4367 rt2x00_rt(rt2x00dev, RT5592))
4368 vgc = 0x1c + (2 * rt2x00dev->lna_gain);
4369 else
4370 vgc = 0x2e + rt2x00dev->lna_gain;
4371 } else { /* 5GHZ band */
4372 if (rt2x00_rt(rt2x00dev, RT3572))
4373 vgc = 0x22 + (rt2x00dev->lna_gain * 5) / 3;
4374 else if (rt2x00_rt(rt2x00dev, RT5592))
4375 vgc = 0x24 + (2 * rt2x00dev->lna_gain);
4376 else {
4377 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
4378 vgc = 0x32 + (rt2x00dev->lna_gain * 5) / 3;
4379 else
4380 vgc = 0x3a + (rt2x00dev->lna_gain * 5) / 3;
4381 }
4382 }
4383
4384 return vgc;
4385 }
4386
4387 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
4388 struct link_qual *qual, u8 vgc_level)
4389 {
4390 if (qual->vgc_level != vgc_level) {
4391 if (rt2x00_rt(rt2x00dev, RT5592)) {
4392 rt2800_bbp_write(rt2x00dev, 83, qual->rssi > -65 ? 0x4a : 0x7a);
4393 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, vgc_level);
4394 } else
4395 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
4396 qual->vgc_level = vgc_level;
4397 qual->vgc_level_reg = vgc_level;
4398 }
4399 }
4400
4401 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
4402 {
4403 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
4404 }
4405 EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
4406
4407 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
4408 const u32 count)
4409 {
4410 u8 vgc;
4411
4412 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
4413 return;
4414 /*
4415 * When RSSI is better then -80 increase VGC level with 0x10, except
4416 * for rt5592 chip.
4417 */
4418
4419 vgc = rt2800_get_default_vgc(rt2x00dev);
4420
4421 if (rt2x00_rt(rt2x00dev, RT5592) && qual->rssi > -65)
4422 vgc += 0x20;
4423 else if (qual->rssi > -80)
4424 vgc += 0x10;
4425
4426 rt2800_set_vgc(rt2x00dev, qual, vgc);
4427 }
4428 EXPORT_SYMBOL_GPL(rt2800_link_tuner);
4429
4430 /*
4431 * Initialization functions.
4432 */
4433 static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
4434 {
4435 u32 reg;
4436 u16 eeprom;
4437 unsigned int i;
4438 int ret;
4439
4440 rt2800_disable_wpdma(rt2x00dev);
4441
4442 ret = rt2800_drv_init_registers(rt2x00dev);
4443 if (ret)
4444 return ret;
4445
4446 rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
4447 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
4448 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
4449 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
4450 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
4451 rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
4452
4453 rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
4454 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
4455 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
4456 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
4457 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
4458 rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
4459
4460 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
4461 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
4462
4463 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
4464
4465 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
4466 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
4467 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
4468 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
4469 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
4470 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
4471 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
4472 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
4473
4474 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
4475
4476 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
4477 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
4478 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
4479 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
4480
4481 if (rt2x00_rt(rt2x00dev, RT3290)) {
4482 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
4483 if (rt2x00_get_field32(reg, WLAN_EN) == 1) {
4484 rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 1);
4485 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
4486 }
4487
4488 rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
4489 if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) {
4490 rt2x00_set_field32(&reg, LDO0_EN, 1);
4491 rt2x00_set_field32(&reg, LDO_BGSEL, 3);
4492 rt2800_register_write(rt2x00dev, CMB_CTRL, reg);
4493 }
4494
4495 rt2800_register_read(rt2x00dev, OSC_CTRL, &reg);
4496 rt2x00_set_field32(&reg, OSC_ROSC_EN, 1);
4497 rt2x00_set_field32(&reg, OSC_CAL_REQ, 1);
4498 rt2x00_set_field32(&reg, OSC_REF_CYCLE, 0x27);
4499 rt2800_register_write(rt2x00dev, OSC_CTRL, reg);
4500
4501 rt2800_register_read(rt2x00dev, COEX_CFG0, &reg);
4502 rt2x00_set_field32(&reg, COEX_CFG_ANT, 0x5e);
4503 rt2800_register_write(rt2x00dev, COEX_CFG0, reg);
4504
4505 rt2800_register_read(rt2x00dev, COEX_CFG2, &reg);
4506 rt2x00_set_field32(&reg, BT_COEX_CFG1, 0x00);
4507 rt2x00_set_field32(&reg, BT_COEX_CFG0, 0x17);
4508 rt2x00_set_field32(&reg, WL_COEX_CFG1, 0x93);
4509 rt2x00_set_field32(&reg, WL_COEX_CFG0, 0x7f);
4510 rt2800_register_write(rt2x00dev, COEX_CFG2, reg);
4511
4512 rt2800_register_read(rt2x00dev, PLL_CTRL, &reg);
4513 rt2x00_set_field32(&reg, PLL_CONTROL, 1);
4514 rt2800_register_write(rt2x00dev, PLL_CTRL, reg);
4515 }
4516
4517 if (rt2x00_rt(rt2x00dev, RT3071) ||
4518 rt2x00_rt(rt2x00dev, RT3090) ||
4519 rt2x00_rt(rt2x00dev, RT3290) ||
4520 rt2x00_rt(rt2x00dev, RT3390)) {
4521
4522 if (rt2x00_rt(rt2x00dev, RT3290))
4523 rt2800_register_write(rt2x00dev, TX_SW_CFG0,
4524 0x00000404);
4525 else
4526 rt2800_register_write(rt2x00dev, TX_SW_CFG0,
4527 0x00000400);
4528
4529 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
4530 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
4531 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
4532 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
4533 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1,
4534 &eeprom);
4535 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
4536 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4537 0x0000002c);
4538 else
4539 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4540 0x0000000f);
4541 } else {
4542 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
4543 }
4544 } else if (rt2x00_rt(rt2x00dev, RT3070)) {
4545 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
4546
4547 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
4548 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
4549 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
4550 } else {
4551 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4552 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
4553 }
4554 } else if (rt2800_is_305x_soc(rt2x00dev)) {
4555 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
4556 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
4557 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
4558 } else if (rt2x00_rt(rt2x00dev, RT3352)) {
4559 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
4560 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4561 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
4562 } else if (rt2x00_rt(rt2x00dev, RT3572)) {
4563 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
4564 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4565 } else if (rt2x00_rt(rt2x00dev, RT3593)) {
4566 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
4567 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
4568 if (rt2x00_rt_rev_lt(rt2x00dev, RT3593, REV_RT3593E)) {
4569 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1,
4570 &eeprom);
4571 if (rt2x00_get_field16(eeprom,
4572 EEPROM_NIC_CONF1_DAC_TEST))
4573 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4574 0x0000001f);
4575 else
4576 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4577 0x0000000f);
4578 } else {
4579 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4580 0x00000000);
4581 }
4582 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
4583 rt2x00_rt(rt2x00dev, RT5392) ||
4584 rt2x00_rt(rt2x00dev, RT5592)) {
4585 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
4586 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4587 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
4588 } else {
4589 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
4590 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4591 }
4592
4593 rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
4594 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
4595 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
4596 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
4597 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
4598 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
4599 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
4600 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
4601 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
4602 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
4603
4604 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
4605 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
4606 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
4607 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
4608 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
4609
4610 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
4611 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
4612 if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
4613 rt2x00_rt(rt2x00dev, RT2883) ||
4614 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
4615 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
4616 else
4617 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
4618 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
4619 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
4620 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
4621
4622 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
4623 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
4624 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
4625 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
4626 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
4627 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
4628 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
4629 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
4630 rt2800_register_write(rt2x00dev, LED_CFG, reg);
4631
4632 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
4633
4634 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
4635 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
4636 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
4637 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
4638 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
4639 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
4640 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
4641 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
4642
4643 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
4644 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
4645 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
4646 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
4647 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
4648 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
4649 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
4650 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
4651 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
4652
4653 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
4654 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
4655 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
4656 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
4657 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4658 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4659 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4660 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
4661 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4662 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
4663 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
4664 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
4665
4666 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
4667 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
4668 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
4669 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
4670 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4671 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4672 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4673 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
4674 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4675 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
4676 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
4677 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
4678
4679 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
4680 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
4681 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
4682 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
4683 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4684 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4685 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4686 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
4687 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4688 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
4689 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
4690 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
4691
4692 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
4693 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
4694 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
4695 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
4696 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4697 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4698 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4699 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
4700 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4701 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
4702 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
4703 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
4704
4705 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
4706 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
4707 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
4708 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
4709 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4710 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4711 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4712 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
4713 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4714 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
4715 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
4716 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
4717
4718 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
4719 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
4720 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
4721 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
4722 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4723 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4724 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4725 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
4726 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4727 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
4728 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
4729 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
4730
4731 if (rt2x00_is_usb(rt2x00dev)) {
4732 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
4733
4734 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
4735 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
4736 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
4737 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
4738 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
4739 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
4740 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
4741 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
4742 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
4743 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
4744 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
4745 }
4746
4747 /*
4748 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
4749 * although it is reserved.
4750 */
4751 rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, &reg);
4752 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
4753 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
4754 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
4755 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
4756 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
4757 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
4758 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
4759 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
4760 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
4761 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
4762 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
4763
4764 reg = rt2x00_rt(rt2x00dev, RT5592) ? 0x00000082 : 0x00000002;
4765 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, reg);
4766
4767 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
4768 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
4769 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
4770 IEEE80211_MAX_RTS_THRESHOLD);
4771 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
4772 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
4773
4774 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
4775
4776 /*
4777 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
4778 * time should be set to 16. However, the original Ralink driver uses
4779 * 16 for both and indeed using a value of 10 for CCK SIFS results in
4780 * connection problems with 11g + CTS protection. Hence, use the same
4781 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
4782 */
4783 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
4784 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
4785 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
4786 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
4787 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
4788 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
4789 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
4790
4791 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
4792
4793 /*
4794 * ASIC will keep garbage value after boot, clear encryption keys.
4795 */
4796 for (i = 0; i < 4; i++)
4797 rt2800_register_write(rt2x00dev,
4798 SHARED_KEY_MODE_ENTRY(i), 0);
4799
4800 for (i = 0; i < 256; i++) {
4801 rt2800_config_wcid(rt2x00dev, NULL, i);
4802 rt2800_delete_wcid_attr(rt2x00dev, i);
4803 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
4804 }
4805
4806 /*
4807 * Clear all beacons
4808 */
4809 for (i = 0; i < 8; i++)
4810 rt2800_clear_beacon_register(rt2x00dev, i);
4811
4812 if (rt2x00_is_usb(rt2x00dev)) {
4813 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
4814 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
4815 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
4816 } else if (rt2x00_is_pcie(rt2x00dev)) {
4817 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
4818 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
4819 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
4820 }
4821
4822 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
4823 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
4824 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
4825 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
4826 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
4827 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
4828 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
4829 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
4830 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
4831 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
4832
4833 rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
4834 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
4835 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
4836 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
4837 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
4838 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
4839 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
4840 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
4841 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
4842 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
4843
4844 rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
4845 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
4846 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
4847 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
4848 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
4849 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
4850 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
4851 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
4852 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
4853 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
4854
4855 rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
4856 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
4857 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
4858 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
4859 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
4860 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
4861
4862 /*
4863 * Do not force the BA window size, we use the TXWI to set it
4864 */
4865 rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, &reg);
4866 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
4867 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
4868 rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
4869
4870 /*
4871 * We must clear the error counters.
4872 * These registers are cleared on read,
4873 * so we may pass a useless variable to store the value.
4874 */
4875 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
4876 rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
4877 rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
4878 rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
4879 rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
4880 rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
4881
4882 /*
4883 * Setup leadtime for pre tbtt interrupt to 6ms
4884 */
4885 rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
4886 rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
4887 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
4888
4889 /*
4890 * Set up channel statistics timer
4891 */
4892 rt2800_register_read(rt2x00dev, CH_TIME_CFG, &reg);
4893 rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
4894 rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
4895 rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
4896 rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
4897 rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
4898 rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
4899
4900 return 0;
4901 }
4902
4903 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
4904 {
4905 unsigned int i;
4906 u32 reg;
4907
4908 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
4909 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
4910 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
4911 return 0;
4912
4913 udelay(REGISTER_BUSY_DELAY);
4914 }
4915
4916 rt2x00_err(rt2x00dev, "BBP/RF register access failed, aborting\n");
4917 return -EACCES;
4918 }
4919
4920 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
4921 {
4922 unsigned int i;
4923 u8 value;
4924
4925 /*
4926 * BBP was enabled after firmware was loaded,
4927 * but we need to reactivate it now.
4928 */
4929 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
4930 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
4931 msleep(1);
4932
4933 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
4934 rt2800_bbp_read(rt2x00dev, 0, &value);
4935 if ((value != 0xff) && (value != 0x00))
4936 return 0;
4937 udelay(REGISTER_BUSY_DELAY);
4938 }
4939
4940 rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n");
4941 return -EACCES;
4942 }
4943
4944 static void rt2800_bbp4_mac_if_ctrl(struct rt2x00_dev *rt2x00dev)
4945 {
4946 u8 value;
4947
4948 rt2800_bbp_read(rt2x00dev, 4, &value);
4949 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
4950 rt2800_bbp_write(rt2x00dev, 4, value);
4951 }
4952
4953 static void rt2800_init_freq_calibration(struct rt2x00_dev *rt2x00dev)
4954 {
4955 rt2800_bbp_write(rt2x00dev, 142, 1);
4956 rt2800_bbp_write(rt2x00dev, 143, 57);
4957 }
4958
4959 static void rt2800_init_bbp_5592_glrt(struct rt2x00_dev *rt2x00dev)
4960 {
4961 const u8 glrt_table[] = {
4962 0xE0, 0x1F, 0X38, 0x32, 0x08, 0x28, 0x19, 0x0A, 0xFF, 0x00, /* 128 ~ 137 */
4963 0x16, 0x10, 0x10, 0x0B, 0x36, 0x2C, 0x26, 0x24, 0x42, 0x36, /* 138 ~ 147 */
4964 0x30, 0x2D, 0x4C, 0x46, 0x3D, 0x40, 0x3E, 0x42, 0x3D, 0x40, /* 148 ~ 157 */
4965 0X3C, 0x34, 0x2C, 0x2F, 0x3C, 0x35, 0x2E, 0x2A, 0x49, 0x41, /* 158 ~ 167 */
4966 0x36, 0x31, 0x30, 0x30, 0x0E, 0x0D, 0x28, 0x21, 0x1C, 0x16, /* 168 ~ 177 */
4967 0x50, 0x4A, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, /* 178 ~ 187 */
4968 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 188 ~ 197 */
4969 0x00, 0x00, 0x7D, 0x14, 0x32, 0x2C, 0x36, 0x4C, 0x43, 0x2C, /* 198 ~ 207 */
4970 0x2E, 0x36, 0x30, 0x6E, /* 208 ~ 211 */
4971 };
4972 int i;
4973
4974 for (i = 0; i < ARRAY_SIZE(glrt_table); i++) {
4975 rt2800_bbp_write(rt2x00dev, 195, 128 + i);
4976 rt2800_bbp_write(rt2x00dev, 196, glrt_table[i]);
4977 }
4978 };
4979
4980 static void rt2800_init_bbp_early(struct rt2x00_dev *rt2x00dev)
4981 {
4982 rt2800_bbp_write(rt2x00dev, 65, 0x2C);
4983 rt2800_bbp_write(rt2x00dev, 66, 0x38);
4984 rt2800_bbp_write(rt2x00dev, 68, 0x0B);
4985 rt2800_bbp_write(rt2x00dev, 69, 0x12);
4986 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
4987 rt2800_bbp_write(rt2x00dev, 73, 0x10);
4988 rt2800_bbp_write(rt2x00dev, 81, 0x37);
4989 rt2800_bbp_write(rt2x00dev, 82, 0x62);
4990 rt2800_bbp_write(rt2x00dev, 83, 0x6A);
4991 rt2800_bbp_write(rt2x00dev, 84, 0x99);
4992 rt2800_bbp_write(rt2x00dev, 86, 0x00);
4993 rt2800_bbp_write(rt2x00dev, 91, 0x04);
4994 rt2800_bbp_write(rt2x00dev, 92, 0x00);
4995 rt2800_bbp_write(rt2x00dev, 103, 0x00);
4996 rt2800_bbp_write(rt2x00dev, 105, 0x05);
4997 rt2800_bbp_write(rt2x00dev, 106, 0x35);
4998 }
4999
5000 static void rt2800_disable_unused_dac_adc(struct rt2x00_dev *rt2x00dev)
5001 {
5002 u16 eeprom;
5003 u8 value;
5004
5005 rt2800_bbp_read(rt2x00dev, 138, &value);
5006 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
5007 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
5008 value |= 0x20;
5009 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
5010 value &= ~0x02;
5011 rt2800_bbp_write(rt2x00dev, 138, value);
5012 }
5013
5014 static void rt2800_init_bbp_305x_soc(struct rt2x00_dev *rt2x00dev)
5015 {
5016 rt2800_bbp_write(rt2x00dev, 31, 0x08);
5017
5018 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5019 rt2800_bbp_write(rt2x00dev, 66, 0x38);
5020
5021 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5022 rt2800_bbp_write(rt2x00dev, 73, 0x10);
5023
5024 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5025
5026 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
5027 rt2800_bbp_write(rt2x00dev, 80, 0x08);
5028
5029 rt2800_bbp_write(rt2x00dev, 82, 0x62);
5030
5031 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
5032
5033 rt2800_bbp_write(rt2x00dev, 84, 0x99);
5034
5035 rt2800_bbp_write(rt2x00dev, 86, 0x00);
5036
5037 rt2800_bbp_write(rt2x00dev, 91, 0x04);
5038
5039 rt2800_bbp_write(rt2x00dev, 92, 0x00);
5040
5041 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5042
5043 rt2800_bbp_write(rt2x00dev, 105, 0x01);
5044
5045 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5046 }
5047
5048 static void rt2800_init_bbp_28xx(struct rt2x00_dev *rt2x00dev)
5049 {
5050 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5051 rt2800_bbp_write(rt2x00dev, 66, 0x38);
5052
5053 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
5054 rt2800_bbp_write(rt2x00dev, 69, 0x16);
5055 rt2800_bbp_write(rt2x00dev, 73, 0x12);
5056 } else {
5057 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5058 rt2800_bbp_write(rt2x00dev, 73, 0x10);
5059 }
5060
5061 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5062
5063 rt2800_bbp_write(rt2x00dev, 81, 0x37);
5064
5065 rt2800_bbp_write(rt2x00dev, 82, 0x62);
5066
5067 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
5068
5069 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
5070 rt2800_bbp_write(rt2x00dev, 84, 0x19);
5071 else
5072 rt2800_bbp_write(rt2x00dev, 84, 0x99);
5073
5074 rt2800_bbp_write(rt2x00dev, 86, 0x00);
5075
5076 rt2800_bbp_write(rt2x00dev, 91, 0x04);
5077
5078 rt2800_bbp_write(rt2x00dev, 92, 0x00);
5079
5080 rt2800_bbp_write(rt2x00dev, 103, 0x00);
5081
5082 rt2800_bbp_write(rt2x00dev, 105, 0x05);
5083
5084 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5085 }
5086
5087 static void rt2800_init_bbp_30xx(struct rt2x00_dev *rt2x00dev)
5088 {
5089 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5090 rt2800_bbp_write(rt2x00dev, 66, 0x38);
5091
5092 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5093 rt2800_bbp_write(rt2x00dev, 73, 0x10);
5094
5095 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5096
5097 rt2800_bbp_write(rt2x00dev, 79, 0x13);
5098 rt2800_bbp_write(rt2x00dev, 80, 0x05);
5099 rt2800_bbp_write(rt2x00dev, 81, 0x33);
5100
5101 rt2800_bbp_write(rt2x00dev, 82, 0x62);
5102
5103 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
5104
5105 rt2800_bbp_write(rt2x00dev, 84, 0x99);
5106
5107 rt2800_bbp_write(rt2x00dev, 86, 0x00);
5108
5109 rt2800_bbp_write(rt2x00dev, 91, 0x04);
5110
5111 rt2800_bbp_write(rt2x00dev, 92, 0x00);
5112
5113 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
5114 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
5115 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E))
5116 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5117 else
5118 rt2800_bbp_write(rt2x00dev, 103, 0x00);
5119
5120 rt2800_bbp_write(rt2x00dev, 105, 0x05);
5121
5122 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5123
5124 if (rt2x00_rt(rt2x00dev, RT3071) ||
5125 rt2x00_rt(rt2x00dev, RT3090))
5126 rt2800_disable_unused_dac_adc(rt2x00dev);
5127 }
5128
5129 static void rt2800_init_bbp_3290(struct rt2x00_dev *rt2x00dev)
5130 {
5131 u8 value;
5132
5133 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5134
5135 rt2800_bbp_write(rt2x00dev, 31, 0x08);
5136
5137 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5138 rt2800_bbp_write(rt2x00dev, 66, 0x38);
5139
5140 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
5141
5142 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5143 rt2800_bbp_write(rt2x00dev, 73, 0x13);
5144 rt2800_bbp_write(rt2x00dev, 75, 0x46);
5145 rt2800_bbp_write(rt2x00dev, 76, 0x28);
5146
5147 rt2800_bbp_write(rt2x00dev, 77, 0x58);
5148
5149 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5150
5151 rt2800_bbp_write(rt2x00dev, 74, 0x0b);
5152 rt2800_bbp_write(rt2x00dev, 79, 0x18);
5153 rt2800_bbp_write(rt2x00dev, 80, 0x09);
5154 rt2800_bbp_write(rt2x00dev, 81, 0x33);
5155
5156 rt2800_bbp_write(rt2x00dev, 82, 0x62);
5157
5158 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
5159
5160 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
5161
5162 rt2800_bbp_write(rt2x00dev, 86, 0x38);
5163
5164 rt2800_bbp_write(rt2x00dev, 91, 0x04);
5165
5166 rt2800_bbp_write(rt2x00dev, 92, 0x02);
5167
5168 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5169
5170 rt2800_bbp_write(rt2x00dev, 104, 0x92);
5171
5172 rt2800_bbp_write(rt2x00dev, 105, 0x1c);
5173
5174 rt2800_bbp_write(rt2x00dev, 106, 0x03);
5175
5176 rt2800_bbp_write(rt2x00dev, 128, 0x12);
5177
5178 rt2800_bbp_write(rt2x00dev, 67, 0x24);
5179 rt2800_bbp_write(rt2x00dev, 143, 0x04);
5180 rt2800_bbp_write(rt2x00dev, 142, 0x99);
5181 rt2800_bbp_write(rt2x00dev, 150, 0x30);
5182 rt2800_bbp_write(rt2x00dev, 151, 0x2e);
5183 rt2800_bbp_write(rt2x00dev, 152, 0x20);
5184 rt2800_bbp_write(rt2x00dev, 153, 0x34);
5185 rt2800_bbp_write(rt2x00dev, 154, 0x40);
5186 rt2800_bbp_write(rt2x00dev, 155, 0x3b);
5187 rt2800_bbp_write(rt2x00dev, 253, 0x04);
5188
5189 rt2800_bbp_read(rt2x00dev, 47, &value);
5190 rt2x00_set_field8(&value, BBP47_TSSI_ADC6, 1);
5191 rt2800_bbp_write(rt2x00dev, 47, value);
5192
5193 /* Use 5-bit ADC for Acquisition and 8-bit ADC for data */
5194 rt2800_bbp_read(rt2x00dev, 3, &value);
5195 rt2x00_set_field8(&value, BBP3_ADC_MODE_SWITCH, 1);
5196 rt2x00_set_field8(&value, BBP3_ADC_INIT_MODE, 1);
5197 rt2800_bbp_write(rt2x00dev, 3, value);
5198 }
5199
5200 static void rt2800_init_bbp_3352(struct rt2x00_dev *rt2x00dev)
5201 {
5202 rt2800_bbp_write(rt2x00dev, 3, 0x00);
5203 rt2800_bbp_write(rt2x00dev, 4, 0x50);
5204
5205 rt2800_bbp_write(rt2x00dev, 31, 0x08);
5206
5207 rt2800_bbp_write(rt2x00dev, 47, 0x48);
5208
5209 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5210 rt2800_bbp_write(rt2x00dev, 66, 0x38);
5211
5212 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
5213
5214 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5215 rt2800_bbp_write(rt2x00dev, 73, 0x13);
5216 rt2800_bbp_write(rt2x00dev, 75, 0x46);
5217 rt2800_bbp_write(rt2x00dev, 76, 0x28);
5218
5219 rt2800_bbp_write(rt2x00dev, 77, 0x59);
5220
5221 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5222
5223 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
5224 rt2800_bbp_write(rt2x00dev, 80, 0x08);
5225 rt2800_bbp_write(rt2x00dev, 81, 0x37);
5226
5227 rt2800_bbp_write(rt2x00dev, 82, 0x62);
5228
5229 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
5230
5231 rt2800_bbp_write(rt2x00dev, 84, 0x99);
5232
5233 rt2800_bbp_write(rt2x00dev, 86, 0x38);
5234
5235 rt2800_bbp_write(rt2x00dev, 88, 0x90);
5236
5237 rt2800_bbp_write(rt2x00dev, 91, 0x04);
5238
5239 rt2800_bbp_write(rt2x00dev, 92, 0x02);
5240
5241 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5242
5243 rt2800_bbp_write(rt2x00dev, 104, 0x92);
5244
5245 rt2800_bbp_write(rt2x00dev, 105, 0x34);
5246
5247 rt2800_bbp_write(rt2x00dev, 106, 0x05);
5248
5249 rt2800_bbp_write(rt2x00dev, 120, 0x50);
5250
5251 rt2800_bbp_write(rt2x00dev, 137, 0x0f);
5252
5253 rt2800_bbp_write(rt2x00dev, 163, 0xbd);
5254 /* Set ITxBF timeout to 0x9c40=1000msec */
5255 rt2800_bbp_write(rt2x00dev, 179, 0x02);
5256 rt2800_bbp_write(rt2x00dev, 180, 0x00);
5257 rt2800_bbp_write(rt2x00dev, 182, 0x40);
5258 rt2800_bbp_write(rt2x00dev, 180, 0x01);
5259 rt2800_bbp_write(rt2x00dev, 182, 0x9c);
5260 rt2800_bbp_write(rt2x00dev, 179, 0x00);
5261 /* Reprogram the inband interface to put right values in RXWI */
5262 rt2800_bbp_write(rt2x00dev, 142, 0x04);
5263 rt2800_bbp_write(rt2x00dev, 143, 0x3b);
5264 rt2800_bbp_write(rt2x00dev, 142, 0x06);
5265 rt2800_bbp_write(rt2x00dev, 143, 0xa0);
5266 rt2800_bbp_write(rt2x00dev, 142, 0x07);
5267 rt2800_bbp_write(rt2x00dev, 143, 0xa1);
5268 rt2800_bbp_write(rt2x00dev, 142, 0x08);
5269 rt2800_bbp_write(rt2x00dev, 143, 0xa2);
5270
5271 rt2800_bbp_write(rt2x00dev, 148, 0xc8);
5272 }
5273
5274 static void rt2800_init_bbp_3390(struct rt2x00_dev *rt2x00dev)
5275 {
5276 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5277 rt2800_bbp_write(rt2x00dev, 66, 0x38);
5278
5279 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5280 rt2800_bbp_write(rt2x00dev, 73, 0x10);
5281
5282 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5283
5284 rt2800_bbp_write(rt2x00dev, 79, 0x13);
5285 rt2800_bbp_write(rt2x00dev, 80, 0x05);
5286 rt2800_bbp_write(rt2x00dev, 81, 0x33);
5287
5288 rt2800_bbp_write(rt2x00dev, 82, 0x62);
5289
5290 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
5291
5292 rt2800_bbp_write(rt2x00dev, 84, 0x99);
5293
5294 rt2800_bbp_write(rt2x00dev, 86, 0x00);
5295
5296 rt2800_bbp_write(rt2x00dev, 91, 0x04);
5297
5298 rt2800_bbp_write(rt2x00dev, 92, 0x00);
5299
5300 if (rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E))
5301 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5302 else
5303 rt2800_bbp_write(rt2x00dev, 103, 0x00);
5304
5305 rt2800_bbp_write(rt2x00dev, 105, 0x05);
5306
5307 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5308
5309 rt2800_disable_unused_dac_adc(rt2x00dev);
5310 }
5311
5312 static void rt2800_init_bbp_3572(struct rt2x00_dev *rt2x00dev)
5313 {
5314 rt2800_bbp_write(rt2x00dev, 31, 0x08);
5315
5316 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5317 rt2800_bbp_write(rt2x00dev, 66, 0x38);
5318
5319 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5320 rt2800_bbp_write(rt2x00dev, 73, 0x10);
5321
5322 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5323
5324 rt2800_bbp_write(rt2x00dev, 79, 0x13);
5325 rt2800_bbp_write(rt2x00dev, 80, 0x05);
5326 rt2800_bbp_write(rt2x00dev, 81, 0x33);
5327
5328 rt2800_bbp_write(rt2x00dev, 82, 0x62);
5329
5330 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
5331
5332 rt2800_bbp_write(rt2x00dev, 84, 0x99);
5333
5334 rt2800_bbp_write(rt2x00dev, 86, 0x00);
5335
5336 rt2800_bbp_write(rt2x00dev, 91, 0x04);
5337
5338 rt2800_bbp_write(rt2x00dev, 92, 0x00);
5339
5340 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5341
5342 rt2800_bbp_write(rt2x00dev, 105, 0x05);
5343
5344 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5345
5346 rt2800_disable_unused_dac_adc(rt2x00dev);
5347 }
5348
5349 static void rt2800_init_bbp_3593(struct rt2x00_dev *rt2x00dev)
5350 {
5351 rt2800_init_bbp_early(rt2x00dev);
5352
5353 rt2800_bbp_write(rt2x00dev, 79, 0x13);
5354 rt2800_bbp_write(rt2x00dev, 80, 0x05);
5355 rt2800_bbp_write(rt2x00dev, 81, 0x33);
5356 rt2800_bbp_write(rt2x00dev, 137, 0x0f);
5357
5358 rt2800_bbp_write(rt2x00dev, 84, 0x19);
5359
5360 /* Enable DC filter */
5361 if (rt2x00_rt_rev_gte(rt2x00dev, RT3593, REV_RT3593E))
5362 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5363 }
5364
5365 static void rt2800_init_bbp_53xx(struct rt2x00_dev *rt2x00dev)
5366 {
5367 int ant, div_mode;
5368 u16 eeprom;
5369 u8 value;
5370
5371 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5372
5373 rt2800_bbp_write(rt2x00dev, 31, 0x08);
5374
5375 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5376 rt2800_bbp_write(rt2x00dev, 66, 0x38);
5377
5378 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
5379
5380 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5381 rt2800_bbp_write(rt2x00dev, 73, 0x13);
5382 rt2800_bbp_write(rt2x00dev, 75, 0x46);
5383 rt2800_bbp_write(rt2x00dev, 76, 0x28);
5384
5385 rt2800_bbp_write(rt2x00dev, 77, 0x59);
5386
5387 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5388
5389 rt2800_bbp_write(rt2x00dev, 79, 0x13);
5390 rt2800_bbp_write(rt2x00dev, 80, 0x05);
5391 rt2800_bbp_write(rt2x00dev, 81, 0x33);
5392
5393 rt2800_bbp_write(rt2x00dev, 82, 0x62);
5394
5395 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
5396
5397 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
5398
5399 rt2800_bbp_write(rt2x00dev, 86, 0x38);
5400
5401 if (rt2x00_rt(rt2x00dev, RT5392))
5402 rt2800_bbp_write(rt2x00dev, 88, 0x90);
5403
5404 rt2800_bbp_write(rt2x00dev, 91, 0x04);
5405
5406 rt2800_bbp_write(rt2x00dev, 92, 0x02);
5407
5408 if (rt2x00_rt(rt2x00dev, RT5392)) {
5409 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
5410 rt2800_bbp_write(rt2x00dev, 98, 0x12);
5411 }
5412
5413 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5414
5415 rt2800_bbp_write(rt2x00dev, 104, 0x92);
5416
5417 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
5418
5419 if (rt2x00_rt(rt2x00dev, RT5390))
5420 rt2800_bbp_write(rt2x00dev, 106, 0x03);
5421 else if (rt2x00_rt(rt2x00dev, RT5392))
5422 rt2800_bbp_write(rt2x00dev, 106, 0x12);
5423 else
5424 WARN_ON(1);
5425
5426 rt2800_bbp_write(rt2x00dev, 128, 0x12);
5427
5428 if (rt2x00_rt(rt2x00dev, RT5392)) {
5429 rt2800_bbp_write(rt2x00dev, 134, 0xd0);
5430 rt2800_bbp_write(rt2x00dev, 135, 0xf6);
5431 }
5432
5433 rt2800_disable_unused_dac_adc(rt2x00dev);
5434
5435 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
5436 div_mode = rt2x00_get_field16(eeprom,
5437 EEPROM_NIC_CONF1_ANT_DIVERSITY);
5438 ant = (div_mode == 3) ? 1 : 0;
5439
5440 /* check if this is a Bluetooth combo card */
5441 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
5442 u32 reg;
5443
5444 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
5445 rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
5446 rt2x00_set_field32(&reg, GPIO_CTRL_DIR6, 0);
5447 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 0);
5448 rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 0);
5449 if (ant == 0)
5450 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 1);
5451 else if (ant == 1)
5452 rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 1);
5453 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
5454 }
5455
5456 /* This chip has hardware antenna diversity*/
5457 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
5458 rt2800_bbp_write(rt2x00dev, 150, 0); /* Disable Antenna Software OFDM */
5459 rt2800_bbp_write(rt2x00dev, 151, 0); /* Disable Antenna Software CCK */
5460 rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */
5461 }
5462
5463 rt2800_bbp_read(rt2x00dev, 152, &value);
5464 if (ant == 0)
5465 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
5466 else
5467 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
5468 rt2800_bbp_write(rt2x00dev, 152, value);
5469
5470 rt2800_init_freq_calibration(rt2x00dev);
5471 }
5472
5473 static void rt2800_init_bbp_5592(struct rt2x00_dev *rt2x00dev)
5474 {
5475 int ant, div_mode;
5476 u16 eeprom;
5477 u8 value;
5478
5479 rt2800_init_bbp_early(rt2x00dev);
5480
5481 rt2800_bbp_read(rt2x00dev, 105, &value);
5482 rt2x00_set_field8(&value, BBP105_MLD,
5483 rt2x00dev->default_ant.rx_chain_num == 2);
5484 rt2800_bbp_write(rt2x00dev, 105, value);
5485
5486 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5487
5488 rt2800_bbp_write(rt2x00dev, 20, 0x06);
5489 rt2800_bbp_write(rt2x00dev, 31, 0x08);
5490 rt2800_bbp_write(rt2x00dev, 65, 0x2C);
5491 rt2800_bbp_write(rt2x00dev, 68, 0xDD);
5492 rt2800_bbp_write(rt2x00dev, 69, 0x1A);
5493 rt2800_bbp_write(rt2x00dev, 70, 0x05);
5494 rt2800_bbp_write(rt2x00dev, 73, 0x13);
5495 rt2800_bbp_write(rt2x00dev, 74, 0x0F);
5496 rt2800_bbp_write(rt2x00dev, 75, 0x4F);
5497 rt2800_bbp_write(rt2x00dev, 76, 0x28);
5498 rt2800_bbp_write(rt2x00dev, 77, 0x59);
5499 rt2800_bbp_write(rt2x00dev, 84, 0x9A);
5500 rt2800_bbp_write(rt2x00dev, 86, 0x38);
5501 rt2800_bbp_write(rt2x00dev, 88, 0x90);
5502 rt2800_bbp_write(rt2x00dev, 91, 0x04);
5503 rt2800_bbp_write(rt2x00dev, 92, 0x02);
5504 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
5505 rt2800_bbp_write(rt2x00dev, 98, 0x12);
5506 rt2800_bbp_write(rt2x00dev, 103, 0xC0);
5507 rt2800_bbp_write(rt2x00dev, 104, 0x92);
5508 /* FIXME BBP105 owerwrite */
5509 rt2800_bbp_write(rt2x00dev, 105, 0x3C);
5510 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5511 rt2800_bbp_write(rt2x00dev, 128, 0x12);
5512 rt2800_bbp_write(rt2x00dev, 134, 0xD0);
5513 rt2800_bbp_write(rt2x00dev, 135, 0xF6);
5514 rt2800_bbp_write(rt2x00dev, 137, 0x0F);
5515
5516 /* Initialize GLRT (Generalized Likehood Radio Test) */
5517 rt2800_init_bbp_5592_glrt(rt2x00dev);
5518
5519 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5520
5521 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
5522 div_mode = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_ANT_DIVERSITY);
5523 ant = (div_mode == 3) ? 1 : 0;
5524 rt2800_bbp_read(rt2x00dev, 152, &value);
5525 if (ant == 0) {
5526 /* Main antenna */
5527 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
5528 } else {
5529 /* Auxiliary antenna */
5530 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
5531 }
5532 rt2800_bbp_write(rt2x00dev, 152, value);
5533
5534 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) {
5535 rt2800_bbp_read(rt2x00dev, 254, &value);
5536 rt2x00_set_field8(&value, BBP254_BIT7, 1);
5537 rt2800_bbp_write(rt2x00dev, 254, value);
5538 }
5539
5540 rt2800_init_freq_calibration(rt2x00dev);
5541
5542 rt2800_bbp_write(rt2x00dev, 84, 0x19);
5543 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
5544 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5545 }
5546
5547 static void rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
5548 {
5549 unsigned int i;
5550 u16 eeprom;
5551 u8 reg_id;
5552 u8 value;
5553
5554 if (rt2800_is_305x_soc(rt2x00dev))
5555 rt2800_init_bbp_305x_soc(rt2x00dev);
5556
5557 switch (rt2x00dev->chip.rt) {
5558 case RT2860:
5559 case RT2872:
5560 case RT2883:
5561 rt2800_init_bbp_28xx(rt2x00dev);
5562 break;
5563 case RT3070:
5564 case RT3071:
5565 case RT3090:
5566 rt2800_init_bbp_30xx(rt2x00dev);
5567 break;
5568 case RT3290:
5569 rt2800_init_bbp_3290(rt2x00dev);
5570 break;
5571 case RT3352:
5572 rt2800_init_bbp_3352(rt2x00dev);
5573 break;
5574 case RT3390:
5575 rt2800_init_bbp_3390(rt2x00dev);
5576 break;
5577 case RT3572:
5578 rt2800_init_bbp_3572(rt2x00dev);
5579 break;
5580 case RT3593:
5581 rt2800_init_bbp_3593(rt2x00dev);
5582 return;
5583 case RT5390:
5584 case RT5392:
5585 rt2800_init_bbp_53xx(rt2x00dev);
5586 break;
5587 case RT5592:
5588 rt2800_init_bbp_5592(rt2x00dev);
5589 return;
5590 }
5591
5592 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
5593 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_BBP_START, i,
5594 &eeprom);
5595
5596 if (eeprom != 0xffff && eeprom != 0x0000) {
5597 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
5598 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
5599 rt2800_bbp_write(rt2x00dev, reg_id, value);
5600 }
5601 }
5602 }
5603
5604 static void rt2800_led_open_drain_enable(struct rt2x00_dev *rt2x00dev)
5605 {
5606 u32 reg;
5607
5608 rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
5609 rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
5610 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
5611 }
5612
5613 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev, bool bw40,
5614 u8 filter_target)
5615 {
5616 unsigned int i;
5617 u8 bbp;
5618 u8 rfcsr;
5619 u8 passband;
5620 u8 stopband;
5621 u8 overtuned = 0;
5622 u8 rfcsr24 = (bw40) ? 0x27 : 0x07;
5623
5624 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
5625
5626 rt2800_bbp_read(rt2x00dev, 4, &bbp);
5627 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
5628 rt2800_bbp_write(rt2x00dev, 4, bbp);
5629
5630 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
5631 rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
5632 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
5633
5634 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
5635 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
5636 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
5637
5638 /*
5639 * Set power & frequency of passband test tone
5640 */
5641 rt2800_bbp_write(rt2x00dev, 24, 0);
5642
5643 for (i = 0; i < 100; i++) {
5644 rt2800_bbp_write(rt2x00dev, 25, 0x90);
5645 msleep(1);
5646
5647 rt2800_bbp_read(rt2x00dev, 55, &passband);
5648 if (passband)
5649 break;
5650 }
5651
5652 /*
5653 * Set power & frequency of stopband test tone
5654 */
5655 rt2800_bbp_write(rt2x00dev, 24, 0x06);
5656
5657 for (i = 0; i < 100; i++) {
5658 rt2800_bbp_write(rt2x00dev, 25, 0x90);
5659 msleep(1);
5660
5661 rt2800_bbp_read(rt2x00dev, 55, &stopband);
5662
5663 if ((passband - stopband) <= filter_target) {
5664 rfcsr24++;
5665 overtuned += ((passband - stopband) == filter_target);
5666 } else
5667 break;
5668
5669 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
5670 }
5671
5672 rfcsr24 -= !!overtuned;
5673
5674 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
5675 return rfcsr24;
5676 }
5677
5678 static void rt2800_rf_init_calibration(struct rt2x00_dev *rt2x00dev,
5679 const unsigned int rf_reg)
5680 {
5681 u8 rfcsr;
5682
5683 rt2800_rfcsr_read(rt2x00dev, rf_reg, &rfcsr);
5684 rt2x00_set_field8(&rfcsr, FIELD8(0x80), 1);
5685 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
5686 msleep(1);
5687 rt2x00_set_field8(&rfcsr, FIELD8(0x80), 0);
5688 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
5689 }
5690
5691 static void rt2800_rx_filter_calibration(struct rt2x00_dev *rt2x00dev)
5692 {
5693 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5694 u8 filter_tgt_bw20;
5695 u8 filter_tgt_bw40;
5696 u8 rfcsr, bbp;
5697
5698 /*
5699 * TODO: sync filter_tgt values with vendor driver
5700 */
5701 if (rt2x00_rt(rt2x00dev, RT3070)) {
5702 filter_tgt_bw20 = 0x16;
5703 filter_tgt_bw40 = 0x19;
5704 } else {
5705 filter_tgt_bw20 = 0x13;
5706 filter_tgt_bw40 = 0x15;
5707 }
5708
5709 drv_data->calibration_bw20 =
5710 rt2800_init_rx_filter(rt2x00dev, false, filter_tgt_bw20);
5711 drv_data->calibration_bw40 =
5712 rt2800_init_rx_filter(rt2x00dev, true, filter_tgt_bw40);
5713
5714 /*
5715 * Save BBP 25 & 26 values for later use in channel switching (for 3052)
5716 */
5717 rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25);
5718 rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26);
5719
5720 /*
5721 * Set back to initial state
5722 */
5723 rt2800_bbp_write(rt2x00dev, 24, 0);
5724
5725 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
5726 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
5727 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
5728
5729 /*
5730 * Set BBP back to BW20
5731 */
5732 rt2800_bbp_read(rt2x00dev, 4, &bbp);
5733 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
5734 rt2800_bbp_write(rt2x00dev, 4, bbp);
5735 }
5736
5737 static void rt2800_normal_mode_setup_3xxx(struct rt2x00_dev *rt2x00dev)
5738 {
5739 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5740 u8 min_gain, rfcsr, bbp;
5741 u16 eeprom;
5742
5743 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
5744
5745 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
5746 if (rt2x00_rt(rt2x00dev, RT3070) ||
5747 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
5748 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
5749 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
5750 if (!test_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags))
5751 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
5752 }
5753
5754 min_gain = rt2x00_rt(rt2x00dev, RT3070) ? 1 : 2;
5755 if (drv_data->txmixer_gain_24g >= min_gain) {
5756 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
5757 drv_data->txmixer_gain_24g);
5758 }
5759
5760 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
5761
5762 if (rt2x00_rt(rt2x00dev, RT3090)) {
5763 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
5764 rt2800_bbp_read(rt2x00dev, 138, &bbp);
5765 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
5766 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
5767 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
5768 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
5769 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
5770 rt2800_bbp_write(rt2x00dev, 138, bbp);
5771 }
5772
5773 if (rt2x00_rt(rt2x00dev, RT3070)) {
5774 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
5775 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
5776 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
5777 else
5778 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
5779 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
5780 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
5781 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
5782 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
5783 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
5784 rt2x00_rt(rt2x00dev, RT3090) ||
5785 rt2x00_rt(rt2x00dev, RT3390)) {
5786 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
5787 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
5788 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
5789 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
5790 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
5791 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
5792 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
5793
5794 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
5795 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
5796 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
5797
5798 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
5799 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
5800 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
5801
5802 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
5803 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
5804 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
5805 }
5806 }
5807
5808 static void rt2800_normal_mode_setup_3593(struct rt2x00_dev *rt2x00dev)
5809 {
5810 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5811 u8 rfcsr;
5812 u8 tx_gain;
5813
5814 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
5815 rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO2_EN, 0);
5816 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
5817
5818 rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr);
5819 tx_gain = rt2x00_get_field8(drv_data->txmixer_gain_24g,
5820 RFCSR17_TXMIXER_GAIN);
5821 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, tx_gain);
5822 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
5823
5824 rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr);
5825 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
5826 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
5827
5828 rt2800_rfcsr_read(rt2x00dev, 39, &rfcsr);
5829 rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
5830 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
5831
5832 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
5833 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
5834 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
5835 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
5836
5837 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
5838 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
5839 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
5840
5841 /* TODO: enable stream mode */
5842 }
5843
5844 static void rt2800_normal_mode_setup_5xxx(struct rt2x00_dev *rt2x00dev)
5845 {
5846 u8 reg;
5847 u16 eeprom;
5848
5849 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
5850 rt2800_bbp_read(rt2x00dev, 138, &reg);
5851 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
5852 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
5853 rt2x00_set_field8(&reg, BBP138_RX_ADC1, 0);
5854 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
5855 rt2x00_set_field8(&reg, BBP138_TX_DAC1, 1);
5856 rt2800_bbp_write(rt2x00dev, 138, reg);
5857
5858 rt2800_rfcsr_read(rt2x00dev, 38, &reg);
5859 rt2x00_set_field8(&reg, RFCSR38_RX_LO1_EN, 0);
5860 rt2800_rfcsr_write(rt2x00dev, 38, reg);
5861
5862 rt2800_rfcsr_read(rt2x00dev, 39, &reg);
5863 rt2x00_set_field8(&reg, RFCSR39_RX_LO2_EN, 0);
5864 rt2800_rfcsr_write(rt2x00dev, 39, reg);
5865
5866 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5867
5868 rt2800_rfcsr_read(rt2x00dev, 30, &reg);
5869 rt2x00_set_field8(&reg, RFCSR30_RX_VCM, 2);
5870 rt2800_rfcsr_write(rt2x00dev, 30, reg);
5871 }
5872
5873 static void rt2800_init_rfcsr_305x_soc(struct rt2x00_dev *rt2x00dev)
5874 {
5875 rt2800_rf_init_calibration(rt2x00dev, 30);
5876
5877 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
5878 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
5879 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
5880 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
5881 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
5882 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
5883 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
5884 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
5885 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
5886 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
5887 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
5888 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
5889 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
5890 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
5891 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
5892 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
5893 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
5894 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
5895 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
5896 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
5897 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
5898 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
5899 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
5900 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
5901 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
5902 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
5903 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
5904 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
5905 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
5906 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
5907 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
5908 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
5909 }
5910
5911 static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev)
5912 {
5913 u8 rfcsr;
5914 u16 eeprom;
5915 u32 reg;
5916
5917 /* XXX vendor driver do this only for 3070 */
5918 rt2800_rf_init_calibration(rt2x00dev, 30);
5919
5920 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
5921 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
5922 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
5923 rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
5924 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
5925 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
5926 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
5927 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
5928 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
5929 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
5930 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
5931 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
5932 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
5933 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
5934 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
5935 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
5936 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
5937 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
5938 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
5939
5940 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
5941 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
5942 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
5943 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
5944 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
5945 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
5946 rt2x00_rt(rt2x00dev, RT3090)) {
5947 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
5948
5949 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
5950 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
5951 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
5952
5953 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
5954 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
5955 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
5956 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
5957 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1,
5958 &eeprom);
5959 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
5960 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
5961 else
5962 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
5963 }
5964 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
5965
5966 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
5967 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
5968 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
5969 }
5970
5971 rt2800_rx_filter_calibration(rt2x00dev);
5972
5973 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
5974 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
5975 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E))
5976 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
5977
5978 rt2800_led_open_drain_enable(rt2x00dev);
5979 rt2800_normal_mode_setup_3xxx(rt2x00dev);
5980 }
5981
5982 static void rt2800_init_rfcsr_3290(struct rt2x00_dev *rt2x00dev)
5983 {
5984 u8 rfcsr;
5985
5986 rt2800_rf_init_calibration(rt2x00dev, 2);
5987
5988 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
5989 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
5990 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
5991 rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
5992 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
5993 rt2800_rfcsr_write(rt2x00dev, 8, 0xf3);
5994 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
5995 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
5996 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
5997 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
5998 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
5999 rt2800_rfcsr_write(rt2x00dev, 18, 0x02);
6000 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
6001 rt2800_rfcsr_write(rt2x00dev, 25, 0x83);
6002 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
6003 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
6004 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
6005 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
6006 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6007 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
6008 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
6009 rt2800_rfcsr_write(rt2x00dev, 34, 0x05);
6010 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
6011 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
6012 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
6013 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
6014 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
6015 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
6016 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
6017 rt2800_rfcsr_write(rt2x00dev, 43, 0x7b);
6018 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
6019 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
6020 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
6021 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
6022 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
6023 rt2800_rfcsr_write(rt2x00dev, 49, 0x98);
6024 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
6025 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
6026 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
6027 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
6028 rt2800_rfcsr_write(rt2x00dev, 56, 0x02);
6029 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
6030 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
6031 rt2800_rfcsr_write(rt2x00dev, 59, 0x09);
6032 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
6033 rt2800_rfcsr_write(rt2x00dev, 61, 0xc1);
6034
6035 rt2800_rfcsr_read(rt2x00dev, 29, &rfcsr);
6036 rt2x00_set_field8(&rfcsr, RFCSR29_RSSI_GAIN, 3);
6037 rt2800_rfcsr_write(rt2x00dev, 29, rfcsr);
6038
6039 rt2800_led_open_drain_enable(rt2x00dev);
6040 rt2800_normal_mode_setup_3xxx(rt2x00dev);
6041 }
6042
6043 static void rt2800_init_rfcsr_3352(struct rt2x00_dev *rt2x00dev)
6044 {
6045 rt2800_rf_init_calibration(rt2x00dev, 30);
6046
6047 rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
6048 rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
6049 rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
6050 rt2800_rfcsr_write(rt2x00dev, 3, 0x18);
6051 rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
6052 rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
6053 rt2800_rfcsr_write(rt2x00dev, 6, 0x33);
6054 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
6055 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
6056 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
6057 rt2800_rfcsr_write(rt2x00dev, 10, 0xd2);
6058 rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
6059 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
6060 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
6061 rt2800_rfcsr_write(rt2x00dev, 14, 0x5a);
6062 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
6063 rt2800_rfcsr_write(rt2x00dev, 16, 0x01);
6064 rt2800_rfcsr_write(rt2x00dev, 18, 0x45);
6065 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
6066 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
6067 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
6068 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
6069 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
6070 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
6071 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
6072 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
6073 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
6074 rt2800_rfcsr_write(rt2x00dev, 28, 0x03);
6075 rt2800_rfcsr_write(rt2x00dev, 29, 0x00);
6076 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
6077 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6078 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
6079 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
6080 rt2800_rfcsr_write(rt2x00dev, 34, 0x01);
6081 rt2800_rfcsr_write(rt2x00dev, 35, 0x03);
6082 rt2800_rfcsr_write(rt2x00dev, 36, 0xbd);
6083 rt2800_rfcsr_write(rt2x00dev, 37, 0x3c);
6084 rt2800_rfcsr_write(rt2x00dev, 38, 0x5f);
6085 rt2800_rfcsr_write(rt2x00dev, 39, 0xc5);
6086 rt2800_rfcsr_write(rt2x00dev, 40, 0x33);
6087 rt2800_rfcsr_write(rt2x00dev, 41, 0x5b);
6088 rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
6089 rt2800_rfcsr_write(rt2x00dev, 43, 0xdb);
6090 rt2800_rfcsr_write(rt2x00dev, 44, 0xdb);
6091 rt2800_rfcsr_write(rt2x00dev, 45, 0xdb);
6092 rt2800_rfcsr_write(rt2x00dev, 46, 0xdd);
6093 rt2800_rfcsr_write(rt2x00dev, 47, 0x0d);
6094 rt2800_rfcsr_write(rt2x00dev, 48, 0x14);
6095 rt2800_rfcsr_write(rt2x00dev, 49, 0x00);
6096 rt2800_rfcsr_write(rt2x00dev, 50, 0x2d);
6097 rt2800_rfcsr_write(rt2x00dev, 51, 0x7f);
6098 rt2800_rfcsr_write(rt2x00dev, 52, 0x00);
6099 rt2800_rfcsr_write(rt2x00dev, 53, 0x52);
6100 rt2800_rfcsr_write(rt2x00dev, 54, 0x1b);
6101 rt2800_rfcsr_write(rt2x00dev, 55, 0x7f);
6102 rt2800_rfcsr_write(rt2x00dev, 56, 0x00);
6103 rt2800_rfcsr_write(rt2x00dev, 57, 0x52);
6104 rt2800_rfcsr_write(rt2x00dev, 58, 0x1b);
6105 rt2800_rfcsr_write(rt2x00dev, 59, 0x00);
6106 rt2800_rfcsr_write(rt2x00dev, 60, 0x00);
6107 rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
6108 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
6109 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
6110
6111 rt2800_rx_filter_calibration(rt2x00dev);
6112 rt2800_led_open_drain_enable(rt2x00dev);
6113 rt2800_normal_mode_setup_3xxx(rt2x00dev);
6114 }
6115
6116 static void rt2800_init_rfcsr_3390(struct rt2x00_dev *rt2x00dev)
6117 {
6118 u32 reg;
6119
6120 rt2800_rf_init_calibration(rt2x00dev, 30);
6121
6122 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
6123 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
6124 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
6125 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
6126 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
6127 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
6128 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
6129 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
6130 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
6131 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
6132 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
6133 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
6134 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
6135 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
6136 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
6137 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
6138 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
6139 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
6140 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
6141 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
6142 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
6143 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
6144 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
6145 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
6146 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
6147 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
6148 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
6149 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
6150 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
6151 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
6152 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
6153 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
6154
6155 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
6156 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
6157 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
6158
6159 rt2800_rx_filter_calibration(rt2x00dev);
6160
6161 if (rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
6162 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
6163
6164 rt2800_led_open_drain_enable(rt2x00dev);
6165 rt2800_normal_mode_setup_3xxx(rt2x00dev);
6166 }
6167
6168 static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev)
6169 {
6170 u8 rfcsr;
6171 u32 reg;
6172
6173 rt2800_rf_init_calibration(rt2x00dev, 30);
6174
6175 rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
6176 rt2800_rfcsr_write(rt2x00dev, 1, 0x81);
6177 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
6178 rt2800_rfcsr_write(rt2x00dev, 3, 0x02);
6179 rt2800_rfcsr_write(rt2x00dev, 4, 0x4c);
6180 rt2800_rfcsr_write(rt2x00dev, 5, 0x05);
6181 rt2800_rfcsr_write(rt2x00dev, 6, 0x4a);
6182 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
6183 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
6184 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
6185 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
6186 rt2800_rfcsr_write(rt2x00dev, 12, 0x70);
6187 rt2800_rfcsr_write(rt2x00dev, 13, 0x65);
6188 rt2800_rfcsr_write(rt2x00dev, 14, 0xa0);
6189 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
6190 rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
6191 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
6192 rt2800_rfcsr_write(rt2x00dev, 18, 0xac);
6193 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
6194 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
6195 rt2800_rfcsr_write(rt2x00dev, 21, 0xd0);
6196 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
6197 rt2800_rfcsr_write(rt2x00dev, 23, 0x3c);
6198 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
6199 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
6200 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
6201 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
6202 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
6203 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
6204 rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
6205 rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
6206
6207 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
6208 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
6209 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
6210
6211 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6212 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
6213 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6214 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6215 msleep(1);
6216 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6217 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
6218 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6219 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6220
6221 rt2800_rx_filter_calibration(rt2x00dev);
6222 rt2800_led_open_drain_enable(rt2x00dev);
6223 rt2800_normal_mode_setup_3xxx(rt2x00dev);
6224 }
6225
6226 static void rt3593_post_bbp_init(struct rt2x00_dev *rt2x00dev)
6227 {
6228 u8 bbp;
6229 bool txbf_enabled = false; /* FIXME */
6230
6231 rt2800_bbp_read(rt2x00dev, 105, &bbp);
6232 if (rt2x00dev->default_ant.rx_chain_num == 1)
6233 rt2x00_set_field8(&bbp, BBP105_MLD, 0);
6234 else
6235 rt2x00_set_field8(&bbp, BBP105_MLD, 1);
6236 rt2800_bbp_write(rt2x00dev, 105, bbp);
6237
6238 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6239
6240 rt2800_bbp_write(rt2x00dev, 92, 0x02);
6241 rt2800_bbp_write(rt2x00dev, 82, 0x82);
6242 rt2800_bbp_write(rt2x00dev, 106, 0x05);
6243 rt2800_bbp_write(rt2x00dev, 104, 0x92);
6244 rt2800_bbp_write(rt2x00dev, 88, 0x90);
6245 rt2800_bbp_write(rt2x00dev, 148, 0xc8);
6246 rt2800_bbp_write(rt2x00dev, 47, 0x48);
6247 rt2800_bbp_write(rt2x00dev, 120, 0x50);
6248
6249 if (txbf_enabled)
6250 rt2800_bbp_write(rt2x00dev, 163, 0xbd);
6251 else
6252 rt2800_bbp_write(rt2x00dev, 163, 0x9d);
6253
6254 /* SNR mapping */
6255 rt2800_bbp_write(rt2x00dev, 142, 6);
6256 rt2800_bbp_write(rt2x00dev, 143, 160);
6257 rt2800_bbp_write(rt2x00dev, 142, 7);
6258 rt2800_bbp_write(rt2x00dev, 143, 161);
6259 rt2800_bbp_write(rt2x00dev, 142, 8);
6260 rt2800_bbp_write(rt2x00dev, 143, 162);
6261
6262 /* ADC/DAC control */
6263 rt2800_bbp_write(rt2x00dev, 31, 0x08);
6264
6265 /* RX AGC energy lower bound in log2 */
6266 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
6267
6268 /* FIXME: BBP 105 owerwrite? */
6269 rt2800_bbp_write(rt2x00dev, 105, 0x04);
6270
6271 }
6272
6273 static void rt2800_init_rfcsr_3593(struct rt2x00_dev *rt2x00dev)
6274 {
6275 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
6276 u32 reg;
6277 u8 rfcsr;
6278
6279 /* Disable GPIO #4 and #7 function for LAN PE control */
6280 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
6281 rt2x00_set_field32(&reg, GPIO_SWITCH_4, 0);
6282 rt2x00_set_field32(&reg, GPIO_SWITCH_7, 0);
6283 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
6284
6285 /* Initialize default register values */
6286 rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
6287 rt2800_rfcsr_write(rt2x00dev, 3, 0x80);
6288 rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
6289 rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
6290 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
6291 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
6292 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
6293 rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
6294 rt2800_rfcsr_write(rt2x00dev, 12, 0x4e);
6295 rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
6296 rt2800_rfcsr_write(rt2x00dev, 18, 0x40);
6297 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
6298 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
6299 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6300 rt2800_rfcsr_write(rt2x00dev, 32, 0x78);
6301 rt2800_rfcsr_write(rt2x00dev, 33, 0x3b);
6302 rt2800_rfcsr_write(rt2x00dev, 34, 0x3c);
6303 rt2800_rfcsr_write(rt2x00dev, 35, 0xe0);
6304 rt2800_rfcsr_write(rt2x00dev, 38, 0x86);
6305 rt2800_rfcsr_write(rt2x00dev, 39, 0x23);
6306 rt2800_rfcsr_write(rt2x00dev, 44, 0xd3);
6307 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
6308 rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
6309 rt2800_rfcsr_write(rt2x00dev, 49, 0x8e);
6310 rt2800_rfcsr_write(rt2x00dev, 50, 0x86);
6311 rt2800_rfcsr_write(rt2x00dev, 51, 0x75);
6312 rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
6313 rt2800_rfcsr_write(rt2x00dev, 53, 0x18);
6314 rt2800_rfcsr_write(rt2x00dev, 54, 0x18);
6315 rt2800_rfcsr_write(rt2x00dev, 55, 0x18);
6316 rt2800_rfcsr_write(rt2x00dev, 56, 0xdb);
6317 rt2800_rfcsr_write(rt2x00dev, 57, 0x6e);
6318
6319 /* Initiate calibration */
6320 /* TODO: use rt2800_rf_init_calibration ? */
6321 rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
6322 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
6323 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
6324
6325 rt2800_adjust_freq_offset(rt2x00dev);
6326
6327 rt2800_rfcsr_read(rt2x00dev, 18, &rfcsr);
6328 rt2x00_set_field8(&rfcsr, RFCSR18_XO_TUNE_BYPASS, 1);
6329 rt2800_rfcsr_write(rt2x00dev, 18, rfcsr);
6330
6331 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6332 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
6333 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6334 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6335 usleep_range(1000, 1500);
6336 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6337 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
6338 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6339
6340 /* Set initial values for RX filter calibration */
6341 drv_data->calibration_bw20 = 0x1f;
6342 drv_data->calibration_bw40 = 0x2f;
6343
6344 /* Save BBP 25 & 26 values for later use in channel switching */
6345 rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25);
6346 rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26);
6347
6348 rt2800_led_open_drain_enable(rt2x00dev);
6349 rt2800_normal_mode_setup_3593(rt2x00dev);
6350
6351 rt3593_post_bbp_init(rt2x00dev);
6352
6353 /* TODO: enable stream mode support */
6354 }
6355
6356 static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev)
6357 {
6358 rt2800_rf_init_calibration(rt2x00dev, 2);
6359
6360 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
6361 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
6362 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
6363 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
6364 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6365 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
6366 else
6367 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
6368 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
6369 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
6370 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
6371 rt2800_rfcsr_write(rt2x00dev, 12, 0xc6);
6372 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
6373 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
6374 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
6375 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
6376 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
6377 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
6378
6379 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
6380 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
6381 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
6382 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
6383 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
6384 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6385 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
6386 else
6387 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
6388 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
6389 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
6390 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
6391 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
6392
6393 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
6394 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6395 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
6396 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
6397 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
6398 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
6399 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
6400 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
6401 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
6402 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
6403
6404 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6405 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
6406 else
6407 rt2800_rfcsr_write(rt2x00dev, 40, 0x4b);
6408 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
6409 rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
6410 rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
6411 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
6412 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
6413 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6414 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
6415 else
6416 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
6417 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
6418 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
6419 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
6420
6421 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
6422 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6423 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
6424 else
6425 rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
6426 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
6427 rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
6428 rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
6429 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
6430 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
6431 rt2800_rfcsr_write(rt2x00dev, 59, 0x63);
6432
6433 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
6434 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6435 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
6436 else
6437 rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
6438 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
6439 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
6440
6441 rt2800_normal_mode_setup_5xxx(rt2x00dev);
6442
6443 rt2800_led_open_drain_enable(rt2x00dev);
6444 }
6445
6446 static void rt2800_init_rfcsr_5392(struct rt2x00_dev *rt2x00dev)
6447 {
6448 rt2800_rf_init_calibration(rt2x00dev, 2);
6449
6450 rt2800_rfcsr_write(rt2x00dev, 1, 0x17);
6451 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
6452 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
6453 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
6454 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
6455 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
6456 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
6457 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
6458 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
6459 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
6460 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
6461 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
6462 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
6463 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
6464 rt2800_rfcsr_write(rt2x00dev, 19, 0x4d);
6465 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
6466 rt2800_rfcsr_write(rt2x00dev, 21, 0x8d);
6467 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
6468 rt2800_rfcsr_write(rt2x00dev, 23, 0x0b);
6469 rt2800_rfcsr_write(rt2x00dev, 24, 0x44);
6470 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
6471 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
6472 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
6473 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
6474 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
6475 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
6476 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6477 rt2800_rfcsr_write(rt2x00dev, 32, 0x20);
6478 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
6479 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
6480 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
6481 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
6482 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
6483 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
6484 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
6485 rt2800_rfcsr_write(rt2x00dev, 40, 0x0f);
6486 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
6487 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
6488 rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
6489 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
6490 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
6491 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
6492 rt2800_rfcsr_write(rt2x00dev, 47, 0x0c);
6493 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
6494 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
6495 rt2800_rfcsr_write(rt2x00dev, 50, 0x94);
6496 rt2800_rfcsr_write(rt2x00dev, 51, 0x3a);
6497 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
6498 rt2800_rfcsr_write(rt2x00dev, 53, 0x44);
6499 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
6500 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
6501 rt2800_rfcsr_write(rt2x00dev, 56, 0xa1);
6502 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
6503 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
6504 rt2800_rfcsr_write(rt2x00dev, 59, 0x07);
6505 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
6506 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
6507 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
6508 rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
6509
6510 rt2800_normal_mode_setup_5xxx(rt2x00dev);
6511
6512 rt2800_led_open_drain_enable(rt2x00dev);
6513 }
6514
6515 static void rt2800_init_rfcsr_5592(struct rt2x00_dev *rt2x00dev)
6516 {
6517 rt2800_rf_init_calibration(rt2x00dev, 30);
6518
6519 rt2800_rfcsr_write(rt2x00dev, 1, 0x3F);
6520 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
6521 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
6522 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
6523 rt2800_rfcsr_write(rt2x00dev, 6, 0xE4);
6524 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
6525 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
6526 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
6527 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
6528 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
6529 rt2800_rfcsr_write(rt2x00dev, 19, 0x4D);
6530 rt2800_rfcsr_write(rt2x00dev, 20, 0x10);
6531 rt2800_rfcsr_write(rt2x00dev, 21, 0x8D);
6532 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
6533 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
6534 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
6535 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
6536 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
6537 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
6538 rt2800_rfcsr_write(rt2x00dev, 47, 0x0C);
6539 rt2800_rfcsr_write(rt2x00dev, 53, 0x22);
6540 rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
6541
6542 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
6543 msleep(1);
6544
6545 rt2800_adjust_freq_offset(rt2x00dev);
6546
6547 /* Enable DC filter */
6548 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
6549 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6550
6551 rt2800_normal_mode_setup_5xxx(rt2x00dev);
6552
6553 if (rt2x00_rt_rev_lt(rt2x00dev, RT5592, REV_RT5592C))
6554 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
6555
6556 rt2800_led_open_drain_enable(rt2x00dev);
6557 }
6558
6559 static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
6560 {
6561 if (rt2800_is_305x_soc(rt2x00dev)) {
6562 rt2800_init_rfcsr_305x_soc(rt2x00dev);
6563 return;
6564 }
6565
6566 switch (rt2x00dev->chip.rt) {
6567 case RT3070:
6568 case RT3071:
6569 case RT3090:
6570 rt2800_init_rfcsr_30xx(rt2x00dev);
6571 break;
6572 case RT3290:
6573 rt2800_init_rfcsr_3290(rt2x00dev);
6574 break;
6575 case RT3352:
6576 rt2800_init_rfcsr_3352(rt2x00dev);
6577 break;
6578 case RT3390:
6579 rt2800_init_rfcsr_3390(rt2x00dev);
6580 break;
6581 case RT3572:
6582 rt2800_init_rfcsr_3572(rt2x00dev);
6583 break;
6584 case RT3593:
6585 rt2800_init_rfcsr_3593(rt2x00dev);
6586 break;
6587 case RT5390:
6588 rt2800_init_rfcsr_5390(rt2x00dev);
6589 break;
6590 case RT5392:
6591 rt2800_init_rfcsr_5392(rt2x00dev);
6592 break;
6593 case RT5592:
6594 rt2800_init_rfcsr_5592(rt2x00dev);
6595 break;
6596 }
6597 }
6598
6599 int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
6600 {
6601 u32 reg;
6602 u16 word;
6603
6604 /*
6605 * Initialize all registers.
6606 */
6607 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
6608 rt2800_init_registers(rt2x00dev)))
6609 return -EIO;
6610
6611 /*
6612 * Send signal to firmware during boot time.
6613 */
6614 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
6615 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
6616 if (rt2x00_is_usb(rt2x00dev)) {
6617 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
6618 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
6619 }
6620 msleep(1);
6621
6622 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
6623 rt2800_wait_bbp_ready(rt2x00dev)))
6624 return -EIO;
6625
6626 rt2800_init_bbp(rt2x00dev);
6627 rt2800_init_rfcsr(rt2x00dev);
6628
6629 if (rt2x00_is_usb(rt2x00dev) &&
6630 (rt2x00_rt(rt2x00dev, RT3070) ||
6631 rt2x00_rt(rt2x00dev, RT3071) ||
6632 rt2x00_rt(rt2x00dev, RT3572))) {
6633 udelay(200);
6634 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
6635 udelay(10);
6636 }
6637
6638 /*
6639 * Enable RX.
6640 */
6641 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
6642 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
6643 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
6644 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
6645
6646 udelay(50);
6647
6648 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
6649 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
6650 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
6651 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
6652 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
6653 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
6654
6655 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
6656 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
6657 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
6658 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
6659
6660 /*
6661 * Initialize LED control
6662 */
6663 rt2800_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word);
6664 rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
6665 word & 0xff, (word >> 8) & 0xff);
6666
6667 rt2800_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word);
6668 rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
6669 word & 0xff, (word >> 8) & 0xff);
6670
6671 rt2800_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word);
6672 rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
6673 word & 0xff, (word >> 8) & 0xff);
6674
6675 return 0;
6676 }
6677 EXPORT_SYMBOL_GPL(rt2800_enable_radio);
6678
6679 void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
6680 {
6681 u32 reg;
6682
6683 rt2800_disable_wpdma(rt2x00dev);
6684
6685 /* Wait for DMA, ignore error */
6686 rt2800_wait_wpdma_ready(rt2x00dev);
6687
6688 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
6689 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
6690 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
6691 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
6692 }
6693 EXPORT_SYMBOL_GPL(rt2800_disable_radio);
6694
6695 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
6696 {
6697 u32 reg;
6698 u16 efuse_ctrl_reg;
6699
6700 if (rt2x00_rt(rt2x00dev, RT3290))
6701 efuse_ctrl_reg = EFUSE_CTRL_3290;
6702 else
6703 efuse_ctrl_reg = EFUSE_CTRL;
6704
6705 rt2800_register_read(rt2x00dev, efuse_ctrl_reg, &reg);
6706 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
6707 }
6708 EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
6709
6710 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
6711 {
6712 u32 reg;
6713 u16 efuse_ctrl_reg;
6714 u16 efuse_data0_reg;
6715 u16 efuse_data1_reg;
6716 u16 efuse_data2_reg;
6717 u16 efuse_data3_reg;
6718
6719 if (rt2x00_rt(rt2x00dev, RT3290)) {
6720 efuse_ctrl_reg = EFUSE_CTRL_3290;
6721 efuse_data0_reg = EFUSE_DATA0_3290;
6722 efuse_data1_reg = EFUSE_DATA1_3290;
6723 efuse_data2_reg = EFUSE_DATA2_3290;
6724 efuse_data3_reg = EFUSE_DATA3_3290;
6725 } else {
6726 efuse_ctrl_reg = EFUSE_CTRL;
6727 efuse_data0_reg = EFUSE_DATA0;
6728 efuse_data1_reg = EFUSE_DATA1;
6729 efuse_data2_reg = EFUSE_DATA2;
6730 efuse_data3_reg = EFUSE_DATA3;
6731 }
6732 mutex_lock(&rt2x00dev->csr_mutex);
6733
6734 rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg, &reg);
6735 rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
6736 rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
6737 rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
6738 rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg);
6739
6740 /* Wait until the EEPROM has been loaded */
6741 rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, &reg);
6742 /* Apparently the data is read from end to start */
6743 rt2800_register_read_lock(rt2x00dev, efuse_data3_reg, &reg);
6744 /* The returned value is in CPU order, but eeprom is le */
6745 *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg);
6746 rt2800_register_read_lock(rt2x00dev, efuse_data2_reg, &reg);
6747 *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg);
6748 rt2800_register_read_lock(rt2x00dev, efuse_data1_reg, &reg);
6749 *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg);
6750 rt2800_register_read_lock(rt2x00dev, efuse_data0_reg, &reg);
6751 *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg);
6752
6753 mutex_unlock(&rt2x00dev->csr_mutex);
6754 }
6755
6756 int rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
6757 {
6758 unsigned int i;
6759
6760 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
6761 rt2800_efuse_read(rt2x00dev, i);
6762
6763 return 0;
6764 }
6765 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
6766
6767 static u8 rt2800_get_txmixer_gain_24g(struct rt2x00_dev *rt2x00dev)
6768 {
6769 u16 word;
6770
6771 if (rt2x00_rt(rt2x00dev, RT3593))
6772 return 0;
6773
6774 rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &word);
6775 if ((word & 0x00ff) != 0x00ff)
6776 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL);
6777
6778 return 0;
6779 }
6780
6781 static u8 rt2800_get_txmixer_gain_5g(struct rt2x00_dev *rt2x00dev)
6782 {
6783 u16 word;
6784
6785 if (rt2x00_rt(rt2x00dev, RT3593))
6786 return 0;
6787
6788 rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A, &word);
6789 if ((word & 0x00ff) != 0x00ff)
6790 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL);
6791
6792 return 0;
6793 }
6794
6795 static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
6796 {
6797 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
6798 u16 word;
6799 u8 *mac;
6800 u8 default_lna_gain;
6801 int retval;
6802
6803 /*
6804 * Read the EEPROM.
6805 */
6806 retval = rt2800_read_eeprom(rt2x00dev);
6807 if (retval)
6808 return retval;
6809
6810 /*
6811 * Start validation of the data that has been read.
6812 */
6813 mac = rt2800_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
6814 if (!is_valid_ether_addr(mac)) {
6815 eth_random_addr(mac);
6816 rt2x00_eeprom_dbg(rt2x00dev, "MAC: %pM\n", mac);
6817 }
6818
6819 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word);
6820 if (word == 0xffff) {
6821 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
6822 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
6823 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
6824 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
6825 rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word);
6826 } else if (rt2x00_rt(rt2x00dev, RT2860) ||
6827 rt2x00_rt(rt2x00dev, RT2872)) {
6828 /*
6829 * There is a max of 2 RX streams for RT28x0 series
6830 */
6831 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
6832 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
6833 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
6834 }
6835
6836 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
6837 if (word == 0xffff) {
6838 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
6839 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
6840 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
6841 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
6842 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
6843 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
6844 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
6845 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
6846 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
6847 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
6848 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
6849 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
6850 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
6851 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
6852 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
6853 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
6854 rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word);
6855 }
6856
6857 rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
6858 if ((word & 0x00ff) == 0x00ff) {
6859 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
6860 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
6861 rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word);
6862 }
6863 if ((word & 0xff00) == 0xff00) {
6864 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
6865 LED_MODE_TXRX_ACTIVITY);
6866 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
6867 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
6868 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
6869 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
6870 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
6871 rt2x00_eeprom_dbg(rt2x00dev, "Led Mode: 0x%04x\n", word);
6872 }
6873
6874 /*
6875 * During the LNA validation we are going to use
6876 * lna0 as correct value. Note that EEPROM_LNA
6877 * is never validated.
6878 */
6879 rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
6880 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
6881
6882 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
6883 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
6884 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
6885 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
6886 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
6887 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
6888
6889 drv_data->txmixer_gain_24g = rt2800_get_txmixer_gain_24g(rt2x00dev);
6890
6891 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
6892 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
6893 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
6894 if (!rt2x00_rt(rt2x00dev, RT3593)) {
6895 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
6896 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
6897 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
6898 default_lna_gain);
6899 }
6900 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
6901
6902 drv_data->txmixer_gain_5g = rt2800_get_txmixer_gain_5g(rt2x00dev);
6903
6904 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
6905 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
6906 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
6907 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
6908 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
6909 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
6910
6911 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
6912 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
6913 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
6914 if (!rt2x00_rt(rt2x00dev, RT3593)) {
6915 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
6916 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
6917 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
6918 default_lna_gain);
6919 }
6920 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
6921
6922 if (rt2x00_rt(rt2x00dev, RT3593)) {
6923 rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &word);
6924 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0x00 ||
6925 rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0xff)
6926 rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1,
6927 default_lna_gain);
6928 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0x00 ||
6929 rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0xff)
6930 rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1,
6931 default_lna_gain);
6932 rt2800_eeprom_write(rt2x00dev, EEPROM_EXT_LNA2, word);
6933 }
6934
6935 return 0;
6936 }
6937
6938 static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
6939 {
6940 u16 value;
6941 u16 eeprom;
6942 u16 rf;
6943
6944 /*
6945 * Read EEPROM word for configuration.
6946 */
6947 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
6948
6949 /*
6950 * Identify RF chipset by EEPROM value
6951 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
6952 * RT53xx: defined in "EEPROM_CHIP_ID" field
6953 */
6954 if (rt2x00_rt(rt2x00dev, RT3290) ||
6955 rt2x00_rt(rt2x00dev, RT5390) ||
6956 rt2x00_rt(rt2x00dev, RT5392))
6957 rt2800_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &rf);
6958 else
6959 rf = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
6960
6961 switch (rf) {
6962 case RF2820:
6963 case RF2850:
6964 case RF2720:
6965 case RF2750:
6966 case RF3020:
6967 case RF2020:
6968 case RF3021:
6969 case RF3022:
6970 case RF3052:
6971 case RF3053:
6972 case RF3290:
6973 case RF3320:
6974 case RF3322:
6975 case RF5360:
6976 case RF5370:
6977 case RF5372:
6978 case RF5390:
6979 case RF5392:
6980 case RF5592:
6981 break;
6982 default:
6983 rt2x00_err(rt2x00dev, "Invalid RF chipset 0x%04x detected\n",
6984 rf);
6985 return -ENODEV;
6986 }
6987
6988 rt2x00_set_rf(rt2x00dev, rf);
6989
6990 /*
6991 * Identify default antenna configuration.
6992 */
6993 rt2x00dev->default_ant.tx_chain_num =
6994 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
6995 rt2x00dev->default_ant.rx_chain_num =
6996 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
6997
6998 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
6999
7000 if (rt2x00_rt(rt2x00dev, RT3070) ||
7001 rt2x00_rt(rt2x00dev, RT3090) ||
7002 rt2x00_rt(rt2x00dev, RT3352) ||
7003 rt2x00_rt(rt2x00dev, RT3390)) {
7004 value = rt2x00_get_field16(eeprom,
7005 EEPROM_NIC_CONF1_ANT_DIVERSITY);
7006 switch (value) {
7007 case 0:
7008 case 1:
7009 case 2:
7010 rt2x00dev->default_ant.tx = ANTENNA_A;
7011 rt2x00dev->default_ant.rx = ANTENNA_A;
7012 break;
7013 case 3:
7014 rt2x00dev->default_ant.tx = ANTENNA_A;
7015 rt2x00dev->default_ant.rx = ANTENNA_B;
7016 break;
7017 }
7018 } else {
7019 rt2x00dev->default_ant.tx = ANTENNA_A;
7020 rt2x00dev->default_ant.rx = ANTENNA_A;
7021 }
7022
7023 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
7024 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; /* Unused */
7025 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; /* Unused */
7026 }
7027
7028 /*
7029 * Determine external LNA informations.
7030 */
7031 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
7032 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
7033 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
7034 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
7035
7036 /*
7037 * Detect if this device has an hardware controlled radio.
7038 */
7039 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
7040 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
7041
7042 /*
7043 * Detect if this device has Bluetooth co-existence.
7044 */
7045 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST))
7046 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags);
7047
7048 /*
7049 * Read frequency offset and RF programming sequence.
7050 */
7051 rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
7052 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
7053
7054 /*
7055 * Store led settings, for correct led behaviour.
7056 */
7057 #ifdef CONFIG_RT2X00_LIB_LEDS
7058 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
7059 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
7060 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
7061
7062 rt2x00dev->led_mcu_reg = eeprom;
7063 #endif /* CONFIG_RT2X00_LIB_LEDS */
7064
7065 /*
7066 * Check if support EIRP tx power limit feature.
7067 */
7068 rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom);
7069
7070 if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
7071 EIRP_MAX_TX_POWER_LIMIT)
7072 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
7073
7074 return 0;
7075 }
7076
7077 /*
7078 * RF value list for rt28xx
7079 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
7080 */
7081 static const struct rf_channel rf_vals[] = {
7082 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
7083 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
7084 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
7085 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
7086 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
7087 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
7088 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
7089 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
7090 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
7091 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
7092 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
7093 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
7094 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
7095 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
7096
7097 /* 802.11 UNI / HyperLan 2 */
7098 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
7099 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
7100 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
7101 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
7102 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
7103 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
7104 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
7105 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
7106 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
7107 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
7108 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
7109 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
7110
7111 /* 802.11 HyperLan 2 */
7112 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
7113 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
7114 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
7115 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
7116 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
7117 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
7118 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
7119 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
7120 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
7121 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
7122 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
7123 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
7124 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
7125 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
7126 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
7127 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
7128
7129 /* 802.11 UNII */
7130 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
7131 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
7132 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
7133 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
7134 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
7135 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
7136 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
7137 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
7138 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
7139 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
7140 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
7141
7142 /* 802.11 Japan */
7143 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
7144 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
7145 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
7146 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
7147 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
7148 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
7149 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
7150 };
7151
7152 /*
7153 * RF value list for rt3xxx
7154 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
7155 */
7156 static const struct rf_channel rf_vals_3x[] = {
7157 {1, 241, 2, 2 },
7158 {2, 241, 2, 7 },
7159 {3, 242, 2, 2 },
7160 {4, 242, 2, 7 },
7161 {5, 243, 2, 2 },
7162 {6, 243, 2, 7 },
7163 {7, 244, 2, 2 },
7164 {8, 244, 2, 7 },
7165 {9, 245, 2, 2 },
7166 {10, 245, 2, 7 },
7167 {11, 246, 2, 2 },
7168 {12, 246, 2, 7 },
7169 {13, 247, 2, 2 },
7170 {14, 248, 2, 4 },
7171
7172 /* 802.11 UNI / HyperLan 2 */
7173 {36, 0x56, 0, 4},
7174 {38, 0x56, 0, 6},
7175 {40, 0x56, 0, 8},
7176 {44, 0x57, 0, 0},
7177 {46, 0x57, 0, 2},
7178 {48, 0x57, 0, 4},
7179 {52, 0x57, 0, 8},
7180 {54, 0x57, 0, 10},
7181 {56, 0x58, 0, 0},
7182 {60, 0x58, 0, 4},
7183 {62, 0x58, 0, 6},
7184 {64, 0x58, 0, 8},
7185
7186 /* 802.11 HyperLan 2 */
7187 {100, 0x5b, 0, 8},
7188 {102, 0x5b, 0, 10},
7189 {104, 0x5c, 0, 0},
7190 {108, 0x5c, 0, 4},
7191 {110, 0x5c, 0, 6},
7192 {112, 0x5c, 0, 8},
7193 {116, 0x5d, 0, 0},
7194 {118, 0x5d, 0, 2},
7195 {120, 0x5d, 0, 4},
7196 {124, 0x5d, 0, 8},
7197 {126, 0x5d, 0, 10},
7198 {128, 0x5e, 0, 0},
7199 {132, 0x5e, 0, 4},
7200 {134, 0x5e, 0, 6},
7201 {136, 0x5e, 0, 8},
7202 {140, 0x5f, 0, 0},
7203
7204 /* 802.11 UNII */
7205 {149, 0x5f, 0, 9},
7206 {151, 0x5f, 0, 11},
7207 {153, 0x60, 0, 1},
7208 {157, 0x60, 0, 5},
7209 {159, 0x60, 0, 7},
7210 {161, 0x60, 0, 9},
7211 {165, 0x61, 0, 1},
7212 {167, 0x61, 0, 3},
7213 {169, 0x61, 0, 5},
7214 {171, 0x61, 0, 7},
7215 {173, 0x61, 0, 9},
7216 };
7217
7218 static const struct rf_channel rf_vals_5592_xtal20[] = {
7219 /* Channel, N, K, mod, R */
7220 {1, 482, 4, 10, 3},
7221 {2, 483, 4, 10, 3},
7222 {3, 484, 4, 10, 3},
7223 {4, 485, 4, 10, 3},
7224 {5, 486, 4, 10, 3},
7225 {6, 487, 4, 10, 3},
7226 {7, 488, 4, 10, 3},
7227 {8, 489, 4, 10, 3},
7228 {9, 490, 4, 10, 3},
7229 {10, 491, 4, 10, 3},
7230 {11, 492, 4, 10, 3},
7231 {12, 493, 4, 10, 3},
7232 {13, 494, 4, 10, 3},
7233 {14, 496, 8, 10, 3},
7234 {36, 172, 8, 12, 1},
7235 {38, 173, 0, 12, 1},
7236 {40, 173, 4, 12, 1},
7237 {42, 173, 8, 12, 1},
7238 {44, 174, 0, 12, 1},
7239 {46, 174, 4, 12, 1},
7240 {48, 174, 8, 12, 1},
7241 {50, 175, 0, 12, 1},
7242 {52, 175, 4, 12, 1},
7243 {54, 175, 8, 12, 1},
7244 {56, 176, 0, 12, 1},
7245 {58, 176, 4, 12, 1},
7246 {60, 176, 8, 12, 1},
7247 {62, 177, 0, 12, 1},
7248 {64, 177, 4, 12, 1},
7249 {100, 183, 4, 12, 1},
7250 {102, 183, 8, 12, 1},
7251 {104, 184, 0, 12, 1},
7252 {106, 184, 4, 12, 1},
7253 {108, 184, 8, 12, 1},
7254 {110, 185, 0, 12, 1},
7255 {112, 185, 4, 12, 1},
7256 {114, 185, 8, 12, 1},
7257 {116, 186, 0, 12, 1},
7258 {118, 186, 4, 12, 1},
7259 {120, 186, 8, 12, 1},
7260 {122, 187, 0, 12, 1},
7261 {124, 187, 4, 12, 1},
7262 {126, 187, 8, 12, 1},
7263 {128, 188, 0, 12, 1},
7264 {130, 188, 4, 12, 1},
7265 {132, 188, 8, 12, 1},
7266 {134, 189, 0, 12, 1},
7267 {136, 189, 4, 12, 1},
7268 {138, 189, 8, 12, 1},
7269 {140, 190, 0, 12, 1},
7270 {149, 191, 6, 12, 1},
7271 {151, 191, 10, 12, 1},
7272 {153, 192, 2, 12, 1},
7273 {155, 192, 6, 12, 1},
7274 {157, 192, 10, 12, 1},
7275 {159, 193, 2, 12, 1},
7276 {161, 193, 6, 12, 1},
7277 {165, 194, 2, 12, 1},
7278 {184, 164, 0, 12, 1},
7279 {188, 164, 4, 12, 1},
7280 {192, 165, 8, 12, 1},
7281 {196, 166, 0, 12, 1},
7282 };
7283
7284 static const struct rf_channel rf_vals_5592_xtal40[] = {
7285 /* Channel, N, K, mod, R */
7286 {1, 241, 2, 10, 3},
7287 {2, 241, 7, 10, 3},
7288 {3, 242, 2, 10, 3},
7289 {4, 242, 7, 10, 3},
7290 {5, 243, 2, 10, 3},
7291 {6, 243, 7, 10, 3},
7292 {7, 244, 2, 10, 3},
7293 {8, 244, 7, 10, 3},
7294 {9, 245, 2, 10, 3},
7295 {10, 245, 7, 10, 3},
7296 {11, 246, 2, 10, 3},
7297 {12, 246, 7, 10, 3},
7298 {13, 247, 2, 10, 3},
7299 {14, 248, 4, 10, 3},
7300 {36, 86, 4, 12, 1},
7301 {38, 86, 6, 12, 1},
7302 {40, 86, 8, 12, 1},
7303 {42, 86, 10, 12, 1},
7304 {44, 87, 0, 12, 1},
7305 {46, 87, 2, 12, 1},
7306 {48, 87, 4, 12, 1},
7307 {50, 87, 6, 12, 1},
7308 {52, 87, 8, 12, 1},
7309 {54, 87, 10, 12, 1},
7310 {56, 88, 0, 12, 1},
7311 {58, 88, 2, 12, 1},
7312 {60, 88, 4, 12, 1},
7313 {62, 88, 6, 12, 1},
7314 {64, 88, 8, 12, 1},
7315 {100, 91, 8, 12, 1},
7316 {102, 91, 10, 12, 1},
7317 {104, 92, 0, 12, 1},
7318 {106, 92, 2, 12, 1},
7319 {108, 92, 4, 12, 1},
7320 {110, 92, 6, 12, 1},
7321 {112, 92, 8, 12, 1},
7322 {114, 92, 10, 12, 1},
7323 {116, 93, 0, 12, 1},
7324 {118, 93, 2, 12, 1},
7325 {120, 93, 4, 12, 1},
7326 {122, 93, 6, 12, 1},
7327 {124, 93, 8, 12, 1},
7328 {126, 93, 10, 12, 1},
7329 {128, 94, 0, 12, 1},
7330 {130, 94, 2, 12, 1},
7331 {132, 94, 4, 12, 1},
7332 {134, 94, 6, 12, 1},
7333 {136, 94, 8, 12, 1},
7334 {138, 94, 10, 12, 1},
7335 {140, 95, 0, 12, 1},
7336 {149, 95, 9, 12, 1},
7337 {151, 95, 11, 12, 1},
7338 {153, 96, 1, 12, 1},
7339 {155, 96, 3, 12, 1},
7340 {157, 96, 5, 12, 1},
7341 {159, 96, 7, 12, 1},
7342 {161, 96, 9, 12, 1},
7343 {165, 97, 1, 12, 1},
7344 {184, 82, 0, 12, 1},
7345 {188, 82, 4, 12, 1},
7346 {192, 82, 8, 12, 1},
7347 {196, 83, 0, 12, 1},
7348 };
7349
7350 static const struct rf_channel rf_vals_3053[] = {
7351 /* Channel, N, R, K */
7352 {1, 241, 2, 2},
7353 {2, 241, 2, 7},
7354 {3, 242, 2, 2},
7355 {4, 242, 2, 7},
7356 {5, 243, 2, 2},
7357 {6, 243, 2, 7},
7358 {7, 244, 2, 2},
7359 {8, 244, 2, 7},
7360 {9, 245, 2, 2},
7361 {10, 245, 2, 7},
7362 {11, 246, 2, 2},
7363 {12, 246, 2, 7},
7364 {13, 247, 2, 2},
7365 {14, 248, 2, 4},
7366
7367 {36, 0x56, 0, 4},
7368 {38, 0x56, 0, 6},
7369 {40, 0x56, 0, 8},
7370 {44, 0x57, 0, 0},
7371 {46, 0x57, 0, 2},
7372 {48, 0x57, 0, 4},
7373 {52, 0x57, 0, 8},
7374 {54, 0x57, 0, 10},
7375 {56, 0x58, 0, 0},
7376 {60, 0x58, 0, 4},
7377 {62, 0x58, 0, 6},
7378 {64, 0x58, 0, 8},
7379
7380 {100, 0x5B, 0, 8},
7381 {102, 0x5B, 0, 10},
7382 {104, 0x5C, 0, 0},
7383 {108, 0x5C, 0, 4},
7384 {110, 0x5C, 0, 6},
7385 {112, 0x5C, 0, 8},
7386
7387 /* NOTE: Channel 114 has been removed intentionally.
7388 * The EEPROM contains no TX power values for that,
7389 * and it is disabled in the vendor driver as well.
7390 */
7391
7392 {116, 0x5D, 0, 0},
7393 {118, 0x5D, 0, 2},
7394 {120, 0x5D, 0, 4},
7395 {124, 0x5D, 0, 8},
7396 {126, 0x5D, 0, 10},
7397 {128, 0x5E, 0, 0},
7398 {132, 0x5E, 0, 4},
7399 {134, 0x5E, 0, 6},
7400 {136, 0x5E, 0, 8},
7401 {140, 0x5F, 0, 0},
7402
7403 {149, 0x5F, 0, 9},
7404 {151, 0x5F, 0, 11},
7405 {153, 0x60, 0, 1},
7406 {157, 0x60, 0, 5},
7407 {159, 0x60, 0, 7},
7408 {161, 0x60, 0, 9},
7409 {165, 0x61, 0, 1},
7410 {167, 0x61, 0, 3},
7411 {169, 0x61, 0, 5},
7412 {171, 0x61, 0, 7},
7413 {173, 0x61, 0, 9},
7414 };
7415
7416 static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
7417 {
7418 struct hw_mode_spec *spec = &rt2x00dev->spec;
7419 struct channel_info *info;
7420 char *default_power1;
7421 char *default_power2;
7422 char *default_power3;
7423 unsigned int i;
7424 u16 eeprom;
7425 u32 reg;
7426
7427 /*
7428 * Disable powersaving as default on PCI devices.
7429 */
7430 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
7431 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
7432
7433 /*
7434 * Initialize all hw fields.
7435 */
7436 rt2x00dev->hw->flags =
7437 IEEE80211_HW_SIGNAL_DBM |
7438 IEEE80211_HW_SUPPORTS_PS |
7439 IEEE80211_HW_PS_NULLFUNC_STACK |
7440 IEEE80211_HW_AMPDU_AGGREGATION |
7441 IEEE80211_HW_REPORTS_TX_ACK_STATUS;
7442
7443 /*
7444 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
7445 * unless we are capable of sending the buffered frames out after the
7446 * DTIM transmission using rt2x00lib_beacondone. This will send out
7447 * multicast and broadcast traffic immediately instead of buffering it
7448 * infinitly and thus dropping it after some time.
7449 */
7450 if (!rt2x00_is_usb(rt2x00dev))
7451 rt2x00dev->hw->flags |=
7452 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
7453
7454 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
7455 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
7456 rt2800_eeprom_addr(rt2x00dev,
7457 EEPROM_MAC_ADDR_0));
7458
7459 /*
7460 * As rt2800 has a global fallback table we cannot specify
7461 * more then one tx rate per frame but since the hw will
7462 * try several rates (based on the fallback table) we should
7463 * initialize max_report_rates to the maximum number of rates
7464 * we are going to try. Otherwise mac80211 will truncate our
7465 * reported tx rates and the rc algortihm will end up with
7466 * incorrect data.
7467 */
7468 rt2x00dev->hw->max_rates = 1;
7469 rt2x00dev->hw->max_report_rates = 7;
7470 rt2x00dev->hw->max_rate_tries = 1;
7471
7472 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
7473
7474 /*
7475 * Initialize hw_mode information.
7476 */
7477 spec->supported_bands = SUPPORT_BAND_2GHZ;
7478 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
7479
7480 if (rt2x00_rf(rt2x00dev, RF2820) ||
7481 rt2x00_rf(rt2x00dev, RF2720)) {
7482 spec->num_channels = 14;
7483 spec->channels = rf_vals;
7484 } else if (rt2x00_rf(rt2x00dev, RF2850) ||
7485 rt2x00_rf(rt2x00dev, RF2750)) {
7486 spec->supported_bands |= SUPPORT_BAND_5GHZ;
7487 spec->num_channels = ARRAY_SIZE(rf_vals);
7488 spec->channels = rf_vals;
7489 } else if (rt2x00_rf(rt2x00dev, RF3020) ||
7490 rt2x00_rf(rt2x00dev, RF2020) ||
7491 rt2x00_rf(rt2x00dev, RF3021) ||
7492 rt2x00_rf(rt2x00dev, RF3022) ||
7493 rt2x00_rf(rt2x00dev, RF3290) ||
7494 rt2x00_rf(rt2x00dev, RF3320) ||
7495 rt2x00_rf(rt2x00dev, RF3322) ||
7496 rt2x00_rf(rt2x00dev, RF5360) ||
7497 rt2x00_rf(rt2x00dev, RF5370) ||
7498 rt2x00_rf(rt2x00dev, RF5372) ||
7499 rt2x00_rf(rt2x00dev, RF5390) ||
7500 rt2x00_rf(rt2x00dev, RF5392)) {
7501 spec->num_channels = 14;
7502 spec->channels = rf_vals_3x;
7503 } else if (rt2x00_rf(rt2x00dev, RF3052)) {
7504 spec->supported_bands |= SUPPORT_BAND_5GHZ;
7505 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
7506 spec->channels = rf_vals_3x;
7507 } else if (rt2x00_rf(rt2x00dev, RF3053)) {
7508 spec->supported_bands |= SUPPORT_BAND_5GHZ;
7509 spec->num_channels = ARRAY_SIZE(rf_vals_3053);
7510 spec->channels = rf_vals_3053;
7511 } else if (rt2x00_rf(rt2x00dev, RF5592)) {
7512 spec->supported_bands |= SUPPORT_BAND_5GHZ;
7513
7514 rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX, &reg);
7515 if (rt2x00_get_field32(reg, MAC_DEBUG_INDEX_XTAL)) {
7516 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal40);
7517 spec->channels = rf_vals_5592_xtal40;
7518 } else {
7519 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal20);
7520 spec->channels = rf_vals_5592_xtal20;
7521 }
7522 }
7523
7524 if (WARN_ON_ONCE(!spec->channels))
7525 return -ENODEV;
7526
7527 /*
7528 * Initialize HT information.
7529 */
7530 if (!rt2x00_rf(rt2x00dev, RF2020))
7531 spec->ht.ht_supported = true;
7532 else
7533 spec->ht.ht_supported = false;
7534
7535 spec->ht.cap =
7536 IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
7537 IEEE80211_HT_CAP_GRN_FLD |
7538 IEEE80211_HT_CAP_SGI_20 |
7539 IEEE80211_HT_CAP_SGI_40;
7540
7541 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) >= 2)
7542 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
7543
7544 spec->ht.cap |=
7545 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) <<
7546 IEEE80211_HT_CAP_RX_STBC_SHIFT;
7547
7548 spec->ht.ampdu_factor = 3;
7549 spec->ht.ampdu_density = 4;
7550 spec->ht.mcs.tx_params =
7551 IEEE80211_HT_MCS_TX_DEFINED |
7552 IEEE80211_HT_MCS_TX_RX_DIFF |
7553 ((rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) - 1) <<
7554 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
7555
7556 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH)) {
7557 case 3:
7558 spec->ht.mcs.rx_mask[2] = 0xff;
7559 case 2:
7560 spec->ht.mcs.rx_mask[1] = 0xff;
7561 case 1:
7562 spec->ht.mcs.rx_mask[0] = 0xff;
7563 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
7564 break;
7565 }
7566
7567 /*
7568 * Create channel information array
7569 */
7570 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
7571 if (!info)
7572 return -ENOMEM;
7573
7574 spec->channels_info = info;
7575
7576 default_power1 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
7577 default_power2 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
7578
7579 if (rt2x00dev->default_ant.tx_chain_num > 2)
7580 default_power3 = rt2800_eeprom_addr(rt2x00dev,
7581 EEPROM_EXT_TXPOWER_BG3);
7582 else
7583 default_power3 = NULL;
7584
7585 for (i = 0; i < 14; i++) {
7586 info[i].default_power1 = default_power1[i];
7587 info[i].default_power2 = default_power2[i];
7588 if (default_power3)
7589 info[i].default_power3 = default_power3[i];
7590 }
7591
7592 if (spec->num_channels > 14) {
7593 default_power1 = rt2800_eeprom_addr(rt2x00dev,
7594 EEPROM_TXPOWER_A1);
7595 default_power2 = rt2800_eeprom_addr(rt2x00dev,
7596 EEPROM_TXPOWER_A2);
7597
7598 if (rt2x00dev->default_ant.tx_chain_num > 2)
7599 default_power3 =
7600 rt2800_eeprom_addr(rt2x00dev,
7601 EEPROM_EXT_TXPOWER_A3);
7602 else
7603 default_power3 = NULL;
7604
7605 for (i = 14; i < spec->num_channels; i++) {
7606 info[i].default_power1 = default_power1[i - 14];
7607 info[i].default_power2 = default_power2[i - 14];
7608 if (default_power3)
7609 info[i].default_power3 = default_power3[i - 14];
7610 }
7611 }
7612
7613 switch (rt2x00dev->chip.rf) {
7614 case RF2020:
7615 case RF3020:
7616 case RF3021:
7617 case RF3022:
7618 case RF3320:
7619 case RF3052:
7620 case RF3053:
7621 case RF3290:
7622 case RF5360:
7623 case RF5370:
7624 case RF5372:
7625 case RF5390:
7626 case RF5392:
7627 __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags);
7628 break;
7629 }
7630
7631 return 0;
7632 }
7633
7634 static int rt2800_probe_rt(struct rt2x00_dev *rt2x00dev)
7635 {
7636 u32 reg;
7637 u32 rt;
7638 u32 rev;
7639
7640 if (rt2x00_rt(rt2x00dev, RT3290))
7641 rt2800_register_read(rt2x00dev, MAC_CSR0_3290, &reg);
7642 else
7643 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
7644
7645 rt = rt2x00_get_field32(reg, MAC_CSR0_CHIPSET);
7646 rev = rt2x00_get_field32(reg, MAC_CSR0_REVISION);
7647
7648 switch (rt) {
7649 case RT2860:
7650 case RT2872:
7651 case RT2883:
7652 case RT3070:
7653 case RT3071:
7654 case RT3090:
7655 case RT3290:
7656 case RT3352:
7657 case RT3390:
7658 case RT3572:
7659 case RT3593:
7660 case RT5390:
7661 case RT5392:
7662 case RT5592:
7663 break;
7664 default:
7665 rt2x00_err(rt2x00dev, "Invalid RT chipset 0x%04x, rev %04x detected\n",
7666 rt, rev);
7667 return -ENODEV;
7668 }
7669
7670 rt2x00_set_rt(rt2x00dev, rt, rev);
7671
7672 return 0;
7673 }
7674
7675 int rt2800_probe_hw(struct rt2x00_dev *rt2x00dev)
7676 {
7677 int retval;
7678 u32 reg;
7679
7680 retval = rt2800_probe_rt(rt2x00dev);
7681 if (retval)
7682 return retval;
7683
7684 /*
7685 * Allocate eeprom data.
7686 */
7687 retval = rt2800_validate_eeprom(rt2x00dev);
7688 if (retval)
7689 return retval;
7690
7691 retval = rt2800_init_eeprom(rt2x00dev);
7692 if (retval)
7693 return retval;
7694
7695 /*
7696 * Enable rfkill polling by setting GPIO direction of the
7697 * rfkill switch GPIO pin correctly.
7698 */
7699 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
7700 rt2x00_set_field32(&reg, GPIO_CTRL_DIR2, 1);
7701 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
7702
7703 /*
7704 * Initialize hw specifications.
7705 */
7706 retval = rt2800_probe_hw_mode(rt2x00dev);
7707 if (retval)
7708 return retval;
7709
7710 /*
7711 * Set device capabilities.
7712 */
7713 __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
7714 __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags);
7715 if (!rt2x00_is_usb(rt2x00dev))
7716 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags);
7717
7718 /*
7719 * Set device requirements.
7720 */
7721 if (!rt2x00_is_soc(rt2x00dev))
7722 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
7723 __set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags);
7724 __set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags);
7725 if (!rt2800_hwcrypt_disabled(rt2x00dev))
7726 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
7727 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
7728 __set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags);
7729 if (rt2x00_is_usb(rt2x00dev))
7730 __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags);
7731 else {
7732 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
7733 __set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags);
7734 }
7735
7736 /*
7737 * Set the rssi offset.
7738 */
7739 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
7740
7741 return 0;
7742 }
7743 EXPORT_SYMBOL_GPL(rt2800_probe_hw);
7744
7745 /*
7746 * IEEE80211 stack callback functions.
7747 */
7748 void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
7749 u16 *iv16)
7750 {
7751 struct rt2x00_dev *rt2x00dev = hw->priv;
7752 struct mac_iveiv_entry iveiv_entry;
7753 u32 offset;
7754
7755 offset = MAC_IVEIV_ENTRY(hw_key_idx);
7756 rt2800_register_multiread(rt2x00dev, offset,
7757 &iveiv_entry, sizeof(iveiv_entry));
7758
7759 memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
7760 memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
7761 }
7762 EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
7763
7764 int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
7765 {
7766 struct rt2x00_dev *rt2x00dev = hw->priv;
7767 u32 reg;
7768 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
7769
7770 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
7771 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
7772 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
7773
7774 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
7775 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
7776 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
7777
7778 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
7779 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
7780 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
7781
7782 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
7783 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
7784 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
7785
7786 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
7787 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
7788 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
7789
7790 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
7791 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
7792 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
7793
7794 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
7795 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
7796 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
7797
7798 return 0;
7799 }
7800 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
7801
7802 int rt2800_conf_tx(struct ieee80211_hw *hw,
7803 struct ieee80211_vif *vif, u16 queue_idx,
7804 const struct ieee80211_tx_queue_params *params)
7805 {
7806 struct rt2x00_dev *rt2x00dev = hw->priv;
7807 struct data_queue *queue;
7808 struct rt2x00_field32 field;
7809 int retval;
7810 u32 reg;
7811 u32 offset;
7812
7813 /*
7814 * First pass the configuration through rt2x00lib, that will
7815 * update the queue settings and validate the input. After that
7816 * we are free to update the registers based on the value
7817 * in the queue parameter.
7818 */
7819 retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params);
7820 if (retval)
7821 return retval;
7822
7823 /*
7824 * We only need to perform additional register initialization
7825 * for WMM queues/
7826 */
7827 if (queue_idx >= 4)
7828 return 0;
7829
7830 queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
7831
7832 /* Update WMM TXOP register */
7833 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
7834 field.bit_offset = (queue_idx & 1) * 16;
7835 field.bit_mask = 0xffff << field.bit_offset;
7836
7837 rt2800_register_read(rt2x00dev, offset, &reg);
7838 rt2x00_set_field32(&reg, field, queue->txop);
7839 rt2800_register_write(rt2x00dev, offset, reg);
7840
7841 /* Update WMM registers */
7842 field.bit_offset = queue_idx * 4;
7843 field.bit_mask = 0xf << field.bit_offset;
7844
7845 rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
7846 rt2x00_set_field32(&reg, field, queue->aifs);
7847 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
7848
7849 rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
7850 rt2x00_set_field32(&reg, field, queue->cw_min);
7851 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
7852
7853 rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
7854 rt2x00_set_field32(&reg, field, queue->cw_max);
7855 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
7856
7857 /* Update EDCA registers */
7858 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
7859
7860 rt2800_register_read(rt2x00dev, offset, &reg);
7861 rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
7862 rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
7863 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
7864 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
7865 rt2800_register_write(rt2x00dev, offset, reg);
7866
7867 return 0;
7868 }
7869 EXPORT_SYMBOL_GPL(rt2800_conf_tx);
7870
7871 u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
7872 {
7873 struct rt2x00_dev *rt2x00dev = hw->priv;
7874 u64 tsf;
7875 u32 reg;
7876
7877 rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
7878 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
7879 rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
7880 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
7881
7882 return tsf;
7883 }
7884 EXPORT_SYMBOL_GPL(rt2800_get_tsf);
7885
7886 int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
7887 enum ieee80211_ampdu_mlme_action action,
7888 struct ieee80211_sta *sta, u16 tid, u16 *ssn,
7889 u8 buf_size)
7890 {
7891 struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv;
7892 int ret = 0;
7893
7894 /*
7895 * Don't allow aggregation for stations the hardware isn't aware
7896 * of because tx status reports for frames to an unknown station
7897 * always contain wcid=255 and thus we can't distinguish between
7898 * multiple stations which leads to unwanted situations when the
7899 * hw reorders frames due to aggregation.
7900 */
7901 if (sta_priv->wcid < 0)
7902 return 1;
7903
7904 switch (action) {
7905 case IEEE80211_AMPDU_RX_START:
7906 case IEEE80211_AMPDU_RX_STOP:
7907 /*
7908 * The hw itself takes care of setting up BlockAck mechanisms.
7909 * So, we only have to allow mac80211 to nagotiate a BlockAck
7910 * agreement. Once that is done, the hw will BlockAck incoming
7911 * AMPDUs without further setup.
7912 */
7913 break;
7914 case IEEE80211_AMPDU_TX_START:
7915 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
7916 break;
7917 case IEEE80211_AMPDU_TX_STOP_CONT:
7918 case IEEE80211_AMPDU_TX_STOP_FLUSH:
7919 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
7920 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
7921 break;
7922 case IEEE80211_AMPDU_TX_OPERATIONAL:
7923 break;
7924 default:
7925 rt2x00_warn((struct rt2x00_dev *)hw->priv,
7926 "Unknown AMPDU action\n");
7927 }
7928
7929 return ret;
7930 }
7931 EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
7932
7933 int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
7934 struct survey_info *survey)
7935 {
7936 struct rt2x00_dev *rt2x00dev = hw->priv;
7937 struct ieee80211_conf *conf = &hw->conf;
7938 u32 idle, busy, busy_ext;
7939
7940 if (idx != 0)
7941 return -ENOENT;
7942
7943 survey->channel = conf->chandef.chan;
7944
7945 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle);
7946 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy);
7947 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext);
7948
7949 if (idle || busy) {
7950 survey->filled = SURVEY_INFO_CHANNEL_TIME |
7951 SURVEY_INFO_CHANNEL_TIME_BUSY |
7952 SURVEY_INFO_CHANNEL_TIME_EXT_BUSY;
7953
7954 survey->channel_time = (idle + busy) / 1000;
7955 survey->channel_time_busy = busy / 1000;
7956 survey->channel_time_ext_busy = busy_ext / 1000;
7957 }
7958
7959 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
7960 survey->filled |= SURVEY_INFO_IN_USE;
7961
7962 return 0;
7963
7964 }
7965 EXPORT_SYMBOL_GPL(rt2800_get_survey);
7966
7967 MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
7968 MODULE_VERSION(DRV_VERSION);
7969 MODULE_DESCRIPTION("Ralink RT2800 library");
7970 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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