2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
3 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
4 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
5 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
7 Based on the original rt2800pci.c and rt2800usb.c.
8 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
9 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
10 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
11 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
12 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
13 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
14 <http://rt2x00.serialmonkey.com>
16 This program is free software; you can redistribute it and/or modify
17 it under the terms of the GNU General Public License as published by
18 the Free Software Foundation; either version 2 of the License, or
19 (at your option) any later version.
21 This program is distributed in the hope that it will be useful,
22 but WITHOUT ANY WARRANTY; without even the implied warranty of
23 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 GNU General Public License for more details.
26 You should have received a copy of the GNU General Public License
27 along with this program; if not, write to the
28 Free Software Foundation, Inc.,
29 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
34 Abstract: rt2800 generic device routines.
37 #include <linux/crc-ccitt.h>
38 #include <linux/kernel.h>
39 #include <linux/module.h>
40 #include <linux/slab.h>
43 #include "rt2800lib.h"
48 * All access to the CSR registers will go through the methods
49 * rt2800_register_read and rt2800_register_write.
50 * BBP and RF register require indirect register access,
51 * and use the CSR registers BBPCSR and RFCSR to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
55 * between each attampt. When the busy bit is still set at that time,
56 * the access attempt is considered to have failed,
57 * and we will print an error.
58 * The _lock versions must be used if you already hold the csr_mutex
60 #define WAIT_FOR_BBP(__dev, __reg) \
61 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
62 #define WAIT_FOR_RFCSR(__dev, __reg) \
63 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
64 #define WAIT_FOR_RF(__dev, __reg) \
65 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
66 #define WAIT_FOR_MCU(__dev, __reg) \
67 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
68 H2M_MAILBOX_CSR_OWNER, (__reg))
70 static inline bool rt2800_is_305x_soc(struct rt2x00_dev
*rt2x00dev
)
72 /* check for rt2872 on SoC */
73 if (!rt2x00_is_soc(rt2x00dev
) ||
74 !rt2x00_rt(rt2x00dev
, RT2872
))
77 /* we know for sure that these rf chipsets are used on rt305x boards */
78 if (rt2x00_rf(rt2x00dev
, RF3020
) ||
79 rt2x00_rf(rt2x00dev
, RF3021
) ||
80 rt2x00_rf(rt2x00dev
, RF3022
))
83 NOTICE(rt2x00dev
, "Unknown RF chipset on rt305x\n");
87 static void rt2800_bbp_write(struct rt2x00_dev
*rt2x00dev
,
88 const unsigned int word
, const u8 value
)
92 mutex_lock(&rt2x00dev
->csr_mutex
);
95 * Wait until the BBP becomes available, afterwards we
96 * can safely write the new data into the register.
98 if (WAIT_FOR_BBP(rt2x00dev
, ®
)) {
100 rt2x00_set_field32(®
, BBP_CSR_CFG_VALUE
, value
);
101 rt2x00_set_field32(®
, BBP_CSR_CFG_REGNUM
, word
);
102 rt2x00_set_field32(®
, BBP_CSR_CFG_BUSY
, 1);
103 rt2x00_set_field32(®
, BBP_CSR_CFG_READ_CONTROL
, 0);
104 rt2x00_set_field32(®
, BBP_CSR_CFG_BBP_RW_MODE
, 1);
106 rt2800_register_write_lock(rt2x00dev
, BBP_CSR_CFG
, reg
);
109 mutex_unlock(&rt2x00dev
->csr_mutex
);
112 static void rt2800_bbp_read(struct rt2x00_dev
*rt2x00dev
,
113 const unsigned int word
, u8
*value
)
117 mutex_lock(&rt2x00dev
->csr_mutex
);
120 * Wait until the BBP becomes available, afterwards we
121 * can safely write the read request into the register.
122 * After the data has been written, we wait until hardware
123 * returns the correct value, if at any time the register
124 * doesn't become available in time, reg will be 0xffffffff
125 * which means we return 0xff to the caller.
127 if (WAIT_FOR_BBP(rt2x00dev
, ®
)) {
129 rt2x00_set_field32(®
, BBP_CSR_CFG_REGNUM
, word
);
130 rt2x00_set_field32(®
, BBP_CSR_CFG_BUSY
, 1);
131 rt2x00_set_field32(®
, BBP_CSR_CFG_READ_CONTROL
, 1);
132 rt2x00_set_field32(®
, BBP_CSR_CFG_BBP_RW_MODE
, 1);
134 rt2800_register_write_lock(rt2x00dev
, BBP_CSR_CFG
, reg
);
136 WAIT_FOR_BBP(rt2x00dev
, ®
);
139 *value
= rt2x00_get_field32(reg
, BBP_CSR_CFG_VALUE
);
141 mutex_unlock(&rt2x00dev
->csr_mutex
);
144 static void rt2800_rfcsr_write(struct rt2x00_dev
*rt2x00dev
,
145 const unsigned int word
, const u8 value
)
149 mutex_lock(&rt2x00dev
->csr_mutex
);
152 * Wait until the RFCSR becomes available, afterwards we
153 * can safely write the new data into the register.
155 if (WAIT_FOR_RFCSR(rt2x00dev
, ®
)) {
157 rt2x00_set_field32(®
, RF_CSR_CFG_DATA
, value
);
158 rt2x00_set_field32(®
, RF_CSR_CFG_REGNUM
, word
);
159 rt2x00_set_field32(®
, RF_CSR_CFG_WRITE
, 1);
160 rt2x00_set_field32(®
, RF_CSR_CFG_BUSY
, 1);
162 rt2800_register_write_lock(rt2x00dev
, RF_CSR_CFG
, reg
);
165 mutex_unlock(&rt2x00dev
->csr_mutex
);
168 static void rt2800_rfcsr_read(struct rt2x00_dev
*rt2x00dev
,
169 const unsigned int word
, u8
*value
)
173 mutex_lock(&rt2x00dev
->csr_mutex
);
176 * Wait until the RFCSR becomes available, afterwards we
177 * can safely write the read request into the register.
178 * After the data has been written, we wait until hardware
179 * returns the correct value, if at any time the register
180 * doesn't become available in time, reg will be 0xffffffff
181 * which means we return 0xff to the caller.
183 if (WAIT_FOR_RFCSR(rt2x00dev
, ®
)) {
185 rt2x00_set_field32(®
, RF_CSR_CFG_REGNUM
, word
);
186 rt2x00_set_field32(®
, RF_CSR_CFG_WRITE
, 0);
187 rt2x00_set_field32(®
, RF_CSR_CFG_BUSY
, 1);
189 rt2800_register_write_lock(rt2x00dev
, RF_CSR_CFG
, reg
);
191 WAIT_FOR_RFCSR(rt2x00dev
, ®
);
194 *value
= rt2x00_get_field32(reg
, RF_CSR_CFG_DATA
);
196 mutex_unlock(&rt2x00dev
->csr_mutex
);
199 static void rt2800_rf_write(struct rt2x00_dev
*rt2x00dev
,
200 const unsigned int word
, const u32 value
)
204 mutex_lock(&rt2x00dev
->csr_mutex
);
207 * Wait until the RF becomes available, afterwards we
208 * can safely write the new data into the register.
210 if (WAIT_FOR_RF(rt2x00dev
, ®
)) {
212 rt2x00_set_field32(®
, RF_CSR_CFG0_REG_VALUE_BW
, value
);
213 rt2x00_set_field32(®
, RF_CSR_CFG0_STANDBYMODE
, 0);
214 rt2x00_set_field32(®
, RF_CSR_CFG0_SEL
, 0);
215 rt2x00_set_field32(®
, RF_CSR_CFG0_BUSY
, 1);
217 rt2800_register_write_lock(rt2x00dev
, RF_CSR_CFG0
, reg
);
218 rt2x00_rf_write(rt2x00dev
, word
, value
);
221 mutex_unlock(&rt2x00dev
->csr_mutex
);
224 void rt2800_mcu_request(struct rt2x00_dev
*rt2x00dev
,
225 const u8 command
, const u8 token
,
226 const u8 arg0
, const u8 arg1
)
231 * SOC devices don't support MCU requests.
233 if (rt2x00_is_soc(rt2x00dev
))
236 mutex_lock(&rt2x00dev
->csr_mutex
);
239 * Wait until the MCU becomes available, afterwards we
240 * can safely write the new data into the register.
242 if (WAIT_FOR_MCU(rt2x00dev
, ®
)) {
243 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_OWNER
, 1);
244 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_CMD_TOKEN
, token
);
245 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_ARG0
, arg0
);
246 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_ARG1
, arg1
);
247 rt2800_register_write_lock(rt2x00dev
, H2M_MAILBOX_CSR
, reg
);
250 rt2x00_set_field32(®
, HOST_CMD_CSR_HOST_COMMAND
, command
);
251 rt2800_register_write_lock(rt2x00dev
, HOST_CMD_CSR
, reg
);
254 mutex_unlock(&rt2x00dev
->csr_mutex
);
256 EXPORT_SYMBOL_GPL(rt2800_mcu_request
);
258 int rt2800_wait_csr_ready(struct rt2x00_dev
*rt2x00dev
)
263 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
264 rt2800_register_read(rt2x00dev
, MAC_CSR0
, ®
);
265 if (reg
&& reg
!= ~0)
270 ERROR(rt2x00dev
, "Unstable hardware.\n");
273 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready
);
275 int rt2800_wait_wpdma_ready(struct rt2x00_dev
*rt2x00dev
)
281 * Some devices are really slow to respond here. Wait a whole second
284 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
285 rt2800_register_read(rt2x00dev
, WPDMA_GLO_CFG
, ®
);
286 if (!rt2x00_get_field32(reg
, WPDMA_GLO_CFG_TX_DMA_BUSY
) &&
287 !rt2x00_get_field32(reg
, WPDMA_GLO_CFG_RX_DMA_BUSY
))
293 ERROR(rt2x00dev
, "WPDMA TX/RX busy [0x%08x].\n", reg
);
296 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready
);
298 void rt2800_disable_wpdma(struct rt2x00_dev
*rt2x00dev
)
302 rt2800_register_read(rt2x00dev
, WPDMA_GLO_CFG
, ®
);
303 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_TX_DMA
, 0);
304 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_DMA_BUSY
, 0);
305 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_RX_DMA
, 0);
306 rt2x00_set_field32(®
, WPDMA_GLO_CFG_RX_DMA_BUSY
, 0);
307 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_WRITEBACK_DONE
, 1);
308 rt2800_register_write(rt2x00dev
, WPDMA_GLO_CFG
, reg
);
310 EXPORT_SYMBOL_GPL(rt2800_disable_wpdma
);
312 static bool rt2800_check_firmware_crc(const u8
*data
, const size_t len
)
318 * The last 2 bytes in the firmware array are the crc checksum itself,
319 * this means that we should never pass those 2 bytes to the crc
322 fw_crc
= (data
[len
- 2] << 8 | data
[len
- 1]);
325 * Use the crc ccitt algorithm.
326 * This will return the same value as the legacy driver which
327 * used bit ordering reversion on the both the firmware bytes
328 * before input input as well as on the final output.
329 * Obviously using crc ccitt directly is much more efficient.
331 crc
= crc_ccitt(~0, data
, len
- 2);
334 * There is a small difference between the crc-itu-t + bitrev and
335 * the crc-ccitt crc calculation. In the latter method the 2 bytes
336 * will be swapped, use swab16 to convert the crc to the correct
341 return fw_crc
== crc
;
344 int rt2800_check_firmware(struct rt2x00_dev
*rt2x00dev
,
345 const u8
*data
, const size_t len
)
352 * PCI(e) & SOC devices require firmware with a length
353 * of 8kb. USB devices require firmware files with a length
354 * of 4kb. Certain USB chipsets however require different firmware,
355 * which Ralink only provides attached to the original firmware
356 * file. Thus for USB devices, firmware files have a length
357 * which is a multiple of 4kb.
359 if (rt2x00_is_usb(rt2x00dev
)) {
368 * Validate the firmware length
370 if (len
!= fw_len
&& (!multiple
|| (len
% fw_len
) != 0))
371 return FW_BAD_LENGTH
;
374 * Check if the chipset requires one of the upper parts
377 if (rt2x00_is_usb(rt2x00dev
) &&
378 !rt2x00_rt(rt2x00dev
, RT2860
) &&
379 !rt2x00_rt(rt2x00dev
, RT2872
) &&
380 !rt2x00_rt(rt2x00dev
, RT3070
) &&
381 ((len
/ fw_len
) == 1))
382 return FW_BAD_VERSION
;
385 * 8kb firmware files must be checked as if it were
386 * 2 separate firmware files.
388 while (offset
< len
) {
389 if (!rt2800_check_firmware_crc(data
+ offset
, fw_len
))
397 EXPORT_SYMBOL_GPL(rt2800_check_firmware
);
399 int rt2800_load_firmware(struct rt2x00_dev
*rt2x00dev
,
400 const u8
*data
, const size_t len
)
406 * If driver doesn't wake up firmware here,
407 * rt2800_load_firmware will hang forever when interface is up again.
409 rt2800_register_write(rt2x00dev
, AUTOWAKEUP_CFG
, 0x00000000);
412 * Wait for stable hardware.
414 if (rt2800_wait_csr_ready(rt2x00dev
))
417 if (rt2x00_is_pci(rt2x00dev
)) {
418 if (rt2x00_rt(rt2x00dev
, RT3572
) ||
419 rt2x00_rt(rt2x00dev
, RT5390
) ||
420 rt2x00_rt(rt2x00dev
, RT5392
)) {
421 rt2800_register_read(rt2x00dev
, AUX_CTRL
, ®
);
422 rt2x00_set_field32(®
, AUX_CTRL_FORCE_PCIE_CLK
, 1);
423 rt2x00_set_field32(®
, AUX_CTRL_WAKE_PCIE_EN
, 1);
424 rt2800_register_write(rt2x00dev
, AUX_CTRL
, reg
);
426 rt2800_register_write(rt2x00dev
, PWR_PIN_CFG
, 0x00000002);
429 rt2800_disable_wpdma(rt2x00dev
);
432 * Write firmware to the device.
434 rt2800_drv_write_firmware(rt2x00dev
, data
, len
);
437 * Wait for device to stabilize.
439 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
440 rt2800_register_read(rt2x00dev
, PBF_SYS_CTRL
, ®
);
441 if (rt2x00_get_field32(reg
, PBF_SYS_CTRL_READY
))
446 if (i
== REGISTER_BUSY_COUNT
) {
447 ERROR(rt2x00dev
, "PBF system register not ready.\n");
452 * Disable DMA, will be reenabled later when enabling
455 rt2800_disable_wpdma(rt2x00dev
);
458 * Initialize firmware.
460 rt2800_register_write(rt2x00dev
, H2M_BBP_AGENT
, 0);
461 rt2800_register_write(rt2x00dev
, H2M_MAILBOX_CSR
, 0);
462 if (rt2x00_is_usb(rt2x00dev
))
463 rt2800_register_write(rt2x00dev
, H2M_INT_SRC
, 0);
468 EXPORT_SYMBOL_GPL(rt2800_load_firmware
);
470 void rt2800_write_tx_data(struct queue_entry
*entry
,
471 struct txentry_desc
*txdesc
)
473 __le32
*txwi
= rt2800_drv_get_txwi(entry
);
477 * Initialize TX Info descriptor
479 rt2x00_desc_read(txwi
, 0, &word
);
480 rt2x00_set_field32(&word
, TXWI_W0_FRAG
,
481 test_bit(ENTRY_TXD_MORE_FRAG
, &txdesc
->flags
));
482 rt2x00_set_field32(&word
, TXWI_W0_MIMO_PS
,
483 test_bit(ENTRY_TXD_HT_MIMO_PS
, &txdesc
->flags
));
484 rt2x00_set_field32(&word
, TXWI_W0_CF_ACK
, 0);
485 rt2x00_set_field32(&word
, TXWI_W0_TS
,
486 test_bit(ENTRY_TXD_REQ_TIMESTAMP
, &txdesc
->flags
));
487 rt2x00_set_field32(&word
, TXWI_W0_AMPDU
,
488 test_bit(ENTRY_TXD_HT_AMPDU
, &txdesc
->flags
));
489 rt2x00_set_field32(&word
, TXWI_W0_MPDU_DENSITY
,
490 txdesc
->u
.ht
.mpdu_density
);
491 rt2x00_set_field32(&word
, TXWI_W0_TX_OP
, txdesc
->u
.ht
.txop
);
492 rt2x00_set_field32(&word
, TXWI_W0_MCS
, txdesc
->u
.ht
.mcs
);
493 rt2x00_set_field32(&word
, TXWI_W0_BW
,
494 test_bit(ENTRY_TXD_HT_BW_40
, &txdesc
->flags
));
495 rt2x00_set_field32(&word
, TXWI_W0_SHORT_GI
,
496 test_bit(ENTRY_TXD_HT_SHORT_GI
, &txdesc
->flags
));
497 rt2x00_set_field32(&word
, TXWI_W0_STBC
, txdesc
->u
.ht
.stbc
);
498 rt2x00_set_field32(&word
, TXWI_W0_PHYMODE
, txdesc
->rate_mode
);
499 rt2x00_desc_write(txwi
, 0, word
);
501 rt2x00_desc_read(txwi
, 1, &word
);
502 rt2x00_set_field32(&word
, TXWI_W1_ACK
,
503 test_bit(ENTRY_TXD_ACK
, &txdesc
->flags
));
504 rt2x00_set_field32(&word
, TXWI_W1_NSEQ
,
505 test_bit(ENTRY_TXD_GENERATE_SEQ
, &txdesc
->flags
));
506 rt2x00_set_field32(&word
, TXWI_W1_BW_WIN_SIZE
, txdesc
->u
.ht
.ba_size
);
507 rt2x00_set_field32(&word
, TXWI_W1_WIRELESS_CLI_ID
,
508 test_bit(ENTRY_TXD_ENCRYPT
, &txdesc
->flags
) ?
509 txdesc
->key_idx
: txdesc
->u
.ht
.wcid
);
510 rt2x00_set_field32(&word
, TXWI_W1_MPDU_TOTAL_BYTE_COUNT
,
512 rt2x00_set_field32(&word
, TXWI_W1_PACKETID_QUEUE
, entry
->queue
->qid
);
513 rt2x00_set_field32(&word
, TXWI_W1_PACKETID_ENTRY
, (entry
->entry_idx
% 3) + 1);
514 rt2x00_desc_write(txwi
, 1, word
);
517 * Always write 0 to IV/EIV fields, hardware will insert the IV
518 * from the IVEIV register when TXD_W3_WIV is set to 0.
519 * When TXD_W3_WIV is set to 1 it will use the IV data
520 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
521 * crypto entry in the registers should be used to encrypt the frame.
523 _rt2x00_desc_write(txwi
, 2, 0 /* skbdesc->iv[0] */);
524 _rt2x00_desc_write(txwi
, 3, 0 /* skbdesc->iv[1] */);
526 EXPORT_SYMBOL_GPL(rt2800_write_tx_data
);
528 static int rt2800_agc_to_rssi(struct rt2x00_dev
*rt2x00dev
, u32 rxwi_w2
)
530 s8 rssi0
= rt2x00_get_field32(rxwi_w2
, RXWI_W2_RSSI0
);
531 s8 rssi1
= rt2x00_get_field32(rxwi_w2
, RXWI_W2_RSSI1
);
532 s8 rssi2
= rt2x00_get_field32(rxwi_w2
, RXWI_W2_RSSI2
);
538 if (rt2x00dev
->curr_band
== IEEE80211_BAND_2GHZ
) {
539 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_BG
, &eeprom
);
540 offset0
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_BG_OFFSET0
);
541 offset1
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_BG_OFFSET1
);
542 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_BG2
, &eeprom
);
543 offset2
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_BG2_OFFSET2
);
545 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_A
, &eeprom
);
546 offset0
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_A_OFFSET0
);
547 offset1
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_A_OFFSET1
);
548 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_A2
, &eeprom
);
549 offset2
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_A2_OFFSET2
);
553 * Convert the value from the descriptor into the RSSI value
554 * If the value in the descriptor is 0, it is considered invalid
555 * and the default (extremely low) rssi value is assumed
557 rssi0
= (rssi0
) ? (-12 - offset0
- rt2x00dev
->lna_gain
- rssi0
) : -128;
558 rssi1
= (rssi1
) ? (-12 - offset1
- rt2x00dev
->lna_gain
- rssi1
) : -128;
559 rssi2
= (rssi2
) ? (-12 - offset2
- rt2x00dev
->lna_gain
- rssi2
) : -128;
562 * mac80211 only accepts a single RSSI value. Calculating the
563 * average doesn't deliver a fair answer either since -60:-60 would
564 * be considered equally good as -50:-70 while the second is the one
565 * which gives less energy...
567 rssi0
= max(rssi0
, rssi1
);
568 return (int)max(rssi0
, rssi2
);
571 void rt2800_process_rxwi(struct queue_entry
*entry
,
572 struct rxdone_entry_desc
*rxdesc
)
574 __le32
*rxwi
= (__le32
*) entry
->skb
->data
;
577 rt2x00_desc_read(rxwi
, 0, &word
);
579 rxdesc
->cipher
= rt2x00_get_field32(word
, RXWI_W0_UDF
);
580 rxdesc
->size
= rt2x00_get_field32(word
, RXWI_W0_MPDU_TOTAL_BYTE_COUNT
);
582 rt2x00_desc_read(rxwi
, 1, &word
);
584 if (rt2x00_get_field32(word
, RXWI_W1_SHORT_GI
))
585 rxdesc
->flags
|= RX_FLAG_SHORT_GI
;
587 if (rt2x00_get_field32(word
, RXWI_W1_BW
))
588 rxdesc
->flags
|= RX_FLAG_40MHZ
;
591 * Detect RX rate, always use MCS as signal type.
593 rxdesc
->dev_flags
|= RXDONE_SIGNAL_MCS
;
594 rxdesc
->signal
= rt2x00_get_field32(word
, RXWI_W1_MCS
);
595 rxdesc
->rate_mode
= rt2x00_get_field32(word
, RXWI_W1_PHYMODE
);
598 * Mask of 0x8 bit to remove the short preamble flag.
600 if (rxdesc
->rate_mode
== RATE_MODE_CCK
)
601 rxdesc
->signal
&= ~0x8;
603 rt2x00_desc_read(rxwi
, 2, &word
);
606 * Convert descriptor AGC value to RSSI value.
608 rxdesc
->rssi
= rt2800_agc_to_rssi(entry
->queue
->rt2x00dev
, word
);
611 * Remove RXWI descriptor from start of buffer.
613 skb_pull(entry
->skb
, RXWI_DESC_SIZE
);
615 EXPORT_SYMBOL_GPL(rt2800_process_rxwi
);
617 void rt2800_txdone_entry(struct queue_entry
*entry
, u32 status
, __le32
*txwi
)
619 struct rt2x00_dev
*rt2x00dev
= entry
->queue
->rt2x00dev
;
620 struct skb_frame_desc
*skbdesc
= get_skb_frame_desc(entry
->skb
);
621 struct txdone_entry_desc txdesc
;
627 * Obtain the status about this packet.
630 rt2x00_desc_read(txwi
, 0, &word
);
632 mcs
= rt2x00_get_field32(word
, TXWI_W0_MCS
);
633 ampdu
= rt2x00_get_field32(word
, TXWI_W0_AMPDU
);
635 real_mcs
= rt2x00_get_field32(status
, TX_STA_FIFO_MCS
);
636 aggr
= rt2x00_get_field32(status
, TX_STA_FIFO_TX_AGGRE
);
639 * If a frame was meant to be sent as a single non-aggregated MPDU
640 * but ended up in an aggregate the used tx rate doesn't correlate
641 * with the one specified in the TXWI as the whole aggregate is sent
642 * with the same rate.
644 * For example: two frames are sent to rt2x00, the first one sets
645 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
646 * and requests MCS15. If the hw aggregates both frames into one
647 * AMDPU the tx status for both frames will contain MCS7 although
648 * the frame was sent successfully.
650 * Hence, replace the requested rate with the real tx rate to not
651 * confuse the rate control algortihm by providing clearly wrong
654 if (unlikely(aggr
== 1 && ampdu
== 0 && real_mcs
!= mcs
)) {
655 skbdesc
->tx_rate_idx
= real_mcs
;
659 if (aggr
== 1 || ampdu
== 1)
660 __set_bit(TXDONE_AMPDU
, &txdesc
.flags
);
663 * Ralink has a retry mechanism using a global fallback
664 * table. We setup this fallback table to try the immediate
665 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
666 * always contains the MCS used for the last transmission, be
667 * it successful or not.
669 if (rt2x00_get_field32(status
, TX_STA_FIFO_TX_SUCCESS
)) {
671 * Transmission succeeded. The number of retries is
674 __set_bit(TXDONE_SUCCESS
, &txdesc
.flags
);
675 txdesc
.retry
= ((mcs
> real_mcs
) ? mcs
- real_mcs
: 0);
678 * Transmission failed. The number of retries is
679 * always 7 in this case (for a total number of 8
682 __set_bit(TXDONE_FAILURE
, &txdesc
.flags
);
683 txdesc
.retry
= rt2x00dev
->long_retry
;
687 * the frame was retried at least once
688 * -> hw used fallback rates
691 __set_bit(TXDONE_FALLBACK
, &txdesc
.flags
);
693 rt2x00lib_txdone(entry
, &txdesc
);
695 EXPORT_SYMBOL_GPL(rt2800_txdone_entry
);
697 void rt2800_write_beacon(struct queue_entry
*entry
, struct txentry_desc
*txdesc
)
699 struct rt2x00_dev
*rt2x00dev
= entry
->queue
->rt2x00dev
;
700 struct skb_frame_desc
*skbdesc
= get_skb_frame_desc(entry
->skb
);
701 unsigned int beacon_base
;
702 unsigned int padding_len
;
706 * Disable beaconing while we are reloading the beacon data,
707 * otherwise we might be sending out invalid data.
709 rt2800_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
711 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_GEN
, 0);
712 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
715 * Add space for the TXWI in front of the skb.
717 memset(skb_push(entry
->skb
, TXWI_DESC_SIZE
), 0, TXWI_DESC_SIZE
);
720 * Register descriptor details in skb frame descriptor.
722 skbdesc
->flags
|= SKBDESC_DESC_IN_SKB
;
723 skbdesc
->desc
= entry
->skb
->data
;
724 skbdesc
->desc_len
= TXWI_DESC_SIZE
;
727 * Add the TXWI for the beacon to the skb.
729 rt2800_write_tx_data(entry
, txdesc
);
732 * Dump beacon to userspace through debugfs.
734 rt2x00debug_dump_frame(rt2x00dev
, DUMP_FRAME_BEACON
, entry
->skb
);
737 * Write entire beacon with TXWI and padding to register.
739 padding_len
= roundup(entry
->skb
->len
, 4) - entry
->skb
->len
;
740 if (padding_len
&& skb_pad(entry
->skb
, padding_len
)) {
741 ERROR(rt2x00dev
, "Failure padding beacon, aborting\n");
742 /* skb freed by skb_pad() on failure */
744 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, orig_reg
);
748 beacon_base
= HW_BEACON_OFFSET(entry
->entry_idx
);
749 rt2800_register_multiwrite(rt2x00dev
, beacon_base
, entry
->skb
->data
,
750 entry
->skb
->len
+ padding_len
);
753 * Enable beaconing again.
755 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_GEN
, 1);
756 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
759 * Clean up beacon skb.
761 dev_kfree_skb_any(entry
->skb
);
764 EXPORT_SYMBOL_GPL(rt2800_write_beacon
);
766 static inline void rt2800_clear_beacon_register(struct rt2x00_dev
*rt2x00dev
,
767 unsigned int beacon_base
)
772 * For the Beacon base registers we only need to clear
773 * the whole TXWI which (when set to 0) will invalidate
776 for (i
= 0; i
< TXWI_DESC_SIZE
; i
+= sizeof(__le32
))
777 rt2800_register_write(rt2x00dev
, beacon_base
+ i
, 0);
780 void rt2800_clear_beacon(struct queue_entry
*entry
)
782 struct rt2x00_dev
*rt2x00dev
= entry
->queue
->rt2x00dev
;
786 * Disable beaconing while we are reloading the beacon data,
787 * otherwise we might be sending out invalid data.
789 rt2800_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
790 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_GEN
, 0);
791 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
796 rt2800_clear_beacon_register(rt2x00dev
,
797 HW_BEACON_OFFSET(entry
->entry_idx
));
800 * Enabled beaconing again.
802 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_GEN
, 1);
803 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
805 EXPORT_SYMBOL_GPL(rt2800_clear_beacon
);
807 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
808 const struct rt2x00debug rt2800_rt2x00debug
= {
809 .owner
= THIS_MODULE
,
811 .read
= rt2800_register_read
,
812 .write
= rt2800_register_write
,
813 .flags
= RT2X00DEBUGFS_OFFSET
,
814 .word_base
= CSR_REG_BASE
,
815 .word_size
= sizeof(u32
),
816 .word_count
= CSR_REG_SIZE
/ sizeof(u32
),
819 .read
= rt2x00_eeprom_read
,
820 .write
= rt2x00_eeprom_write
,
821 .word_base
= EEPROM_BASE
,
822 .word_size
= sizeof(u16
),
823 .word_count
= EEPROM_SIZE
/ sizeof(u16
),
826 .read
= rt2800_bbp_read
,
827 .write
= rt2800_bbp_write
,
828 .word_base
= BBP_BASE
,
829 .word_size
= sizeof(u8
),
830 .word_count
= BBP_SIZE
/ sizeof(u8
),
833 .read
= rt2x00_rf_read
,
834 .write
= rt2800_rf_write
,
835 .word_base
= RF_BASE
,
836 .word_size
= sizeof(u32
),
837 .word_count
= RF_SIZE
/ sizeof(u32
),
840 .read
= rt2800_rfcsr_read
,
841 .write
= rt2800_rfcsr_write
,
842 .word_base
= RFCSR_BASE
,
843 .word_size
= sizeof(u8
),
844 .word_count
= RFCSR_SIZE
/ sizeof(u8
),
847 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug
);
848 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
850 int rt2800_rfkill_poll(struct rt2x00_dev
*rt2x00dev
)
854 rt2800_register_read(rt2x00dev
, GPIO_CTRL_CFG
, ®
);
855 return rt2x00_get_field32(reg
, GPIO_CTRL_CFG_BIT2
);
857 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll
);
859 #ifdef CONFIG_RT2X00_LIB_LEDS
860 static void rt2800_brightness_set(struct led_classdev
*led_cdev
,
861 enum led_brightness brightness
)
863 struct rt2x00_led
*led
=
864 container_of(led_cdev
, struct rt2x00_led
, led_dev
);
865 unsigned int enabled
= brightness
!= LED_OFF
;
866 unsigned int bg_mode
=
867 (enabled
&& led
->rt2x00dev
->curr_band
== IEEE80211_BAND_2GHZ
);
868 unsigned int polarity
=
869 rt2x00_get_field16(led
->rt2x00dev
->led_mcu_reg
,
870 EEPROM_FREQ_LED_POLARITY
);
871 unsigned int ledmode
=
872 rt2x00_get_field16(led
->rt2x00dev
->led_mcu_reg
,
873 EEPROM_FREQ_LED_MODE
);
876 /* Check for SoC (SOC devices don't support MCU requests) */
877 if (rt2x00_is_soc(led
->rt2x00dev
)) {
878 rt2800_register_read(led
->rt2x00dev
, LED_CFG
, ®
);
880 /* Set LED Polarity */
881 rt2x00_set_field32(®
, LED_CFG_LED_POLAR
, polarity
);
884 if (led
->type
== LED_TYPE_RADIO
) {
885 rt2x00_set_field32(®
, LED_CFG_G_LED_MODE
,
887 } else if (led
->type
== LED_TYPE_ASSOC
) {
888 rt2x00_set_field32(®
, LED_CFG_Y_LED_MODE
,
890 } else if (led
->type
== LED_TYPE_QUALITY
) {
891 rt2x00_set_field32(®
, LED_CFG_R_LED_MODE
,
895 rt2800_register_write(led
->rt2x00dev
, LED_CFG
, reg
);
898 if (led
->type
== LED_TYPE_RADIO
) {
899 rt2800_mcu_request(led
->rt2x00dev
, MCU_LED
, 0xff, ledmode
,
901 } else if (led
->type
== LED_TYPE_ASSOC
) {
902 rt2800_mcu_request(led
->rt2x00dev
, MCU_LED
, 0xff, ledmode
,
903 enabled
? (bg_mode
? 0x60 : 0xa0) : 0x20);
904 } else if (led
->type
== LED_TYPE_QUALITY
) {
906 * The brightness is divided into 6 levels (0 - 5),
907 * The specs tell us the following levels:
909 * to determine the level in a simple way we can simply
910 * work with bitshifting:
913 rt2800_mcu_request(led
->rt2x00dev
, MCU_LED_STRENGTH
, 0xff,
914 (1 << brightness
/ (LED_FULL
/ 6)) - 1,
920 static void rt2800_init_led(struct rt2x00_dev
*rt2x00dev
,
921 struct rt2x00_led
*led
, enum led_type type
)
923 led
->rt2x00dev
= rt2x00dev
;
925 led
->led_dev
.brightness_set
= rt2800_brightness_set
;
926 led
->flags
= LED_INITIALIZED
;
928 #endif /* CONFIG_RT2X00_LIB_LEDS */
931 * Configuration handlers.
933 static void rt2800_config_wcid(struct rt2x00_dev
*rt2x00dev
,
937 struct mac_wcid_entry wcid_entry
;
940 offset
= MAC_WCID_ENTRY(wcid
);
942 memset(&wcid_entry
, 0xff, sizeof(wcid_entry
));
944 memcpy(wcid_entry
.mac
, address
, ETH_ALEN
);
946 rt2800_register_multiwrite(rt2x00dev
, offset
,
947 &wcid_entry
, sizeof(wcid_entry
));
950 static void rt2800_delete_wcid_attr(struct rt2x00_dev
*rt2x00dev
, int wcid
)
953 offset
= MAC_WCID_ATTR_ENTRY(wcid
);
954 rt2800_register_write(rt2x00dev
, offset
, 0);
957 static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev
*rt2x00dev
,
958 int wcid
, u32 bssidx
)
960 u32 offset
= MAC_WCID_ATTR_ENTRY(wcid
);
964 * The BSS Idx numbers is split in a main value of 3 bits,
965 * and a extended field for adding one additional bit to the value.
967 rt2800_register_read(rt2x00dev
, offset
, ®
);
968 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_BSS_IDX
, (bssidx
& 0x7));
969 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT
,
970 (bssidx
& 0x8) >> 3);
971 rt2800_register_write(rt2x00dev
, offset
, reg
);
974 static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev
*rt2x00dev
,
975 struct rt2x00lib_crypto
*crypto
,
976 struct ieee80211_key_conf
*key
)
978 struct mac_iveiv_entry iveiv_entry
;
982 offset
= MAC_WCID_ATTR_ENTRY(key
->hw_key_idx
);
984 if (crypto
->cmd
== SET_KEY
) {
985 rt2800_register_read(rt2x00dev
, offset
, ®
);
986 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_KEYTAB
,
987 !!(key
->flags
& IEEE80211_KEY_FLAG_PAIRWISE
));
989 * Both the cipher as the BSS Idx numbers are split in a main
990 * value of 3 bits, and a extended field for adding one additional
993 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_CIPHER
,
994 (crypto
->cipher
& 0x7));
995 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_CIPHER_EXT
,
996 (crypto
->cipher
& 0x8) >> 3);
997 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_RX_WIUDF
, crypto
->cipher
);
998 rt2800_register_write(rt2x00dev
, offset
, reg
);
1000 /* Delete the cipher without touching the bssidx */
1001 rt2800_register_read(rt2x00dev
, offset
, ®
);
1002 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_KEYTAB
, 0);
1003 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_CIPHER
, 0);
1004 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_CIPHER_EXT
, 0);
1005 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_RX_WIUDF
, 0);
1006 rt2800_register_write(rt2x00dev
, offset
, reg
);
1009 offset
= MAC_IVEIV_ENTRY(key
->hw_key_idx
);
1011 memset(&iveiv_entry
, 0, sizeof(iveiv_entry
));
1012 if ((crypto
->cipher
== CIPHER_TKIP
) ||
1013 (crypto
->cipher
== CIPHER_TKIP_NO_MIC
) ||
1014 (crypto
->cipher
== CIPHER_AES
))
1015 iveiv_entry
.iv
[3] |= 0x20;
1016 iveiv_entry
.iv
[3] |= key
->keyidx
<< 6;
1017 rt2800_register_multiwrite(rt2x00dev
, offset
,
1018 &iveiv_entry
, sizeof(iveiv_entry
));
1021 int rt2800_config_shared_key(struct rt2x00_dev
*rt2x00dev
,
1022 struct rt2x00lib_crypto
*crypto
,
1023 struct ieee80211_key_conf
*key
)
1025 struct hw_key_entry key_entry
;
1026 struct rt2x00_field32 field
;
1030 if (crypto
->cmd
== SET_KEY
) {
1031 key
->hw_key_idx
= (4 * crypto
->bssidx
) + key
->keyidx
;
1033 memcpy(key_entry
.key
, crypto
->key
,
1034 sizeof(key_entry
.key
));
1035 memcpy(key_entry
.tx_mic
, crypto
->tx_mic
,
1036 sizeof(key_entry
.tx_mic
));
1037 memcpy(key_entry
.rx_mic
, crypto
->rx_mic
,
1038 sizeof(key_entry
.rx_mic
));
1040 offset
= SHARED_KEY_ENTRY(key
->hw_key_idx
);
1041 rt2800_register_multiwrite(rt2x00dev
, offset
,
1042 &key_entry
, sizeof(key_entry
));
1046 * The cipher types are stored over multiple registers
1047 * starting with SHARED_KEY_MODE_BASE each word will have
1048 * 32 bits and contains the cipher types for 2 bssidx each.
1049 * Using the correct defines correctly will cause overhead,
1050 * so just calculate the correct offset.
1052 field
.bit_offset
= 4 * (key
->hw_key_idx
% 8);
1053 field
.bit_mask
= 0x7 << field
.bit_offset
;
1055 offset
= SHARED_KEY_MODE_ENTRY(key
->hw_key_idx
/ 8);
1057 rt2800_register_read(rt2x00dev
, offset
, ®
);
1058 rt2x00_set_field32(®
, field
,
1059 (crypto
->cmd
== SET_KEY
) * crypto
->cipher
);
1060 rt2800_register_write(rt2x00dev
, offset
, reg
);
1063 * Update WCID information
1065 rt2800_config_wcid(rt2x00dev
, crypto
->address
, key
->hw_key_idx
);
1066 rt2800_config_wcid_attr_bssidx(rt2x00dev
, key
->hw_key_idx
,
1068 rt2800_config_wcid_attr_cipher(rt2x00dev
, crypto
, key
);
1072 EXPORT_SYMBOL_GPL(rt2800_config_shared_key
);
1074 static inline int rt2800_find_wcid(struct rt2x00_dev
*rt2x00dev
)
1076 struct mac_wcid_entry wcid_entry
;
1081 * Search for the first free WCID entry and return the corresponding
1084 * Make sure the WCID starts _after_ the last possible shared key
1087 * Since parts of the pairwise key table might be shared with
1088 * the beacon frame buffers 6 & 7 we should only write into the
1089 * first 222 entries.
1091 for (idx
= 33; idx
<= 222; idx
++) {
1092 offset
= MAC_WCID_ENTRY(idx
);
1093 rt2800_register_multiread(rt2x00dev
, offset
, &wcid_entry
,
1094 sizeof(wcid_entry
));
1095 if (is_broadcast_ether_addr(wcid_entry
.mac
))
1100 * Use -1 to indicate that we don't have any more space in the WCID
1106 int rt2800_config_pairwise_key(struct rt2x00_dev
*rt2x00dev
,
1107 struct rt2x00lib_crypto
*crypto
,
1108 struct ieee80211_key_conf
*key
)
1110 struct hw_key_entry key_entry
;
1113 if (crypto
->cmd
== SET_KEY
) {
1115 * Allow key configuration only for STAs that are
1118 if (crypto
->wcid
< 0)
1120 key
->hw_key_idx
= crypto
->wcid
;
1122 memcpy(key_entry
.key
, crypto
->key
,
1123 sizeof(key_entry
.key
));
1124 memcpy(key_entry
.tx_mic
, crypto
->tx_mic
,
1125 sizeof(key_entry
.tx_mic
));
1126 memcpy(key_entry
.rx_mic
, crypto
->rx_mic
,
1127 sizeof(key_entry
.rx_mic
));
1129 offset
= PAIRWISE_KEY_ENTRY(key
->hw_key_idx
);
1130 rt2800_register_multiwrite(rt2x00dev
, offset
,
1131 &key_entry
, sizeof(key_entry
));
1135 * Update WCID information
1137 rt2800_config_wcid_attr_cipher(rt2x00dev
, crypto
, key
);
1141 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key
);
1143 int rt2800_sta_add(struct rt2x00_dev
*rt2x00dev
, struct ieee80211_vif
*vif
,
1144 struct ieee80211_sta
*sta
)
1147 struct rt2x00_sta
*sta_priv
= sta_to_rt2x00_sta(sta
);
1150 * Find next free WCID.
1152 wcid
= rt2800_find_wcid(rt2x00dev
);
1155 * Store selected wcid even if it is invalid so that we can
1156 * later decide if the STA is uploaded into the hw.
1158 sta_priv
->wcid
= wcid
;
1161 * No space left in the device, however, we can still communicate
1162 * with the STA -> No error.
1168 * Clean up WCID attributes and write STA address to the device.
1170 rt2800_delete_wcid_attr(rt2x00dev
, wcid
);
1171 rt2800_config_wcid(rt2x00dev
, sta
->addr
, wcid
);
1172 rt2800_config_wcid_attr_bssidx(rt2x00dev
, wcid
,
1173 rt2x00lib_get_bssidx(rt2x00dev
, vif
));
1176 EXPORT_SYMBOL_GPL(rt2800_sta_add
);
1178 int rt2800_sta_remove(struct rt2x00_dev
*rt2x00dev
, int wcid
)
1181 * Remove WCID entry, no need to clean the attributes as they will
1182 * get renewed when the WCID is reused.
1184 rt2800_config_wcid(rt2x00dev
, NULL
, wcid
);
1188 EXPORT_SYMBOL_GPL(rt2800_sta_remove
);
1190 void rt2800_config_filter(struct rt2x00_dev
*rt2x00dev
,
1191 const unsigned int filter_flags
)
1196 * Start configuration steps.
1197 * Note that the version error will always be dropped
1198 * and broadcast frames will always be accepted since
1199 * there is no filter for it at this time.
1201 rt2800_register_read(rt2x00dev
, RX_FILTER_CFG
, ®
);
1202 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CRC_ERROR
,
1203 !(filter_flags
& FIF_FCSFAIL
));
1204 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_PHY_ERROR
,
1205 !(filter_flags
& FIF_PLCPFAIL
));
1206 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_NOT_TO_ME
,
1207 !(filter_flags
& FIF_PROMISC_IN_BSS
));
1208 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_NOT_MY_BSSD
, 0);
1209 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_VER_ERROR
, 1);
1210 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_MULTICAST
,
1211 !(filter_flags
& FIF_ALLMULTI
));
1212 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_BROADCAST
, 0);
1213 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_DUPLICATE
, 1);
1214 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CF_END_ACK
,
1215 !(filter_flags
& FIF_CONTROL
));
1216 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CF_END
,
1217 !(filter_flags
& FIF_CONTROL
));
1218 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_ACK
,
1219 !(filter_flags
& FIF_CONTROL
));
1220 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CTS
,
1221 !(filter_flags
& FIF_CONTROL
));
1222 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_RTS
,
1223 !(filter_flags
& FIF_CONTROL
));
1224 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_PSPOLL
,
1225 !(filter_flags
& FIF_PSPOLL
));
1226 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_BA
,
1227 !(filter_flags
& FIF_CONTROL
));
1228 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_BAR
,
1229 !(filter_flags
& FIF_CONTROL
));
1230 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CNTL
,
1231 !(filter_flags
& FIF_CONTROL
));
1232 rt2800_register_write(rt2x00dev
, RX_FILTER_CFG
, reg
);
1234 EXPORT_SYMBOL_GPL(rt2800_config_filter
);
1236 void rt2800_config_intf(struct rt2x00_dev
*rt2x00dev
, struct rt2x00_intf
*intf
,
1237 struct rt2x00intf_conf
*conf
, const unsigned int flags
)
1240 bool update_bssid
= false;
1242 if (flags
& CONFIG_UPDATE_TYPE
) {
1244 * Enable synchronisation.
1246 rt2800_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
1247 rt2x00_set_field32(®
, BCN_TIME_CFG_TSF_SYNC
, conf
->sync
);
1248 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
1250 if (conf
->sync
== TSF_SYNC_AP_NONE
) {
1252 * Tune beacon queue transmit parameters for AP mode
1254 rt2800_register_read(rt2x00dev
, TBTT_SYNC_CFG
, ®
);
1255 rt2x00_set_field32(®
, TBTT_SYNC_CFG_BCN_CWMIN
, 0);
1256 rt2x00_set_field32(®
, TBTT_SYNC_CFG_BCN_AIFSN
, 1);
1257 rt2x00_set_field32(®
, TBTT_SYNC_CFG_BCN_EXP_WIN
, 32);
1258 rt2x00_set_field32(®
, TBTT_SYNC_CFG_TBTT_ADJUST
, 0);
1259 rt2800_register_write(rt2x00dev
, TBTT_SYNC_CFG
, reg
);
1261 rt2800_register_read(rt2x00dev
, TBTT_SYNC_CFG
, ®
);
1262 rt2x00_set_field32(®
, TBTT_SYNC_CFG_BCN_CWMIN
, 4);
1263 rt2x00_set_field32(®
, TBTT_SYNC_CFG_BCN_AIFSN
, 2);
1264 rt2x00_set_field32(®
, TBTT_SYNC_CFG_BCN_EXP_WIN
, 32);
1265 rt2x00_set_field32(®
, TBTT_SYNC_CFG_TBTT_ADJUST
, 16);
1266 rt2800_register_write(rt2x00dev
, TBTT_SYNC_CFG
, reg
);
1270 if (flags
& CONFIG_UPDATE_MAC
) {
1271 if (flags
& CONFIG_UPDATE_TYPE
&&
1272 conf
->sync
== TSF_SYNC_AP_NONE
) {
1274 * The BSSID register has to be set to our own mac
1275 * address in AP mode.
1277 memcpy(conf
->bssid
, conf
->mac
, sizeof(conf
->mac
));
1278 update_bssid
= true;
1281 if (!is_zero_ether_addr((const u8
*)conf
->mac
)) {
1282 reg
= le32_to_cpu(conf
->mac
[1]);
1283 rt2x00_set_field32(®
, MAC_ADDR_DW1_UNICAST_TO_ME_MASK
, 0xff);
1284 conf
->mac
[1] = cpu_to_le32(reg
);
1287 rt2800_register_multiwrite(rt2x00dev
, MAC_ADDR_DW0
,
1288 conf
->mac
, sizeof(conf
->mac
));
1291 if ((flags
& CONFIG_UPDATE_BSSID
) || update_bssid
) {
1292 if (!is_zero_ether_addr((const u8
*)conf
->bssid
)) {
1293 reg
= le32_to_cpu(conf
->bssid
[1]);
1294 rt2x00_set_field32(®
, MAC_BSSID_DW1_BSS_ID_MASK
, 3);
1295 rt2x00_set_field32(®
, MAC_BSSID_DW1_BSS_BCN_NUM
, 7);
1296 conf
->bssid
[1] = cpu_to_le32(reg
);
1299 rt2800_register_multiwrite(rt2x00dev
, MAC_BSSID_DW0
,
1300 conf
->bssid
, sizeof(conf
->bssid
));
1303 EXPORT_SYMBOL_GPL(rt2800_config_intf
);
1305 static void rt2800_config_ht_opmode(struct rt2x00_dev
*rt2x00dev
,
1306 struct rt2x00lib_erp
*erp
)
1308 bool any_sta_nongf
= !!(erp
->ht_opmode
&
1309 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT
);
1310 u8 protection
= erp
->ht_opmode
& IEEE80211_HT_OP_MODE_PROTECTION
;
1311 u8 mm20_mode
, mm40_mode
, gf20_mode
, gf40_mode
;
1312 u16 mm20_rate
, mm40_rate
, gf20_rate
, gf40_rate
;
1315 /* default protection rate for HT20: OFDM 24M */
1316 mm20_rate
= gf20_rate
= 0x4004;
1318 /* default protection rate for HT40: duplicate OFDM 24M */
1319 mm40_rate
= gf40_rate
= 0x4084;
1321 switch (protection
) {
1322 case IEEE80211_HT_OP_MODE_PROTECTION_NONE
:
1324 * All STAs in this BSS are HT20/40 but there might be
1325 * STAs not supporting greenfield mode.
1326 * => Disable protection for HT transmissions.
1328 mm20_mode
= mm40_mode
= gf20_mode
= gf40_mode
= 0;
1331 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ
:
1333 * All STAs in this BSS are HT20 or HT20/40 but there
1334 * might be STAs not supporting greenfield mode.
1335 * => Protect all HT40 transmissions.
1337 mm20_mode
= gf20_mode
= 0;
1338 mm40_mode
= gf40_mode
= 2;
1341 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER
:
1343 * Nonmember protection:
1344 * According to 802.11n we _should_ protect all
1345 * HT transmissions (but we don't have to).
1347 * But if cts_protection is enabled we _shall_ protect
1348 * all HT transmissions using a CCK rate.
1350 * And if any station is non GF we _shall_ protect
1353 * We decide to protect everything
1354 * -> fall through to mixed mode.
1356 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED
:
1358 * Legacy STAs are present
1359 * => Protect all HT transmissions.
1361 mm20_mode
= mm40_mode
= gf20_mode
= gf40_mode
= 2;
1364 * If erp protection is needed we have to protect HT
1365 * transmissions with CCK 11M long preamble.
1367 if (erp
->cts_protection
) {
1368 /* don't duplicate RTS/CTS in CCK mode */
1369 mm20_rate
= mm40_rate
= 0x0003;
1370 gf20_rate
= gf40_rate
= 0x0003;
1375 /* check for STAs not supporting greenfield mode */
1377 gf20_mode
= gf40_mode
= 2;
1379 /* Update HT protection config */
1380 rt2800_register_read(rt2x00dev
, MM20_PROT_CFG
, ®
);
1381 rt2x00_set_field32(®
, MM20_PROT_CFG_PROTECT_RATE
, mm20_rate
);
1382 rt2x00_set_field32(®
, MM20_PROT_CFG_PROTECT_CTRL
, mm20_mode
);
1383 rt2800_register_write(rt2x00dev
, MM20_PROT_CFG
, reg
);
1385 rt2800_register_read(rt2x00dev
, MM40_PROT_CFG
, ®
);
1386 rt2x00_set_field32(®
, MM40_PROT_CFG_PROTECT_RATE
, mm40_rate
);
1387 rt2x00_set_field32(®
, MM40_PROT_CFG_PROTECT_CTRL
, mm40_mode
);
1388 rt2800_register_write(rt2x00dev
, MM40_PROT_CFG
, reg
);
1390 rt2800_register_read(rt2x00dev
, GF20_PROT_CFG
, ®
);
1391 rt2x00_set_field32(®
, GF20_PROT_CFG_PROTECT_RATE
, gf20_rate
);
1392 rt2x00_set_field32(®
, GF20_PROT_CFG_PROTECT_CTRL
, gf20_mode
);
1393 rt2800_register_write(rt2x00dev
, GF20_PROT_CFG
, reg
);
1395 rt2800_register_read(rt2x00dev
, GF40_PROT_CFG
, ®
);
1396 rt2x00_set_field32(®
, GF40_PROT_CFG_PROTECT_RATE
, gf40_rate
);
1397 rt2x00_set_field32(®
, GF40_PROT_CFG_PROTECT_CTRL
, gf40_mode
);
1398 rt2800_register_write(rt2x00dev
, GF40_PROT_CFG
, reg
);
1401 void rt2800_config_erp(struct rt2x00_dev
*rt2x00dev
, struct rt2x00lib_erp
*erp
,
1406 if (changed
& BSS_CHANGED_ERP_PREAMBLE
) {
1407 rt2800_register_read(rt2x00dev
, AUTO_RSP_CFG
, ®
);
1408 rt2x00_set_field32(®
, AUTO_RSP_CFG_BAC_ACK_POLICY
,
1409 !!erp
->short_preamble
);
1410 rt2x00_set_field32(®
, AUTO_RSP_CFG_AR_PREAMBLE
,
1411 !!erp
->short_preamble
);
1412 rt2800_register_write(rt2x00dev
, AUTO_RSP_CFG
, reg
);
1415 if (changed
& BSS_CHANGED_ERP_CTS_PROT
) {
1416 rt2800_register_read(rt2x00dev
, OFDM_PROT_CFG
, ®
);
1417 rt2x00_set_field32(®
, OFDM_PROT_CFG_PROTECT_CTRL
,
1418 erp
->cts_protection
? 2 : 0);
1419 rt2800_register_write(rt2x00dev
, OFDM_PROT_CFG
, reg
);
1422 if (changed
& BSS_CHANGED_BASIC_RATES
) {
1423 rt2800_register_write(rt2x00dev
, LEGACY_BASIC_RATE
,
1425 rt2800_register_write(rt2x00dev
, HT_BASIC_RATE
, 0x00008003);
1428 if (changed
& BSS_CHANGED_ERP_SLOT
) {
1429 rt2800_register_read(rt2x00dev
, BKOFF_SLOT_CFG
, ®
);
1430 rt2x00_set_field32(®
, BKOFF_SLOT_CFG_SLOT_TIME
,
1432 rt2800_register_write(rt2x00dev
, BKOFF_SLOT_CFG
, reg
);
1434 rt2800_register_read(rt2x00dev
, XIFS_TIME_CFG
, ®
);
1435 rt2x00_set_field32(®
, XIFS_TIME_CFG_EIFS
, erp
->eifs
);
1436 rt2800_register_write(rt2x00dev
, XIFS_TIME_CFG
, reg
);
1439 if (changed
& BSS_CHANGED_BEACON_INT
) {
1440 rt2800_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
1441 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_INTERVAL
,
1442 erp
->beacon_int
* 16);
1443 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
1446 if (changed
& BSS_CHANGED_HT
)
1447 rt2800_config_ht_opmode(rt2x00dev
, erp
);
1449 EXPORT_SYMBOL_GPL(rt2800_config_erp
);
1451 static void rt2800_config_3572bt_ant(struct rt2x00_dev
*rt2x00dev
)
1455 u8 led_ctrl
, led_g_mode
, led_r_mode
;
1457 rt2800_register_read(rt2x00dev
, GPIO_SWITCH
, ®
);
1458 if (rt2x00dev
->curr_band
== IEEE80211_BAND_5GHZ
) {
1459 rt2x00_set_field32(®
, GPIO_SWITCH_0
, 1);
1460 rt2x00_set_field32(®
, GPIO_SWITCH_1
, 1);
1462 rt2x00_set_field32(®
, GPIO_SWITCH_0
, 0);
1463 rt2x00_set_field32(®
, GPIO_SWITCH_1
, 0);
1465 rt2800_register_write(rt2x00dev
, GPIO_SWITCH
, reg
);
1467 rt2800_register_read(rt2x00dev
, LED_CFG
, ®
);
1468 led_g_mode
= rt2x00_get_field32(reg
, LED_CFG_LED_POLAR
) ? 3 : 0;
1469 led_r_mode
= rt2x00_get_field32(reg
, LED_CFG_LED_POLAR
) ? 0 : 3;
1470 if (led_g_mode
!= rt2x00_get_field32(reg
, LED_CFG_G_LED_MODE
) ||
1471 led_r_mode
!= rt2x00_get_field32(reg
, LED_CFG_R_LED_MODE
)) {
1472 rt2x00_eeprom_read(rt2x00dev
, EEPROM_FREQ
, &eeprom
);
1473 led_ctrl
= rt2x00_get_field16(eeprom
, EEPROM_FREQ_LED_MODE
);
1474 if (led_ctrl
== 0 || led_ctrl
> 0x40) {
1475 rt2x00_set_field32(®
, LED_CFG_G_LED_MODE
, led_g_mode
);
1476 rt2x00_set_field32(®
, LED_CFG_R_LED_MODE
, led_r_mode
);
1477 rt2800_register_write(rt2x00dev
, LED_CFG
, reg
);
1479 rt2800_mcu_request(rt2x00dev
, MCU_BAND_SELECT
, 0xff,
1480 (led_g_mode
<< 2) | led_r_mode
, 1);
1485 static void rt2800_set_ant_diversity(struct rt2x00_dev
*rt2x00dev
,
1489 u8 eesk_pin
= (ant
== ANTENNA_A
) ? 1 : 0;
1490 u8 gpio_bit3
= (ant
== ANTENNA_A
) ? 0 : 1;
1492 if (rt2x00_is_pci(rt2x00dev
)) {
1493 rt2800_register_read(rt2x00dev
, E2PROM_CSR
, ®
);
1494 rt2x00_set_field32(®
, E2PROM_CSR_DATA_CLOCK
, eesk_pin
);
1495 rt2800_register_write(rt2x00dev
, E2PROM_CSR
, reg
);
1496 } else if (rt2x00_is_usb(rt2x00dev
))
1497 rt2800_mcu_request(rt2x00dev
, MCU_ANT_SELECT
, 0xff,
1500 rt2800_register_read(rt2x00dev
, GPIO_CTRL_CFG
, ®
);
1501 rt2x00_set_field32(®
, GPIO_CTRL_CFG_GPIOD_BIT3
, 0);
1502 rt2x00_set_field32(®
, GPIO_CTRL_CFG_BIT3
, gpio_bit3
);
1503 rt2800_register_write(rt2x00dev
, GPIO_CTRL_CFG
, reg
);
1506 void rt2800_config_ant(struct rt2x00_dev
*rt2x00dev
, struct antenna_setup
*ant
)
1512 rt2800_bbp_read(rt2x00dev
, 1, &r1
);
1513 rt2800_bbp_read(rt2x00dev
, 3, &r3
);
1515 if (rt2x00_rt(rt2x00dev
, RT3572
) &&
1516 test_bit(CAPABILITY_BT_COEXIST
, &rt2x00dev
->cap_flags
))
1517 rt2800_config_3572bt_ant(rt2x00dev
);
1520 * Configure the TX antenna.
1522 switch (ant
->tx_chain_num
) {
1524 rt2x00_set_field8(&r1
, BBP1_TX_ANTENNA
, 0);
1527 if (rt2x00_rt(rt2x00dev
, RT3572
) &&
1528 test_bit(CAPABILITY_BT_COEXIST
, &rt2x00dev
->cap_flags
))
1529 rt2x00_set_field8(&r1
, BBP1_TX_ANTENNA
, 1);
1531 rt2x00_set_field8(&r1
, BBP1_TX_ANTENNA
, 2);
1534 rt2x00_set_field8(&r1
, BBP1_TX_ANTENNA
, 0);
1539 * Configure the RX antenna.
1541 switch (ant
->rx_chain_num
) {
1543 if (rt2x00_rt(rt2x00dev
, RT3070
) ||
1544 rt2x00_rt(rt2x00dev
, RT3090
) ||
1545 rt2x00_rt(rt2x00dev
, RT3390
)) {
1546 rt2x00_eeprom_read(rt2x00dev
,
1547 EEPROM_NIC_CONF1
, &eeprom
);
1548 if (rt2x00_get_field16(eeprom
,
1549 EEPROM_NIC_CONF1_ANT_DIVERSITY
))
1550 rt2800_set_ant_diversity(rt2x00dev
,
1551 rt2x00dev
->default_ant
.rx
);
1553 rt2x00_set_field8(&r3
, BBP3_RX_ANTENNA
, 0);
1556 if (rt2x00_rt(rt2x00dev
, RT3572
) &&
1557 test_bit(CAPABILITY_BT_COEXIST
, &rt2x00dev
->cap_flags
)) {
1558 rt2x00_set_field8(&r3
, BBP3_RX_ADC
, 1);
1559 rt2x00_set_field8(&r3
, BBP3_RX_ANTENNA
,
1560 rt2x00dev
->curr_band
== IEEE80211_BAND_5GHZ
);
1561 rt2800_set_ant_diversity(rt2x00dev
, ANTENNA_B
);
1563 rt2x00_set_field8(&r3
, BBP3_RX_ANTENNA
, 1);
1567 rt2x00_set_field8(&r3
, BBP3_RX_ANTENNA
, 2);
1571 rt2800_bbp_write(rt2x00dev
, 3, r3
);
1572 rt2800_bbp_write(rt2x00dev
, 1, r1
);
1574 EXPORT_SYMBOL_GPL(rt2800_config_ant
);
1576 static void rt2800_config_lna_gain(struct rt2x00_dev
*rt2x00dev
,
1577 struct rt2x00lib_conf
*libconf
)
1582 if (libconf
->rf
.channel
<= 14) {
1583 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LNA
, &eeprom
);
1584 lna_gain
= rt2x00_get_field16(eeprom
, EEPROM_LNA_BG
);
1585 } else if (libconf
->rf
.channel
<= 64) {
1586 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LNA
, &eeprom
);
1587 lna_gain
= rt2x00_get_field16(eeprom
, EEPROM_LNA_A0
);
1588 } else if (libconf
->rf
.channel
<= 128) {
1589 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_BG2
, &eeprom
);
1590 lna_gain
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_BG2_LNA_A1
);
1592 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_A2
, &eeprom
);
1593 lna_gain
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_A2_LNA_A2
);
1596 rt2x00dev
->lna_gain
= lna_gain
;
1599 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev
*rt2x00dev
,
1600 struct ieee80211_conf
*conf
,
1601 struct rf_channel
*rf
,
1602 struct channel_info
*info
)
1604 rt2x00_set_field32(&rf
->rf4
, RF4_FREQ_OFFSET
, rt2x00dev
->freq_offset
);
1606 if (rt2x00dev
->default_ant
.tx_chain_num
== 1)
1607 rt2x00_set_field32(&rf
->rf2
, RF2_ANTENNA_TX1
, 1);
1609 if (rt2x00dev
->default_ant
.rx_chain_num
== 1) {
1610 rt2x00_set_field32(&rf
->rf2
, RF2_ANTENNA_RX1
, 1);
1611 rt2x00_set_field32(&rf
->rf2
, RF2_ANTENNA_RX2
, 1);
1612 } else if (rt2x00dev
->default_ant
.rx_chain_num
== 2)
1613 rt2x00_set_field32(&rf
->rf2
, RF2_ANTENNA_RX2
, 1);
1615 if (rf
->channel
> 14) {
1617 * When TX power is below 0, we should increase it by 7 to
1618 * make it a positive value (Minimum value is -7).
1619 * However this means that values between 0 and 7 have
1620 * double meaning, and we should set a 7DBm boost flag.
1622 rt2x00_set_field32(&rf
->rf3
, RF3_TXPOWER_A_7DBM_BOOST
,
1623 (info
->default_power1
>= 0));
1625 if (info
->default_power1
< 0)
1626 info
->default_power1
+= 7;
1628 rt2x00_set_field32(&rf
->rf3
, RF3_TXPOWER_A
, info
->default_power1
);
1630 rt2x00_set_field32(&rf
->rf4
, RF4_TXPOWER_A_7DBM_BOOST
,
1631 (info
->default_power2
>= 0));
1633 if (info
->default_power2
< 0)
1634 info
->default_power2
+= 7;
1636 rt2x00_set_field32(&rf
->rf4
, RF4_TXPOWER_A
, info
->default_power2
);
1638 rt2x00_set_field32(&rf
->rf3
, RF3_TXPOWER_G
, info
->default_power1
);
1639 rt2x00_set_field32(&rf
->rf4
, RF4_TXPOWER_G
, info
->default_power2
);
1642 rt2x00_set_field32(&rf
->rf4
, RF4_HT40
, conf_is_ht40(conf
));
1644 rt2800_rf_write(rt2x00dev
, 1, rf
->rf1
);
1645 rt2800_rf_write(rt2x00dev
, 2, rf
->rf2
);
1646 rt2800_rf_write(rt2x00dev
, 3, rf
->rf3
& ~0x00000004);
1647 rt2800_rf_write(rt2x00dev
, 4, rf
->rf4
);
1651 rt2800_rf_write(rt2x00dev
, 1, rf
->rf1
);
1652 rt2800_rf_write(rt2x00dev
, 2, rf
->rf2
);
1653 rt2800_rf_write(rt2x00dev
, 3, rf
->rf3
| 0x00000004);
1654 rt2800_rf_write(rt2x00dev
, 4, rf
->rf4
);
1658 rt2800_rf_write(rt2x00dev
, 1, rf
->rf1
);
1659 rt2800_rf_write(rt2x00dev
, 2, rf
->rf2
);
1660 rt2800_rf_write(rt2x00dev
, 3, rf
->rf3
& ~0x00000004);
1661 rt2800_rf_write(rt2x00dev
, 4, rf
->rf4
);
1664 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev
*rt2x00dev
,
1665 struct ieee80211_conf
*conf
,
1666 struct rf_channel
*rf
,
1667 struct channel_info
*info
)
1669 struct rt2800_drv_data
*drv_data
= rt2x00dev
->drv_data
;
1670 u8 rfcsr
, calib_tx
, calib_rx
;
1672 rt2800_rfcsr_write(rt2x00dev
, 2, rf
->rf1
);
1674 rt2800_rfcsr_read(rt2x00dev
, 3, &rfcsr
);
1675 rt2x00_set_field8(&rfcsr
, RFCSR3_K
, rf
->rf3
);
1676 rt2800_rfcsr_write(rt2x00dev
, 3, rfcsr
);
1678 rt2800_rfcsr_read(rt2x00dev
, 6, &rfcsr
);
1679 rt2x00_set_field8(&rfcsr
, RFCSR6_R1
, rf
->rf2
);
1680 rt2800_rfcsr_write(rt2x00dev
, 6, rfcsr
);
1682 rt2800_rfcsr_read(rt2x00dev
, 12, &rfcsr
);
1683 rt2x00_set_field8(&rfcsr
, RFCSR12_TX_POWER
, info
->default_power1
);
1684 rt2800_rfcsr_write(rt2x00dev
, 12, rfcsr
);
1686 rt2800_rfcsr_read(rt2x00dev
, 13, &rfcsr
);
1687 rt2x00_set_field8(&rfcsr
, RFCSR13_TX_POWER
, info
->default_power2
);
1688 rt2800_rfcsr_write(rt2x00dev
, 13, rfcsr
);
1690 rt2800_rfcsr_read(rt2x00dev
, 1, &rfcsr
);
1691 rt2x00_set_field8(&rfcsr
, RFCSR1_RX0_PD
, 0);
1692 rt2x00_set_field8(&rfcsr
, RFCSR1_TX0_PD
, 0);
1693 if (rt2x00_rt(rt2x00dev
, RT3390
)) {
1694 rt2x00_set_field8(&rfcsr
, RFCSR1_RX1_PD
,
1695 rt2x00dev
->default_ant
.rx_chain_num
== 1);
1696 rt2x00_set_field8(&rfcsr
, RFCSR1_TX1_PD
,
1697 rt2x00dev
->default_ant
.tx_chain_num
== 1);
1699 rt2x00_set_field8(&rfcsr
, RFCSR1_RX1_PD
, 0);
1700 rt2x00_set_field8(&rfcsr
, RFCSR1_TX1_PD
, 0);
1701 rt2x00_set_field8(&rfcsr
, RFCSR1_RX2_PD
, 0);
1702 rt2x00_set_field8(&rfcsr
, RFCSR1_TX2_PD
, 0);
1704 switch (rt2x00dev
->default_ant
.tx_chain_num
) {
1706 rt2x00_set_field8(&rfcsr
, RFCSR1_TX1_PD
, 1);
1709 rt2x00_set_field8(&rfcsr
, RFCSR1_TX2_PD
, 1);
1713 switch (rt2x00dev
->default_ant
.rx_chain_num
) {
1715 rt2x00_set_field8(&rfcsr
, RFCSR1_RX1_PD
, 1);
1718 rt2x00_set_field8(&rfcsr
, RFCSR1_RX2_PD
, 1);
1722 rt2800_rfcsr_write(rt2x00dev
, 1, rfcsr
);
1724 rt2800_rfcsr_read(rt2x00dev
, 30, &rfcsr
);
1725 rt2x00_set_field8(&rfcsr
, RFCSR30_RF_CALIBRATION
, 1);
1726 rt2800_rfcsr_write(rt2x00dev
, 30, rfcsr
);
1728 rt2x00_set_field8(&rfcsr
, RFCSR30_RF_CALIBRATION
, 0);
1729 rt2800_rfcsr_write(rt2x00dev
, 30, rfcsr
);
1731 rt2800_rfcsr_read(rt2x00dev
, 23, &rfcsr
);
1732 rt2x00_set_field8(&rfcsr
, RFCSR23_FREQ_OFFSET
, rt2x00dev
->freq_offset
);
1733 rt2800_rfcsr_write(rt2x00dev
, 23, rfcsr
);
1735 if (rt2x00_rt(rt2x00dev
, RT3390
)) {
1736 calib_tx
= conf_is_ht40(conf
) ? 0x68 : 0x4f;
1737 calib_rx
= conf_is_ht40(conf
) ? 0x6f : 0x4f;
1739 if (conf_is_ht40(conf
)) {
1740 calib_tx
= drv_data
->calibration_bw40
;
1741 calib_rx
= drv_data
->calibration_bw40
;
1743 calib_tx
= drv_data
->calibration_bw20
;
1744 calib_rx
= drv_data
->calibration_bw20
;
1748 rt2800_rfcsr_read(rt2x00dev
, 24, &rfcsr
);
1749 rt2x00_set_field8(&rfcsr
, RFCSR24_TX_CALIB
, calib_tx
);
1750 rt2800_rfcsr_write(rt2x00dev
, 24, rfcsr
);
1752 rt2800_rfcsr_read(rt2x00dev
, 31, &rfcsr
);
1753 rt2x00_set_field8(&rfcsr
, RFCSR31_RX_CALIB
, calib_rx
);
1754 rt2800_rfcsr_write(rt2x00dev
, 31, rfcsr
);
1756 rt2800_rfcsr_read(rt2x00dev
, 7, &rfcsr
);
1757 rt2x00_set_field8(&rfcsr
, RFCSR7_RF_TUNING
, 1);
1758 rt2800_rfcsr_write(rt2x00dev
, 7, rfcsr
);
1760 rt2800_rfcsr_read(rt2x00dev
, 30, &rfcsr
);
1761 rt2x00_set_field8(&rfcsr
, RFCSR30_RF_CALIBRATION
, 1);
1762 rt2800_rfcsr_write(rt2x00dev
, 30, rfcsr
);
1764 rt2x00_set_field8(&rfcsr
, RFCSR30_RF_CALIBRATION
, 0);
1765 rt2800_rfcsr_write(rt2x00dev
, 30, rfcsr
);
1768 static void rt2800_config_channel_rf3052(struct rt2x00_dev
*rt2x00dev
,
1769 struct ieee80211_conf
*conf
,
1770 struct rf_channel
*rf
,
1771 struct channel_info
*info
)
1773 struct rt2800_drv_data
*drv_data
= rt2x00dev
->drv_data
;
1777 if (rf
->channel
<= 14) {
1778 rt2800_bbp_write(rt2x00dev
, 25, drv_data
->bbp25
);
1779 rt2800_bbp_write(rt2x00dev
, 26, drv_data
->bbp26
);
1781 rt2800_bbp_write(rt2x00dev
, 25, 0x09);
1782 rt2800_bbp_write(rt2x00dev
, 26, 0xff);
1785 rt2800_rfcsr_write(rt2x00dev
, 2, rf
->rf1
);
1786 rt2800_rfcsr_write(rt2x00dev
, 3, rf
->rf3
);
1788 rt2800_rfcsr_read(rt2x00dev
, 6, &rfcsr
);
1789 rt2x00_set_field8(&rfcsr
, RFCSR6_R1
, rf
->rf2
);
1790 if (rf
->channel
<= 14)
1791 rt2x00_set_field8(&rfcsr
, RFCSR6_TXDIV
, 2);
1793 rt2x00_set_field8(&rfcsr
, RFCSR6_TXDIV
, 1);
1794 rt2800_rfcsr_write(rt2x00dev
, 6, rfcsr
);
1796 rt2800_rfcsr_read(rt2x00dev
, 5, &rfcsr
);
1797 if (rf
->channel
<= 14)
1798 rt2x00_set_field8(&rfcsr
, RFCSR5_R1
, 1);
1800 rt2x00_set_field8(&rfcsr
, RFCSR5_R1
, 2);
1801 rt2800_rfcsr_write(rt2x00dev
, 5, rfcsr
);
1803 rt2800_rfcsr_read(rt2x00dev
, 12, &rfcsr
);
1804 if (rf
->channel
<= 14) {
1805 rt2x00_set_field8(&rfcsr
, RFCSR12_DR0
, 3);
1806 rt2x00_set_field8(&rfcsr
, RFCSR12_TX_POWER
,
1807 info
->default_power1
);
1809 rt2x00_set_field8(&rfcsr
, RFCSR12_DR0
, 7);
1810 rt2x00_set_field8(&rfcsr
, RFCSR12_TX_POWER
,
1811 (info
->default_power1
& 0x3) |
1812 ((info
->default_power1
& 0xC) << 1));
1814 rt2800_rfcsr_write(rt2x00dev
, 12, rfcsr
);
1816 rt2800_rfcsr_read(rt2x00dev
, 13, &rfcsr
);
1817 if (rf
->channel
<= 14) {
1818 rt2x00_set_field8(&rfcsr
, RFCSR13_DR0
, 3);
1819 rt2x00_set_field8(&rfcsr
, RFCSR13_TX_POWER
,
1820 info
->default_power2
);
1822 rt2x00_set_field8(&rfcsr
, RFCSR13_DR0
, 7);
1823 rt2x00_set_field8(&rfcsr
, RFCSR13_TX_POWER
,
1824 (info
->default_power2
& 0x3) |
1825 ((info
->default_power2
& 0xC) << 1));
1827 rt2800_rfcsr_write(rt2x00dev
, 13, rfcsr
);
1829 rt2800_rfcsr_read(rt2x00dev
, 1, &rfcsr
);
1830 rt2x00_set_field8(&rfcsr
, RFCSR1_RX0_PD
, 0);
1831 rt2x00_set_field8(&rfcsr
, RFCSR1_TX0_PD
, 0);
1832 rt2x00_set_field8(&rfcsr
, RFCSR1_RX1_PD
, 0);
1833 rt2x00_set_field8(&rfcsr
, RFCSR1_TX1_PD
, 0);
1834 rt2x00_set_field8(&rfcsr
, RFCSR1_RX2_PD
, 0);
1835 rt2x00_set_field8(&rfcsr
, RFCSR1_TX2_PD
, 0);
1836 if (test_bit(CAPABILITY_BT_COEXIST
, &rt2x00dev
->cap_flags
)) {
1837 if (rf
->channel
<= 14) {
1838 rt2x00_set_field8(&rfcsr
, RFCSR1_RX0_PD
, 1);
1839 rt2x00_set_field8(&rfcsr
, RFCSR1_TX0_PD
, 1);
1841 rt2x00_set_field8(&rfcsr
, RFCSR1_RX2_PD
, 1);
1842 rt2x00_set_field8(&rfcsr
, RFCSR1_TX2_PD
, 1);
1844 switch (rt2x00dev
->default_ant
.tx_chain_num
) {
1846 rt2x00_set_field8(&rfcsr
, RFCSR1_TX1_PD
, 1);
1848 rt2x00_set_field8(&rfcsr
, RFCSR1_TX2_PD
, 1);
1852 switch (rt2x00dev
->default_ant
.rx_chain_num
) {
1854 rt2x00_set_field8(&rfcsr
, RFCSR1_RX1_PD
, 1);
1856 rt2x00_set_field8(&rfcsr
, RFCSR1_RX2_PD
, 1);
1860 rt2800_rfcsr_write(rt2x00dev
, 1, rfcsr
);
1862 rt2800_rfcsr_read(rt2x00dev
, 23, &rfcsr
);
1863 rt2x00_set_field8(&rfcsr
, RFCSR23_FREQ_OFFSET
, rt2x00dev
->freq_offset
);
1864 rt2800_rfcsr_write(rt2x00dev
, 23, rfcsr
);
1866 if (conf_is_ht40(conf
)) {
1867 rt2800_rfcsr_write(rt2x00dev
, 24, drv_data
->calibration_bw40
);
1868 rt2800_rfcsr_write(rt2x00dev
, 31, drv_data
->calibration_bw40
);
1870 rt2800_rfcsr_write(rt2x00dev
, 24, drv_data
->calibration_bw20
);
1871 rt2800_rfcsr_write(rt2x00dev
, 31, drv_data
->calibration_bw20
);
1874 if (rf
->channel
<= 14) {
1875 rt2800_rfcsr_write(rt2x00dev
, 7, 0xd8);
1876 rt2800_rfcsr_write(rt2x00dev
, 9, 0xc3);
1877 rt2800_rfcsr_write(rt2x00dev
, 10, 0xf1);
1878 rt2800_rfcsr_write(rt2x00dev
, 11, 0xb9);
1879 rt2800_rfcsr_write(rt2x00dev
, 15, 0x53);
1881 rt2x00_set_field8(&rfcsr
, RFCSR16_TXMIXER_GAIN
,
1882 drv_data
->txmixer_gain_24g
);
1883 rt2800_rfcsr_write(rt2x00dev
, 16, rfcsr
);
1884 rt2800_rfcsr_write(rt2x00dev
, 17, 0x23);
1885 rt2800_rfcsr_write(rt2x00dev
, 19, 0x93);
1886 rt2800_rfcsr_write(rt2x00dev
, 20, 0xb3);
1887 rt2800_rfcsr_write(rt2x00dev
, 25, 0x15);
1888 rt2800_rfcsr_write(rt2x00dev
, 26, 0x85);
1889 rt2800_rfcsr_write(rt2x00dev
, 27, 0x00);
1890 rt2800_rfcsr_write(rt2x00dev
, 29, 0x9b);
1892 rt2800_rfcsr_read(rt2x00dev
, 7, &rfcsr
);
1893 rt2x00_set_field8(&rfcsr
, RFCSR7_BIT2
, 1);
1894 rt2x00_set_field8(&rfcsr
, RFCSR7_BIT3
, 0);
1895 rt2x00_set_field8(&rfcsr
, RFCSR7_BIT4
, 1);
1896 rt2x00_set_field8(&rfcsr
, RFCSR7_BITS67
, 0);
1897 rt2800_rfcsr_write(rt2x00dev
, 7, rfcsr
);
1898 rt2800_rfcsr_write(rt2x00dev
, 9, 0xc0);
1899 rt2800_rfcsr_write(rt2x00dev
, 10, 0xf1);
1900 rt2800_rfcsr_write(rt2x00dev
, 11, 0x00);
1901 rt2800_rfcsr_write(rt2x00dev
, 15, 0x43);
1903 rt2x00_set_field8(&rfcsr
, RFCSR16_TXMIXER_GAIN
,
1904 drv_data
->txmixer_gain_5g
);
1905 rt2800_rfcsr_write(rt2x00dev
, 16, rfcsr
);
1906 rt2800_rfcsr_write(rt2x00dev
, 17, 0x23);
1907 if (rf
->channel
<= 64) {
1908 rt2800_rfcsr_write(rt2x00dev
, 19, 0xb7);
1909 rt2800_rfcsr_write(rt2x00dev
, 20, 0xf6);
1910 rt2800_rfcsr_write(rt2x00dev
, 25, 0x3d);
1911 } else if (rf
->channel
<= 128) {
1912 rt2800_rfcsr_write(rt2x00dev
, 19, 0x74);
1913 rt2800_rfcsr_write(rt2x00dev
, 20, 0xf4);
1914 rt2800_rfcsr_write(rt2x00dev
, 25, 0x01);
1916 rt2800_rfcsr_write(rt2x00dev
, 19, 0x72);
1917 rt2800_rfcsr_write(rt2x00dev
, 20, 0xf3);
1918 rt2800_rfcsr_write(rt2x00dev
, 25, 0x01);
1920 rt2800_rfcsr_write(rt2x00dev
, 26, 0x87);
1921 rt2800_rfcsr_write(rt2x00dev
, 27, 0x01);
1922 rt2800_rfcsr_write(rt2x00dev
, 29, 0x9f);
1925 rt2800_register_read(rt2x00dev
, GPIO_CTRL_CFG
, ®
);
1926 rt2x00_set_field32(®
, GPIO_CTRL_CFG_GPIOD_BIT7
, 0);
1927 if (rf
->channel
<= 14)
1928 rt2x00_set_field32(®
, GPIO_CTRL_CFG_BIT7
, 1);
1930 rt2x00_set_field32(®
, GPIO_CTRL_CFG_BIT7
, 0);
1931 rt2800_register_write(rt2x00dev
, GPIO_CTRL_CFG
, reg
);
1933 rt2800_rfcsr_read(rt2x00dev
, 7, &rfcsr
);
1934 rt2x00_set_field8(&rfcsr
, RFCSR7_RF_TUNING
, 1);
1935 rt2800_rfcsr_write(rt2x00dev
, 7, rfcsr
);
1938 #define RT5390_POWER_BOUND 0x27
1939 #define RT5390_FREQ_OFFSET_BOUND 0x5f
1941 static void rt2800_config_channel_rf53xx(struct rt2x00_dev
*rt2x00dev
,
1942 struct ieee80211_conf
*conf
,
1943 struct rf_channel
*rf
,
1944 struct channel_info
*info
)
1948 rt2800_rfcsr_write(rt2x00dev
, 8, rf
->rf1
);
1949 rt2800_rfcsr_write(rt2x00dev
, 9, rf
->rf3
);
1950 rt2800_rfcsr_read(rt2x00dev
, 11, &rfcsr
);
1951 rt2x00_set_field8(&rfcsr
, RFCSR11_R
, rf
->rf2
);
1952 rt2800_rfcsr_write(rt2x00dev
, 11, rfcsr
);
1954 rt2800_rfcsr_read(rt2x00dev
, 49, &rfcsr
);
1955 if (info
->default_power1
> RT5390_POWER_BOUND
)
1956 rt2x00_set_field8(&rfcsr
, RFCSR49_TX
, RT5390_POWER_BOUND
);
1958 rt2x00_set_field8(&rfcsr
, RFCSR49_TX
, info
->default_power1
);
1959 rt2800_rfcsr_write(rt2x00dev
, 49, rfcsr
);
1961 rt2800_rfcsr_read(rt2x00dev
, 1, &rfcsr
);
1962 rt2x00_set_field8(&rfcsr
, RFCSR1_RF_BLOCK_EN
, 1);
1963 rt2x00_set_field8(&rfcsr
, RFCSR1_PLL_PD
, 1);
1964 rt2x00_set_field8(&rfcsr
, RFCSR1_RX0_PD
, 1);
1965 rt2x00_set_field8(&rfcsr
, RFCSR1_TX0_PD
, 1);
1966 rt2800_rfcsr_write(rt2x00dev
, 1, rfcsr
);
1968 rt2800_rfcsr_read(rt2x00dev
, 17, &rfcsr
);
1969 if (rt2x00dev
->freq_offset
> RT5390_FREQ_OFFSET_BOUND
)
1970 rt2x00_set_field8(&rfcsr
, RFCSR17_CODE
,
1971 RT5390_FREQ_OFFSET_BOUND
);
1973 rt2x00_set_field8(&rfcsr
, RFCSR17_CODE
, rt2x00dev
->freq_offset
);
1974 rt2800_rfcsr_write(rt2x00dev
, 17, rfcsr
);
1976 if (rf
->channel
<= 14) {
1977 int idx
= rf
->channel
-1;
1979 if (test_bit(CAPABILITY_BT_COEXIST
, &rt2x00dev
->cap_flags
)) {
1980 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390F
)) {
1981 /* r55/r59 value array of channel 1~14 */
1982 static const char r55_bt_rev
[] = {0x83, 0x83,
1983 0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
1984 0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
1985 static const char r59_bt_rev
[] = {0x0e, 0x0e,
1986 0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
1987 0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
1989 rt2800_rfcsr_write(rt2x00dev
, 55,
1991 rt2800_rfcsr_write(rt2x00dev
, 59,
1994 static const char r59_bt
[] = {0x8b, 0x8b, 0x8b,
1995 0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
1996 0x88, 0x88, 0x86, 0x85, 0x84};
1998 rt2800_rfcsr_write(rt2x00dev
, 59, r59_bt
[idx
]);
2001 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390F
)) {
2002 static const char r55_nonbt_rev
[] = {0x23, 0x23,
2003 0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
2004 0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
2005 static const char r59_nonbt_rev
[] = {0x07, 0x07,
2006 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
2007 0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
2009 rt2800_rfcsr_write(rt2x00dev
, 55,
2010 r55_nonbt_rev
[idx
]);
2011 rt2800_rfcsr_write(rt2x00dev
, 59,
2012 r59_nonbt_rev
[idx
]);
2013 } else if (rt2x00_rt(rt2x00dev
, RT5390
) ||
2014 rt2x00_rt(rt2x00dev
, RT5392
)) {
2015 static const char r59_non_bt
[] = {0x8f, 0x8f,
2016 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
2017 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
2019 rt2800_rfcsr_write(rt2x00dev
, 59,
2025 rt2800_rfcsr_read(rt2x00dev
, 30, &rfcsr
);
2026 rt2x00_set_field8(&rfcsr
, RFCSR30_TX_H20M
, 0);
2027 rt2x00_set_field8(&rfcsr
, RFCSR30_RX_H20M
, 0);
2028 rt2800_rfcsr_write(rt2x00dev
, 30, rfcsr
);
2030 rt2800_rfcsr_read(rt2x00dev
, 3, &rfcsr
);
2031 rt2x00_set_field8(&rfcsr
, RFCSR30_RF_CALIBRATION
, 1);
2032 rt2800_rfcsr_write(rt2x00dev
, 3, rfcsr
);
2035 static void rt2800_config_channel(struct rt2x00_dev
*rt2x00dev
,
2036 struct ieee80211_conf
*conf
,
2037 struct rf_channel
*rf
,
2038 struct channel_info
*info
)
2041 unsigned int tx_pin
;
2044 if (rf
->channel
<= 14) {
2045 info
->default_power1
= TXPOWER_G_TO_DEV(info
->default_power1
);
2046 info
->default_power2
= TXPOWER_G_TO_DEV(info
->default_power2
);
2048 info
->default_power1
= TXPOWER_A_TO_DEV(info
->default_power1
);
2049 info
->default_power2
= TXPOWER_A_TO_DEV(info
->default_power2
);
2052 switch (rt2x00dev
->chip
.rf
) {
2058 rt2800_config_channel_rf3xxx(rt2x00dev
, conf
, rf
, info
);
2061 rt2800_config_channel_rf3052(rt2x00dev
, conf
, rf
, info
);
2066 rt2800_config_channel_rf53xx(rt2x00dev
, conf
, rf
, info
);
2069 rt2800_config_channel_rf2xxx(rt2x00dev
, conf
, rf
, info
);
2073 * Change BBP settings
2075 rt2800_bbp_write(rt2x00dev
, 62, 0x37 - rt2x00dev
->lna_gain
);
2076 rt2800_bbp_write(rt2x00dev
, 63, 0x37 - rt2x00dev
->lna_gain
);
2077 rt2800_bbp_write(rt2x00dev
, 64, 0x37 - rt2x00dev
->lna_gain
);
2078 rt2800_bbp_write(rt2x00dev
, 86, 0);
2080 if (rf
->channel
<= 14) {
2081 if (!rt2x00_rt(rt2x00dev
, RT5390
) &&
2082 !rt2x00_rt(rt2x00dev
, RT5392
)) {
2083 if (test_bit(CAPABILITY_EXTERNAL_LNA_BG
,
2084 &rt2x00dev
->cap_flags
)) {
2085 rt2800_bbp_write(rt2x00dev
, 82, 0x62);
2086 rt2800_bbp_write(rt2x00dev
, 75, 0x46);
2088 rt2800_bbp_write(rt2x00dev
, 82, 0x84);
2089 rt2800_bbp_write(rt2x00dev
, 75, 0x50);
2093 if (rt2x00_rt(rt2x00dev
, RT3572
))
2094 rt2800_bbp_write(rt2x00dev
, 82, 0x94);
2096 rt2800_bbp_write(rt2x00dev
, 82, 0xf2);
2098 if (test_bit(CAPABILITY_EXTERNAL_LNA_A
, &rt2x00dev
->cap_flags
))
2099 rt2800_bbp_write(rt2x00dev
, 75, 0x46);
2101 rt2800_bbp_write(rt2x00dev
, 75, 0x50);
2104 rt2800_register_read(rt2x00dev
, TX_BAND_CFG
, ®
);
2105 rt2x00_set_field32(®
, TX_BAND_CFG_HT40_MINUS
, conf_is_ht40_minus(conf
));
2106 rt2x00_set_field32(®
, TX_BAND_CFG_A
, rf
->channel
> 14);
2107 rt2x00_set_field32(®
, TX_BAND_CFG_BG
, rf
->channel
<= 14);
2108 rt2800_register_write(rt2x00dev
, TX_BAND_CFG
, reg
);
2110 if (rt2x00_rt(rt2x00dev
, RT3572
))
2111 rt2800_rfcsr_write(rt2x00dev
, 8, 0);
2115 /* Turn on unused PA or LNA when not using 1T or 1R */
2116 if (rt2x00dev
->default_ant
.tx_chain_num
== 2) {
2117 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_A1_EN
,
2119 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_G1_EN
,
2123 /* Turn on unused PA or LNA when not using 1T or 1R */
2124 if (rt2x00dev
->default_ant
.rx_chain_num
== 2) {
2125 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_LNA_PE_A1_EN
, 1);
2126 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_LNA_PE_G1_EN
, 1);
2129 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_LNA_PE_A0_EN
, 1);
2130 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_LNA_PE_G0_EN
, 1);
2131 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_RFTR_EN
, 1);
2132 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_TRSW_EN
, 1);
2133 if (test_bit(CAPABILITY_BT_COEXIST
, &rt2x00dev
->cap_flags
))
2134 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_G0_EN
, 1);
2136 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_G0_EN
,
2138 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_A0_EN
, rf
->channel
> 14);
2140 rt2800_register_write(rt2x00dev
, TX_PIN_CFG
, tx_pin
);
2142 if (rt2x00_rt(rt2x00dev
, RT3572
))
2143 rt2800_rfcsr_write(rt2x00dev
, 8, 0x80);
2145 rt2800_bbp_read(rt2x00dev
, 4, &bbp
);
2146 rt2x00_set_field8(&bbp
, BBP4_BANDWIDTH
, 2 * conf_is_ht40(conf
));
2147 rt2800_bbp_write(rt2x00dev
, 4, bbp
);
2149 rt2800_bbp_read(rt2x00dev
, 3, &bbp
);
2150 rt2x00_set_field8(&bbp
, BBP3_HT40_MINUS
, conf_is_ht40_minus(conf
));
2151 rt2800_bbp_write(rt2x00dev
, 3, bbp
);
2153 if (rt2x00_rt_rev(rt2x00dev
, RT2860
, REV_RT2860C
)) {
2154 if (conf_is_ht40(conf
)) {
2155 rt2800_bbp_write(rt2x00dev
, 69, 0x1a);
2156 rt2800_bbp_write(rt2x00dev
, 70, 0x0a);
2157 rt2800_bbp_write(rt2x00dev
, 73, 0x16);
2159 rt2800_bbp_write(rt2x00dev
, 69, 0x16);
2160 rt2800_bbp_write(rt2x00dev
, 70, 0x08);
2161 rt2800_bbp_write(rt2x00dev
, 73, 0x11);
2168 * Clear channel statistic counters
2170 rt2800_register_read(rt2x00dev
, CH_IDLE_STA
, ®
);
2171 rt2800_register_read(rt2x00dev
, CH_BUSY_STA
, ®
);
2172 rt2800_register_read(rt2x00dev
, CH_BUSY_STA_SEC
, ®
);
2175 static int rt2800_get_gain_calibration_delta(struct rt2x00_dev
*rt2x00dev
)
2184 * Read TSSI boundaries for temperature compensation from
2187 * Array idx 0 1 2 3 4 5 6 7 8
2188 * Matching Delta value -4 -3 -2 -1 0 +1 +2 +3 +4
2189 * Example TSSI bounds 0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
2191 if (rt2x00dev
->curr_band
== IEEE80211_BAND_2GHZ
) {
2192 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_BG1
, &eeprom
);
2193 tssi_bounds
[0] = rt2x00_get_field16(eeprom
,
2194 EEPROM_TSSI_BOUND_BG1_MINUS4
);
2195 tssi_bounds
[1] = rt2x00_get_field16(eeprom
,
2196 EEPROM_TSSI_BOUND_BG1_MINUS3
);
2198 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_BG2
, &eeprom
);
2199 tssi_bounds
[2] = rt2x00_get_field16(eeprom
,
2200 EEPROM_TSSI_BOUND_BG2_MINUS2
);
2201 tssi_bounds
[3] = rt2x00_get_field16(eeprom
,
2202 EEPROM_TSSI_BOUND_BG2_MINUS1
);
2204 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_BG3
, &eeprom
);
2205 tssi_bounds
[4] = rt2x00_get_field16(eeprom
,
2206 EEPROM_TSSI_BOUND_BG3_REF
);
2207 tssi_bounds
[5] = rt2x00_get_field16(eeprom
,
2208 EEPROM_TSSI_BOUND_BG3_PLUS1
);
2210 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_BG4
, &eeprom
);
2211 tssi_bounds
[6] = rt2x00_get_field16(eeprom
,
2212 EEPROM_TSSI_BOUND_BG4_PLUS2
);
2213 tssi_bounds
[7] = rt2x00_get_field16(eeprom
,
2214 EEPROM_TSSI_BOUND_BG4_PLUS3
);
2216 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_BG5
, &eeprom
);
2217 tssi_bounds
[8] = rt2x00_get_field16(eeprom
,
2218 EEPROM_TSSI_BOUND_BG5_PLUS4
);
2220 step
= rt2x00_get_field16(eeprom
,
2221 EEPROM_TSSI_BOUND_BG5_AGC_STEP
);
2223 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_A1
, &eeprom
);
2224 tssi_bounds
[0] = rt2x00_get_field16(eeprom
,
2225 EEPROM_TSSI_BOUND_A1_MINUS4
);
2226 tssi_bounds
[1] = rt2x00_get_field16(eeprom
,
2227 EEPROM_TSSI_BOUND_A1_MINUS3
);
2229 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_A2
, &eeprom
);
2230 tssi_bounds
[2] = rt2x00_get_field16(eeprom
,
2231 EEPROM_TSSI_BOUND_A2_MINUS2
);
2232 tssi_bounds
[3] = rt2x00_get_field16(eeprom
,
2233 EEPROM_TSSI_BOUND_A2_MINUS1
);
2235 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_A3
, &eeprom
);
2236 tssi_bounds
[4] = rt2x00_get_field16(eeprom
,
2237 EEPROM_TSSI_BOUND_A3_REF
);
2238 tssi_bounds
[5] = rt2x00_get_field16(eeprom
,
2239 EEPROM_TSSI_BOUND_A3_PLUS1
);
2241 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_A4
, &eeprom
);
2242 tssi_bounds
[6] = rt2x00_get_field16(eeprom
,
2243 EEPROM_TSSI_BOUND_A4_PLUS2
);
2244 tssi_bounds
[7] = rt2x00_get_field16(eeprom
,
2245 EEPROM_TSSI_BOUND_A4_PLUS3
);
2247 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_A5
, &eeprom
);
2248 tssi_bounds
[8] = rt2x00_get_field16(eeprom
,
2249 EEPROM_TSSI_BOUND_A5_PLUS4
);
2251 step
= rt2x00_get_field16(eeprom
,
2252 EEPROM_TSSI_BOUND_A5_AGC_STEP
);
2256 * Check if temperature compensation is supported.
2258 if (tssi_bounds
[4] == 0xff)
2262 * Read current TSSI (BBP 49).
2264 rt2800_bbp_read(rt2x00dev
, 49, ¤t_tssi
);
2267 * Compare TSSI value (BBP49) with the compensation boundaries
2268 * from the EEPROM and increase or decrease tx power.
2270 for (i
= 0; i
<= 3; i
++) {
2271 if (current_tssi
> tssi_bounds
[i
])
2276 for (i
= 8; i
>= 5; i
--) {
2277 if (current_tssi
< tssi_bounds
[i
])
2282 return (i
- 4) * step
;
2285 static int rt2800_get_txpower_bw_comp(struct rt2x00_dev
*rt2x00dev
,
2286 enum ieee80211_band band
)
2293 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TXPOWER_DELTA
, &eeprom
);
2296 * HT40 compensation not required.
2298 if (eeprom
== 0xffff ||
2299 !test_bit(CONFIG_CHANNEL_HT40
, &rt2x00dev
->flags
))
2302 if (band
== IEEE80211_BAND_2GHZ
) {
2303 comp_en
= rt2x00_get_field16(eeprom
,
2304 EEPROM_TXPOWER_DELTA_ENABLE_2G
);
2306 comp_type
= rt2x00_get_field16(eeprom
,
2307 EEPROM_TXPOWER_DELTA_TYPE_2G
);
2308 comp_value
= rt2x00_get_field16(eeprom
,
2309 EEPROM_TXPOWER_DELTA_VALUE_2G
);
2311 comp_value
= -comp_value
;
2314 comp_en
= rt2x00_get_field16(eeprom
,
2315 EEPROM_TXPOWER_DELTA_ENABLE_5G
);
2317 comp_type
= rt2x00_get_field16(eeprom
,
2318 EEPROM_TXPOWER_DELTA_TYPE_5G
);
2319 comp_value
= rt2x00_get_field16(eeprom
,
2320 EEPROM_TXPOWER_DELTA_VALUE_5G
);
2322 comp_value
= -comp_value
;
2329 static u8
rt2800_compensate_txpower(struct rt2x00_dev
*rt2x00dev
, int is_rate_b
,
2330 enum ieee80211_band band
, int power_level
,
2331 u8 txpower
, int delta
)
2337 u8 eirp_txpower_criterion
;
2340 if (!((band
== IEEE80211_BAND_5GHZ
) && is_rate_b
))
2343 if (test_bit(CAPABILITY_POWER_LIMIT
, &rt2x00dev
->cap_flags
)) {
2345 * Check if eirp txpower exceed txpower_limit.
2346 * We use OFDM 6M as criterion and its eirp txpower
2347 * is stored at EEPROM_EIRP_MAX_TX_POWER.
2348 * .11b data rate need add additional 4dbm
2349 * when calculating eirp txpower.
2351 rt2800_register_read(rt2x00dev
, TX_PWR_CFG_0
, ®
);
2352 criterion
= rt2x00_get_field32(reg
, TX_PWR_CFG_0_6MBS
);
2354 rt2x00_eeprom_read(rt2x00dev
,
2355 EEPROM_EIRP_MAX_TX_POWER
, &eeprom
);
2357 if (band
== IEEE80211_BAND_2GHZ
)
2358 eirp_txpower_criterion
= rt2x00_get_field16(eeprom
,
2359 EEPROM_EIRP_MAX_TX_POWER_2GHZ
);
2361 eirp_txpower_criterion
= rt2x00_get_field16(eeprom
,
2362 EEPROM_EIRP_MAX_TX_POWER_5GHZ
);
2364 eirp_txpower
= eirp_txpower_criterion
+ (txpower
- criterion
) +
2365 (is_rate_b
? 4 : 0) + delta
;
2367 reg_limit
= (eirp_txpower
> power_level
) ?
2368 (eirp_txpower
- power_level
) : 0;
2372 return txpower
+ delta
- reg_limit
;
2375 static void rt2800_config_txpower(struct rt2x00_dev
*rt2x00dev
,
2376 enum ieee80211_band band
,
2388 * Calculate HT40 compensation delta
2390 delta
= rt2800_get_txpower_bw_comp(rt2x00dev
, band
);
2393 * calculate temperature compensation delta
2395 delta
+= rt2800_get_gain_calibration_delta(rt2x00dev
);
2398 * set to normal bbp tx power control mode: +/- 0dBm
2400 rt2800_bbp_read(rt2x00dev
, 1, &r1
);
2401 rt2x00_set_field8(&r1
, BBP1_TX_POWER_CTRL
, 0);
2402 rt2800_bbp_write(rt2x00dev
, 1, r1
);
2403 offset
= TX_PWR_CFG_0
;
2405 for (i
= 0; i
< EEPROM_TXPOWER_BYRATE_SIZE
; i
+= 2) {
2406 /* just to be safe */
2407 if (offset
> TX_PWR_CFG_4
)
2410 rt2800_register_read(rt2x00dev
, offset
, ®
);
2412 /* read the next four txpower values */
2413 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TXPOWER_BYRATE
+ i
,
2416 is_rate_b
= i
? 0 : 1;
2418 * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
2419 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
2420 * TX_PWR_CFG_4: unknown
2422 txpower
= rt2x00_get_field16(eeprom
,
2423 EEPROM_TXPOWER_BYRATE_RATE0
);
2424 txpower
= rt2800_compensate_txpower(rt2x00dev
, is_rate_b
, band
,
2425 power_level
, txpower
, delta
);
2426 rt2x00_set_field32(®
, TX_PWR_CFG_RATE0
, txpower
);
2429 * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
2430 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
2431 * TX_PWR_CFG_4: unknown
2433 txpower
= rt2x00_get_field16(eeprom
,
2434 EEPROM_TXPOWER_BYRATE_RATE1
);
2435 txpower
= rt2800_compensate_txpower(rt2x00dev
, is_rate_b
, band
,
2436 power_level
, txpower
, delta
);
2437 rt2x00_set_field32(®
, TX_PWR_CFG_RATE1
, txpower
);
2440 * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
2441 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14,
2442 * TX_PWR_CFG_4: unknown
2444 txpower
= rt2x00_get_field16(eeprom
,
2445 EEPROM_TXPOWER_BYRATE_RATE2
);
2446 txpower
= rt2800_compensate_txpower(rt2x00dev
, is_rate_b
, band
,
2447 power_level
, txpower
, delta
);
2448 rt2x00_set_field32(®
, TX_PWR_CFG_RATE2
, txpower
);
2451 * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
2452 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15,
2453 * TX_PWR_CFG_4: unknown
2455 txpower
= rt2x00_get_field16(eeprom
,
2456 EEPROM_TXPOWER_BYRATE_RATE3
);
2457 txpower
= rt2800_compensate_txpower(rt2x00dev
, is_rate_b
, band
,
2458 power_level
, txpower
, delta
);
2459 rt2x00_set_field32(®
, TX_PWR_CFG_RATE3
, txpower
);
2461 /* read the next four txpower values */
2462 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TXPOWER_BYRATE
+ i
+ 1,
2467 * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
2468 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
2469 * TX_PWR_CFG_4: unknown
2471 txpower
= rt2x00_get_field16(eeprom
,
2472 EEPROM_TXPOWER_BYRATE_RATE0
);
2473 txpower
= rt2800_compensate_txpower(rt2x00dev
, is_rate_b
, band
,
2474 power_level
, txpower
, delta
);
2475 rt2x00_set_field32(®
, TX_PWR_CFG_RATE4
, txpower
);
2478 * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
2479 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
2480 * TX_PWR_CFG_4: unknown
2482 txpower
= rt2x00_get_field16(eeprom
,
2483 EEPROM_TXPOWER_BYRATE_RATE1
);
2484 txpower
= rt2800_compensate_txpower(rt2x00dev
, is_rate_b
, band
,
2485 power_level
, txpower
, delta
);
2486 rt2x00_set_field32(®
, TX_PWR_CFG_RATE5
, txpower
);
2489 * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
2490 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
2491 * TX_PWR_CFG_4: unknown
2493 txpower
= rt2x00_get_field16(eeprom
,
2494 EEPROM_TXPOWER_BYRATE_RATE2
);
2495 txpower
= rt2800_compensate_txpower(rt2x00dev
, is_rate_b
, band
,
2496 power_level
, txpower
, delta
);
2497 rt2x00_set_field32(®
, TX_PWR_CFG_RATE6
, txpower
);
2500 * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
2501 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
2502 * TX_PWR_CFG_4: unknown
2504 txpower
= rt2x00_get_field16(eeprom
,
2505 EEPROM_TXPOWER_BYRATE_RATE3
);
2506 txpower
= rt2800_compensate_txpower(rt2x00dev
, is_rate_b
, band
,
2507 power_level
, txpower
, delta
);
2508 rt2x00_set_field32(®
, TX_PWR_CFG_RATE7
, txpower
);
2510 rt2800_register_write(rt2x00dev
, offset
, reg
);
2512 /* next TX_PWR_CFG register */
2517 void rt2800_gain_calibration(struct rt2x00_dev
*rt2x00dev
)
2519 rt2800_config_txpower(rt2x00dev
, rt2x00dev
->curr_band
,
2520 rt2x00dev
->tx_power
);
2522 EXPORT_SYMBOL_GPL(rt2800_gain_calibration
);
2524 void rt2800_vco_calibration(struct rt2x00_dev
*rt2x00dev
)
2530 * A voltage-controlled oscillator(VCO) is an electronic oscillator
2531 * designed to be controlled in oscillation frequency by a voltage
2532 * input. Maybe the temperature will affect the frequency of
2533 * oscillation to be shifted. The VCO calibration will be called
2534 * periodically to adjust the frequency to be precision.
2537 rt2800_register_read(rt2x00dev
, TX_PIN_CFG
, &tx_pin
);
2538 tx_pin
&= TX_PIN_CFG_PA_PE_DISABLE
;
2539 rt2800_register_write(rt2x00dev
, TX_PIN_CFG
, tx_pin
);
2541 switch (rt2x00dev
->chip
.rf
) {
2548 rt2800_rfcsr_read(rt2x00dev
, 7, &rfcsr
);
2549 rt2x00_set_field8(&rfcsr
, RFCSR7_RF_TUNING
, 1);
2550 rt2800_rfcsr_write(rt2x00dev
, 7, rfcsr
);
2555 rt2800_rfcsr_read(rt2x00dev
, 3, &rfcsr
);
2556 rt2x00_set_field8(&rfcsr
, RFCSR30_RF_CALIBRATION
, 1);
2557 rt2800_rfcsr_write(rt2x00dev
, 3, rfcsr
);
2565 rt2800_register_read(rt2x00dev
, TX_PIN_CFG
, &tx_pin
);
2566 if (rt2x00dev
->rf_channel
<= 14) {
2567 switch (rt2x00dev
->default_ant
.tx_chain_num
) {
2569 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_G2_EN
, 1);
2572 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_G1_EN
, 1);
2576 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_G0_EN
, 1);
2580 switch (rt2x00dev
->default_ant
.tx_chain_num
) {
2582 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_A2_EN
, 1);
2585 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_A1_EN
, 1);
2589 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_A0_EN
, 1);
2593 rt2800_register_write(rt2x00dev
, TX_PIN_CFG
, tx_pin
);
2596 EXPORT_SYMBOL_GPL(rt2800_vco_calibration
);
2598 static void rt2800_config_retry_limit(struct rt2x00_dev
*rt2x00dev
,
2599 struct rt2x00lib_conf
*libconf
)
2603 rt2800_register_read(rt2x00dev
, TX_RTY_CFG
, ®
);
2604 rt2x00_set_field32(®
, TX_RTY_CFG_SHORT_RTY_LIMIT
,
2605 libconf
->conf
->short_frame_max_tx_count
);
2606 rt2x00_set_field32(®
, TX_RTY_CFG_LONG_RTY_LIMIT
,
2607 libconf
->conf
->long_frame_max_tx_count
);
2608 rt2800_register_write(rt2x00dev
, TX_RTY_CFG
, reg
);
2611 static void rt2800_config_ps(struct rt2x00_dev
*rt2x00dev
,
2612 struct rt2x00lib_conf
*libconf
)
2614 enum dev_state state
=
2615 (libconf
->conf
->flags
& IEEE80211_CONF_PS
) ?
2616 STATE_SLEEP
: STATE_AWAKE
;
2619 if (state
== STATE_SLEEP
) {
2620 rt2800_register_write(rt2x00dev
, AUTOWAKEUP_CFG
, 0);
2622 rt2800_register_read(rt2x00dev
, AUTOWAKEUP_CFG
, ®
);
2623 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_AUTO_LEAD_TIME
, 5);
2624 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE
,
2625 libconf
->conf
->listen_interval
- 1);
2626 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_AUTOWAKE
, 1);
2627 rt2800_register_write(rt2x00dev
, AUTOWAKEUP_CFG
, reg
);
2629 rt2x00dev
->ops
->lib
->set_device_state(rt2x00dev
, state
);
2631 rt2800_register_read(rt2x00dev
, AUTOWAKEUP_CFG
, ®
);
2632 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_AUTO_LEAD_TIME
, 0);
2633 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE
, 0);
2634 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_AUTOWAKE
, 0);
2635 rt2800_register_write(rt2x00dev
, AUTOWAKEUP_CFG
, reg
);
2637 rt2x00dev
->ops
->lib
->set_device_state(rt2x00dev
, state
);
2641 void rt2800_config(struct rt2x00_dev
*rt2x00dev
,
2642 struct rt2x00lib_conf
*libconf
,
2643 const unsigned int flags
)
2645 /* Always recalculate LNA gain before changing configuration */
2646 rt2800_config_lna_gain(rt2x00dev
, libconf
);
2648 if (flags
& IEEE80211_CONF_CHANGE_CHANNEL
) {
2649 rt2800_config_channel(rt2x00dev
, libconf
->conf
,
2650 &libconf
->rf
, &libconf
->channel
);
2651 rt2800_config_txpower(rt2x00dev
, libconf
->conf
->channel
->band
,
2652 libconf
->conf
->power_level
);
2654 if (flags
& IEEE80211_CONF_CHANGE_POWER
)
2655 rt2800_config_txpower(rt2x00dev
, libconf
->conf
->channel
->band
,
2656 libconf
->conf
->power_level
);
2657 if (flags
& IEEE80211_CONF_CHANGE_RETRY_LIMITS
)
2658 rt2800_config_retry_limit(rt2x00dev
, libconf
);
2659 if (flags
& IEEE80211_CONF_CHANGE_PS
)
2660 rt2800_config_ps(rt2x00dev
, libconf
);
2662 EXPORT_SYMBOL_GPL(rt2800_config
);
2667 void rt2800_link_stats(struct rt2x00_dev
*rt2x00dev
, struct link_qual
*qual
)
2672 * Update FCS error count from register.
2674 rt2800_register_read(rt2x00dev
, RX_STA_CNT0
, ®
);
2675 qual
->rx_failed
= rt2x00_get_field32(reg
, RX_STA_CNT0_CRC_ERR
);
2677 EXPORT_SYMBOL_GPL(rt2800_link_stats
);
2679 static u8
rt2800_get_default_vgc(struct rt2x00_dev
*rt2x00dev
)
2681 if (rt2x00dev
->curr_band
== IEEE80211_BAND_2GHZ
) {
2682 if (rt2x00_rt(rt2x00dev
, RT3070
) ||
2683 rt2x00_rt(rt2x00dev
, RT3071
) ||
2684 rt2x00_rt(rt2x00dev
, RT3090
) ||
2685 rt2x00_rt(rt2x00dev
, RT3390
) ||
2686 rt2x00_rt(rt2x00dev
, RT5390
) ||
2687 rt2x00_rt(rt2x00dev
, RT5392
))
2688 return 0x1c + (2 * rt2x00dev
->lna_gain
);
2690 return 0x2e + rt2x00dev
->lna_gain
;
2693 if (!test_bit(CONFIG_CHANNEL_HT40
, &rt2x00dev
->flags
))
2694 return 0x32 + (rt2x00dev
->lna_gain
* 5) / 3;
2696 return 0x3a + (rt2x00dev
->lna_gain
* 5) / 3;
2699 static inline void rt2800_set_vgc(struct rt2x00_dev
*rt2x00dev
,
2700 struct link_qual
*qual
, u8 vgc_level
)
2702 if (qual
->vgc_level
!= vgc_level
) {
2703 rt2800_bbp_write(rt2x00dev
, 66, vgc_level
);
2704 qual
->vgc_level
= vgc_level
;
2705 qual
->vgc_level_reg
= vgc_level
;
2709 void rt2800_reset_tuner(struct rt2x00_dev
*rt2x00dev
, struct link_qual
*qual
)
2711 rt2800_set_vgc(rt2x00dev
, qual
, rt2800_get_default_vgc(rt2x00dev
));
2713 EXPORT_SYMBOL_GPL(rt2800_reset_tuner
);
2715 void rt2800_link_tuner(struct rt2x00_dev
*rt2x00dev
, struct link_qual
*qual
,
2718 if (rt2x00_rt_rev(rt2x00dev
, RT2860
, REV_RT2860C
))
2722 * When RSSI is better then -80 increase VGC level with 0x10
2724 rt2800_set_vgc(rt2x00dev
, qual
,
2725 rt2800_get_default_vgc(rt2x00dev
) +
2726 ((qual
->rssi
> -80) * 0x10));
2728 EXPORT_SYMBOL_GPL(rt2800_link_tuner
);
2731 * Initialization functions.
2733 static int rt2800_init_registers(struct rt2x00_dev
*rt2x00dev
)
2740 rt2800_disable_wpdma(rt2x00dev
);
2742 ret
= rt2800_drv_init_registers(rt2x00dev
);
2746 rt2800_register_read(rt2x00dev
, BCN_OFFSET0
, ®
);
2747 rt2x00_set_field32(®
, BCN_OFFSET0_BCN0
, 0xe0); /* 0x3800 */
2748 rt2x00_set_field32(®
, BCN_OFFSET0_BCN1
, 0xe8); /* 0x3a00 */
2749 rt2x00_set_field32(®
, BCN_OFFSET0_BCN2
, 0xf0); /* 0x3c00 */
2750 rt2x00_set_field32(®
, BCN_OFFSET0_BCN3
, 0xf8); /* 0x3e00 */
2751 rt2800_register_write(rt2x00dev
, BCN_OFFSET0
, reg
);
2753 rt2800_register_read(rt2x00dev
, BCN_OFFSET1
, ®
);
2754 rt2x00_set_field32(®
, BCN_OFFSET1_BCN4
, 0xc8); /* 0x3200 */
2755 rt2x00_set_field32(®
, BCN_OFFSET1_BCN5
, 0xd0); /* 0x3400 */
2756 rt2x00_set_field32(®
, BCN_OFFSET1_BCN6
, 0x77); /* 0x1dc0 */
2757 rt2x00_set_field32(®
, BCN_OFFSET1_BCN7
, 0x6f); /* 0x1bc0 */
2758 rt2800_register_write(rt2x00dev
, BCN_OFFSET1
, reg
);
2760 rt2800_register_write(rt2x00dev
, LEGACY_BASIC_RATE
, 0x0000013f);
2761 rt2800_register_write(rt2x00dev
, HT_BASIC_RATE
, 0x00008003);
2763 rt2800_register_write(rt2x00dev
, MAC_SYS_CTRL
, 0x00000000);
2765 rt2800_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
2766 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_INTERVAL
, 1600);
2767 rt2x00_set_field32(®
, BCN_TIME_CFG_TSF_TICKING
, 0);
2768 rt2x00_set_field32(®
, BCN_TIME_CFG_TSF_SYNC
, 0);
2769 rt2x00_set_field32(®
, BCN_TIME_CFG_TBTT_ENABLE
, 0);
2770 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_GEN
, 0);
2771 rt2x00_set_field32(®
, BCN_TIME_CFG_TX_TIME_COMPENSATE
, 0);
2772 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
2774 rt2800_config_filter(rt2x00dev
, FIF_ALLMULTI
);
2776 rt2800_register_read(rt2x00dev
, BKOFF_SLOT_CFG
, ®
);
2777 rt2x00_set_field32(®
, BKOFF_SLOT_CFG_SLOT_TIME
, 9);
2778 rt2x00_set_field32(®
, BKOFF_SLOT_CFG_CC_DELAY_TIME
, 2);
2779 rt2800_register_write(rt2x00dev
, BKOFF_SLOT_CFG
, reg
);
2781 if (rt2x00_rt(rt2x00dev
, RT3071
) ||
2782 rt2x00_rt(rt2x00dev
, RT3090
) ||
2783 rt2x00_rt(rt2x00dev
, RT3390
)) {
2784 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000400);
2785 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00000000);
2786 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3071
, REV_RT3071E
) ||
2787 rt2x00_rt_rev_lt(rt2x00dev
, RT3090
, REV_RT3090E
) ||
2788 rt2x00_rt_rev_lt(rt2x00dev
, RT3390
, REV_RT3390E
)) {
2789 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF1
, &eeprom
);
2790 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF1_DAC_TEST
))
2791 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
,
2794 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
,
2797 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
, 0x00000000);
2799 } else if (rt2x00_rt(rt2x00dev
, RT3070
)) {
2800 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000400);
2802 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070F
)) {
2803 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00000000);
2804 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
, 0x0000002c);
2806 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00080606);
2807 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
, 0x00000000);
2809 } else if (rt2800_is_305x_soc(rt2x00dev
)) {
2810 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000400);
2811 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00000000);
2812 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
, 0x00000030);
2813 } else if (rt2x00_rt(rt2x00dev
, RT3572
)) {
2814 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000400);
2815 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00080606);
2816 } else if (rt2x00_rt(rt2x00dev
, RT5390
) ||
2817 rt2x00_rt(rt2x00dev
, RT5392
)) {
2818 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000404);
2819 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00080606);
2820 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
, 0x00000000);
2822 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000000);
2823 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00080606);
2826 rt2800_register_read(rt2x00dev
, TX_LINK_CFG
, ®
);
2827 rt2x00_set_field32(®
, TX_LINK_CFG_REMOTE_MFB_LIFETIME
, 32);
2828 rt2x00_set_field32(®
, TX_LINK_CFG_MFB_ENABLE
, 0);
2829 rt2x00_set_field32(®
, TX_LINK_CFG_REMOTE_UMFS_ENABLE
, 0);
2830 rt2x00_set_field32(®
, TX_LINK_CFG_TX_MRQ_EN
, 0);
2831 rt2x00_set_field32(®
, TX_LINK_CFG_TX_RDG_EN
, 0);
2832 rt2x00_set_field32(®
, TX_LINK_CFG_TX_CF_ACK_EN
, 1);
2833 rt2x00_set_field32(®
, TX_LINK_CFG_REMOTE_MFB
, 0);
2834 rt2x00_set_field32(®
, TX_LINK_CFG_REMOTE_MFS
, 0);
2835 rt2800_register_write(rt2x00dev
, TX_LINK_CFG
, reg
);
2837 rt2800_register_read(rt2x00dev
, TX_TIMEOUT_CFG
, ®
);
2838 rt2x00_set_field32(®
, TX_TIMEOUT_CFG_MPDU_LIFETIME
, 9);
2839 rt2x00_set_field32(®
, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT
, 32);
2840 rt2x00_set_field32(®
, TX_TIMEOUT_CFG_TX_OP_TIMEOUT
, 10);
2841 rt2800_register_write(rt2x00dev
, TX_TIMEOUT_CFG
, reg
);
2843 rt2800_register_read(rt2x00dev
, MAX_LEN_CFG
, ®
);
2844 rt2x00_set_field32(®
, MAX_LEN_CFG_MAX_MPDU
, AGGREGATION_SIZE
);
2845 if (rt2x00_rt_rev_gte(rt2x00dev
, RT2872
, REV_RT2872E
) ||
2846 rt2x00_rt(rt2x00dev
, RT2883
) ||
2847 rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070E
))
2848 rt2x00_set_field32(®
, MAX_LEN_CFG_MAX_PSDU
, 2);
2850 rt2x00_set_field32(®
, MAX_LEN_CFG_MAX_PSDU
, 1);
2851 rt2x00_set_field32(®
, MAX_LEN_CFG_MIN_PSDU
, 0);
2852 rt2x00_set_field32(®
, MAX_LEN_CFG_MIN_MPDU
, 0);
2853 rt2800_register_write(rt2x00dev
, MAX_LEN_CFG
, reg
);
2855 rt2800_register_read(rt2x00dev
, LED_CFG
, ®
);
2856 rt2x00_set_field32(®
, LED_CFG_ON_PERIOD
, 70);
2857 rt2x00_set_field32(®
, LED_CFG_OFF_PERIOD
, 30);
2858 rt2x00_set_field32(®
, LED_CFG_SLOW_BLINK_PERIOD
, 3);
2859 rt2x00_set_field32(®
, LED_CFG_R_LED_MODE
, 3);
2860 rt2x00_set_field32(®
, LED_CFG_G_LED_MODE
, 3);
2861 rt2x00_set_field32(®
, LED_CFG_Y_LED_MODE
, 3);
2862 rt2x00_set_field32(®
, LED_CFG_LED_POLAR
, 1);
2863 rt2800_register_write(rt2x00dev
, LED_CFG
, reg
);
2865 rt2800_register_write(rt2x00dev
, PBF_MAX_PCNT
, 0x1f3fbf9f);
2867 rt2800_register_read(rt2x00dev
, TX_RTY_CFG
, ®
);
2868 rt2x00_set_field32(®
, TX_RTY_CFG_SHORT_RTY_LIMIT
, 15);
2869 rt2x00_set_field32(®
, TX_RTY_CFG_LONG_RTY_LIMIT
, 31);
2870 rt2x00_set_field32(®
, TX_RTY_CFG_LONG_RTY_THRE
, 2000);
2871 rt2x00_set_field32(®
, TX_RTY_CFG_NON_AGG_RTY_MODE
, 0);
2872 rt2x00_set_field32(®
, TX_RTY_CFG_AGG_RTY_MODE
, 0);
2873 rt2x00_set_field32(®
, TX_RTY_CFG_TX_AUTO_FB_ENABLE
, 1);
2874 rt2800_register_write(rt2x00dev
, TX_RTY_CFG
, reg
);
2876 rt2800_register_read(rt2x00dev
, AUTO_RSP_CFG
, ®
);
2877 rt2x00_set_field32(®
, AUTO_RSP_CFG_AUTORESPONDER
, 1);
2878 rt2x00_set_field32(®
, AUTO_RSP_CFG_BAC_ACK_POLICY
, 1);
2879 rt2x00_set_field32(®
, AUTO_RSP_CFG_CTS_40_MMODE
, 0);
2880 rt2x00_set_field32(®
, AUTO_RSP_CFG_CTS_40_MREF
, 0);
2881 rt2x00_set_field32(®
, AUTO_RSP_CFG_AR_PREAMBLE
, 1);
2882 rt2x00_set_field32(®
, AUTO_RSP_CFG_DUAL_CTS_EN
, 0);
2883 rt2x00_set_field32(®
, AUTO_RSP_CFG_ACK_CTS_PSM_BIT
, 0);
2884 rt2800_register_write(rt2x00dev
, AUTO_RSP_CFG
, reg
);
2886 rt2800_register_read(rt2x00dev
, CCK_PROT_CFG
, ®
);
2887 rt2x00_set_field32(®
, CCK_PROT_CFG_PROTECT_RATE
, 3);
2888 rt2x00_set_field32(®
, CCK_PROT_CFG_PROTECT_CTRL
, 0);
2889 rt2x00_set_field32(®
, CCK_PROT_CFG_PROTECT_NAV_SHORT
, 1);
2890 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
2891 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
2892 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
2893 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_MM40
, 0);
2894 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
2895 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_GF40
, 0);
2896 rt2x00_set_field32(®
, CCK_PROT_CFG_RTS_TH_EN
, 1);
2897 rt2800_register_write(rt2x00dev
, CCK_PROT_CFG
, reg
);
2899 rt2800_register_read(rt2x00dev
, OFDM_PROT_CFG
, ®
);
2900 rt2x00_set_field32(®
, OFDM_PROT_CFG_PROTECT_RATE
, 3);
2901 rt2x00_set_field32(®
, OFDM_PROT_CFG_PROTECT_CTRL
, 0);
2902 rt2x00_set_field32(®
, OFDM_PROT_CFG_PROTECT_NAV_SHORT
, 1);
2903 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
2904 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
2905 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
2906 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_MM40
, 0);
2907 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
2908 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_GF40
, 0);
2909 rt2x00_set_field32(®
, OFDM_PROT_CFG_RTS_TH_EN
, 1);
2910 rt2800_register_write(rt2x00dev
, OFDM_PROT_CFG
, reg
);
2912 rt2800_register_read(rt2x00dev
, MM20_PROT_CFG
, ®
);
2913 rt2x00_set_field32(®
, MM20_PROT_CFG_PROTECT_RATE
, 0x4004);
2914 rt2x00_set_field32(®
, MM20_PROT_CFG_PROTECT_CTRL
, 0);
2915 rt2x00_set_field32(®
, MM20_PROT_CFG_PROTECT_NAV_SHORT
, 1);
2916 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
2917 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
2918 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
2919 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_MM40
, 0);
2920 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
2921 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_GF40
, 0);
2922 rt2x00_set_field32(®
, MM20_PROT_CFG_RTS_TH_EN
, 0);
2923 rt2800_register_write(rt2x00dev
, MM20_PROT_CFG
, reg
);
2925 rt2800_register_read(rt2x00dev
, MM40_PROT_CFG
, ®
);
2926 rt2x00_set_field32(®
, MM40_PROT_CFG_PROTECT_RATE
, 0x4084);
2927 rt2x00_set_field32(®
, MM40_PROT_CFG_PROTECT_CTRL
, 0);
2928 rt2x00_set_field32(®
, MM40_PROT_CFG_PROTECT_NAV_SHORT
, 1);
2929 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
2930 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
2931 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
2932 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_MM40
, 1);
2933 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
2934 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_GF40
, 1);
2935 rt2x00_set_field32(®
, MM40_PROT_CFG_RTS_TH_EN
, 0);
2936 rt2800_register_write(rt2x00dev
, MM40_PROT_CFG
, reg
);
2938 rt2800_register_read(rt2x00dev
, GF20_PROT_CFG
, ®
);
2939 rt2x00_set_field32(®
, GF20_PROT_CFG_PROTECT_RATE
, 0x4004);
2940 rt2x00_set_field32(®
, GF20_PROT_CFG_PROTECT_CTRL
, 0);
2941 rt2x00_set_field32(®
, GF20_PROT_CFG_PROTECT_NAV_SHORT
, 1);
2942 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
2943 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
2944 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
2945 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_MM40
, 0);
2946 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
2947 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_GF40
, 0);
2948 rt2x00_set_field32(®
, GF20_PROT_CFG_RTS_TH_EN
, 0);
2949 rt2800_register_write(rt2x00dev
, GF20_PROT_CFG
, reg
);
2951 rt2800_register_read(rt2x00dev
, GF40_PROT_CFG
, ®
);
2952 rt2x00_set_field32(®
, GF40_PROT_CFG_PROTECT_RATE
, 0x4084);
2953 rt2x00_set_field32(®
, GF40_PROT_CFG_PROTECT_CTRL
, 0);
2954 rt2x00_set_field32(®
, GF40_PROT_CFG_PROTECT_NAV_SHORT
, 1);
2955 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
2956 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
2957 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
2958 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_MM40
, 1);
2959 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
2960 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_GF40
, 1);
2961 rt2x00_set_field32(®
, GF40_PROT_CFG_RTS_TH_EN
, 0);
2962 rt2800_register_write(rt2x00dev
, GF40_PROT_CFG
, reg
);
2964 if (rt2x00_is_usb(rt2x00dev
)) {
2965 rt2800_register_write(rt2x00dev
, PBF_CFG
, 0xf40006);
2967 rt2800_register_read(rt2x00dev
, WPDMA_GLO_CFG
, ®
);
2968 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_TX_DMA
, 0);
2969 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_DMA_BUSY
, 0);
2970 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_RX_DMA
, 0);
2971 rt2x00_set_field32(®
, WPDMA_GLO_CFG_RX_DMA_BUSY
, 0);
2972 rt2x00_set_field32(®
, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE
, 3);
2973 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_WRITEBACK_DONE
, 0);
2974 rt2x00_set_field32(®
, WPDMA_GLO_CFG_BIG_ENDIAN
, 0);
2975 rt2x00_set_field32(®
, WPDMA_GLO_CFG_RX_HDR_SCATTER
, 0);
2976 rt2x00_set_field32(®
, WPDMA_GLO_CFG_HDR_SEG_LEN
, 0);
2977 rt2800_register_write(rt2x00dev
, WPDMA_GLO_CFG
, reg
);
2981 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
2982 * although it is reserved.
2984 rt2800_register_read(rt2x00dev
, TXOP_CTRL_CFG
, ®
);
2985 rt2x00_set_field32(®
, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN
, 1);
2986 rt2x00_set_field32(®
, TXOP_CTRL_CFG_AC_TRUN_EN
, 1);
2987 rt2x00_set_field32(®
, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN
, 1);
2988 rt2x00_set_field32(®
, TXOP_CTRL_CFG_USER_MODE_TRUN_EN
, 1);
2989 rt2x00_set_field32(®
, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN
, 1);
2990 rt2x00_set_field32(®
, TXOP_CTRL_CFG_RESERVED_TRUN_EN
, 1);
2991 rt2x00_set_field32(®
, TXOP_CTRL_CFG_LSIG_TXOP_EN
, 0);
2992 rt2x00_set_field32(®
, TXOP_CTRL_CFG_EXT_CCA_EN
, 0);
2993 rt2x00_set_field32(®
, TXOP_CTRL_CFG_EXT_CCA_DLY
, 88);
2994 rt2x00_set_field32(®
, TXOP_CTRL_CFG_EXT_CWMIN
, 0);
2995 rt2800_register_write(rt2x00dev
, TXOP_CTRL_CFG
, reg
);
2997 rt2800_register_write(rt2x00dev
, TXOP_HLDR_ET
, 0x00000002);
2999 rt2800_register_read(rt2x00dev
, TX_RTS_CFG
, ®
);
3000 rt2x00_set_field32(®
, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT
, 32);
3001 rt2x00_set_field32(®
, TX_RTS_CFG_RTS_THRES
,
3002 IEEE80211_MAX_RTS_THRESHOLD
);
3003 rt2x00_set_field32(®
, TX_RTS_CFG_RTS_FBK_EN
, 0);
3004 rt2800_register_write(rt2x00dev
, TX_RTS_CFG
, reg
);
3006 rt2800_register_write(rt2x00dev
, EXP_ACK_TIME
, 0x002400ca);
3009 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
3010 * time should be set to 16. However, the original Ralink driver uses
3011 * 16 for both and indeed using a value of 10 for CCK SIFS results in
3012 * connection problems with 11g + CTS protection. Hence, use the same
3013 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
3015 rt2800_register_read(rt2x00dev
, XIFS_TIME_CFG
, ®
);
3016 rt2x00_set_field32(®
, XIFS_TIME_CFG_CCKM_SIFS_TIME
, 16);
3017 rt2x00_set_field32(®
, XIFS_TIME_CFG_OFDM_SIFS_TIME
, 16);
3018 rt2x00_set_field32(®
, XIFS_TIME_CFG_OFDM_XIFS_TIME
, 4);
3019 rt2x00_set_field32(®
, XIFS_TIME_CFG_EIFS
, 314);
3020 rt2x00_set_field32(®
, XIFS_TIME_CFG_BB_RXEND_ENABLE
, 1);
3021 rt2800_register_write(rt2x00dev
, XIFS_TIME_CFG
, reg
);
3023 rt2800_register_write(rt2x00dev
, PWR_PIN_CFG
, 0x00000003);
3026 * ASIC will keep garbage value after boot, clear encryption keys.
3028 for (i
= 0; i
< 4; i
++)
3029 rt2800_register_write(rt2x00dev
,
3030 SHARED_KEY_MODE_ENTRY(i
), 0);
3032 for (i
= 0; i
< 256; i
++) {
3033 rt2800_config_wcid(rt2x00dev
, NULL
, i
);
3034 rt2800_delete_wcid_attr(rt2x00dev
, i
);
3035 rt2800_register_write(rt2x00dev
, MAC_IVEIV_ENTRY(i
), 0);
3041 rt2800_clear_beacon_register(rt2x00dev
, HW_BEACON_BASE0
);
3042 rt2800_clear_beacon_register(rt2x00dev
, HW_BEACON_BASE1
);
3043 rt2800_clear_beacon_register(rt2x00dev
, HW_BEACON_BASE2
);
3044 rt2800_clear_beacon_register(rt2x00dev
, HW_BEACON_BASE3
);
3045 rt2800_clear_beacon_register(rt2x00dev
, HW_BEACON_BASE4
);
3046 rt2800_clear_beacon_register(rt2x00dev
, HW_BEACON_BASE5
);
3047 rt2800_clear_beacon_register(rt2x00dev
, HW_BEACON_BASE6
);
3048 rt2800_clear_beacon_register(rt2x00dev
, HW_BEACON_BASE7
);
3050 if (rt2x00_is_usb(rt2x00dev
)) {
3051 rt2800_register_read(rt2x00dev
, US_CYC_CNT
, ®
);
3052 rt2x00_set_field32(®
, US_CYC_CNT_CLOCK_CYCLE
, 30);
3053 rt2800_register_write(rt2x00dev
, US_CYC_CNT
, reg
);
3054 } else if (rt2x00_is_pcie(rt2x00dev
)) {
3055 rt2800_register_read(rt2x00dev
, US_CYC_CNT
, ®
);
3056 rt2x00_set_field32(®
, US_CYC_CNT_CLOCK_CYCLE
, 125);
3057 rt2800_register_write(rt2x00dev
, US_CYC_CNT
, reg
);
3060 rt2800_register_read(rt2x00dev
, HT_FBK_CFG0
, ®
);
3061 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS0FBK
, 0);
3062 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS1FBK
, 0);
3063 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS2FBK
, 1);
3064 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS3FBK
, 2);
3065 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS4FBK
, 3);
3066 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS5FBK
, 4);
3067 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS6FBK
, 5);
3068 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS7FBK
, 6);
3069 rt2800_register_write(rt2x00dev
, HT_FBK_CFG0
, reg
);
3071 rt2800_register_read(rt2x00dev
, HT_FBK_CFG1
, ®
);
3072 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS8FBK
, 8);
3073 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS9FBK
, 8);
3074 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS10FBK
, 9);
3075 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS11FBK
, 10);
3076 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS12FBK
, 11);
3077 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS13FBK
, 12);
3078 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS14FBK
, 13);
3079 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS15FBK
, 14);
3080 rt2800_register_write(rt2x00dev
, HT_FBK_CFG1
, reg
);
3082 rt2800_register_read(rt2x00dev
, LG_FBK_CFG0
, ®
);
3083 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS0FBK
, 8);
3084 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS1FBK
, 8);
3085 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS2FBK
, 9);
3086 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS3FBK
, 10);
3087 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS4FBK
, 11);
3088 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS5FBK
, 12);
3089 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS6FBK
, 13);
3090 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS7FBK
, 14);
3091 rt2800_register_write(rt2x00dev
, LG_FBK_CFG0
, reg
);
3093 rt2800_register_read(rt2x00dev
, LG_FBK_CFG1
, ®
);
3094 rt2x00_set_field32(®
, LG_FBK_CFG0_CCKMCS0FBK
, 0);
3095 rt2x00_set_field32(®
, LG_FBK_CFG0_CCKMCS1FBK
, 0);
3096 rt2x00_set_field32(®
, LG_FBK_CFG0_CCKMCS2FBK
, 1);
3097 rt2x00_set_field32(®
, LG_FBK_CFG0_CCKMCS3FBK
, 2);
3098 rt2800_register_write(rt2x00dev
, LG_FBK_CFG1
, reg
);
3101 * Do not force the BA window size, we use the TXWI to set it
3103 rt2800_register_read(rt2x00dev
, AMPDU_BA_WINSIZE
, ®
);
3104 rt2x00_set_field32(®
, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE
, 0);
3105 rt2x00_set_field32(®
, AMPDU_BA_WINSIZE_FORCE_WINSIZE
, 0);
3106 rt2800_register_write(rt2x00dev
, AMPDU_BA_WINSIZE
, reg
);
3109 * We must clear the error counters.
3110 * These registers are cleared on read,
3111 * so we may pass a useless variable to store the value.
3113 rt2800_register_read(rt2x00dev
, RX_STA_CNT0
, ®
);
3114 rt2800_register_read(rt2x00dev
, RX_STA_CNT1
, ®
);
3115 rt2800_register_read(rt2x00dev
, RX_STA_CNT2
, ®
);
3116 rt2800_register_read(rt2x00dev
, TX_STA_CNT0
, ®
);
3117 rt2800_register_read(rt2x00dev
, TX_STA_CNT1
, ®
);
3118 rt2800_register_read(rt2x00dev
, TX_STA_CNT2
, ®
);
3121 * Setup leadtime for pre tbtt interrupt to 6ms
3123 rt2800_register_read(rt2x00dev
, INT_TIMER_CFG
, ®
);
3124 rt2x00_set_field32(®
, INT_TIMER_CFG_PRE_TBTT_TIMER
, 6 << 4);
3125 rt2800_register_write(rt2x00dev
, INT_TIMER_CFG
, reg
);
3128 * Set up channel statistics timer
3130 rt2800_register_read(rt2x00dev
, CH_TIME_CFG
, ®
);
3131 rt2x00_set_field32(®
, CH_TIME_CFG_EIFS_BUSY
, 1);
3132 rt2x00_set_field32(®
, CH_TIME_CFG_NAV_BUSY
, 1);
3133 rt2x00_set_field32(®
, CH_TIME_CFG_RX_BUSY
, 1);
3134 rt2x00_set_field32(®
, CH_TIME_CFG_TX_BUSY
, 1);
3135 rt2x00_set_field32(®
, CH_TIME_CFG_TMR_EN
, 1);
3136 rt2800_register_write(rt2x00dev
, CH_TIME_CFG
, reg
);
3141 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev
*rt2x00dev
)
3146 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
3147 rt2800_register_read(rt2x00dev
, MAC_STATUS_CFG
, ®
);
3148 if (!rt2x00_get_field32(reg
, MAC_STATUS_CFG_BBP_RF_BUSY
))
3151 udelay(REGISTER_BUSY_DELAY
);
3154 ERROR(rt2x00dev
, "BBP/RF register access failed, aborting.\n");
3158 static int rt2800_wait_bbp_ready(struct rt2x00_dev
*rt2x00dev
)
3164 * BBP was enabled after firmware was loaded,
3165 * but we need to reactivate it now.
3167 rt2800_register_write(rt2x00dev
, H2M_BBP_AGENT
, 0);
3168 rt2800_register_write(rt2x00dev
, H2M_MAILBOX_CSR
, 0);
3171 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
3172 rt2800_bbp_read(rt2x00dev
, 0, &value
);
3173 if ((value
!= 0xff) && (value
!= 0x00))
3175 udelay(REGISTER_BUSY_DELAY
);
3178 ERROR(rt2x00dev
, "BBP register access failed, aborting.\n");
3182 static int rt2800_init_bbp(struct rt2x00_dev
*rt2x00dev
)
3189 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev
) ||
3190 rt2800_wait_bbp_ready(rt2x00dev
)))
3193 if (rt2x00_rt(rt2x00dev
, RT5390
) ||
3194 rt2x00_rt(rt2x00dev
, RT5392
)) {
3195 rt2800_bbp_read(rt2x00dev
, 4, &value
);
3196 rt2x00_set_field8(&value
, BBP4_MAC_IF_CTRL
, 1);
3197 rt2800_bbp_write(rt2x00dev
, 4, value
);
3200 if (rt2800_is_305x_soc(rt2x00dev
) ||
3201 rt2x00_rt(rt2x00dev
, RT3572
) ||
3202 rt2x00_rt(rt2x00dev
, RT5390
) ||
3203 rt2x00_rt(rt2x00dev
, RT5392
))
3204 rt2800_bbp_write(rt2x00dev
, 31, 0x08);
3206 rt2800_bbp_write(rt2x00dev
, 65, 0x2c);
3207 rt2800_bbp_write(rt2x00dev
, 66, 0x38);
3209 if (rt2x00_rt(rt2x00dev
, RT5390
) ||
3210 rt2x00_rt(rt2x00dev
, RT5392
))
3211 rt2800_bbp_write(rt2x00dev
, 68, 0x0b);
3213 if (rt2x00_rt_rev(rt2x00dev
, RT2860
, REV_RT2860C
)) {
3214 rt2800_bbp_write(rt2x00dev
, 69, 0x16);
3215 rt2800_bbp_write(rt2x00dev
, 73, 0x12);
3216 } else if (rt2x00_rt(rt2x00dev
, RT5390
) ||
3217 rt2x00_rt(rt2x00dev
, RT5392
)) {
3218 rt2800_bbp_write(rt2x00dev
, 69, 0x12);
3219 rt2800_bbp_write(rt2x00dev
, 73, 0x13);
3220 rt2800_bbp_write(rt2x00dev
, 75, 0x46);
3221 rt2800_bbp_write(rt2x00dev
, 76, 0x28);
3222 rt2800_bbp_write(rt2x00dev
, 77, 0x59);
3224 rt2800_bbp_write(rt2x00dev
, 69, 0x12);
3225 rt2800_bbp_write(rt2x00dev
, 73, 0x10);
3228 rt2800_bbp_write(rt2x00dev
, 70, 0x0a);
3230 if (rt2x00_rt(rt2x00dev
, RT3070
) ||
3231 rt2x00_rt(rt2x00dev
, RT3071
) ||
3232 rt2x00_rt(rt2x00dev
, RT3090
) ||
3233 rt2x00_rt(rt2x00dev
, RT3390
) ||
3234 rt2x00_rt(rt2x00dev
, RT3572
) ||
3235 rt2x00_rt(rt2x00dev
, RT5390
) ||
3236 rt2x00_rt(rt2x00dev
, RT5392
)) {
3237 rt2800_bbp_write(rt2x00dev
, 79, 0x13);
3238 rt2800_bbp_write(rt2x00dev
, 80, 0x05);
3239 rt2800_bbp_write(rt2x00dev
, 81, 0x33);
3240 } else if (rt2800_is_305x_soc(rt2x00dev
)) {
3241 rt2800_bbp_write(rt2x00dev
, 78, 0x0e);
3242 rt2800_bbp_write(rt2x00dev
, 80, 0x08);
3244 rt2800_bbp_write(rt2x00dev
, 81, 0x37);
3247 rt2800_bbp_write(rt2x00dev
, 82, 0x62);
3248 if (rt2x00_rt(rt2x00dev
, RT5390
) ||
3249 rt2x00_rt(rt2x00dev
, RT5392
))
3250 rt2800_bbp_write(rt2x00dev
, 83, 0x7a);
3252 rt2800_bbp_write(rt2x00dev
, 83, 0x6a);
3254 if (rt2x00_rt_rev(rt2x00dev
, RT2860
, REV_RT2860D
))
3255 rt2800_bbp_write(rt2x00dev
, 84, 0x19);
3256 else if (rt2x00_rt(rt2x00dev
, RT5390
) ||
3257 rt2x00_rt(rt2x00dev
, RT5392
))
3258 rt2800_bbp_write(rt2x00dev
, 84, 0x9a);
3260 rt2800_bbp_write(rt2x00dev
, 84, 0x99);
3262 if (rt2x00_rt(rt2x00dev
, RT5390
) ||
3263 rt2x00_rt(rt2x00dev
, RT5392
))
3264 rt2800_bbp_write(rt2x00dev
, 86, 0x38);
3266 rt2800_bbp_write(rt2x00dev
, 86, 0x00);
3268 if (rt2x00_rt(rt2x00dev
, RT5392
))
3269 rt2800_bbp_write(rt2x00dev
, 88, 0x90);
3271 rt2800_bbp_write(rt2x00dev
, 91, 0x04);
3273 if (rt2x00_rt(rt2x00dev
, RT5390
) ||
3274 rt2x00_rt(rt2x00dev
, RT5392
))
3275 rt2800_bbp_write(rt2x00dev
, 92, 0x02);
3277 rt2800_bbp_write(rt2x00dev
, 92, 0x00);
3279 if (rt2x00_rt(rt2x00dev
, RT5392
)) {
3280 rt2800_bbp_write(rt2x00dev
, 95, 0x9a);
3281 rt2800_bbp_write(rt2x00dev
, 98, 0x12);
3284 if (rt2x00_rt_rev_gte(rt2x00dev
, RT3070
, REV_RT3070F
) ||
3285 rt2x00_rt_rev_gte(rt2x00dev
, RT3071
, REV_RT3071E
) ||
3286 rt2x00_rt_rev_gte(rt2x00dev
, RT3090
, REV_RT3090E
) ||
3287 rt2x00_rt_rev_gte(rt2x00dev
, RT3390
, REV_RT3390E
) ||
3288 rt2x00_rt(rt2x00dev
, RT3572
) ||
3289 rt2x00_rt(rt2x00dev
, RT5390
) ||
3290 rt2x00_rt(rt2x00dev
, RT5392
) ||
3291 rt2800_is_305x_soc(rt2x00dev
))
3292 rt2800_bbp_write(rt2x00dev
, 103, 0xc0);
3294 rt2800_bbp_write(rt2x00dev
, 103, 0x00);
3296 if (rt2x00_rt(rt2x00dev
, RT5390
) ||
3297 rt2x00_rt(rt2x00dev
, RT5392
))
3298 rt2800_bbp_write(rt2x00dev
, 104, 0x92);
3300 if (rt2800_is_305x_soc(rt2x00dev
))
3301 rt2800_bbp_write(rt2x00dev
, 105, 0x01);
3302 else if (rt2x00_rt(rt2x00dev
, RT5390
) ||
3303 rt2x00_rt(rt2x00dev
, RT5392
))
3304 rt2800_bbp_write(rt2x00dev
, 105, 0x3c);
3306 rt2800_bbp_write(rt2x00dev
, 105, 0x05);
3308 if (rt2x00_rt(rt2x00dev
, RT5390
))
3309 rt2800_bbp_write(rt2x00dev
, 106, 0x03);
3310 else if (rt2x00_rt(rt2x00dev
, RT5392
))
3311 rt2800_bbp_write(rt2x00dev
, 106, 0x12);
3313 rt2800_bbp_write(rt2x00dev
, 106, 0x35);
3315 if (rt2x00_rt(rt2x00dev
, RT5390
) ||
3316 rt2x00_rt(rt2x00dev
, RT5392
))
3317 rt2800_bbp_write(rt2x00dev
, 128, 0x12);
3319 if (rt2x00_rt(rt2x00dev
, RT5392
)) {
3320 rt2800_bbp_write(rt2x00dev
, 134, 0xd0);
3321 rt2800_bbp_write(rt2x00dev
, 135, 0xf6);
3324 if (rt2x00_rt(rt2x00dev
, RT3071
) ||
3325 rt2x00_rt(rt2x00dev
, RT3090
) ||
3326 rt2x00_rt(rt2x00dev
, RT3390
) ||
3327 rt2x00_rt(rt2x00dev
, RT3572
) ||
3328 rt2x00_rt(rt2x00dev
, RT5390
) ||
3329 rt2x00_rt(rt2x00dev
, RT5392
)) {
3330 rt2800_bbp_read(rt2x00dev
, 138, &value
);
3332 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF0
, &eeprom
);
3333 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_TXPATH
) == 1)
3335 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_RXPATH
) == 1)
3338 rt2800_bbp_write(rt2x00dev
, 138, value
);
3341 if (rt2x00_rt(rt2x00dev
, RT5390
) ||
3342 rt2x00_rt(rt2x00dev
, RT5392
)) {
3345 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF1
, &eeprom
);
3346 div_mode
= rt2x00_get_field16(eeprom
,
3347 EEPROM_NIC_CONF1_ANT_DIVERSITY
);
3348 ant
= (div_mode
== 3) ? 1 : 0;
3350 /* check if this is a Bluetooth combo card */
3351 if (test_bit(CAPABILITY_BT_COEXIST
, &rt2x00dev
->cap_flags
)) {
3354 rt2800_register_read(rt2x00dev
, GPIO_CTRL_CFG
, ®
);
3355 rt2x00_set_field32(®
, GPIO_CTRL_CFG_GPIOD_BIT3
, 0);
3356 rt2x00_set_field32(®
, GPIO_CTRL_CFG_GPIOD_BIT6
, 0);
3357 rt2x00_set_field32(®
, GPIO_CTRL_CFG_BIT3
, 0);
3358 rt2x00_set_field32(®
, GPIO_CTRL_CFG_BIT6
, 0);
3360 rt2x00_set_field32(®
, GPIO_CTRL_CFG_BIT3
, 1);
3362 rt2x00_set_field32(®
, GPIO_CTRL_CFG_BIT6
, 1);
3363 rt2800_register_write(rt2x00dev
, GPIO_CTRL_CFG
, reg
);
3366 /* This chip has hardware antenna diversity*/
3367 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390R
)) {
3368 rt2800_bbp_write(rt2x00dev
, 150, 0); /* Disable Antenna Software OFDM */
3369 rt2800_bbp_write(rt2x00dev
, 151, 0); /* Disable Antenna Software CCK */
3370 rt2800_bbp_write(rt2x00dev
, 154, 0); /* Clear previously selected antenna */
3373 rt2800_bbp_read(rt2x00dev
, 152, &value
);
3375 rt2x00_set_field8(&value
, BBP152_RX_DEFAULT_ANT
, 1);
3377 rt2x00_set_field8(&value
, BBP152_RX_DEFAULT_ANT
, 0);
3378 rt2800_bbp_write(rt2x00dev
, 152, value
);
3380 /* Init frequency calibration */
3381 rt2800_bbp_write(rt2x00dev
, 142, 1);
3382 rt2800_bbp_write(rt2x00dev
, 143, 57);
3385 for (i
= 0; i
< EEPROM_BBP_SIZE
; i
++) {
3386 rt2x00_eeprom_read(rt2x00dev
, EEPROM_BBP_START
+ i
, &eeprom
);
3388 if (eeprom
!= 0xffff && eeprom
!= 0x0000) {
3389 reg_id
= rt2x00_get_field16(eeprom
, EEPROM_BBP_REG_ID
);
3390 value
= rt2x00_get_field16(eeprom
, EEPROM_BBP_VALUE
);
3391 rt2800_bbp_write(rt2x00dev
, reg_id
, value
);
3398 static u8
rt2800_init_rx_filter(struct rt2x00_dev
*rt2x00dev
,
3399 bool bw40
, u8 rfcsr24
, u8 filter_target
)
3408 rt2800_rfcsr_write(rt2x00dev
, 24, rfcsr24
);
3410 rt2800_bbp_read(rt2x00dev
, 4, &bbp
);
3411 rt2x00_set_field8(&bbp
, BBP4_BANDWIDTH
, 2 * bw40
);
3412 rt2800_bbp_write(rt2x00dev
, 4, bbp
);
3414 rt2800_rfcsr_read(rt2x00dev
, 31, &rfcsr
);
3415 rt2x00_set_field8(&rfcsr
, RFCSR31_RX_H20M
, bw40
);
3416 rt2800_rfcsr_write(rt2x00dev
, 31, rfcsr
);
3418 rt2800_rfcsr_read(rt2x00dev
, 22, &rfcsr
);
3419 rt2x00_set_field8(&rfcsr
, RFCSR22_BASEBAND_LOOPBACK
, 1);
3420 rt2800_rfcsr_write(rt2x00dev
, 22, rfcsr
);
3423 * Set power & frequency of passband test tone
3425 rt2800_bbp_write(rt2x00dev
, 24, 0);
3427 for (i
= 0; i
< 100; i
++) {
3428 rt2800_bbp_write(rt2x00dev
, 25, 0x90);
3431 rt2800_bbp_read(rt2x00dev
, 55, &passband
);
3437 * Set power & frequency of stopband test tone
3439 rt2800_bbp_write(rt2x00dev
, 24, 0x06);
3441 for (i
= 0; i
< 100; i
++) {
3442 rt2800_bbp_write(rt2x00dev
, 25, 0x90);
3445 rt2800_bbp_read(rt2x00dev
, 55, &stopband
);
3447 if ((passband
- stopband
) <= filter_target
) {
3449 overtuned
+= ((passband
- stopband
) == filter_target
);
3453 rt2800_rfcsr_write(rt2x00dev
, 24, rfcsr24
);
3456 rfcsr24
-= !!overtuned
;
3458 rt2800_rfcsr_write(rt2x00dev
, 24, rfcsr24
);
3462 static int rt2800_init_rfcsr(struct rt2x00_dev
*rt2x00dev
)
3464 struct rt2800_drv_data
*drv_data
= rt2x00dev
->drv_data
;
3470 if (!rt2x00_rt(rt2x00dev
, RT3070
) &&
3471 !rt2x00_rt(rt2x00dev
, RT3071
) &&
3472 !rt2x00_rt(rt2x00dev
, RT3090
) &&
3473 !rt2x00_rt(rt2x00dev
, RT3390
) &&
3474 !rt2x00_rt(rt2x00dev
, RT3572
) &&
3475 !rt2x00_rt(rt2x00dev
, RT5390
) &&
3476 !rt2x00_rt(rt2x00dev
, RT5392
) &&
3477 !rt2800_is_305x_soc(rt2x00dev
))
3481 * Init RF calibration.
3483 if (rt2x00_rt(rt2x00dev
, RT5390
) ||
3484 rt2x00_rt(rt2x00dev
, RT5392
)) {
3485 rt2800_rfcsr_read(rt2x00dev
, 2, &rfcsr
);
3486 rt2x00_set_field8(&rfcsr
, RFCSR2_RESCAL_EN
, 1);
3487 rt2800_rfcsr_write(rt2x00dev
, 2, rfcsr
);
3489 rt2x00_set_field8(&rfcsr
, RFCSR2_RESCAL_EN
, 0);
3490 rt2800_rfcsr_write(rt2x00dev
, 2, rfcsr
);
3492 rt2800_rfcsr_read(rt2x00dev
, 30, &rfcsr
);
3493 rt2x00_set_field8(&rfcsr
, RFCSR30_RF_CALIBRATION
, 1);
3494 rt2800_rfcsr_write(rt2x00dev
, 30, rfcsr
);
3496 rt2x00_set_field8(&rfcsr
, RFCSR30_RF_CALIBRATION
, 0);
3497 rt2800_rfcsr_write(rt2x00dev
, 30, rfcsr
);
3500 if (rt2x00_rt(rt2x00dev
, RT3070
) ||
3501 rt2x00_rt(rt2x00dev
, RT3071
) ||
3502 rt2x00_rt(rt2x00dev
, RT3090
)) {
3503 rt2800_rfcsr_write(rt2x00dev
, 4, 0x40);
3504 rt2800_rfcsr_write(rt2x00dev
, 5, 0x03);
3505 rt2800_rfcsr_write(rt2x00dev
, 6, 0x02);
3506 rt2800_rfcsr_write(rt2x00dev
, 7, 0x60);
3507 rt2800_rfcsr_write(rt2x00dev
, 9, 0x0f);
3508 rt2800_rfcsr_write(rt2x00dev
, 10, 0x41);
3509 rt2800_rfcsr_write(rt2x00dev
, 11, 0x21);
3510 rt2800_rfcsr_write(rt2x00dev
, 12, 0x7b);
3511 rt2800_rfcsr_write(rt2x00dev
, 14, 0x90);
3512 rt2800_rfcsr_write(rt2x00dev
, 15, 0x58);
3513 rt2800_rfcsr_write(rt2x00dev
, 16, 0xb3);
3514 rt2800_rfcsr_write(rt2x00dev
, 17, 0x92);
3515 rt2800_rfcsr_write(rt2x00dev
, 18, 0x2c);
3516 rt2800_rfcsr_write(rt2x00dev
, 19, 0x02);
3517 rt2800_rfcsr_write(rt2x00dev
, 20, 0xba);
3518 rt2800_rfcsr_write(rt2x00dev
, 21, 0xdb);
3519 rt2800_rfcsr_write(rt2x00dev
, 24, 0x16);
3520 rt2800_rfcsr_write(rt2x00dev
, 25, 0x01);
3521 rt2800_rfcsr_write(rt2x00dev
, 29, 0x1f);
3522 } else if (rt2x00_rt(rt2x00dev
, RT3390
)) {
3523 rt2800_rfcsr_write(rt2x00dev
, 0, 0xa0);
3524 rt2800_rfcsr_write(rt2x00dev
, 1, 0xe1);
3525 rt2800_rfcsr_write(rt2x00dev
, 2, 0xf1);
3526 rt2800_rfcsr_write(rt2x00dev
, 3, 0x62);
3527 rt2800_rfcsr_write(rt2x00dev
, 4, 0x40);
3528 rt2800_rfcsr_write(rt2x00dev
, 5, 0x8b);
3529 rt2800_rfcsr_write(rt2x00dev
, 6, 0x42);
3530 rt2800_rfcsr_write(rt2x00dev
, 7, 0x34);
3531 rt2800_rfcsr_write(rt2x00dev
, 8, 0x00);
3532 rt2800_rfcsr_write(rt2x00dev
, 9, 0xc0);
3533 rt2800_rfcsr_write(rt2x00dev
, 10, 0x61);
3534 rt2800_rfcsr_write(rt2x00dev
, 11, 0x21);
3535 rt2800_rfcsr_write(rt2x00dev
, 12, 0x3b);
3536 rt2800_rfcsr_write(rt2x00dev
, 13, 0xe0);
3537 rt2800_rfcsr_write(rt2x00dev
, 14, 0x90);
3538 rt2800_rfcsr_write(rt2x00dev
, 15, 0x53);
3539 rt2800_rfcsr_write(rt2x00dev
, 16, 0xe0);
3540 rt2800_rfcsr_write(rt2x00dev
, 17, 0x94);
3541 rt2800_rfcsr_write(rt2x00dev
, 18, 0x5c);
3542 rt2800_rfcsr_write(rt2x00dev
, 19, 0x4a);
3543 rt2800_rfcsr_write(rt2x00dev
, 20, 0xb2);
3544 rt2800_rfcsr_write(rt2x00dev
, 21, 0xf6);
3545 rt2800_rfcsr_write(rt2x00dev
, 22, 0x00);
3546 rt2800_rfcsr_write(rt2x00dev
, 23, 0x14);
3547 rt2800_rfcsr_write(rt2x00dev
, 24, 0x08);
3548 rt2800_rfcsr_write(rt2x00dev
, 25, 0x3d);
3549 rt2800_rfcsr_write(rt2x00dev
, 26, 0x85);
3550 rt2800_rfcsr_write(rt2x00dev
, 27, 0x00);
3551 rt2800_rfcsr_write(rt2x00dev
, 28, 0x41);
3552 rt2800_rfcsr_write(rt2x00dev
, 29, 0x8f);
3553 rt2800_rfcsr_write(rt2x00dev
, 30, 0x20);
3554 rt2800_rfcsr_write(rt2x00dev
, 31, 0x0f);
3555 } else if (rt2x00_rt(rt2x00dev
, RT3572
)) {
3556 rt2800_rfcsr_write(rt2x00dev
, 0, 0x70);
3557 rt2800_rfcsr_write(rt2x00dev
, 1, 0x81);
3558 rt2800_rfcsr_write(rt2x00dev
, 2, 0xf1);
3559 rt2800_rfcsr_write(rt2x00dev
, 3, 0x02);
3560 rt2800_rfcsr_write(rt2x00dev
, 4, 0x4c);
3561 rt2800_rfcsr_write(rt2x00dev
, 5, 0x05);
3562 rt2800_rfcsr_write(rt2x00dev
, 6, 0x4a);
3563 rt2800_rfcsr_write(rt2x00dev
, 7, 0xd8);
3564 rt2800_rfcsr_write(rt2x00dev
, 9, 0xc3);
3565 rt2800_rfcsr_write(rt2x00dev
, 10, 0xf1);
3566 rt2800_rfcsr_write(rt2x00dev
, 11, 0xb9);
3567 rt2800_rfcsr_write(rt2x00dev
, 12, 0x70);
3568 rt2800_rfcsr_write(rt2x00dev
, 13, 0x65);
3569 rt2800_rfcsr_write(rt2x00dev
, 14, 0xa0);
3570 rt2800_rfcsr_write(rt2x00dev
, 15, 0x53);
3571 rt2800_rfcsr_write(rt2x00dev
, 16, 0x4c);
3572 rt2800_rfcsr_write(rt2x00dev
, 17, 0x23);
3573 rt2800_rfcsr_write(rt2x00dev
, 18, 0xac);
3574 rt2800_rfcsr_write(rt2x00dev
, 19, 0x93);
3575 rt2800_rfcsr_write(rt2x00dev
, 20, 0xb3);
3576 rt2800_rfcsr_write(rt2x00dev
, 21, 0xd0);
3577 rt2800_rfcsr_write(rt2x00dev
, 22, 0x00);
3578 rt2800_rfcsr_write(rt2x00dev
, 23, 0x3c);
3579 rt2800_rfcsr_write(rt2x00dev
, 24, 0x16);
3580 rt2800_rfcsr_write(rt2x00dev
, 25, 0x15);
3581 rt2800_rfcsr_write(rt2x00dev
, 26, 0x85);
3582 rt2800_rfcsr_write(rt2x00dev
, 27, 0x00);
3583 rt2800_rfcsr_write(rt2x00dev
, 28, 0x00);
3584 rt2800_rfcsr_write(rt2x00dev
, 29, 0x9b);
3585 rt2800_rfcsr_write(rt2x00dev
, 30, 0x09);
3586 rt2800_rfcsr_write(rt2x00dev
, 31, 0x10);
3587 } else if (rt2800_is_305x_soc(rt2x00dev
)) {
3588 rt2800_rfcsr_write(rt2x00dev
, 0, 0x50);
3589 rt2800_rfcsr_write(rt2x00dev
, 1, 0x01);
3590 rt2800_rfcsr_write(rt2x00dev
, 2, 0xf7);
3591 rt2800_rfcsr_write(rt2x00dev
, 3, 0x75);
3592 rt2800_rfcsr_write(rt2x00dev
, 4, 0x40);
3593 rt2800_rfcsr_write(rt2x00dev
, 5, 0x03);
3594 rt2800_rfcsr_write(rt2x00dev
, 6, 0x02);
3595 rt2800_rfcsr_write(rt2x00dev
, 7, 0x50);
3596 rt2800_rfcsr_write(rt2x00dev
, 8, 0x39);
3597 rt2800_rfcsr_write(rt2x00dev
, 9, 0x0f);
3598 rt2800_rfcsr_write(rt2x00dev
, 10, 0x60);
3599 rt2800_rfcsr_write(rt2x00dev
, 11, 0x21);
3600 rt2800_rfcsr_write(rt2x00dev
, 12, 0x75);
3601 rt2800_rfcsr_write(rt2x00dev
, 13, 0x75);
3602 rt2800_rfcsr_write(rt2x00dev
, 14, 0x90);
3603 rt2800_rfcsr_write(rt2x00dev
, 15, 0x58);
3604 rt2800_rfcsr_write(rt2x00dev
, 16, 0xb3);
3605 rt2800_rfcsr_write(rt2x00dev
, 17, 0x92);
3606 rt2800_rfcsr_write(rt2x00dev
, 18, 0x2c);
3607 rt2800_rfcsr_write(rt2x00dev
, 19, 0x02);
3608 rt2800_rfcsr_write(rt2x00dev
, 20, 0xba);
3609 rt2800_rfcsr_write(rt2x00dev
, 21, 0xdb);
3610 rt2800_rfcsr_write(rt2x00dev
, 22, 0x00);
3611 rt2800_rfcsr_write(rt2x00dev
, 23, 0x31);
3612 rt2800_rfcsr_write(rt2x00dev
, 24, 0x08);
3613 rt2800_rfcsr_write(rt2x00dev
, 25, 0x01);
3614 rt2800_rfcsr_write(rt2x00dev
, 26, 0x25);
3615 rt2800_rfcsr_write(rt2x00dev
, 27, 0x23);
3616 rt2800_rfcsr_write(rt2x00dev
, 28, 0x13);
3617 rt2800_rfcsr_write(rt2x00dev
, 29, 0x83);
3618 rt2800_rfcsr_write(rt2x00dev
, 30, 0x00);
3619 rt2800_rfcsr_write(rt2x00dev
, 31, 0x00);
3621 } else if (rt2x00_rt(rt2x00dev
, RT5390
)) {
3622 rt2800_rfcsr_write(rt2x00dev
, 1, 0x0f);
3623 rt2800_rfcsr_write(rt2x00dev
, 2, 0x80);
3624 rt2800_rfcsr_write(rt2x00dev
, 3, 0x88);
3625 rt2800_rfcsr_write(rt2x00dev
, 5, 0x10);
3626 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390F
))
3627 rt2800_rfcsr_write(rt2x00dev
, 6, 0xe0);
3629 rt2800_rfcsr_write(rt2x00dev
, 6, 0xa0);
3630 rt2800_rfcsr_write(rt2x00dev
, 7, 0x00);
3631 rt2800_rfcsr_write(rt2x00dev
, 10, 0x53);
3632 rt2800_rfcsr_write(rt2x00dev
, 11, 0x4a);
3633 rt2800_rfcsr_write(rt2x00dev
, 12, 0xc6);
3634 rt2800_rfcsr_write(rt2x00dev
, 13, 0x9f);
3635 rt2800_rfcsr_write(rt2x00dev
, 14, 0x00);
3636 rt2800_rfcsr_write(rt2x00dev
, 15, 0x00);
3637 rt2800_rfcsr_write(rt2x00dev
, 16, 0x00);
3638 rt2800_rfcsr_write(rt2x00dev
, 18, 0x03);
3639 rt2800_rfcsr_write(rt2x00dev
, 19, 0x00);
3641 rt2800_rfcsr_write(rt2x00dev
, 20, 0x00);
3642 rt2800_rfcsr_write(rt2x00dev
, 21, 0x00);
3643 rt2800_rfcsr_write(rt2x00dev
, 22, 0x20);
3644 rt2800_rfcsr_write(rt2x00dev
, 23, 0x00);
3645 rt2800_rfcsr_write(rt2x00dev
, 24, 0x00);
3646 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390F
))
3647 rt2800_rfcsr_write(rt2x00dev
, 25, 0x80);
3649 rt2800_rfcsr_write(rt2x00dev
, 25, 0xc0);
3650 rt2800_rfcsr_write(rt2x00dev
, 26, 0x00);
3651 rt2800_rfcsr_write(rt2x00dev
, 27, 0x09);
3652 rt2800_rfcsr_write(rt2x00dev
, 28, 0x00);
3653 rt2800_rfcsr_write(rt2x00dev
, 29, 0x10);
3655 rt2800_rfcsr_write(rt2x00dev
, 30, 0x00);
3656 rt2800_rfcsr_write(rt2x00dev
, 31, 0x80);
3657 rt2800_rfcsr_write(rt2x00dev
, 32, 0x80);
3658 rt2800_rfcsr_write(rt2x00dev
, 33, 0x00);
3659 rt2800_rfcsr_write(rt2x00dev
, 34, 0x07);
3660 rt2800_rfcsr_write(rt2x00dev
, 35, 0x12);
3661 rt2800_rfcsr_write(rt2x00dev
, 36, 0x00);
3662 rt2800_rfcsr_write(rt2x00dev
, 37, 0x08);
3663 rt2800_rfcsr_write(rt2x00dev
, 38, 0x85);
3664 rt2800_rfcsr_write(rt2x00dev
, 39, 0x1b);
3666 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390F
))
3667 rt2800_rfcsr_write(rt2x00dev
, 40, 0x0b);
3669 rt2800_rfcsr_write(rt2x00dev
, 40, 0x4b);
3670 rt2800_rfcsr_write(rt2x00dev
, 41, 0xbb);
3671 rt2800_rfcsr_write(rt2x00dev
, 42, 0xd2);
3672 rt2800_rfcsr_write(rt2x00dev
, 43, 0x9a);
3673 rt2800_rfcsr_write(rt2x00dev
, 44, 0x0e);
3674 rt2800_rfcsr_write(rt2x00dev
, 45, 0xa2);
3675 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390F
))
3676 rt2800_rfcsr_write(rt2x00dev
, 46, 0x73);
3678 rt2800_rfcsr_write(rt2x00dev
, 46, 0x7b);
3679 rt2800_rfcsr_write(rt2x00dev
, 47, 0x00);
3680 rt2800_rfcsr_write(rt2x00dev
, 48, 0x10);
3681 rt2800_rfcsr_write(rt2x00dev
, 49, 0x94);
3683 rt2800_rfcsr_write(rt2x00dev
, 52, 0x38);
3684 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390F
))
3685 rt2800_rfcsr_write(rt2x00dev
, 53, 0x00);
3687 rt2800_rfcsr_write(rt2x00dev
, 53, 0x84);
3688 rt2800_rfcsr_write(rt2x00dev
, 54, 0x78);
3689 rt2800_rfcsr_write(rt2x00dev
, 55, 0x44);
3690 rt2800_rfcsr_write(rt2x00dev
, 56, 0x22);
3691 rt2800_rfcsr_write(rt2x00dev
, 57, 0x80);
3692 rt2800_rfcsr_write(rt2x00dev
, 58, 0x7f);
3693 rt2800_rfcsr_write(rt2x00dev
, 59, 0x63);
3695 rt2800_rfcsr_write(rt2x00dev
, 60, 0x45);
3696 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390F
))
3697 rt2800_rfcsr_write(rt2x00dev
, 61, 0xd1);
3699 rt2800_rfcsr_write(rt2x00dev
, 61, 0xdd);
3700 rt2800_rfcsr_write(rt2x00dev
, 62, 0x00);
3701 rt2800_rfcsr_write(rt2x00dev
, 63, 0x00);
3702 } else if (rt2x00_rt(rt2x00dev
, RT5392
)) {
3703 rt2800_rfcsr_write(rt2x00dev
, 1, 0x17);
3704 rt2800_rfcsr_write(rt2x00dev
, 2, 0x80);
3705 rt2800_rfcsr_write(rt2x00dev
, 3, 0x88);
3706 rt2800_rfcsr_write(rt2x00dev
, 5, 0x10);
3707 rt2800_rfcsr_write(rt2x00dev
, 6, 0xe0);
3708 rt2800_rfcsr_write(rt2x00dev
, 7, 0x00);
3709 rt2800_rfcsr_write(rt2x00dev
, 10, 0x53);
3710 rt2800_rfcsr_write(rt2x00dev
, 11, 0x4a);
3711 rt2800_rfcsr_write(rt2x00dev
, 12, 0x46);
3712 rt2800_rfcsr_write(rt2x00dev
, 13, 0x9f);
3713 rt2800_rfcsr_write(rt2x00dev
, 14, 0x00);
3714 rt2800_rfcsr_write(rt2x00dev
, 15, 0x00);
3715 rt2800_rfcsr_write(rt2x00dev
, 16, 0x00);
3716 rt2800_rfcsr_write(rt2x00dev
, 18, 0x03);
3717 rt2800_rfcsr_write(rt2x00dev
, 19, 0x4d);
3718 rt2800_rfcsr_write(rt2x00dev
, 20, 0x00);
3719 rt2800_rfcsr_write(rt2x00dev
, 21, 0x8d);
3720 rt2800_rfcsr_write(rt2x00dev
, 22, 0x20);
3721 rt2800_rfcsr_write(rt2x00dev
, 23, 0x0b);
3722 rt2800_rfcsr_write(rt2x00dev
, 24, 0x44);
3723 rt2800_rfcsr_write(rt2x00dev
, 25, 0x80);
3724 rt2800_rfcsr_write(rt2x00dev
, 26, 0x82);
3725 rt2800_rfcsr_write(rt2x00dev
, 27, 0x09);
3726 rt2800_rfcsr_write(rt2x00dev
, 28, 0x00);
3727 rt2800_rfcsr_write(rt2x00dev
, 29, 0x10);
3728 rt2800_rfcsr_write(rt2x00dev
, 30, 0x10);
3729 rt2800_rfcsr_write(rt2x00dev
, 31, 0x80);
3730 rt2800_rfcsr_write(rt2x00dev
, 32, 0x20);
3731 rt2800_rfcsr_write(rt2x00dev
, 33, 0xC0);
3732 rt2800_rfcsr_write(rt2x00dev
, 34, 0x07);
3733 rt2800_rfcsr_write(rt2x00dev
, 35, 0x12);
3734 rt2800_rfcsr_write(rt2x00dev
, 36, 0x00);
3735 rt2800_rfcsr_write(rt2x00dev
, 37, 0x08);
3736 rt2800_rfcsr_write(rt2x00dev
, 38, 0x89);
3737 rt2800_rfcsr_write(rt2x00dev
, 39, 0x1b);
3738 rt2800_rfcsr_write(rt2x00dev
, 40, 0x0f);
3739 rt2800_rfcsr_write(rt2x00dev
, 41, 0xbb);
3740 rt2800_rfcsr_write(rt2x00dev
, 42, 0xd5);
3741 rt2800_rfcsr_write(rt2x00dev
, 43, 0x9b);
3742 rt2800_rfcsr_write(rt2x00dev
, 44, 0x0e);
3743 rt2800_rfcsr_write(rt2x00dev
, 45, 0xa2);
3744 rt2800_rfcsr_write(rt2x00dev
, 46, 0x73);
3745 rt2800_rfcsr_write(rt2x00dev
, 47, 0x0c);
3746 rt2800_rfcsr_write(rt2x00dev
, 48, 0x10);
3747 rt2800_rfcsr_write(rt2x00dev
, 49, 0x94);
3748 rt2800_rfcsr_write(rt2x00dev
, 50, 0x94);
3749 rt2800_rfcsr_write(rt2x00dev
, 51, 0x3a);
3750 rt2800_rfcsr_write(rt2x00dev
, 52, 0x48);
3751 rt2800_rfcsr_write(rt2x00dev
, 53, 0x44);
3752 rt2800_rfcsr_write(rt2x00dev
, 54, 0x38);
3753 rt2800_rfcsr_write(rt2x00dev
, 55, 0x43);
3754 rt2800_rfcsr_write(rt2x00dev
, 56, 0xa1);
3755 rt2800_rfcsr_write(rt2x00dev
, 57, 0x00);
3756 rt2800_rfcsr_write(rt2x00dev
, 58, 0x39);
3757 rt2800_rfcsr_write(rt2x00dev
, 59, 0x07);
3758 rt2800_rfcsr_write(rt2x00dev
, 60, 0x45);
3759 rt2800_rfcsr_write(rt2x00dev
, 61, 0x91);
3760 rt2800_rfcsr_write(rt2x00dev
, 62, 0x39);
3761 rt2800_rfcsr_write(rt2x00dev
, 63, 0x07);
3764 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070F
)) {
3765 rt2800_register_read(rt2x00dev
, LDO_CFG0
, ®
);
3766 rt2x00_set_field32(®
, LDO_CFG0_BGSEL
, 1);
3767 rt2x00_set_field32(®
, LDO_CFG0_LDO_CORE_VLEVEL
, 3);
3768 rt2800_register_write(rt2x00dev
, LDO_CFG0
, reg
);
3769 } else if (rt2x00_rt(rt2x00dev
, RT3071
) ||
3770 rt2x00_rt(rt2x00dev
, RT3090
)) {
3771 rt2800_rfcsr_write(rt2x00dev
, 31, 0x14);
3773 rt2800_rfcsr_read(rt2x00dev
, 6, &rfcsr
);
3774 rt2x00_set_field8(&rfcsr
, RFCSR6_R2
, 1);
3775 rt2800_rfcsr_write(rt2x00dev
, 6, rfcsr
);
3777 rt2800_register_read(rt2x00dev
, LDO_CFG0
, ®
);
3778 rt2x00_set_field32(®
, LDO_CFG0_BGSEL
, 1);
3779 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3071
, REV_RT3071E
) ||
3780 rt2x00_rt_rev_lt(rt2x00dev
, RT3090
, REV_RT3090E
)) {
3781 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF1
, &eeprom
);
3782 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF1_DAC_TEST
))
3783 rt2x00_set_field32(®
, LDO_CFG0_LDO_CORE_VLEVEL
, 3);
3785 rt2x00_set_field32(®
, LDO_CFG0_LDO_CORE_VLEVEL
, 0);
3787 rt2800_register_write(rt2x00dev
, LDO_CFG0
, reg
);
3789 rt2800_register_read(rt2x00dev
, GPIO_SWITCH
, ®
);
3790 rt2x00_set_field32(®
, GPIO_SWITCH_5
, 0);
3791 rt2800_register_write(rt2x00dev
, GPIO_SWITCH
, reg
);
3792 } else if (rt2x00_rt(rt2x00dev
, RT3390
)) {
3793 rt2800_register_read(rt2x00dev
, GPIO_SWITCH
, ®
);
3794 rt2x00_set_field32(®
, GPIO_SWITCH_5
, 0);
3795 rt2800_register_write(rt2x00dev
, GPIO_SWITCH
, reg
);
3796 } else if (rt2x00_rt(rt2x00dev
, RT3572
)) {
3797 rt2800_rfcsr_read(rt2x00dev
, 6, &rfcsr
);
3798 rt2x00_set_field8(&rfcsr
, RFCSR6_R2
, 1);
3799 rt2800_rfcsr_write(rt2x00dev
, 6, rfcsr
);
3801 rt2800_register_read(rt2x00dev
, LDO_CFG0
, ®
);
3802 rt2x00_set_field32(®
, LDO_CFG0_LDO_CORE_VLEVEL
, 3);
3803 rt2x00_set_field32(®
, LDO_CFG0_BGSEL
, 1);
3804 rt2800_register_write(rt2x00dev
, LDO_CFG0
, reg
);
3806 rt2800_register_read(rt2x00dev
, LDO_CFG0
, ®
);
3807 rt2x00_set_field32(®
, LDO_CFG0_BGSEL
, 1);
3808 rt2800_register_write(rt2x00dev
, LDO_CFG0
, reg
);
3812 * Set RX Filter calibration for 20MHz and 40MHz
3814 if (rt2x00_rt(rt2x00dev
, RT3070
)) {
3815 drv_data
->calibration_bw20
=
3816 rt2800_init_rx_filter(rt2x00dev
, false, 0x07, 0x16);
3817 drv_data
->calibration_bw40
=
3818 rt2800_init_rx_filter(rt2x00dev
, true, 0x27, 0x19);
3819 } else if (rt2x00_rt(rt2x00dev
, RT3071
) ||
3820 rt2x00_rt(rt2x00dev
, RT3090
) ||
3821 rt2x00_rt(rt2x00dev
, RT3390
) ||
3822 rt2x00_rt(rt2x00dev
, RT3572
)) {
3823 drv_data
->calibration_bw20
=
3824 rt2800_init_rx_filter(rt2x00dev
, false, 0x07, 0x13);
3825 drv_data
->calibration_bw40
=
3826 rt2800_init_rx_filter(rt2x00dev
, true, 0x27, 0x15);
3830 * Save BBP 25 & 26 values for later use in channel switching
3832 rt2800_bbp_read(rt2x00dev
, 25, &drv_data
->bbp25
);
3833 rt2800_bbp_read(rt2x00dev
, 26, &drv_data
->bbp26
);
3835 if (!rt2x00_rt(rt2x00dev
, RT5390
) &&
3836 !rt2x00_rt(rt2x00dev
, RT5392
)) {
3838 * Set back to initial state
3840 rt2800_bbp_write(rt2x00dev
, 24, 0);
3842 rt2800_rfcsr_read(rt2x00dev
, 22, &rfcsr
);
3843 rt2x00_set_field8(&rfcsr
, RFCSR22_BASEBAND_LOOPBACK
, 0);
3844 rt2800_rfcsr_write(rt2x00dev
, 22, rfcsr
);
3847 * Set BBP back to BW20
3849 rt2800_bbp_read(rt2x00dev
, 4, &bbp
);
3850 rt2x00_set_field8(&bbp
, BBP4_BANDWIDTH
, 0);
3851 rt2800_bbp_write(rt2x00dev
, 4, bbp
);
3854 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070F
) ||
3855 rt2x00_rt_rev_lt(rt2x00dev
, RT3071
, REV_RT3071E
) ||
3856 rt2x00_rt_rev_lt(rt2x00dev
, RT3090
, REV_RT3090E
) ||
3857 rt2x00_rt_rev_lt(rt2x00dev
, RT3390
, REV_RT3390E
))
3858 rt2800_rfcsr_write(rt2x00dev
, 27, 0x03);
3860 rt2800_register_read(rt2x00dev
, OPT_14_CSR
, ®
);
3861 rt2x00_set_field32(®
, OPT_14_CSR_BIT0
, 1);
3862 rt2800_register_write(rt2x00dev
, OPT_14_CSR
, reg
);
3864 if (!rt2x00_rt(rt2x00dev
, RT5390
) &&
3865 !rt2x00_rt(rt2x00dev
, RT5392
)) {
3866 rt2800_rfcsr_read(rt2x00dev
, 17, &rfcsr
);
3867 rt2x00_set_field8(&rfcsr
, RFCSR17_TX_LO1_EN
, 0);
3868 if (rt2x00_rt(rt2x00dev
, RT3070
) ||
3869 rt2x00_rt_rev_lt(rt2x00dev
, RT3071
, REV_RT3071E
) ||
3870 rt2x00_rt_rev_lt(rt2x00dev
, RT3090
, REV_RT3090E
) ||
3871 rt2x00_rt_rev_lt(rt2x00dev
, RT3390
, REV_RT3390E
)) {
3872 if (!test_bit(CAPABILITY_EXTERNAL_LNA_BG
,
3873 &rt2x00dev
->cap_flags
))
3874 rt2x00_set_field8(&rfcsr
, RFCSR17_R
, 1);
3876 rt2x00_set_field8(&rfcsr
, RFCSR17_TXMIXER_GAIN
,
3877 drv_data
->txmixer_gain_24g
);
3878 rt2800_rfcsr_write(rt2x00dev
, 17, rfcsr
);
3881 if (rt2x00_rt(rt2x00dev
, RT3090
)) {
3882 rt2800_bbp_read(rt2x00dev
, 138, &bbp
);
3884 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
3885 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF0
, &eeprom
);
3886 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_RXPATH
) == 1)
3887 rt2x00_set_field8(&bbp
, BBP138_RX_ADC1
, 0);
3888 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_TXPATH
) == 1)
3889 rt2x00_set_field8(&bbp
, BBP138_TX_DAC1
, 1);
3891 rt2800_bbp_write(rt2x00dev
, 138, bbp
);
3894 if (rt2x00_rt(rt2x00dev
, RT3071
) ||
3895 rt2x00_rt(rt2x00dev
, RT3090
) ||
3896 rt2x00_rt(rt2x00dev
, RT3390
)) {
3897 rt2800_rfcsr_read(rt2x00dev
, 1, &rfcsr
);
3898 rt2x00_set_field8(&rfcsr
, RFCSR1_RF_BLOCK_EN
, 1);
3899 rt2x00_set_field8(&rfcsr
, RFCSR1_RX0_PD
, 0);
3900 rt2x00_set_field8(&rfcsr
, RFCSR1_TX0_PD
, 0);
3901 rt2x00_set_field8(&rfcsr
, RFCSR1_RX1_PD
, 1);
3902 rt2x00_set_field8(&rfcsr
, RFCSR1_TX1_PD
, 1);
3903 rt2800_rfcsr_write(rt2x00dev
, 1, rfcsr
);
3905 rt2800_rfcsr_read(rt2x00dev
, 15, &rfcsr
);
3906 rt2x00_set_field8(&rfcsr
, RFCSR15_TX_LO2_EN
, 0);
3907 rt2800_rfcsr_write(rt2x00dev
, 15, rfcsr
);
3909 rt2800_rfcsr_read(rt2x00dev
, 20, &rfcsr
);
3910 rt2x00_set_field8(&rfcsr
, RFCSR20_RX_LO1_EN
, 0);
3911 rt2800_rfcsr_write(rt2x00dev
, 20, rfcsr
);
3913 rt2800_rfcsr_read(rt2x00dev
, 21, &rfcsr
);
3914 rt2x00_set_field8(&rfcsr
, RFCSR21_RX_LO2_EN
, 0);
3915 rt2800_rfcsr_write(rt2x00dev
, 21, rfcsr
);
3918 if (rt2x00_rt(rt2x00dev
, RT3070
)) {
3919 rt2800_rfcsr_read(rt2x00dev
, 27, &rfcsr
);
3920 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070F
))
3921 rt2x00_set_field8(&rfcsr
, RFCSR27_R1
, 3);
3923 rt2x00_set_field8(&rfcsr
, RFCSR27_R1
, 0);
3924 rt2x00_set_field8(&rfcsr
, RFCSR27_R2
, 0);
3925 rt2x00_set_field8(&rfcsr
, RFCSR27_R3
, 0);
3926 rt2x00_set_field8(&rfcsr
, RFCSR27_R4
, 0);
3927 rt2800_rfcsr_write(rt2x00dev
, 27, rfcsr
);
3930 if (rt2x00_rt(rt2x00dev
, RT5390
) ||
3931 rt2x00_rt(rt2x00dev
, RT5392
)) {
3932 rt2800_rfcsr_read(rt2x00dev
, 38, &rfcsr
);
3933 rt2x00_set_field8(&rfcsr
, RFCSR38_RX_LO1_EN
, 0);
3934 rt2800_rfcsr_write(rt2x00dev
, 38, rfcsr
);
3936 rt2800_rfcsr_read(rt2x00dev
, 39, &rfcsr
);
3937 rt2x00_set_field8(&rfcsr
, RFCSR39_RX_LO2_EN
, 0);
3938 rt2800_rfcsr_write(rt2x00dev
, 39, rfcsr
);
3940 rt2800_rfcsr_read(rt2x00dev
, 30, &rfcsr
);
3941 rt2x00_set_field8(&rfcsr
, RFCSR30_RX_VCM
, 2);
3942 rt2800_rfcsr_write(rt2x00dev
, 30, rfcsr
);
3948 int rt2800_enable_radio(struct rt2x00_dev
*rt2x00dev
)
3954 * Initialize all registers.
3956 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev
) ||
3957 rt2800_init_registers(rt2x00dev
) ||
3958 rt2800_init_bbp(rt2x00dev
) ||
3959 rt2800_init_rfcsr(rt2x00dev
)))
3963 * Send signal to firmware during boot time.
3965 rt2800_mcu_request(rt2x00dev
, MCU_BOOT_SIGNAL
, 0, 0, 0);
3967 if (rt2x00_is_usb(rt2x00dev
) &&
3968 (rt2x00_rt(rt2x00dev
, RT3070
) ||
3969 rt2x00_rt(rt2x00dev
, RT3071
) ||
3970 rt2x00_rt(rt2x00dev
, RT3572
))) {
3972 rt2800_mcu_request(rt2x00dev
, MCU_CURRENT
, 0, 0, 0);
3979 rt2800_register_read(rt2x00dev
, MAC_SYS_CTRL
, ®
);
3980 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_TX
, 1);
3981 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_RX
, 0);
3982 rt2800_register_write(rt2x00dev
, MAC_SYS_CTRL
, reg
);
3986 rt2800_register_read(rt2x00dev
, WPDMA_GLO_CFG
, ®
);
3987 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_TX_DMA
, 1);
3988 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_RX_DMA
, 1);
3989 rt2x00_set_field32(®
, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE
, 2);
3990 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_WRITEBACK_DONE
, 1);
3991 rt2800_register_write(rt2x00dev
, WPDMA_GLO_CFG
, reg
);
3993 rt2800_register_read(rt2x00dev
, MAC_SYS_CTRL
, ®
);
3994 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_TX
, 1);
3995 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_RX
, 1);
3996 rt2800_register_write(rt2x00dev
, MAC_SYS_CTRL
, reg
);
3999 * Initialize LED control
4001 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LED_AG_CONF
, &word
);
4002 rt2800_mcu_request(rt2x00dev
, MCU_LED_AG_CONF
, 0xff,
4003 word
& 0xff, (word
>> 8) & 0xff);
4005 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LED_ACT_CONF
, &word
);
4006 rt2800_mcu_request(rt2x00dev
, MCU_LED_ACT_CONF
, 0xff,
4007 word
& 0xff, (word
>> 8) & 0xff);
4009 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LED_POLARITY
, &word
);
4010 rt2800_mcu_request(rt2x00dev
, MCU_LED_LED_POLARITY
, 0xff,
4011 word
& 0xff, (word
>> 8) & 0xff);
4015 EXPORT_SYMBOL_GPL(rt2800_enable_radio
);
4017 void rt2800_disable_radio(struct rt2x00_dev
*rt2x00dev
)
4021 rt2800_disable_wpdma(rt2x00dev
);
4023 /* Wait for DMA, ignore error */
4024 rt2800_wait_wpdma_ready(rt2x00dev
);
4026 rt2800_register_read(rt2x00dev
, MAC_SYS_CTRL
, ®
);
4027 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_TX
, 0);
4028 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_RX
, 0);
4029 rt2800_register_write(rt2x00dev
, MAC_SYS_CTRL
, reg
);
4031 EXPORT_SYMBOL_GPL(rt2800_disable_radio
);
4033 int rt2800_efuse_detect(struct rt2x00_dev
*rt2x00dev
)
4037 rt2800_register_read(rt2x00dev
, EFUSE_CTRL
, ®
);
4039 return rt2x00_get_field32(reg
, EFUSE_CTRL_PRESENT
);
4041 EXPORT_SYMBOL_GPL(rt2800_efuse_detect
);
4043 static void rt2800_efuse_read(struct rt2x00_dev
*rt2x00dev
, unsigned int i
)
4047 mutex_lock(&rt2x00dev
->csr_mutex
);
4049 rt2800_register_read_lock(rt2x00dev
, EFUSE_CTRL
, ®
);
4050 rt2x00_set_field32(®
, EFUSE_CTRL_ADDRESS_IN
, i
);
4051 rt2x00_set_field32(®
, EFUSE_CTRL_MODE
, 0);
4052 rt2x00_set_field32(®
, EFUSE_CTRL_KICK
, 1);
4053 rt2800_register_write_lock(rt2x00dev
, EFUSE_CTRL
, reg
);
4055 /* Wait until the EEPROM has been loaded */
4056 rt2800_regbusy_read(rt2x00dev
, EFUSE_CTRL
, EFUSE_CTRL_KICK
, ®
);
4058 /* Apparently the data is read from end to start */
4059 rt2800_register_read_lock(rt2x00dev
, EFUSE_DATA3
, ®
);
4060 /* The returned value is in CPU order, but eeprom is le */
4061 *(u32
*)&rt2x00dev
->eeprom
[i
] = cpu_to_le32(reg
);
4062 rt2800_register_read_lock(rt2x00dev
, EFUSE_DATA2
, ®
);
4063 *(u32
*)&rt2x00dev
->eeprom
[i
+ 2] = cpu_to_le32(reg
);
4064 rt2800_register_read_lock(rt2x00dev
, EFUSE_DATA1
, ®
);
4065 *(u32
*)&rt2x00dev
->eeprom
[i
+ 4] = cpu_to_le32(reg
);
4066 rt2800_register_read_lock(rt2x00dev
, EFUSE_DATA0
, ®
);
4067 *(u32
*)&rt2x00dev
->eeprom
[i
+ 6] = cpu_to_le32(reg
);
4069 mutex_unlock(&rt2x00dev
->csr_mutex
);
4072 void rt2800_read_eeprom_efuse(struct rt2x00_dev
*rt2x00dev
)
4076 for (i
= 0; i
< EEPROM_SIZE
/ sizeof(u16
); i
+= 8)
4077 rt2800_efuse_read(rt2x00dev
, i
);
4079 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse
);
4081 int rt2800_validate_eeprom(struct rt2x00_dev
*rt2x00dev
)
4083 struct rt2800_drv_data
*drv_data
= rt2x00dev
->drv_data
;
4086 u8 default_lna_gain
;
4089 * Start validation of the data that has been read.
4091 mac
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_MAC_ADDR_0
);
4092 if (!is_valid_ether_addr(mac
)) {
4093 random_ether_addr(mac
);
4094 EEPROM(rt2x00dev
, "MAC: %pM\n", mac
);
4097 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF0
, &word
);
4098 if (word
== 0xffff) {
4099 rt2x00_set_field16(&word
, EEPROM_NIC_CONF0_RXPATH
, 2);
4100 rt2x00_set_field16(&word
, EEPROM_NIC_CONF0_TXPATH
, 1);
4101 rt2x00_set_field16(&word
, EEPROM_NIC_CONF0_RF_TYPE
, RF2820
);
4102 rt2x00_eeprom_write(rt2x00dev
, EEPROM_NIC_CONF0
, word
);
4103 EEPROM(rt2x00dev
, "Antenna: 0x%04x\n", word
);
4104 } else if (rt2x00_rt(rt2x00dev
, RT2860
) ||
4105 rt2x00_rt(rt2x00dev
, RT2872
)) {
4107 * There is a max of 2 RX streams for RT28x0 series
4109 if (rt2x00_get_field16(word
, EEPROM_NIC_CONF0_RXPATH
) > 2)
4110 rt2x00_set_field16(&word
, EEPROM_NIC_CONF0_RXPATH
, 2);
4111 rt2x00_eeprom_write(rt2x00dev
, EEPROM_NIC_CONF0
, word
);
4114 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF1
, &word
);
4115 if (word
== 0xffff) {
4116 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_HW_RADIO
, 0);
4117 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC
, 0);
4118 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G
, 0);
4119 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G
, 0);
4120 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_CARDBUS_ACCEL
, 0);
4121 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_BW40M_SB_2G
, 0);
4122 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_BW40M_SB_5G
, 0);
4123 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_WPS_PBC
, 0);
4124 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_BW40M_2G
, 0);
4125 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_BW40M_5G
, 0);
4126 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA
, 0);
4127 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_ANT_DIVERSITY
, 0);
4128 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_INTERNAL_TX_ALC
, 0);
4129 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_BT_COEXIST
, 0);
4130 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_DAC_TEST
, 0);
4131 rt2x00_eeprom_write(rt2x00dev
, EEPROM_NIC_CONF1
, word
);
4132 EEPROM(rt2x00dev
, "NIC: 0x%04x\n", word
);
4135 rt2x00_eeprom_read(rt2x00dev
, EEPROM_FREQ
, &word
);
4136 if ((word
& 0x00ff) == 0x00ff) {
4137 rt2x00_set_field16(&word
, EEPROM_FREQ_OFFSET
, 0);
4138 rt2x00_eeprom_write(rt2x00dev
, EEPROM_FREQ
, word
);
4139 EEPROM(rt2x00dev
, "Freq: 0x%04x\n", word
);
4141 if ((word
& 0xff00) == 0xff00) {
4142 rt2x00_set_field16(&word
, EEPROM_FREQ_LED_MODE
,
4143 LED_MODE_TXRX_ACTIVITY
);
4144 rt2x00_set_field16(&word
, EEPROM_FREQ_LED_POLARITY
, 0);
4145 rt2x00_eeprom_write(rt2x00dev
, EEPROM_FREQ
, word
);
4146 rt2x00_eeprom_write(rt2x00dev
, EEPROM_LED_AG_CONF
, 0x5555);
4147 rt2x00_eeprom_write(rt2x00dev
, EEPROM_LED_ACT_CONF
, 0x2221);
4148 rt2x00_eeprom_write(rt2x00dev
, EEPROM_LED_POLARITY
, 0xa9f8);
4149 EEPROM(rt2x00dev
, "Led Mode: 0x%04x\n", word
);
4153 * During the LNA validation we are going to use
4154 * lna0 as correct value. Note that EEPROM_LNA
4155 * is never validated.
4157 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LNA
, &word
);
4158 default_lna_gain
= rt2x00_get_field16(word
, EEPROM_LNA_A0
);
4160 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_BG
, &word
);
4161 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_BG_OFFSET0
)) > 10)
4162 rt2x00_set_field16(&word
, EEPROM_RSSI_BG_OFFSET0
, 0);
4163 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_BG_OFFSET1
)) > 10)
4164 rt2x00_set_field16(&word
, EEPROM_RSSI_BG_OFFSET1
, 0);
4165 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_BG
, word
);
4167 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TXMIXER_GAIN_BG
, &word
);
4168 if ((word
& 0x00ff) != 0x00ff) {
4169 drv_data
->txmixer_gain_24g
=
4170 rt2x00_get_field16(word
, EEPROM_TXMIXER_GAIN_BG_VAL
);
4172 drv_data
->txmixer_gain_24g
= 0;
4175 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_BG2
, &word
);
4176 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_BG2_OFFSET2
)) > 10)
4177 rt2x00_set_field16(&word
, EEPROM_RSSI_BG2_OFFSET2
, 0);
4178 if (rt2x00_get_field16(word
, EEPROM_RSSI_BG2_LNA_A1
) == 0x00 ||
4179 rt2x00_get_field16(word
, EEPROM_RSSI_BG2_LNA_A1
) == 0xff)
4180 rt2x00_set_field16(&word
, EEPROM_RSSI_BG2_LNA_A1
,
4182 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_BG2
, word
);
4184 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TXMIXER_GAIN_A
, &word
);
4185 if ((word
& 0x00ff) != 0x00ff) {
4186 drv_data
->txmixer_gain_5g
=
4187 rt2x00_get_field16(word
, EEPROM_TXMIXER_GAIN_A_VAL
);
4189 drv_data
->txmixer_gain_5g
= 0;
4192 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_A
, &word
);
4193 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_A_OFFSET0
)) > 10)
4194 rt2x00_set_field16(&word
, EEPROM_RSSI_A_OFFSET0
, 0);
4195 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_A_OFFSET1
)) > 10)
4196 rt2x00_set_field16(&word
, EEPROM_RSSI_A_OFFSET1
, 0);
4197 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_A
, word
);
4199 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_A2
, &word
);
4200 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_A2_OFFSET2
)) > 10)
4201 rt2x00_set_field16(&word
, EEPROM_RSSI_A2_OFFSET2
, 0);
4202 if (rt2x00_get_field16(word
, EEPROM_RSSI_A2_LNA_A2
) == 0x00 ||
4203 rt2x00_get_field16(word
, EEPROM_RSSI_A2_LNA_A2
) == 0xff)
4204 rt2x00_set_field16(&word
, EEPROM_RSSI_A2_LNA_A2
,
4206 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_A2
, word
);
4210 EXPORT_SYMBOL_GPL(rt2800_validate_eeprom
);
4212 int rt2800_init_eeprom(struct rt2x00_dev
*rt2x00dev
)
4219 * Read EEPROM word for configuration.
4221 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF0
, &eeprom
);
4224 * Identify RF chipset by EEPROM value
4225 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
4226 * RT53xx: defined in "EEPROM_CHIP_ID" field
4228 rt2800_register_read(rt2x00dev
, MAC_CSR0
, ®
);
4229 if (rt2x00_get_field32(reg
, MAC_CSR0_CHIPSET
) == RT5390
||
4230 rt2x00_get_field32(reg
, MAC_CSR0_CHIPSET
) == RT5392
)
4231 rt2x00_eeprom_read(rt2x00dev
, EEPROM_CHIP_ID
, &value
);
4233 value
= rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_RF_TYPE
);
4235 rt2x00_set_chip(rt2x00dev
, rt2x00_get_field32(reg
, MAC_CSR0_CHIPSET
),
4236 value
, rt2x00_get_field32(reg
, MAC_CSR0_REVISION
));
4238 switch (rt2x00dev
->chip
.rt
) {
4251 ERROR(rt2x00dev
, "Invalid RT chipset 0x%04x detected.\n", rt2x00dev
->chip
.rt
);
4255 switch (rt2x00dev
->chip
.rf
) {
4271 ERROR(rt2x00dev
, "Invalid RF chipset 0x%04x detected.\n",
4272 rt2x00dev
->chip
.rf
);
4277 * Identify default antenna configuration.
4279 rt2x00dev
->default_ant
.tx_chain_num
=
4280 rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_TXPATH
);
4281 rt2x00dev
->default_ant
.rx_chain_num
=
4282 rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_RXPATH
);
4284 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF1
, &eeprom
);
4286 if (rt2x00_rt(rt2x00dev
, RT3070
) ||
4287 rt2x00_rt(rt2x00dev
, RT3090
) ||
4288 rt2x00_rt(rt2x00dev
, RT3390
)) {
4289 value
= rt2x00_get_field16(eeprom
,
4290 EEPROM_NIC_CONF1_ANT_DIVERSITY
);
4295 rt2x00dev
->default_ant
.tx
= ANTENNA_A
;
4296 rt2x00dev
->default_ant
.rx
= ANTENNA_A
;
4299 rt2x00dev
->default_ant
.tx
= ANTENNA_A
;
4300 rt2x00dev
->default_ant
.rx
= ANTENNA_B
;
4304 rt2x00dev
->default_ant
.tx
= ANTENNA_A
;
4305 rt2x00dev
->default_ant
.rx
= ANTENNA_A
;
4308 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390R
)) {
4309 rt2x00dev
->default_ant
.tx
= ANTENNA_HW_DIVERSITY
; /* Unused */
4310 rt2x00dev
->default_ant
.rx
= ANTENNA_HW_DIVERSITY
; /* Unused */
4314 * Determine external LNA informations.
4316 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G
))
4317 __set_bit(CAPABILITY_EXTERNAL_LNA_A
, &rt2x00dev
->cap_flags
);
4318 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G
))
4319 __set_bit(CAPABILITY_EXTERNAL_LNA_BG
, &rt2x00dev
->cap_flags
);
4322 * Detect if this device has an hardware controlled radio.
4324 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF1_HW_RADIO
))
4325 __set_bit(CAPABILITY_HW_BUTTON
, &rt2x00dev
->cap_flags
);
4328 * Detect if this device has Bluetooth co-existence.
4330 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF1_BT_COEXIST
))
4331 __set_bit(CAPABILITY_BT_COEXIST
, &rt2x00dev
->cap_flags
);
4334 * Read frequency offset and RF programming sequence.
4336 rt2x00_eeprom_read(rt2x00dev
, EEPROM_FREQ
, &eeprom
);
4337 rt2x00dev
->freq_offset
= rt2x00_get_field16(eeprom
, EEPROM_FREQ_OFFSET
);
4340 * Store led settings, for correct led behaviour.
4342 #ifdef CONFIG_RT2X00_LIB_LEDS
4343 rt2800_init_led(rt2x00dev
, &rt2x00dev
->led_radio
, LED_TYPE_RADIO
);
4344 rt2800_init_led(rt2x00dev
, &rt2x00dev
->led_assoc
, LED_TYPE_ASSOC
);
4345 rt2800_init_led(rt2x00dev
, &rt2x00dev
->led_qual
, LED_TYPE_QUALITY
);
4347 rt2x00dev
->led_mcu_reg
= eeprom
;
4348 #endif /* CONFIG_RT2X00_LIB_LEDS */
4351 * Check if support EIRP tx power limit feature.
4353 rt2x00_eeprom_read(rt2x00dev
, EEPROM_EIRP_MAX_TX_POWER
, &eeprom
);
4355 if (rt2x00_get_field16(eeprom
, EEPROM_EIRP_MAX_TX_POWER_2GHZ
) <
4356 EIRP_MAX_TX_POWER_LIMIT
)
4357 __set_bit(CAPABILITY_POWER_LIMIT
, &rt2x00dev
->cap_flags
);
4361 EXPORT_SYMBOL_GPL(rt2800_init_eeprom
);
4364 * RF value list for rt28xx
4365 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
4367 static const struct rf_channel rf_vals
[] = {
4368 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
4369 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
4370 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
4371 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
4372 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
4373 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
4374 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
4375 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
4376 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
4377 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
4378 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
4379 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
4380 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
4381 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
4383 /* 802.11 UNI / HyperLan 2 */
4384 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
4385 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
4386 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
4387 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
4388 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
4389 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
4390 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
4391 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
4392 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
4393 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
4394 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
4395 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
4397 /* 802.11 HyperLan 2 */
4398 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
4399 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
4400 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
4401 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
4402 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
4403 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
4404 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
4405 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
4406 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
4407 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
4408 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
4409 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
4410 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
4411 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
4412 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
4413 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
4416 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
4417 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
4418 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
4419 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
4420 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
4421 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
4422 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
4423 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
4424 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
4425 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
4426 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
4429 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
4430 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
4431 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
4432 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
4433 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
4434 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
4435 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
4439 * RF value list for rt3xxx
4440 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
4442 static const struct rf_channel rf_vals_3x
[] = {
4458 /* 802.11 UNI / HyperLan 2 */
4472 /* 802.11 HyperLan 2 */
4504 int rt2800_probe_hw_mode(struct rt2x00_dev
*rt2x00dev
)
4506 struct hw_mode_spec
*spec
= &rt2x00dev
->spec
;
4507 struct channel_info
*info
;
4508 char *default_power1
;
4509 char *default_power2
;
4514 * Disable powersaving as default on PCI devices.
4516 if (rt2x00_is_pci(rt2x00dev
) || rt2x00_is_soc(rt2x00dev
))
4517 rt2x00dev
->hw
->wiphy
->flags
&= ~WIPHY_FLAG_PS_ON_BY_DEFAULT
;
4520 * Initialize all hw fields.
4522 rt2x00dev
->hw
->flags
=
4523 IEEE80211_HW_SIGNAL_DBM
|
4524 IEEE80211_HW_SUPPORTS_PS
|
4525 IEEE80211_HW_PS_NULLFUNC_STACK
|
4526 IEEE80211_HW_AMPDU_AGGREGATION
|
4527 IEEE80211_HW_REPORTS_TX_ACK_STATUS
;
4530 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
4531 * unless we are capable of sending the buffered frames out after the
4532 * DTIM transmission using rt2x00lib_beacondone. This will send out
4533 * multicast and broadcast traffic immediately instead of buffering it
4534 * infinitly and thus dropping it after some time.
4536 if (!rt2x00_is_usb(rt2x00dev
))
4537 rt2x00dev
->hw
->flags
|=
4538 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING
;
4540 SET_IEEE80211_DEV(rt2x00dev
->hw
, rt2x00dev
->dev
);
4541 SET_IEEE80211_PERM_ADDR(rt2x00dev
->hw
,
4542 rt2x00_eeprom_addr(rt2x00dev
,
4543 EEPROM_MAC_ADDR_0
));
4546 * As rt2800 has a global fallback table we cannot specify
4547 * more then one tx rate per frame but since the hw will
4548 * try several rates (based on the fallback table) we should
4549 * initialize max_report_rates to the maximum number of rates
4550 * we are going to try. Otherwise mac80211 will truncate our
4551 * reported tx rates and the rc algortihm will end up with
4554 rt2x00dev
->hw
->max_rates
= 1;
4555 rt2x00dev
->hw
->max_report_rates
= 7;
4556 rt2x00dev
->hw
->max_rate_tries
= 1;
4558 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF0
, &eeprom
);
4561 * Initialize hw_mode information.
4563 spec
->supported_bands
= SUPPORT_BAND_2GHZ
;
4564 spec
->supported_rates
= SUPPORT_RATE_CCK
| SUPPORT_RATE_OFDM
;
4566 if (rt2x00_rf(rt2x00dev
, RF2820
) ||
4567 rt2x00_rf(rt2x00dev
, RF2720
)) {
4568 spec
->num_channels
= 14;
4569 spec
->channels
= rf_vals
;
4570 } else if (rt2x00_rf(rt2x00dev
, RF2850
) ||
4571 rt2x00_rf(rt2x00dev
, RF2750
)) {
4572 spec
->supported_bands
|= SUPPORT_BAND_5GHZ
;
4573 spec
->num_channels
= ARRAY_SIZE(rf_vals
);
4574 spec
->channels
= rf_vals
;
4575 } else if (rt2x00_rf(rt2x00dev
, RF3020
) ||
4576 rt2x00_rf(rt2x00dev
, RF2020
) ||
4577 rt2x00_rf(rt2x00dev
, RF3021
) ||
4578 rt2x00_rf(rt2x00dev
, RF3022
) ||
4579 rt2x00_rf(rt2x00dev
, RF3320
) ||
4580 rt2x00_rf(rt2x00dev
, RF5370
) ||
4581 rt2x00_rf(rt2x00dev
, RF5372
) ||
4582 rt2x00_rf(rt2x00dev
, RF5390
)) {
4583 spec
->num_channels
= 14;
4584 spec
->channels
= rf_vals_3x
;
4585 } else if (rt2x00_rf(rt2x00dev
, RF3052
)) {
4586 spec
->supported_bands
|= SUPPORT_BAND_5GHZ
;
4587 spec
->num_channels
= ARRAY_SIZE(rf_vals_3x
);
4588 spec
->channels
= rf_vals_3x
;
4592 * Initialize HT information.
4594 if (!rt2x00_rf(rt2x00dev
, RF2020
))
4595 spec
->ht
.ht_supported
= true;
4597 spec
->ht
.ht_supported
= false;
4600 IEEE80211_HT_CAP_SUP_WIDTH_20_40
|
4601 IEEE80211_HT_CAP_GRN_FLD
|
4602 IEEE80211_HT_CAP_SGI_20
|
4603 IEEE80211_HT_CAP_SGI_40
;
4605 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_TXPATH
) >= 2)
4606 spec
->ht
.cap
|= IEEE80211_HT_CAP_TX_STBC
;
4609 rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_RXPATH
) <<
4610 IEEE80211_HT_CAP_RX_STBC_SHIFT
;
4612 spec
->ht
.ampdu_factor
= 3;
4613 spec
->ht
.ampdu_density
= 4;
4614 spec
->ht
.mcs
.tx_params
=
4615 IEEE80211_HT_MCS_TX_DEFINED
|
4616 IEEE80211_HT_MCS_TX_RX_DIFF
|
4617 ((rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_TXPATH
) - 1) <<
4618 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT
);
4620 switch (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_RXPATH
)) {
4622 spec
->ht
.mcs
.rx_mask
[2] = 0xff;
4624 spec
->ht
.mcs
.rx_mask
[1] = 0xff;
4626 spec
->ht
.mcs
.rx_mask
[0] = 0xff;
4627 spec
->ht
.mcs
.rx_mask
[4] = 0x1; /* MCS32 */
4632 * Create channel information array
4634 info
= kcalloc(spec
->num_channels
, sizeof(*info
), GFP_KERNEL
);
4638 spec
->channels_info
= info
;
4640 default_power1
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_BG1
);
4641 default_power2
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_BG2
);
4643 for (i
= 0; i
< 14; i
++) {
4644 info
[i
].default_power1
= default_power1
[i
];
4645 info
[i
].default_power2
= default_power2
[i
];
4648 if (spec
->num_channels
> 14) {
4649 default_power1
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_A1
);
4650 default_power2
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_A2
);
4652 for (i
= 14; i
< spec
->num_channels
; i
++) {
4653 info
[i
].default_power1
= default_power1
[i
];
4654 info
[i
].default_power2
= default_power2
[i
];
4658 switch (rt2x00dev
->chip
.rf
) {
4668 __set_bit(CAPABILITY_VCO_RECALIBRATION
, &rt2x00dev
->cap_flags
);
4674 EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode
);
4677 * IEEE80211 stack callback functions.
4679 void rt2800_get_tkip_seq(struct ieee80211_hw
*hw
, u8 hw_key_idx
, u32
*iv32
,
4682 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
4683 struct mac_iveiv_entry iveiv_entry
;
4686 offset
= MAC_IVEIV_ENTRY(hw_key_idx
);
4687 rt2800_register_multiread(rt2x00dev
, offset
,
4688 &iveiv_entry
, sizeof(iveiv_entry
));
4690 memcpy(iv16
, &iveiv_entry
.iv
[0], sizeof(*iv16
));
4691 memcpy(iv32
, &iveiv_entry
.iv
[4], sizeof(*iv32
));
4693 EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq
);
4695 int rt2800_set_rts_threshold(struct ieee80211_hw
*hw
, u32 value
)
4697 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
4699 bool enabled
= (value
< IEEE80211_MAX_RTS_THRESHOLD
);
4701 rt2800_register_read(rt2x00dev
, TX_RTS_CFG
, ®
);
4702 rt2x00_set_field32(®
, TX_RTS_CFG_RTS_THRES
, value
);
4703 rt2800_register_write(rt2x00dev
, TX_RTS_CFG
, reg
);
4705 rt2800_register_read(rt2x00dev
, CCK_PROT_CFG
, ®
);
4706 rt2x00_set_field32(®
, CCK_PROT_CFG_RTS_TH_EN
, enabled
);
4707 rt2800_register_write(rt2x00dev
, CCK_PROT_CFG
, reg
);
4709 rt2800_register_read(rt2x00dev
, OFDM_PROT_CFG
, ®
);
4710 rt2x00_set_field32(®
, OFDM_PROT_CFG_RTS_TH_EN
, enabled
);
4711 rt2800_register_write(rt2x00dev
, OFDM_PROT_CFG
, reg
);
4713 rt2800_register_read(rt2x00dev
, MM20_PROT_CFG
, ®
);
4714 rt2x00_set_field32(®
, MM20_PROT_CFG_RTS_TH_EN
, enabled
);
4715 rt2800_register_write(rt2x00dev
, MM20_PROT_CFG
, reg
);
4717 rt2800_register_read(rt2x00dev
, MM40_PROT_CFG
, ®
);
4718 rt2x00_set_field32(®
, MM40_PROT_CFG_RTS_TH_EN
, enabled
);
4719 rt2800_register_write(rt2x00dev
, MM40_PROT_CFG
, reg
);
4721 rt2800_register_read(rt2x00dev
, GF20_PROT_CFG
, ®
);
4722 rt2x00_set_field32(®
, GF20_PROT_CFG_RTS_TH_EN
, enabled
);
4723 rt2800_register_write(rt2x00dev
, GF20_PROT_CFG
, reg
);
4725 rt2800_register_read(rt2x00dev
, GF40_PROT_CFG
, ®
);
4726 rt2x00_set_field32(®
, GF40_PROT_CFG_RTS_TH_EN
, enabled
);
4727 rt2800_register_write(rt2x00dev
, GF40_PROT_CFG
, reg
);
4731 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold
);
4733 int rt2800_conf_tx(struct ieee80211_hw
*hw
,
4734 struct ieee80211_vif
*vif
, u16 queue_idx
,
4735 const struct ieee80211_tx_queue_params
*params
)
4737 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
4738 struct data_queue
*queue
;
4739 struct rt2x00_field32 field
;
4745 * First pass the configuration through rt2x00lib, that will
4746 * update the queue settings and validate the input. After that
4747 * we are free to update the registers based on the value
4748 * in the queue parameter.
4750 retval
= rt2x00mac_conf_tx(hw
, vif
, queue_idx
, params
);
4755 * We only need to perform additional register initialization
4761 queue
= rt2x00queue_get_tx_queue(rt2x00dev
, queue_idx
);
4763 /* Update WMM TXOP register */
4764 offset
= WMM_TXOP0_CFG
+ (sizeof(u32
) * (!!(queue_idx
& 2)));
4765 field
.bit_offset
= (queue_idx
& 1) * 16;
4766 field
.bit_mask
= 0xffff << field
.bit_offset
;
4768 rt2800_register_read(rt2x00dev
, offset
, ®
);
4769 rt2x00_set_field32(®
, field
, queue
->txop
);
4770 rt2800_register_write(rt2x00dev
, offset
, reg
);
4772 /* Update WMM registers */
4773 field
.bit_offset
= queue_idx
* 4;
4774 field
.bit_mask
= 0xf << field
.bit_offset
;
4776 rt2800_register_read(rt2x00dev
, WMM_AIFSN_CFG
, ®
);
4777 rt2x00_set_field32(®
, field
, queue
->aifs
);
4778 rt2800_register_write(rt2x00dev
, WMM_AIFSN_CFG
, reg
);
4780 rt2800_register_read(rt2x00dev
, WMM_CWMIN_CFG
, ®
);
4781 rt2x00_set_field32(®
, field
, queue
->cw_min
);
4782 rt2800_register_write(rt2x00dev
, WMM_CWMIN_CFG
, reg
);
4784 rt2800_register_read(rt2x00dev
, WMM_CWMAX_CFG
, ®
);
4785 rt2x00_set_field32(®
, field
, queue
->cw_max
);
4786 rt2800_register_write(rt2x00dev
, WMM_CWMAX_CFG
, reg
);
4788 /* Update EDCA registers */
4789 offset
= EDCA_AC0_CFG
+ (sizeof(u32
) * queue_idx
);
4791 rt2800_register_read(rt2x00dev
, offset
, ®
);
4792 rt2x00_set_field32(®
, EDCA_AC0_CFG_TX_OP
, queue
->txop
);
4793 rt2x00_set_field32(®
, EDCA_AC0_CFG_AIFSN
, queue
->aifs
);
4794 rt2x00_set_field32(®
, EDCA_AC0_CFG_CWMIN
, queue
->cw_min
);
4795 rt2x00_set_field32(®
, EDCA_AC0_CFG_CWMAX
, queue
->cw_max
);
4796 rt2800_register_write(rt2x00dev
, offset
, reg
);
4800 EXPORT_SYMBOL_GPL(rt2800_conf_tx
);
4802 u64
rt2800_get_tsf(struct ieee80211_hw
*hw
, struct ieee80211_vif
*vif
)
4804 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
4808 rt2800_register_read(rt2x00dev
, TSF_TIMER_DW1
, ®
);
4809 tsf
= (u64
) rt2x00_get_field32(reg
, TSF_TIMER_DW1_HIGH_WORD
) << 32;
4810 rt2800_register_read(rt2x00dev
, TSF_TIMER_DW0
, ®
);
4811 tsf
|= rt2x00_get_field32(reg
, TSF_TIMER_DW0_LOW_WORD
);
4815 EXPORT_SYMBOL_GPL(rt2800_get_tsf
);
4817 int rt2800_ampdu_action(struct ieee80211_hw
*hw
, struct ieee80211_vif
*vif
,
4818 enum ieee80211_ampdu_mlme_action action
,
4819 struct ieee80211_sta
*sta
, u16 tid
, u16
*ssn
,
4822 struct rt2x00_sta
*sta_priv
= (struct rt2x00_sta
*)sta
->drv_priv
;
4826 * Don't allow aggregation for stations the hardware isn't aware
4827 * of because tx status reports for frames to an unknown station
4828 * always contain wcid=255 and thus we can't distinguish between
4829 * multiple stations which leads to unwanted situations when the
4830 * hw reorders frames due to aggregation.
4832 if (sta_priv
->wcid
< 0)
4836 case IEEE80211_AMPDU_RX_START
:
4837 case IEEE80211_AMPDU_RX_STOP
:
4839 * The hw itself takes care of setting up BlockAck mechanisms.
4840 * So, we only have to allow mac80211 to nagotiate a BlockAck
4841 * agreement. Once that is done, the hw will BlockAck incoming
4842 * AMPDUs without further setup.
4845 case IEEE80211_AMPDU_TX_START
:
4846 ieee80211_start_tx_ba_cb_irqsafe(vif
, sta
->addr
, tid
);
4848 case IEEE80211_AMPDU_TX_STOP
:
4849 ieee80211_stop_tx_ba_cb_irqsafe(vif
, sta
->addr
, tid
);
4851 case IEEE80211_AMPDU_TX_OPERATIONAL
:
4854 WARNING((struct rt2x00_dev
*)hw
->priv
, "Unknown AMPDU action\n");
4859 EXPORT_SYMBOL_GPL(rt2800_ampdu_action
);
4861 int rt2800_get_survey(struct ieee80211_hw
*hw
, int idx
,
4862 struct survey_info
*survey
)
4864 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
4865 struct ieee80211_conf
*conf
= &hw
->conf
;
4866 u32 idle
, busy
, busy_ext
;
4871 survey
->channel
= conf
->channel
;
4873 rt2800_register_read(rt2x00dev
, CH_IDLE_STA
, &idle
);
4874 rt2800_register_read(rt2x00dev
, CH_BUSY_STA
, &busy
);
4875 rt2800_register_read(rt2x00dev
, CH_BUSY_STA_SEC
, &busy_ext
);
4878 survey
->filled
= SURVEY_INFO_CHANNEL_TIME
|
4879 SURVEY_INFO_CHANNEL_TIME_BUSY
|
4880 SURVEY_INFO_CHANNEL_TIME_EXT_BUSY
;
4882 survey
->channel_time
= (idle
+ busy
) / 1000;
4883 survey
->channel_time_busy
= busy
/ 1000;
4884 survey
->channel_time_ext_busy
= busy_ext
/ 1000;
4887 if (!(hw
->conf
.flags
& IEEE80211_CONF_OFFCHANNEL
))
4888 survey
->filled
|= SURVEY_INFO_IN_USE
;
4893 EXPORT_SYMBOL_GPL(rt2800_get_survey
);
4895 MODULE_AUTHOR(DRV_PROJECT
", Bartlomiej Zolnierkiewicz");
4896 MODULE_VERSION(DRV_VERSION
);
4897 MODULE_DESCRIPTION("Ralink RT2800 library");
4898 MODULE_LICENSE("GPL");