2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
3 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
4 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
5 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
7 Based on the original rt2800pci.c and rt2800usb.c.
8 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
9 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
10 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
11 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
12 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
13 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
14 <http://rt2x00.serialmonkey.com>
16 This program is free software; you can redistribute it and/or modify
17 it under the terms of the GNU General Public License as published by
18 the Free Software Foundation; either version 2 of the License, or
19 (at your option) any later version.
21 This program is distributed in the hope that it will be useful,
22 but WITHOUT ANY WARRANTY; without even the implied warranty of
23 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 GNU General Public License for more details.
26 You should have received a copy of the GNU General Public License
27 along with this program; if not, write to the
28 Free Software Foundation, Inc.,
29 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
34 Abstract: rt2800 generic device routines.
37 #include <linux/crc-ccitt.h>
38 #include <linux/kernel.h>
39 #include <linux/module.h>
40 #include <linux/slab.h>
43 #include "rt2800lib.h"
48 * All access to the CSR registers will go through the methods
49 * rt2800_register_read and rt2800_register_write.
50 * BBP and RF register require indirect register access,
51 * and use the CSR registers BBPCSR and RFCSR to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
55 * between each attampt. When the busy bit is still set at that time,
56 * the access attempt is considered to have failed,
57 * and we will print an error.
58 * The _lock versions must be used if you already hold the csr_mutex
60 #define WAIT_FOR_BBP(__dev, __reg) \
61 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
62 #define WAIT_FOR_RFCSR(__dev, __reg) \
63 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
64 #define WAIT_FOR_RF(__dev, __reg) \
65 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
66 #define WAIT_FOR_MCU(__dev, __reg) \
67 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
68 H2M_MAILBOX_CSR_OWNER, (__reg))
70 static inline bool rt2800_is_305x_soc(struct rt2x00_dev
*rt2x00dev
)
72 /* check for rt2872 on SoC */
73 if (!rt2x00_is_soc(rt2x00dev
) ||
74 !rt2x00_rt(rt2x00dev
, RT2872
))
77 /* we know for sure that these rf chipsets are used on rt305x boards */
78 if (rt2x00_rf(rt2x00dev
, RF3020
) ||
79 rt2x00_rf(rt2x00dev
, RF3021
) ||
80 rt2x00_rf(rt2x00dev
, RF3022
))
83 rt2x00_warn(rt2x00dev
, "Unknown RF chipset on rt305x\n");
87 static void rt2800_bbp_write(struct rt2x00_dev
*rt2x00dev
,
88 const unsigned int word
, const u8 value
)
92 mutex_lock(&rt2x00dev
->csr_mutex
);
95 * Wait until the BBP becomes available, afterwards we
96 * can safely write the new data into the register.
98 if (WAIT_FOR_BBP(rt2x00dev
, ®
)) {
100 rt2x00_set_field32(®
, BBP_CSR_CFG_VALUE
, value
);
101 rt2x00_set_field32(®
, BBP_CSR_CFG_REGNUM
, word
);
102 rt2x00_set_field32(®
, BBP_CSR_CFG_BUSY
, 1);
103 rt2x00_set_field32(®
, BBP_CSR_CFG_READ_CONTROL
, 0);
104 rt2x00_set_field32(®
, BBP_CSR_CFG_BBP_RW_MODE
, 1);
106 rt2800_register_write_lock(rt2x00dev
, BBP_CSR_CFG
, reg
);
109 mutex_unlock(&rt2x00dev
->csr_mutex
);
112 static void rt2800_bbp_read(struct rt2x00_dev
*rt2x00dev
,
113 const unsigned int word
, u8
*value
)
117 mutex_lock(&rt2x00dev
->csr_mutex
);
120 * Wait until the BBP becomes available, afterwards we
121 * can safely write the read request into the register.
122 * After the data has been written, we wait until hardware
123 * returns the correct value, if at any time the register
124 * doesn't become available in time, reg will be 0xffffffff
125 * which means we return 0xff to the caller.
127 if (WAIT_FOR_BBP(rt2x00dev
, ®
)) {
129 rt2x00_set_field32(®
, BBP_CSR_CFG_REGNUM
, word
);
130 rt2x00_set_field32(®
, BBP_CSR_CFG_BUSY
, 1);
131 rt2x00_set_field32(®
, BBP_CSR_CFG_READ_CONTROL
, 1);
132 rt2x00_set_field32(®
, BBP_CSR_CFG_BBP_RW_MODE
, 1);
134 rt2800_register_write_lock(rt2x00dev
, BBP_CSR_CFG
, reg
);
136 WAIT_FOR_BBP(rt2x00dev
, ®
);
139 *value
= rt2x00_get_field32(reg
, BBP_CSR_CFG_VALUE
);
141 mutex_unlock(&rt2x00dev
->csr_mutex
);
144 static void rt2800_rfcsr_write(struct rt2x00_dev
*rt2x00dev
,
145 const unsigned int word
, const u8 value
)
149 mutex_lock(&rt2x00dev
->csr_mutex
);
152 * Wait until the RFCSR becomes available, afterwards we
153 * can safely write the new data into the register.
155 if (WAIT_FOR_RFCSR(rt2x00dev
, ®
)) {
157 rt2x00_set_field32(®
, RF_CSR_CFG_DATA
, value
);
158 rt2x00_set_field32(®
, RF_CSR_CFG_REGNUM
, word
);
159 rt2x00_set_field32(®
, RF_CSR_CFG_WRITE
, 1);
160 rt2x00_set_field32(®
, RF_CSR_CFG_BUSY
, 1);
162 rt2800_register_write_lock(rt2x00dev
, RF_CSR_CFG
, reg
);
165 mutex_unlock(&rt2x00dev
->csr_mutex
);
168 static void rt2800_rfcsr_read(struct rt2x00_dev
*rt2x00dev
,
169 const unsigned int word
, u8
*value
)
173 mutex_lock(&rt2x00dev
->csr_mutex
);
176 * Wait until the RFCSR becomes available, afterwards we
177 * can safely write the read request into the register.
178 * After the data has been written, we wait until hardware
179 * returns the correct value, if at any time the register
180 * doesn't become available in time, reg will be 0xffffffff
181 * which means we return 0xff to the caller.
183 if (WAIT_FOR_RFCSR(rt2x00dev
, ®
)) {
185 rt2x00_set_field32(®
, RF_CSR_CFG_REGNUM
, word
);
186 rt2x00_set_field32(®
, RF_CSR_CFG_WRITE
, 0);
187 rt2x00_set_field32(®
, RF_CSR_CFG_BUSY
, 1);
189 rt2800_register_write_lock(rt2x00dev
, RF_CSR_CFG
, reg
);
191 WAIT_FOR_RFCSR(rt2x00dev
, ®
);
194 *value
= rt2x00_get_field32(reg
, RF_CSR_CFG_DATA
);
196 mutex_unlock(&rt2x00dev
->csr_mutex
);
199 static void rt2800_rf_write(struct rt2x00_dev
*rt2x00dev
,
200 const unsigned int word
, const u32 value
)
204 mutex_lock(&rt2x00dev
->csr_mutex
);
207 * Wait until the RF becomes available, afterwards we
208 * can safely write the new data into the register.
210 if (WAIT_FOR_RF(rt2x00dev
, ®
)) {
212 rt2x00_set_field32(®
, RF_CSR_CFG0_REG_VALUE_BW
, value
);
213 rt2x00_set_field32(®
, RF_CSR_CFG0_STANDBYMODE
, 0);
214 rt2x00_set_field32(®
, RF_CSR_CFG0_SEL
, 0);
215 rt2x00_set_field32(®
, RF_CSR_CFG0_BUSY
, 1);
217 rt2800_register_write_lock(rt2x00dev
, RF_CSR_CFG0
, reg
);
218 rt2x00_rf_write(rt2x00dev
, word
, value
);
221 mutex_unlock(&rt2x00dev
->csr_mutex
);
224 static int rt2800_enable_wlan_rt3290(struct rt2x00_dev
*rt2x00dev
)
229 rt2800_register_read(rt2x00dev
, WLAN_FUN_CTRL
, ®
);
230 if (rt2x00_get_field32(reg
, WLAN_EN
))
233 rt2x00_set_field32(®
, WLAN_GPIO_OUT_OE_BIT_ALL
, 0xff);
234 rt2x00_set_field32(®
, FRC_WL_ANT_SET
, 1);
235 rt2x00_set_field32(®
, WLAN_CLK_EN
, 0);
236 rt2x00_set_field32(®
, WLAN_EN
, 1);
237 rt2800_register_write(rt2x00dev
, WLAN_FUN_CTRL
, reg
);
239 udelay(REGISTER_BUSY_DELAY
);
244 * Check PLL_LD & XTAL_RDY.
246 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
247 rt2800_register_read(rt2x00dev
, CMB_CTRL
, ®
);
248 if (rt2x00_get_field32(reg
, PLL_LD
) &&
249 rt2x00_get_field32(reg
, XTAL_RDY
))
251 udelay(REGISTER_BUSY_DELAY
);
254 if (i
>= REGISTER_BUSY_COUNT
) {
259 rt2800_register_write(rt2x00dev
, 0x58, 0x018);
260 udelay(REGISTER_BUSY_DELAY
);
261 rt2800_register_write(rt2x00dev
, 0x58, 0x418);
262 udelay(REGISTER_BUSY_DELAY
);
263 rt2800_register_write(rt2x00dev
, 0x58, 0x618);
264 udelay(REGISTER_BUSY_DELAY
);
270 rt2800_register_read(rt2x00dev
, WLAN_FUN_CTRL
, ®
);
271 rt2x00_set_field32(®
, PCIE_APP0_CLK_REQ
, 0);
272 rt2x00_set_field32(®
, WLAN_CLK_EN
, 1);
273 rt2x00_set_field32(®
, WLAN_RESET
, 1);
274 rt2800_register_write(rt2x00dev
, WLAN_FUN_CTRL
, reg
);
276 rt2x00_set_field32(®
, WLAN_RESET
, 0);
277 rt2800_register_write(rt2x00dev
, WLAN_FUN_CTRL
, reg
);
279 rt2800_register_write(rt2x00dev
, INT_SOURCE_CSR
, 0x7fffffff);
280 } while (count
!= 0);
285 void rt2800_mcu_request(struct rt2x00_dev
*rt2x00dev
,
286 const u8 command
, const u8 token
,
287 const u8 arg0
, const u8 arg1
)
292 * SOC devices don't support MCU requests.
294 if (rt2x00_is_soc(rt2x00dev
))
297 mutex_lock(&rt2x00dev
->csr_mutex
);
300 * Wait until the MCU becomes available, afterwards we
301 * can safely write the new data into the register.
303 if (WAIT_FOR_MCU(rt2x00dev
, ®
)) {
304 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_OWNER
, 1);
305 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_CMD_TOKEN
, token
);
306 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_ARG0
, arg0
);
307 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_ARG1
, arg1
);
308 rt2800_register_write_lock(rt2x00dev
, H2M_MAILBOX_CSR
, reg
);
311 rt2x00_set_field32(®
, HOST_CMD_CSR_HOST_COMMAND
, command
);
312 rt2800_register_write_lock(rt2x00dev
, HOST_CMD_CSR
, reg
);
315 mutex_unlock(&rt2x00dev
->csr_mutex
);
317 EXPORT_SYMBOL_GPL(rt2800_mcu_request
);
319 int rt2800_wait_csr_ready(struct rt2x00_dev
*rt2x00dev
)
324 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
325 rt2800_register_read(rt2x00dev
, MAC_CSR0
, ®
);
326 if (reg
&& reg
!= ~0)
331 rt2x00_err(rt2x00dev
, "Unstable hardware\n");
334 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready
);
336 int rt2800_wait_wpdma_ready(struct rt2x00_dev
*rt2x00dev
)
342 * Some devices are really slow to respond here. Wait a whole second
345 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
346 rt2800_register_read(rt2x00dev
, WPDMA_GLO_CFG
, ®
);
347 if (!rt2x00_get_field32(reg
, WPDMA_GLO_CFG_TX_DMA_BUSY
) &&
348 !rt2x00_get_field32(reg
, WPDMA_GLO_CFG_RX_DMA_BUSY
))
354 rt2x00_err(rt2x00dev
, "WPDMA TX/RX busy [0x%08x]\n", reg
);
357 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready
);
359 void rt2800_disable_wpdma(struct rt2x00_dev
*rt2x00dev
)
363 rt2800_register_read(rt2x00dev
, WPDMA_GLO_CFG
, ®
);
364 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_TX_DMA
, 0);
365 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_DMA_BUSY
, 0);
366 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_RX_DMA
, 0);
367 rt2x00_set_field32(®
, WPDMA_GLO_CFG_RX_DMA_BUSY
, 0);
368 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_WRITEBACK_DONE
, 1);
369 rt2800_register_write(rt2x00dev
, WPDMA_GLO_CFG
, reg
);
371 EXPORT_SYMBOL_GPL(rt2800_disable_wpdma
);
373 static bool rt2800_check_firmware_crc(const u8
*data
, const size_t len
)
379 * The last 2 bytes in the firmware array are the crc checksum itself,
380 * this means that we should never pass those 2 bytes to the crc
383 fw_crc
= (data
[len
- 2] << 8 | data
[len
- 1]);
386 * Use the crc ccitt algorithm.
387 * This will return the same value as the legacy driver which
388 * used bit ordering reversion on the both the firmware bytes
389 * before input input as well as on the final output.
390 * Obviously using crc ccitt directly is much more efficient.
392 crc
= crc_ccitt(~0, data
, len
- 2);
395 * There is a small difference between the crc-itu-t + bitrev and
396 * the crc-ccitt crc calculation. In the latter method the 2 bytes
397 * will be swapped, use swab16 to convert the crc to the correct
402 return fw_crc
== crc
;
405 int rt2800_check_firmware(struct rt2x00_dev
*rt2x00dev
,
406 const u8
*data
, const size_t len
)
413 * PCI(e) & SOC devices require firmware with a length
414 * of 8kb. USB devices require firmware files with a length
415 * of 4kb. Certain USB chipsets however require different firmware,
416 * which Ralink only provides attached to the original firmware
417 * file. Thus for USB devices, firmware files have a length
418 * which is a multiple of 4kb. The firmware for rt3290 chip also
419 * have a length which is a multiple of 4kb.
421 if (rt2x00_is_usb(rt2x00dev
) || rt2x00_rt(rt2x00dev
, RT3290
))
428 * Validate the firmware length
430 if (len
!= fw_len
&& (!multiple
|| (len
% fw_len
) != 0))
431 return FW_BAD_LENGTH
;
434 * Check if the chipset requires one of the upper parts
437 if (rt2x00_is_usb(rt2x00dev
) &&
438 !rt2x00_rt(rt2x00dev
, RT2860
) &&
439 !rt2x00_rt(rt2x00dev
, RT2872
) &&
440 !rt2x00_rt(rt2x00dev
, RT3070
) &&
441 ((len
/ fw_len
) == 1))
442 return FW_BAD_VERSION
;
445 * 8kb firmware files must be checked as if it were
446 * 2 separate firmware files.
448 while (offset
< len
) {
449 if (!rt2800_check_firmware_crc(data
+ offset
, fw_len
))
457 EXPORT_SYMBOL_GPL(rt2800_check_firmware
);
459 int rt2800_load_firmware(struct rt2x00_dev
*rt2x00dev
,
460 const u8
*data
, const size_t len
)
466 if (rt2x00_rt(rt2x00dev
, RT3290
)) {
467 retval
= rt2800_enable_wlan_rt3290(rt2x00dev
);
473 * If driver doesn't wake up firmware here,
474 * rt2800_load_firmware will hang forever when interface is up again.
476 rt2800_register_write(rt2x00dev
, AUTOWAKEUP_CFG
, 0x00000000);
479 * Wait for stable hardware.
481 if (rt2800_wait_csr_ready(rt2x00dev
))
484 if (rt2x00_is_pci(rt2x00dev
)) {
485 if (rt2x00_rt(rt2x00dev
, RT3290
) ||
486 rt2x00_rt(rt2x00dev
, RT3572
) ||
487 rt2x00_rt(rt2x00dev
, RT5390
) ||
488 rt2x00_rt(rt2x00dev
, RT5392
)) {
489 rt2800_register_read(rt2x00dev
, AUX_CTRL
, ®
);
490 rt2x00_set_field32(®
, AUX_CTRL_FORCE_PCIE_CLK
, 1);
491 rt2x00_set_field32(®
, AUX_CTRL_WAKE_PCIE_EN
, 1);
492 rt2800_register_write(rt2x00dev
, AUX_CTRL
, reg
);
494 rt2800_register_write(rt2x00dev
, PWR_PIN_CFG
, 0x00000002);
497 rt2800_disable_wpdma(rt2x00dev
);
500 * Write firmware to the device.
502 rt2800_drv_write_firmware(rt2x00dev
, data
, len
);
505 * Wait for device to stabilize.
507 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
508 rt2800_register_read(rt2x00dev
, PBF_SYS_CTRL
, ®
);
509 if (rt2x00_get_field32(reg
, PBF_SYS_CTRL_READY
))
514 if (i
== REGISTER_BUSY_COUNT
) {
515 rt2x00_err(rt2x00dev
, "PBF system register not ready\n");
520 * Disable DMA, will be reenabled later when enabling
523 rt2800_disable_wpdma(rt2x00dev
);
526 * Initialize firmware.
528 rt2800_register_write(rt2x00dev
, H2M_BBP_AGENT
, 0);
529 rt2800_register_write(rt2x00dev
, H2M_MAILBOX_CSR
, 0);
530 if (rt2x00_is_usb(rt2x00dev
)) {
531 rt2800_register_write(rt2x00dev
, H2M_INT_SRC
, 0);
532 rt2800_mcu_request(rt2x00dev
, MCU_BOOT_SIGNAL
, 0, 0, 0);
538 EXPORT_SYMBOL_GPL(rt2800_load_firmware
);
540 void rt2800_write_tx_data(struct queue_entry
*entry
,
541 struct txentry_desc
*txdesc
)
543 __le32
*txwi
= rt2800_drv_get_txwi(entry
);
548 * Initialize TX Info descriptor
550 rt2x00_desc_read(txwi
, 0, &word
);
551 rt2x00_set_field32(&word
, TXWI_W0_FRAG
,
552 test_bit(ENTRY_TXD_MORE_FRAG
, &txdesc
->flags
));
553 rt2x00_set_field32(&word
, TXWI_W0_MIMO_PS
,
554 test_bit(ENTRY_TXD_HT_MIMO_PS
, &txdesc
->flags
));
555 rt2x00_set_field32(&word
, TXWI_W0_CF_ACK
, 0);
556 rt2x00_set_field32(&word
, TXWI_W0_TS
,
557 test_bit(ENTRY_TXD_REQ_TIMESTAMP
, &txdesc
->flags
));
558 rt2x00_set_field32(&word
, TXWI_W0_AMPDU
,
559 test_bit(ENTRY_TXD_HT_AMPDU
, &txdesc
->flags
));
560 rt2x00_set_field32(&word
, TXWI_W0_MPDU_DENSITY
,
561 txdesc
->u
.ht
.mpdu_density
);
562 rt2x00_set_field32(&word
, TXWI_W0_TX_OP
, txdesc
->u
.ht
.txop
);
563 rt2x00_set_field32(&word
, TXWI_W0_MCS
, txdesc
->u
.ht
.mcs
);
564 rt2x00_set_field32(&word
, TXWI_W0_BW
,
565 test_bit(ENTRY_TXD_HT_BW_40
, &txdesc
->flags
));
566 rt2x00_set_field32(&word
, TXWI_W0_SHORT_GI
,
567 test_bit(ENTRY_TXD_HT_SHORT_GI
, &txdesc
->flags
));
568 rt2x00_set_field32(&word
, TXWI_W0_STBC
, txdesc
->u
.ht
.stbc
);
569 rt2x00_set_field32(&word
, TXWI_W0_PHYMODE
, txdesc
->rate_mode
);
570 rt2x00_desc_write(txwi
, 0, word
);
572 rt2x00_desc_read(txwi
, 1, &word
);
573 rt2x00_set_field32(&word
, TXWI_W1_ACK
,
574 test_bit(ENTRY_TXD_ACK
, &txdesc
->flags
));
575 rt2x00_set_field32(&word
, TXWI_W1_NSEQ
,
576 test_bit(ENTRY_TXD_GENERATE_SEQ
, &txdesc
->flags
));
577 rt2x00_set_field32(&word
, TXWI_W1_BW_WIN_SIZE
, txdesc
->u
.ht
.ba_size
);
578 rt2x00_set_field32(&word
, TXWI_W1_WIRELESS_CLI_ID
,
579 test_bit(ENTRY_TXD_ENCRYPT
, &txdesc
->flags
) ?
580 txdesc
->key_idx
: txdesc
->u
.ht
.wcid
);
581 rt2x00_set_field32(&word
, TXWI_W1_MPDU_TOTAL_BYTE_COUNT
,
583 rt2x00_set_field32(&word
, TXWI_W1_PACKETID_QUEUE
, entry
->queue
->qid
);
584 rt2x00_set_field32(&word
, TXWI_W1_PACKETID_ENTRY
, (entry
->entry_idx
% 3) + 1);
585 rt2x00_desc_write(txwi
, 1, word
);
588 * Always write 0 to IV/EIV fields (word 2 and 3), hardware will insert
589 * the IV from the IVEIV register when TXD_W3_WIV is set to 0.
590 * When TXD_W3_WIV is set to 1 it will use the IV data
591 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
592 * crypto entry in the registers should be used to encrypt the frame.
594 * Nulify all remaining words as well, we don't know how to program them.
596 for (i
= 2; i
< entry
->queue
->winfo_size
/ sizeof(__le32
); i
++)
597 _rt2x00_desc_write(txwi
, i
, 0);
599 EXPORT_SYMBOL_GPL(rt2800_write_tx_data
);
601 static int rt2800_agc_to_rssi(struct rt2x00_dev
*rt2x00dev
, u32 rxwi_w2
)
603 s8 rssi0
= rt2x00_get_field32(rxwi_w2
, RXWI_W2_RSSI0
);
604 s8 rssi1
= rt2x00_get_field32(rxwi_w2
, RXWI_W2_RSSI1
);
605 s8 rssi2
= rt2x00_get_field32(rxwi_w2
, RXWI_W2_RSSI2
);
611 if (rt2x00dev
->curr_band
== IEEE80211_BAND_2GHZ
) {
612 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_BG
, &eeprom
);
613 offset0
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_BG_OFFSET0
);
614 offset1
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_BG_OFFSET1
);
615 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_BG2
, &eeprom
);
616 offset2
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_BG2_OFFSET2
);
618 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_A
, &eeprom
);
619 offset0
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_A_OFFSET0
);
620 offset1
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_A_OFFSET1
);
621 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_A2
, &eeprom
);
622 offset2
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_A2_OFFSET2
);
626 * Convert the value from the descriptor into the RSSI value
627 * If the value in the descriptor is 0, it is considered invalid
628 * and the default (extremely low) rssi value is assumed
630 rssi0
= (rssi0
) ? (-12 - offset0
- rt2x00dev
->lna_gain
- rssi0
) : -128;
631 rssi1
= (rssi1
) ? (-12 - offset1
- rt2x00dev
->lna_gain
- rssi1
) : -128;
632 rssi2
= (rssi2
) ? (-12 - offset2
- rt2x00dev
->lna_gain
- rssi2
) : -128;
635 * mac80211 only accepts a single RSSI value. Calculating the
636 * average doesn't deliver a fair answer either since -60:-60 would
637 * be considered equally good as -50:-70 while the second is the one
638 * which gives less energy...
640 rssi0
= max(rssi0
, rssi1
);
641 return (int)max(rssi0
, rssi2
);
644 void rt2800_process_rxwi(struct queue_entry
*entry
,
645 struct rxdone_entry_desc
*rxdesc
)
647 __le32
*rxwi
= (__le32
*) entry
->skb
->data
;
650 rt2x00_desc_read(rxwi
, 0, &word
);
652 rxdesc
->cipher
= rt2x00_get_field32(word
, RXWI_W0_UDF
);
653 rxdesc
->size
= rt2x00_get_field32(word
, RXWI_W0_MPDU_TOTAL_BYTE_COUNT
);
655 rt2x00_desc_read(rxwi
, 1, &word
);
657 if (rt2x00_get_field32(word
, RXWI_W1_SHORT_GI
))
658 rxdesc
->flags
|= RX_FLAG_SHORT_GI
;
660 if (rt2x00_get_field32(word
, RXWI_W1_BW
))
661 rxdesc
->flags
|= RX_FLAG_40MHZ
;
664 * Detect RX rate, always use MCS as signal type.
666 rxdesc
->dev_flags
|= RXDONE_SIGNAL_MCS
;
667 rxdesc
->signal
= rt2x00_get_field32(word
, RXWI_W1_MCS
);
668 rxdesc
->rate_mode
= rt2x00_get_field32(word
, RXWI_W1_PHYMODE
);
671 * Mask of 0x8 bit to remove the short preamble flag.
673 if (rxdesc
->rate_mode
== RATE_MODE_CCK
)
674 rxdesc
->signal
&= ~0x8;
676 rt2x00_desc_read(rxwi
, 2, &word
);
679 * Convert descriptor AGC value to RSSI value.
681 rxdesc
->rssi
= rt2800_agc_to_rssi(entry
->queue
->rt2x00dev
, word
);
683 * Remove RXWI descriptor from start of the buffer.
685 skb_pull(entry
->skb
, entry
->queue
->winfo_size
);
687 EXPORT_SYMBOL_GPL(rt2800_process_rxwi
);
689 void rt2800_txdone_entry(struct queue_entry
*entry
, u32 status
, __le32
*txwi
)
691 struct rt2x00_dev
*rt2x00dev
= entry
->queue
->rt2x00dev
;
692 struct skb_frame_desc
*skbdesc
= get_skb_frame_desc(entry
->skb
);
693 struct txdone_entry_desc txdesc
;
699 * Obtain the status about this packet.
702 rt2x00_desc_read(txwi
, 0, &word
);
704 mcs
= rt2x00_get_field32(word
, TXWI_W0_MCS
);
705 ampdu
= rt2x00_get_field32(word
, TXWI_W0_AMPDU
);
707 real_mcs
= rt2x00_get_field32(status
, TX_STA_FIFO_MCS
);
708 aggr
= rt2x00_get_field32(status
, TX_STA_FIFO_TX_AGGRE
);
711 * If a frame was meant to be sent as a single non-aggregated MPDU
712 * but ended up in an aggregate the used tx rate doesn't correlate
713 * with the one specified in the TXWI as the whole aggregate is sent
714 * with the same rate.
716 * For example: two frames are sent to rt2x00, the first one sets
717 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
718 * and requests MCS15. If the hw aggregates both frames into one
719 * AMDPU the tx status for both frames will contain MCS7 although
720 * the frame was sent successfully.
722 * Hence, replace the requested rate with the real tx rate to not
723 * confuse the rate control algortihm by providing clearly wrong
726 if (unlikely(aggr
== 1 && ampdu
== 0 && real_mcs
!= mcs
)) {
727 skbdesc
->tx_rate_idx
= real_mcs
;
731 if (aggr
== 1 || ampdu
== 1)
732 __set_bit(TXDONE_AMPDU
, &txdesc
.flags
);
735 * Ralink has a retry mechanism using a global fallback
736 * table. We setup this fallback table to try the immediate
737 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
738 * always contains the MCS used for the last transmission, be
739 * it successful or not.
741 if (rt2x00_get_field32(status
, TX_STA_FIFO_TX_SUCCESS
)) {
743 * Transmission succeeded. The number of retries is
746 __set_bit(TXDONE_SUCCESS
, &txdesc
.flags
);
747 txdesc
.retry
= ((mcs
> real_mcs
) ? mcs
- real_mcs
: 0);
750 * Transmission failed. The number of retries is
751 * always 7 in this case (for a total number of 8
754 __set_bit(TXDONE_FAILURE
, &txdesc
.flags
);
755 txdesc
.retry
= rt2x00dev
->long_retry
;
759 * the frame was retried at least once
760 * -> hw used fallback rates
763 __set_bit(TXDONE_FALLBACK
, &txdesc
.flags
);
765 rt2x00lib_txdone(entry
, &txdesc
);
767 EXPORT_SYMBOL_GPL(rt2800_txdone_entry
);
769 void rt2800_write_beacon(struct queue_entry
*entry
, struct txentry_desc
*txdesc
)
771 struct rt2x00_dev
*rt2x00dev
= entry
->queue
->rt2x00dev
;
772 struct skb_frame_desc
*skbdesc
= get_skb_frame_desc(entry
->skb
);
773 unsigned int beacon_base
;
774 unsigned int padding_len
;
776 const int txwi_desc_size
= entry
->queue
->winfo_size
;
779 * Disable beaconing while we are reloading the beacon data,
780 * otherwise we might be sending out invalid data.
782 rt2800_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
784 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_GEN
, 0);
785 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
788 * Add space for the TXWI in front of the skb.
790 memset(skb_push(entry
->skb
, txwi_desc_size
), 0, txwi_desc_size
);
793 * Register descriptor details in skb frame descriptor.
795 skbdesc
->flags
|= SKBDESC_DESC_IN_SKB
;
796 skbdesc
->desc
= entry
->skb
->data
;
797 skbdesc
->desc_len
= txwi_desc_size
;
800 * Add the TXWI for the beacon to the skb.
802 rt2800_write_tx_data(entry
, txdesc
);
805 * Dump beacon to userspace through debugfs.
807 rt2x00debug_dump_frame(rt2x00dev
, DUMP_FRAME_BEACON
, entry
->skb
);
810 * Write entire beacon with TXWI and padding to register.
812 padding_len
= roundup(entry
->skb
->len
, 4) - entry
->skb
->len
;
813 if (padding_len
&& skb_pad(entry
->skb
, padding_len
)) {
814 rt2x00_err(rt2x00dev
, "Failure padding beacon, aborting\n");
815 /* skb freed by skb_pad() on failure */
817 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, orig_reg
);
821 beacon_base
= HW_BEACON_OFFSET(entry
->entry_idx
);
822 rt2800_register_multiwrite(rt2x00dev
, beacon_base
, entry
->skb
->data
,
823 entry
->skb
->len
+ padding_len
);
826 * Enable beaconing again.
828 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_GEN
, 1);
829 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
832 * Clean up beacon skb.
834 dev_kfree_skb_any(entry
->skb
);
837 EXPORT_SYMBOL_GPL(rt2800_write_beacon
);
839 static inline void rt2800_clear_beacon_register(struct rt2x00_dev
*rt2x00dev
,
840 unsigned int beacon_base
)
843 const int txwi_desc_size
= rt2x00dev
->ops
->bcn
->winfo_size
;
846 * For the Beacon base registers we only need to clear
847 * the whole TXWI which (when set to 0) will invalidate
850 for (i
= 0; i
< txwi_desc_size
; i
+= sizeof(__le32
))
851 rt2800_register_write(rt2x00dev
, beacon_base
+ i
, 0);
854 void rt2800_clear_beacon(struct queue_entry
*entry
)
856 struct rt2x00_dev
*rt2x00dev
= entry
->queue
->rt2x00dev
;
860 * Disable beaconing while we are reloading the beacon data,
861 * otherwise we might be sending out invalid data.
863 rt2800_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
864 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_GEN
, 0);
865 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
870 rt2800_clear_beacon_register(rt2x00dev
,
871 HW_BEACON_OFFSET(entry
->entry_idx
));
874 * Enabled beaconing again.
876 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_GEN
, 1);
877 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
879 EXPORT_SYMBOL_GPL(rt2800_clear_beacon
);
881 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
882 const struct rt2x00debug rt2800_rt2x00debug
= {
883 .owner
= THIS_MODULE
,
885 .read
= rt2800_register_read
,
886 .write
= rt2800_register_write
,
887 .flags
= RT2X00DEBUGFS_OFFSET
,
888 .word_base
= CSR_REG_BASE
,
889 .word_size
= sizeof(u32
),
890 .word_count
= CSR_REG_SIZE
/ sizeof(u32
),
893 .read
= rt2x00_eeprom_read
,
894 .write
= rt2x00_eeprom_write
,
895 .word_base
= EEPROM_BASE
,
896 .word_size
= sizeof(u16
),
897 .word_count
= EEPROM_SIZE
/ sizeof(u16
),
900 .read
= rt2800_bbp_read
,
901 .write
= rt2800_bbp_write
,
902 .word_base
= BBP_BASE
,
903 .word_size
= sizeof(u8
),
904 .word_count
= BBP_SIZE
/ sizeof(u8
),
907 .read
= rt2x00_rf_read
,
908 .write
= rt2800_rf_write
,
909 .word_base
= RF_BASE
,
910 .word_size
= sizeof(u32
),
911 .word_count
= RF_SIZE
/ sizeof(u32
),
914 .read
= rt2800_rfcsr_read
,
915 .write
= rt2800_rfcsr_write
,
916 .word_base
= RFCSR_BASE
,
917 .word_size
= sizeof(u8
),
918 .word_count
= RFCSR_SIZE
/ sizeof(u8
),
921 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug
);
922 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
924 int rt2800_rfkill_poll(struct rt2x00_dev
*rt2x00dev
)
928 if (rt2x00_rt(rt2x00dev
, RT3290
)) {
929 rt2800_register_read(rt2x00dev
, WLAN_FUN_CTRL
, ®
);
930 return rt2x00_get_field32(reg
, WLAN_GPIO_IN_BIT0
);
932 rt2800_register_read(rt2x00dev
, GPIO_CTRL
, ®
);
933 return rt2x00_get_field32(reg
, GPIO_CTRL_VAL2
);
936 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll
);
938 #ifdef CONFIG_RT2X00_LIB_LEDS
939 static void rt2800_brightness_set(struct led_classdev
*led_cdev
,
940 enum led_brightness brightness
)
942 struct rt2x00_led
*led
=
943 container_of(led_cdev
, struct rt2x00_led
, led_dev
);
944 unsigned int enabled
= brightness
!= LED_OFF
;
945 unsigned int bg_mode
=
946 (enabled
&& led
->rt2x00dev
->curr_band
== IEEE80211_BAND_2GHZ
);
947 unsigned int polarity
=
948 rt2x00_get_field16(led
->rt2x00dev
->led_mcu_reg
,
949 EEPROM_FREQ_LED_POLARITY
);
950 unsigned int ledmode
=
951 rt2x00_get_field16(led
->rt2x00dev
->led_mcu_reg
,
952 EEPROM_FREQ_LED_MODE
);
955 /* Check for SoC (SOC devices don't support MCU requests) */
956 if (rt2x00_is_soc(led
->rt2x00dev
)) {
957 rt2800_register_read(led
->rt2x00dev
, LED_CFG
, ®
);
959 /* Set LED Polarity */
960 rt2x00_set_field32(®
, LED_CFG_LED_POLAR
, polarity
);
963 if (led
->type
== LED_TYPE_RADIO
) {
964 rt2x00_set_field32(®
, LED_CFG_G_LED_MODE
,
966 } else if (led
->type
== LED_TYPE_ASSOC
) {
967 rt2x00_set_field32(®
, LED_CFG_Y_LED_MODE
,
969 } else if (led
->type
== LED_TYPE_QUALITY
) {
970 rt2x00_set_field32(®
, LED_CFG_R_LED_MODE
,
974 rt2800_register_write(led
->rt2x00dev
, LED_CFG
, reg
);
977 if (led
->type
== LED_TYPE_RADIO
) {
978 rt2800_mcu_request(led
->rt2x00dev
, MCU_LED
, 0xff, ledmode
,
980 } else if (led
->type
== LED_TYPE_ASSOC
) {
981 rt2800_mcu_request(led
->rt2x00dev
, MCU_LED
, 0xff, ledmode
,
982 enabled
? (bg_mode
? 0x60 : 0xa0) : 0x20);
983 } else if (led
->type
== LED_TYPE_QUALITY
) {
985 * The brightness is divided into 6 levels (0 - 5),
986 * The specs tell us the following levels:
988 * to determine the level in a simple way we can simply
989 * work with bitshifting:
992 rt2800_mcu_request(led
->rt2x00dev
, MCU_LED_STRENGTH
, 0xff,
993 (1 << brightness
/ (LED_FULL
/ 6)) - 1,
999 static void rt2800_init_led(struct rt2x00_dev
*rt2x00dev
,
1000 struct rt2x00_led
*led
, enum led_type type
)
1002 led
->rt2x00dev
= rt2x00dev
;
1004 led
->led_dev
.brightness_set
= rt2800_brightness_set
;
1005 led
->flags
= LED_INITIALIZED
;
1007 #endif /* CONFIG_RT2X00_LIB_LEDS */
1010 * Configuration handlers.
1012 static void rt2800_config_wcid(struct rt2x00_dev
*rt2x00dev
,
1016 struct mac_wcid_entry wcid_entry
;
1019 offset
= MAC_WCID_ENTRY(wcid
);
1021 memset(&wcid_entry
, 0xff, sizeof(wcid_entry
));
1023 memcpy(wcid_entry
.mac
, address
, ETH_ALEN
);
1025 rt2800_register_multiwrite(rt2x00dev
, offset
,
1026 &wcid_entry
, sizeof(wcid_entry
));
1029 static void rt2800_delete_wcid_attr(struct rt2x00_dev
*rt2x00dev
, int wcid
)
1032 offset
= MAC_WCID_ATTR_ENTRY(wcid
);
1033 rt2800_register_write(rt2x00dev
, offset
, 0);
1036 static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev
*rt2x00dev
,
1037 int wcid
, u32 bssidx
)
1039 u32 offset
= MAC_WCID_ATTR_ENTRY(wcid
);
1043 * The BSS Idx numbers is split in a main value of 3 bits,
1044 * and a extended field for adding one additional bit to the value.
1046 rt2800_register_read(rt2x00dev
, offset
, ®
);
1047 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_BSS_IDX
, (bssidx
& 0x7));
1048 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT
,
1049 (bssidx
& 0x8) >> 3);
1050 rt2800_register_write(rt2x00dev
, offset
, reg
);
1053 static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev
*rt2x00dev
,
1054 struct rt2x00lib_crypto
*crypto
,
1055 struct ieee80211_key_conf
*key
)
1057 struct mac_iveiv_entry iveiv_entry
;
1061 offset
= MAC_WCID_ATTR_ENTRY(key
->hw_key_idx
);
1063 if (crypto
->cmd
== SET_KEY
) {
1064 rt2800_register_read(rt2x00dev
, offset
, ®
);
1065 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_KEYTAB
,
1066 !!(key
->flags
& IEEE80211_KEY_FLAG_PAIRWISE
));
1068 * Both the cipher as the BSS Idx numbers are split in a main
1069 * value of 3 bits, and a extended field for adding one additional
1072 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_CIPHER
,
1073 (crypto
->cipher
& 0x7));
1074 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_CIPHER_EXT
,
1075 (crypto
->cipher
& 0x8) >> 3);
1076 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_RX_WIUDF
, crypto
->cipher
);
1077 rt2800_register_write(rt2x00dev
, offset
, reg
);
1079 /* Delete the cipher without touching the bssidx */
1080 rt2800_register_read(rt2x00dev
, offset
, ®
);
1081 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_KEYTAB
, 0);
1082 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_CIPHER
, 0);
1083 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_CIPHER_EXT
, 0);
1084 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_RX_WIUDF
, 0);
1085 rt2800_register_write(rt2x00dev
, offset
, reg
);
1088 offset
= MAC_IVEIV_ENTRY(key
->hw_key_idx
);
1090 memset(&iveiv_entry
, 0, sizeof(iveiv_entry
));
1091 if ((crypto
->cipher
== CIPHER_TKIP
) ||
1092 (crypto
->cipher
== CIPHER_TKIP_NO_MIC
) ||
1093 (crypto
->cipher
== CIPHER_AES
))
1094 iveiv_entry
.iv
[3] |= 0x20;
1095 iveiv_entry
.iv
[3] |= key
->keyidx
<< 6;
1096 rt2800_register_multiwrite(rt2x00dev
, offset
,
1097 &iveiv_entry
, sizeof(iveiv_entry
));
1100 int rt2800_config_shared_key(struct rt2x00_dev
*rt2x00dev
,
1101 struct rt2x00lib_crypto
*crypto
,
1102 struct ieee80211_key_conf
*key
)
1104 struct hw_key_entry key_entry
;
1105 struct rt2x00_field32 field
;
1109 if (crypto
->cmd
== SET_KEY
) {
1110 key
->hw_key_idx
= (4 * crypto
->bssidx
) + key
->keyidx
;
1112 memcpy(key_entry
.key
, crypto
->key
,
1113 sizeof(key_entry
.key
));
1114 memcpy(key_entry
.tx_mic
, crypto
->tx_mic
,
1115 sizeof(key_entry
.tx_mic
));
1116 memcpy(key_entry
.rx_mic
, crypto
->rx_mic
,
1117 sizeof(key_entry
.rx_mic
));
1119 offset
= SHARED_KEY_ENTRY(key
->hw_key_idx
);
1120 rt2800_register_multiwrite(rt2x00dev
, offset
,
1121 &key_entry
, sizeof(key_entry
));
1125 * The cipher types are stored over multiple registers
1126 * starting with SHARED_KEY_MODE_BASE each word will have
1127 * 32 bits and contains the cipher types for 2 bssidx each.
1128 * Using the correct defines correctly will cause overhead,
1129 * so just calculate the correct offset.
1131 field
.bit_offset
= 4 * (key
->hw_key_idx
% 8);
1132 field
.bit_mask
= 0x7 << field
.bit_offset
;
1134 offset
= SHARED_KEY_MODE_ENTRY(key
->hw_key_idx
/ 8);
1136 rt2800_register_read(rt2x00dev
, offset
, ®
);
1137 rt2x00_set_field32(®
, field
,
1138 (crypto
->cmd
== SET_KEY
) * crypto
->cipher
);
1139 rt2800_register_write(rt2x00dev
, offset
, reg
);
1142 * Update WCID information
1144 rt2800_config_wcid(rt2x00dev
, crypto
->address
, key
->hw_key_idx
);
1145 rt2800_config_wcid_attr_bssidx(rt2x00dev
, key
->hw_key_idx
,
1147 rt2800_config_wcid_attr_cipher(rt2x00dev
, crypto
, key
);
1151 EXPORT_SYMBOL_GPL(rt2800_config_shared_key
);
1153 static inline int rt2800_find_wcid(struct rt2x00_dev
*rt2x00dev
)
1155 struct mac_wcid_entry wcid_entry
;
1160 * Search for the first free WCID entry and return the corresponding
1163 * Make sure the WCID starts _after_ the last possible shared key
1166 * Since parts of the pairwise key table might be shared with
1167 * the beacon frame buffers 6 & 7 we should only write into the
1168 * first 222 entries.
1170 for (idx
= 33; idx
<= 222; idx
++) {
1171 offset
= MAC_WCID_ENTRY(idx
);
1172 rt2800_register_multiread(rt2x00dev
, offset
, &wcid_entry
,
1173 sizeof(wcid_entry
));
1174 if (is_broadcast_ether_addr(wcid_entry
.mac
))
1179 * Use -1 to indicate that we don't have any more space in the WCID
1185 int rt2800_config_pairwise_key(struct rt2x00_dev
*rt2x00dev
,
1186 struct rt2x00lib_crypto
*crypto
,
1187 struct ieee80211_key_conf
*key
)
1189 struct hw_key_entry key_entry
;
1192 if (crypto
->cmd
== SET_KEY
) {
1194 * Allow key configuration only for STAs that are
1197 if (crypto
->wcid
< 0)
1199 key
->hw_key_idx
= crypto
->wcid
;
1201 memcpy(key_entry
.key
, crypto
->key
,
1202 sizeof(key_entry
.key
));
1203 memcpy(key_entry
.tx_mic
, crypto
->tx_mic
,
1204 sizeof(key_entry
.tx_mic
));
1205 memcpy(key_entry
.rx_mic
, crypto
->rx_mic
,
1206 sizeof(key_entry
.rx_mic
));
1208 offset
= PAIRWISE_KEY_ENTRY(key
->hw_key_idx
);
1209 rt2800_register_multiwrite(rt2x00dev
, offset
,
1210 &key_entry
, sizeof(key_entry
));
1214 * Update WCID information
1216 rt2800_config_wcid_attr_cipher(rt2x00dev
, crypto
, key
);
1220 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key
);
1222 int rt2800_sta_add(struct rt2x00_dev
*rt2x00dev
, struct ieee80211_vif
*vif
,
1223 struct ieee80211_sta
*sta
)
1226 struct rt2x00_sta
*sta_priv
= sta_to_rt2x00_sta(sta
);
1229 * Find next free WCID.
1231 wcid
= rt2800_find_wcid(rt2x00dev
);
1234 * Store selected wcid even if it is invalid so that we can
1235 * later decide if the STA is uploaded into the hw.
1237 sta_priv
->wcid
= wcid
;
1240 * No space left in the device, however, we can still communicate
1241 * with the STA -> No error.
1247 * Clean up WCID attributes and write STA address to the device.
1249 rt2800_delete_wcid_attr(rt2x00dev
, wcid
);
1250 rt2800_config_wcid(rt2x00dev
, sta
->addr
, wcid
);
1251 rt2800_config_wcid_attr_bssidx(rt2x00dev
, wcid
,
1252 rt2x00lib_get_bssidx(rt2x00dev
, vif
));
1255 EXPORT_SYMBOL_GPL(rt2800_sta_add
);
1257 int rt2800_sta_remove(struct rt2x00_dev
*rt2x00dev
, int wcid
)
1260 * Remove WCID entry, no need to clean the attributes as they will
1261 * get renewed when the WCID is reused.
1263 rt2800_config_wcid(rt2x00dev
, NULL
, wcid
);
1267 EXPORT_SYMBOL_GPL(rt2800_sta_remove
);
1269 void rt2800_config_filter(struct rt2x00_dev
*rt2x00dev
,
1270 const unsigned int filter_flags
)
1275 * Start configuration steps.
1276 * Note that the version error will always be dropped
1277 * and broadcast frames will always be accepted since
1278 * there is no filter for it at this time.
1280 rt2800_register_read(rt2x00dev
, RX_FILTER_CFG
, ®
);
1281 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CRC_ERROR
,
1282 !(filter_flags
& FIF_FCSFAIL
));
1283 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_PHY_ERROR
,
1284 !(filter_flags
& FIF_PLCPFAIL
));
1285 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_NOT_TO_ME
,
1286 !(filter_flags
& FIF_PROMISC_IN_BSS
));
1287 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_NOT_MY_BSSD
, 0);
1288 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_VER_ERROR
, 1);
1289 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_MULTICAST
,
1290 !(filter_flags
& FIF_ALLMULTI
));
1291 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_BROADCAST
, 0);
1292 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_DUPLICATE
, 1);
1293 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CF_END_ACK
,
1294 !(filter_flags
& FIF_CONTROL
));
1295 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CF_END
,
1296 !(filter_flags
& FIF_CONTROL
));
1297 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_ACK
,
1298 !(filter_flags
& FIF_CONTROL
));
1299 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CTS
,
1300 !(filter_flags
& FIF_CONTROL
));
1301 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_RTS
,
1302 !(filter_flags
& FIF_CONTROL
));
1303 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_PSPOLL
,
1304 !(filter_flags
& FIF_PSPOLL
));
1305 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_BA
, 0);
1306 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_BAR
,
1307 !(filter_flags
& FIF_CONTROL
));
1308 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CNTL
,
1309 !(filter_flags
& FIF_CONTROL
));
1310 rt2800_register_write(rt2x00dev
, RX_FILTER_CFG
, reg
);
1312 EXPORT_SYMBOL_GPL(rt2800_config_filter
);
1314 void rt2800_config_intf(struct rt2x00_dev
*rt2x00dev
, struct rt2x00_intf
*intf
,
1315 struct rt2x00intf_conf
*conf
, const unsigned int flags
)
1318 bool update_bssid
= false;
1320 if (flags
& CONFIG_UPDATE_TYPE
) {
1322 * Enable synchronisation.
1324 rt2800_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
1325 rt2x00_set_field32(®
, BCN_TIME_CFG_TSF_SYNC
, conf
->sync
);
1326 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
1328 if (conf
->sync
== TSF_SYNC_AP_NONE
) {
1330 * Tune beacon queue transmit parameters for AP mode
1332 rt2800_register_read(rt2x00dev
, TBTT_SYNC_CFG
, ®
);
1333 rt2x00_set_field32(®
, TBTT_SYNC_CFG_BCN_CWMIN
, 0);
1334 rt2x00_set_field32(®
, TBTT_SYNC_CFG_BCN_AIFSN
, 1);
1335 rt2x00_set_field32(®
, TBTT_SYNC_CFG_BCN_EXP_WIN
, 32);
1336 rt2x00_set_field32(®
, TBTT_SYNC_CFG_TBTT_ADJUST
, 0);
1337 rt2800_register_write(rt2x00dev
, TBTT_SYNC_CFG
, reg
);
1339 rt2800_register_read(rt2x00dev
, TBTT_SYNC_CFG
, ®
);
1340 rt2x00_set_field32(®
, TBTT_SYNC_CFG_BCN_CWMIN
, 4);
1341 rt2x00_set_field32(®
, TBTT_SYNC_CFG_BCN_AIFSN
, 2);
1342 rt2x00_set_field32(®
, TBTT_SYNC_CFG_BCN_EXP_WIN
, 32);
1343 rt2x00_set_field32(®
, TBTT_SYNC_CFG_TBTT_ADJUST
, 16);
1344 rt2800_register_write(rt2x00dev
, TBTT_SYNC_CFG
, reg
);
1348 if (flags
& CONFIG_UPDATE_MAC
) {
1349 if (flags
& CONFIG_UPDATE_TYPE
&&
1350 conf
->sync
== TSF_SYNC_AP_NONE
) {
1352 * The BSSID register has to be set to our own mac
1353 * address in AP mode.
1355 memcpy(conf
->bssid
, conf
->mac
, sizeof(conf
->mac
));
1356 update_bssid
= true;
1359 if (!is_zero_ether_addr((const u8
*)conf
->mac
)) {
1360 reg
= le32_to_cpu(conf
->mac
[1]);
1361 rt2x00_set_field32(®
, MAC_ADDR_DW1_UNICAST_TO_ME_MASK
, 0xff);
1362 conf
->mac
[1] = cpu_to_le32(reg
);
1365 rt2800_register_multiwrite(rt2x00dev
, MAC_ADDR_DW0
,
1366 conf
->mac
, sizeof(conf
->mac
));
1369 if ((flags
& CONFIG_UPDATE_BSSID
) || update_bssid
) {
1370 if (!is_zero_ether_addr((const u8
*)conf
->bssid
)) {
1371 reg
= le32_to_cpu(conf
->bssid
[1]);
1372 rt2x00_set_field32(®
, MAC_BSSID_DW1_BSS_ID_MASK
, 3);
1373 rt2x00_set_field32(®
, MAC_BSSID_DW1_BSS_BCN_NUM
, 7);
1374 conf
->bssid
[1] = cpu_to_le32(reg
);
1377 rt2800_register_multiwrite(rt2x00dev
, MAC_BSSID_DW0
,
1378 conf
->bssid
, sizeof(conf
->bssid
));
1381 EXPORT_SYMBOL_GPL(rt2800_config_intf
);
1383 static void rt2800_config_ht_opmode(struct rt2x00_dev
*rt2x00dev
,
1384 struct rt2x00lib_erp
*erp
)
1386 bool any_sta_nongf
= !!(erp
->ht_opmode
&
1387 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT
);
1388 u8 protection
= erp
->ht_opmode
& IEEE80211_HT_OP_MODE_PROTECTION
;
1389 u8 mm20_mode
, mm40_mode
, gf20_mode
, gf40_mode
;
1390 u16 mm20_rate
, mm40_rate
, gf20_rate
, gf40_rate
;
1393 /* default protection rate for HT20: OFDM 24M */
1394 mm20_rate
= gf20_rate
= 0x4004;
1396 /* default protection rate for HT40: duplicate OFDM 24M */
1397 mm40_rate
= gf40_rate
= 0x4084;
1399 switch (protection
) {
1400 case IEEE80211_HT_OP_MODE_PROTECTION_NONE
:
1402 * All STAs in this BSS are HT20/40 but there might be
1403 * STAs not supporting greenfield mode.
1404 * => Disable protection for HT transmissions.
1406 mm20_mode
= mm40_mode
= gf20_mode
= gf40_mode
= 0;
1409 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ
:
1411 * All STAs in this BSS are HT20 or HT20/40 but there
1412 * might be STAs not supporting greenfield mode.
1413 * => Protect all HT40 transmissions.
1415 mm20_mode
= gf20_mode
= 0;
1416 mm40_mode
= gf40_mode
= 2;
1419 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER
:
1421 * Nonmember protection:
1422 * According to 802.11n we _should_ protect all
1423 * HT transmissions (but we don't have to).
1425 * But if cts_protection is enabled we _shall_ protect
1426 * all HT transmissions using a CCK rate.
1428 * And if any station is non GF we _shall_ protect
1431 * We decide to protect everything
1432 * -> fall through to mixed mode.
1434 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED
:
1436 * Legacy STAs are present
1437 * => Protect all HT transmissions.
1439 mm20_mode
= mm40_mode
= gf20_mode
= gf40_mode
= 2;
1442 * If erp protection is needed we have to protect HT
1443 * transmissions with CCK 11M long preamble.
1445 if (erp
->cts_protection
) {
1446 /* don't duplicate RTS/CTS in CCK mode */
1447 mm20_rate
= mm40_rate
= 0x0003;
1448 gf20_rate
= gf40_rate
= 0x0003;
1453 /* check for STAs not supporting greenfield mode */
1455 gf20_mode
= gf40_mode
= 2;
1457 /* Update HT protection config */
1458 rt2800_register_read(rt2x00dev
, MM20_PROT_CFG
, ®
);
1459 rt2x00_set_field32(®
, MM20_PROT_CFG_PROTECT_RATE
, mm20_rate
);
1460 rt2x00_set_field32(®
, MM20_PROT_CFG_PROTECT_CTRL
, mm20_mode
);
1461 rt2800_register_write(rt2x00dev
, MM20_PROT_CFG
, reg
);
1463 rt2800_register_read(rt2x00dev
, MM40_PROT_CFG
, ®
);
1464 rt2x00_set_field32(®
, MM40_PROT_CFG_PROTECT_RATE
, mm40_rate
);
1465 rt2x00_set_field32(®
, MM40_PROT_CFG_PROTECT_CTRL
, mm40_mode
);
1466 rt2800_register_write(rt2x00dev
, MM40_PROT_CFG
, reg
);
1468 rt2800_register_read(rt2x00dev
, GF20_PROT_CFG
, ®
);
1469 rt2x00_set_field32(®
, GF20_PROT_CFG_PROTECT_RATE
, gf20_rate
);
1470 rt2x00_set_field32(®
, GF20_PROT_CFG_PROTECT_CTRL
, gf20_mode
);
1471 rt2800_register_write(rt2x00dev
, GF20_PROT_CFG
, reg
);
1473 rt2800_register_read(rt2x00dev
, GF40_PROT_CFG
, ®
);
1474 rt2x00_set_field32(®
, GF40_PROT_CFG_PROTECT_RATE
, gf40_rate
);
1475 rt2x00_set_field32(®
, GF40_PROT_CFG_PROTECT_CTRL
, gf40_mode
);
1476 rt2800_register_write(rt2x00dev
, GF40_PROT_CFG
, reg
);
1479 void rt2800_config_erp(struct rt2x00_dev
*rt2x00dev
, struct rt2x00lib_erp
*erp
,
1484 if (changed
& BSS_CHANGED_ERP_PREAMBLE
) {
1485 rt2800_register_read(rt2x00dev
, AUTO_RSP_CFG
, ®
);
1486 rt2x00_set_field32(®
, AUTO_RSP_CFG_BAC_ACK_POLICY
,
1487 !!erp
->short_preamble
);
1488 rt2x00_set_field32(®
, AUTO_RSP_CFG_AR_PREAMBLE
,
1489 !!erp
->short_preamble
);
1490 rt2800_register_write(rt2x00dev
, AUTO_RSP_CFG
, reg
);
1493 if (changed
& BSS_CHANGED_ERP_CTS_PROT
) {
1494 rt2800_register_read(rt2x00dev
, OFDM_PROT_CFG
, ®
);
1495 rt2x00_set_field32(®
, OFDM_PROT_CFG_PROTECT_CTRL
,
1496 erp
->cts_protection
? 2 : 0);
1497 rt2800_register_write(rt2x00dev
, OFDM_PROT_CFG
, reg
);
1500 if (changed
& BSS_CHANGED_BASIC_RATES
) {
1501 rt2800_register_write(rt2x00dev
, LEGACY_BASIC_RATE
,
1503 rt2800_register_write(rt2x00dev
, HT_BASIC_RATE
, 0x00008003);
1506 if (changed
& BSS_CHANGED_ERP_SLOT
) {
1507 rt2800_register_read(rt2x00dev
, BKOFF_SLOT_CFG
, ®
);
1508 rt2x00_set_field32(®
, BKOFF_SLOT_CFG_SLOT_TIME
,
1510 rt2800_register_write(rt2x00dev
, BKOFF_SLOT_CFG
, reg
);
1512 rt2800_register_read(rt2x00dev
, XIFS_TIME_CFG
, ®
);
1513 rt2x00_set_field32(®
, XIFS_TIME_CFG_EIFS
, erp
->eifs
);
1514 rt2800_register_write(rt2x00dev
, XIFS_TIME_CFG
, reg
);
1517 if (changed
& BSS_CHANGED_BEACON_INT
) {
1518 rt2800_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
1519 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_INTERVAL
,
1520 erp
->beacon_int
* 16);
1521 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
1524 if (changed
& BSS_CHANGED_HT
)
1525 rt2800_config_ht_opmode(rt2x00dev
, erp
);
1527 EXPORT_SYMBOL_GPL(rt2800_config_erp
);
1529 static void rt2800_config_3572bt_ant(struct rt2x00_dev
*rt2x00dev
)
1533 u8 led_ctrl
, led_g_mode
, led_r_mode
;
1535 rt2800_register_read(rt2x00dev
, GPIO_SWITCH
, ®
);
1536 if (rt2x00dev
->curr_band
== IEEE80211_BAND_5GHZ
) {
1537 rt2x00_set_field32(®
, GPIO_SWITCH_0
, 1);
1538 rt2x00_set_field32(®
, GPIO_SWITCH_1
, 1);
1540 rt2x00_set_field32(®
, GPIO_SWITCH_0
, 0);
1541 rt2x00_set_field32(®
, GPIO_SWITCH_1
, 0);
1543 rt2800_register_write(rt2x00dev
, GPIO_SWITCH
, reg
);
1545 rt2800_register_read(rt2x00dev
, LED_CFG
, ®
);
1546 led_g_mode
= rt2x00_get_field32(reg
, LED_CFG_LED_POLAR
) ? 3 : 0;
1547 led_r_mode
= rt2x00_get_field32(reg
, LED_CFG_LED_POLAR
) ? 0 : 3;
1548 if (led_g_mode
!= rt2x00_get_field32(reg
, LED_CFG_G_LED_MODE
) ||
1549 led_r_mode
!= rt2x00_get_field32(reg
, LED_CFG_R_LED_MODE
)) {
1550 rt2x00_eeprom_read(rt2x00dev
, EEPROM_FREQ
, &eeprom
);
1551 led_ctrl
= rt2x00_get_field16(eeprom
, EEPROM_FREQ_LED_MODE
);
1552 if (led_ctrl
== 0 || led_ctrl
> 0x40) {
1553 rt2x00_set_field32(®
, LED_CFG_G_LED_MODE
, led_g_mode
);
1554 rt2x00_set_field32(®
, LED_CFG_R_LED_MODE
, led_r_mode
);
1555 rt2800_register_write(rt2x00dev
, LED_CFG
, reg
);
1557 rt2800_mcu_request(rt2x00dev
, MCU_BAND_SELECT
, 0xff,
1558 (led_g_mode
<< 2) | led_r_mode
, 1);
1563 static void rt2800_set_ant_diversity(struct rt2x00_dev
*rt2x00dev
,
1567 u8 eesk_pin
= (ant
== ANTENNA_A
) ? 1 : 0;
1568 u8 gpio_bit3
= (ant
== ANTENNA_A
) ? 0 : 1;
1570 if (rt2x00_is_pci(rt2x00dev
)) {
1571 rt2800_register_read(rt2x00dev
, E2PROM_CSR
, ®
);
1572 rt2x00_set_field32(®
, E2PROM_CSR_DATA_CLOCK
, eesk_pin
);
1573 rt2800_register_write(rt2x00dev
, E2PROM_CSR
, reg
);
1574 } else if (rt2x00_is_usb(rt2x00dev
))
1575 rt2800_mcu_request(rt2x00dev
, MCU_ANT_SELECT
, 0xff,
1578 rt2800_register_read(rt2x00dev
, GPIO_CTRL
, ®
);
1579 rt2x00_set_field32(®
, GPIO_CTRL_DIR3
, 0);
1580 rt2x00_set_field32(®
, GPIO_CTRL_VAL3
, gpio_bit3
);
1581 rt2800_register_write(rt2x00dev
, GPIO_CTRL
, reg
);
1584 void rt2800_config_ant(struct rt2x00_dev
*rt2x00dev
, struct antenna_setup
*ant
)
1590 rt2800_bbp_read(rt2x00dev
, 1, &r1
);
1591 rt2800_bbp_read(rt2x00dev
, 3, &r3
);
1593 if (rt2x00_rt(rt2x00dev
, RT3572
) &&
1594 test_bit(CAPABILITY_BT_COEXIST
, &rt2x00dev
->cap_flags
))
1595 rt2800_config_3572bt_ant(rt2x00dev
);
1598 * Configure the TX antenna.
1600 switch (ant
->tx_chain_num
) {
1602 rt2x00_set_field8(&r1
, BBP1_TX_ANTENNA
, 0);
1605 if (rt2x00_rt(rt2x00dev
, RT3572
) &&
1606 test_bit(CAPABILITY_BT_COEXIST
, &rt2x00dev
->cap_flags
))
1607 rt2x00_set_field8(&r1
, BBP1_TX_ANTENNA
, 1);
1609 rt2x00_set_field8(&r1
, BBP1_TX_ANTENNA
, 2);
1612 rt2x00_set_field8(&r1
, BBP1_TX_ANTENNA
, 0);
1617 * Configure the RX antenna.
1619 switch (ant
->rx_chain_num
) {
1621 if (rt2x00_rt(rt2x00dev
, RT3070
) ||
1622 rt2x00_rt(rt2x00dev
, RT3090
) ||
1623 rt2x00_rt(rt2x00dev
, RT3352
) ||
1624 rt2x00_rt(rt2x00dev
, RT3390
)) {
1625 rt2x00_eeprom_read(rt2x00dev
,
1626 EEPROM_NIC_CONF1
, &eeprom
);
1627 if (rt2x00_get_field16(eeprom
,
1628 EEPROM_NIC_CONF1_ANT_DIVERSITY
))
1629 rt2800_set_ant_diversity(rt2x00dev
,
1630 rt2x00dev
->default_ant
.rx
);
1632 rt2x00_set_field8(&r3
, BBP3_RX_ANTENNA
, 0);
1635 if (rt2x00_rt(rt2x00dev
, RT3572
) &&
1636 test_bit(CAPABILITY_BT_COEXIST
, &rt2x00dev
->cap_flags
)) {
1637 rt2x00_set_field8(&r3
, BBP3_RX_ADC
, 1);
1638 rt2x00_set_field8(&r3
, BBP3_RX_ANTENNA
,
1639 rt2x00dev
->curr_band
== IEEE80211_BAND_5GHZ
);
1640 rt2800_set_ant_diversity(rt2x00dev
, ANTENNA_B
);
1642 rt2x00_set_field8(&r3
, BBP3_RX_ANTENNA
, 1);
1646 rt2x00_set_field8(&r3
, BBP3_RX_ANTENNA
, 2);
1650 rt2800_bbp_write(rt2x00dev
, 3, r3
);
1651 rt2800_bbp_write(rt2x00dev
, 1, r1
);
1653 EXPORT_SYMBOL_GPL(rt2800_config_ant
);
1655 static void rt2800_config_lna_gain(struct rt2x00_dev
*rt2x00dev
,
1656 struct rt2x00lib_conf
*libconf
)
1661 if (libconf
->rf
.channel
<= 14) {
1662 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LNA
, &eeprom
);
1663 lna_gain
= rt2x00_get_field16(eeprom
, EEPROM_LNA_BG
);
1664 } else if (libconf
->rf
.channel
<= 64) {
1665 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LNA
, &eeprom
);
1666 lna_gain
= rt2x00_get_field16(eeprom
, EEPROM_LNA_A0
);
1667 } else if (libconf
->rf
.channel
<= 128) {
1668 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_BG2
, &eeprom
);
1669 lna_gain
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_BG2_LNA_A1
);
1671 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_A2
, &eeprom
);
1672 lna_gain
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_A2_LNA_A2
);
1675 rt2x00dev
->lna_gain
= lna_gain
;
1678 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev
*rt2x00dev
,
1679 struct ieee80211_conf
*conf
,
1680 struct rf_channel
*rf
,
1681 struct channel_info
*info
)
1683 rt2x00_set_field32(&rf
->rf4
, RF4_FREQ_OFFSET
, rt2x00dev
->freq_offset
);
1685 if (rt2x00dev
->default_ant
.tx_chain_num
== 1)
1686 rt2x00_set_field32(&rf
->rf2
, RF2_ANTENNA_TX1
, 1);
1688 if (rt2x00dev
->default_ant
.rx_chain_num
== 1) {
1689 rt2x00_set_field32(&rf
->rf2
, RF2_ANTENNA_RX1
, 1);
1690 rt2x00_set_field32(&rf
->rf2
, RF2_ANTENNA_RX2
, 1);
1691 } else if (rt2x00dev
->default_ant
.rx_chain_num
== 2)
1692 rt2x00_set_field32(&rf
->rf2
, RF2_ANTENNA_RX2
, 1);
1694 if (rf
->channel
> 14) {
1696 * When TX power is below 0, we should increase it by 7 to
1697 * make it a positive value (Minimum value is -7).
1698 * However this means that values between 0 and 7 have
1699 * double meaning, and we should set a 7DBm boost flag.
1701 rt2x00_set_field32(&rf
->rf3
, RF3_TXPOWER_A_7DBM_BOOST
,
1702 (info
->default_power1
>= 0));
1704 if (info
->default_power1
< 0)
1705 info
->default_power1
+= 7;
1707 rt2x00_set_field32(&rf
->rf3
, RF3_TXPOWER_A
, info
->default_power1
);
1709 rt2x00_set_field32(&rf
->rf4
, RF4_TXPOWER_A_7DBM_BOOST
,
1710 (info
->default_power2
>= 0));
1712 if (info
->default_power2
< 0)
1713 info
->default_power2
+= 7;
1715 rt2x00_set_field32(&rf
->rf4
, RF4_TXPOWER_A
, info
->default_power2
);
1717 rt2x00_set_field32(&rf
->rf3
, RF3_TXPOWER_G
, info
->default_power1
);
1718 rt2x00_set_field32(&rf
->rf4
, RF4_TXPOWER_G
, info
->default_power2
);
1721 rt2x00_set_field32(&rf
->rf4
, RF4_HT40
, conf_is_ht40(conf
));
1723 rt2800_rf_write(rt2x00dev
, 1, rf
->rf1
);
1724 rt2800_rf_write(rt2x00dev
, 2, rf
->rf2
);
1725 rt2800_rf_write(rt2x00dev
, 3, rf
->rf3
& ~0x00000004);
1726 rt2800_rf_write(rt2x00dev
, 4, rf
->rf4
);
1730 rt2800_rf_write(rt2x00dev
, 1, rf
->rf1
);
1731 rt2800_rf_write(rt2x00dev
, 2, rf
->rf2
);
1732 rt2800_rf_write(rt2x00dev
, 3, rf
->rf3
| 0x00000004);
1733 rt2800_rf_write(rt2x00dev
, 4, rf
->rf4
);
1737 rt2800_rf_write(rt2x00dev
, 1, rf
->rf1
);
1738 rt2800_rf_write(rt2x00dev
, 2, rf
->rf2
);
1739 rt2800_rf_write(rt2x00dev
, 3, rf
->rf3
& ~0x00000004);
1740 rt2800_rf_write(rt2x00dev
, 4, rf
->rf4
);
1743 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev
*rt2x00dev
,
1744 struct ieee80211_conf
*conf
,
1745 struct rf_channel
*rf
,
1746 struct channel_info
*info
)
1748 struct rt2800_drv_data
*drv_data
= rt2x00dev
->drv_data
;
1749 u8 rfcsr
, calib_tx
, calib_rx
;
1751 rt2800_rfcsr_write(rt2x00dev
, 2, rf
->rf1
);
1753 rt2800_rfcsr_read(rt2x00dev
, 3, &rfcsr
);
1754 rt2x00_set_field8(&rfcsr
, RFCSR3_K
, rf
->rf3
);
1755 rt2800_rfcsr_write(rt2x00dev
, 3, rfcsr
);
1757 rt2800_rfcsr_read(rt2x00dev
, 6, &rfcsr
);
1758 rt2x00_set_field8(&rfcsr
, RFCSR6_R1
, rf
->rf2
);
1759 rt2800_rfcsr_write(rt2x00dev
, 6, rfcsr
);
1761 rt2800_rfcsr_read(rt2x00dev
, 12, &rfcsr
);
1762 rt2x00_set_field8(&rfcsr
, RFCSR12_TX_POWER
, info
->default_power1
);
1763 rt2800_rfcsr_write(rt2x00dev
, 12, rfcsr
);
1765 rt2800_rfcsr_read(rt2x00dev
, 13, &rfcsr
);
1766 rt2x00_set_field8(&rfcsr
, RFCSR13_TX_POWER
, info
->default_power2
);
1767 rt2800_rfcsr_write(rt2x00dev
, 13, rfcsr
);
1769 rt2800_rfcsr_read(rt2x00dev
, 1, &rfcsr
);
1770 rt2x00_set_field8(&rfcsr
, RFCSR1_RX0_PD
, 0);
1771 rt2x00_set_field8(&rfcsr
, RFCSR1_RX1_PD
,
1772 rt2x00dev
->default_ant
.rx_chain_num
<= 1);
1773 rt2x00_set_field8(&rfcsr
, RFCSR1_RX2_PD
,
1774 rt2x00dev
->default_ant
.rx_chain_num
<= 2);
1775 rt2x00_set_field8(&rfcsr
, RFCSR1_TX0_PD
, 0);
1776 rt2x00_set_field8(&rfcsr
, RFCSR1_TX1_PD
,
1777 rt2x00dev
->default_ant
.tx_chain_num
<= 1);
1778 rt2x00_set_field8(&rfcsr
, RFCSR1_TX2_PD
,
1779 rt2x00dev
->default_ant
.tx_chain_num
<= 2);
1780 rt2800_rfcsr_write(rt2x00dev
, 1, rfcsr
);
1782 rt2800_rfcsr_read(rt2x00dev
, 30, &rfcsr
);
1783 rt2x00_set_field8(&rfcsr
, RFCSR30_RF_CALIBRATION
, 1);
1784 rt2800_rfcsr_write(rt2x00dev
, 30, rfcsr
);
1786 rt2x00_set_field8(&rfcsr
, RFCSR30_RF_CALIBRATION
, 0);
1787 rt2800_rfcsr_write(rt2x00dev
, 30, rfcsr
);
1789 rt2800_rfcsr_read(rt2x00dev
, 23, &rfcsr
);
1790 rt2x00_set_field8(&rfcsr
, RFCSR23_FREQ_OFFSET
, rt2x00dev
->freq_offset
);
1791 rt2800_rfcsr_write(rt2x00dev
, 23, rfcsr
);
1793 if (rt2x00_rt(rt2x00dev
, RT3390
)) {
1794 calib_tx
= conf_is_ht40(conf
) ? 0x68 : 0x4f;
1795 calib_rx
= conf_is_ht40(conf
) ? 0x6f : 0x4f;
1797 if (conf_is_ht40(conf
)) {
1798 calib_tx
= drv_data
->calibration_bw40
;
1799 calib_rx
= drv_data
->calibration_bw40
;
1801 calib_tx
= drv_data
->calibration_bw20
;
1802 calib_rx
= drv_data
->calibration_bw20
;
1806 rt2800_rfcsr_read(rt2x00dev
, 24, &rfcsr
);
1807 rt2x00_set_field8(&rfcsr
, RFCSR24_TX_CALIB
, calib_tx
);
1808 rt2800_rfcsr_write(rt2x00dev
, 24, rfcsr
);
1810 rt2800_rfcsr_read(rt2x00dev
, 31, &rfcsr
);
1811 rt2x00_set_field8(&rfcsr
, RFCSR31_RX_CALIB
, calib_rx
);
1812 rt2800_rfcsr_write(rt2x00dev
, 31, rfcsr
);
1814 rt2800_rfcsr_read(rt2x00dev
, 7, &rfcsr
);
1815 rt2x00_set_field8(&rfcsr
, RFCSR7_RF_TUNING
, 1);
1816 rt2800_rfcsr_write(rt2x00dev
, 7, rfcsr
);
1818 rt2800_rfcsr_read(rt2x00dev
, 30, &rfcsr
);
1819 rt2x00_set_field8(&rfcsr
, RFCSR30_RF_CALIBRATION
, 1);
1820 rt2800_rfcsr_write(rt2x00dev
, 30, rfcsr
);
1822 rt2x00_set_field8(&rfcsr
, RFCSR30_RF_CALIBRATION
, 0);
1823 rt2800_rfcsr_write(rt2x00dev
, 30, rfcsr
);
1826 static void rt2800_config_channel_rf3052(struct rt2x00_dev
*rt2x00dev
,
1827 struct ieee80211_conf
*conf
,
1828 struct rf_channel
*rf
,
1829 struct channel_info
*info
)
1831 struct rt2800_drv_data
*drv_data
= rt2x00dev
->drv_data
;
1835 if (rf
->channel
<= 14) {
1836 rt2800_bbp_write(rt2x00dev
, 25, drv_data
->bbp25
);
1837 rt2800_bbp_write(rt2x00dev
, 26, drv_data
->bbp26
);
1839 rt2800_bbp_write(rt2x00dev
, 25, 0x09);
1840 rt2800_bbp_write(rt2x00dev
, 26, 0xff);
1843 rt2800_rfcsr_write(rt2x00dev
, 2, rf
->rf1
);
1844 rt2800_rfcsr_write(rt2x00dev
, 3, rf
->rf3
);
1846 rt2800_rfcsr_read(rt2x00dev
, 6, &rfcsr
);
1847 rt2x00_set_field8(&rfcsr
, RFCSR6_R1
, rf
->rf2
);
1848 if (rf
->channel
<= 14)
1849 rt2x00_set_field8(&rfcsr
, RFCSR6_TXDIV
, 2);
1851 rt2x00_set_field8(&rfcsr
, RFCSR6_TXDIV
, 1);
1852 rt2800_rfcsr_write(rt2x00dev
, 6, rfcsr
);
1854 rt2800_rfcsr_read(rt2x00dev
, 5, &rfcsr
);
1855 if (rf
->channel
<= 14)
1856 rt2x00_set_field8(&rfcsr
, RFCSR5_R1
, 1);
1858 rt2x00_set_field8(&rfcsr
, RFCSR5_R1
, 2);
1859 rt2800_rfcsr_write(rt2x00dev
, 5, rfcsr
);
1861 rt2800_rfcsr_read(rt2x00dev
, 12, &rfcsr
);
1862 if (rf
->channel
<= 14) {
1863 rt2x00_set_field8(&rfcsr
, RFCSR12_DR0
, 3);
1864 rt2x00_set_field8(&rfcsr
, RFCSR12_TX_POWER
,
1865 info
->default_power1
);
1867 rt2x00_set_field8(&rfcsr
, RFCSR12_DR0
, 7);
1868 rt2x00_set_field8(&rfcsr
, RFCSR12_TX_POWER
,
1869 (info
->default_power1
& 0x3) |
1870 ((info
->default_power1
& 0xC) << 1));
1872 rt2800_rfcsr_write(rt2x00dev
, 12, rfcsr
);
1874 rt2800_rfcsr_read(rt2x00dev
, 13, &rfcsr
);
1875 if (rf
->channel
<= 14) {
1876 rt2x00_set_field8(&rfcsr
, RFCSR13_DR0
, 3);
1877 rt2x00_set_field8(&rfcsr
, RFCSR13_TX_POWER
,
1878 info
->default_power2
);
1880 rt2x00_set_field8(&rfcsr
, RFCSR13_DR0
, 7);
1881 rt2x00_set_field8(&rfcsr
, RFCSR13_TX_POWER
,
1882 (info
->default_power2
& 0x3) |
1883 ((info
->default_power2
& 0xC) << 1));
1885 rt2800_rfcsr_write(rt2x00dev
, 13, rfcsr
);
1887 rt2800_rfcsr_read(rt2x00dev
, 1, &rfcsr
);
1888 rt2x00_set_field8(&rfcsr
, RFCSR1_RX0_PD
, 0);
1889 rt2x00_set_field8(&rfcsr
, RFCSR1_TX0_PD
, 0);
1890 rt2x00_set_field8(&rfcsr
, RFCSR1_RX1_PD
, 0);
1891 rt2x00_set_field8(&rfcsr
, RFCSR1_TX1_PD
, 0);
1892 rt2x00_set_field8(&rfcsr
, RFCSR1_RX2_PD
, 0);
1893 rt2x00_set_field8(&rfcsr
, RFCSR1_TX2_PD
, 0);
1894 if (test_bit(CAPABILITY_BT_COEXIST
, &rt2x00dev
->cap_flags
)) {
1895 if (rf
->channel
<= 14) {
1896 rt2x00_set_field8(&rfcsr
, RFCSR1_RX0_PD
, 1);
1897 rt2x00_set_field8(&rfcsr
, RFCSR1_TX0_PD
, 1);
1899 rt2x00_set_field8(&rfcsr
, RFCSR1_RX2_PD
, 1);
1900 rt2x00_set_field8(&rfcsr
, RFCSR1_TX2_PD
, 1);
1902 switch (rt2x00dev
->default_ant
.tx_chain_num
) {
1904 rt2x00_set_field8(&rfcsr
, RFCSR1_TX1_PD
, 1);
1906 rt2x00_set_field8(&rfcsr
, RFCSR1_TX2_PD
, 1);
1910 switch (rt2x00dev
->default_ant
.rx_chain_num
) {
1912 rt2x00_set_field8(&rfcsr
, RFCSR1_RX1_PD
, 1);
1914 rt2x00_set_field8(&rfcsr
, RFCSR1_RX2_PD
, 1);
1918 rt2800_rfcsr_write(rt2x00dev
, 1, rfcsr
);
1920 rt2800_rfcsr_read(rt2x00dev
, 23, &rfcsr
);
1921 rt2x00_set_field8(&rfcsr
, RFCSR23_FREQ_OFFSET
, rt2x00dev
->freq_offset
);
1922 rt2800_rfcsr_write(rt2x00dev
, 23, rfcsr
);
1924 if (conf_is_ht40(conf
)) {
1925 rt2800_rfcsr_write(rt2x00dev
, 24, drv_data
->calibration_bw40
);
1926 rt2800_rfcsr_write(rt2x00dev
, 31, drv_data
->calibration_bw40
);
1928 rt2800_rfcsr_write(rt2x00dev
, 24, drv_data
->calibration_bw20
);
1929 rt2800_rfcsr_write(rt2x00dev
, 31, drv_data
->calibration_bw20
);
1932 if (rf
->channel
<= 14) {
1933 rt2800_rfcsr_write(rt2x00dev
, 7, 0xd8);
1934 rt2800_rfcsr_write(rt2x00dev
, 9, 0xc3);
1935 rt2800_rfcsr_write(rt2x00dev
, 10, 0xf1);
1936 rt2800_rfcsr_write(rt2x00dev
, 11, 0xb9);
1937 rt2800_rfcsr_write(rt2x00dev
, 15, 0x53);
1939 rt2x00_set_field8(&rfcsr
, RFCSR16_TXMIXER_GAIN
,
1940 drv_data
->txmixer_gain_24g
);
1941 rt2800_rfcsr_write(rt2x00dev
, 16, rfcsr
);
1942 rt2800_rfcsr_write(rt2x00dev
, 17, 0x23);
1943 rt2800_rfcsr_write(rt2x00dev
, 19, 0x93);
1944 rt2800_rfcsr_write(rt2x00dev
, 20, 0xb3);
1945 rt2800_rfcsr_write(rt2x00dev
, 25, 0x15);
1946 rt2800_rfcsr_write(rt2x00dev
, 26, 0x85);
1947 rt2800_rfcsr_write(rt2x00dev
, 27, 0x00);
1948 rt2800_rfcsr_write(rt2x00dev
, 29, 0x9b);
1950 rt2800_rfcsr_read(rt2x00dev
, 7, &rfcsr
);
1951 rt2x00_set_field8(&rfcsr
, RFCSR7_BIT2
, 1);
1952 rt2x00_set_field8(&rfcsr
, RFCSR7_BIT3
, 0);
1953 rt2x00_set_field8(&rfcsr
, RFCSR7_BIT4
, 1);
1954 rt2x00_set_field8(&rfcsr
, RFCSR7_BITS67
, 0);
1955 rt2800_rfcsr_write(rt2x00dev
, 7, rfcsr
);
1956 rt2800_rfcsr_write(rt2x00dev
, 9, 0xc0);
1957 rt2800_rfcsr_write(rt2x00dev
, 10, 0xf1);
1958 rt2800_rfcsr_write(rt2x00dev
, 11, 0x00);
1959 rt2800_rfcsr_write(rt2x00dev
, 15, 0x43);
1961 rt2x00_set_field8(&rfcsr
, RFCSR16_TXMIXER_GAIN
,
1962 drv_data
->txmixer_gain_5g
);
1963 rt2800_rfcsr_write(rt2x00dev
, 16, rfcsr
);
1964 rt2800_rfcsr_write(rt2x00dev
, 17, 0x23);
1965 if (rf
->channel
<= 64) {
1966 rt2800_rfcsr_write(rt2x00dev
, 19, 0xb7);
1967 rt2800_rfcsr_write(rt2x00dev
, 20, 0xf6);
1968 rt2800_rfcsr_write(rt2x00dev
, 25, 0x3d);
1969 } else if (rf
->channel
<= 128) {
1970 rt2800_rfcsr_write(rt2x00dev
, 19, 0x74);
1971 rt2800_rfcsr_write(rt2x00dev
, 20, 0xf4);
1972 rt2800_rfcsr_write(rt2x00dev
, 25, 0x01);
1974 rt2800_rfcsr_write(rt2x00dev
, 19, 0x72);
1975 rt2800_rfcsr_write(rt2x00dev
, 20, 0xf3);
1976 rt2800_rfcsr_write(rt2x00dev
, 25, 0x01);
1978 rt2800_rfcsr_write(rt2x00dev
, 26, 0x87);
1979 rt2800_rfcsr_write(rt2x00dev
, 27, 0x01);
1980 rt2800_rfcsr_write(rt2x00dev
, 29, 0x9f);
1983 rt2800_register_read(rt2x00dev
, GPIO_CTRL
, ®
);
1984 rt2x00_set_field32(®
, GPIO_CTRL_DIR7
, 0);
1985 if (rf
->channel
<= 14)
1986 rt2x00_set_field32(®
, GPIO_CTRL_VAL7
, 1);
1988 rt2x00_set_field32(®
, GPIO_CTRL_VAL7
, 0);
1989 rt2800_register_write(rt2x00dev
, GPIO_CTRL
, reg
);
1991 rt2800_rfcsr_read(rt2x00dev
, 7, &rfcsr
);
1992 rt2x00_set_field8(&rfcsr
, RFCSR7_RF_TUNING
, 1);
1993 rt2800_rfcsr_write(rt2x00dev
, 7, rfcsr
);
1996 #define POWER_BOUND 0x27
1997 #define POWER_BOUND_5G 0x2b
1998 #define FREQ_OFFSET_BOUND 0x5f
2000 static void rt2800_adjust_freq_offset(struct rt2x00_dev
*rt2x00dev
)
2004 rt2800_rfcsr_read(rt2x00dev
, 17, &rfcsr
);
2005 if (rt2x00dev
->freq_offset
> FREQ_OFFSET_BOUND
)
2006 rt2x00_set_field8(&rfcsr
, RFCSR17_CODE
, FREQ_OFFSET_BOUND
);
2008 rt2x00_set_field8(&rfcsr
, RFCSR17_CODE
, rt2x00dev
->freq_offset
);
2009 rt2800_rfcsr_write(rt2x00dev
, 17, rfcsr
);
2012 static void rt2800_config_channel_rf3290(struct rt2x00_dev
*rt2x00dev
,
2013 struct ieee80211_conf
*conf
,
2014 struct rf_channel
*rf
,
2015 struct channel_info
*info
)
2019 rt2800_rfcsr_write(rt2x00dev
, 8, rf
->rf1
);
2020 rt2800_rfcsr_write(rt2x00dev
, 9, rf
->rf3
);
2021 rt2800_rfcsr_read(rt2x00dev
, 11, &rfcsr
);
2022 rt2x00_set_field8(&rfcsr
, RFCSR11_R
, rf
->rf2
);
2023 rt2800_rfcsr_write(rt2x00dev
, 11, rfcsr
);
2025 rt2800_rfcsr_read(rt2x00dev
, 49, &rfcsr
);
2026 if (info
->default_power1
> POWER_BOUND
)
2027 rt2x00_set_field8(&rfcsr
, RFCSR49_TX
, POWER_BOUND
);
2029 rt2x00_set_field8(&rfcsr
, RFCSR49_TX
, info
->default_power1
);
2030 rt2800_rfcsr_write(rt2x00dev
, 49, rfcsr
);
2032 rt2800_adjust_freq_offset(rt2x00dev
);
2034 if (rf
->channel
<= 14) {
2035 if (rf
->channel
== 6)
2036 rt2800_bbp_write(rt2x00dev
, 68, 0x0c);
2038 rt2800_bbp_write(rt2x00dev
, 68, 0x0b);
2040 if (rf
->channel
>= 1 && rf
->channel
<= 6)
2041 rt2800_bbp_write(rt2x00dev
, 59, 0x0f);
2042 else if (rf
->channel
>= 7 && rf
->channel
<= 11)
2043 rt2800_bbp_write(rt2x00dev
, 59, 0x0e);
2044 else if (rf
->channel
>= 12 && rf
->channel
<= 14)
2045 rt2800_bbp_write(rt2x00dev
, 59, 0x0d);
2049 static void rt2800_config_channel_rf3322(struct rt2x00_dev
*rt2x00dev
,
2050 struct ieee80211_conf
*conf
,
2051 struct rf_channel
*rf
,
2052 struct channel_info
*info
)
2056 rt2800_rfcsr_write(rt2x00dev
, 8, rf
->rf1
);
2057 rt2800_rfcsr_write(rt2x00dev
, 9, rf
->rf3
);
2059 rt2800_rfcsr_write(rt2x00dev
, 11, 0x42);
2060 rt2800_rfcsr_write(rt2x00dev
, 12, 0x1c);
2061 rt2800_rfcsr_write(rt2x00dev
, 13, 0x00);
2063 if (info
->default_power1
> POWER_BOUND
)
2064 rt2800_rfcsr_write(rt2x00dev
, 47, POWER_BOUND
);
2066 rt2800_rfcsr_write(rt2x00dev
, 47, info
->default_power1
);
2068 if (info
->default_power2
> POWER_BOUND
)
2069 rt2800_rfcsr_write(rt2x00dev
, 48, POWER_BOUND
);
2071 rt2800_rfcsr_write(rt2x00dev
, 48, info
->default_power2
);
2073 rt2800_adjust_freq_offset(rt2x00dev
);
2075 rt2800_rfcsr_read(rt2x00dev
, 1, &rfcsr
);
2076 rt2x00_set_field8(&rfcsr
, RFCSR1_RX0_PD
, 1);
2077 rt2x00_set_field8(&rfcsr
, RFCSR1_TX0_PD
, 1);
2079 if ( rt2x00dev
->default_ant
.tx_chain_num
== 2 )
2080 rt2x00_set_field8(&rfcsr
, RFCSR1_TX1_PD
, 1);
2082 rt2x00_set_field8(&rfcsr
, RFCSR1_TX1_PD
, 0);
2084 if ( rt2x00dev
->default_ant
.rx_chain_num
== 2 )
2085 rt2x00_set_field8(&rfcsr
, RFCSR1_RX1_PD
, 1);
2087 rt2x00_set_field8(&rfcsr
, RFCSR1_RX1_PD
, 0);
2089 rt2x00_set_field8(&rfcsr
, RFCSR1_RX2_PD
, 0);
2090 rt2x00_set_field8(&rfcsr
, RFCSR1_TX2_PD
, 0);
2092 rt2800_rfcsr_write(rt2x00dev
, 1, rfcsr
);
2094 rt2800_rfcsr_write(rt2x00dev
, 31, 80);
2097 static void rt2800_config_channel_rf53xx(struct rt2x00_dev
*rt2x00dev
,
2098 struct ieee80211_conf
*conf
,
2099 struct rf_channel
*rf
,
2100 struct channel_info
*info
)
2104 rt2800_rfcsr_write(rt2x00dev
, 8, rf
->rf1
);
2105 rt2800_rfcsr_write(rt2x00dev
, 9, rf
->rf3
);
2106 rt2800_rfcsr_read(rt2x00dev
, 11, &rfcsr
);
2107 rt2x00_set_field8(&rfcsr
, RFCSR11_R
, rf
->rf2
);
2108 rt2800_rfcsr_write(rt2x00dev
, 11, rfcsr
);
2110 rt2800_rfcsr_read(rt2x00dev
, 49, &rfcsr
);
2111 if (info
->default_power1
> POWER_BOUND
)
2112 rt2x00_set_field8(&rfcsr
, RFCSR49_TX
, POWER_BOUND
);
2114 rt2x00_set_field8(&rfcsr
, RFCSR49_TX
, info
->default_power1
);
2115 rt2800_rfcsr_write(rt2x00dev
, 49, rfcsr
);
2117 if (rt2x00_rt(rt2x00dev
, RT5392
)) {
2118 rt2800_rfcsr_read(rt2x00dev
, 50, &rfcsr
);
2119 if (info
->default_power1
> POWER_BOUND
)
2120 rt2x00_set_field8(&rfcsr
, RFCSR50_TX
, POWER_BOUND
);
2122 rt2x00_set_field8(&rfcsr
, RFCSR50_TX
,
2123 info
->default_power2
);
2124 rt2800_rfcsr_write(rt2x00dev
, 50, rfcsr
);
2127 rt2800_rfcsr_read(rt2x00dev
, 1, &rfcsr
);
2128 if (rt2x00_rt(rt2x00dev
, RT5392
)) {
2129 rt2x00_set_field8(&rfcsr
, RFCSR1_RX1_PD
, 1);
2130 rt2x00_set_field8(&rfcsr
, RFCSR1_TX1_PD
, 1);
2132 rt2x00_set_field8(&rfcsr
, RFCSR1_RF_BLOCK_EN
, 1);
2133 rt2x00_set_field8(&rfcsr
, RFCSR1_PLL_PD
, 1);
2134 rt2x00_set_field8(&rfcsr
, RFCSR1_RX0_PD
, 1);
2135 rt2x00_set_field8(&rfcsr
, RFCSR1_TX0_PD
, 1);
2136 rt2800_rfcsr_write(rt2x00dev
, 1, rfcsr
);
2138 rt2800_adjust_freq_offset(rt2x00dev
);
2140 if (rf
->channel
<= 14) {
2141 int idx
= rf
->channel
-1;
2143 if (test_bit(CAPABILITY_BT_COEXIST
, &rt2x00dev
->cap_flags
)) {
2144 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390F
)) {
2145 /* r55/r59 value array of channel 1~14 */
2146 static const char r55_bt_rev
[] = {0x83, 0x83,
2147 0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
2148 0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
2149 static const char r59_bt_rev
[] = {0x0e, 0x0e,
2150 0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
2151 0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
2153 rt2800_rfcsr_write(rt2x00dev
, 55,
2155 rt2800_rfcsr_write(rt2x00dev
, 59,
2158 static const char r59_bt
[] = {0x8b, 0x8b, 0x8b,
2159 0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
2160 0x88, 0x88, 0x86, 0x85, 0x84};
2162 rt2800_rfcsr_write(rt2x00dev
, 59, r59_bt
[idx
]);
2165 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390F
)) {
2166 static const char r55_nonbt_rev
[] = {0x23, 0x23,
2167 0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
2168 0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
2169 static const char r59_nonbt_rev
[] = {0x07, 0x07,
2170 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
2171 0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
2173 rt2800_rfcsr_write(rt2x00dev
, 55,
2174 r55_nonbt_rev
[idx
]);
2175 rt2800_rfcsr_write(rt2x00dev
, 59,
2176 r59_nonbt_rev
[idx
]);
2177 } else if (rt2x00_rt(rt2x00dev
, RT5390
) ||
2178 rt2x00_rt(rt2x00dev
, RT5392
)) {
2179 static const char r59_non_bt
[] = {0x8f, 0x8f,
2180 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
2181 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
2183 rt2800_rfcsr_write(rt2x00dev
, 59,
2190 static void rt2800_config_channel_rf55xx(struct rt2x00_dev
*rt2x00dev
,
2191 struct ieee80211_conf
*conf
,
2192 struct rf_channel
*rf
,
2193 struct channel_info
*info
)
2200 const bool is_11b
= false;
2201 const bool is_type_ep
= false;
2203 rt2800_register_read(rt2x00dev
, LDO_CFG0
, ®
);
2204 rt2x00_set_field32(®
, LDO_CFG0_LDO_CORE_VLEVEL
,
2205 (rf
->channel
> 14 || conf_is_ht40(conf
)) ? 5 : 0);
2206 rt2800_register_write(rt2x00dev
, LDO_CFG0
, reg
);
2208 /* Order of values on rf_channel entry: N, K, mod, R */
2209 rt2800_rfcsr_write(rt2x00dev
, 8, rf
->rf1
& 0xff);
2211 rt2800_rfcsr_read(rt2x00dev
, 9, &rfcsr
);
2212 rt2x00_set_field8(&rfcsr
, RFCSR9_K
, rf
->rf2
& 0xf);
2213 rt2x00_set_field8(&rfcsr
, RFCSR9_N
, (rf
->rf1
& 0x100) >> 8);
2214 rt2x00_set_field8(&rfcsr
, RFCSR9_MOD
, ((rf
->rf3
- 8) & 0x4) >> 2);
2215 rt2800_rfcsr_write(rt2x00dev
, 9, rfcsr
);
2217 rt2800_rfcsr_read(rt2x00dev
, 11, &rfcsr
);
2218 rt2x00_set_field8(&rfcsr
, RFCSR11_R
, rf
->rf4
- 1);
2219 rt2x00_set_field8(&rfcsr
, RFCSR11_MOD
, (rf
->rf3
- 8) & 0x3);
2220 rt2800_rfcsr_write(rt2x00dev
, 11, rfcsr
);
2222 if (rf
->channel
<= 14) {
2223 rt2800_rfcsr_write(rt2x00dev
, 10, 0x90);
2224 /* FIXME: RF11 owerwrite ? */
2225 rt2800_rfcsr_write(rt2x00dev
, 11, 0x4A);
2226 rt2800_rfcsr_write(rt2x00dev
, 12, 0x52);
2227 rt2800_rfcsr_write(rt2x00dev
, 13, 0x42);
2228 rt2800_rfcsr_write(rt2x00dev
, 22, 0x40);
2229 rt2800_rfcsr_write(rt2x00dev
, 24, 0x4A);
2230 rt2800_rfcsr_write(rt2x00dev
, 25, 0x80);
2231 rt2800_rfcsr_write(rt2x00dev
, 27, 0x42);
2232 rt2800_rfcsr_write(rt2x00dev
, 36, 0x80);
2233 rt2800_rfcsr_write(rt2x00dev
, 37, 0x08);
2234 rt2800_rfcsr_write(rt2x00dev
, 38, 0x89);
2235 rt2800_rfcsr_write(rt2x00dev
, 39, 0x1B);
2236 rt2800_rfcsr_write(rt2x00dev
, 40, 0x0D);
2237 rt2800_rfcsr_write(rt2x00dev
, 41, 0x9B);
2238 rt2800_rfcsr_write(rt2x00dev
, 42, 0xD5);
2239 rt2800_rfcsr_write(rt2x00dev
, 43, 0x72);
2240 rt2800_rfcsr_write(rt2x00dev
, 44, 0x0E);
2241 rt2800_rfcsr_write(rt2x00dev
, 45, 0xA2);
2242 rt2800_rfcsr_write(rt2x00dev
, 46, 0x6B);
2243 rt2800_rfcsr_write(rt2x00dev
, 48, 0x10);
2244 rt2800_rfcsr_write(rt2x00dev
, 51, 0x3E);
2245 rt2800_rfcsr_write(rt2x00dev
, 52, 0x48);
2246 rt2800_rfcsr_write(rt2x00dev
, 54, 0x38);
2247 rt2800_rfcsr_write(rt2x00dev
, 56, 0xA1);
2248 rt2800_rfcsr_write(rt2x00dev
, 57, 0x00);
2249 rt2800_rfcsr_write(rt2x00dev
, 58, 0x39);
2250 rt2800_rfcsr_write(rt2x00dev
, 60, 0x45);
2251 rt2800_rfcsr_write(rt2x00dev
, 61, 0x91);
2252 rt2800_rfcsr_write(rt2x00dev
, 62, 0x39);
2254 /* TODO RF27 <- tssi */
2256 rfcsr
= rf
->channel
<= 10 ? 0x07 : 0x06;
2257 rt2800_rfcsr_write(rt2x00dev
, 23, rfcsr
);
2258 rt2800_rfcsr_write(rt2x00dev
, 59, rfcsr
);
2262 rt2800_rfcsr_write(rt2x00dev
, 31, 0xF8);
2263 rt2800_rfcsr_write(rt2x00dev
, 32, 0xC0);
2265 rt2800_rfcsr_write(rt2x00dev
, 55, 0x06);
2267 rt2800_rfcsr_write(rt2x00dev
, 55, 0x47);
2271 rt2800_rfcsr_write(rt2x00dev
, 55, 0x03);
2273 rt2800_rfcsr_write(rt2x00dev
, 55, 0x43);
2276 power_bound
= POWER_BOUND
;
2279 rt2800_rfcsr_write(rt2x00dev
, 10, 0x97);
2280 /* FIMXE: RF11 overwrite */
2281 rt2800_rfcsr_write(rt2x00dev
, 11, 0x40);
2282 rt2800_rfcsr_write(rt2x00dev
, 25, 0xBF);
2283 rt2800_rfcsr_write(rt2x00dev
, 27, 0x42);
2284 rt2800_rfcsr_write(rt2x00dev
, 36, 0x00);
2285 rt2800_rfcsr_write(rt2x00dev
, 37, 0x04);
2286 rt2800_rfcsr_write(rt2x00dev
, 38, 0x85);
2287 rt2800_rfcsr_write(rt2x00dev
, 40, 0x42);
2288 rt2800_rfcsr_write(rt2x00dev
, 41, 0xBB);
2289 rt2800_rfcsr_write(rt2x00dev
, 42, 0xD7);
2290 rt2800_rfcsr_write(rt2x00dev
, 45, 0x41);
2291 rt2800_rfcsr_write(rt2x00dev
, 48, 0x00);
2292 rt2800_rfcsr_write(rt2x00dev
, 57, 0x77);
2293 rt2800_rfcsr_write(rt2x00dev
, 60, 0x05);
2294 rt2800_rfcsr_write(rt2x00dev
, 61, 0x01);
2296 /* TODO RF27 <- tssi */
2298 if (rf
->channel
>= 36 && rf
->channel
<= 64) {
2300 rt2800_rfcsr_write(rt2x00dev
, 12, 0x2E);
2301 rt2800_rfcsr_write(rt2x00dev
, 13, 0x22);
2302 rt2800_rfcsr_write(rt2x00dev
, 22, 0x60);
2303 rt2800_rfcsr_write(rt2x00dev
, 23, 0x7F);
2304 if (rf
->channel
<= 50)
2305 rt2800_rfcsr_write(rt2x00dev
, 24, 0x09);
2306 else if (rf
->channel
>= 52)
2307 rt2800_rfcsr_write(rt2x00dev
, 24, 0x07);
2308 rt2800_rfcsr_write(rt2x00dev
, 39, 0x1C);
2309 rt2800_rfcsr_write(rt2x00dev
, 43, 0x5B);
2310 rt2800_rfcsr_write(rt2x00dev
, 44, 0X40);
2311 rt2800_rfcsr_write(rt2x00dev
, 46, 0X00);
2312 rt2800_rfcsr_write(rt2x00dev
, 51, 0xFE);
2313 rt2800_rfcsr_write(rt2x00dev
, 52, 0x0C);
2314 rt2800_rfcsr_write(rt2x00dev
, 54, 0xF8);
2315 if (rf
->channel
<= 50) {
2316 rt2800_rfcsr_write(rt2x00dev
, 55, 0x06),
2317 rt2800_rfcsr_write(rt2x00dev
, 56, 0xD3);
2318 } else if (rf
->channel
>= 52) {
2319 rt2800_rfcsr_write(rt2x00dev
, 55, 0x04);
2320 rt2800_rfcsr_write(rt2x00dev
, 56, 0xBB);
2323 rt2800_rfcsr_write(rt2x00dev
, 58, 0x15);
2324 rt2800_rfcsr_write(rt2x00dev
, 59, 0x7F);
2325 rt2800_rfcsr_write(rt2x00dev
, 62, 0x15);
2327 } else if (rf
->channel
>= 100 && rf
->channel
<= 165) {
2329 rt2800_rfcsr_write(rt2x00dev
, 12, 0x0E);
2330 rt2800_rfcsr_write(rt2x00dev
, 13, 0x42);
2331 rt2800_rfcsr_write(rt2x00dev
, 22, 0x40);
2332 if (rf
->channel
<= 153) {
2333 rt2800_rfcsr_write(rt2x00dev
, 23, 0x3C);
2334 rt2800_rfcsr_write(rt2x00dev
, 24, 0x06);
2335 } else if (rf
->channel
>= 155) {
2336 rt2800_rfcsr_write(rt2x00dev
, 23, 0x38);
2337 rt2800_rfcsr_write(rt2x00dev
, 24, 0x05);
2339 if (rf
->channel
<= 138) {
2340 rt2800_rfcsr_write(rt2x00dev
, 39, 0x1A);
2341 rt2800_rfcsr_write(rt2x00dev
, 43, 0x3B);
2342 rt2800_rfcsr_write(rt2x00dev
, 44, 0x20);
2343 rt2800_rfcsr_write(rt2x00dev
, 46, 0x18);
2344 } else if (rf
->channel
>= 140) {
2345 rt2800_rfcsr_write(rt2x00dev
, 39, 0x18);
2346 rt2800_rfcsr_write(rt2x00dev
, 43, 0x1B);
2347 rt2800_rfcsr_write(rt2x00dev
, 44, 0x10);
2348 rt2800_rfcsr_write(rt2x00dev
, 46, 0X08);
2350 if (rf
->channel
<= 124)
2351 rt2800_rfcsr_write(rt2x00dev
, 51, 0xFC);
2352 else if (rf
->channel
>= 126)
2353 rt2800_rfcsr_write(rt2x00dev
, 51, 0xEC);
2354 if (rf
->channel
<= 138)
2355 rt2800_rfcsr_write(rt2x00dev
, 52, 0x06);
2356 else if (rf
->channel
>= 140)
2357 rt2800_rfcsr_write(rt2x00dev
, 52, 0x06);
2358 rt2800_rfcsr_write(rt2x00dev
, 54, 0xEB);
2359 if (rf
->channel
<= 138)
2360 rt2800_rfcsr_write(rt2x00dev
, 55, 0x01);
2361 else if (rf
->channel
>= 140)
2362 rt2800_rfcsr_write(rt2x00dev
, 55, 0x00);
2363 if (rf
->channel
<= 128)
2364 rt2800_rfcsr_write(rt2x00dev
, 56, 0xBB);
2365 else if (rf
->channel
>= 130)
2366 rt2800_rfcsr_write(rt2x00dev
, 56, 0xAB);
2367 if (rf
->channel
<= 116)
2368 rt2800_rfcsr_write(rt2x00dev
, 58, 0x1D);
2369 else if (rf
->channel
>= 118)
2370 rt2800_rfcsr_write(rt2x00dev
, 58, 0x15);
2371 if (rf
->channel
<= 138)
2372 rt2800_rfcsr_write(rt2x00dev
, 59, 0x3F);
2373 else if (rf
->channel
>= 140)
2374 rt2800_rfcsr_write(rt2x00dev
, 59, 0x7C);
2375 if (rf
->channel
<= 116)
2376 rt2800_rfcsr_write(rt2x00dev
, 62, 0x1D);
2377 else if (rf
->channel
>= 118)
2378 rt2800_rfcsr_write(rt2x00dev
, 62, 0x15);
2381 power_bound
= POWER_BOUND_5G
;
2385 rt2800_rfcsr_read(rt2x00dev
, 49, &rfcsr
);
2386 if (info
->default_power1
> power_bound
)
2387 rt2x00_set_field8(&rfcsr
, RFCSR49_TX
, power_bound
);
2389 rt2x00_set_field8(&rfcsr
, RFCSR49_TX
, info
->default_power1
);
2391 rt2x00_set_field8(&rfcsr
, RFCSR49_EP
, ep_reg
);
2392 rt2800_rfcsr_write(rt2x00dev
, 49, rfcsr
);
2394 rt2800_rfcsr_read(rt2x00dev
, 50, &rfcsr
);
2395 if (info
->default_power1
> power_bound
)
2396 rt2x00_set_field8(&rfcsr
, RFCSR50_TX
, power_bound
);
2398 rt2x00_set_field8(&rfcsr
, RFCSR50_TX
, info
->default_power2
);
2400 rt2x00_set_field8(&rfcsr
, RFCSR50_EP
, ep_reg
);
2401 rt2800_rfcsr_write(rt2x00dev
, 50, rfcsr
);
2403 rt2800_rfcsr_read(rt2x00dev
, 1, &rfcsr
);
2404 rt2x00_set_field8(&rfcsr
, RFCSR1_RF_BLOCK_EN
, 1);
2405 rt2x00_set_field8(&rfcsr
, RFCSR1_PLL_PD
, 1);
2407 rt2x00_set_field8(&rfcsr
, RFCSR1_TX0_PD
,
2408 rt2x00dev
->default_ant
.tx_chain_num
>= 1);
2409 rt2x00_set_field8(&rfcsr
, RFCSR1_TX1_PD
,
2410 rt2x00dev
->default_ant
.tx_chain_num
== 2);
2411 rt2x00_set_field8(&rfcsr
, RFCSR1_TX2_PD
, 0);
2413 rt2x00_set_field8(&rfcsr
, RFCSR1_RX0_PD
,
2414 rt2x00dev
->default_ant
.rx_chain_num
>= 1);
2415 rt2x00_set_field8(&rfcsr
, RFCSR1_RX1_PD
,
2416 rt2x00dev
->default_ant
.rx_chain_num
== 2);
2417 rt2x00_set_field8(&rfcsr
, RFCSR1_RX2_PD
, 0);
2419 rt2800_rfcsr_write(rt2x00dev
, 1, rfcsr
);
2420 rt2800_rfcsr_write(rt2x00dev
, 6, 0xe4);
2422 if (conf_is_ht40(conf
))
2423 rt2800_rfcsr_write(rt2x00dev
, 30, 0x16);
2425 rt2800_rfcsr_write(rt2x00dev
, 30, 0x10);
2428 rt2800_rfcsr_write(rt2x00dev
, 31, 0x80);
2429 rt2800_rfcsr_write(rt2x00dev
, 32, 0x80);
2432 /* TODO proper frequency adjustment */
2433 rt2800_adjust_freq_offset(rt2x00dev
);
2435 /* TODO merge with others */
2436 rt2800_rfcsr_read(rt2x00dev
, 3, &rfcsr
);
2437 rt2x00_set_field8(&rfcsr
, RFCSR3_VCOCAL_EN
, 1);
2438 rt2800_rfcsr_write(rt2x00dev
, 3, rfcsr
);
2441 rt2800_bbp_write(rt2x00dev
, 62, 0x37 - rt2x00dev
->lna_gain
);
2442 rt2800_bbp_write(rt2x00dev
, 63, 0x37 - rt2x00dev
->lna_gain
);
2443 rt2800_bbp_write(rt2x00dev
, 64, 0x37 - rt2x00dev
->lna_gain
);
2445 rt2800_bbp_write(rt2x00dev
, 79, (rf
->channel
<= 14) ? 0x1C : 0x18);
2446 rt2800_bbp_write(rt2x00dev
, 80, (rf
->channel
<= 14) ? 0x0E : 0x08);
2447 rt2800_bbp_write(rt2x00dev
, 81, (rf
->channel
<= 14) ? 0x3A : 0x38);
2448 rt2800_bbp_write(rt2x00dev
, 82, (rf
->channel
<= 14) ? 0x62 : 0x92);
2450 /* GLRT band configuration */
2451 rt2800_bbp_write(rt2x00dev
, 195, 128);
2452 rt2800_bbp_write(rt2x00dev
, 196, (rf
->channel
<= 14) ? 0xE0 : 0xF0);
2453 rt2800_bbp_write(rt2x00dev
, 195, 129);
2454 rt2800_bbp_write(rt2x00dev
, 196, (rf
->channel
<= 14) ? 0x1F : 0x1E);
2455 rt2800_bbp_write(rt2x00dev
, 195, 130);
2456 rt2800_bbp_write(rt2x00dev
, 196, (rf
->channel
<= 14) ? 0x38 : 0x28);
2457 rt2800_bbp_write(rt2x00dev
, 195, 131);
2458 rt2800_bbp_write(rt2x00dev
, 196, (rf
->channel
<= 14) ? 0x32 : 0x20);
2459 rt2800_bbp_write(rt2x00dev
, 195, 133);
2460 rt2800_bbp_write(rt2x00dev
, 196, (rf
->channel
<= 14) ? 0x28 : 0x7F);
2461 rt2800_bbp_write(rt2x00dev
, 195, 124);
2462 rt2800_bbp_write(rt2x00dev
, 196, (rf
->channel
<= 14) ? 0x19 : 0x7F);
2465 static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev
*rt2x00dev
,
2466 const unsigned int word
,
2471 for (chain
= 0; chain
< rt2x00dev
->default_ant
.rx_chain_num
; chain
++) {
2472 rt2800_bbp_read(rt2x00dev
, 27, ®
);
2473 rt2x00_set_field8(®
, BBP27_RX_CHAIN_SEL
, chain
);
2474 rt2800_bbp_write(rt2x00dev
, 27, reg
);
2476 rt2800_bbp_write(rt2x00dev
, word
, value
);
2480 static void rt2800_iq_calibrate(struct rt2x00_dev
*rt2x00dev
, int channel
)
2485 rt2800_bbp_write(rt2x00dev
, 158, 0x2c);
2487 cal
= rt2x00_eeprom_byte(rt2x00dev
, EEPROM_IQ_GAIN_CAL_TX0_2G
);
2488 else if (channel
>= 36 && channel
<= 64)
2489 cal
= rt2x00_eeprom_byte(rt2x00dev
,
2490 EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5G
);
2491 else if (channel
>= 100 && channel
<= 138)
2492 cal
= rt2x00_eeprom_byte(rt2x00dev
,
2493 EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5G
);
2494 else if (channel
>= 140 && channel
<= 165)
2495 cal
= rt2x00_eeprom_byte(rt2x00dev
,
2496 EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5G
);
2499 rt2800_bbp_write(rt2x00dev
, 159, cal
);
2502 rt2800_bbp_write(rt2x00dev
, 158, 0x2d);
2504 cal
= rt2x00_eeprom_byte(rt2x00dev
, EEPROM_IQ_PHASE_CAL_TX0_2G
);
2505 else if (channel
>= 36 && channel
<= 64)
2506 cal
= rt2x00_eeprom_byte(rt2x00dev
,
2507 EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5G
);
2508 else if (channel
>= 100 && channel
<= 138)
2509 cal
= rt2x00_eeprom_byte(rt2x00dev
,
2510 EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5G
);
2511 else if (channel
>= 140 && channel
<= 165)
2512 cal
= rt2x00_eeprom_byte(rt2x00dev
,
2513 EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5G
);
2516 rt2800_bbp_write(rt2x00dev
, 159, cal
);
2519 rt2800_bbp_write(rt2x00dev
, 158, 0x4a);
2521 cal
= rt2x00_eeprom_byte(rt2x00dev
, EEPROM_IQ_GAIN_CAL_TX1_2G
);
2522 else if (channel
>= 36 && channel
<= 64)
2523 cal
= rt2x00_eeprom_byte(rt2x00dev
,
2524 EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5G
);
2525 else if (channel
>= 100 && channel
<= 138)
2526 cal
= rt2x00_eeprom_byte(rt2x00dev
,
2527 EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5G
);
2528 else if (channel
>= 140 && channel
<= 165)
2529 cal
= rt2x00_eeprom_byte(rt2x00dev
,
2530 EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5G
);
2533 rt2800_bbp_write(rt2x00dev
, 159, cal
);
2536 rt2800_bbp_write(rt2x00dev
, 158, 0x4b);
2538 cal
= rt2x00_eeprom_byte(rt2x00dev
, EEPROM_IQ_PHASE_CAL_TX1_2G
);
2539 else if (channel
>= 36 && channel
<= 64)
2540 cal
= rt2x00_eeprom_byte(rt2x00dev
,
2541 EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5G
);
2542 else if (channel
>= 100 && channel
<= 138)
2543 cal
= rt2x00_eeprom_byte(rt2x00dev
,
2544 EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5G
);
2545 else if (channel
>= 140 && channel
<= 165)
2546 cal
= rt2x00_eeprom_byte(rt2x00dev
,
2547 EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5G
);
2550 rt2800_bbp_write(rt2x00dev
, 159, cal
);
2552 /* FIXME: possible RX0, RX1 callibration ? */
2554 /* RF IQ compensation control */
2555 rt2800_bbp_write(rt2x00dev
, 158, 0x04);
2556 cal
= rt2x00_eeprom_byte(rt2x00dev
, EEPROM_RF_IQ_COMPENSATION_CONTROL
);
2557 rt2800_bbp_write(rt2x00dev
, 159, cal
!= 0xff ? cal
: 0);
2559 /* RF IQ imbalance compensation control */
2560 rt2800_bbp_write(rt2x00dev
, 158, 0x03);
2561 cal
= rt2x00_eeprom_byte(rt2x00dev
,
2562 EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CONTROL
);
2563 rt2800_bbp_write(rt2x00dev
, 159, cal
!= 0xff ? cal
: 0);
2566 static void rt2800_config_channel(struct rt2x00_dev
*rt2x00dev
,
2567 struct ieee80211_conf
*conf
,
2568 struct rf_channel
*rf
,
2569 struct channel_info
*info
)
2572 unsigned int tx_pin
;
2575 if (rf
->channel
<= 14) {
2576 info
->default_power1
= TXPOWER_G_TO_DEV(info
->default_power1
);
2577 info
->default_power2
= TXPOWER_G_TO_DEV(info
->default_power2
);
2579 info
->default_power1
= TXPOWER_A_TO_DEV(info
->default_power1
);
2580 info
->default_power2
= TXPOWER_A_TO_DEV(info
->default_power2
);
2583 switch (rt2x00dev
->chip
.rf
) {
2589 rt2800_config_channel_rf3xxx(rt2x00dev
, conf
, rf
, info
);
2592 rt2800_config_channel_rf3052(rt2x00dev
, conf
, rf
, info
);
2595 rt2800_config_channel_rf3290(rt2x00dev
, conf
, rf
, info
);
2598 rt2800_config_channel_rf3322(rt2x00dev
, conf
, rf
, info
);
2605 rt2800_config_channel_rf53xx(rt2x00dev
, conf
, rf
, info
);
2608 rt2800_config_channel_rf55xx(rt2x00dev
, conf
, rf
, info
);
2611 rt2800_config_channel_rf2xxx(rt2x00dev
, conf
, rf
, info
);
2614 if (rt2x00_rf(rt2x00dev
, RF3290
) ||
2615 rt2x00_rf(rt2x00dev
, RF3322
) ||
2616 rt2x00_rf(rt2x00dev
, RF5360
) ||
2617 rt2x00_rf(rt2x00dev
, RF5370
) ||
2618 rt2x00_rf(rt2x00dev
, RF5372
) ||
2619 rt2x00_rf(rt2x00dev
, RF5390
) ||
2620 rt2x00_rf(rt2x00dev
, RF5392
)) {
2621 rt2800_rfcsr_read(rt2x00dev
, 30, &rfcsr
);
2622 rt2x00_set_field8(&rfcsr
, RFCSR30_TX_H20M
, 0);
2623 rt2x00_set_field8(&rfcsr
, RFCSR30_RX_H20M
, 0);
2624 rt2800_rfcsr_write(rt2x00dev
, 30, rfcsr
);
2626 rt2800_rfcsr_read(rt2x00dev
, 3, &rfcsr
);
2627 rt2x00_set_field8(&rfcsr
, RFCSR3_VCOCAL_EN
, 1);
2628 rt2800_rfcsr_write(rt2x00dev
, 3, rfcsr
);
2632 * Change BBP settings
2634 if (rt2x00_rt(rt2x00dev
, RT3352
)) {
2635 rt2800_bbp_write(rt2x00dev
, 27, 0x0);
2636 rt2800_bbp_write(rt2x00dev
, 66, 0x26 + rt2x00dev
->lna_gain
);
2637 rt2800_bbp_write(rt2x00dev
, 27, 0x20);
2638 rt2800_bbp_write(rt2x00dev
, 66, 0x26 + rt2x00dev
->lna_gain
);
2640 rt2800_bbp_write(rt2x00dev
, 62, 0x37 - rt2x00dev
->lna_gain
);
2641 rt2800_bbp_write(rt2x00dev
, 63, 0x37 - rt2x00dev
->lna_gain
);
2642 rt2800_bbp_write(rt2x00dev
, 64, 0x37 - rt2x00dev
->lna_gain
);
2643 rt2800_bbp_write(rt2x00dev
, 86, 0);
2646 if (rf
->channel
<= 14) {
2647 if (!rt2x00_rt(rt2x00dev
, RT5390
) &&
2648 !rt2x00_rt(rt2x00dev
, RT5392
)) {
2649 if (test_bit(CAPABILITY_EXTERNAL_LNA_BG
,
2650 &rt2x00dev
->cap_flags
)) {
2651 rt2800_bbp_write(rt2x00dev
, 82, 0x62);
2652 rt2800_bbp_write(rt2x00dev
, 75, 0x46);
2654 rt2800_bbp_write(rt2x00dev
, 82, 0x84);
2655 rt2800_bbp_write(rt2x00dev
, 75, 0x50);
2659 if (rt2x00_rt(rt2x00dev
, RT3572
))
2660 rt2800_bbp_write(rt2x00dev
, 82, 0x94);
2662 rt2800_bbp_write(rt2x00dev
, 82, 0xf2);
2664 if (test_bit(CAPABILITY_EXTERNAL_LNA_A
, &rt2x00dev
->cap_flags
))
2665 rt2800_bbp_write(rt2x00dev
, 75, 0x46);
2667 rt2800_bbp_write(rt2x00dev
, 75, 0x50);
2670 rt2800_register_read(rt2x00dev
, TX_BAND_CFG
, ®
);
2671 rt2x00_set_field32(®
, TX_BAND_CFG_HT40_MINUS
, conf_is_ht40_minus(conf
));
2672 rt2x00_set_field32(®
, TX_BAND_CFG_A
, rf
->channel
> 14);
2673 rt2x00_set_field32(®
, TX_BAND_CFG_BG
, rf
->channel
<= 14);
2674 rt2800_register_write(rt2x00dev
, TX_BAND_CFG
, reg
);
2676 if (rt2x00_rt(rt2x00dev
, RT3572
))
2677 rt2800_rfcsr_write(rt2x00dev
, 8, 0);
2681 /* Turn on unused PA or LNA when not using 1T or 1R */
2682 if (rt2x00dev
->default_ant
.tx_chain_num
== 2) {
2683 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_A1_EN
,
2685 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_G1_EN
,
2689 /* Turn on unused PA or LNA when not using 1T or 1R */
2690 if (rt2x00dev
->default_ant
.rx_chain_num
== 2) {
2691 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_LNA_PE_A1_EN
, 1);
2692 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_LNA_PE_G1_EN
, 1);
2695 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_LNA_PE_A0_EN
, 1);
2696 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_LNA_PE_G0_EN
, 1);
2697 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_RFTR_EN
, 1);
2698 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_TRSW_EN
, 1);
2699 if (test_bit(CAPABILITY_BT_COEXIST
, &rt2x00dev
->cap_flags
))
2700 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_G0_EN
, 1);
2702 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_G0_EN
,
2704 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_A0_EN
, rf
->channel
> 14);
2706 rt2800_register_write(rt2x00dev
, TX_PIN_CFG
, tx_pin
);
2708 if (rt2x00_rt(rt2x00dev
, RT3572
))
2709 rt2800_rfcsr_write(rt2x00dev
, 8, 0x80);
2711 if (rt2x00_rt(rt2x00dev
, RT5592
)) {
2712 rt2800_bbp_write(rt2x00dev
, 195, 141);
2713 rt2800_bbp_write(rt2x00dev
, 196, conf_is_ht40(conf
) ? 0x10 : 0x1a);
2716 reg
= (rf
->channel
<= 14 ? 0x1c : 0x24) + 2 * rt2x00dev
->lna_gain
;
2717 rt2800_bbp_write_with_rx_chain(rt2x00dev
, 66, reg
);
2719 rt2800_iq_calibrate(rt2x00dev
, rf
->channel
);
2722 rt2800_bbp_read(rt2x00dev
, 4, &bbp
);
2723 rt2x00_set_field8(&bbp
, BBP4_BANDWIDTH
, 2 * conf_is_ht40(conf
));
2724 rt2800_bbp_write(rt2x00dev
, 4, bbp
);
2726 rt2800_bbp_read(rt2x00dev
, 3, &bbp
);
2727 rt2x00_set_field8(&bbp
, BBP3_HT40_MINUS
, conf_is_ht40_minus(conf
));
2728 rt2800_bbp_write(rt2x00dev
, 3, bbp
);
2730 if (rt2x00_rt_rev(rt2x00dev
, RT2860
, REV_RT2860C
)) {
2731 if (conf_is_ht40(conf
)) {
2732 rt2800_bbp_write(rt2x00dev
, 69, 0x1a);
2733 rt2800_bbp_write(rt2x00dev
, 70, 0x0a);
2734 rt2800_bbp_write(rt2x00dev
, 73, 0x16);
2736 rt2800_bbp_write(rt2x00dev
, 69, 0x16);
2737 rt2800_bbp_write(rt2x00dev
, 70, 0x08);
2738 rt2800_bbp_write(rt2x00dev
, 73, 0x11);
2745 * Clear channel statistic counters
2747 rt2800_register_read(rt2x00dev
, CH_IDLE_STA
, ®
);
2748 rt2800_register_read(rt2x00dev
, CH_BUSY_STA
, ®
);
2749 rt2800_register_read(rt2x00dev
, CH_BUSY_STA_SEC
, ®
);
2754 if (rt2x00_rt(rt2x00dev
, RT3352
)) {
2755 rt2800_bbp_read(rt2x00dev
, 49, &bbp
);
2756 rt2x00_set_field8(&bbp
, BBP49_UPDATE_FLAG
, 0);
2757 rt2800_bbp_write(rt2x00dev
, 49, bbp
);
2761 static int rt2800_get_gain_calibration_delta(struct rt2x00_dev
*rt2x00dev
)
2770 * Read TSSI boundaries for temperature compensation from
2773 * Array idx 0 1 2 3 4 5 6 7 8
2774 * Matching Delta value -4 -3 -2 -1 0 +1 +2 +3 +4
2775 * Example TSSI bounds 0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
2777 if (rt2x00dev
->curr_band
== IEEE80211_BAND_2GHZ
) {
2778 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_BG1
, &eeprom
);
2779 tssi_bounds
[0] = rt2x00_get_field16(eeprom
,
2780 EEPROM_TSSI_BOUND_BG1_MINUS4
);
2781 tssi_bounds
[1] = rt2x00_get_field16(eeprom
,
2782 EEPROM_TSSI_BOUND_BG1_MINUS3
);
2784 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_BG2
, &eeprom
);
2785 tssi_bounds
[2] = rt2x00_get_field16(eeprom
,
2786 EEPROM_TSSI_BOUND_BG2_MINUS2
);
2787 tssi_bounds
[3] = rt2x00_get_field16(eeprom
,
2788 EEPROM_TSSI_BOUND_BG2_MINUS1
);
2790 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_BG3
, &eeprom
);
2791 tssi_bounds
[4] = rt2x00_get_field16(eeprom
,
2792 EEPROM_TSSI_BOUND_BG3_REF
);
2793 tssi_bounds
[5] = rt2x00_get_field16(eeprom
,
2794 EEPROM_TSSI_BOUND_BG3_PLUS1
);
2796 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_BG4
, &eeprom
);
2797 tssi_bounds
[6] = rt2x00_get_field16(eeprom
,
2798 EEPROM_TSSI_BOUND_BG4_PLUS2
);
2799 tssi_bounds
[7] = rt2x00_get_field16(eeprom
,
2800 EEPROM_TSSI_BOUND_BG4_PLUS3
);
2802 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_BG5
, &eeprom
);
2803 tssi_bounds
[8] = rt2x00_get_field16(eeprom
,
2804 EEPROM_TSSI_BOUND_BG5_PLUS4
);
2806 step
= rt2x00_get_field16(eeprom
,
2807 EEPROM_TSSI_BOUND_BG5_AGC_STEP
);
2809 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_A1
, &eeprom
);
2810 tssi_bounds
[0] = rt2x00_get_field16(eeprom
,
2811 EEPROM_TSSI_BOUND_A1_MINUS4
);
2812 tssi_bounds
[1] = rt2x00_get_field16(eeprom
,
2813 EEPROM_TSSI_BOUND_A1_MINUS3
);
2815 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_A2
, &eeprom
);
2816 tssi_bounds
[2] = rt2x00_get_field16(eeprom
,
2817 EEPROM_TSSI_BOUND_A2_MINUS2
);
2818 tssi_bounds
[3] = rt2x00_get_field16(eeprom
,
2819 EEPROM_TSSI_BOUND_A2_MINUS1
);
2821 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_A3
, &eeprom
);
2822 tssi_bounds
[4] = rt2x00_get_field16(eeprom
,
2823 EEPROM_TSSI_BOUND_A3_REF
);
2824 tssi_bounds
[5] = rt2x00_get_field16(eeprom
,
2825 EEPROM_TSSI_BOUND_A3_PLUS1
);
2827 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_A4
, &eeprom
);
2828 tssi_bounds
[6] = rt2x00_get_field16(eeprom
,
2829 EEPROM_TSSI_BOUND_A4_PLUS2
);
2830 tssi_bounds
[7] = rt2x00_get_field16(eeprom
,
2831 EEPROM_TSSI_BOUND_A4_PLUS3
);
2833 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_A5
, &eeprom
);
2834 tssi_bounds
[8] = rt2x00_get_field16(eeprom
,
2835 EEPROM_TSSI_BOUND_A5_PLUS4
);
2837 step
= rt2x00_get_field16(eeprom
,
2838 EEPROM_TSSI_BOUND_A5_AGC_STEP
);
2842 * Check if temperature compensation is supported.
2844 if (tssi_bounds
[4] == 0xff || step
== 0xff)
2848 * Read current TSSI (BBP 49).
2850 rt2800_bbp_read(rt2x00dev
, 49, ¤t_tssi
);
2853 * Compare TSSI value (BBP49) with the compensation boundaries
2854 * from the EEPROM and increase or decrease tx power.
2856 for (i
= 0; i
<= 3; i
++) {
2857 if (current_tssi
> tssi_bounds
[i
])
2862 for (i
= 8; i
>= 5; i
--) {
2863 if (current_tssi
< tssi_bounds
[i
])
2868 return (i
- 4) * step
;
2871 static int rt2800_get_txpower_bw_comp(struct rt2x00_dev
*rt2x00dev
,
2872 enum ieee80211_band band
)
2879 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TXPOWER_DELTA
, &eeprom
);
2882 * HT40 compensation not required.
2884 if (eeprom
== 0xffff ||
2885 !test_bit(CONFIG_CHANNEL_HT40
, &rt2x00dev
->flags
))
2888 if (band
== IEEE80211_BAND_2GHZ
) {
2889 comp_en
= rt2x00_get_field16(eeprom
,
2890 EEPROM_TXPOWER_DELTA_ENABLE_2G
);
2892 comp_type
= rt2x00_get_field16(eeprom
,
2893 EEPROM_TXPOWER_DELTA_TYPE_2G
);
2894 comp_value
= rt2x00_get_field16(eeprom
,
2895 EEPROM_TXPOWER_DELTA_VALUE_2G
);
2897 comp_value
= -comp_value
;
2900 comp_en
= rt2x00_get_field16(eeprom
,
2901 EEPROM_TXPOWER_DELTA_ENABLE_5G
);
2903 comp_type
= rt2x00_get_field16(eeprom
,
2904 EEPROM_TXPOWER_DELTA_TYPE_5G
);
2905 comp_value
= rt2x00_get_field16(eeprom
,
2906 EEPROM_TXPOWER_DELTA_VALUE_5G
);
2908 comp_value
= -comp_value
;
2915 static int rt2800_get_txpower_reg_delta(struct rt2x00_dev
*rt2x00dev
,
2916 int power_level
, int max_power
)
2920 if (test_bit(CAPABILITY_POWER_LIMIT
, &rt2x00dev
->cap_flags
))
2924 * XXX: We don't know the maximum transmit power of our hardware since
2925 * the EEPROM doesn't expose it. We only know that we are calibrated
2928 * Hence, we assume the regulatory limit that cfg80211 calulated for
2929 * the current channel is our maximum and if we are requested to lower
2930 * the value we just reduce our tx power accordingly.
2932 delta
= power_level
- max_power
;
2933 return min(delta
, 0);
2936 static u8
rt2800_compensate_txpower(struct rt2x00_dev
*rt2x00dev
, int is_rate_b
,
2937 enum ieee80211_band band
, int power_level
,
2938 u8 txpower
, int delta
)
2943 u8 eirp_txpower_criterion
;
2946 if (test_bit(CAPABILITY_POWER_LIMIT
, &rt2x00dev
->cap_flags
)) {
2948 * Check if eirp txpower exceed txpower_limit.
2949 * We use OFDM 6M as criterion and its eirp txpower
2950 * is stored at EEPROM_EIRP_MAX_TX_POWER.
2951 * .11b data rate need add additional 4dbm
2952 * when calculating eirp txpower.
2954 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TXPOWER_BYRATE
+ 1,
2956 criterion
= rt2x00_get_field16(eeprom
,
2957 EEPROM_TXPOWER_BYRATE_RATE0
);
2959 rt2x00_eeprom_read(rt2x00dev
, EEPROM_EIRP_MAX_TX_POWER
,
2962 if (band
== IEEE80211_BAND_2GHZ
)
2963 eirp_txpower_criterion
= rt2x00_get_field16(eeprom
,
2964 EEPROM_EIRP_MAX_TX_POWER_2GHZ
);
2966 eirp_txpower_criterion
= rt2x00_get_field16(eeprom
,
2967 EEPROM_EIRP_MAX_TX_POWER_5GHZ
);
2969 eirp_txpower
= eirp_txpower_criterion
+ (txpower
- criterion
) +
2970 (is_rate_b
? 4 : 0) + delta
;
2972 reg_limit
= (eirp_txpower
> power_level
) ?
2973 (eirp_txpower
- power_level
) : 0;
2977 txpower
= max(0, txpower
+ delta
- reg_limit
);
2978 return min_t(u8
, txpower
, 0xc);
2982 * We configure transmit power using MAC TX_PWR_CFG_{0,...,N} registers and
2983 * BBP R1 register. TX_PWR_CFG_X allow to configure per rate TX power values,
2984 * 4 bits for each rate (tune from 0 to 15 dBm). BBP_R1 controls transmit power
2985 * for all rates, but allow to set only 4 discrete values: -12, -6, 0 and 6 dBm.
2986 * Reference per rate transmit power values are located in the EEPROM at
2987 * EEPROM_TXPOWER_BYRATE offset. We adjust them and BBP R1 settings according to
2988 * current conditions (i.e. band, bandwidth, temperature, user settings).
2990 static void rt2800_config_txpower(struct rt2x00_dev
*rt2x00dev
,
2991 struct ieee80211_channel
*chan
,
2997 int i
, is_rate_b
, delta
, power_ctrl
;
2998 enum ieee80211_band band
= chan
->band
;
3001 * Calculate HT40 compensation. For 40MHz we need to add or subtract
3002 * value read from EEPROM (different for 2GHz and for 5GHz).
3004 delta
= rt2800_get_txpower_bw_comp(rt2x00dev
, band
);
3007 * Calculate temperature compensation. Depends on measurement of current
3008 * TSSI (Transmitter Signal Strength Indication) we know TX power (due
3009 * to temperature or maybe other factors) is smaller or bigger than
3010 * expected. We adjust it, based on TSSI reference and boundaries values
3011 * provided in EEPROM.
3013 delta
+= rt2800_get_gain_calibration_delta(rt2x00dev
);
3016 * Decrease power according to user settings, on devices with unknown
3017 * maximum tx power. For other devices we take user power_level into
3018 * consideration on rt2800_compensate_txpower().
3020 delta
+= rt2800_get_txpower_reg_delta(rt2x00dev
, power_level
,
3024 * BBP_R1 controls TX power for all rates, it allow to set the following
3025 * gains -12, -6, 0, +6 dBm by setting values 2, 1, 0, 3 respectively.
3027 * TODO: we do not use +6 dBm option to do not increase power beyond
3028 * regulatory limit, however this could be utilized for devices with
3029 * CAPABILITY_POWER_LIMIT.
3031 * TODO: add different temperature compensation code for RT3290 & RT5390
3032 * to allow to use BBP_R1 for those chips.
3034 if (!rt2x00_rt(rt2x00dev
, RT3290
) &&
3035 !rt2x00_rt(rt2x00dev
, RT5390
)) {
3036 rt2800_bbp_read(rt2x00dev
, 1, &r1
);
3040 } else if (delta
<= -6) {
3046 rt2x00_set_field8(&r1
, BBP1_TX_POWER_CTRL
, power_ctrl
);
3047 rt2800_bbp_write(rt2x00dev
, 1, r1
);
3050 offset
= TX_PWR_CFG_0
;
3052 for (i
= 0; i
< EEPROM_TXPOWER_BYRATE_SIZE
; i
+= 2) {
3053 /* just to be safe */
3054 if (offset
> TX_PWR_CFG_4
)
3057 rt2800_register_read(rt2x00dev
, offset
, ®
);
3059 /* read the next four txpower values */
3060 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TXPOWER_BYRATE
+ i
,
3063 is_rate_b
= i
? 0 : 1;
3065 * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
3066 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
3067 * TX_PWR_CFG_4: unknown
3069 txpower
= rt2x00_get_field16(eeprom
,
3070 EEPROM_TXPOWER_BYRATE_RATE0
);
3071 txpower
= rt2800_compensate_txpower(rt2x00dev
, is_rate_b
, band
,
3072 power_level
, txpower
, delta
);
3073 rt2x00_set_field32(®
, TX_PWR_CFG_RATE0
, txpower
);
3076 * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
3077 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
3078 * TX_PWR_CFG_4: unknown
3080 txpower
= rt2x00_get_field16(eeprom
,
3081 EEPROM_TXPOWER_BYRATE_RATE1
);
3082 txpower
= rt2800_compensate_txpower(rt2x00dev
, is_rate_b
, band
,
3083 power_level
, txpower
, delta
);
3084 rt2x00_set_field32(®
, TX_PWR_CFG_RATE1
, txpower
);
3087 * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
3088 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14,
3089 * TX_PWR_CFG_4: unknown
3091 txpower
= rt2x00_get_field16(eeprom
,
3092 EEPROM_TXPOWER_BYRATE_RATE2
);
3093 txpower
= rt2800_compensate_txpower(rt2x00dev
, is_rate_b
, band
,
3094 power_level
, txpower
, delta
);
3095 rt2x00_set_field32(®
, TX_PWR_CFG_RATE2
, txpower
);
3098 * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
3099 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15,
3100 * TX_PWR_CFG_4: unknown
3102 txpower
= rt2x00_get_field16(eeprom
,
3103 EEPROM_TXPOWER_BYRATE_RATE3
);
3104 txpower
= rt2800_compensate_txpower(rt2x00dev
, is_rate_b
, band
,
3105 power_level
, txpower
, delta
);
3106 rt2x00_set_field32(®
, TX_PWR_CFG_RATE3
, txpower
);
3108 /* read the next four txpower values */
3109 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TXPOWER_BYRATE
+ i
+ 1,
3114 * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
3115 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
3116 * TX_PWR_CFG_4: unknown
3118 txpower
= rt2x00_get_field16(eeprom
,
3119 EEPROM_TXPOWER_BYRATE_RATE0
);
3120 txpower
= rt2800_compensate_txpower(rt2x00dev
, is_rate_b
, band
,
3121 power_level
, txpower
, delta
);
3122 rt2x00_set_field32(®
, TX_PWR_CFG_RATE4
, txpower
);
3125 * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
3126 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
3127 * TX_PWR_CFG_4: unknown
3129 txpower
= rt2x00_get_field16(eeprom
,
3130 EEPROM_TXPOWER_BYRATE_RATE1
);
3131 txpower
= rt2800_compensate_txpower(rt2x00dev
, is_rate_b
, band
,
3132 power_level
, txpower
, delta
);
3133 rt2x00_set_field32(®
, TX_PWR_CFG_RATE5
, txpower
);
3136 * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
3137 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
3138 * TX_PWR_CFG_4: unknown
3140 txpower
= rt2x00_get_field16(eeprom
,
3141 EEPROM_TXPOWER_BYRATE_RATE2
);
3142 txpower
= rt2800_compensate_txpower(rt2x00dev
, is_rate_b
, band
,
3143 power_level
, txpower
, delta
);
3144 rt2x00_set_field32(®
, TX_PWR_CFG_RATE6
, txpower
);
3147 * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
3148 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
3149 * TX_PWR_CFG_4: unknown
3151 txpower
= rt2x00_get_field16(eeprom
,
3152 EEPROM_TXPOWER_BYRATE_RATE3
);
3153 txpower
= rt2800_compensate_txpower(rt2x00dev
, is_rate_b
, band
,
3154 power_level
, txpower
, delta
);
3155 rt2x00_set_field32(®
, TX_PWR_CFG_RATE7
, txpower
);
3157 rt2800_register_write(rt2x00dev
, offset
, reg
);
3159 /* next TX_PWR_CFG register */
3164 void rt2800_gain_calibration(struct rt2x00_dev
*rt2x00dev
)
3166 rt2800_config_txpower(rt2x00dev
, rt2x00dev
->hw
->conf
.chandef
.chan
,
3167 rt2x00dev
->tx_power
);
3169 EXPORT_SYMBOL_GPL(rt2800_gain_calibration
);
3171 void rt2800_vco_calibration(struct rt2x00_dev
*rt2x00dev
)
3177 * A voltage-controlled oscillator(VCO) is an electronic oscillator
3178 * designed to be controlled in oscillation frequency by a voltage
3179 * input. Maybe the temperature will affect the frequency of
3180 * oscillation to be shifted. The VCO calibration will be called
3181 * periodically to adjust the frequency to be precision.
3184 rt2800_register_read(rt2x00dev
, TX_PIN_CFG
, &tx_pin
);
3185 tx_pin
&= TX_PIN_CFG_PA_PE_DISABLE
;
3186 rt2800_register_write(rt2x00dev
, TX_PIN_CFG
, tx_pin
);
3188 switch (rt2x00dev
->chip
.rf
) {
3195 rt2800_rfcsr_read(rt2x00dev
, 7, &rfcsr
);
3196 rt2x00_set_field8(&rfcsr
, RFCSR7_RF_TUNING
, 1);
3197 rt2800_rfcsr_write(rt2x00dev
, 7, rfcsr
);
3205 rt2800_rfcsr_read(rt2x00dev
, 3, &rfcsr
);
3206 rt2x00_set_field8(&rfcsr
, RFCSR3_VCOCAL_EN
, 1);
3207 rt2800_rfcsr_write(rt2x00dev
, 3, rfcsr
);
3215 rt2800_register_read(rt2x00dev
, TX_PIN_CFG
, &tx_pin
);
3216 if (rt2x00dev
->rf_channel
<= 14) {
3217 switch (rt2x00dev
->default_ant
.tx_chain_num
) {
3219 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_G2_EN
, 1);
3222 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_G1_EN
, 1);
3226 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_G0_EN
, 1);
3230 switch (rt2x00dev
->default_ant
.tx_chain_num
) {
3232 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_A2_EN
, 1);
3235 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_A1_EN
, 1);
3239 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_A0_EN
, 1);
3243 rt2800_register_write(rt2x00dev
, TX_PIN_CFG
, tx_pin
);
3246 EXPORT_SYMBOL_GPL(rt2800_vco_calibration
);
3248 static void rt2800_config_retry_limit(struct rt2x00_dev
*rt2x00dev
,
3249 struct rt2x00lib_conf
*libconf
)
3253 rt2800_register_read(rt2x00dev
, TX_RTY_CFG
, ®
);
3254 rt2x00_set_field32(®
, TX_RTY_CFG_SHORT_RTY_LIMIT
,
3255 libconf
->conf
->short_frame_max_tx_count
);
3256 rt2x00_set_field32(®
, TX_RTY_CFG_LONG_RTY_LIMIT
,
3257 libconf
->conf
->long_frame_max_tx_count
);
3258 rt2800_register_write(rt2x00dev
, TX_RTY_CFG
, reg
);
3261 static void rt2800_config_ps(struct rt2x00_dev
*rt2x00dev
,
3262 struct rt2x00lib_conf
*libconf
)
3264 enum dev_state state
=
3265 (libconf
->conf
->flags
& IEEE80211_CONF_PS
) ?
3266 STATE_SLEEP
: STATE_AWAKE
;
3269 if (state
== STATE_SLEEP
) {
3270 rt2800_register_write(rt2x00dev
, AUTOWAKEUP_CFG
, 0);
3272 rt2800_register_read(rt2x00dev
, AUTOWAKEUP_CFG
, ®
);
3273 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_AUTO_LEAD_TIME
, 5);
3274 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE
,
3275 libconf
->conf
->listen_interval
- 1);
3276 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_AUTOWAKE
, 1);
3277 rt2800_register_write(rt2x00dev
, AUTOWAKEUP_CFG
, reg
);
3279 rt2x00dev
->ops
->lib
->set_device_state(rt2x00dev
, state
);
3281 rt2800_register_read(rt2x00dev
, AUTOWAKEUP_CFG
, ®
);
3282 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_AUTO_LEAD_TIME
, 0);
3283 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE
, 0);
3284 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_AUTOWAKE
, 0);
3285 rt2800_register_write(rt2x00dev
, AUTOWAKEUP_CFG
, reg
);
3287 rt2x00dev
->ops
->lib
->set_device_state(rt2x00dev
, state
);
3291 void rt2800_config(struct rt2x00_dev
*rt2x00dev
,
3292 struct rt2x00lib_conf
*libconf
,
3293 const unsigned int flags
)
3295 /* Always recalculate LNA gain before changing configuration */
3296 rt2800_config_lna_gain(rt2x00dev
, libconf
);
3298 if (flags
& IEEE80211_CONF_CHANGE_CHANNEL
) {
3299 rt2800_config_channel(rt2x00dev
, libconf
->conf
,
3300 &libconf
->rf
, &libconf
->channel
);
3301 rt2800_config_txpower(rt2x00dev
, libconf
->conf
->chandef
.chan
,
3302 libconf
->conf
->power_level
);
3304 if (flags
& IEEE80211_CONF_CHANGE_POWER
)
3305 rt2800_config_txpower(rt2x00dev
, libconf
->conf
->chandef
.chan
,
3306 libconf
->conf
->power_level
);
3307 if (flags
& IEEE80211_CONF_CHANGE_RETRY_LIMITS
)
3308 rt2800_config_retry_limit(rt2x00dev
, libconf
);
3309 if (flags
& IEEE80211_CONF_CHANGE_PS
)
3310 rt2800_config_ps(rt2x00dev
, libconf
);
3312 EXPORT_SYMBOL_GPL(rt2800_config
);
3317 void rt2800_link_stats(struct rt2x00_dev
*rt2x00dev
, struct link_qual
*qual
)
3322 * Update FCS error count from register.
3324 rt2800_register_read(rt2x00dev
, RX_STA_CNT0
, ®
);
3325 qual
->rx_failed
= rt2x00_get_field32(reg
, RX_STA_CNT0_CRC_ERR
);
3327 EXPORT_SYMBOL_GPL(rt2800_link_stats
);
3329 static u8
rt2800_get_default_vgc(struct rt2x00_dev
*rt2x00dev
)
3333 if (rt2x00dev
->curr_band
== IEEE80211_BAND_2GHZ
) {
3334 if (rt2x00_rt(rt2x00dev
, RT3070
) ||
3335 rt2x00_rt(rt2x00dev
, RT3071
) ||
3336 rt2x00_rt(rt2x00dev
, RT3090
) ||
3337 rt2x00_rt(rt2x00dev
, RT3290
) ||
3338 rt2x00_rt(rt2x00dev
, RT3390
) ||
3339 rt2x00_rt(rt2x00dev
, RT3572
) ||
3340 rt2x00_rt(rt2x00dev
, RT5390
) ||
3341 rt2x00_rt(rt2x00dev
, RT5392
) ||
3342 rt2x00_rt(rt2x00dev
, RT5592
))
3343 vgc
= 0x1c + (2 * rt2x00dev
->lna_gain
);
3345 vgc
= 0x2e + rt2x00dev
->lna_gain
;
3346 } else { /* 5GHZ band */
3347 if (rt2x00_rt(rt2x00dev
, RT3572
))
3348 vgc
= 0x22 + (rt2x00dev
->lna_gain
* 5) / 3;
3349 else if (rt2x00_rt(rt2x00dev
, RT5592
))
3350 vgc
= 0x24 + (2 * rt2x00dev
->lna_gain
);
3352 if (!test_bit(CONFIG_CHANNEL_HT40
, &rt2x00dev
->flags
))
3353 vgc
= 0x32 + (rt2x00dev
->lna_gain
* 5) / 3;
3355 vgc
= 0x3a + (rt2x00dev
->lna_gain
* 5) / 3;
3362 static inline void rt2800_set_vgc(struct rt2x00_dev
*rt2x00dev
,
3363 struct link_qual
*qual
, u8 vgc_level
)
3365 if (qual
->vgc_level
!= vgc_level
) {
3366 if (rt2x00_rt(rt2x00dev
, RT5592
)) {
3367 rt2800_bbp_write(rt2x00dev
, 83, qual
->rssi
> -65 ? 0x4a : 0x7a);
3368 rt2800_bbp_write_with_rx_chain(rt2x00dev
, 66, vgc_level
);
3370 rt2800_bbp_write(rt2x00dev
, 66, vgc_level
);
3371 qual
->vgc_level
= vgc_level
;
3372 qual
->vgc_level_reg
= vgc_level
;
3376 void rt2800_reset_tuner(struct rt2x00_dev
*rt2x00dev
, struct link_qual
*qual
)
3378 rt2800_set_vgc(rt2x00dev
, qual
, rt2800_get_default_vgc(rt2x00dev
));
3380 EXPORT_SYMBOL_GPL(rt2800_reset_tuner
);
3382 void rt2800_link_tuner(struct rt2x00_dev
*rt2x00dev
, struct link_qual
*qual
,
3387 if (rt2x00_rt_rev(rt2x00dev
, RT2860
, REV_RT2860C
))
3390 * When RSSI is better then -80 increase VGC level with 0x10, except
3394 vgc
= rt2800_get_default_vgc(rt2x00dev
);
3396 if (rt2x00_rt(rt2x00dev
, RT5592
) && qual
->rssi
> -65)
3398 else if (qual
->rssi
> -80)
3401 rt2800_set_vgc(rt2x00dev
, qual
, vgc
);
3403 EXPORT_SYMBOL_GPL(rt2800_link_tuner
);
3406 * Initialization functions.
3408 static int rt2800_init_registers(struct rt2x00_dev
*rt2x00dev
)
3415 rt2800_disable_wpdma(rt2x00dev
);
3417 ret
= rt2800_drv_init_registers(rt2x00dev
);
3421 rt2800_register_read(rt2x00dev
, BCN_OFFSET0
, ®
);
3422 rt2x00_set_field32(®
, BCN_OFFSET0_BCN0
, 0xe0); /* 0x3800 */
3423 rt2x00_set_field32(®
, BCN_OFFSET0_BCN1
, 0xe8); /* 0x3a00 */
3424 rt2x00_set_field32(®
, BCN_OFFSET0_BCN2
, 0xf0); /* 0x3c00 */
3425 rt2x00_set_field32(®
, BCN_OFFSET0_BCN3
, 0xf8); /* 0x3e00 */
3426 rt2800_register_write(rt2x00dev
, BCN_OFFSET0
, reg
);
3428 rt2800_register_read(rt2x00dev
, BCN_OFFSET1
, ®
);
3429 rt2x00_set_field32(®
, BCN_OFFSET1_BCN4
, 0xc8); /* 0x3200 */
3430 rt2x00_set_field32(®
, BCN_OFFSET1_BCN5
, 0xd0); /* 0x3400 */
3431 rt2x00_set_field32(®
, BCN_OFFSET1_BCN6
, 0x77); /* 0x1dc0 */
3432 rt2x00_set_field32(®
, BCN_OFFSET1_BCN7
, 0x6f); /* 0x1bc0 */
3433 rt2800_register_write(rt2x00dev
, BCN_OFFSET1
, reg
);
3435 rt2800_register_write(rt2x00dev
, LEGACY_BASIC_RATE
, 0x0000013f);
3436 rt2800_register_write(rt2x00dev
, HT_BASIC_RATE
, 0x00008003);
3438 rt2800_register_write(rt2x00dev
, MAC_SYS_CTRL
, 0x00000000);
3440 rt2800_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
3441 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_INTERVAL
, 1600);
3442 rt2x00_set_field32(®
, BCN_TIME_CFG_TSF_TICKING
, 0);
3443 rt2x00_set_field32(®
, BCN_TIME_CFG_TSF_SYNC
, 0);
3444 rt2x00_set_field32(®
, BCN_TIME_CFG_TBTT_ENABLE
, 0);
3445 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_GEN
, 0);
3446 rt2x00_set_field32(®
, BCN_TIME_CFG_TX_TIME_COMPENSATE
, 0);
3447 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
3449 rt2800_config_filter(rt2x00dev
, FIF_ALLMULTI
);
3451 rt2800_register_read(rt2x00dev
, BKOFF_SLOT_CFG
, ®
);
3452 rt2x00_set_field32(®
, BKOFF_SLOT_CFG_SLOT_TIME
, 9);
3453 rt2x00_set_field32(®
, BKOFF_SLOT_CFG_CC_DELAY_TIME
, 2);
3454 rt2800_register_write(rt2x00dev
, BKOFF_SLOT_CFG
, reg
);
3456 if (rt2x00_rt(rt2x00dev
, RT3290
)) {
3457 rt2800_register_read(rt2x00dev
, WLAN_FUN_CTRL
, ®
);
3458 if (rt2x00_get_field32(reg
, WLAN_EN
) == 1) {
3459 rt2x00_set_field32(®
, PCIE_APP0_CLK_REQ
, 1);
3460 rt2800_register_write(rt2x00dev
, WLAN_FUN_CTRL
, reg
);
3463 rt2800_register_read(rt2x00dev
, CMB_CTRL
, ®
);
3464 if (!(rt2x00_get_field32(reg
, LDO0_EN
) == 1)) {
3465 rt2x00_set_field32(®
, LDO0_EN
, 1);
3466 rt2x00_set_field32(®
, LDO_BGSEL
, 3);
3467 rt2800_register_write(rt2x00dev
, CMB_CTRL
, reg
);
3470 rt2800_register_read(rt2x00dev
, OSC_CTRL
, ®
);
3471 rt2x00_set_field32(®
, OSC_ROSC_EN
, 1);
3472 rt2x00_set_field32(®
, OSC_CAL_REQ
, 1);
3473 rt2x00_set_field32(®
, OSC_REF_CYCLE
, 0x27);
3474 rt2800_register_write(rt2x00dev
, OSC_CTRL
, reg
);
3476 rt2800_register_read(rt2x00dev
, COEX_CFG0
, ®
);
3477 rt2x00_set_field32(®
, COEX_CFG_ANT
, 0x5e);
3478 rt2800_register_write(rt2x00dev
, COEX_CFG0
, reg
);
3480 rt2800_register_read(rt2x00dev
, COEX_CFG2
, ®
);
3481 rt2x00_set_field32(®
, BT_COEX_CFG1
, 0x00);
3482 rt2x00_set_field32(®
, BT_COEX_CFG0
, 0x17);
3483 rt2x00_set_field32(®
, WL_COEX_CFG1
, 0x93);
3484 rt2x00_set_field32(®
, WL_COEX_CFG0
, 0x7f);
3485 rt2800_register_write(rt2x00dev
, COEX_CFG2
, reg
);
3487 rt2800_register_read(rt2x00dev
, PLL_CTRL
, ®
);
3488 rt2x00_set_field32(®
, PLL_CONTROL
, 1);
3489 rt2800_register_write(rt2x00dev
, PLL_CTRL
, reg
);
3492 if (rt2x00_rt(rt2x00dev
, RT3071
) ||
3493 rt2x00_rt(rt2x00dev
, RT3090
) ||
3494 rt2x00_rt(rt2x00dev
, RT3290
) ||
3495 rt2x00_rt(rt2x00dev
, RT3390
)) {
3497 if (rt2x00_rt(rt2x00dev
, RT3290
))
3498 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
,
3501 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
,
3504 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00000000);
3505 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3071
, REV_RT3071E
) ||
3506 rt2x00_rt_rev_lt(rt2x00dev
, RT3090
, REV_RT3090E
) ||
3507 rt2x00_rt_rev_lt(rt2x00dev
, RT3390
, REV_RT3390E
)) {
3508 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF1
, &eeprom
);
3509 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF1_DAC_TEST
))
3510 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
,
3513 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
,
3516 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
, 0x00000000);
3518 } else if (rt2x00_rt(rt2x00dev
, RT3070
)) {
3519 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000400);
3521 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070F
)) {
3522 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00000000);
3523 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
, 0x0000002c);
3525 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00080606);
3526 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
, 0x00000000);
3528 } else if (rt2800_is_305x_soc(rt2x00dev
)) {
3529 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000400);
3530 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00000000);
3531 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
, 0x00000030);
3532 } else if (rt2x00_rt(rt2x00dev
, RT3352
)) {
3533 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000402);
3534 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00080606);
3535 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
, 0x00000000);
3536 } else if (rt2x00_rt(rt2x00dev
, RT3572
)) {
3537 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000400);
3538 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00080606);
3539 } else if (rt2x00_rt(rt2x00dev
, RT5390
) ||
3540 rt2x00_rt(rt2x00dev
, RT5392
) ||
3541 rt2x00_rt(rt2x00dev
, RT5592
)) {
3542 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000404);
3543 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00080606);
3544 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
, 0x00000000);
3546 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000000);
3547 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00080606);
3550 rt2800_register_read(rt2x00dev
, TX_LINK_CFG
, ®
);
3551 rt2x00_set_field32(®
, TX_LINK_CFG_REMOTE_MFB_LIFETIME
, 32);
3552 rt2x00_set_field32(®
, TX_LINK_CFG_MFB_ENABLE
, 0);
3553 rt2x00_set_field32(®
, TX_LINK_CFG_REMOTE_UMFS_ENABLE
, 0);
3554 rt2x00_set_field32(®
, TX_LINK_CFG_TX_MRQ_EN
, 0);
3555 rt2x00_set_field32(®
, TX_LINK_CFG_TX_RDG_EN
, 0);
3556 rt2x00_set_field32(®
, TX_LINK_CFG_TX_CF_ACK_EN
, 1);
3557 rt2x00_set_field32(®
, TX_LINK_CFG_REMOTE_MFB
, 0);
3558 rt2x00_set_field32(®
, TX_LINK_CFG_REMOTE_MFS
, 0);
3559 rt2800_register_write(rt2x00dev
, TX_LINK_CFG
, reg
);
3561 rt2800_register_read(rt2x00dev
, TX_TIMEOUT_CFG
, ®
);
3562 rt2x00_set_field32(®
, TX_TIMEOUT_CFG_MPDU_LIFETIME
, 9);
3563 rt2x00_set_field32(®
, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT
, 32);
3564 rt2x00_set_field32(®
, TX_TIMEOUT_CFG_TX_OP_TIMEOUT
, 10);
3565 rt2800_register_write(rt2x00dev
, TX_TIMEOUT_CFG
, reg
);
3567 rt2800_register_read(rt2x00dev
, MAX_LEN_CFG
, ®
);
3568 rt2x00_set_field32(®
, MAX_LEN_CFG_MAX_MPDU
, AGGREGATION_SIZE
);
3569 if (rt2x00_rt_rev_gte(rt2x00dev
, RT2872
, REV_RT2872E
) ||
3570 rt2x00_rt(rt2x00dev
, RT2883
) ||
3571 rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070E
))
3572 rt2x00_set_field32(®
, MAX_LEN_CFG_MAX_PSDU
, 2);
3574 rt2x00_set_field32(®
, MAX_LEN_CFG_MAX_PSDU
, 1);
3575 rt2x00_set_field32(®
, MAX_LEN_CFG_MIN_PSDU
, 0);
3576 rt2x00_set_field32(®
, MAX_LEN_CFG_MIN_MPDU
, 0);
3577 rt2800_register_write(rt2x00dev
, MAX_LEN_CFG
, reg
);
3579 rt2800_register_read(rt2x00dev
, LED_CFG
, ®
);
3580 rt2x00_set_field32(®
, LED_CFG_ON_PERIOD
, 70);
3581 rt2x00_set_field32(®
, LED_CFG_OFF_PERIOD
, 30);
3582 rt2x00_set_field32(®
, LED_CFG_SLOW_BLINK_PERIOD
, 3);
3583 rt2x00_set_field32(®
, LED_CFG_R_LED_MODE
, 3);
3584 rt2x00_set_field32(®
, LED_CFG_G_LED_MODE
, 3);
3585 rt2x00_set_field32(®
, LED_CFG_Y_LED_MODE
, 3);
3586 rt2x00_set_field32(®
, LED_CFG_LED_POLAR
, 1);
3587 rt2800_register_write(rt2x00dev
, LED_CFG
, reg
);
3589 rt2800_register_write(rt2x00dev
, PBF_MAX_PCNT
, 0x1f3fbf9f);
3591 rt2800_register_read(rt2x00dev
, TX_RTY_CFG
, ®
);
3592 rt2x00_set_field32(®
, TX_RTY_CFG_SHORT_RTY_LIMIT
, 15);
3593 rt2x00_set_field32(®
, TX_RTY_CFG_LONG_RTY_LIMIT
, 31);
3594 rt2x00_set_field32(®
, TX_RTY_CFG_LONG_RTY_THRE
, 2000);
3595 rt2x00_set_field32(®
, TX_RTY_CFG_NON_AGG_RTY_MODE
, 0);
3596 rt2x00_set_field32(®
, TX_RTY_CFG_AGG_RTY_MODE
, 0);
3597 rt2x00_set_field32(®
, TX_RTY_CFG_TX_AUTO_FB_ENABLE
, 1);
3598 rt2800_register_write(rt2x00dev
, TX_RTY_CFG
, reg
);
3600 rt2800_register_read(rt2x00dev
, AUTO_RSP_CFG
, ®
);
3601 rt2x00_set_field32(®
, AUTO_RSP_CFG_AUTORESPONDER
, 1);
3602 rt2x00_set_field32(®
, AUTO_RSP_CFG_BAC_ACK_POLICY
, 1);
3603 rt2x00_set_field32(®
, AUTO_RSP_CFG_CTS_40_MMODE
, 0);
3604 rt2x00_set_field32(®
, AUTO_RSP_CFG_CTS_40_MREF
, 0);
3605 rt2x00_set_field32(®
, AUTO_RSP_CFG_AR_PREAMBLE
, 1);
3606 rt2x00_set_field32(®
, AUTO_RSP_CFG_DUAL_CTS_EN
, 0);
3607 rt2x00_set_field32(®
, AUTO_RSP_CFG_ACK_CTS_PSM_BIT
, 0);
3608 rt2800_register_write(rt2x00dev
, AUTO_RSP_CFG
, reg
);
3610 rt2800_register_read(rt2x00dev
, CCK_PROT_CFG
, ®
);
3611 rt2x00_set_field32(®
, CCK_PROT_CFG_PROTECT_RATE
, 3);
3612 rt2x00_set_field32(®
, CCK_PROT_CFG_PROTECT_CTRL
, 0);
3613 rt2x00_set_field32(®
, CCK_PROT_CFG_PROTECT_NAV_SHORT
, 1);
3614 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
3615 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
3616 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
3617 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_MM40
, 0);
3618 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
3619 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_GF40
, 0);
3620 rt2x00_set_field32(®
, CCK_PROT_CFG_RTS_TH_EN
, 1);
3621 rt2800_register_write(rt2x00dev
, CCK_PROT_CFG
, reg
);
3623 rt2800_register_read(rt2x00dev
, OFDM_PROT_CFG
, ®
);
3624 rt2x00_set_field32(®
, OFDM_PROT_CFG_PROTECT_RATE
, 3);
3625 rt2x00_set_field32(®
, OFDM_PROT_CFG_PROTECT_CTRL
, 0);
3626 rt2x00_set_field32(®
, OFDM_PROT_CFG_PROTECT_NAV_SHORT
, 1);
3627 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
3628 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
3629 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
3630 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_MM40
, 0);
3631 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
3632 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_GF40
, 0);
3633 rt2x00_set_field32(®
, OFDM_PROT_CFG_RTS_TH_EN
, 1);
3634 rt2800_register_write(rt2x00dev
, OFDM_PROT_CFG
, reg
);
3636 rt2800_register_read(rt2x00dev
, MM20_PROT_CFG
, ®
);
3637 rt2x00_set_field32(®
, MM20_PROT_CFG_PROTECT_RATE
, 0x4004);
3638 rt2x00_set_field32(®
, MM20_PROT_CFG_PROTECT_CTRL
, 0);
3639 rt2x00_set_field32(®
, MM20_PROT_CFG_PROTECT_NAV_SHORT
, 1);
3640 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
3641 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
3642 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
3643 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_MM40
, 0);
3644 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
3645 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_GF40
, 0);
3646 rt2x00_set_field32(®
, MM20_PROT_CFG_RTS_TH_EN
, 0);
3647 rt2800_register_write(rt2x00dev
, MM20_PROT_CFG
, reg
);
3649 rt2800_register_read(rt2x00dev
, MM40_PROT_CFG
, ®
);
3650 rt2x00_set_field32(®
, MM40_PROT_CFG_PROTECT_RATE
, 0x4084);
3651 rt2x00_set_field32(®
, MM40_PROT_CFG_PROTECT_CTRL
, 0);
3652 rt2x00_set_field32(®
, MM40_PROT_CFG_PROTECT_NAV_SHORT
, 1);
3653 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
3654 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
3655 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
3656 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_MM40
, 1);
3657 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
3658 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_GF40
, 1);
3659 rt2x00_set_field32(®
, MM40_PROT_CFG_RTS_TH_EN
, 0);
3660 rt2800_register_write(rt2x00dev
, MM40_PROT_CFG
, reg
);
3662 rt2800_register_read(rt2x00dev
, GF20_PROT_CFG
, ®
);
3663 rt2x00_set_field32(®
, GF20_PROT_CFG_PROTECT_RATE
, 0x4004);
3664 rt2x00_set_field32(®
, GF20_PROT_CFG_PROTECT_CTRL
, 0);
3665 rt2x00_set_field32(®
, GF20_PROT_CFG_PROTECT_NAV_SHORT
, 1);
3666 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
3667 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
3668 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
3669 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_MM40
, 0);
3670 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
3671 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_GF40
, 0);
3672 rt2x00_set_field32(®
, GF20_PROT_CFG_RTS_TH_EN
, 0);
3673 rt2800_register_write(rt2x00dev
, GF20_PROT_CFG
, reg
);
3675 rt2800_register_read(rt2x00dev
, GF40_PROT_CFG
, ®
);
3676 rt2x00_set_field32(®
, GF40_PROT_CFG_PROTECT_RATE
, 0x4084);
3677 rt2x00_set_field32(®
, GF40_PROT_CFG_PROTECT_CTRL
, 0);
3678 rt2x00_set_field32(®
, GF40_PROT_CFG_PROTECT_NAV_SHORT
, 1);
3679 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
3680 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
3681 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
3682 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_MM40
, 1);
3683 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
3684 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_GF40
, 1);
3685 rt2x00_set_field32(®
, GF40_PROT_CFG_RTS_TH_EN
, 0);
3686 rt2800_register_write(rt2x00dev
, GF40_PROT_CFG
, reg
);
3688 if (rt2x00_is_usb(rt2x00dev
)) {
3689 rt2800_register_write(rt2x00dev
, PBF_CFG
, 0xf40006);
3691 rt2800_register_read(rt2x00dev
, WPDMA_GLO_CFG
, ®
);
3692 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_TX_DMA
, 0);
3693 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_DMA_BUSY
, 0);
3694 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_RX_DMA
, 0);
3695 rt2x00_set_field32(®
, WPDMA_GLO_CFG_RX_DMA_BUSY
, 0);
3696 rt2x00_set_field32(®
, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE
, 3);
3697 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_WRITEBACK_DONE
, 0);
3698 rt2x00_set_field32(®
, WPDMA_GLO_CFG_BIG_ENDIAN
, 0);
3699 rt2x00_set_field32(®
, WPDMA_GLO_CFG_RX_HDR_SCATTER
, 0);
3700 rt2x00_set_field32(®
, WPDMA_GLO_CFG_HDR_SEG_LEN
, 0);
3701 rt2800_register_write(rt2x00dev
, WPDMA_GLO_CFG
, reg
);
3705 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
3706 * although it is reserved.
3708 rt2800_register_read(rt2x00dev
, TXOP_CTRL_CFG
, ®
);
3709 rt2x00_set_field32(®
, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN
, 1);
3710 rt2x00_set_field32(®
, TXOP_CTRL_CFG_AC_TRUN_EN
, 1);
3711 rt2x00_set_field32(®
, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN
, 1);
3712 rt2x00_set_field32(®
, TXOP_CTRL_CFG_USER_MODE_TRUN_EN
, 1);
3713 rt2x00_set_field32(®
, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN
, 1);
3714 rt2x00_set_field32(®
, TXOP_CTRL_CFG_RESERVED_TRUN_EN
, 1);
3715 rt2x00_set_field32(®
, TXOP_CTRL_CFG_LSIG_TXOP_EN
, 0);
3716 rt2x00_set_field32(®
, TXOP_CTRL_CFG_EXT_CCA_EN
, 0);
3717 rt2x00_set_field32(®
, TXOP_CTRL_CFG_EXT_CCA_DLY
, 88);
3718 rt2x00_set_field32(®
, TXOP_CTRL_CFG_EXT_CWMIN
, 0);
3719 rt2800_register_write(rt2x00dev
, TXOP_CTRL_CFG
, reg
);
3721 reg
= rt2x00_rt(rt2x00dev
, RT5592
) ? 0x00000082 : 0x00000002;
3722 rt2800_register_write(rt2x00dev
, TXOP_HLDR_ET
, reg
);
3724 rt2800_register_read(rt2x00dev
, TX_RTS_CFG
, ®
);
3725 rt2x00_set_field32(®
, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT
, 32);
3726 rt2x00_set_field32(®
, TX_RTS_CFG_RTS_THRES
,
3727 IEEE80211_MAX_RTS_THRESHOLD
);
3728 rt2x00_set_field32(®
, TX_RTS_CFG_RTS_FBK_EN
, 0);
3729 rt2800_register_write(rt2x00dev
, TX_RTS_CFG
, reg
);
3731 rt2800_register_write(rt2x00dev
, EXP_ACK_TIME
, 0x002400ca);
3734 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
3735 * time should be set to 16. However, the original Ralink driver uses
3736 * 16 for both and indeed using a value of 10 for CCK SIFS results in
3737 * connection problems with 11g + CTS protection. Hence, use the same
3738 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
3740 rt2800_register_read(rt2x00dev
, XIFS_TIME_CFG
, ®
);
3741 rt2x00_set_field32(®
, XIFS_TIME_CFG_CCKM_SIFS_TIME
, 16);
3742 rt2x00_set_field32(®
, XIFS_TIME_CFG_OFDM_SIFS_TIME
, 16);
3743 rt2x00_set_field32(®
, XIFS_TIME_CFG_OFDM_XIFS_TIME
, 4);
3744 rt2x00_set_field32(®
, XIFS_TIME_CFG_EIFS
, 314);
3745 rt2x00_set_field32(®
, XIFS_TIME_CFG_BB_RXEND_ENABLE
, 1);
3746 rt2800_register_write(rt2x00dev
, XIFS_TIME_CFG
, reg
);
3748 rt2800_register_write(rt2x00dev
, PWR_PIN_CFG
, 0x00000003);
3751 * ASIC will keep garbage value after boot, clear encryption keys.
3753 for (i
= 0; i
< 4; i
++)
3754 rt2800_register_write(rt2x00dev
,
3755 SHARED_KEY_MODE_ENTRY(i
), 0);
3757 for (i
= 0; i
< 256; i
++) {
3758 rt2800_config_wcid(rt2x00dev
, NULL
, i
);
3759 rt2800_delete_wcid_attr(rt2x00dev
, i
);
3760 rt2800_register_write(rt2x00dev
, MAC_IVEIV_ENTRY(i
), 0);
3766 rt2800_clear_beacon_register(rt2x00dev
, HW_BEACON_BASE0
);
3767 rt2800_clear_beacon_register(rt2x00dev
, HW_BEACON_BASE1
);
3768 rt2800_clear_beacon_register(rt2x00dev
, HW_BEACON_BASE2
);
3769 rt2800_clear_beacon_register(rt2x00dev
, HW_BEACON_BASE3
);
3770 rt2800_clear_beacon_register(rt2x00dev
, HW_BEACON_BASE4
);
3771 rt2800_clear_beacon_register(rt2x00dev
, HW_BEACON_BASE5
);
3772 rt2800_clear_beacon_register(rt2x00dev
, HW_BEACON_BASE6
);
3773 rt2800_clear_beacon_register(rt2x00dev
, HW_BEACON_BASE7
);
3775 if (rt2x00_is_usb(rt2x00dev
)) {
3776 rt2800_register_read(rt2x00dev
, US_CYC_CNT
, ®
);
3777 rt2x00_set_field32(®
, US_CYC_CNT_CLOCK_CYCLE
, 30);
3778 rt2800_register_write(rt2x00dev
, US_CYC_CNT
, reg
);
3779 } else if (rt2x00_is_pcie(rt2x00dev
)) {
3780 rt2800_register_read(rt2x00dev
, US_CYC_CNT
, ®
);
3781 rt2x00_set_field32(®
, US_CYC_CNT_CLOCK_CYCLE
, 125);
3782 rt2800_register_write(rt2x00dev
, US_CYC_CNT
, reg
);
3785 rt2800_register_read(rt2x00dev
, HT_FBK_CFG0
, ®
);
3786 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS0FBK
, 0);
3787 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS1FBK
, 0);
3788 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS2FBK
, 1);
3789 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS3FBK
, 2);
3790 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS4FBK
, 3);
3791 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS5FBK
, 4);
3792 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS6FBK
, 5);
3793 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS7FBK
, 6);
3794 rt2800_register_write(rt2x00dev
, HT_FBK_CFG0
, reg
);
3796 rt2800_register_read(rt2x00dev
, HT_FBK_CFG1
, ®
);
3797 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS8FBK
, 8);
3798 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS9FBK
, 8);
3799 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS10FBK
, 9);
3800 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS11FBK
, 10);
3801 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS12FBK
, 11);
3802 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS13FBK
, 12);
3803 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS14FBK
, 13);
3804 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS15FBK
, 14);
3805 rt2800_register_write(rt2x00dev
, HT_FBK_CFG1
, reg
);
3807 rt2800_register_read(rt2x00dev
, LG_FBK_CFG0
, ®
);
3808 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS0FBK
, 8);
3809 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS1FBK
, 8);
3810 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS2FBK
, 9);
3811 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS3FBK
, 10);
3812 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS4FBK
, 11);
3813 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS5FBK
, 12);
3814 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS6FBK
, 13);
3815 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS7FBK
, 14);
3816 rt2800_register_write(rt2x00dev
, LG_FBK_CFG0
, reg
);
3818 rt2800_register_read(rt2x00dev
, LG_FBK_CFG1
, ®
);
3819 rt2x00_set_field32(®
, LG_FBK_CFG0_CCKMCS0FBK
, 0);
3820 rt2x00_set_field32(®
, LG_FBK_CFG0_CCKMCS1FBK
, 0);
3821 rt2x00_set_field32(®
, LG_FBK_CFG0_CCKMCS2FBK
, 1);
3822 rt2x00_set_field32(®
, LG_FBK_CFG0_CCKMCS3FBK
, 2);
3823 rt2800_register_write(rt2x00dev
, LG_FBK_CFG1
, reg
);
3826 * Do not force the BA window size, we use the TXWI to set it
3828 rt2800_register_read(rt2x00dev
, AMPDU_BA_WINSIZE
, ®
);
3829 rt2x00_set_field32(®
, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE
, 0);
3830 rt2x00_set_field32(®
, AMPDU_BA_WINSIZE_FORCE_WINSIZE
, 0);
3831 rt2800_register_write(rt2x00dev
, AMPDU_BA_WINSIZE
, reg
);
3834 * We must clear the error counters.
3835 * These registers are cleared on read,
3836 * so we may pass a useless variable to store the value.
3838 rt2800_register_read(rt2x00dev
, RX_STA_CNT0
, ®
);
3839 rt2800_register_read(rt2x00dev
, RX_STA_CNT1
, ®
);
3840 rt2800_register_read(rt2x00dev
, RX_STA_CNT2
, ®
);
3841 rt2800_register_read(rt2x00dev
, TX_STA_CNT0
, ®
);
3842 rt2800_register_read(rt2x00dev
, TX_STA_CNT1
, ®
);
3843 rt2800_register_read(rt2x00dev
, TX_STA_CNT2
, ®
);
3846 * Setup leadtime for pre tbtt interrupt to 6ms
3848 rt2800_register_read(rt2x00dev
, INT_TIMER_CFG
, ®
);
3849 rt2x00_set_field32(®
, INT_TIMER_CFG_PRE_TBTT_TIMER
, 6 << 4);
3850 rt2800_register_write(rt2x00dev
, INT_TIMER_CFG
, reg
);
3853 * Set up channel statistics timer
3855 rt2800_register_read(rt2x00dev
, CH_TIME_CFG
, ®
);
3856 rt2x00_set_field32(®
, CH_TIME_CFG_EIFS_BUSY
, 1);
3857 rt2x00_set_field32(®
, CH_TIME_CFG_NAV_BUSY
, 1);
3858 rt2x00_set_field32(®
, CH_TIME_CFG_RX_BUSY
, 1);
3859 rt2x00_set_field32(®
, CH_TIME_CFG_TX_BUSY
, 1);
3860 rt2x00_set_field32(®
, CH_TIME_CFG_TMR_EN
, 1);
3861 rt2800_register_write(rt2x00dev
, CH_TIME_CFG
, reg
);
3866 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev
*rt2x00dev
)
3871 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
3872 rt2800_register_read(rt2x00dev
, MAC_STATUS_CFG
, ®
);
3873 if (!rt2x00_get_field32(reg
, MAC_STATUS_CFG_BBP_RF_BUSY
))
3876 udelay(REGISTER_BUSY_DELAY
);
3879 rt2x00_err(rt2x00dev
, "BBP/RF register access failed, aborting\n");
3883 static int rt2800_wait_bbp_ready(struct rt2x00_dev
*rt2x00dev
)
3889 * BBP was enabled after firmware was loaded,
3890 * but we need to reactivate it now.
3892 rt2800_register_write(rt2x00dev
, H2M_BBP_AGENT
, 0);
3893 rt2800_register_write(rt2x00dev
, H2M_MAILBOX_CSR
, 0);
3896 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
3897 rt2800_bbp_read(rt2x00dev
, 0, &value
);
3898 if ((value
!= 0xff) && (value
!= 0x00))
3900 udelay(REGISTER_BUSY_DELAY
);
3903 rt2x00_err(rt2x00dev
, "BBP register access failed, aborting\n");
3907 static void rt2800_bbp4_mac_if_ctrl(struct rt2x00_dev
*rt2x00dev
)
3911 rt2800_bbp_read(rt2x00dev
, 4, &value
);
3912 rt2x00_set_field8(&value
, BBP4_MAC_IF_CTRL
, 1);
3913 rt2800_bbp_write(rt2x00dev
, 4, value
);
3916 static void rt2800_init_freq_calibration(struct rt2x00_dev
*rt2x00dev
)
3918 rt2800_bbp_write(rt2x00dev
, 142, 1);
3919 rt2800_bbp_write(rt2x00dev
, 143, 57);
3922 static void rt2800_init_bbp_5592_glrt(struct rt2x00_dev
*rt2x00dev
)
3924 const u8 glrt_table
[] = {
3925 0xE0, 0x1F, 0X38, 0x32, 0x08, 0x28, 0x19, 0x0A, 0xFF, 0x00, /* 128 ~ 137 */
3926 0x16, 0x10, 0x10, 0x0B, 0x36, 0x2C, 0x26, 0x24, 0x42, 0x36, /* 138 ~ 147 */
3927 0x30, 0x2D, 0x4C, 0x46, 0x3D, 0x40, 0x3E, 0x42, 0x3D, 0x40, /* 148 ~ 157 */
3928 0X3C, 0x34, 0x2C, 0x2F, 0x3C, 0x35, 0x2E, 0x2A, 0x49, 0x41, /* 158 ~ 167 */
3929 0x36, 0x31, 0x30, 0x30, 0x0E, 0x0D, 0x28, 0x21, 0x1C, 0x16, /* 168 ~ 177 */
3930 0x50, 0x4A, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, /* 178 ~ 187 */
3931 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 188 ~ 197 */
3932 0x00, 0x00, 0x7D, 0x14, 0x32, 0x2C, 0x36, 0x4C, 0x43, 0x2C, /* 198 ~ 207 */
3933 0x2E, 0x36, 0x30, 0x6E, /* 208 ~ 211 */
3937 for (i
= 0; i
< ARRAY_SIZE(glrt_table
); i
++) {
3938 rt2800_bbp_write(rt2x00dev
, 195, 128 + i
);
3939 rt2800_bbp_write(rt2x00dev
, 196, glrt_table
[i
]);
3943 static void rt2800_init_bbp_early(struct rt2x00_dev
*rt2x00dev
)
3945 rt2800_bbp_write(rt2x00dev
, 65, 0x2C);
3946 rt2800_bbp_write(rt2x00dev
, 66, 0x38);
3947 rt2800_bbp_write(rt2x00dev
, 68, 0x0B);
3948 rt2800_bbp_write(rt2x00dev
, 69, 0x12);
3949 rt2800_bbp_write(rt2x00dev
, 70, 0x0a);
3950 rt2800_bbp_write(rt2x00dev
, 73, 0x10);
3951 rt2800_bbp_write(rt2x00dev
, 81, 0x37);
3952 rt2800_bbp_write(rt2x00dev
, 82, 0x62);
3953 rt2800_bbp_write(rt2x00dev
, 83, 0x6A);
3954 rt2800_bbp_write(rt2x00dev
, 84, 0x99);
3955 rt2800_bbp_write(rt2x00dev
, 86, 0x00);
3956 rt2800_bbp_write(rt2x00dev
, 91, 0x04);
3957 rt2800_bbp_write(rt2x00dev
, 92, 0x00);
3958 rt2800_bbp_write(rt2x00dev
, 103, 0x00);
3959 rt2800_bbp_write(rt2x00dev
, 105, 0x05);
3960 rt2800_bbp_write(rt2x00dev
, 106, 0x35);
3963 static void rt2800_init_bbp_5592(struct rt2x00_dev
*rt2x00dev
)
3969 rt2800_init_bbp_early(rt2x00dev
);
3971 rt2800_bbp_read(rt2x00dev
, 105, &value
);
3972 rt2x00_set_field8(&value
, BBP105_MLD
,
3973 rt2x00dev
->default_ant
.rx_chain_num
== 2);
3974 rt2800_bbp_write(rt2x00dev
, 105, value
);
3976 rt2800_bbp4_mac_if_ctrl(rt2x00dev
);
3978 rt2800_bbp_write(rt2x00dev
, 20, 0x06);
3979 rt2800_bbp_write(rt2x00dev
, 31, 0x08);
3980 rt2800_bbp_write(rt2x00dev
, 65, 0x2C);
3981 rt2800_bbp_write(rt2x00dev
, 68, 0xDD);
3982 rt2800_bbp_write(rt2x00dev
, 69, 0x1A);
3983 rt2800_bbp_write(rt2x00dev
, 70, 0x05);
3984 rt2800_bbp_write(rt2x00dev
, 73, 0x13);
3985 rt2800_bbp_write(rt2x00dev
, 74, 0x0F);
3986 rt2800_bbp_write(rt2x00dev
, 75, 0x4F);
3987 rt2800_bbp_write(rt2x00dev
, 76, 0x28);
3988 rt2800_bbp_write(rt2x00dev
, 77, 0x59);
3989 rt2800_bbp_write(rt2x00dev
, 84, 0x9A);
3990 rt2800_bbp_write(rt2x00dev
, 86, 0x38);
3991 rt2800_bbp_write(rt2x00dev
, 88, 0x90);
3992 rt2800_bbp_write(rt2x00dev
, 91, 0x04);
3993 rt2800_bbp_write(rt2x00dev
, 92, 0x02);
3994 rt2800_bbp_write(rt2x00dev
, 95, 0x9a);
3995 rt2800_bbp_write(rt2x00dev
, 98, 0x12);
3996 rt2800_bbp_write(rt2x00dev
, 103, 0xC0);
3997 rt2800_bbp_write(rt2x00dev
, 104, 0x92);
3998 /* FIXME BBP105 owerwrite */
3999 rt2800_bbp_write(rt2x00dev
, 105, 0x3C);
4000 rt2800_bbp_write(rt2x00dev
, 106, 0x35);
4001 rt2800_bbp_write(rt2x00dev
, 128, 0x12);
4002 rt2800_bbp_write(rt2x00dev
, 134, 0xD0);
4003 rt2800_bbp_write(rt2x00dev
, 135, 0xF6);
4004 rt2800_bbp_write(rt2x00dev
, 137, 0x0F);
4006 /* Initialize GLRT (Generalized Likehood Radio Test) */
4007 rt2800_init_bbp_5592_glrt(rt2x00dev
);
4009 rt2800_bbp4_mac_if_ctrl(rt2x00dev
);
4011 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF1
, &eeprom
);
4012 div_mode
= rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF1_ANT_DIVERSITY
);
4013 ant
= (div_mode
== 3) ? 1 : 0;
4014 rt2800_bbp_read(rt2x00dev
, 152, &value
);
4017 rt2x00_set_field8(&value
, BBP152_RX_DEFAULT_ANT
, 1);
4019 /* Auxiliary antenna */
4020 rt2x00_set_field8(&value
, BBP152_RX_DEFAULT_ANT
, 0);
4022 rt2800_bbp_write(rt2x00dev
, 152, value
);
4024 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5592
, REV_RT5592C
)) {
4025 rt2800_bbp_read(rt2x00dev
, 254, &value
);
4026 rt2x00_set_field8(&value
, BBP254_BIT7
, 1);
4027 rt2800_bbp_write(rt2x00dev
, 254, value
);
4030 rt2800_init_freq_calibration(rt2x00dev
);
4032 rt2800_bbp_write(rt2x00dev
, 84, 0x19);
4033 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5592
, REV_RT5592C
))
4034 rt2800_bbp_write(rt2x00dev
, 103, 0xc0);
4037 static int rt2800_init_bbp(struct rt2x00_dev
*rt2x00dev
)
4044 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev
) ||
4045 rt2800_wait_bbp_ready(rt2x00dev
)))
4048 if (rt2x00_rt(rt2x00dev
, RT5592
)) {
4049 rt2800_init_bbp_5592(rt2x00dev
);
4053 if (rt2x00_rt(rt2x00dev
, RT3352
)) {
4054 rt2800_bbp_write(rt2x00dev
, 3, 0x00);
4055 rt2800_bbp_write(rt2x00dev
, 4, 0x50);
4058 if (rt2x00_rt(rt2x00dev
, RT3290
) ||
4059 rt2x00_rt(rt2x00dev
, RT5390
) ||
4060 rt2x00_rt(rt2x00dev
, RT5392
))
4061 rt2800_bbp4_mac_if_ctrl(rt2x00dev
);
4063 if (rt2800_is_305x_soc(rt2x00dev
) ||
4064 rt2x00_rt(rt2x00dev
, RT3290
) ||
4065 rt2x00_rt(rt2x00dev
, RT3352
) ||
4066 rt2x00_rt(rt2x00dev
, RT3572
) ||
4067 rt2x00_rt(rt2x00dev
, RT5390
) ||
4068 rt2x00_rt(rt2x00dev
, RT5392
))
4069 rt2800_bbp_write(rt2x00dev
, 31, 0x08);
4071 if (rt2x00_rt(rt2x00dev
, RT3352
))
4072 rt2800_bbp_write(rt2x00dev
, 47, 0x48);
4074 rt2800_bbp_write(rt2x00dev
, 65, 0x2c);
4075 rt2800_bbp_write(rt2x00dev
, 66, 0x38);
4077 if (rt2x00_rt(rt2x00dev
, RT3290
) ||
4078 rt2x00_rt(rt2x00dev
, RT3352
) ||
4079 rt2x00_rt(rt2x00dev
, RT5390
) ||
4080 rt2x00_rt(rt2x00dev
, RT5392
))
4081 rt2800_bbp_write(rt2x00dev
, 68, 0x0b);
4083 if (rt2x00_rt_rev(rt2x00dev
, RT2860
, REV_RT2860C
)) {
4084 rt2800_bbp_write(rt2x00dev
, 69, 0x16);
4085 rt2800_bbp_write(rt2x00dev
, 73, 0x12);
4086 } else if (rt2x00_rt(rt2x00dev
, RT3290
) ||
4087 rt2x00_rt(rt2x00dev
, RT3352
) ||
4088 rt2x00_rt(rt2x00dev
, RT5390
) ||
4089 rt2x00_rt(rt2x00dev
, RT5392
)) {
4090 rt2800_bbp_write(rt2x00dev
, 69, 0x12);
4091 rt2800_bbp_write(rt2x00dev
, 73, 0x13);
4092 rt2800_bbp_write(rt2x00dev
, 75, 0x46);
4093 rt2800_bbp_write(rt2x00dev
, 76, 0x28);
4095 if (rt2x00_rt(rt2x00dev
, RT3290
))
4096 rt2800_bbp_write(rt2x00dev
, 77, 0x58);
4098 rt2800_bbp_write(rt2x00dev
, 77, 0x59);
4100 rt2800_bbp_write(rt2x00dev
, 69, 0x12);
4101 rt2800_bbp_write(rt2x00dev
, 73, 0x10);
4104 rt2800_bbp_write(rt2x00dev
, 70, 0x0a);
4106 if (rt2x00_rt(rt2x00dev
, RT3070
) ||
4107 rt2x00_rt(rt2x00dev
, RT3071
) ||
4108 rt2x00_rt(rt2x00dev
, RT3090
) ||
4109 rt2x00_rt(rt2x00dev
, RT3390
) ||
4110 rt2x00_rt(rt2x00dev
, RT3572
) ||
4111 rt2x00_rt(rt2x00dev
, RT5390
) ||
4112 rt2x00_rt(rt2x00dev
, RT5392
)) {
4113 rt2800_bbp_write(rt2x00dev
, 79, 0x13);
4114 rt2800_bbp_write(rt2x00dev
, 80, 0x05);
4115 rt2800_bbp_write(rt2x00dev
, 81, 0x33);
4116 } else if (rt2800_is_305x_soc(rt2x00dev
)) {
4117 rt2800_bbp_write(rt2x00dev
, 78, 0x0e);
4118 rt2800_bbp_write(rt2x00dev
, 80, 0x08);
4119 } else if (rt2x00_rt(rt2x00dev
, RT3290
)) {
4120 rt2800_bbp_write(rt2x00dev
, 74, 0x0b);
4121 rt2800_bbp_write(rt2x00dev
, 79, 0x18);
4122 rt2800_bbp_write(rt2x00dev
, 80, 0x09);
4123 rt2800_bbp_write(rt2x00dev
, 81, 0x33);
4124 } else if (rt2x00_rt(rt2x00dev
, RT3352
)) {
4125 rt2800_bbp_write(rt2x00dev
, 78, 0x0e);
4126 rt2800_bbp_write(rt2x00dev
, 80, 0x08);
4127 rt2800_bbp_write(rt2x00dev
, 81, 0x37);
4129 rt2800_bbp_write(rt2x00dev
, 81, 0x37);
4132 rt2800_bbp_write(rt2x00dev
, 82, 0x62);
4133 if (rt2x00_rt(rt2x00dev
, RT3290
) ||
4134 rt2x00_rt(rt2x00dev
, RT5390
) ||
4135 rt2x00_rt(rt2x00dev
, RT5392
))
4136 rt2800_bbp_write(rt2x00dev
, 83, 0x7a);
4138 rt2800_bbp_write(rt2x00dev
, 83, 0x6a);
4140 if (rt2x00_rt_rev(rt2x00dev
, RT2860
, REV_RT2860D
))
4141 rt2800_bbp_write(rt2x00dev
, 84, 0x19);
4142 else if (rt2x00_rt(rt2x00dev
, RT3290
) ||
4143 rt2x00_rt(rt2x00dev
, RT5390
) ||
4144 rt2x00_rt(rt2x00dev
, RT5392
))
4145 rt2800_bbp_write(rt2x00dev
, 84, 0x9a);
4147 rt2800_bbp_write(rt2x00dev
, 84, 0x99);
4149 if (rt2x00_rt(rt2x00dev
, RT3290
) ||
4150 rt2x00_rt(rt2x00dev
, RT3352
) ||
4151 rt2x00_rt(rt2x00dev
, RT5390
) ||
4152 rt2x00_rt(rt2x00dev
, RT5392
))
4153 rt2800_bbp_write(rt2x00dev
, 86, 0x38);
4155 rt2800_bbp_write(rt2x00dev
, 86, 0x00);
4157 if (rt2x00_rt(rt2x00dev
, RT3352
) ||
4158 rt2x00_rt(rt2x00dev
, RT5392
))
4159 rt2800_bbp_write(rt2x00dev
, 88, 0x90);
4161 rt2800_bbp_write(rt2x00dev
, 91, 0x04);
4163 if (rt2x00_rt(rt2x00dev
, RT3290
) ||
4164 rt2x00_rt(rt2x00dev
, RT3352
) ||
4165 rt2x00_rt(rt2x00dev
, RT5390
) ||
4166 rt2x00_rt(rt2x00dev
, RT5392
))
4167 rt2800_bbp_write(rt2x00dev
, 92, 0x02);
4169 rt2800_bbp_write(rt2x00dev
, 92, 0x00);
4171 if (rt2x00_rt(rt2x00dev
, RT5392
)) {
4172 rt2800_bbp_write(rt2x00dev
, 95, 0x9a);
4173 rt2800_bbp_write(rt2x00dev
, 98, 0x12);
4176 if (rt2x00_rt_rev_gte(rt2x00dev
, RT3070
, REV_RT3070F
) ||
4177 rt2x00_rt_rev_gte(rt2x00dev
, RT3071
, REV_RT3071E
) ||
4178 rt2x00_rt_rev_gte(rt2x00dev
, RT3090
, REV_RT3090E
) ||
4179 rt2x00_rt_rev_gte(rt2x00dev
, RT3390
, REV_RT3390E
) ||
4180 rt2x00_rt(rt2x00dev
, RT3290
) ||
4181 rt2x00_rt(rt2x00dev
, RT3352
) ||
4182 rt2x00_rt(rt2x00dev
, RT3572
) ||
4183 rt2x00_rt(rt2x00dev
, RT5390
) ||
4184 rt2x00_rt(rt2x00dev
, RT5392
) ||
4185 rt2800_is_305x_soc(rt2x00dev
))
4186 rt2800_bbp_write(rt2x00dev
, 103, 0xc0);
4188 rt2800_bbp_write(rt2x00dev
, 103, 0x00);
4190 if (rt2x00_rt(rt2x00dev
, RT3290
) ||
4191 rt2x00_rt(rt2x00dev
, RT3352
) ||
4192 rt2x00_rt(rt2x00dev
, RT5390
) ||
4193 rt2x00_rt(rt2x00dev
, RT5392
))
4194 rt2800_bbp_write(rt2x00dev
, 104, 0x92);
4196 if (rt2800_is_305x_soc(rt2x00dev
))
4197 rt2800_bbp_write(rt2x00dev
, 105, 0x01);
4198 else if (rt2x00_rt(rt2x00dev
, RT3290
))
4199 rt2800_bbp_write(rt2x00dev
, 105, 0x1c);
4200 else if (rt2x00_rt(rt2x00dev
, RT3352
))
4201 rt2800_bbp_write(rt2x00dev
, 105, 0x34);
4202 else if (rt2x00_rt(rt2x00dev
, RT5390
) ||
4203 rt2x00_rt(rt2x00dev
, RT5392
))
4204 rt2800_bbp_write(rt2x00dev
, 105, 0x3c);
4206 rt2800_bbp_write(rt2x00dev
, 105, 0x05);
4208 if (rt2x00_rt(rt2x00dev
, RT3290
) ||
4209 rt2x00_rt(rt2x00dev
, RT5390
))
4210 rt2800_bbp_write(rt2x00dev
, 106, 0x03);
4211 else if (rt2x00_rt(rt2x00dev
, RT3352
))
4212 rt2800_bbp_write(rt2x00dev
, 106, 0x05);
4213 else if (rt2x00_rt(rt2x00dev
, RT5392
))
4214 rt2800_bbp_write(rt2x00dev
, 106, 0x12);
4216 rt2800_bbp_write(rt2x00dev
, 106, 0x35);
4218 if (rt2x00_rt(rt2x00dev
, RT3352
))
4219 rt2800_bbp_write(rt2x00dev
, 120, 0x50);
4221 if (rt2x00_rt(rt2x00dev
, RT3290
) ||
4222 rt2x00_rt(rt2x00dev
, RT5390
) ||
4223 rt2x00_rt(rt2x00dev
, RT5392
))
4224 rt2800_bbp_write(rt2x00dev
, 128, 0x12);
4226 if (rt2x00_rt(rt2x00dev
, RT5392
)) {
4227 rt2800_bbp_write(rt2x00dev
, 134, 0xd0);
4228 rt2800_bbp_write(rt2x00dev
, 135, 0xf6);
4231 if (rt2x00_rt(rt2x00dev
, RT3352
))
4232 rt2800_bbp_write(rt2x00dev
, 137, 0x0f);
4234 if (rt2x00_rt(rt2x00dev
, RT3071
) ||
4235 rt2x00_rt(rt2x00dev
, RT3090
) ||
4236 rt2x00_rt(rt2x00dev
, RT3390
) ||
4237 rt2x00_rt(rt2x00dev
, RT3572
) ||
4238 rt2x00_rt(rt2x00dev
, RT5390
) ||
4239 rt2x00_rt(rt2x00dev
, RT5392
)) {
4240 rt2800_bbp_read(rt2x00dev
, 138, &value
);
4242 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF0
, &eeprom
);
4243 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_TXPATH
) == 1)
4245 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_RXPATH
) == 1)
4248 rt2800_bbp_write(rt2x00dev
, 138, value
);
4251 if (rt2x00_rt(rt2x00dev
, RT3290
)) {
4252 rt2800_bbp_write(rt2x00dev
, 67, 0x24);
4253 rt2800_bbp_write(rt2x00dev
, 143, 0x04);
4254 rt2800_bbp_write(rt2x00dev
, 142, 0x99);
4255 rt2800_bbp_write(rt2x00dev
, 150, 0x30);
4256 rt2800_bbp_write(rt2x00dev
, 151, 0x2e);
4257 rt2800_bbp_write(rt2x00dev
, 152, 0x20);
4258 rt2800_bbp_write(rt2x00dev
, 153, 0x34);
4259 rt2800_bbp_write(rt2x00dev
, 154, 0x40);
4260 rt2800_bbp_write(rt2x00dev
, 155, 0x3b);
4261 rt2800_bbp_write(rt2x00dev
, 253, 0x04);
4263 rt2800_bbp_read(rt2x00dev
, 47, &value
);
4264 rt2x00_set_field8(&value
, BBP47_TSSI_ADC6
, 1);
4265 rt2800_bbp_write(rt2x00dev
, 47, value
);
4267 /* Use 5-bit ADC for Acquisition and 8-bit ADC for data */
4268 rt2800_bbp_read(rt2x00dev
, 3, &value
);
4269 rt2x00_set_field8(&value
, BBP3_ADC_MODE_SWITCH
, 1);
4270 rt2x00_set_field8(&value
, BBP3_ADC_INIT_MODE
, 1);
4271 rt2800_bbp_write(rt2x00dev
, 3, value
);
4274 if (rt2x00_rt(rt2x00dev
, RT3352
)) {
4275 rt2800_bbp_write(rt2x00dev
, 163, 0xbd);
4276 /* Set ITxBF timeout to 0x9c40=1000msec */
4277 rt2800_bbp_write(rt2x00dev
, 179, 0x02);
4278 rt2800_bbp_write(rt2x00dev
, 180, 0x00);
4279 rt2800_bbp_write(rt2x00dev
, 182, 0x40);
4280 rt2800_bbp_write(rt2x00dev
, 180, 0x01);
4281 rt2800_bbp_write(rt2x00dev
, 182, 0x9c);
4282 rt2800_bbp_write(rt2x00dev
, 179, 0x00);
4283 /* Reprogram the inband interface to put right values in RXWI */
4284 rt2800_bbp_write(rt2x00dev
, 142, 0x04);
4285 rt2800_bbp_write(rt2x00dev
, 143, 0x3b);
4286 rt2800_bbp_write(rt2x00dev
, 142, 0x06);
4287 rt2800_bbp_write(rt2x00dev
, 143, 0xa0);
4288 rt2800_bbp_write(rt2x00dev
, 142, 0x07);
4289 rt2800_bbp_write(rt2x00dev
, 143, 0xa1);
4290 rt2800_bbp_write(rt2x00dev
, 142, 0x08);
4291 rt2800_bbp_write(rt2x00dev
, 143, 0xa2);
4293 rt2800_bbp_write(rt2x00dev
, 148, 0xc8);
4296 if (rt2x00_rt(rt2x00dev
, RT5390
) ||
4297 rt2x00_rt(rt2x00dev
, RT5392
)) {
4300 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF1
, &eeprom
);
4301 div_mode
= rt2x00_get_field16(eeprom
,
4302 EEPROM_NIC_CONF1_ANT_DIVERSITY
);
4303 ant
= (div_mode
== 3) ? 1 : 0;
4305 /* check if this is a Bluetooth combo card */
4306 if (test_bit(CAPABILITY_BT_COEXIST
, &rt2x00dev
->cap_flags
)) {
4309 rt2800_register_read(rt2x00dev
, GPIO_CTRL
, ®
);
4310 rt2x00_set_field32(®
, GPIO_CTRL_DIR3
, 0);
4311 rt2x00_set_field32(®
, GPIO_CTRL_DIR6
, 0);
4312 rt2x00_set_field32(®
, GPIO_CTRL_VAL3
, 0);
4313 rt2x00_set_field32(®
, GPIO_CTRL_VAL6
, 0);
4315 rt2x00_set_field32(®
, GPIO_CTRL_VAL3
, 1);
4317 rt2x00_set_field32(®
, GPIO_CTRL_VAL6
, 1);
4318 rt2800_register_write(rt2x00dev
, GPIO_CTRL
, reg
);
4321 /* This chip has hardware antenna diversity*/
4322 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390R
)) {
4323 rt2800_bbp_write(rt2x00dev
, 150, 0); /* Disable Antenna Software OFDM */
4324 rt2800_bbp_write(rt2x00dev
, 151, 0); /* Disable Antenna Software CCK */
4325 rt2800_bbp_write(rt2x00dev
, 154, 0); /* Clear previously selected antenna */
4328 rt2800_bbp_read(rt2x00dev
, 152, &value
);
4330 rt2x00_set_field8(&value
, BBP152_RX_DEFAULT_ANT
, 1);
4332 rt2x00_set_field8(&value
, BBP152_RX_DEFAULT_ANT
, 0);
4333 rt2800_bbp_write(rt2x00dev
, 152, value
);
4335 rt2800_init_freq_calibration(rt2x00dev
);
4338 for (i
= 0; i
< EEPROM_BBP_SIZE
; i
++) {
4339 rt2x00_eeprom_read(rt2x00dev
, EEPROM_BBP_START
+ i
, &eeprom
);
4341 if (eeprom
!= 0xffff && eeprom
!= 0x0000) {
4342 reg_id
= rt2x00_get_field16(eeprom
, EEPROM_BBP_REG_ID
);
4343 value
= rt2x00_get_field16(eeprom
, EEPROM_BBP_VALUE
);
4344 rt2800_bbp_write(rt2x00dev
, reg_id
, value
);
4351 static void rt2800_led_open_drain_enable(struct rt2x00_dev
*rt2x00dev
)
4355 rt2800_register_read(rt2x00dev
, OPT_14_CSR
, ®
);
4356 rt2x00_set_field32(®
, OPT_14_CSR_BIT0
, 1);
4357 rt2800_register_write(rt2x00dev
, OPT_14_CSR
, reg
);
4360 static u8
rt2800_init_rx_filter(struct rt2x00_dev
*rt2x00dev
, bool bw40
,
4369 u8 rfcsr24
= (bw40
) ? 0x27 : 0x07;
4371 rt2800_rfcsr_write(rt2x00dev
, 24, rfcsr24
);
4373 rt2800_bbp_read(rt2x00dev
, 4, &bbp
);
4374 rt2x00_set_field8(&bbp
, BBP4_BANDWIDTH
, 2 * bw40
);
4375 rt2800_bbp_write(rt2x00dev
, 4, bbp
);
4377 rt2800_rfcsr_read(rt2x00dev
, 31, &rfcsr
);
4378 rt2x00_set_field8(&rfcsr
, RFCSR31_RX_H20M
, bw40
);
4379 rt2800_rfcsr_write(rt2x00dev
, 31, rfcsr
);
4381 rt2800_rfcsr_read(rt2x00dev
, 22, &rfcsr
);
4382 rt2x00_set_field8(&rfcsr
, RFCSR22_BASEBAND_LOOPBACK
, 1);
4383 rt2800_rfcsr_write(rt2x00dev
, 22, rfcsr
);
4386 * Set power & frequency of passband test tone
4388 rt2800_bbp_write(rt2x00dev
, 24, 0);
4390 for (i
= 0; i
< 100; i
++) {
4391 rt2800_bbp_write(rt2x00dev
, 25, 0x90);
4394 rt2800_bbp_read(rt2x00dev
, 55, &passband
);
4400 * Set power & frequency of stopband test tone
4402 rt2800_bbp_write(rt2x00dev
, 24, 0x06);
4404 for (i
= 0; i
< 100; i
++) {
4405 rt2800_bbp_write(rt2x00dev
, 25, 0x90);
4408 rt2800_bbp_read(rt2x00dev
, 55, &stopband
);
4410 if ((passband
- stopband
) <= filter_target
) {
4412 overtuned
+= ((passband
- stopband
) == filter_target
);
4416 rt2800_rfcsr_write(rt2x00dev
, 24, rfcsr24
);
4419 rfcsr24
-= !!overtuned
;
4421 rt2800_rfcsr_write(rt2x00dev
, 24, rfcsr24
);
4425 static void rt2800_rf_init_calibration(struct rt2x00_dev
*rt2x00dev
,
4426 const unsigned int rf_reg
)
4430 rt2800_rfcsr_read(rt2x00dev
, rf_reg
, &rfcsr
);
4431 rt2x00_set_field8(&rfcsr
, FIELD8(0x80), 1);
4432 rt2800_rfcsr_write(rt2x00dev
, rf_reg
, rfcsr
);
4434 rt2x00_set_field8(&rfcsr
, FIELD8(0x80), 0);
4435 rt2800_rfcsr_write(rt2x00dev
, rf_reg
, rfcsr
);
4438 static void rt2800_rx_filter_calibration(struct rt2x00_dev
*rt2x00dev
)
4440 struct rt2800_drv_data
*drv_data
= rt2x00dev
->drv_data
;
4446 * TODO: sync filter_tgt values with vendor driver
4448 if (rt2x00_rt(rt2x00dev
, RT3070
)) {
4449 filter_tgt_bw20
= 0x16;
4450 filter_tgt_bw40
= 0x19;
4452 filter_tgt_bw20
= 0x13;
4453 filter_tgt_bw40
= 0x15;
4456 drv_data
->calibration_bw20
=
4457 rt2800_init_rx_filter(rt2x00dev
, false, filter_tgt_bw20
);
4458 drv_data
->calibration_bw40
=
4459 rt2800_init_rx_filter(rt2x00dev
, true, filter_tgt_bw40
);
4462 * Save BBP 25 & 26 values for later use in channel switching (for 3052)
4464 rt2800_bbp_read(rt2x00dev
, 25, &drv_data
->bbp25
);
4465 rt2800_bbp_read(rt2x00dev
, 26, &drv_data
->bbp26
);
4468 * Set back to initial state
4470 rt2800_bbp_write(rt2x00dev
, 24, 0);
4472 rt2800_rfcsr_read(rt2x00dev
, 22, &rfcsr
);
4473 rt2x00_set_field8(&rfcsr
, RFCSR22_BASEBAND_LOOPBACK
, 0);
4474 rt2800_rfcsr_write(rt2x00dev
, 22, rfcsr
);
4477 * Set BBP back to BW20
4479 rt2800_bbp_read(rt2x00dev
, 4, &bbp
);
4480 rt2x00_set_field8(&bbp
, BBP4_BANDWIDTH
, 0);
4481 rt2800_bbp_write(rt2x00dev
, 4, bbp
);
4484 static void rt2800_normal_mode_setup_3xxx(struct rt2x00_dev
*rt2x00dev
)
4486 struct rt2800_drv_data
*drv_data
= rt2x00dev
->drv_data
;
4487 u8 min_gain
, rfcsr
, bbp
;
4490 rt2800_rfcsr_read(rt2x00dev
, 17, &rfcsr
);
4492 rt2x00_set_field8(&rfcsr
, RFCSR17_TX_LO1_EN
, 0);
4493 if (rt2x00_rt(rt2x00dev
, RT3070
) ||
4494 rt2x00_rt_rev_lt(rt2x00dev
, RT3071
, REV_RT3071E
) ||
4495 rt2x00_rt_rev_lt(rt2x00dev
, RT3090
, REV_RT3090E
) ||
4496 rt2x00_rt_rev_lt(rt2x00dev
, RT3390
, REV_RT3390E
)) {
4497 if (!test_bit(CAPABILITY_EXTERNAL_LNA_BG
, &rt2x00dev
->cap_flags
))
4498 rt2x00_set_field8(&rfcsr
, RFCSR17_R
, 1);
4501 min_gain
= rt2x00_rt(rt2x00dev
, RT3070
) ? 1 : 2;
4502 if (drv_data
->txmixer_gain_24g
>= min_gain
) {
4503 rt2x00_set_field8(&rfcsr
, RFCSR17_TXMIXER_GAIN
,
4504 drv_data
->txmixer_gain_24g
);
4507 rt2800_rfcsr_write(rt2x00dev
, 17, rfcsr
);
4509 if (rt2x00_rt(rt2x00dev
, RT3090
)) {
4510 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
4511 rt2800_bbp_read(rt2x00dev
, 138, &bbp
);
4512 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF0
, &eeprom
);
4513 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_RXPATH
) == 1)
4514 rt2x00_set_field8(&bbp
, BBP138_RX_ADC1
, 0);
4515 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_TXPATH
) == 1)
4516 rt2x00_set_field8(&bbp
, BBP138_TX_DAC1
, 1);
4517 rt2800_bbp_write(rt2x00dev
, 138, bbp
);
4520 if (rt2x00_rt(rt2x00dev
, RT3070
)) {
4521 rt2800_rfcsr_read(rt2x00dev
, 27, &rfcsr
);
4522 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070F
))
4523 rt2x00_set_field8(&rfcsr
, RFCSR27_R1
, 3);
4525 rt2x00_set_field8(&rfcsr
, RFCSR27_R1
, 0);
4526 rt2x00_set_field8(&rfcsr
, RFCSR27_R2
, 0);
4527 rt2x00_set_field8(&rfcsr
, RFCSR27_R3
, 0);
4528 rt2x00_set_field8(&rfcsr
, RFCSR27_R4
, 0);
4529 rt2800_rfcsr_write(rt2x00dev
, 27, rfcsr
);
4530 } else if (rt2x00_rt(rt2x00dev
, RT3071
) ||
4531 rt2x00_rt(rt2x00dev
, RT3090
) ||
4532 rt2x00_rt(rt2x00dev
, RT3390
)) {
4533 rt2800_rfcsr_read(rt2x00dev
, 1, &rfcsr
);
4534 rt2x00_set_field8(&rfcsr
, RFCSR1_RF_BLOCK_EN
, 1);
4535 rt2x00_set_field8(&rfcsr
, RFCSR1_RX0_PD
, 0);
4536 rt2x00_set_field8(&rfcsr
, RFCSR1_TX0_PD
, 0);
4537 rt2x00_set_field8(&rfcsr
, RFCSR1_RX1_PD
, 1);
4538 rt2x00_set_field8(&rfcsr
, RFCSR1_TX1_PD
, 1);
4539 rt2800_rfcsr_write(rt2x00dev
, 1, rfcsr
);
4541 rt2800_rfcsr_read(rt2x00dev
, 15, &rfcsr
);
4542 rt2x00_set_field8(&rfcsr
, RFCSR15_TX_LO2_EN
, 0);
4543 rt2800_rfcsr_write(rt2x00dev
, 15, rfcsr
);
4545 rt2800_rfcsr_read(rt2x00dev
, 20, &rfcsr
);
4546 rt2x00_set_field8(&rfcsr
, RFCSR20_RX_LO1_EN
, 0);
4547 rt2800_rfcsr_write(rt2x00dev
, 20, rfcsr
);
4549 rt2800_rfcsr_read(rt2x00dev
, 21, &rfcsr
);
4550 rt2x00_set_field8(&rfcsr
, RFCSR21_RX_LO2_EN
, 0);
4551 rt2800_rfcsr_write(rt2x00dev
, 21, rfcsr
);
4555 static void rt2800_normal_mode_setup_5xxx(struct rt2x00_dev
*rt2x00dev
)
4560 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
4561 rt2800_bbp_read(rt2x00dev
, 138, ®
);
4562 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF0
, &eeprom
);
4563 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_RXPATH
) == 1)
4564 rt2x00_set_field8(®
, BBP138_RX_ADC1
, 0);
4565 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_TXPATH
) == 1)
4566 rt2x00_set_field8(®
, BBP138_TX_DAC1
, 1);
4567 rt2800_bbp_write(rt2x00dev
, 138, reg
);
4569 rt2800_rfcsr_read(rt2x00dev
, 38, ®
);
4570 rt2x00_set_field8(®
, RFCSR38_RX_LO1_EN
, 0);
4571 rt2800_rfcsr_write(rt2x00dev
, 38, reg
);
4573 rt2800_rfcsr_read(rt2x00dev
, 39, ®
);
4574 rt2x00_set_field8(®
, RFCSR39_RX_LO2_EN
, 0);
4575 rt2800_rfcsr_write(rt2x00dev
, 39, reg
);
4577 rt2800_bbp4_mac_if_ctrl(rt2x00dev
);
4579 rt2800_rfcsr_read(rt2x00dev
, 30, ®
);
4580 rt2x00_set_field8(®
, RFCSR30_RX_VCM
, 2);
4581 rt2800_rfcsr_write(rt2x00dev
, 30, reg
);
4584 static void rt2800_init_rfcsr_305x_soc(struct rt2x00_dev
*rt2x00dev
)
4586 rt2800_rf_init_calibration(rt2x00dev
, 30);
4588 rt2800_rfcsr_write(rt2x00dev
, 0, 0x50);
4589 rt2800_rfcsr_write(rt2x00dev
, 1, 0x01);
4590 rt2800_rfcsr_write(rt2x00dev
, 2, 0xf7);
4591 rt2800_rfcsr_write(rt2x00dev
, 3, 0x75);
4592 rt2800_rfcsr_write(rt2x00dev
, 4, 0x40);
4593 rt2800_rfcsr_write(rt2x00dev
, 5, 0x03);
4594 rt2800_rfcsr_write(rt2x00dev
, 6, 0x02);
4595 rt2800_rfcsr_write(rt2x00dev
, 7, 0x50);
4596 rt2800_rfcsr_write(rt2x00dev
, 8, 0x39);
4597 rt2800_rfcsr_write(rt2x00dev
, 9, 0x0f);
4598 rt2800_rfcsr_write(rt2x00dev
, 10, 0x60);
4599 rt2800_rfcsr_write(rt2x00dev
, 11, 0x21);
4600 rt2800_rfcsr_write(rt2x00dev
, 12, 0x75);
4601 rt2800_rfcsr_write(rt2x00dev
, 13, 0x75);
4602 rt2800_rfcsr_write(rt2x00dev
, 14, 0x90);
4603 rt2800_rfcsr_write(rt2x00dev
, 15, 0x58);
4604 rt2800_rfcsr_write(rt2x00dev
, 16, 0xb3);
4605 rt2800_rfcsr_write(rt2x00dev
, 17, 0x92);
4606 rt2800_rfcsr_write(rt2x00dev
, 18, 0x2c);
4607 rt2800_rfcsr_write(rt2x00dev
, 19, 0x02);
4608 rt2800_rfcsr_write(rt2x00dev
, 20, 0xba);
4609 rt2800_rfcsr_write(rt2x00dev
, 21, 0xdb);
4610 rt2800_rfcsr_write(rt2x00dev
, 22, 0x00);
4611 rt2800_rfcsr_write(rt2x00dev
, 23, 0x31);
4612 rt2800_rfcsr_write(rt2x00dev
, 24, 0x08);
4613 rt2800_rfcsr_write(rt2x00dev
, 25, 0x01);
4614 rt2800_rfcsr_write(rt2x00dev
, 26, 0x25);
4615 rt2800_rfcsr_write(rt2x00dev
, 27, 0x23);
4616 rt2800_rfcsr_write(rt2x00dev
, 28, 0x13);
4617 rt2800_rfcsr_write(rt2x00dev
, 29, 0x83);
4618 rt2800_rfcsr_write(rt2x00dev
, 30, 0x00);
4619 rt2800_rfcsr_write(rt2x00dev
, 31, 0x00);
4622 static void rt2800_init_rfcsr_30xx(struct rt2x00_dev
*rt2x00dev
)
4628 /* XXX vendor driver do this only for 3070 */
4629 rt2800_rf_init_calibration(rt2x00dev
, 30);
4631 rt2800_rfcsr_write(rt2x00dev
, 4, 0x40);
4632 rt2800_rfcsr_write(rt2x00dev
, 5, 0x03);
4633 rt2800_rfcsr_write(rt2x00dev
, 6, 0x02);
4634 rt2800_rfcsr_write(rt2x00dev
, 7, 0x60);
4635 rt2800_rfcsr_write(rt2x00dev
, 9, 0x0f);
4636 rt2800_rfcsr_write(rt2x00dev
, 10, 0x41);
4637 rt2800_rfcsr_write(rt2x00dev
, 11, 0x21);
4638 rt2800_rfcsr_write(rt2x00dev
, 12, 0x7b);
4639 rt2800_rfcsr_write(rt2x00dev
, 14, 0x90);
4640 rt2800_rfcsr_write(rt2x00dev
, 15, 0x58);
4641 rt2800_rfcsr_write(rt2x00dev
, 16, 0xb3);
4642 rt2800_rfcsr_write(rt2x00dev
, 17, 0x92);
4643 rt2800_rfcsr_write(rt2x00dev
, 18, 0x2c);
4644 rt2800_rfcsr_write(rt2x00dev
, 19, 0x02);
4645 rt2800_rfcsr_write(rt2x00dev
, 20, 0xba);
4646 rt2800_rfcsr_write(rt2x00dev
, 21, 0xdb);
4647 rt2800_rfcsr_write(rt2x00dev
, 24, 0x16);
4648 rt2800_rfcsr_write(rt2x00dev
, 25, 0x01);
4649 rt2800_rfcsr_write(rt2x00dev
, 29, 0x1f);
4651 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070F
)) {
4652 rt2800_register_read(rt2x00dev
, LDO_CFG0
, ®
);
4653 rt2x00_set_field32(®
, LDO_CFG0_BGSEL
, 1);
4654 rt2x00_set_field32(®
, LDO_CFG0_LDO_CORE_VLEVEL
, 3);
4655 rt2800_register_write(rt2x00dev
, LDO_CFG0
, reg
);
4656 } else if (rt2x00_rt(rt2x00dev
, RT3071
) ||
4657 rt2x00_rt(rt2x00dev
, RT3090
)) {
4658 rt2800_rfcsr_write(rt2x00dev
, 31, 0x14);
4660 rt2800_rfcsr_read(rt2x00dev
, 6, &rfcsr
);
4661 rt2x00_set_field8(&rfcsr
, RFCSR6_R2
, 1);
4662 rt2800_rfcsr_write(rt2x00dev
, 6, rfcsr
);
4664 rt2800_register_read(rt2x00dev
, LDO_CFG0
, ®
);
4665 rt2x00_set_field32(®
, LDO_CFG0_BGSEL
, 1);
4666 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3071
, REV_RT3071E
) ||
4667 rt2x00_rt_rev_lt(rt2x00dev
, RT3090
, REV_RT3090E
)) {
4668 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF1
, &eeprom
);
4669 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF1_DAC_TEST
))
4670 rt2x00_set_field32(®
, LDO_CFG0_LDO_CORE_VLEVEL
, 3);
4672 rt2x00_set_field32(®
, LDO_CFG0_LDO_CORE_VLEVEL
, 0);
4674 rt2800_register_write(rt2x00dev
, LDO_CFG0
, reg
);
4676 rt2800_register_read(rt2x00dev
, GPIO_SWITCH
, ®
);
4677 rt2x00_set_field32(®
, GPIO_SWITCH_5
, 0);
4678 rt2800_register_write(rt2x00dev
, GPIO_SWITCH
, reg
);
4681 rt2800_rx_filter_calibration(rt2x00dev
);
4683 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070F
) ||
4684 rt2x00_rt_rev_lt(rt2x00dev
, RT3071
, REV_RT3071E
) ||
4685 rt2x00_rt_rev_lt(rt2x00dev
, RT3090
, REV_RT3090E
))
4686 rt2800_rfcsr_write(rt2x00dev
, 27, 0x03);
4688 rt2800_led_open_drain_enable(rt2x00dev
);
4689 rt2800_normal_mode_setup_3xxx(rt2x00dev
);
4692 static void rt2800_init_rfcsr_3290(struct rt2x00_dev
*rt2x00dev
)
4696 rt2800_rf_init_calibration(rt2x00dev
, 2);
4698 rt2800_rfcsr_write(rt2x00dev
, 1, 0x0f);
4699 rt2800_rfcsr_write(rt2x00dev
, 2, 0x80);
4700 rt2800_rfcsr_write(rt2x00dev
, 3, 0x08);
4701 rt2800_rfcsr_write(rt2x00dev
, 4, 0x00);
4702 rt2800_rfcsr_write(rt2x00dev
, 6, 0xa0);
4703 rt2800_rfcsr_write(rt2x00dev
, 8, 0xf3);
4704 rt2800_rfcsr_write(rt2x00dev
, 9, 0x02);
4705 rt2800_rfcsr_write(rt2x00dev
, 10, 0x53);
4706 rt2800_rfcsr_write(rt2x00dev
, 11, 0x4a);
4707 rt2800_rfcsr_write(rt2x00dev
, 12, 0x46);
4708 rt2800_rfcsr_write(rt2x00dev
, 13, 0x9f);
4709 rt2800_rfcsr_write(rt2x00dev
, 18, 0x02);
4710 rt2800_rfcsr_write(rt2x00dev
, 22, 0x20);
4711 rt2800_rfcsr_write(rt2x00dev
, 25, 0x83);
4712 rt2800_rfcsr_write(rt2x00dev
, 26, 0x82);
4713 rt2800_rfcsr_write(rt2x00dev
, 27, 0x09);
4714 rt2800_rfcsr_write(rt2x00dev
, 29, 0x10);
4715 rt2800_rfcsr_write(rt2x00dev
, 30, 0x10);
4716 rt2800_rfcsr_write(rt2x00dev
, 31, 0x80);
4717 rt2800_rfcsr_write(rt2x00dev
, 32, 0x80);
4718 rt2800_rfcsr_write(rt2x00dev
, 33, 0x00);
4719 rt2800_rfcsr_write(rt2x00dev
, 34, 0x05);
4720 rt2800_rfcsr_write(rt2x00dev
, 35, 0x12);
4721 rt2800_rfcsr_write(rt2x00dev
, 36, 0x00);
4722 rt2800_rfcsr_write(rt2x00dev
, 38, 0x85);
4723 rt2800_rfcsr_write(rt2x00dev
, 39, 0x1b);
4724 rt2800_rfcsr_write(rt2x00dev
, 40, 0x0b);
4725 rt2800_rfcsr_write(rt2x00dev
, 41, 0xbb);
4726 rt2800_rfcsr_write(rt2x00dev
, 42, 0xd5);
4727 rt2800_rfcsr_write(rt2x00dev
, 43, 0x7b);
4728 rt2800_rfcsr_write(rt2x00dev
, 44, 0x0e);
4729 rt2800_rfcsr_write(rt2x00dev
, 45, 0xa2);
4730 rt2800_rfcsr_write(rt2x00dev
, 46, 0x73);
4731 rt2800_rfcsr_write(rt2x00dev
, 47, 0x00);
4732 rt2800_rfcsr_write(rt2x00dev
, 48, 0x10);
4733 rt2800_rfcsr_write(rt2x00dev
, 49, 0x98);
4734 rt2800_rfcsr_write(rt2x00dev
, 52, 0x38);
4735 rt2800_rfcsr_write(rt2x00dev
, 53, 0x00);
4736 rt2800_rfcsr_write(rt2x00dev
, 54, 0x78);
4737 rt2800_rfcsr_write(rt2x00dev
, 55, 0x43);
4738 rt2800_rfcsr_write(rt2x00dev
, 56, 0x02);
4739 rt2800_rfcsr_write(rt2x00dev
, 57, 0x80);
4740 rt2800_rfcsr_write(rt2x00dev
, 58, 0x7f);
4741 rt2800_rfcsr_write(rt2x00dev
, 59, 0x09);
4742 rt2800_rfcsr_write(rt2x00dev
, 60, 0x45);
4743 rt2800_rfcsr_write(rt2x00dev
, 61, 0xc1);
4745 rt2800_rfcsr_read(rt2x00dev
, 29, &rfcsr
);
4746 rt2x00_set_field8(&rfcsr
, RFCSR29_RSSI_GAIN
, 3);
4747 rt2800_rfcsr_write(rt2x00dev
, 29, rfcsr
);
4749 rt2800_led_open_drain_enable(rt2x00dev
);
4750 rt2800_normal_mode_setup_3xxx(rt2x00dev
);
4753 static void rt2800_init_rfcsr_3352(struct rt2x00_dev
*rt2x00dev
)
4755 rt2800_rf_init_calibration(rt2x00dev
, 30);
4757 rt2800_rfcsr_write(rt2x00dev
, 0, 0xf0);
4758 rt2800_rfcsr_write(rt2x00dev
, 1, 0x23);
4759 rt2800_rfcsr_write(rt2x00dev
, 2, 0x50);
4760 rt2800_rfcsr_write(rt2x00dev
, 3, 0x18);
4761 rt2800_rfcsr_write(rt2x00dev
, 4, 0x00);
4762 rt2800_rfcsr_write(rt2x00dev
, 5, 0x00);
4763 rt2800_rfcsr_write(rt2x00dev
, 6, 0x33);
4764 rt2800_rfcsr_write(rt2x00dev
, 7, 0x00);
4765 rt2800_rfcsr_write(rt2x00dev
, 8, 0xf1);
4766 rt2800_rfcsr_write(rt2x00dev
, 9, 0x02);
4767 rt2800_rfcsr_write(rt2x00dev
, 10, 0xd2);
4768 rt2800_rfcsr_write(rt2x00dev
, 11, 0x42);
4769 rt2800_rfcsr_write(rt2x00dev
, 12, 0x1c);
4770 rt2800_rfcsr_write(rt2x00dev
, 13, 0x00);
4771 rt2800_rfcsr_write(rt2x00dev
, 14, 0x5a);
4772 rt2800_rfcsr_write(rt2x00dev
, 15, 0x00);
4773 rt2800_rfcsr_write(rt2x00dev
, 16, 0x01);
4774 rt2800_rfcsr_write(rt2x00dev
, 18, 0x45);
4775 rt2800_rfcsr_write(rt2x00dev
, 19, 0x02);
4776 rt2800_rfcsr_write(rt2x00dev
, 20, 0x00);
4777 rt2800_rfcsr_write(rt2x00dev
, 21, 0x00);
4778 rt2800_rfcsr_write(rt2x00dev
, 22, 0x00);
4779 rt2800_rfcsr_write(rt2x00dev
, 23, 0x00);
4780 rt2800_rfcsr_write(rt2x00dev
, 24, 0x00);
4781 rt2800_rfcsr_write(rt2x00dev
, 25, 0x80);
4782 rt2800_rfcsr_write(rt2x00dev
, 26, 0x00);
4783 rt2800_rfcsr_write(rt2x00dev
, 27, 0x03);
4784 rt2800_rfcsr_write(rt2x00dev
, 28, 0x03);
4785 rt2800_rfcsr_write(rt2x00dev
, 29, 0x00);
4786 rt2800_rfcsr_write(rt2x00dev
, 30, 0x10);
4787 rt2800_rfcsr_write(rt2x00dev
, 31, 0x80);
4788 rt2800_rfcsr_write(rt2x00dev
, 32, 0x80);
4789 rt2800_rfcsr_write(rt2x00dev
, 33, 0x00);
4790 rt2800_rfcsr_write(rt2x00dev
, 34, 0x01);
4791 rt2800_rfcsr_write(rt2x00dev
, 35, 0x03);
4792 rt2800_rfcsr_write(rt2x00dev
, 36, 0xbd);
4793 rt2800_rfcsr_write(rt2x00dev
, 37, 0x3c);
4794 rt2800_rfcsr_write(rt2x00dev
, 38, 0x5f);
4795 rt2800_rfcsr_write(rt2x00dev
, 39, 0xc5);
4796 rt2800_rfcsr_write(rt2x00dev
, 40, 0x33);
4797 rt2800_rfcsr_write(rt2x00dev
, 41, 0x5b);
4798 rt2800_rfcsr_write(rt2x00dev
, 42, 0x5b);
4799 rt2800_rfcsr_write(rt2x00dev
, 43, 0xdb);
4800 rt2800_rfcsr_write(rt2x00dev
, 44, 0xdb);
4801 rt2800_rfcsr_write(rt2x00dev
, 45, 0xdb);
4802 rt2800_rfcsr_write(rt2x00dev
, 46, 0xdd);
4803 rt2800_rfcsr_write(rt2x00dev
, 47, 0x0d);
4804 rt2800_rfcsr_write(rt2x00dev
, 48, 0x14);
4805 rt2800_rfcsr_write(rt2x00dev
, 49, 0x00);
4806 rt2800_rfcsr_write(rt2x00dev
, 50, 0x2d);
4807 rt2800_rfcsr_write(rt2x00dev
, 51, 0x7f);
4808 rt2800_rfcsr_write(rt2x00dev
, 52, 0x00);
4809 rt2800_rfcsr_write(rt2x00dev
, 53, 0x52);
4810 rt2800_rfcsr_write(rt2x00dev
, 54, 0x1b);
4811 rt2800_rfcsr_write(rt2x00dev
, 55, 0x7f);
4812 rt2800_rfcsr_write(rt2x00dev
, 56, 0x00);
4813 rt2800_rfcsr_write(rt2x00dev
, 57, 0x52);
4814 rt2800_rfcsr_write(rt2x00dev
, 58, 0x1b);
4815 rt2800_rfcsr_write(rt2x00dev
, 59, 0x00);
4816 rt2800_rfcsr_write(rt2x00dev
, 60, 0x00);
4817 rt2800_rfcsr_write(rt2x00dev
, 61, 0x00);
4818 rt2800_rfcsr_write(rt2x00dev
, 62, 0x00);
4819 rt2800_rfcsr_write(rt2x00dev
, 63, 0x00);
4821 rt2800_rx_filter_calibration(rt2x00dev
);
4822 rt2800_led_open_drain_enable(rt2x00dev
);
4823 rt2800_normal_mode_setup_3xxx(rt2x00dev
);
4826 static void rt2800_init_rfcsr_3390(struct rt2x00_dev
*rt2x00dev
)
4830 rt2800_rf_init_calibration(rt2x00dev
, 30);
4832 rt2800_rfcsr_write(rt2x00dev
, 0, 0xa0);
4833 rt2800_rfcsr_write(rt2x00dev
, 1, 0xe1);
4834 rt2800_rfcsr_write(rt2x00dev
, 2, 0xf1);
4835 rt2800_rfcsr_write(rt2x00dev
, 3, 0x62);
4836 rt2800_rfcsr_write(rt2x00dev
, 4, 0x40);
4837 rt2800_rfcsr_write(rt2x00dev
, 5, 0x8b);
4838 rt2800_rfcsr_write(rt2x00dev
, 6, 0x42);
4839 rt2800_rfcsr_write(rt2x00dev
, 7, 0x34);
4840 rt2800_rfcsr_write(rt2x00dev
, 8, 0x00);
4841 rt2800_rfcsr_write(rt2x00dev
, 9, 0xc0);
4842 rt2800_rfcsr_write(rt2x00dev
, 10, 0x61);
4843 rt2800_rfcsr_write(rt2x00dev
, 11, 0x21);
4844 rt2800_rfcsr_write(rt2x00dev
, 12, 0x3b);
4845 rt2800_rfcsr_write(rt2x00dev
, 13, 0xe0);
4846 rt2800_rfcsr_write(rt2x00dev
, 14, 0x90);
4847 rt2800_rfcsr_write(rt2x00dev
, 15, 0x53);
4848 rt2800_rfcsr_write(rt2x00dev
, 16, 0xe0);
4849 rt2800_rfcsr_write(rt2x00dev
, 17, 0x94);
4850 rt2800_rfcsr_write(rt2x00dev
, 18, 0x5c);
4851 rt2800_rfcsr_write(rt2x00dev
, 19, 0x4a);
4852 rt2800_rfcsr_write(rt2x00dev
, 20, 0xb2);
4853 rt2800_rfcsr_write(rt2x00dev
, 21, 0xf6);
4854 rt2800_rfcsr_write(rt2x00dev
, 22, 0x00);
4855 rt2800_rfcsr_write(rt2x00dev
, 23, 0x14);
4856 rt2800_rfcsr_write(rt2x00dev
, 24, 0x08);
4857 rt2800_rfcsr_write(rt2x00dev
, 25, 0x3d);
4858 rt2800_rfcsr_write(rt2x00dev
, 26, 0x85);
4859 rt2800_rfcsr_write(rt2x00dev
, 27, 0x00);
4860 rt2800_rfcsr_write(rt2x00dev
, 28, 0x41);
4861 rt2800_rfcsr_write(rt2x00dev
, 29, 0x8f);
4862 rt2800_rfcsr_write(rt2x00dev
, 30, 0x20);
4863 rt2800_rfcsr_write(rt2x00dev
, 31, 0x0f);
4865 rt2800_register_read(rt2x00dev
, GPIO_SWITCH
, ®
);
4866 rt2x00_set_field32(®
, GPIO_SWITCH_5
, 0);
4867 rt2800_register_write(rt2x00dev
, GPIO_SWITCH
, reg
);
4869 rt2800_rx_filter_calibration(rt2x00dev
);
4871 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3390
, REV_RT3390E
))
4872 rt2800_rfcsr_write(rt2x00dev
, 27, 0x03);
4874 rt2800_led_open_drain_enable(rt2x00dev
);
4875 rt2800_normal_mode_setup_3xxx(rt2x00dev
);
4878 static void rt2800_init_rfcsr_3572(struct rt2x00_dev
*rt2x00dev
)
4883 rt2800_rf_init_calibration(rt2x00dev
, 30);
4885 rt2800_rfcsr_write(rt2x00dev
, 0, 0x70);
4886 rt2800_rfcsr_write(rt2x00dev
, 1, 0x81);
4887 rt2800_rfcsr_write(rt2x00dev
, 2, 0xf1);
4888 rt2800_rfcsr_write(rt2x00dev
, 3, 0x02);
4889 rt2800_rfcsr_write(rt2x00dev
, 4, 0x4c);
4890 rt2800_rfcsr_write(rt2x00dev
, 5, 0x05);
4891 rt2800_rfcsr_write(rt2x00dev
, 6, 0x4a);
4892 rt2800_rfcsr_write(rt2x00dev
, 7, 0xd8);
4893 rt2800_rfcsr_write(rt2x00dev
, 9, 0xc3);
4894 rt2800_rfcsr_write(rt2x00dev
, 10, 0xf1);
4895 rt2800_rfcsr_write(rt2x00dev
, 11, 0xb9);
4896 rt2800_rfcsr_write(rt2x00dev
, 12, 0x70);
4897 rt2800_rfcsr_write(rt2x00dev
, 13, 0x65);
4898 rt2800_rfcsr_write(rt2x00dev
, 14, 0xa0);
4899 rt2800_rfcsr_write(rt2x00dev
, 15, 0x53);
4900 rt2800_rfcsr_write(rt2x00dev
, 16, 0x4c);
4901 rt2800_rfcsr_write(rt2x00dev
, 17, 0x23);
4902 rt2800_rfcsr_write(rt2x00dev
, 18, 0xac);
4903 rt2800_rfcsr_write(rt2x00dev
, 19, 0x93);
4904 rt2800_rfcsr_write(rt2x00dev
, 20, 0xb3);
4905 rt2800_rfcsr_write(rt2x00dev
, 21, 0xd0);
4906 rt2800_rfcsr_write(rt2x00dev
, 22, 0x00);
4907 rt2800_rfcsr_write(rt2x00dev
, 23, 0x3c);
4908 rt2800_rfcsr_write(rt2x00dev
, 24, 0x16);
4909 rt2800_rfcsr_write(rt2x00dev
, 25, 0x15);
4910 rt2800_rfcsr_write(rt2x00dev
, 26, 0x85);
4911 rt2800_rfcsr_write(rt2x00dev
, 27, 0x00);
4912 rt2800_rfcsr_write(rt2x00dev
, 28, 0x00);
4913 rt2800_rfcsr_write(rt2x00dev
, 29, 0x9b);
4914 rt2800_rfcsr_write(rt2x00dev
, 30, 0x09);
4915 rt2800_rfcsr_write(rt2x00dev
, 31, 0x10);
4917 rt2800_rfcsr_read(rt2x00dev
, 6, &rfcsr
);
4918 rt2x00_set_field8(&rfcsr
, RFCSR6_R2
, 1);
4919 rt2800_rfcsr_write(rt2x00dev
, 6, rfcsr
);
4921 rt2800_register_read(rt2x00dev
, LDO_CFG0
, ®
);
4922 rt2x00_set_field32(®
, LDO_CFG0_LDO_CORE_VLEVEL
, 3);
4923 rt2x00_set_field32(®
, LDO_CFG0_BGSEL
, 1);
4924 rt2800_register_write(rt2x00dev
, LDO_CFG0
, reg
);
4926 rt2800_register_read(rt2x00dev
, LDO_CFG0
, ®
);
4927 rt2x00_set_field32(®
, LDO_CFG0_LDO_CORE_VLEVEL
, 0);
4928 rt2x00_set_field32(®
, LDO_CFG0_BGSEL
, 1);
4929 rt2800_register_write(rt2x00dev
, LDO_CFG0
, reg
);
4931 rt2800_rx_filter_calibration(rt2x00dev
);
4932 rt2800_led_open_drain_enable(rt2x00dev
);
4933 rt2800_normal_mode_setup_3xxx(rt2x00dev
);
4936 static void rt2800_init_rfcsr_5390(struct rt2x00_dev
*rt2x00dev
)
4938 rt2800_rf_init_calibration(rt2x00dev
, 2);
4940 rt2800_rfcsr_write(rt2x00dev
, 1, 0x0f);
4941 rt2800_rfcsr_write(rt2x00dev
, 2, 0x80);
4942 rt2800_rfcsr_write(rt2x00dev
, 3, 0x88);
4943 rt2800_rfcsr_write(rt2x00dev
, 5, 0x10);
4944 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390F
))
4945 rt2800_rfcsr_write(rt2x00dev
, 6, 0xe0);
4947 rt2800_rfcsr_write(rt2x00dev
, 6, 0xa0);
4948 rt2800_rfcsr_write(rt2x00dev
, 7, 0x00);
4949 rt2800_rfcsr_write(rt2x00dev
, 10, 0x53);
4950 rt2800_rfcsr_write(rt2x00dev
, 11, 0x4a);
4951 rt2800_rfcsr_write(rt2x00dev
, 12, 0xc6);
4952 rt2800_rfcsr_write(rt2x00dev
, 13, 0x9f);
4953 rt2800_rfcsr_write(rt2x00dev
, 14, 0x00);
4954 rt2800_rfcsr_write(rt2x00dev
, 15, 0x00);
4955 rt2800_rfcsr_write(rt2x00dev
, 16, 0x00);
4956 rt2800_rfcsr_write(rt2x00dev
, 18, 0x03);
4957 rt2800_rfcsr_write(rt2x00dev
, 19, 0x00);
4959 rt2800_rfcsr_write(rt2x00dev
, 20, 0x00);
4960 rt2800_rfcsr_write(rt2x00dev
, 21, 0x00);
4961 rt2800_rfcsr_write(rt2x00dev
, 22, 0x20);
4962 rt2800_rfcsr_write(rt2x00dev
, 23, 0x00);
4963 rt2800_rfcsr_write(rt2x00dev
, 24, 0x00);
4964 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390F
))
4965 rt2800_rfcsr_write(rt2x00dev
, 25, 0x80);
4967 rt2800_rfcsr_write(rt2x00dev
, 25, 0xc0);
4968 rt2800_rfcsr_write(rt2x00dev
, 26, 0x00);
4969 rt2800_rfcsr_write(rt2x00dev
, 27, 0x09);
4970 rt2800_rfcsr_write(rt2x00dev
, 28, 0x00);
4971 rt2800_rfcsr_write(rt2x00dev
, 29, 0x10);
4973 rt2800_rfcsr_write(rt2x00dev
, 30, 0x00);
4974 rt2800_rfcsr_write(rt2x00dev
, 31, 0x80);
4975 rt2800_rfcsr_write(rt2x00dev
, 32, 0x80);
4976 rt2800_rfcsr_write(rt2x00dev
, 33, 0x00);
4977 rt2800_rfcsr_write(rt2x00dev
, 34, 0x07);
4978 rt2800_rfcsr_write(rt2x00dev
, 35, 0x12);
4979 rt2800_rfcsr_write(rt2x00dev
, 36, 0x00);
4980 rt2800_rfcsr_write(rt2x00dev
, 37, 0x08);
4981 rt2800_rfcsr_write(rt2x00dev
, 38, 0x85);
4982 rt2800_rfcsr_write(rt2x00dev
, 39, 0x1b);
4984 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390F
))
4985 rt2800_rfcsr_write(rt2x00dev
, 40, 0x0b);
4987 rt2800_rfcsr_write(rt2x00dev
, 40, 0x4b);
4988 rt2800_rfcsr_write(rt2x00dev
, 41, 0xbb);
4989 rt2800_rfcsr_write(rt2x00dev
, 42, 0xd2);
4990 rt2800_rfcsr_write(rt2x00dev
, 43, 0x9a);
4991 rt2800_rfcsr_write(rt2x00dev
, 44, 0x0e);
4992 rt2800_rfcsr_write(rt2x00dev
, 45, 0xa2);
4993 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390F
))
4994 rt2800_rfcsr_write(rt2x00dev
, 46, 0x73);
4996 rt2800_rfcsr_write(rt2x00dev
, 46, 0x7b);
4997 rt2800_rfcsr_write(rt2x00dev
, 47, 0x00);
4998 rt2800_rfcsr_write(rt2x00dev
, 48, 0x10);
4999 rt2800_rfcsr_write(rt2x00dev
, 49, 0x94);
5001 rt2800_rfcsr_write(rt2x00dev
, 52, 0x38);
5002 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390F
))
5003 rt2800_rfcsr_write(rt2x00dev
, 53, 0x00);
5005 rt2800_rfcsr_write(rt2x00dev
, 53, 0x84);
5006 rt2800_rfcsr_write(rt2x00dev
, 54, 0x78);
5007 rt2800_rfcsr_write(rt2x00dev
, 55, 0x44);
5008 rt2800_rfcsr_write(rt2x00dev
, 56, 0x22);
5009 rt2800_rfcsr_write(rt2x00dev
, 57, 0x80);
5010 rt2800_rfcsr_write(rt2x00dev
, 58, 0x7f);
5011 rt2800_rfcsr_write(rt2x00dev
, 59, 0x63);
5013 rt2800_rfcsr_write(rt2x00dev
, 60, 0x45);
5014 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390F
))
5015 rt2800_rfcsr_write(rt2x00dev
, 61, 0xd1);
5017 rt2800_rfcsr_write(rt2x00dev
, 61, 0xdd);
5018 rt2800_rfcsr_write(rt2x00dev
, 62, 0x00);
5019 rt2800_rfcsr_write(rt2x00dev
, 63, 0x00);
5021 rt2800_normal_mode_setup_5xxx(rt2x00dev
);
5023 rt2800_led_open_drain_enable(rt2x00dev
);
5026 static void rt2800_init_rfcsr_5392(struct rt2x00_dev
*rt2x00dev
)
5028 rt2800_rf_init_calibration(rt2x00dev
, 2);
5030 rt2800_rfcsr_write(rt2x00dev
, 1, 0x17);
5031 rt2800_rfcsr_write(rt2x00dev
, 2, 0x80);
5032 rt2800_rfcsr_write(rt2x00dev
, 3, 0x88);
5033 rt2800_rfcsr_write(rt2x00dev
, 5, 0x10);
5034 rt2800_rfcsr_write(rt2x00dev
, 6, 0xe0);
5035 rt2800_rfcsr_write(rt2x00dev
, 7, 0x00);
5036 rt2800_rfcsr_write(rt2x00dev
, 10, 0x53);
5037 rt2800_rfcsr_write(rt2x00dev
, 11, 0x4a);
5038 rt2800_rfcsr_write(rt2x00dev
, 12, 0x46);
5039 rt2800_rfcsr_write(rt2x00dev
, 13, 0x9f);
5040 rt2800_rfcsr_write(rt2x00dev
, 14, 0x00);
5041 rt2800_rfcsr_write(rt2x00dev
, 15, 0x00);
5042 rt2800_rfcsr_write(rt2x00dev
, 16, 0x00);
5043 rt2800_rfcsr_write(rt2x00dev
, 18, 0x03);
5044 rt2800_rfcsr_write(rt2x00dev
, 19, 0x4d);
5045 rt2800_rfcsr_write(rt2x00dev
, 20, 0x00);
5046 rt2800_rfcsr_write(rt2x00dev
, 21, 0x8d);
5047 rt2800_rfcsr_write(rt2x00dev
, 22, 0x20);
5048 rt2800_rfcsr_write(rt2x00dev
, 23, 0x0b);
5049 rt2800_rfcsr_write(rt2x00dev
, 24, 0x44);
5050 rt2800_rfcsr_write(rt2x00dev
, 25, 0x80);
5051 rt2800_rfcsr_write(rt2x00dev
, 26, 0x82);
5052 rt2800_rfcsr_write(rt2x00dev
, 27, 0x09);
5053 rt2800_rfcsr_write(rt2x00dev
, 28, 0x00);
5054 rt2800_rfcsr_write(rt2x00dev
, 29, 0x10);
5055 rt2800_rfcsr_write(rt2x00dev
, 30, 0x10);
5056 rt2800_rfcsr_write(rt2x00dev
, 31, 0x80);
5057 rt2800_rfcsr_write(rt2x00dev
, 32, 0x20);
5058 rt2800_rfcsr_write(rt2x00dev
, 33, 0xC0);
5059 rt2800_rfcsr_write(rt2x00dev
, 34, 0x07);
5060 rt2800_rfcsr_write(rt2x00dev
, 35, 0x12);
5061 rt2800_rfcsr_write(rt2x00dev
, 36, 0x00);
5062 rt2800_rfcsr_write(rt2x00dev
, 37, 0x08);
5063 rt2800_rfcsr_write(rt2x00dev
, 38, 0x89);
5064 rt2800_rfcsr_write(rt2x00dev
, 39, 0x1b);
5065 rt2800_rfcsr_write(rt2x00dev
, 40, 0x0f);
5066 rt2800_rfcsr_write(rt2x00dev
, 41, 0xbb);
5067 rt2800_rfcsr_write(rt2x00dev
, 42, 0xd5);
5068 rt2800_rfcsr_write(rt2x00dev
, 43, 0x9b);
5069 rt2800_rfcsr_write(rt2x00dev
, 44, 0x0e);
5070 rt2800_rfcsr_write(rt2x00dev
, 45, 0xa2);
5071 rt2800_rfcsr_write(rt2x00dev
, 46, 0x73);
5072 rt2800_rfcsr_write(rt2x00dev
, 47, 0x0c);
5073 rt2800_rfcsr_write(rt2x00dev
, 48, 0x10);
5074 rt2800_rfcsr_write(rt2x00dev
, 49, 0x94);
5075 rt2800_rfcsr_write(rt2x00dev
, 50, 0x94);
5076 rt2800_rfcsr_write(rt2x00dev
, 51, 0x3a);
5077 rt2800_rfcsr_write(rt2x00dev
, 52, 0x48);
5078 rt2800_rfcsr_write(rt2x00dev
, 53, 0x44);
5079 rt2800_rfcsr_write(rt2x00dev
, 54, 0x38);
5080 rt2800_rfcsr_write(rt2x00dev
, 55, 0x43);
5081 rt2800_rfcsr_write(rt2x00dev
, 56, 0xa1);
5082 rt2800_rfcsr_write(rt2x00dev
, 57, 0x00);
5083 rt2800_rfcsr_write(rt2x00dev
, 58, 0x39);
5084 rt2800_rfcsr_write(rt2x00dev
, 59, 0x07);
5085 rt2800_rfcsr_write(rt2x00dev
, 60, 0x45);
5086 rt2800_rfcsr_write(rt2x00dev
, 61, 0x91);
5087 rt2800_rfcsr_write(rt2x00dev
, 62, 0x39);
5088 rt2800_rfcsr_write(rt2x00dev
, 63, 0x07);
5090 rt2800_normal_mode_setup_5xxx(rt2x00dev
);
5092 rt2800_led_open_drain_enable(rt2x00dev
);
5095 static void rt2800_init_rfcsr_5592(struct rt2x00_dev
*rt2x00dev
)
5097 rt2800_rf_init_calibration(rt2x00dev
, 30);
5099 rt2800_rfcsr_write(rt2x00dev
, 1, 0x3F);
5100 rt2800_rfcsr_write(rt2x00dev
, 3, 0x08);
5101 rt2800_rfcsr_write(rt2x00dev
, 3, 0x08);
5102 rt2800_rfcsr_write(rt2x00dev
, 5, 0x10);
5103 rt2800_rfcsr_write(rt2x00dev
, 6, 0xE4);
5104 rt2800_rfcsr_write(rt2x00dev
, 7, 0x00);
5105 rt2800_rfcsr_write(rt2x00dev
, 14, 0x00);
5106 rt2800_rfcsr_write(rt2x00dev
, 15, 0x00);
5107 rt2800_rfcsr_write(rt2x00dev
, 16, 0x00);
5108 rt2800_rfcsr_write(rt2x00dev
, 18, 0x03);
5109 rt2800_rfcsr_write(rt2x00dev
, 19, 0x4D);
5110 rt2800_rfcsr_write(rt2x00dev
, 20, 0x10);
5111 rt2800_rfcsr_write(rt2x00dev
, 21, 0x8D);
5112 rt2800_rfcsr_write(rt2x00dev
, 26, 0x82);
5113 rt2800_rfcsr_write(rt2x00dev
, 28, 0x00);
5114 rt2800_rfcsr_write(rt2x00dev
, 29, 0x10);
5115 rt2800_rfcsr_write(rt2x00dev
, 33, 0xC0);
5116 rt2800_rfcsr_write(rt2x00dev
, 34, 0x07);
5117 rt2800_rfcsr_write(rt2x00dev
, 35, 0x12);
5118 rt2800_rfcsr_write(rt2x00dev
, 47, 0x0C);
5119 rt2800_rfcsr_write(rt2x00dev
, 53, 0x22);
5120 rt2800_rfcsr_write(rt2x00dev
, 63, 0x07);
5122 rt2800_rfcsr_write(rt2x00dev
, 2, 0x80);
5125 rt2800_adjust_freq_offset(rt2x00dev
);
5127 /* Enable DC filter */
5128 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5592
, REV_RT5592C
))
5129 rt2800_bbp_write(rt2x00dev
, 103, 0xc0);
5131 rt2800_normal_mode_setup_5xxx(rt2x00dev
);
5133 if (rt2x00_rt_rev_lt(rt2x00dev
, RT5592
, REV_RT5592C
))
5134 rt2800_rfcsr_write(rt2x00dev
, 27, 0x03);
5136 rt2800_led_open_drain_enable(rt2x00dev
);
5139 static void rt2800_init_rfcsr(struct rt2x00_dev
*rt2x00dev
)
5141 if (rt2800_is_305x_soc(rt2x00dev
)) {
5142 rt2800_init_rfcsr_305x_soc(rt2x00dev
);
5146 switch (rt2x00dev
->chip
.rt
) {
5150 rt2800_init_rfcsr_30xx(rt2x00dev
);
5153 rt2800_init_rfcsr_3290(rt2x00dev
);
5156 rt2800_init_rfcsr_3352(rt2x00dev
);
5159 rt2800_init_rfcsr_3390(rt2x00dev
);
5162 rt2800_init_rfcsr_3572(rt2x00dev
);
5165 rt2800_init_rfcsr_5390(rt2x00dev
);
5168 rt2800_init_rfcsr_5392(rt2x00dev
);
5171 rt2800_init_rfcsr_5592(rt2x00dev
);
5176 int rt2800_enable_radio(struct rt2x00_dev
*rt2x00dev
)
5182 * Initialize all registers.
5184 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev
) ||
5185 rt2800_init_registers(rt2x00dev
)))
5189 * Send signal to firmware during boot time.
5191 rt2800_register_write(rt2x00dev
, H2M_BBP_AGENT
, 0);
5192 rt2800_register_write(rt2x00dev
, H2M_MAILBOX_CSR
, 0);
5193 if (rt2x00_is_usb(rt2x00dev
)) {
5194 rt2800_register_write(rt2x00dev
, H2M_INT_SRC
, 0);
5195 rt2800_mcu_request(rt2x00dev
, MCU_BOOT_SIGNAL
, 0, 0, 0);
5199 if (unlikely(rt2800_init_bbp(rt2x00dev
)))
5202 rt2800_init_rfcsr(rt2x00dev
);
5204 if (rt2x00_is_usb(rt2x00dev
) &&
5205 (rt2x00_rt(rt2x00dev
, RT3070
) ||
5206 rt2x00_rt(rt2x00dev
, RT3071
) ||
5207 rt2x00_rt(rt2x00dev
, RT3572
))) {
5209 rt2800_mcu_request(rt2x00dev
, MCU_CURRENT
, 0, 0, 0);
5216 rt2800_register_read(rt2x00dev
, MAC_SYS_CTRL
, ®
);
5217 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_TX
, 1);
5218 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_RX
, 0);
5219 rt2800_register_write(rt2x00dev
, MAC_SYS_CTRL
, reg
);
5223 rt2800_register_read(rt2x00dev
, WPDMA_GLO_CFG
, ®
);
5224 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_TX_DMA
, 1);
5225 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_RX_DMA
, 1);
5226 rt2x00_set_field32(®
, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE
, 2);
5227 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_WRITEBACK_DONE
, 1);
5228 rt2800_register_write(rt2x00dev
, WPDMA_GLO_CFG
, reg
);
5230 rt2800_register_read(rt2x00dev
, MAC_SYS_CTRL
, ®
);
5231 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_TX
, 1);
5232 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_RX
, 1);
5233 rt2800_register_write(rt2x00dev
, MAC_SYS_CTRL
, reg
);
5236 * Initialize LED control
5238 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LED_AG_CONF
, &word
);
5239 rt2800_mcu_request(rt2x00dev
, MCU_LED_AG_CONF
, 0xff,
5240 word
& 0xff, (word
>> 8) & 0xff);
5242 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LED_ACT_CONF
, &word
);
5243 rt2800_mcu_request(rt2x00dev
, MCU_LED_ACT_CONF
, 0xff,
5244 word
& 0xff, (word
>> 8) & 0xff);
5246 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LED_POLARITY
, &word
);
5247 rt2800_mcu_request(rt2x00dev
, MCU_LED_LED_POLARITY
, 0xff,
5248 word
& 0xff, (word
>> 8) & 0xff);
5252 EXPORT_SYMBOL_GPL(rt2800_enable_radio
);
5254 void rt2800_disable_radio(struct rt2x00_dev
*rt2x00dev
)
5258 rt2800_disable_wpdma(rt2x00dev
);
5260 /* Wait for DMA, ignore error */
5261 rt2800_wait_wpdma_ready(rt2x00dev
);
5263 rt2800_register_read(rt2x00dev
, MAC_SYS_CTRL
, ®
);
5264 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_TX
, 0);
5265 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_RX
, 0);
5266 rt2800_register_write(rt2x00dev
, MAC_SYS_CTRL
, reg
);
5268 EXPORT_SYMBOL_GPL(rt2800_disable_radio
);
5270 int rt2800_efuse_detect(struct rt2x00_dev
*rt2x00dev
)
5275 if (rt2x00_rt(rt2x00dev
, RT3290
))
5276 efuse_ctrl_reg
= EFUSE_CTRL_3290
;
5278 efuse_ctrl_reg
= EFUSE_CTRL
;
5280 rt2800_register_read(rt2x00dev
, efuse_ctrl_reg
, ®
);
5281 return rt2x00_get_field32(reg
, EFUSE_CTRL_PRESENT
);
5283 EXPORT_SYMBOL_GPL(rt2800_efuse_detect
);
5285 static void rt2800_efuse_read(struct rt2x00_dev
*rt2x00dev
, unsigned int i
)
5289 u16 efuse_data0_reg
;
5290 u16 efuse_data1_reg
;
5291 u16 efuse_data2_reg
;
5292 u16 efuse_data3_reg
;
5294 if (rt2x00_rt(rt2x00dev
, RT3290
)) {
5295 efuse_ctrl_reg
= EFUSE_CTRL_3290
;
5296 efuse_data0_reg
= EFUSE_DATA0_3290
;
5297 efuse_data1_reg
= EFUSE_DATA1_3290
;
5298 efuse_data2_reg
= EFUSE_DATA2_3290
;
5299 efuse_data3_reg
= EFUSE_DATA3_3290
;
5301 efuse_ctrl_reg
= EFUSE_CTRL
;
5302 efuse_data0_reg
= EFUSE_DATA0
;
5303 efuse_data1_reg
= EFUSE_DATA1
;
5304 efuse_data2_reg
= EFUSE_DATA2
;
5305 efuse_data3_reg
= EFUSE_DATA3
;
5307 mutex_lock(&rt2x00dev
->csr_mutex
);
5309 rt2800_register_read_lock(rt2x00dev
, efuse_ctrl_reg
, ®
);
5310 rt2x00_set_field32(®
, EFUSE_CTRL_ADDRESS_IN
, i
);
5311 rt2x00_set_field32(®
, EFUSE_CTRL_MODE
, 0);
5312 rt2x00_set_field32(®
, EFUSE_CTRL_KICK
, 1);
5313 rt2800_register_write_lock(rt2x00dev
, efuse_ctrl_reg
, reg
);
5315 /* Wait until the EEPROM has been loaded */
5316 rt2800_regbusy_read(rt2x00dev
, efuse_ctrl_reg
, EFUSE_CTRL_KICK
, ®
);
5317 /* Apparently the data is read from end to start */
5318 rt2800_register_read_lock(rt2x00dev
, efuse_data3_reg
, ®
);
5319 /* The returned value is in CPU order, but eeprom is le */
5320 *(u32
*)&rt2x00dev
->eeprom
[i
] = cpu_to_le32(reg
);
5321 rt2800_register_read_lock(rt2x00dev
, efuse_data2_reg
, ®
);
5322 *(u32
*)&rt2x00dev
->eeprom
[i
+ 2] = cpu_to_le32(reg
);
5323 rt2800_register_read_lock(rt2x00dev
, efuse_data1_reg
, ®
);
5324 *(u32
*)&rt2x00dev
->eeprom
[i
+ 4] = cpu_to_le32(reg
);
5325 rt2800_register_read_lock(rt2x00dev
, efuse_data0_reg
, ®
);
5326 *(u32
*)&rt2x00dev
->eeprom
[i
+ 6] = cpu_to_le32(reg
);
5328 mutex_unlock(&rt2x00dev
->csr_mutex
);
5331 int rt2800_read_eeprom_efuse(struct rt2x00_dev
*rt2x00dev
)
5335 for (i
= 0; i
< EEPROM_SIZE
/ sizeof(u16
); i
+= 8)
5336 rt2800_efuse_read(rt2x00dev
, i
);
5340 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse
);
5342 static int rt2800_validate_eeprom(struct rt2x00_dev
*rt2x00dev
)
5344 struct rt2800_drv_data
*drv_data
= rt2x00dev
->drv_data
;
5347 u8 default_lna_gain
;
5353 retval
= rt2800_read_eeprom(rt2x00dev
);
5358 * Start validation of the data that has been read.
5360 mac
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_MAC_ADDR_0
);
5361 if (!is_valid_ether_addr(mac
)) {
5362 eth_random_addr(mac
);
5363 rt2x00_eeprom_dbg(rt2x00dev
, "MAC: %pM\n", mac
);
5366 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF0
, &word
);
5367 if (word
== 0xffff) {
5368 rt2x00_set_field16(&word
, EEPROM_NIC_CONF0_RXPATH
, 2);
5369 rt2x00_set_field16(&word
, EEPROM_NIC_CONF0_TXPATH
, 1);
5370 rt2x00_set_field16(&word
, EEPROM_NIC_CONF0_RF_TYPE
, RF2820
);
5371 rt2x00_eeprom_write(rt2x00dev
, EEPROM_NIC_CONF0
, word
);
5372 rt2x00_eeprom_dbg(rt2x00dev
, "Antenna: 0x%04x\n", word
);
5373 } else if (rt2x00_rt(rt2x00dev
, RT2860
) ||
5374 rt2x00_rt(rt2x00dev
, RT2872
)) {
5376 * There is a max of 2 RX streams for RT28x0 series
5378 if (rt2x00_get_field16(word
, EEPROM_NIC_CONF0_RXPATH
) > 2)
5379 rt2x00_set_field16(&word
, EEPROM_NIC_CONF0_RXPATH
, 2);
5380 rt2x00_eeprom_write(rt2x00dev
, EEPROM_NIC_CONF0
, word
);
5383 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF1
, &word
);
5384 if (word
== 0xffff) {
5385 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_HW_RADIO
, 0);
5386 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC
, 0);
5387 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G
, 0);
5388 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G
, 0);
5389 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_CARDBUS_ACCEL
, 0);
5390 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_BW40M_SB_2G
, 0);
5391 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_BW40M_SB_5G
, 0);
5392 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_WPS_PBC
, 0);
5393 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_BW40M_2G
, 0);
5394 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_BW40M_5G
, 0);
5395 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA
, 0);
5396 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_ANT_DIVERSITY
, 0);
5397 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_INTERNAL_TX_ALC
, 0);
5398 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_BT_COEXIST
, 0);
5399 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_DAC_TEST
, 0);
5400 rt2x00_eeprom_write(rt2x00dev
, EEPROM_NIC_CONF1
, word
);
5401 rt2x00_eeprom_dbg(rt2x00dev
, "NIC: 0x%04x\n", word
);
5404 rt2x00_eeprom_read(rt2x00dev
, EEPROM_FREQ
, &word
);
5405 if ((word
& 0x00ff) == 0x00ff) {
5406 rt2x00_set_field16(&word
, EEPROM_FREQ_OFFSET
, 0);
5407 rt2x00_eeprom_write(rt2x00dev
, EEPROM_FREQ
, word
);
5408 rt2x00_eeprom_dbg(rt2x00dev
, "Freq: 0x%04x\n", word
);
5410 if ((word
& 0xff00) == 0xff00) {
5411 rt2x00_set_field16(&word
, EEPROM_FREQ_LED_MODE
,
5412 LED_MODE_TXRX_ACTIVITY
);
5413 rt2x00_set_field16(&word
, EEPROM_FREQ_LED_POLARITY
, 0);
5414 rt2x00_eeprom_write(rt2x00dev
, EEPROM_FREQ
, word
);
5415 rt2x00_eeprom_write(rt2x00dev
, EEPROM_LED_AG_CONF
, 0x5555);
5416 rt2x00_eeprom_write(rt2x00dev
, EEPROM_LED_ACT_CONF
, 0x2221);
5417 rt2x00_eeprom_write(rt2x00dev
, EEPROM_LED_POLARITY
, 0xa9f8);
5418 rt2x00_eeprom_dbg(rt2x00dev
, "Led Mode: 0x%04x\n", word
);
5422 * During the LNA validation we are going to use
5423 * lna0 as correct value. Note that EEPROM_LNA
5424 * is never validated.
5426 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LNA
, &word
);
5427 default_lna_gain
= rt2x00_get_field16(word
, EEPROM_LNA_A0
);
5429 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_BG
, &word
);
5430 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_BG_OFFSET0
)) > 10)
5431 rt2x00_set_field16(&word
, EEPROM_RSSI_BG_OFFSET0
, 0);
5432 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_BG_OFFSET1
)) > 10)
5433 rt2x00_set_field16(&word
, EEPROM_RSSI_BG_OFFSET1
, 0);
5434 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_BG
, word
);
5436 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TXMIXER_GAIN_BG
, &word
);
5437 if ((word
& 0x00ff) != 0x00ff) {
5438 drv_data
->txmixer_gain_24g
=
5439 rt2x00_get_field16(word
, EEPROM_TXMIXER_GAIN_BG_VAL
);
5441 drv_data
->txmixer_gain_24g
= 0;
5444 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_BG2
, &word
);
5445 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_BG2_OFFSET2
)) > 10)
5446 rt2x00_set_field16(&word
, EEPROM_RSSI_BG2_OFFSET2
, 0);
5447 if (rt2x00_get_field16(word
, EEPROM_RSSI_BG2_LNA_A1
) == 0x00 ||
5448 rt2x00_get_field16(word
, EEPROM_RSSI_BG2_LNA_A1
) == 0xff)
5449 rt2x00_set_field16(&word
, EEPROM_RSSI_BG2_LNA_A1
,
5451 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_BG2
, word
);
5453 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TXMIXER_GAIN_A
, &word
);
5454 if ((word
& 0x00ff) != 0x00ff) {
5455 drv_data
->txmixer_gain_5g
=
5456 rt2x00_get_field16(word
, EEPROM_TXMIXER_GAIN_A_VAL
);
5458 drv_data
->txmixer_gain_5g
= 0;
5461 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_A
, &word
);
5462 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_A_OFFSET0
)) > 10)
5463 rt2x00_set_field16(&word
, EEPROM_RSSI_A_OFFSET0
, 0);
5464 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_A_OFFSET1
)) > 10)
5465 rt2x00_set_field16(&word
, EEPROM_RSSI_A_OFFSET1
, 0);
5466 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_A
, word
);
5468 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_A2
, &word
);
5469 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_A2_OFFSET2
)) > 10)
5470 rt2x00_set_field16(&word
, EEPROM_RSSI_A2_OFFSET2
, 0);
5471 if (rt2x00_get_field16(word
, EEPROM_RSSI_A2_LNA_A2
) == 0x00 ||
5472 rt2x00_get_field16(word
, EEPROM_RSSI_A2_LNA_A2
) == 0xff)
5473 rt2x00_set_field16(&word
, EEPROM_RSSI_A2_LNA_A2
,
5475 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_A2
, word
);
5480 static int rt2800_init_eeprom(struct rt2x00_dev
*rt2x00dev
)
5487 * Read EEPROM word for configuration.
5489 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF0
, &eeprom
);
5492 * Identify RF chipset by EEPROM value
5493 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
5494 * RT53xx: defined in "EEPROM_CHIP_ID" field
5496 if (rt2x00_rt(rt2x00dev
, RT3290
) ||
5497 rt2x00_rt(rt2x00dev
, RT5390
) ||
5498 rt2x00_rt(rt2x00dev
, RT5392
))
5499 rt2x00_eeprom_read(rt2x00dev
, EEPROM_CHIP_ID
, &rf
);
5501 rf
= rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_RF_TYPE
);
5524 rt2x00_err(rt2x00dev
, "Invalid RF chipset 0x%04x detected\n",
5529 rt2x00_set_rf(rt2x00dev
, rf
);
5532 * Identify default antenna configuration.
5534 rt2x00dev
->default_ant
.tx_chain_num
=
5535 rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_TXPATH
);
5536 rt2x00dev
->default_ant
.rx_chain_num
=
5537 rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_RXPATH
);
5539 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF1
, &eeprom
);
5541 if (rt2x00_rt(rt2x00dev
, RT3070
) ||
5542 rt2x00_rt(rt2x00dev
, RT3090
) ||
5543 rt2x00_rt(rt2x00dev
, RT3352
) ||
5544 rt2x00_rt(rt2x00dev
, RT3390
)) {
5545 value
= rt2x00_get_field16(eeprom
,
5546 EEPROM_NIC_CONF1_ANT_DIVERSITY
);
5551 rt2x00dev
->default_ant
.tx
= ANTENNA_A
;
5552 rt2x00dev
->default_ant
.rx
= ANTENNA_A
;
5555 rt2x00dev
->default_ant
.tx
= ANTENNA_A
;
5556 rt2x00dev
->default_ant
.rx
= ANTENNA_B
;
5560 rt2x00dev
->default_ant
.tx
= ANTENNA_A
;
5561 rt2x00dev
->default_ant
.rx
= ANTENNA_A
;
5564 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390R
)) {
5565 rt2x00dev
->default_ant
.tx
= ANTENNA_HW_DIVERSITY
; /* Unused */
5566 rt2x00dev
->default_ant
.rx
= ANTENNA_HW_DIVERSITY
; /* Unused */
5570 * Determine external LNA informations.
5572 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G
))
5573 __set_bit(CAPABILITY_EXTERNAL_LNA_A
, &rt2x00dev
->cap_flags
);
5574 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G
))
5575 __set_bit(CAPABILITY_EXTERNAL_LNA_BG
, &rt2x00dev
->cap_flags
);
5578 * Detect if this device has an hardware controlled radio.
5580 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF1_HW_RADIO
))
5581 __set_bit(CAPABILITY_HW_BUTTON
, &rt2x00dev
->cap_flags
);
5584 * Detect if this device has Bluetooth co-existence.
5586 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF1_BT_COEXIST
))
5587 __set_bit(CAPABILITY_BT_COEXIST
, &rt2x00dev
->cap_flags
);
5590 * Read frequency offset and RF programming sequence.
5592 rt2x00_eeprom_read(rt2x00dev
, EEPROM_FREQ
, &eeprom
);
5593 rt2x00dev
->freq_offset
= rt2x00_get_field16(eeprom
, EEPROM_FREQ_OFFSET
);
5596 * Store led settings, for correct led behaviour.
5598 #ifdef CONFIG_RT2X00_LIB_LEDS
5599 rt2800_init_led(rt2x00dev
, &rt2x00dev
->led_radio
, LED_TYPE_RADIO
);
5600 rt2800_init_led(rt2x00dev
, &rt2x00dev
->led_assoc
, LED_TYPE_ASSOC
);
5601 rt2800_init_led(rt2x00dev
, &rt2x00dev
->led_qual
, LED_TYPE_QUALITY
);
5603 rt2x00dev
->led_mcu_reg
= eeprom
;
5604 #endif /* CONFIG_RT2X00_LIB_LEDS */
5607 * Check if support EIRP tx power limit feature.
5609 rt2x00_eeprom_read(rt2x00dev
, EEPROM_EIRP_MAX_TX_POWER
, &eeprom
);
5611 if (rt2x00_get_field16(eeprom
, EEPROM_EIRP_MAX_TX_POWER_2GHZ
) <
5612 EIRP_MAX_TX_POWER_LIMIT
)
5613 __set_bit(CAPABILITY_POWER_LIMIT
, &rt2x00dev
->cap_flags
);
5619 * RF value list for rt28xx
5620 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
5622 static const struct rf_channel rf_vals
[] = {
5623 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
5624 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
5625 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
5626 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
5627 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
5628 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
5629 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
5630 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
5631 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
5632 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
5633 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
5634 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
5635 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
5636 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
5638 /* 802.11 UNI / HyperLan 2 */
5639 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
5640 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
5641 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
5642 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
5643 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
5644 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
5645 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
5646 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
5647 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
5648 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
5649 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
5650 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
5652 /* 802.11 HyperLan 2 */
5653 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
5654 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
5655 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
5656 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
5657 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
5658 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
5659 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
5660 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
5661 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
5662 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
5663 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
5664 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
5665 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
5666 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
5667 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
5668 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
5671 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
5672 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
5673 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
5674 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
5675 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
5676 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
5677 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
5678 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
5679 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
5680 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
5681 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
5684 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
5685 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
5686 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
5687 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
5688 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
5689 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
5690 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
5694 * RF value list for rt3xxx
5695 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
5697 static const struct rf_channel rf_vals_3x
[] = {
5713 /* 802.11 UNI / HyperLan 2 */
5727 /* 802.11 HyperLan 2 */
5759 static const struct rf_channel rf_vals_5592_xtal20
[] = {
5760 /* Channel, N, K, mod, R */
5770 {10, 491, 4, 10, 3},
5771 {11, 492, 4, 10, 3},
5772 {12, 493, 4, 10, 3},
5773 {13, 494, 4, 10, 3},
5774 {14, 496, 8, 10, 3},
5775 {36, 172, 8, 12, 1},
5776 {38, 173, 0, 12, 1},
5777 {40, 173, 4, 12, 1},
5778 {42, 173, 8, 12, 1},
5779 {44, 174, 0, 12, 1},
5780 {46, 174, 4, 12, 1},
5781 {48, 174, 8, 12, 1},
5782 {50, 175, 0, 12, 1},
5783 {52, 175, 4, 12, 1},
5784 {54, 175, 8, 12, 1},
5785 {56, 176, 0, 12, 1},
5786 {58, 176, 4, 12, 1},
5787 {60, 176, 8, 12, 1},
5788 {62, 177, 0, 12, 1},
5789 {64, 177, 4, 12, 1},
5790 {100, 183, 4, 12, 1},
5791 {102, 183, 8, 12, 1},
5792 {104, 184, 0, 12, 1},
5793 {106, 184, 4, 12, 1},
5794 {108, 184, 8, 12, 1},
5795 {110, 185, 0, 12, 1},
5796 {112, 185, 4, 12, 1},
5797 {114, 185, 8, 12, 1},
5798 {116, 186, 0, 12, 1},
5799 {118, 186, 4, 12, 1},
5800 {120, 186, 8, 12, 1},
5801 {122, 187, 0, 12, 1},
5802 {124, 187, 4, 12, 1},
5803 {126, 187, 8, 12, 1},
5804 {128, 188, 0, 12, 1},
5805 {130, 188, 4, 12, 1},
5806 {132, 188, 8, 12, 1},
5807 {134, 189, 0, 12, 1},
5808 {136, 189, 4, 12, 1},
5809 {138, 189, 8, 12, 1},
5810 {140, 190, 0, 12, 1},
5811 {149, 191, 6, 12, 1},
5812 {151, 191, 10, 12, 1},
5813 {153, 192, 2, 12, 1},
5814 {155, 192, 6, 12, 1},
5815 {157, 192, 10, 12, 1},
5816 {159, 193, 2, 12, 1},
5817 {161, 193, 6, 12, 1},
5818 {165, 194, 2, 12, 1},
5819 {184, 164, 0, 12, 1},
5820 {188, 164, 4, 12, 1},
5821 {192, 165, 8, 12, 1},
5822 {196, 166, 0, 12, 1},
5825 static const struct rf_channel rf_vals_5592_xtal40
[] = {
5826 /* Channel, N, K, mod, R */
5836 {10, 245, 7, 10, 3},
5837 {11, 246, 2, 10, 3},
5838 {12, 246, 7, 10, 3},
5839 {13, 247, 2, 10, 3},
5840 {14, 248, 4, 10, 3},
5844 {42, 86, 10, 12, 1},
5850 {54, 87, 10, 12, 1},
5856 {100, 91, 8, 12, 1},
5857 {102, 91, 10, 12, 1},
5858 {104, 92, 0, 12, 1},
5859 {106, 92, 2, 12, 1},
5860 {108, 92, 4, 12, 1},
5861 {110, 92, 6, 12, 1},
5862 {112, 92, 8, 12, 1},
5863 {114, 92, 10, 12, 1},
5864 {116, 93, 0, 12, 1},
5865 {118, 93, 2, 12, 1},
5866 {120, 93, 4, 12, 1},
5867 {122, 93, 6, 12, 1},
5868 {124, 93, 8, 12, 1},
5869 {126, 93, 10, 12, 1},
5870 {128, 94, 0, 12, 1},
5871 {130, 94, 2, 12, 1},
5872 {132, 94, 4, 12, 1},
5873 {134, 94, 6, 12, 1},
5874 {136, 94, 8, 12, 1},
5875 {138, 94, 10, 12, 1},
5876 {140, 95, 0, 12, 1},
5877 {149, 95, 9, 12, 1},
5878 {151, 95, 11, 12, 1},
5879 {153, 96, 1, 12, 1},
5880 {155, 96, 3, 12, 1},
5881 {157, 96, 5, 12, 1},
5882 {159, 96, 7, 12, 1},
5883 {161, 96, 9, 12, 1},
5884 {165, 97, 1, 12, 1},
5885 {184, 82, 0, 12, 1},
5886 {188, 82, 4, 12, 1},
5887 {192, 82, 8, 12, 1},
5888 {196, 83, 0, 12, 1},
5891 static int rt2800_probe_hw_mode(struct rt2x00_dev
*rt2x00dev
)
5893 struct hw_mode_spec
*spec
= &rt2x00dev
->spec
;
5894 struct channel_info
*info
;
5895 char *default_power1
;
5896 char *default_power2
;
5902 * Disable powersaving as default on PCI devices.
5904 if (rt2x00_is_pci(rt2x00dev
) || rt2x00_is_soc(rt2x00dev
))
5905 rt2x00dev
->hw
->wiphy
->flags
&= ~WIPHY_FLAG_PS_ON_BY_DEFAULT
;
5908 * Initialize all hw fields.
5910 rt2x00dev
->hw
->flags
=
5911 IEEE80211_HW_SIGNAL_DBM
|
5912 IEEE80211_HW_SUPPORTS_PS
|
5913 IEEE80211_HW_PS_NULLFUNC_STACK
|
5914 IEEE80211_HW_AMPDU_AGGREGATION
|
5915 IEEE80211_HW_REPORTS_TX_ACK_STATUS
;
5918 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
5919 * unless we are capable of sending the buffered frames out after the
5920 * DTIM transmission using rt2x00lib_beacondone. This will send out
5921 * multicast and broadcast traffic immediately instead of buffering it
5922 * infinitly and thus dropping it after some time.
5924 if (!rt2x00_is_usb(rt2x00dev
))
5925 rt2x00dev
->hw
->flags
|=
5926 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING
;
5928 SET_IEEE80211_DEV(rt2x00dev
->hw
, rt2x00dev
->dev
);
5929 SET_IEEE80211_PERM_ADDR(rt2x00dev
->hw
,
5930 rt2x00_eeprom_addr(rt2x00dev
,
5931 EEPROM_MAC_ADDR_0
));
5934 * As rt2800 has a global fallback table we cannot specify
5935 * more then one tx rate per frame but since the hw will
5936 * try several rates (based on the fallback table) we should
5937 * initialize max_report_rates to the maximum number of rates
5938 * we are going to try. Otherwise mac80211 will truncate our
5939 * reported tx rates and the rc algortihm will end up with
5942 rt2x00dev
->hw
->max_rates
= 1;
5943 rt2x00dev
->hw
->max_report_rates
= 7;
5944 rt2x00dev
->hw
->max_rate_tries
= 1;
5946 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF0
, &eeprom
);
5949 * Initialize hw_mode information.
5951 spec
->supported_bands
= SUPPORT_BAND_2GHZ
;
5952 spec
->supported_rates
= SUPPORT_RATE_CCK
| SUPPORT_RATE_OFDM
;
5954 if (rt2x00_rf(rt2x00dev
, RF2820
) ||
5955 rt2x00_rf(rt2x00dev
, RF2720
)) {
5956 spec
->num_channels
= 14;
5957 spec
->channels
= rf_vals
;
5958 } else if (rt2x00_rf(rt2x00dev
, RF2850
) ||
5959 rt2x00_rf(rt2x00dev
, RF2750
)) {
5960 spec
->supported_bands
|= SUPPORT_BAND_5GHZ
;
5961 spec
->num_channels
= ARRAY_SIZE(rf_vals
);
5962 spec
->channels
= rf_vals
;
5963 } else if (rt2x00_rf(rt2x00dev
, RF3020
) ||
5964 rt2x00_rf(rt2x00dev
, RF2020
) ||
5965 rt2x00_rf(rt2x00dev
, RF3021
) ||
5966 rt2x00_rf(rt2x00dev
, RF3022
) ||
5967 rt2x00_rf(rt2x00dev
, RF3290
) ||
5968 rt2x00_rf(rt2x00dev
, RF3320
) ||
5969 rt2x00_rf(rt2x00dev
, RF3322
) ||
5970 rt2x00_rf(rt2x00dev
, RF5360
) ||
5971 rt2x00_rf(rt2x00dev
, RF5370
) ||
5972 rt2x00_rf(rt2x00dev
, RF5372
) ||
5973 rt2x00_rf(rt2x00dev
, RF5390
) ||
5974 rt2x00_rf(rt2x00dev
, RF5392
)) {
5975 spec
->num_channels
= 14;
5976 spec
->channels
= rf_vals_3x
;
5977 } else if (rt2x00_rf(rt2x00dev
, RF3052
)) {
5978 spec
->supported_bands
|= SUPPORT_BAND_5GHZ
;
5979 spec
->num_channels
= ARRAY_SIZE(rf_vals_3x
);
5980 spec
->channels
= rf_vals_3x
;
5981 } else if (rt2x00_rf(rt2x00dev
, RF5592
)) {
5982 spec
->supported_bands
|= SUPPORT_BAND_5GHZ
;
5984 rt2800_register_read(rt2x00dev
, MAC_DEBUG_INDEX
, ®
);
5985 if (rt2x00_get_field32(reg
, MAC_DEBUG_INDEX_XTAL
)) {
5986 spec
->num_channels
= ARRAY_SIZE(rf_vals_5592_xtal40
);
5987 spec
->channels
= rf_vals_5592_xtal40
;
5989 spec
->num_channels
= ARRAY_SIZE(rf_vals_5592_xtal20
);
5990 spec
->channels
= rf_vals_5592_xtal20
;
5994 if (WARN_ON_ONCE(!spec
->channels
))
5998 * Initialize HT information.
6000 if (!rt2x00_rf(rt2x00dev
, RF2020
))
6001 spec
->ht
.ht_supported
= true;
6003 spec
->ht
.ht_supported
= false;
6006 IEEE80211_HT_CAP_SUP_WIDTH_20_40
|
6007 IEEE80211_HT_CAP_GRN_FLD
|
6008 IEEE80211_HT_CAP_SGI_20
|
6009 IEEE80211_HT_CAP_SGI_40
;
6011 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_TXPATH
) >= 2)
6012 spec
->ht
.cap
|= IEEE80211_HT_CAP_TX_STBC
;
6015 rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_RXPATH
) <<
6016 IEEE80211_HT_CAP_RX_STBC_SHIFT
;
6018 spec
->ht
.ampdu_factor
= 3;
6019 spec
->ht
.ampdu_density
= 4;
6020 spec
->ht
.mcs
.tx_params
=
6021 IEEE80211_HT_MCS_TX_DEFINED
|
6022 IEEE80211_HT_MCS_TX_RX_DIFF
|
6023 ((rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_TXPATH
) - 1) <<
6024 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT
);
6026 switch (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_RXPATH
)) {
6028 spec
->ht
.mcs
.rx_mask
[2] = 0xff;
6030 spec
->ht
.mcs
.rx_mask
[1] = 0xff;
6032 spec
->ht
.mcs
.rx_mask
[0] = 0xff;
6033 spec
->ht
.mcs
.rx_mask
[4] = 0x1; /* MCS32 */
6038 * Create channel information array
6040 info
= kcalloc(spec
->num_channels
, sizeof(*info
), GFP_KERNEL
);
6044 spec
->channels_info
= info
;
6046 default_power1
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_BG1
);
6047 default_power2
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_BG2
);
6049 for (i
= 0; i
< 14; i
++) {
6050 info
[i
].default_power1
= default_power1
[i
];
6051 info
[i
].default_power2
= default_power2
[i
];
6054 if (spec
->num_channels
> 14) {
6055 default_power1
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_A1
);
6056 default_power2
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_A2
);
6058 for (i
= 14; i
< spec
->num_channels
; i
++) {
6059 info
[i
].default_power1
= default_power1
[i
];
6060 info
[i
].default_power2
= default_power2
[i
];
6064 switch (rt2x00dev
->chip
.rf
) {
6077 __set_bit(CAPABILITY_VCO_RECALIBRATION
, &rt2x00dev
->cap_flags
);
6084 static int rt2800_probe_rt(struct rt2x00_dev
*rt2x00dev
)
6090 if (rt2x00_rt(rt2x00dev
, RT3290
))
6091 rt2800_register_read(rt2x00dev
, MAC_CSR0_3290
, ®
);
6093 rt2800_register_read(rt2x00dev
, MAC_CSR0
, ®
);
6095 rt
= rt2x00_get_field32(reg
, MAC_CSR0_CHIPSET
);
6096 rev
= rt2x00_get_field32(reg
, MAC_CSR0_REVISION
);
6114 rt2x00_err(rt2x00dev
, "Invalid RT chipset 0x%04x, rev %04x detected\n",
6119 rt2x00_set_rt(rt2x00dev
, rt
, rev
);
6124 int rt2800_probe_hw(struct rt2x00_dev
*rt2x00dev
)
6129 retval
= rt2800_probe_rt(rt2x00dev
);
6134 * Allocate eeprom data.
6136 retval
= rt2800_validate_eeprom(rt2x00dev
);
6140 retval
= rt2800_init_eeprom(rt2x00dev
);
6145 * Enable rfkill polling by setting GPIO direction of the
6146 * rfkill switch GPIO pin correctly.
6148 rt2800_register_read(rt2x00dev
, GPIO_CTRL
, ®
);
6149 rt2x00_set_field32(®
, GPIO_CTRL_DIR2
, 1);
6150 rt2800_register_write(rt2x00dev
, GPIO_CTRL
, reg
);
6153 * Initialize hw specifications.
6155 retval
= rt2800_probe_hw_mode(rt2x00dev
);
6160 * Set device capabilities.
6162 __set_bit(CAPABILITY_CONTROL_FILTERS
, &rt2x00dev
->cap_flags
);
6163 __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL
, &rt2x00dev
->cap_flags
);
6164 if (!rt2x00_is_usb(rt2x00dev
))
6165 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT
, &rt2x00dev
->cap_flags
);
6168 * Set device requirements.
6170 if (!rt2x00_is_soc(rt2x00dev
))
6171 __set_bit(REQUIRE_FIRMWARE
, &rt2x00dev
->cap_flags
);
6172 __set_bit(REQUIRE_L2PAD
, &rt2x00dev
->cap_flags
);
6173 __set_bit(REQUIRE_TXSTATUS_FIFO
, &rt2x00dev
->cap_flags
);
6174 if (!rt2800_hwcrypt_disabled(rt2x00dev
))
6175 __set_bit(CAPABILITY_HW_CRYPTO
, &rt2x00dev
->cap_flags
);
6176 __set_bit(CAPABILITY_LINK_TUNING
, &rt2x00dev
->cap_flags
);
6177 __set_bit(REQUIRE_HT_TX_DESC
, &rt2x00dev
->cap_flags
);
6178 if (rt2x00_is_usb(rt2x00dev
))
6179 __set_bit(REQUIRE_PS_AUTOWAKE
, &rt2x00dev
->cap_flags
);
6181 __set_bit(REQUIRE_DMA
, &rt2x00dev
->cap_flags
);
6182 __set_bit(REQUIRE_TASKLET_CONTEXT
, &rt2x00dev
->cap_flags
);
6186 * Set the rssi offset.
6188 rt2x00dev
->rssi_offset
= DEFAULT_RSSI_OFFSET
;
6192 EXPORT_SYMBOL_GPL(rt2800_probe_hw
);
6195 * IEEE80211 stack callback functions.
6197 void rt2800_get_tkip_seq(struct ieee80211_hw
*hw
, u8 hw_key_idx
, u32
*iv32
,
6200 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
6201 struct mac_iveiv_entry iveiv_entry
;
6204 offset
= MAC_IVEIV_ENTRY(hw_key_idx
);
6205 rt2800_register_multiread(rt2x00dev
, offset
,
6206 &iveiv_entry
, sizeof(iveiv_entry
));
6208 memcpy(iv16
, &iveiv_entry
.iv
[0], sizeof(*iv16
));
6209 memcpy(iv32
, &iveiv_entry
.iv
[4], sizeof(*iv32
));
6211 EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq
);
6213 int rt2800_set_rts_threshold(struct ieee80211_hw
*hw
, u32 value
)
6215 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
6217 bool enabled
= (value
< IEEE80211_MAX_RTS_THRESHOLD
);
6219 rt2800_register_read(rt2x00dev
, TX_RTS_CFG
, ®
);
6220 rt2x00_set_field32(®
, TX_RTS_CFG_RTS_THRES
, value
);
6221 rt2800_register_write(rt2x00dev
, TX_RTS_CFG
, reg
);
6223 rt2800_register_read(rt2x00dev
, CCK_PROT_CFG
, ®
);
6224 rt2x00_set_field32(®
, CCK_PROT_CFG_RTS_TH_EN
, enabled
);
6225 rt2800_register_write(rt2x00dev
, CCK_PROT_CFG
, reg
);
6227 rt2800_register_read(rt2x00dev
, OFDM_PROT_CFG
, ®
);
6228 rt2x00_set_field32(®
, OFDM_PROT_CFG_RTS_TH_EN
, enabled
);
6229 rt2800_register_write(rt2x00dev
, OFDM_PROT_CFG
, reg
);
6231 rt2800_register_read(rt2x00dev
, MM20_PROT_CFG
, ®
);
6232 rt2x00_set_field32(®
, MM20_PROT_CFG_RTS_TH_EN
, enabled
);
6233 rt2800_register_write(rt2x00dev
, MM20_PROT_CFG
, reg
);
6235 rt2800_register_read(rt2x00dev
, MM40_PROT_CFG
, ®
);
6236 rt2x00_set_field32(®
, MM40_PROT_CFG_RTS_TH_EN
, enabled
);
6237 rt2800_register_write(rt2x00dev
, MM40_PROT_CFG
, reg
);
6239 rt2800_register_read(rt2x00dev
, GF20_PROT_CFG
, ®
);
6240 rt2x00_set_field32(®
, GF20_PROT_CFG_RTS_TH_EN
, enabled
);
6241 rt2800_register_write(rt2x00dev
, GF20_PROT_CFG
, reg
);
6243 rt2800_register_read(rt2x00dev
, GF40_PROT_CFG
, ®
);
6244 rt2x00_set_field32(®
, GF40_PROT_CFG_RTS_TH_EN
, enabled
);
6245 rt2800_register_write(rt2x00dev
, GF40_PROT_CFG
, reg
);
6249 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold
);
6251 int rt2800_conf_tx(struct ieee80211_hw
*hw
,
6252 struct ieee80211_vif
*vif
, u16 queue_idx
,
6253 const struct ieee80211_tx_queue_params
*params
)
6255 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
6256 struct data_queue
*queue
;
6257 struct rt2x00_field32 field
;
6263 * First pass the configuration through rt2x00lib, that will
6264 * update the queue settings and validate the input. After that
6265 * we are free to update the registers based on the value
6266 * in the queue parameter.
6268 retval
= rt2x00mac_conf_tx(hw
, vif
, queue_idx
, params
);
6273 * We only need to perform additional register initialization
6279 queue
= rt2x00queue_get_tx_queue(rt2x00dev
, queue_idx
);
6281 /* Update WMM TXOP register */
6282 offset
= WMM_TXOP0_CFG
+ (sizeof(u32
) * (!!(queue_idx
& 2)));
6283 field
.bit_offset
= (queue_idx
& 1) * 16;
6284 field
.bit_mask
= 0xffff << field
.bit_offset
;
6286 rt2800_register_read(rt2x00dev
, offset
, ®
);
6287 rt2x00_set_field32(®
, field
, queue
->txop
);
6288 rt2800_register_write(rt2x00dev
, offset
, reg
);
6290 /* Update WMM registers */
6291 field
.bit_offset
= queue_idx
* 4;
6292 field
.bit_mask
= 0xf << field
.bit_offset
;
6294 rt2800_register_read(rt2x00dev
, WMM_AIFSN_CFG
, ®
);
6295 rt2x00_set_field32(®
, field
, queue
->aifs
);
6296 rt2800_register_write(rt2x00dev
, WMM_AIFSN_CFG
, reg
);
6298 rt2800_register_read(rt2x00dev
, WMM_CWMIN_CFG
, ®
);
6299 rt2x00_set_field32(®
, field
, queue
->cw_min
);
6300 rt2800_register_write(rt2x00dev
, WMM_CWMIN_CFG
, reg
);
6302 rt2800_register_read(rt2x00dev
, WMM_CWMAX_CFG
, ®
);
6303 rt2x00_set_field32(®
, field
, queue
->cw_max
);
6304 rt2800_register_write(rt2x00dev
, WMM_CWMAX_CFG
, reg
);
6306 /* Update EDCA registers */
6307 offset
= EDCA_AC0_CFG
+ (sizeof(u32
) * queue_idx
);
6309 rt2800_register_read(rt2x00dev
, offset
, ®
);
6310 rt2x00_set_field32(®
, EDCA_AC0_CFG_TX_OP
, queue
->txop
);
6311 rt2x00_set_field32(®
, EDCA_AC0_CFG_AIFSN
, queue
->aifs
);
6312 rt2x00_set_field32(®
, EDCA_AC0_CFG_CWMIN
, queue
->cw_min
);
6313 rt2x00_set_field32(®
, EDCA_AC0_CFG_CWMAX
, queue
->cw_max
);
6314 rt2800_register_write(rt2x00dev
, offset
, reg
);
6318 EXPORT_SYMBOL_GPL(rt2800_conf_tx
);
6320 u64
rt2800_get_tsf(struct ieee80211_hw
*hw
, struct ieee80211_vif
*vif
)
6322 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
6326 rt2800_register_read(rt2x00dev
, TSF_TIMER_DW1
, ®
);
6327 tsf
= (u64
) rt2x00_get_field32(reg
, TSF_TIMER_DW1_HIGH_WORD
) << 32;
6328 rt2800_register_read(rt2x00dev
, TSF_TIMER_DW0
, ®
);
6329 tsf
|= rt2x00_get_field32(reg
, TSF_TIMER_DW0_LOW_WORD
);
6333 EXPORT_SYMBOL_GPL(rt2800_get_tsf
);
6335 int rt2800_ampdu_action(struct ieee80211_hw
*hw
, struct ieee80211_vif
*vif
,
6336 enum ieee80211_ampdu_mlme_action action
,
6337 struct ieee80211_sta
*sta
, u16 tid
, u16
*ssn
,
6340 struct rt2x00_sta
*sta_priv
= (struct rt2x00_sta
*)sta
->drv_priv
;
6344 * Don't allow aggregation for stations the hardware isn't aware
6345 * of because tx status reports for frames to an unknown station
6346 * always contain wcid=255 and thus we can't distinguish between
6347 * multiple stations which leads to unwanted situations when the
6348 * hw reorders frames due to aggregation.
6350 if (sta_priv
->wcid
< 0)
6354 case IEEE80211_AMPDU_RX_START
:
6355 case IEEE80211_AMPDU_RX_STOP
:
6357 * The hw itself takes care of setting up BlockAck mechanisms.
6358 * So, we only have to allow mac80211 to nagotiate a BlockAck
6359 * agreement. Once that is done, the hw will BlockAck incoming
6360 * AMPDUs without further setup.
6363 case IEEE80211_AMPDU_TX_START
:
6364 ieee80211_start_tx_ba_cb_irqsafe(vif
, sta
->addr
, tid
);
6366 case IEEE80211_AMPDU_TX_STOP_CONT
:
6367 case IEEE80211_AMPDU_TX_STOP_FLUSH
:
6368 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT
:
6369 ieee80211_stop_tx_ba_cb_irqsafe(vif
, sta
->addr
, tid
);
6371 case IEEE80211_AMPDU_TX_OPERATIONAL
:
6374 rt2x00_warn((struct rt2x00_dev
*)hw
->priv
,
6375 "Unknown AMPDU action\n");
6380 EXPORT_SYMBOL_GPL(rt2800_ampdu_action
);
6382 int rt2800_get_survey(struct ieee80211_hw
*hw
, int idx
,
6383 struct survey_info
*survey
)
6385 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
6386 struct ieee80211_conf
*conf
= &hw
->conf
;
6387 u32 idle
, busy
, busy_ext
;
6392 survey
->channel
= conf
->chandef
.chan
;
6394 rt2800_register_read(rt2x00dev
, CH_IDLE_STA
, &idle
);
6395 rt2800_register_read(rt2x00dev
, CH_BUSY_STA
, &busy
);
6396 rt2800_register_read(rt2x00dev
, CH_BUSY_STA_SEC
, &busy_ext
);
6399 survey
->filled
= SURVEY_INFO_CHANNEL_TIME
|
6400 SURVEY_INFO_CHANNEL_TIME_BUSY
|
6401 SURVEY_INFO_CHANNEL_TIME_EXT_BUSY
;
6403 survey
->channel_time
= (idle
+ busy
) / 1000;
6404 survey
->channel_time_busy
= busy
/ 1000;
6405 survey
->channel_time_ext_busy
= busy_ext
/ 1000;
6408 if (!(hw
->conf
.flags
& IEEE80211_CONF_OFFCHANNEL
))
6409 survey
->filled
|= SURVEY_INFO_IN_USE
;
6414 EXPORT_SYMBOL_GPL(rt2800_get_survey
);
6416 MODULE_AUTHOR(DRV_PROJECT
", Bartlomiej Zolnierkiewicz");
6417 MODULE_VERSION(DRV_VERSION
);
6418 MODULE_DESCRIPTION("Ralink RT2800 library");
6419 MODULE_LICENSE("GPL");