2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
3 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
4 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
5 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
7 Based on the original rt2800pci.c and rt2800usb.c.
8 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
9 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
10 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
11 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
12 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
13 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
14 <http://rt2x00.serialmonkey.com>
16 This program is free software; you can redistribute it and/or modify
17 it under the terms of the GNU General Public License as published by
18 the Free Software Foundation; either version 2 of the License, or
19 (at your option) any later version.
21 This program is distributed in the hope that it will be useful,
22 but WITHOUT ANY WARRANTY; without even the implied warranty of
23 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 GNU General Public License for more details.
26 You should have received a copy of the GNU General Public License
27 along with this program; if not, write to the
28 Free Software Foundation, Inc.,
29 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
34 Abstract: rt2800 generic device routines.
37 #include <linux/crc-ccitt.h>
38 #include <linux/kernel.h>
39 #include <linux/module.h>
40 #include <linux/slab.h>
43 #include "rt2800lib.h"
48 * All access to the CSR registers will go through the methods
49 * rt2800_register_read and rt2800_register_write.
50 * BBP and RF register require indirect register access,
51 * and use the CSR registers BBPCSR and RFCSR to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
55 * between each attampt. When the busy bit is still set at that time,
56 * the access attempt is considered to have failed,
57 * and we will print an error.
58 * The _lock versions must be used if you already hold the csr_mutex
60 #define WAIT_FOR_BBP(__dev, __reg) \
61 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
62 #define WAIT_FOR_RFCSR(__dev, __reg) \
63 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
64 #define WAIT_FOR_RF(__dev, __reg) \
65 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
66 #define WAIT_FOR_MCU(__dev, __reg) \
67 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
68 H2M_MAILBOX_CSR_OWNER, (__reg))
70 static inline bool rt2800_is_305x_soc(struct rt2x00_dev
*rt2x00dev
)
72 /* check for rt2872 on SoC */
73 if (!rt2x00_is_soc(rt2x00dev
) ||
74 !rt2x00_rt(rt2x00dev
, RT2872
))
77 /* we know for sure that these rf chipsets are used on rt305x boards */
78 if (rt2x00_rf(rt2x00dev
, RF3020
) ||
79 rt2x00_rf(rt2x00dev
, RF3021
) ||
80 rt2x00_rf(rt2x00dev
, RF3022
))
83 rt2x00_warn(rt2x00dev
, "Unknown RF chipset on rt305x\n");
87 static void rt2800_bbp_write(struct rt2x00_dev
*rt2x00dev
,
88 const unsigned int word
, const u8 value
)
92 mutex_lock(&rt2x00dev
->csr_mutex
);
95 * Wait until the BBP becomes available, afterwards we
96 * can safely write the new data into the register.
98 if (WAIT_FOR_BBP(rt2x00dev
, ®
)) {
100 rt2x00_set_field32(®
, BBP_CSR_CFG_VALUE
, value
);
101 rt2x00_set_field32(®
, BBP_CSR_CFG_REGNUM
, word
);
102 rt2x00_set_field32(®
, BBP_CSR_CFG_BUSY
, 1);
103 rt2x00_set_field32(®
, BBP_CSR_CFG_READ_CONTROL
, 0);
104 rt2x00_set_field32(®
, BBP_CSR_CFG_BBP_RW_MODE
, 1);
106 rt2800_register_write_lock(rt2x00dev
, BBP_CSR_CFG
, reg
);
109 mutex_unlock(&rt2x00dev
->csr_mutex
);
112 static void rt2800_bbp_read(struct rt2x00_dev
*rt2x00dev
,
113 const unsigned int word
, u8
*value
)
117 mutex_lock(&rt2x00dev
->csr_mutex
);
120 * Wait until the BBP becomes available, afterwards we
121 * can safely write the read request into the register.
122 * After the data has been written, we wait until hardware
123 * returns the correct value, if at any time the register
124 * doesn't become available in time, reg will be 0xffffffff
125 * which means we return 0xff to the caller.
127 if (WAIT_FOR_BBP(rt2x00dev
, ®
)) {
129 rt2x00_set_field32(®
, BBP_CSR_CFG_REGNUM
, word
);
130 rt2x00_set_field32(®
, BBP_CSR_CFG_BUSY
, 1);
131 rt2x00_set_field32(®
, BBP_CSR_CFG_READ_CONTROL
, 1);
132 rt2x00_set_field32(®
, BBP_CSR_CFG_BBP_RW_MODE
, 1);
134 rt2800_register_write_lock(rt2x00dev
, BBP_CSR_CFG
, reg
);
136 WAIT_FOR_BBP(rt2x00dev
, ®
);
139 *value
= rt2x00_get_field32(reg
, BBP_CSR_CFG_VALUE
);
141 mutex_unlock(&rt2x00dev
->csr_mutex
);
144 static void rt2800_rfcsr_write(struct rt2x00_dev
*rt2x00dev
,
145 const unsigned int word
, const u8 value
)
149 mutex_lock(&rt2x00dev
->csr_mutex
);
152 * Wait until the RFCSR becomes available, afterwards we
153 * can safely write the new data into the register.
155 if (WAIT_FOR_RFCSR(rt2x00dev
, ®
)) {
157 rt2x00_set_field32(®
, RF_CSR_CFG_DATA
, value
);
158 rt2x00_set_field32(®
, RF_CSR_CFG_REGNUM
, word
);
159 rt2x00_set_field32(®
, RF_CSR_CFG_WRITE
, 1);
160 rt2x00_set_field32(®
, RF_CSR_CFG_BUSY
, 1);
162 rt2800_register_write_lock(rt2x00dev
, RF_CSR_CFG
, reg
);
165 mutex_unlock(&rt2x00dev
->csr_mutex
);
168 static void rt2800_rfcsr_read(struct rt2x00_dev
*rt2x00dev
,
169 const unsigned int word
, u8
*value
)
173 mutex_lock(&rt2x00dev
->csr_mutex
);
176 * Wait until the RFCSR becomes available, afterwards we
177 * can safely write the read request into the register.
178 * After the data has been written, we wait until hardware
179 * returns the correct value, if at any time the register
180 * doesn't become available in time, reg will be 0xffffffff
181 * which means we return 0xff to the caller.
183 if (WAIT_FOR_RFCSR(rt2x00dev
, ®
)) {
185 rt2x00_set_field32(®
, RF_CSR_CFG_REGNUM
, word
);
186 rt2x00_set_field32(®
, RF_CSR_CFG_WRITE
, 0);
187 rt2x00_set_field32(®
, RF_CSR_CFG_BUSY
, 1);
189 rt2800_register_write_lock(rt2x00dev
, RF_CSR_CFG
, reg
);
191 WAIT_FOR_RFCSR(rt2x00dev
, ®
);
194 *value
= rt2x00_get_field32(reg
, RF_CSR_CFG_DATA
);
196 mutex_unlock(&rt2x00dev
->csr_mutex
);
199 static void rt2800_rf_write(struct rt2x00_dev
*rt2x00dev
,
200 const unsigned int word
, const u32 value
)
204 mutex_lock(&rt2x00dev
->csr_mutex
);
207 * Wait until the RF becomes available, afterwards we
208 * can safely write the new data into the register.
210 if (WAIT_FOR_RF(rt2x00dev
, ®
)) {
212 rt2x00_set_field32(®
, RF_CSR_CFG0_REG_VALUE_BW
, value
);
213 rt2x00_set_field32(®
, RF_CSR_CFG0_STANDBYMODE
, 0);
214 rt2x00_set_field32(®
, RF_CSR_CFG0_SEL
, 0);
215 rt2x00_set_field32(®
, RF_CSR_CFG0_BUSY
, 1);
217 rt2800_register_write_lock(rt2x00dev
, RF_CSR_CFG0
, reg
);
218 rt2x00_rf_write(rt2x00dev
, word
, value
);
221 mutex_unlock(&rt2x00dev
->csr_mutex
);
224 static const unsigned int rt2800_eeprom_map
[EEPROM_WORD_COUNT
] = {
225 [EEPROM_CHIP_ID
] = 0x0000,
226 [EEPROM_VERSION
] = 0x0001,
227 [EEPROM_MAC_ADDR_0
] = 0x0002,
228 [EEPROM_MAC_ADDR_1
] = 0x0003,
229 [EEPROM_MAC_ADDR_2
] = 0x0004,
230 [EEPROM_NIC_CONF0
] = 0x001a,
231 [EEPROM_NIC_CONF1
] = 0x001b,
232 [EEPROM_FREQ
] = 0x001d,
233 [EEPROM_LED_AG_CONF
] = 0x001e,
234 [EEPROM_LED_ACT_CONF
] = 0x001f,
235 [EEPROM_LED_POLARITY
] = 0x0020,
236 [EEPROM_NIC_CONF2
] = 0x0021,
237 [EEPROM_LNA
] = 0x0022,
238 [EEPROM_RSSI_BG
] = 0x0023,
239 [EEPROM_RSSI_BG2
] = 0x0024,
240 [EEPROM_TXMIXER_GAIN_BG
] = 0x0024, /* overlaps with RSSI_BG2 */
241 [EEPROM_RSSI_A
] = 0x0025,
242 [EEPROM_RSSI_A2
] = 0x0026,
243 [EEPROM_TXMIXER_GAIN_A
] = 0x0026, /* overlaps with RSSI_A2 */
244 [EEPROM_EIRP_MAX_TX_POWER
] = 0x0027,
245 [EEPROM_TXPOWER_DELTA
] = 0x0028,
246 [EEPROM_TXPOWER_BG1
] = 0x0029,
247 [EEPROM_TXPOWER_BG2
] = 0x0030,
248 [EEPROM_TSSI_BOUND_BG1
] = 0x0037,
249 [EEPROM_TSSI_BOUND_BG2
] = 0x0038,
250 [EEPROM_TSSI_BOUND_BG3
] = 0x0039,
251 [EEPROM_TSSI_BOUND_BG4
] = 0x003a,
252 [EEPROM_TSSI_BOUND_BG5
] = 0x003b,
253 [EEPROM_TXPOWER_A1
] = 0x003c,
254 [EEPROM_TXPOWER_A2
] = 0x0053,
255 [EEPROM_TSSI_BOUND_A1
] = 0x006a,
256 [EEPROM_TSSI_BOUND_A2
] = 0x006b,
257 [EEPROM_TSSI_BOUND_A3
] = 0x006c,
258 [EEPROM_TSSI_BOUND_A4
] = 0x006d,
259 [EEPROM_TSSI_BOUND_A5
] = 0x006e,
260 [EEPROM_TXPOWER_BYRATE
] = 0x006f,
261 [EEPROM_BBP_START
] = 0x0078,
264 static const unsigned int rt2800_eeprom_map_ext
[EEPROM_WORD_COUNT
] = {
265 [EEPROM_CHIP_ID
] = 0x0000,
266 [EEPROM_VERSION
] = 0x0001,
267 [EEPROM_MAC_ADDR_0
] = 0x0002,
268 [EEPROM_MAC_ADDR_1
] = 0x0003,
269 [EEPROM_MAC_ADDR_2
] = 0x0004,
270 [EEPROM_NIC_CONF0
] = 0x001a,
271 [EEPROM_NIC_CONF1
] = 0x001b,
272 [EEPROM_NIC_CONF2
] = 0x001c,
273 [EEPROM_EIRP_MAX_TX_POWER
] = 0x0020,
274 [EEPROM_FREQ
] = 0x0022,
275 [EEPROM_LED_AG_CONF
] = 0x0023,
276 [EEPROM_LED_ACT_CONF
] = 0x0024,
277 [EEPROM_LED_POLARITY
] = 0x0025,
278 [EEPROM_LNA
] = 0x0026,
279 [EEPROM_EXT_LNA2
] = 0x0027,
280 [EEPROM_RSSI_BG
] = 0x0028,
281 [EEPROM_TXPOWER_DELTA
] = 0x0028, /* Overlaps with RSSI_BG */
282 [EEPROM_RSSI_BG2
] = 0x0029,
283 [EEPROM_TXMIXER_GAIN_BG
] = 0x0029, /* Overlaps with RSSI_BG2 */
284 [EEPROM_RSSI_A
] = 0x002a,
285 [EEPROM_RSSI_A2
] = 0x002b,
286 [EEPROM_TXMIXER_GAIN_A
] = 0x002b, /* Overlaps with RSSI_A2 */
287 [EEPROM_TXPOWER_BG1
] = 0x0030,
288 [EEPROM_TXPOWER_BG2
] = 0x0037,
289 [EEPROM_EXT_TXPOWER_BG3
] = 0x003e,
290 [EEPROM_TSSI_BOUND_BG1
] = 0x0045,
291 [EEPROM_TSSI_BOUND_BG2
] = 0x0046,
292 [EEPROM_TSSI_BOUND_BG3
] = 0x0047,
293 [EEPROM_TSSI_BOUND_BG4
] = 0x0048,
294 [EEPROM_TSSI_BOUND_BG5
] = 0x0049,
295 [EEPROM_TXPOWER_A1
] = 0x004b,
296 [EEPROM_TXPOWER_A2
] = 0x0065,
297 [EEPROM_EXT_TXPOWER_A3
] = 0x007f,
298 [EEPROM_TSSI_BOUND_A1
] = 0x009a,
299 [EEPROM_TSSI_BOUND_A2
] = 0x009b,
300 [EEPROM_TSSI_BOUND_A3
] = 0x009c,
301 [EEPROM_TSSI_BOUND_A4
] = 0x009d,
302 [EEPROM_TSSI_BOUND_A5
] = 0x009e,
303 [EEPROM_TXPOWER_BYRATE
] = 0x00a0,
306 static unsigned int rt2800_eeprom_word_index(struct rt2x00_dev
*rt2x00dev
,
307 const enum rt2800_eeprom_word word
)
309 const unsigned int *map
;
312 if (WARN_ONCE(word
>= EEPROM_WORD_COUNT
,
313 "%s: invalid EEPROM word %d\n",
314 wiphy_name(rt2x00dev
->hw
->wiphy
), word
))
317 if (rt2x00_rt(rt2x00dev
, RT3593
))
318 map
= rt2800_eeprom_map_ext
;
320 map
= rt2800_eeprom_map
;
324 /* Index 0 is valid only for EEPROM_CHIP_ID.
325 * Otherwise it means that the offset of the
326 * given word is not initialized in the map,
327 * or that the field is not usable on the
330 WARN_ONCE(word
!= EEPROM_CHIP_ID
&& index
== 0,
331 "%s: invalid access of EEPROM word %d\n",
332 wiphy_name(rt2x00dev
->hw
->wiphy
), word
);
337 static void *rt2800_eeprom_addr(struct rt2x00_dev
*rt2x00dev
,
338 const enum rt2800_eeprom_word word
)
342 index
= rt2800_eeprom_word_index(rt2x00dev
, word
);
343 return rt2x00_eeprom_addr(rt2x00dev
, index
);
346 static void rt2800_eeprom_read(struct rt2x00_dev
*rt2x00dev
,
347 const enum rt2800_eeprom_word word
, u16
*data
)
351 index
= rt2800_eeprom_word_index(rt2x00dev
, word
);
352 rt2x00_eeprom_read(rt2x00dev
, index
, data
);
355 static void rt2800_eeprom_write(struct rt2x00_dev
*rt2x00dev
,
356 const enum rt2800_eeprom_word word
, u16 data
)
360 index
= rt2800_eeprom_word_index(rt2x00dev
, word
);
361 rt2x00_eeprom_write(rt2x00dev
, index
, data
);
364 static void rt2800_eeprom_read_from_array(struct rt2x00_dev
*rt2x00dev
,
365 const enum rt2800_eeprom_word array
,
371 index
= rt2800_eeprom_word_index(rt2x00dev
, array
);
372 rt2x00_eeprom_read(rt2x00dev
, index
+ offset
, data
);
375 static int rt2800_enable_wlan_rt3290(struct rt2x00_dev
*rt2x00dev
)
380 rt2800_register_read(rt2x00dev
, WLAN_FUN_CTRL
, ®
);
381 if (rt2x00_get_field32(reg
, WLAN_EN
))
384 rt2x00_set_field32(®
, WLAN_GPIO_OUT_OE_BIT_ALL
, 0xff);
385 rt2x00_set_field32(®
, FRC_WL_ANT_SET
, 1);
386 rt2x00_set_field32(®
, WLAN_CLK_EN
, 0);
387 rt2x00_set_field32(®
, WLAN_EN
, 1);
388 rt2800_register_write(rt2x00dev
, WLAN_FUN_CTRL
, reg
);
390 udelay(REGISTER_BUSY_DELAY
);
395 * Check PLL_LD & XTAL_RDY.
397 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
398 rt2800_register_read(rt2x00dev
, CMB_CTRL
, ®
);
399 if (rt2x00_get_field32(reg
, PLL_LD
) &&
400 rt2x00_get_field32(reg
, XTAL_RDY
))
402 udelay(REGISTER_BUSY_DELAY
);
405 if (i
>= REGISTER_BUSY_COUNT
) {
410 rt2800_register_write(rt2x00dev
, 0x58, 0x018);
411 udelay(REGISTER_BUSY_DELAY
);
412 rt2800_register_write(rt2x00dev
, 0x58, 0x418);
413 udelay(REGISTER_BUSY_DELAY
);
414 rt2800_register_write(rt2x00dev
, 0x58, 0x618);
415 udelay(REGISTER_BUSY_DELAY
);
421 rt2800_register_read(rt2x00dev
, WLAN_FUN_CTRL
, ®
);
422 rt2x00_set_field32(®
, PCIE_APP0_CLK_REQ
, 0);
423 rt2x00_set_field32(®
, WLAN_CLK_EN
, 1);
424 rt2x00_set_field32(®
, WLAN_RESET
, 1);
425 rt2800_register_write(rt2x00dev
, WLAN_FUN_CTRL
, reg
);
427 rt2x00_set_field32(®
, WLAN_RESET
, 0);
428 rt2800_register_write(rt2x00dev
, WLAN_FUN_CTRL
, reg
);
430 rt2800_register_write(rt2x00dev
, INT_SOURCE_CSR
, 0x7fffffff);
431 } while (count
!= 0);
436 void rt2800_mcu_request(struct rt2x00_dev
*rt2x00dev
,
437 const u8 command
, const u8 token
,
438 const u8 arg0
, const u8 arg1
)
443 * SOC devices don't support MCU requests.
445 if (rt2x00_is_soc(rt2x00dev
))
448 mutex_lock(&rt2x00dev
->csr_mutex
);
451 * Wait until the MCU becomes available, afterwards we
452 * can safely write the new data into the register.
454 if (WAIT_FOR_MCU(rt2x00dev
, ®
)) {
455 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_OWNER
, 1);
456 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_CMD_TOKEN
, token
);
457 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_ARG0
, arg0
);
458 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_ARG1
, arg1
);
459 rt2800_register_write_lock(rt2x00dev
, H2M_MAILBOX_CSR
, reg
);
462 rt2x00_set_field32(®
, HOST_CMD_CSR_HOST_COMMAND
, command
);
463 rt2800_register_write_lock(rt2x00dev
, HOST_CMD_CSR
, reg
);
466 mutex_unlock(&rt2x00dev
->csr_mutex
);
468 EXPORT_SYMBOL_GPL(rt2800_mcu_request
);
470 int rt2800_wait_csr_ready(struct rt2x00_dev
*rt2x00dev
)
475 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
476 rt2800_register_read(rt2x00dev
, MAC_CSR0
, ®
);
477 if (reg
&& reg
!= ~0)
482 rt2x00_err(rt2x00dev
, "Unstable hardware\n");
485 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready
);
487 int rt2800_wait_wpdma_ready(struct rt2x00_dev
*rt2x00dev
)
493 * Some devices are really slow to respond here. Wait a whole second
496 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
497 rt2800_register_read(rt2x00dev
, WPDMA_GLO_CFG
, ®
);
498 if (!rt2x00_get_field32(reg
, WPDMA_GLO_CFG_TX_DMA_BUSY
) &&
499 !rt2x00_get_field32(reg
, WPDMA_GLO_CFG_RX_DMA_BUSY
))
505 rt2x00_err(rt2x00dev
, "WPDMA TX/RX busy [0x%08x]\n", reg
);
508 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready
);
510 void rt2800_disable_wpdma(struct rt2x00_dev
*rt2x00dev
)
514 rt2800_register_read(rt2x00dev
, WPDMA_GLO_CFG
, ®
);
515 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_TX_DMA
, 0);
516 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_DMA_BUSY
, 0);
517 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_RX_DMA
, 0);
518 rt2x00_set_field32(®
, WPDMA_GLO_CFG_RX_DMA_BUSY
, 0);
519 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_WRITEBACK_DONE
, 1);
520 rt2800_register_write(rt2x00dev
, WPDMA_GLO_CFG
, reg
);
522 EXPORT_SYMBOL_GPL(rt2800_disable_wpdma
);
524 void rt2800_get_txwi_rxwi_size(struct rt2x00_dev
*rt2x00dev
,
525 unsigned short *txwi_size
,
526 unsigned short *rxwi_size
)
528 switch (rt2x00dev
->chip
.rt
) {
530 *txwi_size
= TXWI_DESC_SIZE_4WORDS
;
531 *rxwi_size
= RXWI_DESC_SIZE_5WORDS
;
535 *txwi_size
= TXWI_DESC_SIZE_5WORDS
;
536 *rxwi_size
= RXWI_DESC_SIZE_6WORDS
;
540 *txwi_size
= TXWI_DESC_SIZE_4WORDS
;
541 *rxwi_size
= RXWI_DESC_SIZE_4WORDS
;
545 EXPORT_SYMBOL_GPL(rt2800_get_txwi_rxwi_size
);
547 static bool rt2800_check_firmware_crc(const u8
*data
, const size_t len
)
553 * The last 2 bytes in the firmware array are the crc checksum itself,
554 * this means that we should never pass those 2 bytes to the crc
557 fw_crc
= (data
[len
- 2] << 8 | data
[len
- 1]);
560 * Use the crc ccitt algorithm.
561 * This will return the same value as the legacy driver which
562 * used bit ordering reversion on the both the firmware bytes
563 * before input input as well as on the final output.
564 * Obviously using crc ccitt directly is much more efficient.
566 crc
= crc_ccitt(~0, data
, len
- 2);
569 * There is a small difference between the crc-itu-t + bitrev and
570 * the crc-ccitt crc calculation. In the latter method the 2 bytes
571 * will be swapped, use swab16 to convert the crc to the correct
576 return fw_crc
== crc
;
579 int rt2800_check_firmware(struct rt2x00_dev
*rt2x00dev
,
580 const u8
*data
, const size_t len
)
587 * PCI(e) & SOC devices require firmware with a length
588 * of 8kb. USB devices require firmware files with a length
589 * of 4kb. Certain USB chipsets however require different firmware,
590 * which Ralink only provides attached to the original firmware
591 * file. Thus for USB devices, firmware files have a length
592 * which is a multiple of 4kb. The firmware for rt3290 chip also
593 * have a length which is a multiple of 4kb.
595 if (rt2x00_is_usb(rt2x00dev
) || rt2x00_rt(rt2x00dev
, RT3290
))
602 * Validate the firmware length
604 if (len
!= fw_len
&& (!multiple
|| (len
% fw_len
) != 0))
605 return FW_BAD_LENGTH
;
608 * Check if the chipset requires one of the upper parts
611 if (rt2x00_is_usb(rt2x00dev
) &&
612 !rt2x00_rt(rt2x00dev
, RT2860
) &&
613 !rt2x00_rt(rt2x00dev
, RT2872
) &&
614 !rt2x00_rt(rt2x00dev
, RT3070
) &&
615 ((len
/ fw_len
) == 1))
616 return FW_BAD_VERSION
;
619 * 8kb firmware files must be checked as if it were
620 * 2 separate firmware files.
622 while (offset
< len
) {
623 if (!rt2800_check_firmware_crc(data
+ offset
, fw_len
))
631 EXPORT_SYMBOL_GPL(rt2800_check_firmware
);
633 int rt2800_load_firmware(struct rt2x00_dev
*rt2x00dev
,
634 const u8
*data
, const size_t len
)
640 if (rt2x00_rt(rt2x00dev
, RT3290
)) {
641 retval
= rt2800_enable_wlan_rt3290(rt2x00dev
);
647 * If driver doesn't wake up firmware here,
648 * rt2800_load_firmware will hang forever when interface is up again.
650 rt2800_register_write(rt2x00dev
, AUTOWAKEUP_CFG
, 0x00000000);
653 * Wait for stable hardware.
655 if (rt2800_wait_csr_ready(rt2x00dev
))
658 if (rt2x00_is_pci(rt2x00dev
)) {
659 if (rt2x00_rt(rt2x00dev
, RT3290
) ||
660 rt2x00_rt(rt2x00dev
, RT3572
) ||
661 rt2x00_rt(rt2x00dev
, RT5390
) ||
662 rt2x00_rt(rt2x00dev
, RT5392
)) {
663 rt2800_register_read(rt2x00dev
, AUX_CTRL
, ®
);
664 rt2x00_set_field32(®
, AUX_CTRL_FORCE_PCIE_CLK
, 1);
665 rt2x00_set_field32(®
, AUX_CTRL_WAKE_PCIE_EN
, 1);
666 rt2800_register_write(rt2x00dev
, AUX_CTRL
, reg
);
668 rt2800_register_write(rt2x00dev
, PWR_PIN_CFG
, 0x00000002);
671 rt2800_disable_wpdma(rt2x00dev
);
674 * Write firmware to the device.
676 rt2800_drv_write_firmware(rt2x00dev
, data
, len
);
679 * Wait for device to stabilize.
681 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
682 rt2800_register_read(rt2x00dev
, PBF_SYS_CTRL
, ®
);
683 if (rt2x00_get_field32(reg
, PBF_SYS_CTRL_READY
))
688 if (i
== REGISTER_BUSY_COUNT
) {
689 rt2x00_err(rt2x00dev
, "PBF system register not ready\n");
694 * Disable DMA, will be reenabled later when enabling
697 rt2800_disable_wpdma(rt2x00dev
);
700 * Initialize firmware.
702 rt2800_register_write(rt2x00dev
, H2M_BBP_AGENT
, 0);
703 rt2800_register_write(rt2x00dev
, H2M_MAILBOX_CSR
, 0);
704 if (rt2x00_is_usb(rt2x00dev
)) {
705 rt2800_register_write(rt2x00dev
, H2M_INT_SRC
, 0);
706 rt2800_mcu_request(rt2x00dev
, MCU_BOOT_SIGNAL
, 0, 0, 0);
712 EXPORT_SYMBOL_GPL(rt2800_load_firmware
);
714 void rt2800_write_tx_data(struct queue_entry
*entry
,
715 struct txentry_desc
*txdesc
)
717 __le32
*txwi
= rt2800_drv_get_txwi(entry
);
722 * Initialize TX Info descriptor
724 rt2x00_desc_read(txwi
, 0, &word
);
725 rt2x00_set_field32(&word
, TXWI_W0_FRAG
,
726 test_bit(ENTRY_TXD_MORE_FRAG
, &txdesc
->flags
));
727 rt2x00_set_field32(&word
, TXWI_W0_MIMO_PS
,
728 test_bit(ENTRY_TXD_HT_MIMO_PS
, &txdesc
->flags
));
729 rt2x00_set_field32(&word
, TXWI_W0_CF_ACK
, 0);
730 rt2x00_set_field32(&word
, TXWI_W0_TS
,
731 test_bit(ENTRY_TXD_REQ_TIMESTAMP
, &txdesc
->flags
));
732 rt2x00_set_field32(&word
, TXWI_W0_AMPDU
,
733 test_bit(ENTRY_TXD_HT_AMPDU
, &txdesc
->flags
));
734 rt2x00_set_field32(&word
, TXWI_W0_MPDU_DENSITY
,
735 txdesc
->u
.ht
.mpdu_density
);
736 rt2x00_set_field32(&word
, TXWI_W0_TX_OP
, txdesc
->u
.ht
.txop
);
737 rt2x00_set_field32(&word
, TXWI_W0_MCS
, txdesc
->u
.ht
.mcs
);
738 rt2x00_set_field32(&word
, TXWI_W0_BW
,
739 test_bit(ENTRY_TXD_HT_BW_40
, &txdesc
->flags
));
740 rt2x00_set_field32(&word
, TXWI_W0_SHORT_GI
,
741 test_bit(ENTRY_TXD_HT_SHORT_GI
, &txdesc
->flags
));
742 rt2x00_set_field32(&word
, TXWI_W0_STBC
, txdesc
->u
.ht
.stbc
);
743 rt2x00_set_field32(&word
, TXWI_W0_PHYMODE
, txdesc
->rate_mode
);
744 rt2x00_desc_write(txwi
, 0, word
);
746 rt2x00_desc_read(txwi
, 1, &word
);
747 rt2x00_set_field32(&word
, TXWI_W1_ACK
,
748 test_bit(ENTRY_TXD_ACK
, &txdesc
->flags
));
749 rt2x00_set_field32(&word
, TXWI_W1_NSEQ
,
750 test_bit(ENTRY_TXD_GENERATE_SEQ
, &txdesc
->flags
));
751 rt2x00_set_field32(&word
, TXWI_W1_BW_WIN_SIZE
, txdesc
->u
.ht
.ba_size
);
752 rt2x00_set_field32(&word
, TXWI_W1_WIRELESS_CLI_ID
,
753 test_bit(ENTRY_TXD_ENCRYPT
, &txdesc
->flags
) ?
754 txdesc
->key_idx
: txdesc
->u
.ht
.wcid
);
755 rt2x00_set_field32(&word
, TXWI_W1_MPDU_TOTAL_BYTE_COUNT
,
757 rt2x00_set_field32(&word
, TXWI_W1_PACKETID_QUEUE
, entry
->queue
->qid
);
758 rt2x00_set_field32(&word
, TXWI_W1_PACKETID_ENTRY
, (entry
->entry_idx
% 3) + 1);
759 rt2x00_desc_write(txwi
, 1, word
);
762 * Always write 0 to IV/EIV fields (word 2 and 3), hardware will insert
763 * the IV from the IVEIV register when TXD_W3_WIV is set to 0.
764 * When TXD_W3_WIV is set to 1 it will use the IV data
765 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
766 * crypto entry in the registers should be used to encrypt the frame.
768 * Nulify all remaining words as well, we don't know how to program them.
770 for (i
= 2; i
< entry
->queue
->winfo_size
/ sizeof(__le32
); i
++)
771 _rt2x00_desc_write(txwi
, i
, 0);
773 EXPORT_SYMBOL_GPL(rt2800_write_tx_data
);
775 static int rt2800_agc_to_rssi(struct rt2x00_dev
*rt2x00dev
, u32 rxwi_w2
)
777 s8 rssi0
= rt2x00_get_field32(rxwi_w2
, RXWI_W2_RSSI0
);
778 s8 rssi1
= rt2x00_get_field32(rxwi_w2
, RXWI_W2_RSSI1
);
779 s8 rssi2
= rt2x00_get_field32(rxwi_w2
, RXWI_W2_RSSI2
);
785 if (rt2x00dev
->curr_band
== IEEE80211_BAND_2GHZ
) {
786 rt2800_eeprom_read(rt2x00dev
, EEPROM_RSSI_BG
, &eeprom
);
787 offset0
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_BG_OFFSET0
);
788 offset1
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_BG_OFFSET1
);
789 rt2800_eeprom_read(rt2x00dev
, EEPROM_RSSI_BG2
, &eeprom
);
790 offset2
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_BG2_OFFSET2
);
792 rt2800_eeprom_read(rt2x00dev
, EEPROM_RSSI_A
, &eeprom
);
793 offset0
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_A_OFFSET0
);
794 offset1
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_A_OFFSET1
);
795 rt2800_eeprom_read(rt2x00dev
, EEPROM_RSSI_A2
, &eeprom
);
796 offset2
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_A2_OFFSET2
);
800 * Convert the value from the descriptor into the RSSI value
801 * If the value in the descriptor is 0, it is considered invalid
802 * and the default (extremely low) rssi value is assumed
804 rssi0
= (rssi0
) ? (-12 - offset0
- rt2x00dev
->lna_gain
- rssi0
) : -128;
805 rssi1
= (rssi1
) ? (-12 - offset1
- rt2x00dev
->lna_gain
- rssi1
) : -128;
806 rssi2
= (rssi2
) ? (-12 - offset2
- rt2x00dev
->lna_gain
- rssi2
) : -128;
809 * mac80211 only accepts a single RSSI value. Calculating the
810 * average doesn't deliver a fair answer either since -60:-60 would
811 * be considered equally good as -50:-70 while the second is the one
812 * which gives less energy...
814 rssi0
= max(rssi0
, rssi1
);
815 return (int)max(rssi0
, rssi2
);
818 void rt2800_process_rxwi(struct queue_entry
*entry
,
819 struct rxdone_entry_desc
*rxdesc
)
821 __le32
*rxwi
= (__le32
*) entry
->skb
->data
;
824 rt2x00_desc_read(rxwi
, 0, &word
);
826 rxdesc
->cipher
= rt2x00_get_field32(word
, RXWI_W0_UDF
);
827 rxdesc
->size
= rt2x00_get_field32(word
, RXWI_W0_MPDU_TOTAL_BYTE_COUNT
);
829 rt2x00_desc_read(rxwi
, 1, &word
);
831 if (rt2x00_get_field32(word
, RXWI_W1_SHORT_GI
))
832 rxdesc
->flags
|= RX_FLAG_SHORT_GI
;
834 if (rt2x00_get_field32(word
, RXWI_W1_BW
))
835 rxdesc
->flags
|= RX_FLAG_40MHZ
;
838 * Detect RX rate, always use MCS as signal type.
840 rxdesc
->dev_flags
|= RXDONE_SIGNAL_MCS
;
841 rxdesc
->signal
= rt2x00_get_field32(word
, RXWI_W1_MCS
);
842 rxdesc
->rate_mode
= rt2x00_get_field32(word
, RXWI_W1_PHYMODE
);
845 * Mask of 0x8 bit to remove the short preamble flag.
847 if (rxdesc
->rate_mode
== RATE_MODE_CCK
)
848 rxdesc
->signal
&= ~0x8;
850 rt2x00_desc_read(rxwi
, 2, &word
);
853 * Convert descriptor AGC value to RSSI value.
855 rxdesc
->rssi
= rt2800_agc_to_rssi(entry
->queue
->rt2x00dev
, word
);
857 * Remove RXWI descriptor from start of the buffer.
859 skb_pull(entry
->skb
, entry
->queue
->winfo_size
);
861 EXPORT_SYMBOL_GPL(rt2800_process_rxwi
);
863 void rt2800_txdone_entry(struct queue_entry
*entry
, u32 status
, __le32
*txwi
)
865 struct rt2x00_dev
*rt2x00dev
= entry
->queue
->rt2x00dev
;
866 struct skb_frame_desc
*skbdesc
= get_skb_frame_desc(entry
->skb
);
867 struct txdone_entry_desc txdesc
;
873 * Obtain the status about this packet.
876 rt2x00_desc_read(txwi
, 0, &word
);
878 mcs
= rt2x00_get_field32(word
, TXWI_W0_MCS
);
879 ampdu
= rt2x00_get_field32(word
, TXWI_W0_AMPDU
);
881 real_mcs
= rt2x00_get_field32(status
, TX_STA_FIFO_MCS
);
882 aggr
= rt2x00_get_field32(status
, TX_STA_FIFO_TX_AGGRE
);
885 * If a frame was meant to be sent as a single non-aggregated MPDU
886 * but ended up in an aggregate the used tx rate doesn't correlate
887 * with the one specified in the TXWI as the whole aggregate is sent
888 * with the same rate.
890 * For example: two frames are sent to rt2x00, the first one sets
891 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
892 * and requests MCS15. If the hw aggregates both frames into one
893 * AMDPU the tx status for both frames will contain MCS7 although
894 * the frame was sent successfully.
896 * Hence, replace the requested rate with the real tx rate to not
897 * confuse the rate control algortihm by providing clearly wrong
900 if (unlikely(aggr
== 1 && ampdu
== 0 && real_mcs
!= mcs
)) {
901 skbdesc
->tx_rate_idx
= real_mcs
;
905 if (aggr
== 1 || ampdu
== 1)
906 __set_bit(TXDONE_AMPDU
, &txdesc
.flags
);
909 * Ralink has a retry mechanism using a global fallback
910 * table. We setup this fallback table to try the immediate
911 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
912 * always contains the MCS used for the last transmission, be
913 * it successful or not.
915 if (rt2x00_get_field32(status
, TX_STA_FIFO_TX_SUCCESS
)) {
917 * Transmission succeeded. The number of retries is
920 __set_bit(TXDONE_SUCCESS
, &txdesc
.flags
);
921 txdesc
.retry
= ((mcs
> real_mcs
) ? mcs
- real_mcs
: 0);
924 * Transmission failed. The number of retries is
925 * always 7 in this case (for a total number of 8
928 __set_bit(TXDONE_FAILURE
, &txdesc
.flags
);
929 txdesc
.retry
= rt2x00dev
->long_retry
;
933 * the frame was retried at least once
934 * -> hw used fallback rates
937 __set_bit(TXDONE_FALLBACK
, &txdesc
.flags
);
939 rt2x00lib_txdone(entry
, &txdesc
);
941 EXPORT_SYMBOL_GPL(rt2800_txdone_entry
);
943 void rt2800_write_beacon(struct queue_entry
*entry
, struct txentry_desc
*txdesc
)
945 struct rt2x00_dev
*rt2x00dev
= entry
->queue
->rt2x00dev
;
946 struct skb_frame_desc
*skbdesc
= get_skb_frame_desc(entry
->skb
);
947 unsigned int beacon_base
;
948 unsigned int padding_len
;
950 const int txwi_desc_size
= entry
->queue
->winfo_size
;
953 * Disable beaconing while we are reloading the beacon data,
954 * otherwise we might be sending out invalid data.
956 rt2800_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
958 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_GEN
, 0);
959 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
962 * Add space for the TXWI in front of the skb.
964 memset(skb_push(entry
->skb
, txwi_desc_size
), 0, txwi_desc_size
);
967 * Register descriptor details in skb frame descriptor.
969 skbdesc
->flags
|= SKBDESC_DESC_IN_SKB
;
970 skbdesc
->desc
= entry
->skb
->data
;
971 skbdesc
->desc_len
= txwi_desc_size
;
974 * Add the TXWI for the beacon to the skb.
976 rt2800_write_tx_data(entry
, txdesc
);
979 * Dump beacon to userspace through debugfs.
981 rt2x00debug_dump_frame(rt2x00dev
, DUMP_FRAME_BEACON
, entry
->skb
);
984 * Write entire beacon with TXWI and padding to register.
986 padding_len
= roundup(entry
->skb
->len
, 4) - entry
->skb
->len
;
987 if (padding_len
&& skb_pad(entry
->skb
, padding_len
)) {
988 rt2x00_err(rt2x00dev
, "Failure padding beacon, aborting\n");
989 /* skb freed by skb_pad() on failure */
991 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, orig_reg
);
995 beacon_base
= HW_BEACON_BASE(entry
->entry_idx
);
996 rt2800_register_multiwrite(rt2x00dev
, beacon_base
, entry
->skb
->data
,
997 entry
->skb
->len
+ padding_len
);
1000 * Enable beaconing again.
1002 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_GEN
, 1);
1003 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
1006 * Clean up beacon skb.
1008 dev_kfree_skb_any(entry
->skb
);
1011 EXPORT_SYMBOL_GPL(rt2800_write_beacon
);
1013 static inline void rt2800_clear_beacon_register(struct rt2x00_dev
*rt2x00dev
,
1017 const int txwi_desc_size
= rt2x00dev
->bcn
->winfo_size
;
1018 unsigned int beacon_base
;
1020 beacon_base
= HW_BEACON_BASE(index
);
1023 * For the Beacon base registers we only need to clear
1024 * the whole TXWI which (when set to 0) will invalidate
1025 * the entire beacon.
1027 for (i
= 0; i
< txwi_desc_size
; i
+= sizeof(__le32
))
1028 rt2800_register_write(rt2x00dev
, beacon_base
+ i
, 0);
1031 void rt2800_clear_beacon(struct queue_entry
*entry
)
1033 struct rt2x00_dev
*rt2x00dev
= entry
->queue
->rt2x00dev
;
1037 * Disable beaconing while we are reloading the beacon data,
1038 * otherwise we might be sending out invalid data.
1040 rt2800_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
1041 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_GEN
, 0);
1042 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
1047 rt2800_clear_beacon_register(rt2x00dev
, entry
->entry_idx
);
1050 * Enabled beaconing again.
1052 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_GEN
, 1);
1053 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
1055 EXPORT_SYMBOL_GPL(rt2800_clear_beacon
);
1057 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1058 const struct rt2x00debug rt2800_rt2x00debug
= {
1059 .owner
= THIS_MODULE
,
1061 .read
= rt2800_register_read
,
1062 .write
= rt2800_register_write
,
1063 .flags
= RT2X00DEBUGFS_OFFSET
,
1064 .word_base
= CSR_REG_BASE
,
1065 .word_size
= sizeof(u32
),
1066 .word_count
= CSR_REG_SIZE
/ sizeof(u32
),
1069 /* NOTE: The local EEPROM access functions can't
1070 * be used here, use the generic versions instead.
1072 .read
= rt2x00_eeprom_read
,
1073 .write
= rt2x00_eeprom_write
,
1074 .word_base
= EEPROM_BASE
,
1075 .word_size
= sizeof(u16
),
1076 .word_count
= EEPROM_SIZE
/ sizeof(u16
),
1079 .read
= rt2800_bbp_read
,
1080 .write
= rt2800_bbp_write
,
1081 .word_base
= BBP_BASE
,
1082 .word_size
= sizeof(u8
),
1083 .word_count
= BBP_SIZE
/ sizeof(u8
),
1086 .read
= rt2x00_rf_read
,
1087 .write
= rt2800_rf_write
,
1088 .word_base
= RF_BASE
,
1089 .word_size
= sizeof(u32
),
1090 .word_count
= RF_SIZE
/ sizeof(u32
),
1093 .read
= rt2800_rfcsr_read
,
1094 .write
= rt2800_rfcsr_write
,
1095 .word_base
= RFCSR_BASE
,
1096 .word_size
= sizeof(u8
),
1097 .word_count
= RFCSR_SIZE
/ sizeof(u8
),
1100 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug
);
1101 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1103 int rt2800_rfkill_poll(struct rt2x00_dev
*rt2x00dev
)
1107 if (rt2x00_rt(rt2x00dev
, RT3290
)) {
1108 rt2800_register_read(rt2x00dev
, WLAN_FUN_CTRL
, ®
);
1109 return rt2x00_get_field32(reg
, WLAN_GPIO_IN_BIT0
);
1111 rt2800_register_read(rt2x00dev
, GPIO_CTRL
, ®
);
1112 return rt2x00_get_field32(reg
, GPIO_CTRL_VAL2
);
1115 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll
);
1117 #ifdef CONFIG_RT2X00_LIB_LEDS
1118 static void rt2800_brightness_set(struct led_classdev
*led_cdev
,
1119 enum led_brightness brightness
)
1121 struct rt2x00_led
*led
=
1122 container_of(led_cdev
, struct rt2x00_led
, led_dev
);
1123 unsigned int enabled
= brightness
!= LED_OFF
;
1124 unsigned int bg_mode
=
1125 (enabled
&& led
->rt2x00dev
->curr_band
== IEEE80211_BAND_2GHZ
);
1126 unsigned int polarity
=
1127 rt2x00_get_field16(led
->rt2x00dev
->led_mcu_reg
,
1128 EEPROM_FREQ_LED_POLARITY
);
1129 unsigned int ledmode
=
1130 rt2x00_get_field16(led
->rt2x00dev
->led_mcu_reg
,
1131 EEPROM_FREQ_LED_MODE
);
1134 /* Check for SoC (SOC devices don't support MCU requests) */
1135 if (rt2x00_is_soc(led
->rt2x00dev
)) {
1136 rt2800_register_read(led
->rt2x00dev
, LED_CFG
, ®
);
1138 /* Set LED Polarity */
1139 rt2x00_set_field32(®
, LED_CFG_LED_POLAR
, polarity
);
1142 if (led
->type
== LED_TYPE_RADIO
) {
1143 rt2x00_set_field32(®
, LED_CFG_G_LED_MODE
,
1145 } else if (led
->type
== LED_TYPE_ASSOC
) {
1146 rt2x00_set_field32(®
, LED_CFG_Y_LED_MODE
,
1148 } else if (led
->type
== LED_TYPE_QUALITY
) {
1149 rt2x00_set_field32(®
, LED_CFG_R_LED_MODE
,
1153 rt2800_register_write(led
->rt2x00dev
, LED_CFG
, reg
);
1156 if (led
->type
== LED_TYPE_RADIO
) {
1157 rt2800_mcu_request(led
->rt2x00dev
, MCU_LED
, 0xff, ledmode
,
1158 enabled
? 0x20 : 0);
1159 } else if (led
->type
== LED_TYPE_ASSOC
) {
1160 rt2800_mcu_request(led
->rt2x00dev
, MCU_LED
, 0xff, ledmode
,
1161 enabled
? (bg_mode
? 0x60 : 0xa0) : 0x20);
1162 } else if (led
->type
== LED_TYPE_QUALITY
) {
1164 * The brightness is divided into 6 levels (0 - 5),
1165 * The specs tell us the following levels:
1166 * 0, 1 ,3, 7, 15, 31
1167 * to determine the level in a simple way we can simply
1168 * work with bitshifting:
1171 rt2800_mcu_request(led
->rt2x00dev
, MCU_LED_STRENGTH
, 0xff,
1172 (1 << brightness
/ (LED_FULL
/ 6)) - 1,
1178 static void rt2800_init_led(struct rt2x00_dev
*rt2x00dev
,
1179 struct rt2x00_led
*led
, enum led_type type
)
1181 led
->rt2x00dev
= rt2x00dev
;
1183 led
->led_dev
.brightness_set
= rt2800_brightness_set
;
1184 led
->flags
= LED_INITIALIZED
;
1186 #endif /* CONFIG_RT2X00_LIB_LEDS */
1189 * Configuration handlers.
1191 static void rt2800_config_wcid(struct rt2x00_dev
*rt2x00dev
,
1195 struct mac_wcid_entry wcid_entry
;
1198 offset
= MAC_WCID_ENTRY(wcid
);
1200 memset(&wcid_entry
, 0xff, sizeof(wcid_entry
));
1202 memcpy(wcid_entry
.mac
, address
, ETH_ALEN
);
1204 rt2800_register_multiwrite(rt2x00dev
, offset
,
1205 &wcid_entry
, sizeof(wcid_entry
));
1208 static void rt2800_delete_wcid_attr(struct rt2x00_dev
*rt2x00dev
, int wcid
)
1211 offset
= MAC_WCID_ATTR_ENTRY(wcid
);
1212 rt2800_register_write(rt2x00dev
, offset
, 0);
1215 static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev
*rt2x00dev
,
1216 int wcid
, u32 bssidx
)
1218 u32 offset
= MAC_WCID_ATTR_ENTRY(wcid
);
1222 * The BSS Idx numbers is split in a main value of 3 bits,
1223 * and a extended field for adding one additional bit to the value.
1225 rt2800_register_read(rt2x00dev
, offset
, ®
);
1226 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_BSS_IDX
, (bssidx
& 0x7));
1227 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT
,
1228 (bssidx
& 0x8) >> 3);
1229 rt2800_register_write(rt2x00dev
, offset
, reg
);
1232 static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev
*rt2x00dev
,
1233 struct rt2x00lib_crypto
*crypto
,
1234 struct ieee80211_key_conf
*key
)
1236 struct mac_iveiv_entry iveiv_entry
;
1240 offset
= MAC_WCID_ATTR_ENTRY(key
->hw_key_idx
);
1242 if (crypto
->cmd
== SET_KEY
) {
1243 rt2800_register_read(rt2x00dev
, offset
, ®
);
1244 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_KEYTAB
,
1245 !!(key
->flags
& IEEE80211_KEY_FLAG_PAIRWISE
));
1247 * Both the cipher as the BSS Idx numbers are split in a main
1248 * value of 3 bits, and a extended field for adding one additional
1251 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_CIPHER
,
1252 (crypto
->cipher
& 0x7));
1253 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_CIPHER_EXT
,
1254 (crypto
->cipher
& 0x8) >> 3);
1255 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_RX_WIUDF
, crypto
->cipher
);
1256 rt2800_register_write(rt2x00dev
, offset
, reg
);
1258 /* Delete the cipher without touching the bssidx */
1259 rt2800_register_read(rt2x00dev
, offset
, ®
);
1260 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_KEYTAB
, 0);
1261 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_CIPHER
, 0);
1262 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_CIPHER_EXT
, 0);
1263 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_RX_WIUDF
, 0);
1264 rt2800_register_write(rt2x00dev
, offset
, reg
);
1267 offset
= MAC_IVEIV_ENTRY(key
->hw_key_idx
);
1269 memset(&iveiv_entry
, 0, sizeof(iveiv_entry
));
1270 if ((crypto
->cipher
== CIPHER_TKIP
) ||
1271 (crypto
->cipher
== CIPHER_TKIP_NO_MIC
) ||
1272 (crypto
->cipher
== CIPHER_AES
))
1273 iveiv_entry
.iv
[3] |= 0x20;
1274 iveiv_entry
.iv
[3] |= key
->keyidx
<< 6;
1275 rt2800_register_multiwrite(rt2x00dev
, offset
,
1276 &iveiv_entry
, sizeof(iveiv_entry
));
1279 int rt2800_config_shared_key(struct rt2x00_dev
*rt2x00dev
,
1280 struct rt2x00lib_crypto
*crypto
,
1281 struct ieee80211_key_conf
*key
)
1283 struct hw_key_entry key_entry
;
1284 struct rt2x00_field32 field
;
1288 if (crypto
->cmd
== SET_KEY
) {
1289 key
->hw_key_idx
= (4 * crypto
->bssidx
) + key
->keyidx
;
1291 memcpy(key_entry
.key
, crypto
->key
,
1292 sizeof(key_entry
.key
));
1293 memcpy(key_entry
.tx_mic
, crypto
->tx_mic
,
1294 sizeof(key_entry
.tx_mic
));
1295 memcpy(key_entry
.rx_mic
, crypto
->rx_mic
,
1296 sizeof(key_entry
.rx_mic
));
1298 offset
= SHARED_KEY_ENTRY(key
->hw_key_idx
);
1299 rt2800_register_multiwrite(rt2x00dev
, offset
,
1300 &key_entry
, sizeof(key_entry
));
1304 * The cipher types are stored over multiple registers
1305 * starting with SHARED_KEY_MODE_BASE each word will have
1306 * 32 bits and contains the cipher types for 2 bssidx each.
1307 * Using the correct defines correctly will cause overhead,
1308 * so just calculate the correct offset.
1310 field
.bit_offset
= 4 * (key
->hw_key_idx
% 8);
1311 field
.bit_mask
= 0x7 << field
.bit_offset
;
1313 offset
= SHARED_KEY_MODE_ENTRY(key
->hw_key_idx
/ 8);
1315 rt2800_register_read(rt2x00dev
, offset
, ®
);
1316 rt2x00_set_field32(®
, field
,
1317 (crypto
->cmd
== SET_KEY
) * crypto
->cipher
);
1318 rt2800_register_write(rt2x00dev
, offset
, reg
);
1321 * Update WCID information
1323 rt2800_config_wcid(rt2x00dev
, crypto
->address
, key
->hw_key_idx
);
1324 rt2800_config_wcid_attr_bssidx(rt2x00dev
, key
->hw_key_idx
,
1326 rt2800_config_wcid_attr_cipher(rt2x00dev
, crypto
, key
);
1330 EXPORT_SYMBOL_GPL(rt2800_config_shared_key
);
1332 static inline int rt2800_find_wcid(struct rt2x00_dev
*rt2x00dev
)
1334 struct mac_wcid_entry wcid_entry
;
1339 * Search for the first free WCID entry and return the corresponding
1342 * Make sure the WCID starts _after_ the last possible shared key
1345 * Since parts of the pairwise key table might be shared with
1346 * the beacon frame buffers 6 & 7 we should only write into the
1347 * first 222 entries.
1349 for (idx
= 33; idx
<= 222; idx
++) {
1350 offset
= MAC_WCID_ENTRY(idx
);
1351 rt2800_register_multiread(rt2x00dev
, offset
, &wcid_entry
,
1352 sizeof(wcid_entry
));
1353 if (is_broadcast_ether_addr(wcid_entry
.mac
))
1358 * Use -1 to indicate that we don't have any more space in the WCID
1364 int rt2800_config_pairwise_key(struct rt2x00_dev
*rt2x00dev
,
1365 struct rt2x00lib_crypto
*crypto
,
1366 struct ieee80211_key_conf
*key
)
1368 struct hw_key_entry key_entry
;
1371 if (crypto
->cmd
== SET_KEY
) {
1373 * Allow key configuration only for STAs that are
1376 if (crypto
->wcid
< 0)
1378 key
->hw_key_idx
= crypto
->wcid
;
1380 memcpy(key_entry
.key
, crypto
->key
,
1381 sizeof(key_entry
.key
));
1382 memcpy(key_entry
.tx_mic
, crypto
->tx_mic
,
1383 sizeof(key_entry
.tx_mic
));
1384 memcpy(key_entry
.rx_mic
, crypto
->rx_mic
,
1385 sizeof(key_entry
.rx_mic
));
1387 offset
= PAIRWISE_KEY_ENTRY(key
->hw_key_idx
);
1388 rt2800_register_multiwrite(rt2x00dev
, offset
,
1389 &key_entry
, sizeof(key_entry
));
1393 * Update WCID information
1395 rt2800_config_wcid_attr_cipher(rt2x00dev
, crypto
, key
);
1399 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key
);
1401 int rt2800_sta_add(struct rt2x00_dev
*rt2x00dev
, struct ieee80211_vif
*vif
,
1402 struct ieee80211_sta
*sta
)
1405 struct rt2x00_sta
*sta_priv
= sta_to_rt2x00_sta(sta
);
1408 * Find next free WCID.
1410 wcid
= rt2800_find_wcid(rt2x00dev
);
1413 * Store selected wcid even if it is invalid so that we can
1414 * later decide if the STA is uploaded into the hw.
1416 sta_priv
->wcid
= wcid
;
1419 * No space left in the device, however, we can still communicate
1420 * with the STA -> No error.
1426 * Clean up WCID attributes and write STA address to the device.
1428 rt2800_delete_wcid_attr(rt2x00dev
, wcid
);
1429 rt2800_config_wcid(rt2x00dev
, sta
->addr
, wcid
);
1430 rt2800_config_wcid_attr_bssidx(rt2x00dev
, wcid
,
1431 rt2x00lib_get_bssidx(rt2x00dev
, vif
));
1434 EXPORT_SYMBOL_GPL(rt2800_sta_add
);
1436 int rt2800_sta_remove(struct rt2x00_dev
*rt2x00dev
, int wcid
)
1439 * Remove WCID entry, no need to clean the attributes as they will
1440 * get renewed when the WCID is reused.
1442 rt2800_config_wcid(rt2x00dev
, NULL
, wcid
);
1446 EXPORT_SYMBOL_GPL(rt2800_sta_remove
);
1448 void rt2800_config_filter(struct rt2x00_dev
*rt2x00dev
,
1449 const unsigned int filter_flags
)
1454 * Start configuration steps.
1455 * Note that the version error will always be dropped
1456 * and broadcast frames will always be accepted since
1457 * there is no filter for it at this time.
1459 rt2800_register_read(rt2x00dev
, RX_FILTER_CFG
, ®
);
1460 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CRC_ERROR
,
1461 !(filter_flags
& FIF_FCSFAIL
));
1462 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_PHY_ERROR
,
1463 !(filter_flags
& FIF_PLCPFAIL
));
1464 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_NOT_TO_ME
,
1465 !(filter_flags
& FIF_PROMISC_IN_BSS
));
1466 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_NOT_MY_BSSD
, 0);
1467 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_VER_ERROR
, 1);
1468 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_MULTICAST
,
1469 !(filter_flags
& FIF_ALLMULTI
));
1470 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_BROADCAST
, 0);
1471 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_DUPLICATE
, 1);
1472 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CF_END_ACK
,
1473 !(filter_flags
& FIF_CONTROL
));
1474 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CF_END
,
1475 !(filter_flags
& FIF_CONTROL
));
1476 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_ACK
,
1477 !(filter_flags
& FIF_CONTROL
));
1478 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CTS
,
1479 !(filter_flags
& FIF_CONTROL
));
1480 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_RTS
,
1481 !(filter_flags
& FIF_CONTROL
));
1482 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_PSPOLL
,
1483 !(filter_flags
& FIF_PSPOLL
));
1484 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_BA
, 0);
1485 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_BAR
,
1486 !(filter_flags
& FIF_CONTROL
));
1487 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CNTL
,
1488 !(filter_flags
& FIF_CONTROL
));
1489 rt2800_register_write(rt2x00dev
, RX_FILTER_CFG
, reg
);
1491 EXPORT_SYMBOL_GPL(rt2800_config_filter
);
1493 void rt2800_config_intf(struct rt2x00_dev
*rt2x00dev
, struct rt2x00_intf
*intf
,
1494 struct rt2x00intf_conf
*conf
, const unsigned int flags
)
1497 bool update_bssid
= false;
1499 if (flags
& CONFIG_UPDATE_TYPE
) {
1501 * Enable synchronisation.
1503 rt2800_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
1504 rt2x00_set_field32(®
, BCN_TIME_CFG_TSF_SYNC
, conf
->sync
);
1505 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
1507 if (conf
->sync
== TSF_SYNC_AP_NONE
) {
1509 * Tune beacon queue transmit parameters for AP mode
1511 rt2800_register_read(rt2x00dev
, TBTT_SYNC_CFG
, ®
);
1512 rt2x00_set_field32(®
, TBTT_SYNC_CFG_BCN_CWMIN
, 0);
1513 rt2x00_set_field32(®
, TBTT_SYNC_CFG_BCN_AIFSN
, 1);
1514 rt2x00_set_field32(®
, TBTT_SYNC_CFG_BCN_EXP_WIN
, 32);
1515 rt2x00_set_field32(®
, TBTT_SYNC_CFG_TBTT_ADJUST
, 0);
1516 rt2800_register_write(rt2x00dev
, TBTT_SYNC_CFG
, reg
);
1518 rt2800_register_read(rt2x00dev
, TBTT_SYNC_CFG
, ®
);
1519 rt2x00_set_field32(®
, TBTT_SYNC_CFG_BCN_CWMIN
, 4);
1520 rt2x00_set_field32(®
, TBTT_SYNC_CFG_BCN_AIFSN
, 2);
1521 rt2x00_set_field32(®
, TBTT_SYNC_CFG_BCN_EXP_WIN
, 32);
1522 rt2x00_set_field32(®
, TBTT_SYNC_CFG_TBTT_ADJUST
, 16);
1523 rt2800_register_write(rt2x00dev
, TBTT_SYNC_CFG
, reg
);
1527 if (flags
& CONFIG_UPDATE_MAC
) {
1528 if (flags
& CONFIG_UPDATE_TYPE
&&
1529 conf
->sync
== TSF_SYNC_AP_NONE
) {
1531 * The BSSID register has to be set to our own mac
1532 * address in AP mode.
1534 memcpy(conf
->bssid
, conf
->mac
, sizeof(conf
->mac
));
1535 update_bssid
= true;
1538 if (!is_zero_ether_addr((const u8
*)conf
->mac
)) {
1539 reg
= le32_to_cpu(conf
->mac
[1]);
1540 rt2x00_set_field32(®
, MAC_ADDR_DW1_UNICAST_TO_ME_MASK
, 0xff);
1541 conf
->mac
[1] = cpu_to_le32(reg
);
1544 rt2800_register_multiwrite(rt2x00dev
, MAC_ADDR_DW0
,
1545 conf
->mac
, sizeof(conf
->mac
));
1548 if ((flags
& CONFIG_UPDATE_BSSID
) || update_bssid
) {
1549 if (!is_zero_ether_addr((const u8
*)conf
->bssid
)) {
1550 reg
= le32_to_cpu(conf
->bssid
[1]);
1551 rt2x00_set_field32(®
, MAC_BSSID_DW1_BSS_ID_MASK
, 3);
1552 rt2x00_set_field32(®
, MAC_BSSID_DW1_BSS_BCN_NUM
, 7);
1553 conf
->bssid
[1] = cpu_to_le32(reg
);
1556 rt2800_register_multiwrite(rt2x00dev
, MAC_BSSID_DW0
,
1557 conf
->bssid
, sizeof(conf
->bssid
));
1560 EXPORT_SYMBOL_GPL(rt2800_config_intf
);
1562 static void rt2800_config_ht_opmode(struct rt2x00_dev
*rt2x00dev
,
1563 struct rt2x00lib_erp
*erp
)
1565 bool any_sta_nongf
= !!(erp
->ht_opmode
&
1566 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT
);
1567 u8 protection
= erp
->ht_opmode
& IEEE80211_HT_OP_MODE_PROTECTION
;
1568 u8 mm20_mode
, mm40_mode
, gf20_mode
, gf40_mode
;
1569 u16 mm20_rate
, mm40_rate
, gf20_rate
, gf40_rate
;
1572 /* default protection rate for HT20: OFDM 24M */
1573 mm20_rate
= gf20_rate
= 0x4004;
1575 /* default protection rate for HT40: duplicate OFDM 24M */
1576 mm40_rate
= gf40_rate
= 0x4084;
1578 switch (protection
) {
1579 case IEEE80211_HT_OP_MODE_PROTECTION_NONE
:
1581 * All STAs in this BSS are HT20/40 but there might be
1582 * STAs not supporting greenfield mode.
1583 * => Disable protection for HT transmissions.
1585 mm20_mode
= mm40_mode
= gf20_mode
= gf40_mode
= 0;
1588 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ
:
1590 * All STAs in this BSS are HT20 or HT20/40 but there
1591 * might be STAs not supporting greenfield mode.
1592 * => Protect all HT40 transmissions.
1594 mm20_mode
= gf20_mode
= 0;
1595 mm40_mode
= gf40_mode
= 2;
1598 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER
:
1600 * Nonmember protection:
1601 * According to 802.11n we _should_ protect all
1602 * HT transmissions (but we don't have to).
1604 * But if cts_protection is enabled we _shall_ protect
1605 * all HT transmissions using a CCK rate.
1607 * And if any station is non GF we _shall_ protect
1610 * We decide to protect everything
1611 * -> fall through to mixed mode.
1613 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED
:
1615 * Legacy STAs are present
1616 * => Protect all HT transmissions.
1618 mm20_mode
= mm40_mode
= gf20_mode
= gf40_mode
= 2;
1621 * If erp protection is needed we have to protect HT
1622 * transmissions with CCK 11M long preamble.
1624 if (erp
->cts_protection
) {
1625 /* don't duplicate RTS/CTS in CCK mode */
1626 mm20_rate
= mm40_rate
= 0x0003;
1627 gf20_rate
= gf40_rate
= 0x0003;
1632 /* check for STAs not supporting greenfield mode */
1634 gf20_mode
= gf40_mode
= 2;
1636 /* Update HT protection config */
1637 rt2800_register_read(rt2x00dev
, MM20_PROT_CFG
, ®
);
1638 rt2x00_set_field32(®
, MM20_PROT_CFG_PROTECT_RATE
, mm20_rate
);
1639 rt2x00_set_field32(®
, MM20_PROT_CFG_PROTECT_CTRL
, mm20_mode
);
1640 rt2800_register_write(rt2x00dev
, MM20_PROT_CFG
, reg
);
1642 rt2800_register_read(rt2x00dev
, MM40_PROT_CFG
, ®
);
1643 rt2x00_set_field32(®
, MM40_PROT_CFG_PROTECT_RATE
, mm40_rate
);
1644 rt2x00_set_field32(®
, MM40_PROT_CFG_PROTECT_CTRL
, mm40_mode
);
1645 rt2800_register_write(rt2x00dev
, MM40_PROT_CFG
, reg
);
1647 rt2800_register_read(rt2x00dev
, GF20_PROT_CFG
, ®
);
1648 rt2x00_set_field32(®
, GF20_PROT_CFG_PROTECT_RATE
, gf20_rate
);
1649 rt2x00_set_field32(®
, GF20_PROT_CFG_PROTECT_CTRL
, gf20_mode
);
1650 rt2800_register_write(rt2x00dev
, GF20_PROT_CFG
, reg
);
1652 rt2800_register_read(rt2x00dev
, GF40_PROT_CFG
, ®
);
1653 rt2x00_set_field32(®
, GF40_PROT_CFG_PROTECT_RATE
, gf40_rate
);
1654 rt2x00_set_field32(®
, GF40_PROT_CFG_PROTECT_CTRL
, gf40_mode
);
1655 rt2800_register_write(rt2x00dev
, GF40_PROT_CFG
, reg
);
1658 void rt2800_config_erp(struct rt2x00_dev
*rt2x00dev
, struct rt2x00lib_erp
*erp
,
1663 if (changed
& BSS_CHANGED_ERP_PREAMBLE
) {
1664 rt2800_register_read(rt2x00dev
, AUTO_RSP_CFG
, ®
);
1665 rt2x00_set_field32(®
, AUTO_RSP_CFG_BAC_ACK_POLICY
,
1666 !!erp
->short_preamble
);
1667 rt2x00_set_field32(®
, AUTO_RSP_CFG_AR_PREAMBLE
,
1668 !!erp
->short_preamble
);
1669 rt2800_register_write(rt2x00dev
, AUTO_RSP_CFG
, reg
);
1672 if (changed
& BSS_CHANGED_ERP_CTS_PROT
) {
1673 rt2800_register_read(rt2x00dev
, OFDM_PROT_CFG
, ®
);
1674 rt2x00_set_field32(®
, OFDM_PROT_CFG_PROTECT_CTRL
,
1675 erp
->cts_protection
? 2 : 0);
1676 rt2800_register_write(rt2x00dev
, OFDM_PROT_CFG
, reg
);
1679 if (changed
& BSS_CHANGED_BASIC_RATES
) {
1680 rt2800_register_write(rt2x00dev
, LEGACY_BASIC_RATE
,
1682 rt2800_register_write(rt2x00dev
, HT_BASIC_RATE
, 0x00008003);
1685 if (changed
& BSS_CHANGED_ERP_SLOT
) {
1686 rt2800_register_read(rt2x00dev
, BKOFF_SLOT_CFG
, ®
);
1687 rt2x00_set_field32(®
, BKOFF_SLOT_CFG_SLOT_TIME
,
1689 rt2800_register_write(rt2x00dev
, BKOFF_SLOT_CFG
, reg
);
1691 rt2800_register_read(rt2x00dev
, XIFS_TIME_CFG
, ®
);
1692 rt2x00_set_field32(®
, XIFS_TIME_CFG_EIFS
, erp
->eifs
);
1693 rt2800_register_write(rt2x00dev
, XIFS_TIME_CFG
, reg
);
1696 if (changed
& BSS_CHANGED_BEACON_INT
) {
1697 rt2800_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
1698 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_INTERVAL
,
1699 erp
->beacon_int
* 16);
1700 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
1703 if (changed
& BSS_CHANGED_HT
)
1704 rt2800_config_ht_opmode(rt2x00dev
, erp
);
1706 EXPORT_SYMBOL_GPL(rt2800_config_erp
);
1708 static void rt2800_config_3572bt_ant(struct rt2x00_dev
*rt2x00dev
)
1712 u8 led_ctrl
, led_g_mode
, led_r_mode
;
1714 rt2800_register_read(rt2x00dev
, GPIO_SWITCH
, ®
);
1715 if (rt2x00dev
->curr_band
== IEEE80211_BAND_5GHZ
) {
1716 rt2x00_set_field32(®
, GPIO_SWITCH_0
, 1);
1717 rt2x00_set_field32(®
, GPIO_SWITCH_1
, 1);
1719 rt2x00_set_field32(®
, GPIO_SWITCH_0
, 0);
1720 rt2x00_set_field32(®
, GPIO_SWITCH_1
, 0);
1722 rt2800_register_write(rt2x00dev
, GPIO_SWITCH
, reg
);
1724 rt2800_register_read(rt2x00dev
, LED_CFG
, ®
);
1725 led_g_mode
= rt2x00_get_field32(reg
, LED_CFG_LED_POLAR
) ? 3 : 0;
1726 led_r_mode
= rt2x00_get_field32(reg
, LED_CFG_LED_POLAR
) ? 0 : 3;
1727 if (led_g_mode
!= rt2x00_get_field32(reg
, LED_CFG_G_LED_MODE
) ||
1728 led_r_mode
!= rt2x00_get_field32(reg
, LED_CFG_R_LED_MODE
)) {
1729 rt2800_eeprom_read(rt2x00dev
, EEPROM_FREQ
, &eeprom
);
1730 led_ctrl
= rt2x00_get_field16(eeprom
, EEPROM_FREQ_LED_MODE
);
1731 if (led_ctrl
== 0 || led_ctrl
> 0x40) {
1732 rt2x00_set_field32(®
, LED_CFG_G_LED_MODE
, led_g_mode
);
1733 rt2x00_set_field32(®
, LED_CFG_R_LED_MODE
, led_r_mode
);
1734 rt2800_register_write(rt2x00dev
, LED_CFG
, reg
);
1736 rt2800_mcu_request(rt2x00dev
, MCU_BAND_SELECT
, 0xff,
1737 (led_g_mode
<< 2) | led_r_mode
, 1);
1742 static void rt2800_set_ant_diversity(struct rt2x00_dev
*rt2x00dev
,
1746 u8 eesk_pin
= (ant
== ANTENNA_A
) ? 1 : 0;
1747 u8 gpio_bit3
= (ant
== ANTENNA_A
) ? 0 : 1;
1749 if (rt2x00_is_pci(rt2x00dev
)) {
1750 rt2800_register_read(rt2x00dev
, E2PROM_CSR
, ®
);
1751 rt2x00_set_field32(®
, E2PROM_CSR_DATA_CLOCK
, eesk_pin
);
1752 rt2800_register_write(rt2x00dev
, E2PROM_CSR
, reg
);
1753 } else if (rt2x00_is_usb(rt2x00dev
))
1754 rt2800_mcu_request(rt2x00dev
, MCU_ANT_SELECT
, 0xff,
1757 rt2800_register_read(rt2x00dev
, GPIO_CTRL
, ®
);
1758 rt2x00_set_field32(®
, GPIO_CTRL_DIR3
, 0);
1759 rt2x00_set_field32(®
, GPIO_CTRL_VAL3
, gpio_bit3
);
1760 rt2800_register_write(rt2x00dev
, GPIO_CTRL
, reg
);
1763 void rt2800_config_ant(struct rt2x00_dev
*rt2x00dev
, struct antenna_setup
*ant
)
1769 rt2800_bbp_read(rt2x00dev
, 1, &r1
);
1770 rt2800_bbp_read(rt2x00dev
, 3, &r3
);
1772 if (rt2x00_rt(rt2x00dev
, RT3572
) &&
1773 test_bit(CAPABILITY_BT_COEXIST
, &rt2x00dev
->cap_flags
))
1774 rt2800_config_3572bt_ant(rt2x00dev
);
1777 * Configure the TX antenna.
1779 switch (ant
->tx_chain_num
) {
1781 rt2x00_set_field8(&r1
, BBP1_TX_ANTENNA
, 0);
1784 if (rt2x00_rt(rt2x00dev
, RT3572
) &&
1785 test_bit(CAPABILITY_BT_COEXIST
, &rt2x00dev
->cap_flags
))
1786 rt2x00_set_field8(&r1
, BBP1_TX_ANTENNA
, 1);
1788 rt2x00_set_field8(&r1
, BBP1_TX_ANTENNA
, 2);
1791 rt2x00_set_field8(&r1
, BBP1_TX_ANTENNA
, 2);
1796 * Configure the RX antenna.
1798 switch (ant
->rx_chain_num
) {
1800 if (rt2x00_rt(rt2x00dev
, RT3070
) ||
1801 rt2x00_rt(rt2x00dev
, RT3090
) ||
1802 rt2x00_rt(rt2x00dev
, RT3352
) ||
1803 rt2x00_rt(rt2x00dev
, RT3390
)) {
1804 rt2800_eeprom_read(rt2x00dev
,
1805 EEPROM_NIC_CONF1
, &eeprom
);
1806 if (rt2x00_get_field16(eeprom
,
1807 EEPROM_NIC_CONF1_ANT_DIVERSITY
))
1808 rt2800_set_ant_diversity(rt2x00dev
,
1809 rt2x00dev
->default_ant
.rx
);
1811 rt2x00_set_field8(&r3
, BBP3_RX_ANTENNA
, 0);
1814 if (rt2x00_rt(rt2x00dev
, RT3572
) &&
1815 test_bit(CAPABILITY_BT_COEXIST
, &rt2x00dev
->cap_flags
)) {
1816 rt2x00_set_field8(&r3
, BBP3_RX_ADC
, 1);
1817 rt2x00_set_field8(&r3
, BBP3_RX_ANTENNA
,
1818 rt2x00dev
->curr_band
== IEEE80211_BAND_5GHZ
);
1819 rt2800_set_ant_diversity(rt2x00dev
, ANTENNA_B
);
1821 rt2x00_set_field8(&r3
, BBP3_RX_ANTENNA
, 1);
1825 rt2x00_set_field8(&r3
, BBP3_RX_ANTENNA
, 2);
1829 rt2800_bbp_write(rt2x00dev
, 3, r3
);
1830 rt2800_bbp_write(rt2x00dev
, 1, r1
);
1832 if (rt2x00_rt(rt2x00dev
, RT3593
)) {
1833 if (ant
->rx_chain_num
== 1)
1834 rt2800_bbp_write(rt2x00dev
, 86, 0x00);
1836 rt2800_bbp_write(rt2x00dev
, 86, 0x46);
1839 EXPORT_SYMBOL_GPL(rt2800_config_ant
);
1841 static void rt2800_config_lna_gain(struct rt2x00_dev
*rt2x00dev
,
1842 struct rt2x00lib_conf
*libconf
)
1847 if (libconf
->rf
.channel
<= 14) {
1848 rt2800_eeprom_read(rt2x00dev
, EEPROM_LNA
, &eeprom
);
1849 lna_gain
= rt2x00_get_field16(eeprom
, EEPROM_LNA_BG
);
1850 } else if (libconf
->rf
.channel
<= 64) {
1851 rt2800_eeprom_read(rt2x00dev
, EEPROM_LNA
, &eeprom
);
1852 lna_gain
= rt2x00_get_field16(eeprom
, EEPROM_LNA_A0
);
1853 } else if (libconf
->rf
.channel
<= 128) {
1854 if (rt2x00_rt(rt2x00dev
, RT3593
)) {
1855 rt2800_eeprom_read(rt2x00dev
, EEPROM_EXT_LNA2
, &eeprom
);
1856 lna_gain
= rt2x00_get_field16(eeprom
,
1857 EEPROM_EXT_LNA2_A1
);
1859 rt2800_eeprom_read(rt2x00dev
, EEPROM_RSSI_BG2
, &eeprom
);
1860 lna_gain
= rt2x00_get_field16(eeprom
,
1861 EEPROM_RSSI_BG2_LNA_A1
);
1864 if (rt2x00_rt(rt2x00dev
, RT3593
)) {
1865 rt2800_eeprom_read(rt2x00dev
, EEPROM_EXT_LNA2
, &eeprom
);
1866 lna_gain
= rt2x00_get_field16(eeprom
,
1867 EEPROM_EXT_LNA2_A2
);
1869 rt2800_eeprom_read(rt2x00dev
, EEPROM_RSSI_A2
, &eeprom
);
1870 lna_gain
= rt2x00_get_field16(eeprom
,
1871 EEPROM_RSSI_A2_LNA_A2
);
1875 rt2x00dev
->lna_gain
= lna_gain
;
1878 #define FREQ_OFFSET_BOUND 0x5f
1880 static void rt2800_adjust_freq_offset(struct rt2x00_dev
*rt2x00dev
)
1882 u8 freq_offset
, prev_freq_offset
;
1883 u8 rfcsr
, prev_rfcsr
;
1885 freq_offset
= rt2x00_get_field8(rt2x00dev
->freq_offset
, RFCSR17_CODE
);
1886 freq_offset
= min_t(u8
, freq_offset
, FREQ_OFFSET_BOUND
);
1888 rt2800_rfcsr_read(rt2x00dev
, 17, &rfcsr
);
1891 rt2x00_set_field8(&rfcsr
, RFCSR17_CODE
, freq_offset
);
1892 if (rfcsr
== prev_rfcsr
)
1895 if (rt2x00_is_usb(rt2x00dev
)) {
1896 rt2800_mcu_request(rt2x00dev
, MCU_FREQ_OFFSET
, 0xff,
1897 freq_offset
, prev_rfcsr
);
1901 prev_freq_offset
= rt2x00_get_field8(prev_rfcsr
, RFCSR17_CODE
);
1902 while (prev_freq_offset
!= freq_offset
) {
1903 if (prev_freq_offset
< freq_offset
)
1908 rt2x00_set_field8(&rfcsr
, RFCSR17_CODE
, prev_freq_offset
);
1909 rt2800_rfcsr_write(rt2x00dev
, 17, rfcsr
);
1911 usleep_range(1000, 1500);
1915 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev
*rt2x00dev
,
1916 struct ieee80211_conf
*conf
,
1917 struct rf_channel
*rf
,
1918 struct channel_info
*info
)
1920 rt2x00_set_field32(&rf
->rf4
, RF4_FREQ_OFFSET
, rt2x00dev
->freq_offset
);
1922 if (rt2x00dev
->default_ant
.tx_chain_num
== 1)
1923 rt2x00_set_field32(&rf
->rf2
, RF2_ANTENNA_TX1
, 1);
1925 if (rt2x00dev
->default_ant
.rx_chain_num
== 1) {
1926 rt2x00_set_field32(&rf
->rf2
, RF2_ANTENNA_RX1
, 1);
1927 rt2x00_set_field32(&rf
->rf2
, RF2_ANTENNA_RX2
, 1);
1928 } else if (rt2x00dev
->default_ant
.rx_chain_num
== 2)
1929 rt2x00_set_field32(&rf
->rf2
, RF2_ANTENNA_RX2
, 1);
1931 if (rf
->channel
> 14) {
1933 * When TX power is below 0, we should increase it by 7 to
1934 * make it a positive value (Minimum value is -7).
1935 * However this means that values between 0 and 7 have
1936 * double meaning, and we should set a 7DBm boost flag.
1938 rt2x00_set_field32(&rf
->rf3
, RF3_TXPOWER_A_7DBM_BOOST
,
1939 (info
->default_power1
>= 0));
1941 if (info
->default_power1
< 0)
1942 info
->default_power1
+= 7;
1944 rt2x00_set_field32(&rf
->rf3
, RF3_TXPOWER_A
, info
->default_power1
);
1946 rt2x00_set_field32(&rf
->rf4
, RF4_TXPOWER_A_7DBM_BOOST
,
1947 (info
->default_power2
>= 0));
1949 if (info
->default_power2
< 0)
1950 info
->default_power2
+= 7;
1952 rt2x00_set_field32(&rf
->rf4
, RF4_TXPOWER_A
, info
->default_power2
);
1954 rt2x00_set_field32(&rf
->rf3
, RF3_TXPOWER_G
, info
->default_power1
);
1955 rt2x00_set_field32(&rf
->rf4
, RF4_TXPOWER_G
, info
->default_power2
);
1958 rt2x00_set_field32(&rf
->rf4
, RF4_HT40
, conf_is_ht40(conf
));
1960 rt2800_rf_write(rt2x00dev
, 1, rf
->rf1
);
1961 rt2800_rf_write(rt2x00dev
, 2, rf
->rf2
);
1962 rt2800_rf_write(rt2x00dev
, 3, rf
->rf3
& ~0x00000004);
1963 rt2800_rf_write(rt2x00dev
, 4, rf
->rf4
);
1967 rt2800_rf_write(rt2x00dev
, 1, rf
->rf1
);
1968 rt2800_rf_write(rt2x00dev
, 2, rf
->rf2
);
1969 rt2800_rf_write(rt2x00dev
, 3, rf
->rf3
| 0x00000004);
1970 rt2800_rf_write(rt2x00dev
, 4, rf
->rf4
);
1974 rt2800_rf_write(rt2x00dev
, 1, rf
->rf1
);
1975 rt2800_rf_write(rt2x00dev
, 2, rf
->rf2
);
1976 rt2800_rf_write(rt2x00dev
, 3, rf
->rf3
& ~0x00000004);
1977 rt2800_rf_write(rt2x00dev
, 4, rf
->rf4
);
1980 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev
*rt2x00dev
,
1981 struct ieee80211_conf
*conf
,
1982 struct rf_channel
*rf
,
1983 struct channel_info
*info
)
1985 struct rt2800_drv_data
*drv_data
= rt2x00dev
->drv_data
;
1986 u8 rfcsr
, calib_tx
, calib_rx
;
1988 rt2800_rfcsr_write(rt2x00dev
, 2, rf
->rf1
);
1990 rt2800_rfcsr_read(rt2x00dev
, 3, &rfcsr
);
1991 rt2x00_set_field8(&rfcsr
, RFCSR3_K
, rf
->rf3
);
1992 rt2800_rfcsr_write(rt2x00dev
, 3, rfcsr
);
1994 rt2800_rfcsr_read(rt2x00dev
, 6, &rfcsr
);
1995 rt2x00_set_field8(&rfcsr
, RFCSR6_R1
, rf
->rf2
);
1996 rt2800_rfcsr_write(rt2x00dev
, 6, rfcsr
);
1998 rt2800_rfcsr_read(rt2x00dev
, 12, &rfcsr
);
1999 rt2x00_set_field8(&rfcsr
, RFCSR12_TX_POWER
, info
->default_power1
);
2000 rt2800_rfcsr_write(rt2x00dev
, 12, rfcsr
);
2002 rt2800_rfcsr_read(rt2x00dev
, 13, &rfcsr
);
2003 rt2x00_set_field8(&rfcsr
, RFCSR13_TX_POWER
, info
->default_power2
);
2004 rt2800_rfcsr_write(rt2x00dev
, 13, rfcsr
);
2006 rt2800_rfcsr_read(rt2x00dev
, 1, &rfcsr
);
2007 rt2x00_set_field8(&rfcsr
, RFCSR1_RX0_PD
, 0);
2008 rt2x00_set_field8(&rfcsr
, RFCSR1_RX1_PD
,
2009 rt2x00dev
->default_ant
.rx_chain_num
<= 1);
2010 rt2x00_set_field8(&rfcsr
, RFCSR1_RX2_PD
,
2011 rt2x00dev
->default_ant
.rx_chain_num
<= 2);
2012 rt2x00_set_field8(&rfcsr
, RFCSR1_TX0_PD
, 0);
2013 rt2x00_set_field8(&rfcsr
, RFCSR1_TX1_PD
,
2014 rt2x00dev
->default_ant
.tx_chain_num
<= 1);
2015 rt2x00_set_field8(&rfcsr
, RFCSR1_TX2_PD
,
2016 rt2x00dev
->default_ant
.tx_chain_num
<= 2);
2017 rt2800_rfcsr_write(rt2x00dev
, 1, rfcsr
);
2019 rt2800_rfcsr_read(rt2x00dev
, 30, &rfcsr
);
2020 rt2x00_set_field8(&rfcsr
, RFCSR30_RF_CALIBRATION
, 1);
2021 rt2800_rfcsr_write(rt2x00dev
, 30, rfcsr
);
2023 rt2x00_set_field8(&rfcsr
, RFCSR30_RF_CALIBRATION
, 0);
2024 rt2800_rfcsr_write(rt2x00dev
, 30, rfcsr
);
2026 rt2800_rfcsr_read(rt2x00dev
, 23, &rfcsr
);
2027 rt2x00_set_field8(&rfcsr
, RFCSR23_FREQ_OFFSET
, rt2x00dev
->freq_offset
);
2028 rt2800_rfcsr_write(rt2x00dev
, 23, rfcsr
);
2030 if (rt2x00_rt(rt2x00dev
, RT3390
)) {
2031 calib_tx
= conf_is_ht40(conf
) ? 0x68 : 0x4f;
2032 calib_rx
= conf_is_ht40(conf
) ? 0x6f : 0x4f;
2034 if (conf_is_ht40(conf
)) {
2035 calib_tx
= drv_data
->calibration_bw40
;
2036 calib_rx
= drv_data
->calibration_bw40
;
2038 calib_tx
= drv_data
->calibration_bw20
;
2039 calib_rx
= drv_data
->calibration_bw20
;
2043 rt2800_rfcsr_read(rt2x00dev
, 24, &rfcsr
);
2044 rt2x00_set_field8(&rfcsr
, RFCSR24_TX_CALIB
, calib_tx
);
2045 rt2800_rfcsr_write(rt2x00dev
, 24, rfcsr
);
2047 rt2800_rfcsr_read(rt2x00dev
, 31, &rfcsr
);
2048 rt2x00_set_field8(&rfcsr
, RFCSR31_RX_CALIB
, calib_rx
);
2049 rt2800_rfcsr_write(rt2x00dev
, 31, rfcsr
);
2051 rt2800_rfcsr_read(rt2x00dev
, 7, &rfcsr
);
2052 rt2x00_set_field8(&rfcsr
, RFCSR7_RF_TUNING
, 1);
2053 rt2800_rfcsr_write(rt2x00dev
, 7, rfcsr
);
2055 rt2800_rfcsr_read(rt2x00dev
, 30, &rfcsr
);
2056 rt2x00_set_field8(&rfcsr
, RFCSR30_RF_CALIBRATION
, 1);
2057 rt2800_rfcsr_write(rt2x00dev
, 30, rfcsr
);
2059 rt2x00_set_field8(&rfcsr
, RFCSR30_RF_CALIBRATION
, 0);
2060 rt2800_rfcsr_write(rt2x00dev
, 30, rfcsr
);
2063 static void rt2800_config_channel_rf3052(struct rt2x00_dev
*rt2x00dev
,
2064 struct ieee80211_conf
*conf
,
2065 struct rf_channel
*rf
,
2066 struct channel_info
*info
)
2068 struct rt2800_drv_data
*drv_data
= rt2x00dev
->drv_data
;
2072 if (rf
->channel
<= 14) {
2073 rt2800_bbp_write(rt2x00dev
, 25, drv_data
->bbp25
);
2074 rt2800_bbp_write(rt2x00dev
, 26, drv_data
->bbp26
);
2076 rt2800_bbp_write(rt2x00dev
, 25, 0x09);
2077 rt2800_bbp_write(rt2x00dev
, 26, 0xff);
2080 rt2800_rfcsr_write(rt2x00dev
, 2, rf
->rf1
);
2081 rt2800_rfcsr_write(rt2x00dev
, 3, rf
->rf3
);
2083 rt2800_rfcsr_read(rt2x00dev
, 6, &rfcsr
);
2084 rt2x00_set_field8(&rfcsr
, RFCSR6_R1
, rf
->rf2
);
2085 if (rf
->channel
<= 14)
2086 rt2x00_set_field8(&rfcsr
, RFCSR6_TXDIV
, 2);
2088 rt2x00_set_field8(&rfcsr
, RFCSR6_TXDIV
, 1);
2089 rt2800_rfcsr_write(rt2x00dev
, 6, rfcsr
);
2091 rt2800_rfcsr_read(rt2x00dev
, 5, &rfcsr
);
2092 if (rf
->channel
<= 14)
2093 rt2x00_set_field8(&rfcsr
, RFCSR5_R1
, 1);
2095 rt2x00_set_field8(&rfcsr
, RFCSR5_R1
, 2);
2096 rt2800_rfcsr_write(rt2x00dev
, 5, rfcsr
);
2098 rt2800_rfcsr_read(rt2x00dev
, 12, &rfcsr
);
2099 if (rf
->channel
<= 14) {
2100 rt2x00_set_field8(&rfcsr
, RFCSR12_DR0
, 3);
2101 rt2x00_set_field8(&rfcsr
, RFCSR12_TX_POWER
,
2102 info
->default_power1
);
2104 rt2x00_set_field8(&rfcsr
, RFCSR12_DR0
, 7);
2105 rt2x00_set_field8(&rfcsr
, RFCSR12_TX_POWER
,
2106 (info
->default_power1
& 0x3) |
2107 ((info
->default_power1
& 0xC) << 1));
2109 rt2800_rfcsr_write(rt2x00dev
, 12, rfcsr
);
2111 rt2800_rfcsr_read(rt2x00dev
, 13, &rfcsr
);
2112 if (rf
->channel
<= 14) {
2113 rt2x00_set_field8(&rfcsr
, RFCSR13_DR0
, 3);
2114 rt2x00_set_field8(&rfcsr
, RFCSR13_TX_POWER
,
2115 info
->default_power2
);
2117 rt2x00_set_field8(&rfcsr
, RFCSR13_DR0
, 7);
2118 rt2x00_set_field8(&rfcsr
, RFCSR13_TX_POWER
,
2119 (info
->default_power2
& 0x3) |
2120 ((info
->default_power2
& 0xC) << 1));
2122 rt2800_rfcsr_write(rt2x00dev
, 13, rfcsr
);
2124 rt2800_rfcsr_read(rt2x00dev
, 1, &rfcsr
);
2125 rt2x00_set_field8(&rfcsr
, RFCSR1_RX0_PD
, 0);
2126 rt2x00_set_field8(&rfcsr
, RFCSR1_TX0_PD
, 0);
2127 rt2x00_set_field8(&rfcsr
, RFCSR1_RX1_PD
, 0);
2128 rt2x00_set_field8(&rfcsr
, RFCSR1_TX1_PD
, 0);
2129 rt2x00_set_field8(&rfcsr
, RFCSR1_RX2_PD
, 0);
2130 rt2x00_set_field8(&rfcsr
, RFCSR1_TX2_PD
, 0);
2131 if (test_bit(CAPABILITY_BT_COEXIST
, &rt2x00dev
->cap_flags
)) {
2132 if (rf
->channel
<= 14) {
2133 rt2x00_set_field8(&rfcsr
, RFCSR1_RX0_PD
, 1);
2134 rt2x00_set_field8(&rfcsr
, RFCSR1_TX0_PD
, 1);
2136 rt2x00_set_field8(&rfcsr
, RFCSR1_RX2_PD
, 1);
2137 rt2x00_set_field8(&rfcsr
, RFCSR1_TX2_PD
, 1);
2139 switch (rt2x00dev
->default_ant
.tx_chain_num
) {
2141 rt2x00_set_field8(&rfcsr
, RFCSR1_TX1_PD
, 1);
2143 rt2x00_set_field8(&rfcsr
, RFCSR1_TX2_PD
, 1);
2147 switch (rt2x00dev
->default_ant
.rx_chain_num
) {
2149 rt2x00_set_field8(&rfcsr
, RFCSR1_RX1_PD
, 1);
2151 rt2x00_set_field8(&rfcsr
, RFCSR1_RX2_PD
, 1);
2155 rt2800_rfcsr_write(rt2x00dev
, 1, rfcsr
);
2157 rt2800_rfcsr_read(rt2x00dev
, 23, &rfcsr
);
2158 rt2x00_set_field8(&rfcsr
, RFCSR23_FREQ_OFFSET
, rt2x00dev
->freq_offset
);
2159 rt2800_rfcsr_write(rt2x00dev
, 23, rfcsr
);
2161 if (conf_is_ht40(conf
)) {
2162 rt2800_rfcsr_write(rt2x00dev
, 24, drv_data
->calibration_bw40
);
2163 rt2800_rfcsr_write(rt2x00dev
, 31, drv_data
->calibration_bw40
);
2165 rt2800_rfcsr_write(rt2x00dev
, 24, drv_data
->calibration_bw20
);
2166 rt2800_rfcsr_write(rt2x00dev
, 31, drv_data
->calibration_bw20
);
2169 if (rf
->channel
<= 14) {
2170 rt2800_rfcsr_write(rt2x00dev
, 7, 0xd8);
2171 rt2800_rfcsr_write(rt2x00dev
, 9, 0xc3);
2172 rt2800_rfcsr_write(rt2x00dev
, 10, 0xf1);
2173 rt2800_rfcsr_write(rt2x00dev
, 11, 0xb9);
2174 rt2800_rfcsr_write(rt2x00dev
, 15, 0x53);
2176 rt2x00_set_field8(&rfcsr
, RFCSR16_TXMIXER_GAIN
,
2177 drv_data
->txmixer_gain_24g
);
2178 rt2800_rfcsr_write(rt2x00dev
, 16, rfcsr
);
2179 rt2800_rfcsr_write(rt2x00dev
, 17, 0x23);
2180 rt2800_rfcsr_write(rt2x00dev
, 19, 0x93);
2181 rt2800_rfcsr_write(rt2x00dev
, 20, 0xb3);
2182 rt2800_rfcsr_write(rt2x00dev
, 25, 0x15);
2183 rt2800_rfcsr_write(rt2x00dev
, 26, 0x85);
2184 rt2800_rfcsr_write(rt2x00dev
, 27, 0x00);
2185 rt2800_rfcsr_write(rt2x00dev
, 29, 0x9b);
2187 rt2800_rfcsr_read(rt2x00dev
, 7, &rfcsr
);
2188 rt2x00_set_field8(&rfcsr
, RFCSR7_BIT2
, 1);
2189 rt2x00_set_field8(&rfcsr
, RFCSR7_BIT3
, 0);
2190 rt2x00_set_field8(&rfcsr
, RFCSR7_BIT4
, 1);
2191 rt2x00_set_field8(&rfcsr
, RFCSR7_BITS67
, 0);
2192 rt2800_rfcsr_write(rt2x00dev
, 7, rfcsr
);
2193 rt2800_rfcsr_write(rt2x00dev
, 9, 0xc0);
2194 rt2800_rfcsr_write(rt2x00dev
, 10, 0xf1);
2195 rt2800_rfcsr_write(rt2x00dev
, 11, 0x00);
2196 rt2800_rfcsr_write(rt2x00dev
, 15, 0x43);
2198 rt2x00_set_field8(&rfcsr
, RFCSR16_TXMIXER_GAIN
,
2199 drv_data
->txmixer_gain_5g
);
2200 rt2800_rfcsr_write(rt2x00dev
, 16, rfcsr
);
2201 rt2800_rfcsr_write(rt2x00dev
, 17, 0x23);
2202 if (rf
->channel
<= 64) {
2203 rt2800_rfcsr_write(rt2x00dev
, 19, 0xb7);
2204 rt2800_rfcsr_write(rt2x00dev
, 20, 0xf6);
2205 rt2800_rfcsr_write(rt2x00dev
, 25, 0x3d);
2206 } else if (rf
->channel
<= 128) {
2207 rt2800_rfcsr_write(rt2x00dev
, 19, 0x74);
2208 rt2800_rfcsr_write(rt2x00dev
, 20, 0xf4);
2209 rt2800_rfcsr_write(rt2x00dev
, 25, 0x01);
2211 rt2800_rfcsr_write(rt2x00dev
, 19, 0x72);
2212 rt2800_rfcsr_write(rt2x00dev
, 20, 0xf3);
2213 rt2800_rfcsr_write(rt2x00dev
, 25, 0x01);
2215 rt2800_rfcsr_write(rt2x00dev
, 26, 0x87);
2216 rt2800_rfcsr_write(rt2x00dev
, 27, 0x01);
2217 rt2800_rfcsr_write(rt2x00dev
, 29, 0x9f);
2220 rt2800_register_read(rt2x00dev
, GPIO_CTRL
, ®
);
2221 rt2x00_set_field32(®
, GPIO_CTRL_DIR7
, 0);
2222 if (rf
->channel
<= 14)
2223 rt2x00_set_field32(®
, GPIO_CTRL_VAL7
, 1);
2225 rt2x00_set_field32(®
, GPIO_CTRL_VAL7
, 0);
2226 rt2800_register_write(rt2x00dev
, GPIO_CTRL
, reg
);
2228 rt2800_rfcsr_read(rt2x00dev
, 7, &rfcsr
);
2229 rt2x00_set_field8(&rfcsr
, RFCSR7_RF_TUNING
, 1);
2230 rt2800_rfcsr_write(rt2x00dev
, 7, rfcsr
);
2233 static void rt2800_config_channel_rf3053(struct rt2x00_dev
*rt2x00dev
,
2234 struct ieee80211_conf
*conf
,
2235 struct rf_channel
*rf
,
2236 struct channel_info
*info
)
2238 struct rt2800_drv_data
*drv_data
= rt2x00dev
->drv_data
;
2243 const bool txbf_enabled
= false; /* TODO */
2245 /* TODO: use TX{0,1,2}FinePowerControl values from EEPROM */
2246 rt2800_bbp_read(rt2x00dev
, 109, &bbp
);
2247 rt2x00_set_field8(&bbp
, BBP109_TX0_POWER
, 0);
2248 rt2x00_set_field8(&bbp
, BBP109_TX1_POWER
, 0);
2249 rt2800_bbp_write(rt2x00dev
, 109, bbp
);
2251 rt2800_bbp_read(rt2x00dev
, 110, &bbp
);
2252 rt2x00_set_field8(&bbp
, BBP110_TX2_POWER
, 0);
2253 rt2800_bbp_write(rt2x00dev
, 110, bbp
);
2255 if (rf
->channel
<= 14) {
2256 /* Restore BBP 25 & 26 for 2.4 GHz */
2257 rt2800_bbp_write(rt2x00dev
, 25, drv_data
->bbp25
);
2258 rt2800_bbp_write(rt2x00dev
, 26, drv_data
->bbp26
);
2260 /* Hard code BBP 25 & 26 for 5GHz */
2262 /* Enable IQ Phase correction */
2263 rt2800_bbp_write(rt2x00dev
, 25, 0x09);
2264 /* Setup IQ Phase correction value */
2265 rt2800_bbp_write(rt2x00dev
, 26, 0xff);
2268 rt2800_rfcsr_write(rt2x00dev
, 8, rf
->rf1
);
2269 rt2800_rfcsr_write(rt2x00dev
, 9, rf
->rf3
& 0xf);
2271 rt2800_rfcsr_read(rt2x00dev
, 11, &rfcsr
);
2272 rt2x00_set_field8(&rfcsr
, RFCSR11_R
, (rf
->rf2
& 0x3));
2273 rt2800_rfcsr_write(rt2x00dev
, 11, rfcsr
);
2275 rt2800_rfcsr_read(rt2x00dev
, 11, &rfcsr
);
2276 rt2x00_set_field8(&rfcsr
, RFCSR11_PLL_IDOH
, 1);
2277 if (rf
->channel
<= 14)
2278 rt2x00_set_field8(&rfcsr
, RFCSR11_PLL_MOD
, 1);
2280 rt2x00_set_field8(&rfcsr
, RFCSR11_PLL_MOD
, 2);
2281 rt2800_rfcsr_write(rt2x00dev
, 11, rfcsr
);
2283 rt2800_rfcsr_read(rt2x00dev
, 53, &rfcsr
);
2284 if (rf
->channel
<= 14) {
2286 rt2x00_set_field8(&rfcsr
, RFCSR53_TX_POWER
,
2287 info
->default_power1
& 0x1f);
2289 if (rt2x00_is_usb(rt2x00dev
))
2292 rt2x00_set_field8(&rfcsr
, RFCSR53_TX_POWER
,
2293 ((info
->default_power1
& 0x18) << 1) |
2294 (info
->default_power1
& 7));
2296 rt2800_rfcsr_write(rt2x00dev
, 53, rfcsr
);
2298 rt2800_rfcsr_read(rt2x00dev
, 55, &rfcsr
);
2299 if (rf
->channel
<= 14) {
2301 rt2x00_set_field8(&rfcsr
, RFCSR55_TX_POWER
,
2302 info
->default_power2
& 0x1f);
2304 if (rt2x00_is_usb(rt2x00dev
))
2307 rt2x00_set_field8(&rfcsr
, RFCSR55_TX_POWER
,
2308 ((info
->default_power2
& 0x18) << 1) |
2309 (info
->default_power2
& 7));
2311 rt2800_rfcsr_write(rt2x00dev
, 55, rfcsr
);
2313 rt2800_rfcsr_read(rt2x00dev
, 54, &rfcsr
);
2314 if (rf
->channel
<= 14) {
2316 rt2x00_set_field8(&rfcsr
, RFCSR54_TX_POWER
,
2317 info
->default_power3
& 0x1f);
2319 if (rt2x00_is_usb(rt2x00dev
))
2322 rt2x00_set_field8(&rfcsr
, RFCSR54_TX_POWER
,
2323 ((info
->default_power3
& 0x18) << 1) |
2324 (info
->default_power3
& 7));
2326 rt2800_rfcsr_write(rt2x00dev
, 54, rfcsr
);
2328 rt2800_rfcsr_read(rt2x00dev
, 1, &rfcsr
);
2329 rt2x00_set_field8(&rfcsr
, RFCSR1_RX0_PD
, 0);
2330 rt2x00_set_field8(&rfcsr
, RFCSR1_TX0_PD
, 0);
2331 rt2x00_set_field8(&rfcsr
, RFCSR1_RX1_PD
, 0);
2332 rt2x00_set_field8(&rfcsr
, RFCSR1_TX1_PD
, 0);
2333 rt2x00_set_field8(&rfcsr
, RFCSR1_RX2_PD
, 0);
2334 rt2x00_set_field8(&rfcsr
, RFCSR1_TX2_PD
, 0);
2335 rt2x00_set_field8(&rfcsr
, RFCSR1_RF_BLOCK_EN
, 1);
2336 rt2x00_set_field8(&rfcsr
, RFCSR1_PLL_PD
, 1);
2338 switch (rt2x00dev
->default_ant
.tx_chain_num
) {
2340 rt2x00_set_field8(&rfcsr
, RFCSR1_TX2_PD
, 1);
2343 rt2x00_set_field8(&rfcsr
, RFCSR1_TX1_PD
, 1);
2346 rt2x00_set_field8(&rfcsr
, RFCSR1_TX0_PD
, 1);
2350 switch (rt2x00dev
->default_ant
.rx_chain_num
) {
2352 rt2x00_set_field8(&rfcsr
, RFCSR1_RX2_PD
, 1);
2355 rt2x00_set_field8(&rfcsr
, RFCSR1_RX1_PD
, 1);
2358 rt2x00_set_field8(&rfcsr
, RFCSR1_RX0_PD
, 1);
2361 rt2800_rfcsr_write(rt2x00dev
, 1, rfcsr
);
2363 /* TODO: frequency calibration? */
2365 if (conf_is_ht40(conf
)) {
2366 txrx_agc_fc
= rt2x00_get_field8(drv_data
->calibration_bw40
,
2368 txrx_h20m
= rt2x00_get_field8(drv_data
->calibration_bw40
,
2371 txrx_agc_fc
= rt2x00_get_field8(drv_data
->calibration_bw20
,
2373 txrx_h20m
= rt2x00_get_field8(drv_data
->calibration_bw20
,
2377 /* NOTE: the reference driver does not writes the new value
2380 rt2800_rfcsr_read(rt2x00dev
, 32, &rfcsr
);
2381 rt2x00_set_field8(&rfcsr
, RFCSR32_TX_AGC_FC
, txrx_agc_fc
);
2383 if (rf
->channel
<= 14)
2387 rt2800_rfcsr_write(rt2x00dev
, 31, rfcsr
);
2389 rt2800_rfcsr_read(rt2x00dev
, 30, &rfcsr
);
2390 rt2x00_set_field8(&rfcsr
, RFCSR30_TX_H20M
, txrx_h20m
);
2391 rt2x00_set_field8(&rfcsr
, RFCSR30_RX_H20M
, txrx_h20m
);
2392 rt2800_rfcsr_write(rt2x00dev
, 30, rfcsr
);
2394 /* Band selection */
2395 rt2800_rfcsr_read(rt2x00dev
, 36, &rfcsr
);
2396 if (rf
->channel
<= 14)
2397 rt2x00_set_field8(&rfcsr
, RFCSR36_RF_BS
, 1);
2399 rt2x00_set_field8(&rfcsr
, RFCSR36_RF_BS
, 0);
2400 rt2800_rfcsr_write(rt2x00dev
, 36, rfcsr
);
2402 rt2800_rfcsr_read(rt2x00dev
, 34, &rfcsr
);
2403 if (rf
->channel
<= 14)
2407 rt2800_rfcsr_write(rt2x00dev
, 34, rfcsr
);
2409 rt2800_rfcsr_read(rt2x00dev
, 12, &rfcsr
);
2410 if (rf
->channel
<= 14)
2414 rt2800_rfcsr_write(rt2x00dev
, 12, rfcsr
);
2416 rt2800_rfcsr_read(rt2x00dev
, 6, &rfcsr
);
2417 if (rf
->channel
>= 1 && rf
->channel
<= 14)
2418 rt2x00_set_field8(&rfcsr
, RFCSR6_VCO_IC
, 1);
2419 else if (rf
->channel
>= 36 && rf
->channel
<= 64)
2420 rt2x00_set_field8(&rfcsr
, RFCSR6_VCO_IC
, 2);
2421 else if (rf
->channel
>= 100 && rf
->channel
<= 128)
2422 rt2x00_set_field8(&rfcsr
, RFCSR6_VCO_IC
, 2);
2424 rt2x00_set_field8(&rfcsr
, RFCSR6_VCO_IC
, 1);
2425 rt2800_rfcsr_write(rt2x00dev
, 6, rfcsr
);
2427 rt2800_rfcsr_read(rt2x00dev
, 30, &rfcsr
);
2428 rt2x00_set_field8(&rfcsr
, RFCSR30_RX_VCM
, 2);
2429 rt2800_rfcsr_write(rt2x00dev
, 30, rfcsr
);
2431 rt2800_rfcsr_write(rt2x00dev
, 46, 0x60);
2433 if (rf
->channel
<= 14) {
2434 rt2800_rfcsr_write(rt2x00dev
, 10, 0xd3);
2435 rt2800_rfcsr_write(rt2x00dev
, 13, 0x12);
2437 rt2800_rfcsr_write(rt2x00dev
, 10, 0xd8);
2438 rt2800_rfcsr_write(rt2x00dev
, 13, 0x23);
2441 rt2800_rfcsr_read(rt2x00dev
, 51, &rfcsr
);
2442 rt2x00_set_field8(&rfcsr
, RFCSR51_BITS01
, 1);
2443 rt2800_rfcsr_write(rt2x00dev
, 51, rfcsr
);
2445 rt2800_rfcsr_read(rt2x00dev
, 51, &rfcsr
);
2446 if (rf
->channel
<= 14) {
2447 rt2x00_set_field8(&rfcsr
, RFCSR51_BITS24
, 5);
2448 rt2x00_set_field8(&rfcsr
, RFCSR51_BITS57
, 3);
2450 rt2x00_set_field8(&rfcsr
, RFCSR51_BITS24
, 4);
2451 rt2x00_set_field8(&rfcsr
, RFCSR51_BITS57
, 2);
2453 rt2800_rfcsr_write(rt2x00dev
, 51, rfcsr
);
2455 rt2800_rfcsr_read(rt2x00dev
, 49, &rfcsr
);
2456 if (rf
->channel
<= 14)
2457 rt2x00_set_field8(&rfcsr
, RFCSR49_TX_LO1_IC
, 3);
2459 rt2x00_set_field8(&rfcsr
, RFCSR49_TX_LO1_IC
, 2);
2462 rt2x00_set_field8(&rfcsr
, RFCSR49_TX_DIV
, 1);
2464 rt2800_rfcsr_write(rt2x00dev
, 49, rfcsr
);
2466 rt2800_rfcsr_read(rt2x00dev
, 50, &rfcsr
);
2467 rt2x00_set_field8(&rfcsr
, RFCSR50_TX_LO1_EN
, 0);
2468 rt2800_rfcsr_write(rt2x00dev
, 50, rfcsr
);
2470 rt2800_rfcsr_read(rt2x00dev
, 57, &rfcsr
);
2471 if (rf
->channel
<= 14)
2472 rt2x00_set_field8(&rfcsr
, RFCSR57_DRV_CC
, 0x1b);
2474 rt2x00_set_field8(&rfcsr
, RFCSR57_DRV_CC
, 0x0f);
2475 rt2800_rfcsr_write(rt2x00dev
, 57, rfcsr
);
2477 if (rf
->channel
<= 14) {
2478 rt2800_rfcsr_write(rt2x00dev
, 44, 0x93);
2479 rt2800_rfcsr_write(rt2x00dev
, 52, 0x45);
2481 rt2800_rfcsr_write(rt2x00dev
, 44, 0x9b);
2482 rt2800_rfcsr_write(rt2x00dev
, 52, 0x05);
2485 /* Initiate VCO calibration */
2486 rt2800_rfcsr_read(rt2x00dev
, 3, &rfcsr
);
2487 if (rf
->channel
<= 14) {
2488 rt2x00_set_field8(&rfcsr
, RFCSR3_VCOCAL_EN
, 1);
2490 rt2x00_set_field8(&rfcsr
, RFCSR3_BIT1
, 1);
2491 rt2x00_set_field8(&rfcsr
, RFCSR3_BIT2
, 1);
2492 rt2x00_set_field8(&rfcsr
, RFCSR3_BIT3
, 1);
2493 rt2x00_set_field8(&rfcsr
, RFCSR3_BIT4
, 1);
2494 rt2x00_set_field8(&rfcsr
, RFCSR3_BIT5
, 1);
2495 rt2x00_set_field8(&rfcsr
, RFCSR3_VCOCAL_EN
, 1);
2497 rt2800_rfcsr_write(rt2x00dev
, 3, rfcsr
);
2499 if (rf
->channel
>= 1 && rf
->channel
<= 14) {
2502 rt2x00_set_field8(&rfcsr
, RFCSR39_RX_DIV
, 1);
2503 rt2800_rfcsr_write(rt2x00dev
, 39, rfcsr
);
2505 rt2800_rfcsr_write(rt2x00dev
, 45, 0xbb);
2506 } else if (rf
->channel
>= 36 && rf
->channel
<= 64) {
2509 rt2x00_set_field8(&rfcsr
, RFCSR39_RX_DIV
, 1);
2510 rt2800_rfcsr_write(rt2x00dev
, 39, 0x36);
2512 rt2800_rfcsr_write(rt2x00dev
, 45, 0xeb);
2513 } else if (rf
->channel
>= 100 && rf
->channel
<= 128) {
2516 rt2x00_set_field8(&rfcsr
, RFCSR39_RX_DIV
, 1);
2517 rt2800_rfcsr_write(rt2x00dev
, 39, rfcsr
);
2519 rt2800_rfcsr_write(rt2x00dev
, 45, 0xb3);
2523 rt2x00_set_field8(&rfcsr
, RFCSR39_RX_DIV
, 1);
2524 rt2800_rfcsr_write(rt2x00dev
, 39, rfcsr
);
2526 rt2800_rfcsr_write(rt2x00dev
, 45, 0x9b);
2530 #define POWER_BOUND 0x27
2531 #define POWER_BOUND_5G 0x2b
2533 static void rt2800_config_channel_rf3290(struct rt2x00_dev
*rt2x00dev
,
2534 struct ieee80211_conf
*conf
,
2535 struct rf_channel
*rf
,
2536 struct channel_info
*info
)
2540 rt2800_rfcsr_write(rt2x00dev
, 8, rf
->rf1
);
2541 rt2800_rfcsr_write(rt2x00dev
, 9, rf
->rf3
);
2542 rt2800_rfcsr_read(rt2x00dev
, 11, &rfcsr
);
2543 rt2x00_set_field8(&rfcsr
, RFCSR11_R
, rf
->rf2
);
2544 rt2800_rfcsr_write(rt2x00dev
, 11, rfcsr
);
2546 rt2800_rfcsr_read(rt2x00dev
, 49, &rfcsr
);
2547 if (info
->default_power1
> POWER_BOUND
)
2548 rt2x00_set_field8(&rfcsr
, RFCSR49_TX
, POWER_BOUND
);
2550 rt2x00_set_field8(&rfcsr
, RFCSR49_TX
, info
->default_power1
);
2551 rt2800_rfcsr_write(rt2x00dev
, 49, rfcsr
);
2553 rt2800_adjust_freq_offset(rt2x00dev
);
2555 if (rf
->channel
<= 14) {
2556 if (rf
->channel
== 6)
2557 rt2800_bbp_write(rt2x00dev
, 68, 0x0c);
2559 rt2800_bbp_write(rt2x00dev
, 68, 0x0b);
2561 if (rf
->channel
>= 1 && rf
->channel
<= 6)
2562 rt2800_bbp_write(rt2x00dev
, 59, 0x0f);
2563 else if (rf
->channel
>= 7 && rf
->channel
<= 11)
2564 rt2800_bbp_write(rt2x00dev
, 59, 0x0e);
2565 else if (rf
->channel
>= 12 && rf
->channel
<= 14)
2566 rt2800_bbp_write(rt2x00dev
, 59, 0x0d);
2570 static void rt2800_config_channel_rf3322(struct rt2x00_dev
*rt2x00dev
,
2571 struct ieee80211_conf
*conf
,
2572 struct rf_channel
*rf
,
2573 struct channel_info
*info
)
2577 rt2800_rfcsr_write(rt2x00dev
, 8, rf
->rf1
);
2578 rt2800_rfcsr_write(rt2x00dev
, 9, rf
->rf3
);
2580 rt2800_rfcsr_write(rt2x00dev
, 11, 0x42);
2581 rt2800_rfcsr_write(rt2x00dev
, 12, 0x1c);
2582 rt2800_rfcsr_write(rt2x00dev
, 13, 0x00);
2584 if (info
->default_power1
> POWER_BOUND
)
2585 rt2800_rfcsr_write(rt2x00dev
, 47, POWER_BOUND
);
2587 rt2800_rfcsr_write(rt2x00dev
, 47, info
->default_power1
);
2589 if (info
->default_power2
> POWER_BOUND
)
2590 rt2800_rfcsr_write(rt2x00dev
, 48, POWER_BOUND
);
2592 rt2800_rfcsr_write(rt2x00dev
, 48, info
->default_power2
);
2594 rt2800_adjust_freq_offset(rt2x00dev
);
2596 rt2800_rfcsr_read(rt2x00dev
, 1, &rfcsr
);
2597 rt2x00_set_field8(&rfcsr
, RFCSR1_RX0_PD
, 1);
2598 rt2x00_set_field8(&rfcsr
, RFCSR1_TX0_PD
, 1);
2600 if ( rt2x00dev
->default_ant
.tx_chain_num
== 2 )
2601 rt2x00_set_field8(&rfcsr
, RFCSR1_TX1_PD
, 1);
2603 rt2x00_set_field8(&rfcsr
, RFCSR1_TX1_PD
, 0);
2605 if ( rt2x00dev
->default_ant
.rx_chain_num
== 2 )
2606 rt2x00_set_field8(&rfcsr
, RFCSR1_RX1_PD
, 1);
2608 rt2x00_set_field8(&rfcsr
, RFCSR1_RX1_PD
, 0);
2610 rt2x00_set_field8(&rfcsr
, RFCSR1_RX2_PD
, 0);
2611 rt2x00_set_field8(&rfcsr
, RFCSR1_TX2_PD
, 0);
2613 rt2800_rfcsr_write(rt2x00dev
, 1, rfcsr
);
2615 rt2800_rfcsr_write(rt2x00dev
, 31, 80);
2618 static void rt2800_config_channel_rf53xx(struct rt2x00_dev
*rt2x00dev
,
2619 struct ieee80211_conf
*conf
,
2620 struct rf_channel
*rf
,
2621 struct channel_info
*info
)
2625 rt2800_rfcsr_write(rt2x00dev
, 8, rf
->rf1
);
2626 rt2800_rfcsr_write(rt2x00dev
, 9, rf
->rf3
);
2627 rt2800_rfcsr_read(rt2x00dev
, 11, &rfcsr
);
2628 rt2x00_set_field8(&rfcsr
, RFCSR11_R
, rf
->rf2
);
2629 rt2800_rfcsr_write(rt2x00dev
, 11, rfcsr
);
2631 rt2800_rfcsr_read(rt2x00dev
, 49, &rfcsr
);
2632 if (info
->default_power1
> POWER_BOUND
)
2633 rt2x00_set_field8(&rfcsr
, RFCSR49_TX
, POWER_BOUND
);
2635 rt2x00_set_field8(&rfcsr
, RFCSR49_TX
, info
->default_power1
);
2636 rt2800_rfcsr_write(rt2x00dev
, 49, rfcsr
);
2638 if (rt2x00_rt(rt2x00dev
, RT5392
)) {
2639 rt2800_rfcsr_read(rt2x00dev
, 50, &rfcsr
);
2640 if (info
->default_power1
> POWER_BOUND
)
2641 rt2x00_set_field8(&rfcsr
, RFCSR50_TX
, POWER_BOUND
);
2643 rt2x00_set_field8(&rfcsr
, RFCSR50_TX
,
2644 info
->default_power2
);
2645 rt2800_rfcsr_write(rt2x00dev
, 50, rfcsr
);
2648 rt2800_rfcsr_read(rt2x00dev
, 1, &rfcsr
);
2649 if (rt2x00_rt(rt2x00dev
, RT5392
)) {
2650 rt2x00_set_field8(&rfcsr
, RFCSR1_RX1_PD
, 1);
2651 rt2x00_set_field8(&rfcsr
, RFCSR1_TX1_PD
, 1);
2653 rt2x00_set_field8(&rfcsr
, RFCSR1_RF_BLOCK_EN
, 1);
2654 rt2x00_set_field8(&rfcsr
, RFCSR1_PLL_PD
, 1);
2655 rt2x00_set_field8(&rfcsr
, RFCSR1_RX0_PD
, 1);
2656 rt2x00_set_field8(&rfcsr
, RFCSR1_TX0_PD
, 1);
2657 rt2800_rfcsr_write(rt2x00dev
, 1, rfcsr
);
2659 rt2800_adjust_freq_offset(rt2x00dev
);
2661 if (rf
->channel
<= 14) {
2662 int idx
= rf
->channel
-1;
2664 if (test_bit(CAPABILITY_BT_COEXIST
, &rt2x00dev
->cap_flags
)) {
2665 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390F
)) {
2666 /* r55/r59 value array of channel 1~14 */
2667 static const char r55_bt_rev
[] = {0x83, 0x83,
2668 0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
2669 0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
2670 static const char r59_bt_rev
[] = {0x0e, 0x0e,
2671 0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
2672 0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
2674 rt2800_rfcsr_write(rt2x00dev
, 55,
2676 rt2800_rfcsr_write(rt2x00dev
, 59,
2679 static const char r59_bt
[] = {0x8b, 0x8b, 0x8b,
2680 0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
2681 0x88, 0x88, 0x86, 0x85, 0x84};
2683 rt2800_rfcsr_write(rt2x00dev
, 59, r59_bt
[idx
]);
2686 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390F
)) {
2687 static const char r55_nonbt_rev
[] = {0x23, 0x23,
2688 0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
2689 0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
2690 static const char r59_nonbt_rev
[] = {0x07, 0x07,
2691 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
2692 0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
2694 rt2800_rfcsr_write(rt2x00dev
, 55,
2695 r55_nonbt_rev
[idx
]);
2696 rt2800_rfcsr_write(rt2x00dev
, 59,
2697 r59_nonbt_rev
[idx
]);
2698 } else if (rt2x00_rt(rt2x00dev
, RT5390
) ||
2699 rt2x00_rt(rt2x00dev
, RT5392
)) {
2700 static const char r59_non_bt
[] = {0x8f, 0x8f,
2701 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
2702 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
2704 rt2800_rfcsr_write(rt2x00dev
, 59,
2711 static void rt2800_config_channel_rf55xx(struct rt2x00_dev
*rt2x00dev
,
2712 struct ieee80211_conf
*conf
,
2713 struct rf_channel
*rf
,
2714 struct channel_info
*info
)
2721 const bool is_11b
= false;
2722 const bool is_type_ep
= false;
2724 rt2800_register_read(rt2x00dev
, LDO_CFG0
, ®
);
2725 rt2x00_set_field32(®
, LDO_CFG0_LDO_CORE_VLEVEL
,
2726 (rf
->channel
> 14 || conf_is_ht40(conf
)) ? 5 : 0);
2727 rt2800_register_write(rt2x00dev
, LDO_CFG0
, reg
);
2729 /* Order of values on rf_channel entry: N, K, mod, R */
2730 rt2800_rfcsr_write(rt2x00dev
, 8, rf
->rf1
& 0xff);
2732 rt2800_rfcsr_read(rt2x00dev
, 9, &rfcsr
);
2733 rt2x00_set_field8(&rfcsr
, RFCSR9_K
, rf
->rf2
& 0xf);
2734 rt2x00_set_field8(&rfcsr
, RFCSR9_N
, (rf
->rf1
& 0x100) >> 8);
2735 rt2x00_set_field8(&rfcsr
, RFCSR9_MOD
, ((rf
->rf3
- 8) & 0x4) >> 2);
2736 rt2800_rfcsr_write(rt2x00dev
, 9, rfcsr
);
2738 rt2800_rfcsr_read(rt2x00dev
, 11, &rfcsr
);
2739 rt2x00_set_field8(&rfcsr
, RFCSR11_R
, rf
->rf4
- 1);
2740 rt2x00_set_field8(&rfcsr
, RFCSR11_MOD
, (rf
->rf3
- 8) & 0x3);
2741 rt2800_rfcsr_write(rt2x00dev
, 11, rfcsr
);
2743 if (rf
->channel
<= 14) {
2744 rt2800_rfcsr_write(rt2x00dev
, 10, 0x90);
2745 /* FIXME: RF11 owerwrite ? */
2746 rt2800_rfcsr_write(rt2x00dev
, 11, 0x4A);
2747 rt2800_rfcsr_write(rt2x00dev
, 12, 0x52);
2748 rt2800_rfcsr_write(rt2x00dev
, 13, 0x42);
2749 rt2800_rfcsr_write(rt2x00dev
, 22, 0x40);
2750 rt2800_rfcsr_write(rt2x00dev
, 24, 0x4A);
2751 rt2800_rfcsr_write(rt2x00dev
, 25, 0x80);
2752 rt2800_rfcsr_write(rt2x00dev
, 27, 0x42);
2753 rt2800_rfcsr_write(rt2x00dev
, 36, 0x80);
2754 rt2800_rfcsr_write(rt2x00dev
, 37, 0x08);
2755 rt2800_rfcsr_write(rt2x00dev
, 38, 0x89);
2756 rt2800_rfcsr_write(rt2x00dev
, 39, 0x1B);
2757 rt2800_rfcsr_write(rt2x00dev
, 40, 0x0D);
2758 rt2800_rfcsr_write(rt2x00dev
, 41, 0x9B);
2759 rt2800_rfcsr_write(rt2x00dev
, 42, 0xD5);
2760 rt2800_rfcsr_write(rt2x00dev
, 43, 0x72);
2761 rt2800_rfcsr_write(rt2x00dev
, 44, 0x0E);
2762 rt2800_rfcsr_write(rt2x00dev
, 45, 0xA2);
2763 rt2800_rfcsr_write(rt2x00dev
, 46, 0x6B);
2764 rt2800_rfcsr_write(rt2x00dev
, 48, 0x10);
2765 rt2800_rfcsr_write(rt2x00dev
, 51, 0x3E);
2766 rt2800_rfcsr_write(rt2x00dev
, 52, 0x48);
2767 rt2800_rfcsr_write(rt2x00dev
, 54, 0x38);
2768 rt2800_rfcsr_write(rt2x00dev
, 56, 0xA1);
2769 rt2800_rfcsr_write(rt2x00dev
, 57, 0x00);
2770 rt2800_rfcsr_write(rt2x00dev
, 58, 0x39);
2771 rt2800_rfcsr_write(rt2x00dev
, 60, 0x45);
2772 rt2800_rfcsr_write(rt2x00dev
, 61, 0x91);
2773 rt2800_rfcsr_write(rt2x00dev
, 62, 0x39);
2775 /* TODO RF27 <- tssi */
2777 rfcsr
= rf
->channel
<= 10 ? 0x07 : 0x06;
2778 rt2800_rfcsr_write(rt2x00dev
, 23, rfcsr
);
2779 rt2800_rfcsr_write(rt2x00dev
, 59, rfcsr
);
2783 rt2800_rfcsr_write(rt2x00dev
, 31, 0xF8);
2784 rt2800_rfcsr_write(rt2x00dev
, 32, 0xC0);
2786 rt2800_rfcsr_write(rt2x00dev
, 55, 0x06);
2788 rt2800_rfcsr_write(rt2x00dev
, 55, 0x47);
2792 rt2800_rfcsr_write(rt2x00dev
, 55, 0x03);
2794 rt2800_rfcsr_write(rt2x00dev
, 55, 0x43);
2797 power_bound
= POWER_BOUND
;
2800 rt2800_rfcsr_write(rt2x00dev
, 10, 0x97);
2801 /* FIMXE: RF11 overwrite */
2802 rt2800_rfcsr_write(rt2x00dev
, 11, 0x40);
2803 rt2800_rfcsr_write(rt2x00dev
, 25, 0xBF);
2804 rt2800_rfcsr_write(rt2x00dev
, 27, 0x42);
2805 rt2800_rfcsr_write(rt2x00dev
, 36, 0x00);
2806 rt2800_rfcsr_write(rt2x00dev
, 37, 0x04);
2807 rt2800_rfcsr_write(rt2x00dev
, 38, 0x85);
2808 rt2800_rfcsr_write(rt2x00dev
, 40, 0x42);
2809 rt2800_rfcsr_write(rt2x00dev
, 41, 0xBB);
2810 rt2800_rfcsr_write(rt2x00dev
, 42, 0xD7);
2811 rt2800_rfcsr_write(rt2x00dev
, 45, 0x41);
2812 rt2800_rfcsr_write(rt2x00dev
, 48, 0x00);
2813 rt2800_rfcsr_write(rt2x00dev
, 57, 0x77);
2814 rt2800_rfcsr_write(rt2x00dev
, 60, 0x05);
2815 rt2800_rfcsr_write(rt2x00dev
, 61, 0x01);
2817 /* TODO RF27 <- tssi */
2819 if (rf
->channel
>= 36 && rf
->channel
<= 64) {
2821 rt2800_rfcsr_write(rt2x00dev
, 12, 0x2E);
2822 rt2800_rfcsr_write(rt2x00dev
, 13, 0x22);
2823 rt2800_rfcsr_write(rt2x00dev
, 22, 0x60);
2824 rt2800_rfcsr_write(rt2x00dev
, 23, 0x7F);
2825 if (rf
->channel
<= 50)
2826 rt2800_rfcsr_write(rt2x00dev
, 24, 0x09);
2827 else if (rf
->channel
>= 52)
2828 rt2800_rfcsr_write(rt2x00dev
, 24, 0x07);
2829 rt2800_rfcsr_write(rt2x00dev
, 39, 0x1C);
2830 rt2800_rfcsr_write(rt2x00dev
, 43, 0x5B);
2831 rt2800_rfcsr_write(rt2x00dev
, 44, 0X40);
2832 rt2800_rfcsr_write(rt2x00dev
, 46, 0X00);
2833 rt2800_rfcsr_write(rt2x00dev
, 51, 0xFE);
2834 rt2800_rfcsr_write(rt2x00dev
, 52, 0x0C);
2835 rt2800_rfcsr_write(rt2x00dev
, 54, 0xF8);
2836 if (rf
->channel
<= 50) {
2837 rt2800_rfcsr_write(rt2x00dev
, 55, 0x06),
2838 rt2800_rfcsr_write(rt2x00dev
, 56, 0xD3);
2839 } else if (rf
->channel
>= 52) {
2840 rt2800_rfcsr_write(rt2x00dev
, 55, 0x04);
2841 rt2800_rfcsr_write(rt2x00dev
, 56, 0xBB);
2844 rt2800_rfcsr_write(rt2x00dev
, 58, 0x15);
2845 rt2800_rfcsr_write(rt2x00dev
, 59, 0x7F);
2846 rt2800_rfcsr_write(rt2x00dev
, 62, 0x15);
2848 } else if (rf
->channel
>= 100 && rf
->channel
<= 165) {
2850 rt2800_rfcsr_write(rt2x00dev
, 12, 0x0E);
2851 rt2800_rfcsr_write(rt2x00dev
, 13, 0x42);
2852 rt2800_rfcsr_write(rt2x00dev
, 22, 0x40);
2853 if (rf
->channel
<= 153) {
2854 rt2800_rfcsr_write(rt2x00dev
, 23, 0x3C);
2855 rt2800_rfcsr_write(rt2x00dev
, 24, 0x06);
2856 } else if (rf
->channel
>= 155) {
2857 rt2800_rfcsr_write(rt2x00dev
, 23, 0x38);
2858 rt2800_rfcsr_write(rt2x00dev
, 24, 0x05);
2860 if (rf
->channel
<= 138) {
2861 rt2800_rfcsr_write(rt2x00dev
, 39, 0x1A);
2862 rt2800_rfcsr_write(rt2x00dev
, 43, 0x3B);
2863 rt2800_rfcsr_write(rt2x00dev
, 44, 0x20);
2864 rt2800_rfcsr_write(rt2x00dev
, 46, 0x18);
2865 } else if (rf
->channel
>= 140) {
2866 rt2800_rfcsr_write(rt2x00dev
, 39, 0x18);
2867 rt2800_rfcsr_write(rt2x00dev
, 43, 0x1B);
2868 rt2800_rfcsr_write(rt2x00dev
, 44, 0x10);
2869 rt2800_rfcsr_write(rt2x00dev
, 46, 0X08);
2871 if (rf
->channel
<= 124)
2872 rt2800_rfcsr_write(rt2x00dev
, 51, 0xFC);
2873 else if (rf
->channel
>= 126)
2874 rt2800_rfcsr_write(rt2x00dev
, 51, 0xEC);
2875 if (rf
->channel
<= 138)
2876 rt2800_rfcsr_write(rt2x00dev
, 52, 0x06);
2877 else if (rf
->channel
>= 140)
2878 rt2800_rfcsr_write(rt2x00dev
, 52, 0x06);
2879 rt2800_rfcsr_write(rt2x00dev
, 54, 0xEB);
2880 if (rf
->channel
<= 138)
2881 rt2800_rfcsr_write(rt2x00dev
, 55, 0x01);
2882 else if (rf
->channel
>= 140)
2883 rt2800_rfcsr_write(rt2x00dev
, 55, 0x00);
2884 if (rf
->channel
<= 128)
2885 rt2800_rfcsr_write(rt2x00dev
, 56, 0xBB);
2886 else if (rf
->channel
>= 130)
2887 rt2800_rfcsr_write(rt2x00dev
, 56, 0xAB);
2888 if (rf
->channel
<= 116)
2889 rt2800_rfcsr_write(rt2x00dev
, 58, 0x1D);
2890 else if (rf
->channel
>= 118)
2891 rt2800_rfcsr_write(rt2x00dev
, 58, 0x15);
2892 if (rf
->channel
<= 138)
2893 rt2800_rfcsr_write(rt2x00dev
, 59, 0x3F);
2894 else if (rf
->channel
>= 140)
2895 rt2800_rfcsr_write(rt2x00dev
, 59, 0x7C);
2896 if (rf
->channel
<= 116)
2897 rt2800_rfcsr_write(rt2x00dev
, 62, 0x1D);
2898 else if (rf
->channel
>= 118)
2899 rt2800_rfcsr_write(rt2x00dev
, 62, 0x15);
2902 power_bound
= POWER_BOUND_5G
;
2906 rt2800_rfcsr_read(rt2x00dev
, 49, &rfcsr
);
2907 if (info
->default_power1
> power_bound
)
2908 rt2x00_set_field8(&rfcsr
, RFCSR49_TX
, power_bound
);
2910 rt2x00_set_field8(&rfcsr
, RFCSR49_TX
, info
->default_power1
);
2912 rt2x00_set_field8(&rfcsr
, RFCSR49_EP
, ep_reg
);
2913 rt2800_rfcsr_write(rt2x00dev
, 49, rfcsr
);
2915 rt2800_rfcsr_read(rt2x00dev
, 50, &rfcsr
);
2916 if (info
->default_power2
> power_bound
)
2917 rt2x00_set_field8(&rfcsr
, RFCSR50_TX
, power_bound
);
2919 rt2x00_set_field8(&rfcsr
, RFCSR50_TX
, info
->default_power2
);
2921 rt2x00_set_field8(&rfcsr
, RFCSR50_EP
, ep_reg
);
2922 rt2800_rfcsr_write(rt2x00dev
, 50, rfcsr
);
2924 rt2800_rfcsr_read(rt2x00dev
, 1, &rfcsr
);
2925 rt2x00_set_field8(&rfcsr
, RFCSR1_RF_BLOCK_EN
, 1);
2926 rt2x00_set_field8(&rfcsr
, RFCSR1_PLL_PD
, 1);
2928 rt2x00_set_field8(&rfcsr
, RFCSR1_TX0_PD
,
2929 rt2x00dev
->default_ant
.tx_chain_num
>= 1);
2930 rt2x00_set_field8(&rfcsr
, RFCSR1_TX1_PD
,
2931 rt2x00dev
->default_ant
.tx_chain_num
== 2);
2932 rt2x00_set_field8(&rfcsr
, RFCSR1_TX2_PD
, 0);
2934 rt2x00_set_field8(&rfcsr
, RFCSR1_RX0_PD
,
2935 rt2x00dev
->default_ant
.rx_chain_num
>= 1);
2936 rt2x00_set_field8(&rfcsr
, RFCSR1_RX1_PD
,
2937 rt2x00dev
->default_ant
.rx_chain_num
== 2);
2938 rt2x00_set_field8(&rfcsr
, RFCSR1_RX2_PD
, 0);
2940 rt2800_rfcsr_write(rt2x00dev
, 1, rfcsr
);
2941 rt2800_rfcsr_write(rt2x00dev
, 6, 0xe4);
2943 if (conf_is_ht40(conf
))
2944 rt2800_rfcsr_write(rt2x00dev
, 30, 0x16);
2946 rt2800_rfcsr_write(rt2x00dev
, 30, 0x10);
2949 rt2800_rfcsr_write(rt2x00dev
, 31, 0x80);
2950 rt2800_rfcsr_write(rt2x00dev
, 32, 0x80);
2953 /* TODO proper frequency adjustment */
2954 rt2800_adjust_freq_offset(rt2x00dev
);
2956 /* TODO merge with others */
2957 rt2800_rfcsr_read(rt2x00dev
, 3, &rfcsr
);
2958 rt2x00_set_field8(&rfcsr
, RFCSR3_VCOCAL_EN
, 1);
2959 rt2800_rfcsr_write(rt2x00dev
, 3, rfcsr
);
2962 rt2800_bbp_write(rt2x00dev
, 62, 0x37 - rt2x00dev
->lna_gain
);
2963 rt2800_bbp_write(rt2x00dev
, 63, 0x37 - rt2x00dev
->lna_gain
);
2964 rt2800_bbp_write(rt2x00dev
, 64, 0x37 - rt2x00dev
->lna_gain
);
2966 rt2800_bbp_write(rt2x00dev
, 79, (rf
->channel
<= 14) ? 0x1C : 0x18);
2967 rt2800_bbp_write(rt2x00dev
, 80, (rf
->channel
<= 14) ? 0x0E : 0x08);
2968 rt2800_bbp_write(rt2x00dev
, 81, (rf
->channel
<= 14) ? 0x3A : 0x38);
2969 rt2800_bbp_write(rt2x00dev
, 82, (rf
->channel
<= 14) ? 0x62 : 0x92);
2971 /* GLRT band configuration */
2972 rt2800_bbp_write(rt2x00dev
, 195, 128);
2973 rt2800_bbp_write(rt2x00dev
, 196, (rf
->channel
<= 14) ? 0xE0 : 0xF0);
2974 rt2800_bbp_write(rt2x00dev
, 195, 129);
2975 rt2800_bbp_write(rt2x00dev
, 196, (rf
->channel
<= 14) ? 0x1F : 0x1E);
2976 rt2800_bbp_write(rt2x00dev
, 195, 130);
2977 rt2800_bbp_write(rt2x00dev
, 196, (rf
->channel
<= 14) ? 0x38 : 0x28);
2978 rt2800_bbp_write(rt2x00dev
, 195, 131);
2979 rt2800_bbp_write(rt2x00dev
, 196, (rf
->channel
<= 14) ? 0x32 : 0x20);
2980 rt2800_bbp_write(rt2x00dev
, 195, 133);
2981 rt2800_bbp_write(rt2x00dev
, 196, (rf
->channel
<= 14) ? 0x28 : 0x7F);
2982 rt2800_bbp_write(rt2x00dev
, 195, 124);
2983 rt2800_bbp_write(rt2x00dev
, 196, (rf
->channel
<= 14) ? 0x19 : 0x7F);
2986 static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev
*rt2x00dev
,
2987 const unsigned int word
,
2992 for (chain
= 0; chain
< rt2x00dev
->default_ant
.rx_chain_num
; chain
++) {
2993 rt2800_bbp_read(rt2x00dev
, 27, ®
);
2994 rt2x00_set_field8(®
, BBP27_RX_CHAIN_SEL
, chain
);
2995 rt2800_bbp_write(rt2x00dev
, 27, reg
);
2997 rt2800_bbp_write(rt2x00dev
, word
, value
);
3001 static void rt2800_iq_calibrate(struct rt2x00_dev
*rt2x00dev
, int channel
)
3006 rt2800_bbp_write(rt2x00dev
, 158, 0x2c);
3008 cal
= rt2x00_eeprom_byte(rt2x00dev
, EEPROM_IQ_GAIN_CAL_TX0_2G
);
3009 else if (channel
>= 36 && channel
<= 64)
3010 cal
= rt2x00_eeprom_byte(rt2x00dev
,
3011 EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5G
);
3012 else if (channel
>= 100 && channel
<= 138)
3013 cal
= rt2x00_eeprom_byte(rt2x00dev
,
3014 EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5G
);
3015 else if (channel
>= 140 && channel
<= 165)
3016 cal
= rt2x00_eeprom_byte(rt2x00dev
,
3017 EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5G
);
3020 rt2800_bbp_write(rt2x00dev
, 159, cal
);
3023 rt2800_bbp_write(rt2x00dev
, 158, 0x2d);
3025 cal
= rt2x00_eeprom_byte(rt2x00dev
, EEPROM_IQ_PHASE_CAL_TX0_2G
);
3026 else if (channel
>= 36 && channel
<= 64)
3027 cal
= rt2x00_eeprom_byte(rt2x00dev
,
3028 EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5G
);
3029 else if (channel
>= 100 && channel
<= 138)
3030 cal
= rt2x00_eeprom_byte(rt2x00dev
,
3031 EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5G
);
3032 else if (channel
>= 140 && channel
<= 165)
3033 cal
= rt2x00_eeprom_byte(rt2x00dev
,
3034 EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5G
);
3037 rt2800_bbp_write(rt2x00dev
, 159, cal
);
3040 rt2800_bbp_write(rt2x00dev
, 158, 0x4a);
3042 cal
= rt2x00_eeprom_byte(rt2x00dev
, EEPROM_IQ_GAIN_CAL_TX1_2G
);
3043 else if (channel
>= 36 && channel
<= 64)
3044 cal
= rt2x00_eeprom_byte(rt2x00dev
,
3045 EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5G
);
3046 else if (channel
>= 100 && channel
<= 138)
3047 cal
= rt2x00_eeprom_byte(rt2x00dev
,
3048 EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5G
);
3049 else if (channel
>= 140 && channel
<= 165)
3050 cal
= rt2x00_eeprom_byte(rt2x00dev
,
3051 EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5G
);
3054 rt2800_bbp_write(rt2x00dev
, 159, cal
);
3057 rt2800_bbp_write(rt2x00dev
, 158, 0x4b);
3059 cal
= rt2x00_eeprom_byte(rt2x00dev
, EEPROM_IQ_PHASE_CAL_TX1_2G
);
3060 else if (channel
>= 36 && channel
<= 64)
3061 cal
= rt2x00_eeprom_byte(rt2x00dev
,
3062 EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5G
);
3063 else if (channel
>= 100 && channel
<= 138)
3064 cal
= rt2x00_eeprom_byte(rt2x00dev
,
3065 EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5G
);
3066 else if (channel
>= 140 && channel
<= 165)
3067 cal
= rt2x00_eeprom_byte(rt2x00dev
,
3068 EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5G
);
3071 rt2800_bbp_write(rt2x00dev
, 159, cal
);
3073 /* FIXME: possible RX0, RX1 callibration ? */
3075 /* RF IQ compensation control */
3076 rt2800_bbp_write(rt2x00dev
, 158, 0x04);
3077 cal
= rt2x00_eeprom_byte(rt2x00dev
, EEPROM_RF_IQ_COMPENSATION_CONTROL
);
3078 rt2800_bbp_write(rt2x00dev
, 159, cal
!= 0xff ? cal
: 0);
3080 /* RF IQ imbalance compensation control */
3081 rt2800_bbp_write(rt2x00dev
, 158, 0x03);
3082 cal
= rt2x00_eeprom_byte(rt2x00dev
,
3083 EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CONTROL
);
3084 rt2800_bbp_write(rt2x00dev
, 159, cal
!= 0xff ? cal
: 0);
3087 static char rt2800_txpower_to_dev(struct rt2x00_dev
*rt2x00dev
,
3088 unsigned int channel
,
3091 if (rt2x00_rt(rt2x00dev
, RT3593
))
3092 txpower
= rt2x00_get_field8(txpower
, EEPROM_TXPOWER_ALC
);
3095 return clamp_t(char, txpower
, MIN_G_TXPOWER
, MAX_G_TXPOWER
);
3097 if (rt2x00_rt(rt2x00dev
, RT3593
))
3098 return clamp_t(char, txpower
, MIN_A_TXPOWER_3593
,
3099 MAX_A_TXPOWER_3593
);
3101 return clamp_t(char, txpower
, MIN_A_TXPOWER
, MAX_A_TXPOWER
);
3104 static void rt2800_config_channel(struct rt2x00_dev
*rt2x00dev
,
3105 struct ieee80211_conf
*conf
,
3106 struct rf_channel
*rf
,
3107 struct channel_info
*info
)
3110 unsigned int tx_pin
;
3113 info
->default_power1
= rt2800_txpower_to_dev(rt2x00dev
, rf
->channel
,
3114 info
->default_power1
);
3115 info
->default_power2
= rt2800_txpower_to_dev(rt2x00dev
, rf
->channel
,
3116 info
->default_power2
);
3117 if (rt2x00dev
->default_ant
.tx_chain_num
> 2)
3118 info
->default_power3
=
3119 rt2800_txpower_to_dev(rt2x00dev
, rf
->channel
,
3120 info
->default_power3
);
3122 switch (rt2x00dev
->chip
.rf
) {
3128 rt2800_config_channel_rf3xxx(rt2x00dev
, conf
, rf
, info
);
3131 rt2800_config_channel_rf3052(rt2x00dev
, conf
, rf
, info
);
3134 rt2800_config_channel_rf3053(rt2x00dev
, conf
, rf
, info
);
3137 rt2800_config_channel_rf3290(rt2x00dev
, conf
, rf
, info
);
3140 rt2800_config_channel_rf3322(rt2x00dev
, conf
, rf
, info
);
3147 rt2800_config_channel_rf53xx(rt2x00dev
, conf
, rf
, info
);
3150 rt2800_config_channel_rf55xx(rt2x00dev
, conf
, rf
, info
);
3153 rt2800_config_channel_rf2xxx(rt2x00dev
, conf
, rf
, info
);
3156 if (rt2x00_rf(rt2x00dev
, RF3290
) ||
3157 rt2x00_rf(rt2x00dev
, RF3322
) ||
3158 rt2x00_rf(rt2x00dev
, RF5360
) ||
3159 rt2x00_rf(rt2x00dev
, RF5370
) ||
3160 rt2x00_rf(rt2x00dev
, RF5372
) ||
3161 rt2x00_rf(rt2x00dev
, RF5390
) ||
3162 rt2x00_rf(rt2x00dev
, RF5392
)) {
3163 rt2800_rfcsr_read(rt2x00dev
, 30, &rfcsr
);
3164 rt2x00_set_field8(&rfcsr
, RFCSR30_TX_H20M
, 0);
3165 rt2x00_set_field8(&rfcsr
, RFCSR30_RX_H20M
, 0);
3166 rt2800_rfcsr_write(rt2x00dev
, 30, rfcsr
);
3168 rt2800_rfcsr_read(rt2x00dev
, 3, &rfcsr
);
3169 rt2x00_set_field8(&rfcsr
, RFCSR3_VCOCAL_EN
, 1);
3170 rt2800_rfcsr_write(rt2x00dev
, 3, rfcsr
);
3174 * Change BBP settings
3176 if (rt2x00_rt(rt2x00dev
, RT3352
)) {
3177 rt2800_bbp_write(rt2x00dev
, 27, 0x0);
3178 rt2800_bbp_write(rt2x00dev
, 66, 0x26 + rt2x00dev
->lna_gain
);
3179 rt2800_bbp_write(rt2x00dev
, 27, 0x20);
3180 rt2800_bbp_write(rt2x00dev
, 66, 0x26 + rt2x00dev
->lna_gain
);
3181 } else if (rt2x00_rt(rt2x00dev
, RT3593
)) {
3182 if (rf
->channel
> 14) {
3183 /* Disable CCK Packet detection on 5GHz */
3184 rt2800_bbp_write(rt2x00dev
, 70, 0x00);
3186 rt2800_bbp_write(rt2x00dev
, 70, 0x0a);
3189 if (conf_is_ht40(conf
))
3190 rt2800_bbp_write(rt2x00dev
, 105, 0x04);
3192 rt2800_bbp_write(rt2x00dev
, 105, 0x34);
3194 rt2800_bbp_write(rt2x00dev
, 62, 0x37 - rt2x00dev
->lna_gain
);
3195 rt2800_bbp_write(rt2x00dev
, 63, 0x37 - rt2x00dev
->lna_gain
);
3196 rt2800_bbp_write(rt2x00dev
, 64, 0x37 - rt2x00dev
->lna_gain
);
3197 rt2800_bbp_write(rt2x00dev
, 77, 0x98);
3199 rt2800_bbp_write(rt2x00dev
, 62, 0x37 - rt2x00dev
->lna_gain
);
3200 rt2800_bbp_write(rt2x00dev
, 63, 0x37 - rt2x00dev
->lna_gain
);
3201 rt2800_bbp_write(rt2x00dev
, 64, 0x37 - rt2x00dev
->lna_gain
);
3202 rt2800_bbp_write(rt2x00dev
, 86, 0);
3205 if (rf
->channel
<= 14) {
3206 if (!rt2x00_rt(rt2x00dev
, RT5390
) &&
3207 !rt2x00_rt(rt2x00dev
, RT5392
)) {
3208 if (test_bit(CAPABILITY_EXTERNAL_LNA_BG
,
3209 &rt2x00dev
->cap_flags
)) {
3210 rt2800_bbp_write(rt2x00dev
, 82, 0x62);
3211 rt2800_bbp_write(rt2x00dev
, 75, 0x46);
3213 if (rt2x00_rt(rt2x00dev
, RT3593
))
3214 rt2800_bbp_write(rt2x00dev
, 82, 0x62);
3216 rt2800_bbp_write(rt2x00dev
, 82, 0x84);
3217 rt2800_bbp_write(rt2x00dev
, 75, 0x50);
3219 if (rt2x00_rt(rt2x00dev
, RT3593
))
3220 rt2800_bbp_write(rt2x00dev
, 83, 0x8a);
3224 if (rt2x00_rt(rt2x00dev
, RT3572
))
3225 rt2800_bbp_write(rt2x00dev
, 82, 0x94);
3226 else if (rt2x00_rt(rt2x00dev
, RT3593
))
3227 rt2800_bbp_write(rt2x00dev
, 82, 0x82);
3229 rt2800_bbp_write(rt2x00dev
, 82, 0xf2);
3231 if (rt2x00_rt(rt2x00dev
, RT3593
))
3232 rt2800_bbp_write(rt2x00dev
, 83, 0x9a);
3234 if (test_bit(CAPABILITY_EXTERNAL_LNA_A
, &rt2x00dev
->cap_flags
))
3235 rt2800_bbp_write(rt2x00dev
, 75, 0x46);
3237 rt2800_bbp_write(rt2x00dev
, 75, 0x50);
3240 rt2800_register_read(rt2x00dev
, TX_BAND_CFG
, ®
);
3241 rt2x00_set_field32(®
, TX_BAND_CFG_HT40_MINUS
, conf_is_ht40_minus(conf
));
3242 rt2x00_set_field32(®
, TX_BAND_CFG_A
, rf
->channel
> 14);
3243 rt2x00_set_field32(®
, TX_BAND_CFG_BG
, rf
->channel
<= 14);
3244 rt2800_register_write(rt2x00dev
, TX_BAND_CFG
, reg
);
3246 if (rt2x00_rt(rt2x00dev
, RT3572
))
3247 rt2800_rfcsr_write(rt2x00dev
, 8, 0);
3251 switch (rt2x00dev
->default_ant
.tx_chain_num
) {
3253 /* Turn on tertiary PAs */
3254 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_A2_EN
,
3256 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_G2_EN
,
3260 /* Turn on secondary PAs */
3261 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_A1_EN
,
3263 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_G1_EN
,
3267 /* Turn on primary PAs */
3268 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_A0_EN
,
3270 if (test_bit(CAPABILITY_BT_COEXIST
, &rt2x00dev
->cap_flags
))
3271 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_G0_EN
, 1);
3273 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_G0_EN
,
3278 switch (rt2x00dev
->default_ant
.rx_chain_num
) {
3280 /* Turn on tertiary LNAs */
3281 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_LNA_PE_A2_EN
, 1);
3282 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_LNA_PE_G2_EN
, 1);
3285 /* Turn on secondary LNAs */
3286 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_LNA_PE_A1_EN
, 1);
3287 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_LNA_PE_G1_EN
, 1);
3290 /* Turn on primary LNAs */
3291 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_LNA_PE_A0_EN
, 1);
3292 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_LNA_PE_G0_EN
, 1);
3296 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_RFTR_EN
, 1);
3297 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_TRSW_EN
, 1);
3299 rt2800_register_write(rt2x00dev
, TX_PIN_CFG
, tx_pin
);
3301 if (rt2x00_rt(rt2x00dev
, RT3572
))
3302 rt2800_rfcsr_write(rt2x00dev
, 8, 0x80);
3304 if (rt2x00_rt(rt2x00dev
, RT3593
)) {
3305 if (rt2x00_is_usb(rt2x00dev
)) {
3306 rt2800_register_read(rt2x00dev
, GPIO_CTRL
, ®
);
3308 /* Band selection. GPIO #8 controls all paths */
3309 rt2x00_set_field32(®
, GPIO_CTRL_DIR8
, 0);
3310 if (rf
->channel
<= 14)
3311 rt2x00_set_field32(®
, GPIO_CTRL_VAL8
, 1);
3313 rt2x00_set_field32(®
, GPIO_CTRL_VAL8
, 0);
3315 rt2x00_set_field32(®
, GPIO_CTRL_DIR4
, 0);
3316 rt2x00_set_field32(®
, GPIO_CTRL_DIR7
, 0);
3319 * GPIO #4 controls PE0 and PE1,
3320 * GPIO #7 controls PE2
3322 rt2x00_set_field32(®
, GPIO_CTRL_VAL4
, 1);
3323 rt2x00_set_field32(®
, GPIO_CTRL_VAL7
, 1);
3325 rt2800_register_write(rt2x00dev
, GPIO_CTRL
, reg
);
3329 if (rf
->channel
<= 14)
3330 reg
= 0x1c + 2 * rt2x00dev
->lna_gain
;
3332 reg
= 0x22 + ((rt2x00dev
->lna_gain
* 5) / 3);
3334 rt2800_bbp_write_with_rx_chain(rt2x00dev
, 66, reg
);
3336 usleep_range(1000, 1500);
3339 if (rt2x00_rt(rt2x00dev
, RT5592
)) {
3340 rt2800_bbp_write(rt2x00dev
, 195, 141);
3341 rt2800_bbp_write(rt2x00dev
, 196, conf_is_ht40(conf
) ? 0x10 : 0x1a);
3344 reg
= (rf
->channel
<= 14 ? 0x1c : 0x24) + 2 * rt2x00dev
->lna_gain
;
3345 rt2800_bbp_write_with_rx_chain(rt2x00dev
, 66, reg
);
3347 rt2800_iq_calibrate(rt2x00dev
, rf
->channel
);
3350 rt2800_bbp_read(rt2x00dev
, 4, &bbp
);
3351 rt2x00_set_field8(&bbp
, BBP4_BANDWIDTH
, 2 * conf_is_ht40(conf
));
3352 rt2800_bbp_write(rt2x00dev
, 4, bbp
);
3354 rt2800_bbp_read(rt2x00dev
, 3, &bbp
);
3355 rt2x00_set_field8(&bbp
, BBP3_HT40_MINUS
, conf_is_ht40_minus(conf
));
3356 rt2800_bbp_write(rt2x00dev
, 3, bbp
);
3358 if (rt2x00_rt_rev(rt2x00dev
, RT2860
, REV_RT2860C
)) {
3359 if (conf_is_ht40(conf
)) {
3360 rt2800_bbp_write(rt2x00dev
, 69, 0x1a);
3361 rt2800_bbp_write(rt2x00dev
, 70, 0x0a);
3362 rt2800_bbp_write(rt2x00dev
, 73, 0x16);
3364 rt2800_bbp_write(rt2x00dev
, 69, 0x16);
3365 rt2800_bbp_write(rt2x00dev
, 70, 0x08);
3366 rt2800_bbp_write(rt2x00dev
, 73, 0x11);
3373 * Clear channel statistic counters
3375 rt2800_register_read(rt2x00dev
, CH_IDLE_STA
, ®
);
3376 rt2800_register_read(rt2x00dev
, CH_BUSY_STA
, ®
);
3377 rt2800_register_read(rt2x00dev
, CH_BUSY_STA_SEC
, ®
);
3382 if (rt2x00_rt(rt2x00dev
, RT3352
)) {
3383 rt2800_bbp_read(rt2x00dev
, 49, &bbp
);
3384 rt2x00_set_field8(&bbp
, BBP49_UPDATE_FLAG
, 0);
3385 rt2800_bbp_write(rt2x00dev
, 49, bbp
);
3389 static int rt2800_get_gain_calibration_delta(struct rt2x00_dev
*rt2x00dev
)
3398 * Read TSSI boundaries for temperature compensation from
3401 * Array idx 0 1 2 3 4 5 6 7 8
3402 * Matching Delta value -4 -3 -2 -1 0 +1 +2 +3 +4
3403 * Example TSSI bounds 0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
3405 if (rt2x00dev
->curr_band
== IEEE80211_BAND_2GHZ
) {
3406 rt2800_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_BG1
, &eeprom
);
3407 tssi_bounds
[0] = rt2x00_get_field16(eeprom
,
3408 EEPROM_TSSI_BOUND_BG1_MINUS4
);
3409 tssi_bounds
[1] = rt2x00_get_field16(eeprom
,
3410 EEPROM_TSSI_BOUND_BG1_MINUS3
);
3412 rt2800_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_BG2
, &eeprom
);
3413 tssi_bounds
[2] = rt2x00_get_field16(eeprom
,
3414 EEPROM_TSSI_BOUND_BG2_MINUS2
);
3415 tssi_bounds
[3] = rt2x00_get_field16(eeprom
,
3416 EEPROM_TSSI_BOUND_BG2_MINUS1
);
3418 rt2800_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_BG3
, &eeprom
);
3419 tssi_bounds
[4] = rt2x00_get_field16(eeprom
,
3420 EEPROM_TSSI_BOUND_BG3_REF
);
3421 tssi_bounds
[5] = rt2x00_get_field16(eeprom
,
3422 EEPROM_TSSI_BOUND_BG3_PLUS1
);
3424 rt2800_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_BG4
, &eeprom
);
3425 tssi_bounds
[6] = rt2x00_get_field16(eeprom
,
3426 EEPROM_TSSI_BOUND_BG4_PLUS2
);
3427 tssi_bounds
[7] = rt2x00_get_field16(eeprom
,
3428 EEPROM_TSSI_BOUND_BG4_PLUS3
);
3430 rt2800_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_BG5
, &eeprom
);
3431 tssi_bounds
[8] = rt2x00_get_field16(eeprom
,
3432 EEPROM_TSSI_BOUND_BG5_PLUS4
);
3434 step
= rt2x00_get_field16(eeprom
,
3435 EEPROM_TSSI_BOUND_BG5_AGC_STEP
);
3437 rt2800_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_A1
, &eeprom
);
3438 tssi_bounds
[0] = rt2x00_get_field16(eeprom
,
3439 EEPROM_TSSI_BOUND_A1_MINUS4
);
3440 tssi_bounds
[1] = rt2x00_get_field16(eeprom
,
3441 EEPROM_TSSI_BOUND_A1_MINUS3
);
3443 rt2800_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_A2
, &eeprom
);
3444 tssi_bounds
[2] = rt2x00_get_field16(eeprom
,
3445 EEPROM_TSSI_BOUND_A2_MINUS2
);
3446 tssi_bounds
[3] = rt2x00_get_field16(eeprom
,
3447 EEPROM_TSSI_BOUND_A2_MINUS1
);
3449 rt2800_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_A3
, &eeprom
);
3450 tssi_bounds
[4] = rt2x00_get_field16(eeprom
,
3451 EEPROM_TSSI_BOUND_A3_REF
);
3452 tssi_bounds
[5] = rt2x00_get_field16(eeprom
,
3453 EEPROM_TSSI_BOUND_A3_PLUS1
);
3455 rt2800_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_A4
, &eeprom
);
3456 tssi_bounds
[6] = rt2x00_get_field16(eeprom
,
3457 EEPROM_TSSI_BOUND_A4_PLUS2
);
3458 tssi_bounds
[7] = rt2x00_get_field16(eeprom
,
3459 EEPROM_TSSI_BOUND_A4_PLUS3
);
3461 rt2800_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_A5
, &eeprom
);
3462 tssi_bounds
[8] = rt2x00_get_field16(eeprom
,
3463 EEPROM_TSSI_BOUND_A5_PLUS4
);
3465 step
= rt2x00_get_field16(eeprom
,
3466 EEPROM_TSSI_BOUND_A5_AGC_STEP
);
3470 * Check if temperature compensation is supported.
3472 if (tssi_bounds
[4] == 0xff || step
== 0xff)
3476 * Read current TSSI (BBP 49).
3478 rt2800_bbp_read(rt2x00dev
, 49, ¤t_tssi
);
3481 * Compare TSSI value (BBP49) with the compensation boundaries
3482 * from the EEPROM and increase or decrease tx power.
3484 for (i
= 0; i
<= 3; i
++) {
3485 if (current_tssi
> tssi_bounds
[i
])
3490 for (i
= 8; i
>= 5; i
--) {
3491 if (current_tssi
< tssi_bounds
[i
])
3496 return (i
- 4) * step
;
3499 static int rt2800_get_txpower_bw_comp(struct rt2x00_dev
*rt2x00dev
,
3500 enum ieee80211_band band
)
3507 rt2800_eeprom_read(rt2x00dev
, EEPROM_TXPOWER_DELTA
, &eeprom
);
3510 * HT40 compensation not required.
3512 if (eeprom
== 0xffff ||
3513 !test_bit(CONFIG_CHANNEL_HT40
, &rt2x00dev
->flags
))
3516 if (band
== IEEE80211_BAND_2GHZ
) {
3517 comp_en
= rt2x00_get_field16(eeprom
,
3518 EEPROM_TXPOWER_DELTA_ENABLE_2G
);
3520 comp_type
= rt2x00_get_field16(eeprom
,
3521 EEPROM_TXPOWER_DELTA_TYPE_2G
);
3522 comp_value
= rt2x00_get_field16(eeprom
,
3523 EEPROM_TXPOWER_DELTA_VALUE_2G
);
3525 comp_value
= -comp_value
;
3528 comp_en
= rt2x00_get_field16(eeprom
,
3529 EEPROM_TXPOWER_DELTA_ENABLE_5G
);
3531 comp_type
= rt2x00_get_field16(eeprom
,
3532 EEPROM_TXPOWER_DELTA_TYPE_5G
);
3533 comp_value
= rt2x00_get_field16(eeprom
,
3534 EEPROM_TXPOWER_DELTA_VALUE_5G
);
3536 comp_value
= -comp_value
;
3543 static int rt2800_get_txpower_reg_delta(struct rt2x00_dev
*rt2x00dev
,
3544 int power_level
, int max_power
)
3548 if (test_bit(CAPABILITY_POWER_LIMIT
, &rt2x00dev
->cap_flags
))
3552 * XXX: We don't know the maximum transmit power of our hardware since
3553 * the EEPROM doesn't expose it. We only know that we are calibrated
3556 * Hence, we assume the regulatory limit that cfg80211 calulated for
3557 * the current channel is our maximum and if we are requested to lower
3558 * the value we just reduce our tx power accordingly.
3560 delta
= power_level
- max_power
;
3561 return min(delta
, 0);
3564 static u8
rt2800_compensate_txpower(struct rt2x00_dev
*rt2x00dev
, int is_rate_b
,
3565 enum ieee80211_band band
, int power_level
,
3566 u8 txpower
, int delta
)
3571 u8 eirp_txpower_criterion
;
3574 if (rt2x00_rt(rt2x00dev
, RT3593
))
3575 return min_t(u8
, txpower
, 0xc);
3577 if (test_bit(CAPABILITY_POWER_LIMIT
, &rt2x00dev
->cap_flags
)) {
3579 * Check if eirp txpower exceed txpower_limit.
3580 * We use OFDM 6M as criterion and its eirp txpower
3581 * is stored at EEPROM_EIRP_MAX_TX_POWER.
3582 * .11b data rate need add additional 4dbm
3583 * when calculating eirp txpower.
3585 rt2800_eeprom_read_from_array(rt2x00dev
, EEPROM_TXPOWER_BYRATE
,
3587 criterion
= rt2x00_get_field16(eeprom
,
3588 EEPROM_TXPOWER_BYRATE_RATE0
);
3590 rt2800_eeprom_read(rt2x00dev
, EEPROM_EIRP_MAX_TX_POWER
,
3593 if (band
== IEEE80211_BAND_2GHZ
)
3594 eirp_txpower_criterion
= rt2x00_get_field16(eeprom
,
3595 EEPROM_EIRP_MAX_TX_POWER_2GHZ
);
3597 eirp_txpower_criterion
= rt2x00_get_field16(eeprom
,
3598 EEPROM_EIRP_MAX_TX_POWER_5GHZ
);
3600 eirp_txpower
= eirp_txpower_criterion
+ (txpower
- criterion
) +
3601 (is_rate_b
? 4 : 0) + delta
;
3603 reg_limit
= (eirp_txpower
> power_level
) ?
3604 (eirp_txpower
- power_level
) : 0;
3608 txpower
= max(0, txpower
+ delta
- reg_limit
);
3609 return min_t(u8
, txpower
, 0xc);
3624 TX_PWR_CFG_0_EXT_IDX
,
3625 TX_PWR_CFG_1_EXT_IDX
,
3626 TX_PWR_CFG_2_EXT_IDX
,
3627 TX_PWR_CFG_3_EXT_IDX
,
3628 TX_PWR_CFG_4_EXT_IDX
,
3629 TX_PWR_CFG_IDX_COUNT
,
3632 static void rt2800_config_txpower_rt3593(struct rt2x00_dev
*rt2x00dev
,
3633 struct ieee80211_channel
*chan
,
3638 u32 regs
[TX_PWR_CFG_IDX_COUNT
];
3639 unsigned int offset
;
3640 enum ieee80211_band band
= chan
->band
;
3644 memset(regs
, '\0', sizeof(regs
));
3646 /* TODO: adapt TX power reduction from the rt28xx code */
3648 /* calculate temperature compensation delta */
3649 delta
= rt2800_get_gain_calibration_delta(rt2x00dev
);
3651 if (band
== IEEE80211_BAND_5GHZ
)
3656 if (test_bit(CONFIG_CHANNEL_HT40
, &rt2x00dev
->flags
))
3659 /* read the next four txpower values */
3660 rt2800_eeprom_read_from_array(rt2x00dev
, EEPROM_TXPOWER_BYRATE
,
3664 txpower
= rt2x00_get_field16(eeprom
, EEPROM_TXPOWER_BYRATE_RATE0
);
3665 txpower
= rt2800_compensate_txpower(rt2x00dev
, 1, band
, power_level
,
3667 rt2x00_set_field32(®s
[TX_PWR_CFG_0_IDX
],
3668 TX_PWR_CFG_0_CCK1_CH0
, txpower
);
3669 rt2x00_set_field32(®s
[TX_PWR_CFG_0_IDX
],
3670 TX_PWR_CFG_0_CCK1_CH1
, txpower
);
3671 rt2x00_set_field32(®s
[TX_PWR_CFG_0_EXT_IDX
],
3672 TX_PWR_CFG_0_EXT_CCK1_CH2
, txpower
);
3674 /* CCK 5.5MBS,11MBS */
3675 txpower
= rt2x00_get_field16(eeprom
, EEPROM_TXPOWER_BYRATE_RATE1
);
3676 txpower
= rt2800_compensate_txpower(rt2x00dev
, 1, band
, power_level
,
3678 rt2x00_set_field32(®s
[TX_PWR_CFG_0_IDX
],
3679 TX_PWR_CFG_0_CCK5_CH0
, txpower
);
3680 rt2x00_set_field32(®s
[TX_PWR_CFG_0_IDX
],
3681 TX_PWR_CFG_0_CCK5_CH1
, txpower
);
3682 rt2x00_set_field32(®s
[TX_PWR_CFG_0_EXT_IDX
],
3683 TX_PWR_CFG_0_EXT_CCK5_CH2
, txpower
);
3685 /* OFDM 6MBS,9MBS */
3686 txpower
= rt2x00_get_field16(eeprom
, EEPROM_TXPOWER_BYRATE_RATE2
);
3687 txpower
= rt2800_compensate_txpower(rt2x00dev
, 0, band
, power_level
,
3689 rt2x00_set_field32(®s
[TX_PWR_CFG_0_IDX
],
3690 TX_PWR_CFG_0_OFDM6_CH0
, txpower
);
3691 rt2x00_set_field32(®s
[TX_PWR_CFG_0_IDX
],
3692 TX_PWR_CFG_0_OFDM6_CH1
, txpower
);
3693 rt2x00_set_field32(®s
[TX_PWR_CFG_0_EXT_IDX
],
3694 TX_PWR_CFG_0_EXT_OFDM6_CH2
, txpower
);
3696 /* OFDM 12MBS,18MBS */
3697 txpower
= rt2x00_get_field16(eeprom
, EEPROM_TXPOWER_BYRATE_RATE3
);
3698 txpower
= rt2800_compensate_txpower(rt2x00dev
, 0, band
, power_level
,
3700 rt2x00_set_field32(®s
[TX_PWR_CFG_0_IDX
],
3701 TX_PWR_CFG_0_OFDM12_CH0
, txpower
);
3702 rt2x00_set_field32(®s
[TX_PWR_CFG_0_IDX
],
3703 TX_PWR_CFG_0_OFDM12_CH1
, txpower
);
3704 rt2x00_set_field32(®s
[TX_PWR_CFG_0_EXT_IDX
],
3705 TX_PWR_CFG_0_EXT_OFDM12_CH2
, txpower
);
3707 /* read the next four txpower values */
3708 rt2800_eeprom_read_from_array(rt2x00dev
, EEPROM_TXPOWER_BYRATE
,
3709 offset
+ 1, &eeprom
);
3711 /* OFDM 24MBS,36MBS */
3712 txpower
= rt2x00_get_field16(eeprom
, EEPROM_TXPOWER_BYRATE_RATE0
);
3713 txpower
= rt2800_compensate_txpower(rt2x00dev
, 0, band
, power_level
,
3715 rt2x00_set_field32(®s
[TX_PWR_CFG_1_IDX
],
3716 TX_PWR_CFG_1_OFDM24_CH0
, txpower
);
3717 rt2x00_set_field32(®s
[TX_PWR_CFG_1_IDX
],
3718 TX_PWR_CFG_1_OFDM24_CH1
, txpower
);
3719 rt2x00_set_field32(®s
[TX_PWR_CFG_1_EXT_IDX
],
3720 TX_PWR_CFG_1_EXT_OFDM24_CH2
, txpower
);
3723 txpower
= rt2x00_get_field16(eeprom
, EEPROM_TXPOWER_BYRATE_RATE1
);
3724 txpower
= rt2800_compensate_txpower(rt2x00dev
, 0, band
, power_level
,
3726 rt2x00_set_field32(®s
[TX_PWR_CFG_1_IDX
],
3727 TX_PWR_CFG_1_OFDM48_CH0
, txpower
);
3728 rt2x00_set_field32(®s
[TX_PWR_CFG_1_IDX
],
3729 TX_PWR_CFG_1_OFDM48_CH1
, txpower
);
3730 rt2x00_set_field32(®s
[TX_PWR_CFG_1_EXT_IDX
],
3731 TX_PWR_CFG_1_EXT_OFDM48_CH2
, txpower
);
3734 txpower
= rt2x00_get_field16(eeprom
, EEPROM_TXPOWER_BYRATE_RATE2
);
3735 txpower
= rt2800_compensate_txpower(rt2x00dev
, 0, band
, power_level
,
3737 rt2x00_set_field32(®s
[TX_PWR_CFG_7_IDX
],
3738 TX_PWR_CFG_7_OFDM54_CH0
, txpower
);
3739 rt2x00_set_field32(®s
[TX_PWR_CFG_7_IDX
],
3740 TX_PWR_CFG_7_OFDM54_CH1
, txpower
);
3741 rt2x00_set_field32(®s
[TX_PWR_CFG_7_IDX
],
3742 TX_PWR_CFG_7_OFDM54_CH2
, txpower
);
3744 /* read the next four txpower values */
3745 rt2800_eeprom_read_from_array(rt2x00dev
, EEPROM_TXPOWER_BYRATE
,
3746 offset
+ 2, &eeprom
);
3749 txpower
= rt2x00_get_field16(eeprom
, EEPROM_TXPOWER_BYRATE_RATE0
);
3750 txpower
= rt2800_compensate_txpower(rt2x00dev
, 0, band
, power_level
,
3752 rt2x00_set_field32(®s
[TX_PWR_CFG_1_IDX
],
3753 TX_PWR_CFG_1_MCS0_CH0
, txpower
);
3754 rt2x00_set_field32(®s
[TX_PWR_CFG_1_IDX
],
3755 TX_PWR_CFG_1_MCS0_CH1
, txpower
);
3756 rt2x00_set_field32(®s
[TX_PWR_CFG_1_EXT_IDX
],
3757 TX_PWR_CFG_1_EXT_MCS0_CH2
, txpower
);
3760 txpower
= rt2x00_get_field16(eeprom
, EEPROM_TXPOWER_BYRATE_RATE1
);
3761 txpower
= rt2800_compensate_txpower(rt2x00dev
, 0, band
, power_level
,
3763 rt2x00_set_field32(®s
[TX_PWR_CFG_1_IDX
],
3764 TX_PWR_CFG_1_MCS2_CH0
, txpower
);
3765 rt2x00_set_field32(®s
[TX_PWR_CFG_1_IDX
],
3766 TX_PWR_CFG_1_MCS2_CH1
, txpower
);
3767 rt2x00_set_field32(®s
[TX_PWR_CFG_1_EXT_IDX
],
3768 TX_PWR_CFG_1_EXT_MCS2_CH2
, txpower
);
3771 txpower
= rt2x00_get_field16(eeprom
, EEPROM_TXPOWER_BYRATE_RATE2
);
3772 txpower
= rt2800_compensate_txpower(rt2x00dev
, 0, band
, power_level
,
3774 rt2x00_set_field32(®s
[TX_PWR_CFG_2_IDX
],
3775 TX_PWR_CFG_2_MCS4_CH0
, txpower
);
3776 rt2x00_set_field32(®s
[TX_PWR_CFG_2_IDX
],
3777 TX_PWR_CFG_2_MCS4_CH1
, txpower
);
3778 rt2x00_set_field32(®s
[TX_PWR_CFG_2_EXT_IDX
],
3779 TX_PWR_CFG_2_EXT_MCS4_CH2
, txpower
);
3782 txpower
= rt2x00_get_field16(eeprom
, EEPROM_TXPOWER_BYRATE_RATE3
);
3783 txpower
= rt2800_compensate_txpower(rt2x00dev
, 0, band
, power_level
,
3785 rt2x00_set_field32(®s
[TX_PWR_CFG_2_IDX
],
3786 TX_PWR_CFG_2_MCS6_CH0
, txpower
);
3787 rt2x00_set_field32(®s
[TX_PWR_CFG_2_IDX
],
3788 TX_PWR_CFG_2_MCS6_CH1
, txpower
);
3789 rt2x00_set_field32(®s
[TX_PWR_CFG_2_EXT_IDX
],
3790 TX_PWR_CFG_2_EXT_MCS6_CH2
, txpower
);
3792 /* read the next four txpower values */
3793 rt2800_eeprom_read_from_array(rt2x00dev
, EEPROM_TXPOWER_BYRATE
,
3794 offset
+ 3, &eeprom
);
3797 txpower
= rt2x00_get_field16(eeprom
, EEPROM_TXPOWER_BYRATE_RATE0
);
3798 txpower
= rt2800_compensate_txpower(rt2x00dev
, 0, band
, power_level
,
3800 rt2x00_set_field32(®s
[TX_PWR_CFG_7_IDX
],
3801 TX_PWR_CFG_7_MCS7_CH0
, txpower
);
3802 rt2x00_set_field32(®s
[TX_PWR_CFG_7_IDX
],
3803 TX_PWR_CFG_7_MCS7_CH1
, txpower
);
3804 rt2x00_set_field32(®s
[TX_PWR_CFG_7_IDX
],
3805 TX_PWR_CFG_7_MCS7_CH2
, txpower
);
3808 txpower
= rt2x00_get_field16(eeprom
, EEPROM_TXPOWER_BYRATE_RATE1
);
3809 txpower
= rt2800_compensate_txpower(rt2x00dev
, 0, band
, power_level
,
3811 rt2x00_set_field32(®s
[TX_PWR_CFG_2_IDX
],
3812 TX_PWR_CFG_2_MCS8_CH0
, txpower
);
3813 rt2x00_set_field32(®s
[TX_PWR_CFG_2_IDX
],
3814 TX_PWR_CFG_2_MCS8_CH1
, txpower
);
3815 rt2x00_set_field32(®s
[TX_PWR_CFG_2_EXT_IDX
],
3816 TX_PWR_CFG_2_EXT_MCS8_CH2
, txpower
);
3819 txpower
= rt2x00_get_field16(eeprom
, EEPROM_TXPOWER_BYRATE_RATE2
);
3820 txpower
= rt2800_compensate_txpower(rt2x00dev
, 0, band
, power_level
,
3822 rt2x00_set_field32(®s
[TX_PWR_CFG_2_IDX
],
3823 TX_PWR_CFG_2_MCS10_CH0
, txpower
);
3824 rt2x00_set_field32(®s
[TX_PWR_CFG_2_IDX
],
3825 TX_PWR_CFG_2_MCS10_CH1
, txpower
);
3826 rt2x00_set_field32(®s
[TX_PWR_CFG_2_EXT_IDX
],
3827 TX_PWR_CFG_2_EXT_MCS10_CH2
, txpower
);
3830 txpower
= rt2x00_get_field16(eeprom
, EEPROM_TXPOWER_BYRATE_RATE3
);
3831 txpower
= rt2800_compensate_txpower(rt2x00dev
, 0, band
, power_level
,
3833 rt2x00_set_field32(®s
[TX_PWR_CFG_3_IDX
],
3834 TX_PWR_CFG_3_MCS12_CH0
, txpower
);
3835 rt2x00_set_field32(®s
[TX_PWR_CFG_3_IDX
],
3836 TX_PWR_CFG_3_MCS12_CH1
, txpower
);
3837 rt2x00_set_field32(®s
[TX_PWR_CFG_3_EXT_IDX
],
3838 TX_PWR_CFG_3_EXT_MCS12_CH2
, txpower
);
3840 /* read the next four txpower values */
3841 rt2800_eeprom_read_from_array(rt2x00dev
, EEPROM_TXPOWER_BYRATE
,
3842 offset
+ 4, &eeprom
);
3845 txpower
= rt2x00_get_field16(eeprom
, EEPROM_TXPOWER_BYRATE_RATE0
);
3846 txpower
= rt2800_compensate_txpower(rt2x00dev
, 0, band
, power_level
,
3848 rt2x00_set_field32(®s
[TX_PWR_CFG_3_IDX
],
3849 TX_PWR_CFG_3_MCS14_CH0
, txpower
);
3850 rt2x00_set_field32(®s
[TX_PWR_CFG_3_IDX
],
3851 TX_PWR_CFG_3_MCS14_CH1
, txpower
);
3852 rt2x00_set_field32(®s
[TX_PWR_CFG_3_EXT_IDX
],
3853 TX_PWR_CFG_3_EXT_MCS14_CH2
, txpower
);
3856 txpower
= rt2x00_get_field16(eeprom
, EEPROM_TXPOWER_BYRATE_RATE1
);
3857 txpower
= rt2800_compensate_txpower(rt2x00dev
, 0, band
, power_level
,
3859 rt2x00_set_field32(®s
[TX_PWR_CFG_8_IDX
],
3860 TX_PWR_CFG_8_MCS15_CH0
, txpower
);
3861 rt2x00_set_field32(®s
[TX_PWR_CFG_8_IDX
],
3862 TX_PWR_CFG_8_MCS15_CH1
, txpower
);
3863 rt2x00_set_field32(®s
[TX_PWR_CFG_8_IDX
],
3864 TX_PWR_CFG_8_MCS15_CH2
, txpower
);
3867 txpower
= rt2x00_get_field16(eeprom
, EEPROM_TXPOWER_BYRATE_RATE2
);
3868 txpower
= rt2800_compensate_txpower(rt2x00dev
, 0, band
, power_level
,
3870 rt2x00_set_field32(®s
[TX_PWR_CFG_5_IDX
],
3871 TX_PWR_CFG_5_MCS16_CH0
, txpower
);
3872 rt2x00_set_field32(®s
[TX_PWR_CFG_5_IDX
],
3873 TX_PWR_CFG_5_MCS16_CH1
, txpower
);
3874 rt2x00_set_field32(®s
[TX_PWR_CFG_5_IDX
],
3875 TX_PWR_CFG_5_MCS16_CH2
, txpower
);
3878 txpower
= rt2x00_get_field16(eeprom
, EEPROM_TXPOWER_BYRATE_RATE3
);
3879 txpower
= rt2800_compensate_txpower(rt2x00dev
, 0, band
, power_level
,
3881 rt2x00_set_field32(®s
[TX_PWR_CFG_5_IDX
],
3882 TX_PWR_CFG_5_MCS18_CH0
, txpower
);
3883 rt2x00_set_field32(®s
[TX_PWR_CFG_5_IDX
],
3884 TX_PWR_CFG_5_MCS18_CH1
, txpower
);
3885 rt2x00_set_field32(®s
[TX_PWR_CFG_5_IDX
],
3886 TX_PWR_CFG_5_MCS18_CH2
, txpower
);
3888 /* read the next four txpower values */
3889 rt2800_eeprom_read_from_array(rt2x00dev
, EEPROM_TXPOWER_BYRATE
,
3890 offset
+ 5, &eeprom
);
3893 txpower
= rt2x00_get_field16(eeprom
, EEPROM_TXPOWER_BYRATE_RATE0
);
3894 txpower
= rt2800_compensate_txpower(rt2x00dev
, 0, band
, power_level
,
3896 rt2x00_set_field32(®s
[TX_PWR_CFG_6_IDX
],
3897 TX_PWR_CFG_6_MCS20_CH0
, txpower
);
3898 rt2x00_set_field32(®s
[TX_PWR_CFG_6_IDX
],
3899 TX_PWR_CFG_6_MCS20_CH1
, txpower
);
3900 rt2x00_set_field32(®s
[TX_PWR_CFG_6_IDX
],
3901 TX_PWR_CFG_6_MCS20_CH2
, txpower
);
3904 txpower
= rt2x00_get_field16(eeprom
, EEPROM_TXPOWER_BYRATE_RATE1
);
3905 txpower
= rt2800_compensate_txpower(rt2x00dev
, 0, band
, power_level
,
3907 rt2x00_set_field32(®s
[TX_PWR_CFG_6_IDX
],
3908 TX_PWR_CFG_6_MCS22_CH0
, txpower
);
3909 rt2x00_set_field32(®s
[TX_PWR_CFG_6_IDX
],
3910 TX_PWR_CFG_6_MCS22_CH1
, txpower
);
3911 rt2x00_set_field32(®s
[TX_PWR_CFG_6_IDX
],
3912 TX_PWR_CFG_6_MCS22_CH2
, txpower
);
3915 txpower
= rt2x00_get_field16(eeprom
, EEPROM_TXPOWER_BYRATE_RATE2
);
3916 txpower
= rt2800_compensate_txpower(rt2x00dev
, 0, band
, power_level
,
3918 rt2x00_set_field32(®s
[TX_PWR_CFG_8_IDX
],
3919 TX_PWR_CFG_8_MCS23_CH0
, txpower
);
3920 rt2x00_set_field32(®s
[TX_PWR_CFG_8_IDX
],
3921 TX_PWR_CFG_8_MCS23_CH1
, txpower
);
3922 rt2x00_set_field32(®s
[TX_PWR_CFG_8_IDX
],
3923 TX_PWR_CFG_8_MCS23_CH2
, txpower
);
3925 /* read the next four txpower values */
3926 rt2800_eeprom_read_from_array(rt2x00dev
, EEPROM_TXPOWER_BYRATE
,
3927 offset
+ 6, &eeprom
);
3930 txpower
= rt2x00_get_field16(eeprom
, EEPROM_TXPOWER_BYRATE_RATE0
);
3931 txpower
= rt2800_compensate_txpower(rt2x00dev
, 0, band
, power_level
,
3933 rt2x00_set_field32(®s
[TX_PWR_CFG_3_IDX
],
3934 TX_PWR_CFG_3_STBC0_CH0
, txpower
);
3935 rt2x00_set_field32(®s
[TX_PWR_CFG_3_IDX
],
3936 TX_PWR_CFG_3_STBC0_CH1
, txpower
);
3937 rt2x00_set_field32(®s
[TX_PWR_CFG_3_EXT_IDX
],
3938 TX_PWR_CFG_3_EXT_STBC0_CH2
, txpower
);
3941 txpower
= rt2x00_get_field16(eeprom
, EEPROM_TXPOWER_BYRATE_RATE1
);
3942 txpower
= rt2800_compensate_txpower(rt2x00dev
, 0, band
, power_level
,
3944 rt2x00_set_field32(®s
[TX_PWR_CFG_3_IDX
],
3945 TX_PWR_CFG_3_STBC2_CH0
, txpower
);
3946 rt2x00_set_field32(®s
[TX_PWR_CFG_3_IDX
],
3947 TX_PWR_CFG_3_STBC2_CH1
, txpower
);
3948 rt2x00_set_field32(®s
[TX_PWR_CFG_3_EXT_IDX
],
3949 TX_PWR_CFG_3_EXT_STBC2_CH2
, txpower
);
3952 txpower
= rt2x00_get_field16(eeprom
, EEPROM_TXPOWER_BYRATE_RATE2
);
3953 txpower
= rt2800_compensate_txpower(rt2x00dev
, 0, band
, power_level
,
3955 rt2x00_set_field32(®s
[TX_PWR_CFG_4_IDX
], TX_PWR_CFG_RATE0
, txpower
);
3956 rt2x00_set_field32(®s
[TX_PWR_CFG_4_IDX
], TX_PWR_CFG_RATE1
, txpower
);
3957 rt2x00_set_field32(®s
[TX_PWR_CFG_4_EXT_IDX
], TX_PWR_CFG_RATE0
,
3961 txpower
= rt2x00_get_field16(eeprom
, EEPROM_TXPOWER_BYRATE_RATE3
);
3962 txpower
= rt2800_compensate_txpower(rt2x00dev
, 0, band
, power_level
,
3964 rt2x00_set_field32(®s
[TX_PWR_CFG_4_IDX
], TX_PWR_CFG_RATE2
, txpower
);
3965 rt2x00_set_field32(®s
[TX_PWR_CFG_4_IDX
], TX_PWR_CFG_RATE3
, txpower
);
3966 rt2x00_set_field32(®s
[TX_PWR_CFG_4_EXT_IDX
], TX_PWR_CFG_RATE2
,
3969 /* read the next four txpower values */
3970 rt2800_eeprom_read_from_array(rt2x00dev
, EEPROM_TXPOWER_BYRATE
,
3971 offset
+ 7, &eeprom
);
3974 txpower
= rt2x00_get_field16(eeprom
, EEPROM_TXPOWER_BYRATE_RATE0
);
3975 txpower
= rt2800_compensate_txpower(rt2x00dev
, 0, band
, power_level
,
3977 rt2x00_set_field32(®s
[TX_PWR_CFG_9_IDX
],
3978 TX_PWR_CFG_9_STBC7_CH0
, txpower
);
3979 rt2x00_set_field32(®s
[TX_PWR_CFG_9_IDX
],
3980 TX_PWR_CFG_9_STBC7_CH1
, txpower
);
3981 rt2x00_set_field32(®s
[TX_PWR_CFG_9_IDX
],
3982 TX_PWR_CFG_9_STBC7_CH2
, txpower
);
3984 rt2800_register_write(rt2x00dev
, TX_PWR_CFG_0
, regs
[TX_PWR_CFG_0_IDX
]);
3985 rt2800_register_write(rt2x00dev
, TX_PWR_CFG_1
, regs
[TX_PWR_CFG_1_IDX
]);
3986 rt2800_register_write(rt2x00dev
, TX_PWR_CFG_2
, regs
[TX_PWR_CFG_2_IDX
]);
3987 rt2800_register_write(rt2x00dev
, TX_PWR_CFG_3
, regs
[TX_PWR_CFG_3_IDX
]);
3988 rt2800_register_write(rt2x00dev
, TX_PWR_CFG_4
, regs
[TX_PWR_CFG_4_IDX
]);
3989 rt2800_register_write(rt2x00dev
, TX_PWR_CFG_5
, regs
[TX_PWR_CFG_5_IDX
]);
3990 rt2800_register_write(rt2x00dev
, TX_PWR_CFG_6
, regs
[TX_PWR_CFG_6_IDX
]);
3991 rt2800_register_write(rt2x00dev
, TX_PWR_CFG_7
, regs
[TX_PWR_CFG_7_IDX
]);
3992 rt2800_register_write(rt2x00dev
, TX_PWR_CFG_8
, regs
[TX_PWR_CFG_8_IDX
]);
3993 rt2800_register_write(rt2x00dev
, TX_PWR_CFG_9
, regs
[TX_PWR_CFG_9_IDX
]);
3995 rt2800_register_write(rt2x00dev
, TX_PWR_CFG_0_EXT
,
3996 regs
[TX_PWR_CFG_0_EXT_IDX
]);
3997 rt2800_register_write(rt2x00dev
, TX_PWR_CFG_1_EXT
,
3998 regs
[TX_PWR_CFG_1_EXT_IDX
]);
3999 rt2800_register_write(rt2x00dev
, TX_PWR_CFG_2_EXT
,
4000 regs
[TX_PWR_CFG_2_EXT_IDX
]);
4001 rt2800_register_write(rt2x00dev
, TX_PWR_CFG_3_EXT
,
4002 regs
[TX_PWR_CFG_3_EXT_IDX
]);
4003 rt2800_register_write(rt2x00dev
, TX_PWR_CFG_4_EXT
,
4004 regs
[TX_PWR_CFG_4_EXT_IDX
]);
4006 for (i
= 0; i
< TX_PWR_CFG_IDX_COUNT
; i
++)
4007 rt2x00_dbg(rt2x00dev
,
4008 "band:%cGHz, BW:%c0MHz, TX_PWR_CFG_%d%s = %08lx\n",
4009 (band
== IEEE80211_BAND_5GHZ
) ? '5' : '2',
4010 (test_bit(CONFIG_CHANNEL_HT40
, &rt2x00dev
->flags
)) ?
4012 (i
> TX_PWR_CFG_9_IDX
) ?
4013 (i
- TX_PWR_CFG_9_IDX
- 1) : i
,
4014 (i
> TX_PWR_CFG_9_IDX
) ? "_EXT" : "",
4015 (unsigned long) regs
[i
]);
4019 * We configure transmit power using MAC TX_PWR_CFG_{0,...,N} registers and
4020 * BBP R1 register. TX_PWR_CFG_X allow to configure per rate TX power values,
4021 * 4 bits for each rate (tune from 0 to 15 dBm). BBP_R1 controls transmit power
4022 * for all rates, but allow to set only 4 discrete values: -12, -6, 0 and 6 dBm.
4023 * Reference per rate transmit power values are located in the EEPROM at
4024 * EEPROM_TXPOWER_BYRATE offset. We adjust them and BBP R1 settings according to
4025 * current conditions (i.e. band, bandwidth, temperature, user settings).
4027 static void rt2800_config_txpower_rt28xx(struct rt2x00_dev
*rt2x00dev
,
4028 struct ieee80211_channel
*chan
,
4034 int i
, is_rate_b
, delta
, power_ctrl
;
4035 enum ieee80211_band band
= chan
->band
;
4038 * Calculate HT40 compensation. For 40MHz we need to add or subtract
4039 * value read from EEPROM (different for 2GHz and for 5GHz).
4041 delta
= rt2800_get_txpower_bw_comp(rt2x00dev
, band
);
4044 * Calculate temperature compensation. Depends on measurement of current
4045 * TSSI (Transmitter Signal Strength Indication) we know TX power (due
4046 * to temperature or maybe other factors) is smaller or bigger than
4047 * expected. We adjust it, based on TSSI reference and boundaries values
4048 * provided in EEPROM.
4050 delta
+= rt2800_get_gain_calibration_delta(rt2x00dev
);
4053 * Decrease power according to user settings, on devices with unknown
4054 * maximum tx power. For other devices we take user power_level into
4055 * consideration on rt2800_compensate_txpower().
4057 delta
+= rt2800_get_txpower_reg_delta(rt2x00dev
, power_level
,
4061 * BBP_R1 controls TX power for all rates, it allow to set the following
4062 * gains -12, -6, 0, +6 dBm by setting values 2, 1, 0, 3 respectively.
4064 * TODO: we do not use +6 dBm option to do not increase power beyond
4065 * regulatory limit, however this could be utilized for devices with
4066 * CAPABILITY_POWER_LIMIT.
4068 * TODO: add different temperature compensation code for RT3290 & RT5390
4069 * to allow to use BBP_R1 for those chips.
4071 if (!rt2x00_rt(rt2x00dev
, RT3290
) &&
4072 !rt2x00_rt(rt2x00dev
, RT5390
)) {
4073 rt2800_bbp_read(rt2x00dev
, 1, &r1
);
4077 } else if (delta
<= -6) {
4083 rt2x00_set_field8(&r1
, BBP1_TX_POWER_CTRL
, power_ctrl
);
4084 rt2800_bbp_write(rt2x00dev
, 1, r1
);
4087 offset
= TX_PWR_CFG_0
;
4089 for (i
= 0; i
< EEPROM_TXPOWER_BYRATE_SIZE
; i
+= 2) {
4090 /* just to be safe */
4091 if (offset
> TX_PWR_CFG_4
)
4094 rt2800_register_read(rt2x00dev
, offset
, ®
);
4096 /* read the next four txpower values */
4097 rt2800_eeprom_read_from_array(rt2x00dev
, EEPROM_TXPOWER_BYRATE
,
4100 is_rate_b
= i
? 0 : 1;
4102 * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
4103 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
4104 * TX_PWR_CFG_4: unknown
4106 txpower
= rt2x00_get_field16(eeprom
,
4107 EEPROM_TXPOWER_BYRATE_RATE0
);
4108 txpower
= rt2800_compensate_txpower(rt2x00dev
, is_rate_b
, band
,
4109 power_level
, txpower
, delta
);
4110 rt2x00_set_field32(®
, TX_PWR_CFG_RATE0
, txpower
);
4113 * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
4114 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
4115 * TX_PWR_CFG_4: unknown
4117 txpower
= rt2x00_get_field16(eeprom
,
4118 EEPROM_TXPOWER_BYRATE_RATE1
);
4119 txpower
= rt2800_compensate_txpower(rt2x00dev
, is_rate_b
, band
,
4120 power_level
, txpower
, delta
);
4121 rt2x00_set_field32(®
, TX_PWR_CFG_RATE1
, txpower
);
4124 * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
4125 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14,
4126 * TX_PWR_CFG_4: unknown
4128 txpower
= rt2x00_get_field16(eeprom
,
4129 EEPROM_TXPOWER_BYRATE_RATE2
);
4130 txpower
= rt2800_compensate_txpower(rt2x00dev
, is_rate_b
, band
,
4131 power_level
, txpower
, delta
);
4132 rt2x00_set_field32(®
, TX_PWR_CFG_RATE2
, txpower
);
4135 * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
4136 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15,
4137 * TX_PWR_CFG_4: unknown
4139 txpower
= rt2x00_get_field16(eeprom
,
4140 EEPROM_TXPOWER_BYRATE_RATE3
);
4141 txpower
= rt2800_compensate_txpower(rt2x00dev
, is_rate_b
, band
,
4142 power_level
, txpower
, delta
);
4143 rt2x00_set_field32(®
, TX_PWR_CFG_RATE3
, txpower
);
4145 /* read the next four txpower values */
4146 rt2800_eeprom_read_from_array(rt2x00dev
, EEPROM_TXPOWER_BYRATE
,
4151 * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
4152 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
4153 * TX_PWR_CFG_4: unknown
4155 txpower
= rt2x00_get_field16(eeprom
,
4156 EEPROM_TXPOWER_BYRATE_RATE0
);
4157 txpower
= rt2800_compensate_txpower(rt2x00dev
, is_rate_b
, band
,
4158 power_level
, txpower
, delta
);
4159 rt2x00_set_field32(®
, TX_PWR_CFG_RATE4
, txpower
);
4162 * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
4163 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
4164 * TX_PWR_CFG_4: unknown
4166 txpower
= rt2x00_get_field16(eeprom
,
4167 EEPROM_TXPOWER_BYRATE_RATE1
);
4168 txpower
= rt2800_compensate_txpower(rt2x00dev
, is_rate_b
, band
,
4169 power_level
, txpower
, delta
);
4170 rt2x00_set_field32(®
, TX_PWR_CFG_RATE5
, txpower
);
4173 * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
4174 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
4175 * TX_PWR_CFG_4: unknown
4177 txpower
= rt2x00_get_field16(eeprom
,
4178 EEPROM_TXPOWER_BYRATE_RATE2
);
4179 txpower
= rt2800_compensate_txpower(rt2x00dev
, is_rate_b
, band
,
4180 power_level
, txpower
, delta
);
4181 rt2x00_set_field32(®
, TX_PWR_CFG_RATE6
, txpower
);
4184 * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
4185 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
4186 * TX_PWR_CFG_4: unknown
4188 txpower
= rt2x00_get_field16(eeprom
,
4189 EEPROM_TXPOWER_BYRATE_RATE3
);
4190 txpower
= rt2800_compensate_txpower(rt2x00dev
, is_rate_b
, band
,
4191 power_level
, txpower
, delta
);
4192 rt2x00_set_field32(®
, TX_PWR_CFG_RATE7
, txpower
);
4194 rt2800_register_write(rt2x00dev
, offset
, reg
);
4196 /* next TX_PWR_CFG register */
4201 static void rt2800_config_txpower(struct rt2x00_dev
*rt2x00dev
,
4202 struct ieee80211_channel
*chan
,
4205 if (rt2x00_rt(rt2x00dev
, RT3593
))
4206 rt2800_config_txpower_rt3593(rt2x00dev
, chan
, power_level
);
4208 rt2800_config_txpower_rt28xx(rt2x00dev
, chan
, power_level
);
4211 void rt2800_gain_calibration(struct rt2x00_dev
*rt2x00dev
)
4213 rt2800_config_txpower(rt2x00dev
, rt2x00dev
->hw
->conf
.chandef
.chan
,
4214 rt2x00dev
->tx_power
);
4216 EXPORT_SYMBOL_GPL(rt2800_gain_calibration
);
4218 void rt2800_vco_calibration(struct rt2x00_dev
*rt2x00dev
)
4224 * A voltage-controlled oscillator(VCO) is an electronic oscillator
4225 * designed to be controlled in oscillation frequency by a voltage
4226 * input. Maybe the temperature will affect the frequency of
4227 * oscillation to be shifted. The VCO calibration will be called
4228 * periodically to adjust the frequency to be precision.
4231 rt2800_register_read(rt2x00dev
, TX_PIN_CFG
, &tx_pin
);
4232 tx_pin
&= TX_PIN_CFG_PA_PE_DISABLE
;
4233 rt2800_register_write(rt2x00dev
, TX_PIN_CFG
, tx_pin
);
4235 switch (rt2x00dev
->chip
.rf
) {
4242 rt2800_rfcsr_read(rt2x00dev
, 7, &rfcsr
);
4243 rt2x00_set_field8(&rfcsr
, RFCSR7_RF_TUNING
, 1);
4244 rt2800_rfcsr_write(rt2x00dev
, 7, rfcsr
);
4253 rt2800_rfcsr_read(rt2x00dev
, 3, &rfcsr
);
4254 rt2x00_set_field8(&rfcsr
, RFCSR3_VCOCAL_EN
, 1);
4255 rt2800_rfcsr_write(rt2x00dev
, 3, rfcsr
);
4263 rt2800_register_read(rt2x00dev
, TX_PIN_CFG
, &tx_pin
);
4264 if (rt2x00dev
->rf_channel
<= 14) {
4265 switch (rt2x00dev
->default_ant
.tx_chain_num
) {
4267 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_G2_EN
, 1);
4270 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_G1_EN
, 1);
4274 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_G0_EN
, 1);
4278 switch (rt2x00dev
->default_ant
.tx_chain_num
) {
4280 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_A2_EN
, 1);
4283 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_A1_EN
, 1);
4287 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_A0_EN
, 1);
4291 rt2800_register_write(rt2x00dev
, TX_PIN_CFG
, tx_pin
);
4294 EXPORT_SYMBOL_GPL(rt2800_vco_calibration
);
4296 static void rt2800_config_retry_limit(struct rt2x00_dev
*rt2x00dev
,
4297 struct rt2x00lib_conf
*libconf
)
4301 rt2800_register_read(rt2x00dev
, TX_RTY_CFG
, ®
);
4302 rt2x00_set_field32(®
, TX_RTY_CFG_SHORT_RTY_LIMIT
,
4303 libconf
->conf
->short_frame_max_tx_count
);
4304 rt2x00_set_field32(®
, TX_RTY_CFG_LONG_RTY_LIMIT
,
4305 libconf
->conf
->long_frame_max_tx_count
);
4306 rt2800_register_write(rt2x00dev
, TX_RTY_CFG
, reg
);
4309 static void rt2800_config_ps(struct rt2x00_dev
*rt2x00dev
,
4310 struct rt2x00lib_conf
*libconf
)
4312 enum dev_state state
=
4313 (libconf
->conf
->flags
& IEEE80211_CONF_PS
) ?
4314 STATE_SLEEP
: STATE_AWAKE
;
4317 if (state
== STATE_SLEEP
) {
4318 rt2800_register_write(rt2x00dev
, AUTOWAKEUP_CFG
, 0);
4320 rt2800_register_read(rt2x00dev
, AUTOWAKEUP_CFG
, ®
);
4321 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_AUTO_LEAD_TIME
, 5);
4322 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE
,
4323 libconf
->conf
->listen_interval
- 1);
4324 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_AUTOWAKE
, 1);
4325 rt2800_register_write(rt2x00dev
, AUTOWAKEUP_CFG
, reg
);
4327 rt2x00dev
->ops
->lib
->set_device_state(rt2x00dev
, state
);
4329 rt2800_register_read(rt2x00dev
, AUTOWAKEUP_CFG
, ®
);
4330 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_AUTO_LEAD_TIME
, 0);
4331 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE
, 0);
4332 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_AUTOWAKE
, 0);
4333 rt2800_register_write(rt2x00dev
, AUTOWAKEUP_CFG
, reg
);
4335 rt2x00dev
->ops
->lib
->set_device_state(rt2x00dev
, state
);
4339 void rt2800_config(struct rt2x00_dev
*rt2x00dev
,
4340 struct rt2x00lib_conf
*libconf
,
4341 const unsigned int flags
)
4343 /* Always recalculate LNA gain before changing configuration */
4344 rt2800_config_lna_gain(rt2x00dev
, libconf
);
4346 if (flags
& IEEE80211_CONF_CHANGE_CHANNEL
) {
4347 rt2800_config_channel(rt2x00dev
, libconf
->conf
,
4348 &libconf
->rf
, &libconf
->channel
);
4349 rt2800_config_txpower(rt2x00dev
, libconf
->conf
->chandef
.chan
,
4350 libconf
->conf
->power_level
);
4352 if (flags
& IEEE80211_CONF_CHANGE_POWER
)
4353 rt2800_config_txpower(rt2x00dev
, libconf
->conf
->chandef
.chan
,
4354 libconf
->conf
->power_level
);
4355 if (flags
& IEEE80211_CONF_CHANGE_RETRY_LIMITS
)
4356 rt2800_config_retry_limit(rt2x00dev
, libconf
);
4357 if (flags
& IEEE80211_CONF_CHANGE_PS
)
4358 rt2800_config_ps(rt2x00dev
, libconf
);
4360 EXPORT_SYMBOL_GPL(rt2800_config
);
4365 void rt2800_link_stats(struct rt2x00_dev
*rt2x00dev
, struct link_qual
*qual
)
4370 * Update FCS error count from register.
4372 rt2800_register_read(rt2x00dev
, RX_STA_CNT0
, ®
);
4373 qual
->rx_failed
= rt2x00_get_field32(reg
, RX_STA_CNT0_CRC_ERR
);
4375 EXPORT_SYMBOL_GPL(rt2800_link_stats
);
4377 static u8
rt2800_get_default_vgc(struct rt2x00_dev
*rt2x00dev
)
4381 if (rt2x00dev
->curr_band
== IEEE80211_BAND_2GHZ
) {
4382 if (rt2x00_rt(rt2x00dev
, RT3070
) ||
4383 rt2x00_rt(rt2x00dev
, RT3071
) ||
4384 rt2x00_rt(rt2x00dev
, RT3090
) ||
4385 rt2x00_rt(rt2x00dev
, RT3290
) ||
4386 rt2x00_rt(rt2x00dev
, RT3390
) ||
4387 rt2x00_rt(rt2x00dev
, RT3572
) ||
4388 rt2x00_rt(rt2x00dev
, RT5390
) ||
4389 rt2x00_rt(rt2x00dev
, RT5392
) ||
4390 rt2x00_rt(rt2x00dev
, RT5592
))
4391 vgc
= 0x1c + (2 * rt2x00dev
->lna_gain
);
4393 vgc
= 0x2e + rt2x00dev
->lna_gain
;
4394 } else { /* 5GHZ band */
4395 if (rt2x00_rt(rt2x00dev
, RT3572
))
4396 vgc
= 0x22 + (rt2x00dev
->lna_gain
* 5) / 3;
4397 else if (rt2x00_rt(rt2x00dev
, RT5592
))
4398 vgc
= 0x24 + (2 * rt2x00dev
->lna_gain
);
4400 if (!test_bit(CONFIG_CHANNEL_HT40
, &rt2x00dev
->flags
))
4401 vgc
= 0x32 + (rt2x00dev
->lna_gain
* 5) / 3;
4403 vgc
= 0x3a + (rt2x00dev
->lna_gain
* 5) / 3;
4410 static inline void rt2800_set_vgc(struct rt2x00_dev
*rt2x00dev
,
4411 struct link_qual
*qual
, u8 vgc_level
)
4413 if (qual
->vgc_level
!= vgc_level
) {
4414 if (rt2x00_rt(rt2x00dev
, RT5592
)) {
4415 rt2800_bbp_write(rt2x00dev
, 83, qual
->rssi
> -65 ? 0x4a : 0x7a);
4416 rt2800_bbp_write_with_rx_chain(rt2x00dev
, 66, vgc_level
);
4418 rt2800_bbp_write(rt2x00dev
, 66, vgc_level
);
4419 qual
->vgc_level
= vgc_level
;
4420 qual
->vgc_level_reg
= vgc_level
;
4424 void rt2800_reset_tuner(struct rt2x00_dev
*rt2x00dev
, struct link_qual
*qual
)
4426 rt2800_set_vgc(rt2x00dev
, qual
, rt2800_get_default_vgc(rt2x00dev
));
4428 EXPORT_SYMBOL_GPL(rt2800_reset_tuner
);
4430 void rt2800_link_tuner(struct rt2x00_dev
*rt2x00dev
, struct link_qual
*qual
,
4435 if (rt2x00_rt_rev(rt2x00dev
, RT2860
, REV_RT2860C
))
4438 * When RSSI is better then -80 increase VGC level with 0x10, except
4442 vgc
= rt2800_get_default_vgc(rt2x00dev
);
4444 if (rt2x00_rt(rt2x00dev
, RT5592
) && qual
->rssi
> -65)
4446 else if (qual
->rssi
> -80)
4449 rt2800_set_vgc(rt2x00dev
, qual
, vgc
);
4451 EXPORT_SYMBOL_GPL(rt2800_link_tuner
);
4454 * Initialization functions.
4456 static int rt2800_init_registers(struct rt2x00_dev
*rt2x00dev
)
4463 rt2800_disable_wpdma(rt2x00dev
);
4465 ret
= rt2800_drv_init_registers(rt2x00dev
);
4469 rt2800_register_read(rt2x00dev
, BCN_OFFSET0
, ®
);
4470 rt2x00_set_field32(®
, BCN_OFFSET0_BCN0
, 0xe0); /* 0x3800 */
4471 rt2x00_set_field32(®
, BCN_OFFSET0_BCN1
, 0xe8); /* 0x3a00 */
4472 rt2x00_set_field32(®
, BCN_OFFSET0_BCN2
, 0xf0); /* 0x3c00 */
4473 rt2x00_set_field32(®
, BCN_OFFSET0_BCN3
, 0xf8); /* 0x3e00 */
4474 rt2800_register_write(rt2x00dev
, BCN_OFFSET0
, reg
);
4476 rt2800_register_read(rt2x00dev
, BCN_OFFSET1
, ®
);
4477 rt2x00_set_field32(®
, BCN_OFFSET1_BCN4
, 0xc8); /* 0x3200 */
4478 rt2x00_set_field32(®
, BCN_OFFSET1_BCN5
, 0xd0); /* 0x3400 */
4479 rt2x00_set_field32(®
, BCN_OFFSET1_BCN6
, 0x77); /* 0x1dc0 */
4480 rt2x00_set_field32(®
, BCN_OFFSET1_BCN7
, 0x6f); /* 0x1bc0 */
4481 rt2800_register_write(rt2x00dev
, BCN_OFFSET1
, reg
);
4483 rt2800_register_write(rt2x00dev
, LEGACY_BASIC_RATE
, 0x0000013f);
4484 rt2800_register_write(rt2x00dev
, HT_BASIC_RATE
, 0x00008003);
4486 rt2800_register_write(rt2x00dev
, MAC_SYS_CTRL
, 0x00000000);
4488 rt2800_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
4489 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_INTERVAL
, 1600);
4490 rt2x00_set_field32(®
, BCN_TIME_CFG_TSF_TICKING
, 0);
4491 rt2x00_set_field32(®
, BCN_TIME_CFG_TSF_SYNC
, 0);
4492 rt2x00_set_field32(®
, BCN_TIME_CFG_TBTT_ENABLE
, 0);
4493 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_GEN
, 0);
4494 rt2x00_set_field32(®
, BCN_TIME_CFG_TX_TIME_COMPENSATE
, 0);
4495 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
4497 rt2800_config_filter(rt2x00dev
, FIF_ALLMULTI
);
4499 rt2800_register_read(rt2x00dev
, BKOFF_SLOT_CFG
, ®
);
4500 rt2x00_set_field32(®
, BKOFF_SLOT_CFG_SLOT_TIME
, 9);
4501 rt2x00_set_field32(®
, BKOFF_SLOT_CFG_CC_DELAY_TIME
, 2);
4502 rt2800_register_write(rt2x00dev
, BKOFF_SLOT_CFG
, reg
);
4504 if (rt2x00_rt(rt2x00dev
, RT3290
)) {
4505 rt2800_register_read(rt2x00dev
, WLAN_FUN_CTRL
, ®
);
4506 if (rt2x00_get_field32(reg
, WLAN_EN
) == 1) {
4507 rt2x00_set_field32(®
, PCIE_APP0_CLK_REQ
, 1);
4508 rt2800_register_write(rt2x00dev
, WLAN_FUN_CTRL
, reg
);
4511 rt2800_register_read(rt2x00dev
, CMB_CTRL
, ®
);
4512 if (!(rt2x00_get_field32(reg
, LDO0_EN
) == 1)) {
4513 rt2x00_set_field32(®
, LDO0_EN
, 1);
4514 rt2x00_set_field32(®
, LDO_BGSEL
, 3);
4515 rt2800_register_write(rt2x00dev
, CMB_CTRL
, reg
);
4518 rt2800_register_read(rt2x00dev
, OSC_CTRL
, ®
);
4519 rt2x00_set_field32(®
, OSC_ROSC_EN
, 1);
4520 rt2x00_set_field32(®
, OSC_CAL_REQ
, 1);
4521 rt2x00_set_field32(®
, OSC_REF_CYCLE
, 0x27);
4522 rt2800_register_write(rt2x00dev
, OSC_CTRL
, reg
);
4524 rt2800_register_read(rt2x00dev
, COEX_CFG0
, ®
);
4525 rt2x00_set_field32(®
, COEX_CFG_ANT
, 0x5e);
4526 rt2800_register_write(rt2x00dev
, COEX_CFG0
, reg
);
4528 rt2800_register_read(rt2x00dev
, COEX_CFG2
, ®
);
4529 rt2x00_set_field32(®
, BT_COEX_CFG1
, 0x00);
4530 rt2x00_set_field32(®
, BT_COEX_CFG0
, 0x17);
4531 rt2x00_set_field32(®
, WL_COEX_CFG1
, 0x93);
4532 rt2x00_set_field32(®
, WL_COEX_CFG0
, 0x7f);
4533 rt2800_register_write(rt2x00dev
, COEX_CFG2
, reg
);
4535 rt2800_register_read(rt2x00dev
, PLL_CTRL
, ®
);
4536 rt2x00_set_field32(®
, PLL_CONTROL
, 1);
4537 rt2800_register_write(rt2x00dev
, PLL_CTRL
, reg
);
4540 if (rt2x00_rt(rt2x00dev
, RT3071
) ||
4541 rt2x00_rt(rt2x00dev
, RT3090
) ||
4542 rt2x00_rt(rt2x00dev
, RT3290
) ||
4543 rt2x00_rt(rt2x00dev
, RT3390
)) {
4545 if (rt2x00_rt(rt2x00dev
, RT3290
))
4546 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
,
4549 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
,
4552 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00000000);
4553 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3071
, REV_RT3071E
) ||
4554 rt2x00_rt_rev_lt(rt2x00dev
, RT3090
, REV_RT3090E
) ||
4555 rt2x00_rt_rev_lt(rt2x00dev
, RT3390
, REV_RT3390E
)) {
4556 rt2800_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF1
,
4558 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF1_DAC_TEST
))
4559 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
,
4562 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
,
4565 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
, 0x00000000);
4567 } else if (rt2x00_rt(rt2x00dev
, RT3070
)) {
4568 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000400);
4570 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070F
)) {
4571 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00000000);
4572 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
, 0x0000002c);
4574 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00080606);
4575 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
, 0x00000000);
4577 } else if (rt2800_is_305x_soc(rt2x00dev
)) {
4578 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000400);
4579 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00000000);
4580 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
, 0x00000030);
4581 } else if (rt2x00_rt(rt2x00dev
, RT3352
)) {
4582 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000402);
4583 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00080606);
4584 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
, 0x00000000);
4585 } else if (rt2x00_rt(rt2x00dev
, RT3572
)) {
4586 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000400);
4587 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00080606);
4588 } else if (rt2x00_rt(rt2x00dev
, RT3593
)) {
4589 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000402);
4590 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00000000);
4591 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3593
, REV_RT3593E
)) {
4592 rt2800_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF1
,
4594 if (rt2x00_get_field16(eeprom
,
4595 EEPROM_NIC_CONF1_DAC_TEST
))
4596 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
,
4599 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
,
4602 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
,
4605 } else if (rt2x00_rt(rt2x00dev
, RT5390
) ||
4606 rt2x00_rt(rt2x00dev
, RT5392
) ||
4607 rt2x00_rt(rt2x00dev
, RT5592
)) {
4608 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000404);
4609 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00080606);
4610 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
, 0x00000000);
4612 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000000);
4613 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00080606);
4616 rt2800_register_read(rt2x00dev
, TX_LINK_CFG
, ®
);
4617 rt2x00_set_field32(®
, TX_LINK_CFG_REMOTE_MFB_LIFETIME
, 32);
4618 rt2x00_set_field32(®
, TX_LINK_CFG_MFB_ENABLE
, 0);
4619 rt2x00_set_field32(®
, TX_LINK_CFG_REMOTE_UMFS_ENABLE
, 0);
4620 rt2x00_set_field32(®
, TX_LINK_CFG_TX_MRQ_EN
, 0);
4621 rt2x00_set_field32(®
, TX_LINK_CFG_TX_RDG_EN
, 0);
4622 rt2x00_set_field32(®
, TX_LINK_CFG_TX_CF_ACK_EN
, 1);
4623 rt2x00_set_field32(®
, TX_LINK_CFG_REMOTE_MFB
, 0);
4624 rt2x00_set_field32(®
, TX_LINK_CFG_REMOTE_MFS
, 0);
4625 rt2800_register_write(rt2x00dev
, TX_LINK_CFG
, reg
);
4627 rt2800_register_read(rt2x00dev
, TX_TIMEOUT_CFG
, ®
);
4628 rt2x00_set_field32(®
, TX_TIMEOUT_CFG_MPDU_LIFETIME
, 9);
4629 rt2x00_set_field32(®
, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT
, 32);
4630 rt2x00_set_field32(®
, TX_TIMEOUT_CFG_TX_OP_TIMEOUT
, 10);
4631 rt2800_register_write(rt2x00dev
, TX_TIMEOUT_CFG
, reg
);
4633 rt2800_register_read(rt2x00dev
, MAX_LEN_CFG
, ®
);
4634 rt2x00_set_field32(®
, MAX_LEN_CFG_MAX_MPDU
, AGGREGATION_SIZE
);
4635 if (rt2x00_rt_rev_gte(rt2x00dev
, RT2872
, REV_RT2872E
) ||
4636 rt2x00_rt(rt2x00dev
, RT2883
) ||
4637 rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070E
))
4638 rt2x00_set_field32(®
, MAX_LEN_CFG_MAX_PSDU
, 2);
4640 rt2x00_set_field32(®
, MAX_LEN_CFG_MAX_PSDU
, 1);
4641 rt2x00_set_field32(®
, MAX_LEN_CFG_MIN_PSDU
, 0);
4642 rt2x00_set_field32(®
, MAX_LEN_CFG_MIN_MPDU
, 0);
4643 rt2800_register_write(rt2x00dev
, MAX_LEN_CFG
, reg
);
4645 rt2800_register_read(rt2x00dev
, LED_CFG
, ®
);
4646 rt2x00_set_field32(®
, LED_CFG_ON_PERIOD
, 70);
4647 rt2x00_set_field32(®
, LED_CFG_OFF_PERIOD
, 30);
4648 rt2x00_set_field32(®
, LED_CFG_SLOW_BLINK_PERIOD
, 3);
4649 rt2x00_set_field32(®
, LED_CFG_R_LED_MODE
, 3);
4650 rt2x00_set_field32(®
, LED_CFG_G_LED_MODE
, 3);
4651 rt2x00_set_field32(®
, LED_CFG_Y_LED_MODE
, 3);
4652 rt2x00_set_field32(®
, LED_CFG_LED_POLAR
, 1);
4653 rt2800_register_write(rt2x00dev
, LED_CFG
, reg
);
4655 rt2800_register_write(rt2x00dev
, PBF_MAX_PCNT
, 0x1f3fbf9f);
4657 rt2800_register_read(rt2x00dev
, TX_RTY_CFG
, ®
);
4658 rt2x00_set_field32(®
, TX_RTY_CFG_SHORT_RTY_LIMIT
, 15);
4659 rt2x00_set_field32(®
, TX_RTY_CFG_LONG_RTY_LIMIT
, 31);
4660 rt2x00_set_field32(®
, TX_RTY_CFG_LONG_RTY_THRE
, 2000);
4661 rt2x00_set_field32(®
, TX_RTY_CFG_NON_AGG_RTY_MODE
, 0);
4662 rt2x00_set_field32(®
, TX_RTY_CFG_AGG_RTY_MODE
, 0);
4663 rt2x00_set_field32(®
, TX_RTY_CFG_TX_AUTO_FB_ENABLE
, 1);
4664 rt2800_register_write(rt2x00dev
, TX_RTY_CFG
, reg
);
4666 rt2800_register_read(rt2x00dev
, AUTO_RSP_CFG
, ®
);
4667 rt2x00_set_field32(®
, AUTO_RSP_CFG_AUTORESPONDER
, 1);
4668 rt2x00_set_field32(®
, AUTO_RSP_CFG_BAC_ACK_POLICY
, 1);
4669 rt2x00_set_field32(®
, AUTO_RSP_CFG_CTS_40_MMODE
, 0);
4670 rt2x00_set_field32(®
, AUTO_RSP_CFG_CTS_40_MREF
, 0);
4671 rt2x00_set_field32(®
, AUTO_RSP_CFG_AR_PREAMBLE
, 1);
4672 rt2x00_set_field32(®
, AUTO_RSP_CFG_DUAL_CTS_EN
, 0);
4673 rt2x00_set_field32(®
, AUTO_RSP_CFG_ACK_CTS_PSM_BIT
, 0);
4674 rt2800_register_write(rt2x00dev
, AUTO_RSP_CFG
, reg
);
4676 rt2800_register_read(rt2x00dev
, CCK_PROT_CFG
, ®
);
4677 rt2x00_set_field32(®
, CCK_PROT_CFG_PROTECT_RATE
, 3);
4678 rt2x00_set_field32(®
, CCK_PROT_CFG_PROTECT_CTRL
, 0);
4679 rt2x00_set_field32(®
, CCK_PROT_CFG_PROTECT_NAV_SHORT
, 1);
4680 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
4681 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
4682 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
4683 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_MM40
, 0);
4684 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
4685 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_GF40
, 0);
4686 rt2x00_set_field32(®
, CCK_PROT_CFG_RTS_TH_EN
, 1);
4687 rt2800_register_write(rt2x00dev
, CCK_PROT_CFG
, reg
);
4689 rt2800_register_read(rt2x00dev
, OFDM_PROT_CFG
, ®
);
4690 rt2x00_set_field32(®
, OFDM_PROT_CFG_PROTECT_RATE
, 3);
4691 rt2x00_set_field32(®
, OFDM_PROT_CFG_PROTECT_CTRL
, 0);
4692 rt2x00_set_field32(®
, OFDM_PROT_CFG_PROTECT_NAV_SHORT
, 1);
4693 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
4694 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
4695 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
4696 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_MM40
, 0);
4697 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
4698 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_GF40
, 0);
4699 rt2x00_set_field32(®
, OFDM_PROT_CFG_RTS_TH_EN
, 1);
4700 rt2800_register_write(rt2x00dev
, OFDM_PROT_CFG
, reg
);
4702 rt2800_register_read(rt2x00dev
, MM20_PROT_CFG
, ®
);
4703 rt2x00_set_field32(®
, MM20_PROT_CFG_PROTECT_RATE
, 0x4004);
4704 rt2x00_set_field32(®
, MM20_PROT_CFG_PROTECT_CTRL
, 0);
4705 rt2x00_set_field32(®
, MM20_PROT_CFG_PROTECT_NAV_SHORT
, 1);
4706 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
4707 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
4708 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
4709 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_MM40
, 0);
4710 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
4711 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_GF40
, 0);
4712 rt2x00_set_field32(®
, MM20_PROT_CFG_RTS_TH_EN
, 0);
4713 rt2800_register_write(rt2x00dev
, MM20_PROT_CFG
, reg
);
4715 rt2800_register_read(rt2x00dev
, MM40_PROT_CFG
, ®
);
4716 rt2x00_set_field32(®
, MM40_PROT_CFG_PROTECT_RATE
, 0x4084);
4717 rt2x00_set_field32(®
, MM40_PROT_CFG_PROTECT_CTRL
, 0);
4718 rt2x00_set_field32(®
, MM40_PROT_CFG_PROTECT_NAV_SHORT
, 1);
4719 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
4720 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
4721 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
4722 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_MM40
, 1);
4723 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
4724 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_GF40
, 1);
4725 rt2x00_set_field32(®
, MM40_PROT_CFG_RTS_TH_EN
, 0);
4726 rt2800_register_write(rt2x00dev
, MM40_PROT_CFG
, reg
);
4728 rt2800_register_read(rt2x00dev
, GF20_PROT_CFG
, ®
);
4729 rt2x00_set_field32(®
, GF20_PROT_CFG_PROTECT_RATE
, 0x4004);
4730 rt2x00_set_field32(®
, GF20_PROT_CFG_PROTECT_CTRL
, 0);
4731 rt2x00_set_field32(®
, GF20_PROT_CFG_PROTECT_NAV_SHORT
, 1);
4732 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
4733 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
4734 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
4735 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_MM40
, 0);
4736 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
4737 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_GF40
, 0);
4738 rt2x00_set_field32(®
, GF20_PROT_CFG_RTS_TH_EN
, 0);
4739 rt2800_register_write(rt2x00dev
, GF20_PROT_CFG
, reg
);
4741 rt2800_register_read(rt2x00dev
, GF40_PROT_CFG
, ®
);
4742 rt2x00_set_field32(®
, GF40_PROT_CFG_PROTECT_RATE
, 0x4084);
4743 rt2x00_set_field32(®
, GF40_PROT_CFG_PROTECT_CTRL
, 0);
4744 rt2x00_set_field32(®
, GF40_PROT_CFG_PROTECT_NAV_SHORT
, 1);
4745 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
4746 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
4747 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
4748 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_MM40
, 1);
4749 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
4750 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_GF40
, 1);
4751 rt2x00_set_field32(®
, GF40_PROT_CFG_RTS_TH_EN
, 0);
4752 rt2800_register_write(rt2x00dev
, GF40_PROT_CFG
, reg
);
4754 if (rt2x00_is_usb(rt2x00dev
)) {
4755 rt2800_register_write(rt2x00dev
, PBF_CFG
, 0xf40006);
4757 rt2800_register_read(rt2x00dev
, WPDMA_GLO_CFG
, ®
);
4758 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_TX_DMA
, 0);
4759 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_DMA_BUSY
, 0);
4760 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_RX_DMA
, 0);
4761 rt2x00_set_field32(®
, WPDMA_GLO_CFG_RX_DMA_BUSY
, 0);
4762 rt2x00_set_field32(®
, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE
, 3);
4763 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_WRITEBACK_DONE
, 0);
4764 rt2x00_set_field32(®
, WPDMA_GLO_CFG_BIG_ENDIAN
, 0);
4765 rt2x00_set_field32(®
, WPDMA_GLO_CFG_RX_HDR_SCATTER
, 0);
4766 rt2x00_set_field32(®
, WPDMA_GLO_CFG_HDR_SEG_LEN
, 0);
4767 rt2800_register_write(rt2x00dev
, WPDMA_GLO_CFG
, reg
);
4771 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
4772 * although it is reserved.
4774 rt2800_register_read(rt2x00dev
, TXOP_CTRL_CFG
, ®
);
4775 rt2x00_set_field32(®
, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN
, 1);
4776 rt2x00_set_field32(®
, TXOP_CTRL_CFG_AC_TRUN_EN
, 1);
4777 rt2x00_set_field32(®
, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN
, 1);
4778 rt2x00_set_field32(®
, TXOP_CTRL_CFG_USER_MODE_TRUN_EN
, 1);
4779 rt2x00_set_field32(®
, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN
, 1);
4780 rt2x00_set_field32(®
, TXOP_CTRL_CFG_RESERVED_TRUN_EN
, 1);
4781 rt2x00_set_field32(®
, TXOP_CTRL_CFG_LSIG_TXOP_EN
, 0);
4782 rt2x00_set_field32(®
, TXOP_CTRL_CFG_EXT_CCA_EN
, 0);
4783 rt2x00_set_field32(®
, TXOP_CTRL_CFG_EXT_CCA_DLY
, 88);
4784 rt2x00_set_field32(®
, TXOP_CTRL_CFG_EXT_CWMIN
, 0);
4785 rt2800_register_write(rt2x00dev
, TXOP_CTRL_CFG
, reg
);
4787 reg
= rt2x00_rt(rt2x00dev
, RT5592
) ? 0x00000082 : 0x00000002;
4788 rt2800_register_write(rt2x00dev
, TXOP_HLDR_ET
, reg
);
4790 rt2800_register_read(rt2x00dev
, TX_RTS_CFG
, ®
);
4791 rt2x00_set_field32(®
, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT
, 32);
4792 rt2x00_set_field32(®
, TX_RTS_CFG_RTS_THRES
,
4793 IEEE80211_MAX_RTS_THRESHOLD
);
4794 rt2x00_set_field32(®
, TX_RTS_CFG_RTS_FBK_EN
, 0);
4795 rt2800_register_write(rt2x00dev
, TX_RTS_CFG
, reg
);
4797 rt2800_register_write(rt2x00dev
, EXP_ACK_TIME
, 0x002400ca);
4800 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
4801 * time should be set to 16. However, the original Ralink driver uses
4802 * 16 for both and indeed using a value of 10 for CCK SIFS results in
4803 * connection problems with 11g + CTS protection. Hence, use the same
4804 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
4806 rt2800_register_read(rt2x00dev
, XIFS_TIME_CFG
, ®
);
4807 rt2x00_set_field32(®
, XIFS_TIME_CFG_CCKM_SIFS_TIME
, 16);
4808 rt2x00_set_field32(®
, XIFS_TIME_CFG_OFDM_SIFS_TIME
, 16);
4809 rt2x00_set_field32(®
, XIFS_TIME_CFG_OFDM_XIFS_TIME
, 4);
4810 rt2x00_set_field32(®
, XIFS_TIME_CFG_EIFS
, 314);
4811 rt2x00_set_field32(®
, XIFS_TIME_CFG_BB_RXEND_ENABLE
, 1);
4812 rt2800_register_write(rt2x00dev
, XIFS_TIME_CFG
, reg
);
4814 rt2800_register_write(rt2x00dev
, PWR_PIN_CFG
, 0x00000003);
4817 * ASIC will keep garbage value after boot, clear encryption keys.
4819 for (i
= 0; i
< 4; i
++)
4820 rt2800_register_write(rt2x00dev
,
4821 SHARED_KEY_MODE_ENTRY(i
), 0);
4823 for (i
= 0; i
< 256; i
++) {
4824 rt2800_config_wcid(rt2x00dev
, NULL
, i
);
4825 rt2800_delete_wcid_attr(rt2x00dev
, i
);
4826 rt2800_register_write(rt2x00dev
, MAC_IVEIV_ENTRY(i
), 0);
4832 for (i
= 0; i
< 8; i
++)
4833 rt2800_clear_beacon_register(rt2x00dev
, i
);
4835 if (rt2x00_is_usb(rt2x00dev
)) {
4836 rt2800_register_read(rt2x00dev
, US_CYC_CNT
, ®
);
4837 rt2x00_set_field32(®
, US_CYC_CNT_CLOCK_CYCLE
, 30);
4838 rt2800_register_write(rt2x00dev
, US_CYC_CNT
, reg
);
4839 } else if (rt2x00_is_pcie(rt2x00dev
)) {
4840 rt2800_register_read(rt2x00dev
, US_CYC_CNT
, ®
);
4841 rt2x00_set_field32(®
, US_CYC_CNT_CLOCK_CYCLE
, 125);
4842 rt2800_register_write(rt2x00dev
, US_CYC_CNT
, reg
);
4845 rt2800_register_read(rt2x00dev
, HT_FBK_CFG0
, ®
);
4846 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS0FBK
, 0);
4847 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS1FBK
, 0);
4848 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS2FBK
, 1);
4849 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS3FBK
, 2);
4850 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS4FBK
, 3);
4851 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS5FBK
, 4);
4852 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS6FBK
, 5);
4853 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS7FBK
, 6);
4854 rt2800_register_write(rt2x00dev
, HT_FBK_CFG0
, reg
);
4856 rt2800_register_read(rt2x00dev
, HT_FBK_CFG1
, ®
);
4857 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS8FBK
, 8);
4858 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS9FBK
, 8);
4859 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS10FBK
, 9);
4860 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS11FBK
, 10);
4861 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS12FBK
, 11);
4862 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS13FBK
, 12);
4863 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS14FBK
, 13);
4864 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS15FBK
, 14);
4865 rt2800_register_write(rt2x00dev
, HT_FBK_CFG1
, reg
);
4867 rt2800_register_read(rt2x00dev
, LG_FBK_CFG0
, ®
);
4868 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS0FBK
, 8);
4869 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS1FBK
, 8);
4870 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS2FBK
, 9);
4871 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS3FBK
, 10);
4872 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS4FBK
, 11);
4873 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS5FBK
, 12);
4874 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS6FBK
, 13);
4875 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS7FBK
, 14);
4876 rt2800_register_write(rt2x00dev
, LG_FBK_CFG0
, reg
);
4878 rt2800_register_read(rt2x00dev
, LG_FBK_CFG1
, ®
);
4879 rt2x00_set_field32(®
, LG_FBK_CFG0_CCKMCS0FBK
, 0);
4880 rt2x00_set_field32(®
, LG_FBK_CFG0_CCKMCS1FBK
, 0);
4881 rt2x00_set_field32(®
, LG_FBK_CFG0_CCKMCS2FBK
, 1);
4882 rt2x00_set_field32(®
, LG_FBK_CFG0_CCKMCS3FBK
, 2);
4883 rt2800_register_write(rt2x00dev
, LG_FBK_CFG1
, reg
);
4886 * Do not force the BA window size, we use the TXWI to set it
4888 rt2800_register_read(rt2x00dev
, AMPDU_BA_WINSIZE
, ®
);
4889 rt2x00_set_field32(®
, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE
, 0);
4890 rt2x00_set_field32(®
, AMPDU_BA_WINSIZE_FORCE_WINSIZE
, 0);
4891 rt2800_register_write(rt2x00dev
, AMPDU_BA_WINSIZE
, reg
);
4894 * We must clear the error counters.
4895 * These registers are cleared on read,
4896 * so we may pass a useless variable to store the value.
4898 rt2800_register_read(rt2x00dev
, RX_STA_CNT0
, ®
);
4899 rt2800_register_read(rt2x00dev
, RX_STA_CNT1
, ®
);
4900 rt2800_register_read(rt2x00dev
, RX_STA_CNT2
, ®
);
4901 rt2800_register_read(rt2x00dev
, TX_STA_CNT0
, ®
);
4902 rt2800_register_read(rt2x00dev
, TX_STA_CNT1
, ®
);
4903 rt2800_register_read(rt2x00dev
, TX_STA_CNT2
, ®
);
4906 * Setup leadtime for pre tbtt interrupt to 6ms
4908 rt2800_register_read(rt2x00dev
, INT_TIMER_CFG
, ®
);
4909 rt2x00_set_field32(®
, INT_TIMER_CFG_PRE_TBTT_TIMER
, 6 << 4);
4910 rt2800_register_write(rt2x00dev
, INT_TIMER_CFG
, reg
);
4913 * Set up channel statistics timer
4915 rt2800_register_read(rt2x00dev
, CH_TIME_CFG
, ®
);
4916 rt2x00_set_field32(®
, CH_TIME_CFG_EIFS_BUSY
, 1);
4917 rt2x00_set_field32(®
, CH_TIME_CFG_NAV_BUSY
, 1);
4918 rt2x00_set_field32(®
, CH_TIME_CFG_RX_BUSY
, 1);
4919 rt2x00_set_field32(®
, CH_TIME_CFG_TX_BUSY
, 1);
4920 rt2x00_set_field32(®
, CH_TIME_CFG_TMR_EN
, 1);
4921 rt2800_register_write(rt2x00dev
, CH_TIME_CFG
, reg
);
4926 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev
*rt2x00dev
)
4931 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
4932 rt2800_register_read(rt2x00dev
, MAC_STATUS_CFG
, ®
);
4933 if (!rt2x00_get_field32(reg
, MAC_STATUS_CFG_BBP_RF_BUSY
))
4936 udelay(REGISTER_BUSY_DELAY
);
4939 rt2x00_err(rt2x00dev
, "BBP/RF register access failed, aborting\n");
4943 static int rt2800_wait_bbp_ready(struct rt2x00_dev
*rt2x00dev
)
4949 * BBP was enabled after firmware was loaded,
4950 * but we need to reactivate it now.
4952 rt2800_register_write(rt2x00dev
, H2M_BBP_AGENT
, 0);
4953 rt2800_register_write(rt2x00dev
, H2M_MAILBOX_CSR
, 0);
4956 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
4957 rt2800_bbp_read(rt2x00dev
, 0, &value
);
4958 if ((value
!= 0xff) && (value
!= 0x00))
4960 udelay(REGISTER_BUSY_DELAY
);
4963 rt2x00_err(rt2x00dev
, "BBP register access failed, aborting\n");
4967 static void rt2800_bbp4_mac_if_ctrl(struct rt2x00_dev
*rt2x00dev
)
4971 rt2800_bbp_read(rt2x00dev
, 4, &value
);
4972 rt2x00_set_field8(&value
, BBP4_MAC_IF_CTRL
, 1);
4973 rt2800_bbp_write(rt2x00dev
, 4, value
);
4976 static void rt2800_init_freq_calibration(struct rt2x00_dev
*rt2x00dev
)
4978 rt2800_bbp_write(rt2x00dev
, 142, 1);
4979 rt2800_bbp_write(rt2x00dev
, 143, 57);
4982 static void rt2800_init_bbp_5592_glrt(struct rt2x00_dev
*rt2x00dev
)
4984 const u8 glrt_table
[] = {
4985 0xE0, 0x1F, 0X38, 0x32, 0x08, 0x28, 0x19, 0x0A, 0xFF, 0x00, /* 128 ~ 137 */
4986 0x16, 0x10, 0x10, 0x0B, 0x36, 0x2C, 0x26, 0x24, 0x42, 0x36, /* 138 ~ 147 */
4987 0x30, 0x2D, 0x4C, 0x46, 0x3D, 0x40, 0x3E, 0x42, 0x3D, 0x40, /* 148 ~ 157 */
4988 0X3C, 0x34, 0x2C, 0x2F, 0x3C, 0x35, 0x2E, 0x2A, 0x49, 0x41, /* 158 ~ 167 */
4989 0x36, 0x31, 0x30, 0x30, 0x0E, 0x0D, 0x28, 0x21, 0x1C, 0x16, /* 168 ~ 177 */
4990 0x50, 0x4A, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, /* 178 ~ 187 */
4991 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 188 ~ 197 */
4992 0x00, 0x00, 0x7D, 0x14, 0x32, 0x2C, 0x36, 0x4C, 0x43, 0x2C, /* 198 ~ 207 */
4993 0x2E, 0x36, 0x30, 0x6E, /* 208 ~ 211 */
4997 for (i
= 0; i
< ARRAY_SIZE(glrt_table
); i
++) {
4998 rt2800_bbp_write(rt2x00dev
, 195, 128 + i
);
4999 rt2800_bbp_write(rt2x00dev
, 196, glrt_table
[i
]);
5003 static void rt2800_init_bbp_early(struct rt2x00_dev
*rt2x00dev
)
5005 rt2800_bbp_write(rt2x00dev
, 65, 0x2C);
5006 rt2800_bbp_write(rt2x00dev
, 66, 0x38);
5007 rt2800_bbp_write(rt2x00dev
, 68, 0x0B);
5008 rt2800_bbp_write(rt2x00dev
, 69, 0x12);
5009 rt2800_bbp_write(rt2x00dev
, 70, 0x0a);
5010 rt2800_bbp_write(rt2x00dev
, 73, 0x10);
5011 rt2800_bbp_write(rt2x00dev
, 81, 0x37);
5012 rt2800_bbp_write(rt2x00dev
, 82, 0x62);
5013 rt2800_bbp_write(rt2x00dev
, 83, 0x6A);
5014 rt2800_bbp_write(rt2x00dev
, 84, 0x99);
5015 rt2800_bbp_write(rt2x00dev
, 86, 0x00);
5016 rt2800_bbp_write(rt2x00dev
, 91, 0x04);
5017 rt2800_bbp_write(rt2x00dev
, 92, 0x00);
5018 rt2800_bbp_write(rt2x00dev
, 103, 0x00);
5019 rt2800_bbp_write(rt2x00dev
, 105, 0x05);
5020 rt2800_bbp_write(rt2x00dev
, 106, 0x35);
5023 static void rt2800_disable_unused_dac_adc(struct rt2x00_dev
*rt2x00dev
)
5028 rt2800_bbp_read(rt2x00dev
, 138, &value
);
5029 rt2800_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF0
, &eeprom
);
5030 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_TXPATH
) == 1)
5032 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_RXPATH
) == 1)
5034 rt2800_bbp_write(rt2x00dev
, 138, value
);
5037 static void rt2800_init_bbp_305x_soc(struct rt2x00_dev
*rt2x00dev
)
5039 rt2800_bbp_write(rt2x00dev
, 31, 0x08);
5041 rt2800_bbp_write(rt2x00dev
, 65, 0x2c);
5042 rt2800_bbp_write(rt2x00dev
, 66, 0x38);
5044 rt2800_bbp_write(rt2x00dev
, 69, 0x12);
5045 rt2800_bbp_write(rt2x00dev
, 73, 0x10);
5047 rt2800_bbp_write(rt2x00dev
, 70, 0x0a);
5049 rt2800_bbp_write(rt2x00dev
, 78, 0x0e);
5050 rt2800_bbp_write(rt2x00dev
, 80, 0x08);
5052 rt2800_bbp_write(rt2x00dev
, 82, 0x62);
5054 rt2800_bbp_write(rt2x00dev
, 83, 0x6a);
5056 rt2800_bbp_write(rt2x00dev
, 84, 0x99);
5058 rt2800_bbp_write(rt2x00dev
, 86, 0x00);
5060 rt2800_bbp_write(rt2x00dev
, 91, 0x04);
5062 rt2800_bbp_write(rt2x00dev
, 92, 0x00);
5064 rt2800_bbp_write(rt2x00dev
, 103, 0xc0);
5066 rt2800_bbp_write(rt2x00dev
, 105, 0x01);
5068 rt2800_bbp_write(rt2x00dev
, 106, 0x35);
5071 static void rt2800_init_bbp_28xx(struct rt2x00_dev
*rt2x00dev
)
5073 rt2800_bbp_write(rt2x00dev
, 65, 0x2c);
5074 rt2800_bbp_write(rt2x00dev
, 66, 0x38);
5076 if (rt2x00_rt_rev(rt2x00dev
, RT2860
, REV_RT2860C
)) {
5077 rt2800_bbp_write(rt2x00dev
, 69, 0x16);
5078 rt2800_bbp_write(rt2x00dev
, 73, 0x12);
5080 rt2800_bbp_write(rt2x00dev
, 69, 0x12);
5081 rt2800_bbp_write(rt2x00dev
, 73, 0x10);
5084 rt2800_bbp_write(rt2x00dev
, 70, 0x0a);
5086 rt2800_bbp_write(rt2x00dev
, 81, 0x37);
5088 rt2800_bbp_write(rt2x00dev
, 82, 0x62);
5090 rt2800_bbp_write(rt2x00dev
, 83, 0x6a);
5092 if (rt2x00_rt_rev(rt2x00dev
, RT2860
, REV_RT2860D
))
5093 rt2800_bbp_write(rt2x00dev
, 84, 0x19);
5095 rt2800_bbp_write(rt2x00dev
, 84, 0x99);
5097 rt2800_bbp_write(rt2x00dev
, 86, 0x00);
5099 rt2800_bbp_write(rt2x00dev
, 91, 0x04);
5101 rt2800_bbp_write(rt2x00dev
, 92, 0x00);
5103 rt2800_bbp_write(rt2x00dev
, 103, 0x00);
5105 rt2800_bbp_write(rt2x00dev
, 105, 0x05);
5107 rt2800_bbp_write(rt2x00dev
, 106, 0x35);
5110 static void rt2800_init_bbp_30xx(struct rt2x00_dev
*rt2x00dev
)
5112 rt2800_bbp_write(rt2x00dev
, 65, 0x2c);
5113 rt2800_bbp_write(rt2x00dev
, 66, 0x38);
5115 rt2800_bbp_write(rt2x00dev
, 69, 0x12);
5116 rt2800_bbp_write(rt2x00dev
, 73, 0x10);
5118 rt2800_bbp_write(rt2x00dev
, 70, 0x0a);
5120 rt2800_bbp_write(rt2x00dev
, 79, 0x13);
5121 rt2800_bbp_write(rt2x00dev
, 80, 0x05);
5122 rt2800_bbp_write(rt2x00dev
, 81, 0x33);
5124 rt2800_bbp_write(rt2x00dev
, 82, 0x62);
5126 rt2800_bbp_write(rt2x00dev
, 83, 0x6a);
5128 rt2800_bbp_write(rt2x00dev
, 84, 0x99);
5130 rt2800_bbp_write(rt2x00dev
, 86, 0x00);
5132 rt2800_bbp_write(rt2x00dev
, 91, 0x04);
5134 rt2800_bbp_write(rt2x00dev
, 92, 0x00);
5136 if (rt2x00_rt_rev_gte(rt2x00dev
, RT3070
, REV_RT3070F
) ||
5137 rt2x00_rt_rev_gte(rt2x00dev
, RT3071
, REV_RT3071E
) ||
5138 rt2x00_rt_rev_gte(rt2x00dev
, RT3090
, REV_RT3090E
))
5139 rt2800_bbp_write(rt2x00dev
, 103, 0xc0);
5141 rt2800_bbp_write(rt2x00dev
, 103, 0x00);
5143 rt2800_bbp_write(rt2x00dev
, 105, 0x05);
5145 rt2800_bbp_write(rt2x00dev
, 106, 0x35);
5147 if (rt2x00_rt(rt2x00dev
, RT3071
) ||
5148 rt2x00_rt(rt2x00dev
, RT3090
))
5149 rt2800_disable_unused_dac_adc(rt2x00dev
);
5152 static void rt2800_init_bbp_3290(struct rt2x00_dev
*rt2x00dev
)
5156 rt2800_bbp4_mac_if_ctrl(rt2x00dev
);
5158 rt2800_bbp_write(rt2x00dev
, 31, 0x08);
5160 rt2800_bbp_write(rt2x00dev
, 65, 0x2c);
5161 rt2800_bbp_write(rt2x00dev
, 66, 0x38);
5163 rt2800_bbp_write(rt2x00dev
, 68, 0x0b);
5165 rt2800_bbp_write(rt2x00dev
, 69, 0x12);
5166 rt2800_bbp_write(rt2x00dev
, 73, 0x13);
5167 rt2800_bbp_write(rt2x00dev
, 75, 0x46);
5168 rt2800_bbp_write(rt2x00dev
, 76, 0x28);
5170 rt2800_bbp_write(rt2x00dev
, 77, 0x58);
5172 rt2800_bbp_write(rt2x00dev
, 70, 0x0a);
5174 rt2800_bbp_write(rt2x00dev
, 74, 0x0b);
5175 rt2800_bbp_write(rt2x00dev
, 79, 0x18);
5176 rt2800_bbp_write(rt2x00dev
, 80, 0x09);
5177 rt2800_bbp_write(rt2x00dev
, 81, 0x33);
5179 rt2800_bbp_write(rt2x00dev
, 82, 0x62);
5181 rt2800_bbp_write(rt2x00dev
, 83, 0x7a);
5183 rt2800_bbp_write(rt2x00dev
, 84, 0x9a);
5185 rt2800_bbp_write(rt2x00dev
, 86, 0x38);
5187 rt2800_bbp_write(rt2x00dev
, 91, 0x04);
5189 rt2800_bbp_write(rt2x00dev
, 92, 0x02);
5191 rt2800_bbp_write(rt2x00dev
, 103, 0xc0);
5193 rt2800_bbp_write(rt2x00dev
, 104, 0x92);
5195 rt2800_bbp_write(rt2x00dev
, 105, 0x1c);
5197 rt2800_bbp_write(rt2x00dev
, 106, 0x03);
5199 rt2800_bbp_write(rt2x00dev
, 128, 0x12);
5201 rt2800_bbp_write(rt2x00dev
, 67, 0x24);
5202 rt2800_bbp_write(rt2x00dev
, 143, 0x04);
5203 rt2800_bbp_write(rt2x00dev
, 142, 0x99);
5204 rt2800_bbp_write(rt2x00dev
, 150, 0x30);
5205 rt2800_bbp_write(rt2x00dev
, 151, 0x2e);
5206 rt2800_bbp_write(rt2x00dev
, 152, 0x20);
5207 rt2800_bbp_write(rt2x00dev
, 153, 0x34);
5208 rt2800_bbp_write(rt2x00dev
, 154, 0x40);
5209 rt2800_bbp_write(rt2x00dev
, 155, 0x3b);
5210 rt2800_bbp_write(rt2x00dev
, 253, 0x04);
5212 rt2800_bbp_read(rt2x00dev
, 47, &value
);
5213 rt2x00_set_field8(&value
, BBP47_TSSI_ADC6
, 1);
5214 rt2800_bbp_write(rt2x00dev
, 47, value
);
5216 /* Use 5-bit ADC for Acquisition and 8-bit ADC for data */
5217 rt2800_bbp_read(rt2x00dev
, 3, &value
);
5218 rt2x00_set_field8(&value
, BBP3_ADC_MODE_SWITCH
, 1);
5219 rt2x00_set_field8(&value
, BBP3_ADC_INIT_MODE
, 1);
5220 rt2800_bbp_write(rt2x00dev
, 3, value
);
5223 static void rt2800_init_bbp_3352(struct rt2x00_dev
*rt2x00dev
)
5225 rt2800_bbp_write(rt2x00dev
, 3, 0x00);
5226 rt2800_bbp_write(rt2x00dev
, 4, 0x50);
5228 rt2800_bbp_write(rt2x00dev
, 31, 0x08);
5230 rt2800_bbp_write(rt2x00dev
, 47, 0x48);
5232 rt2800_bbp_write(rt2x00dev
, 65, 0x2c);
5233 rt2800_bbp_write(rt2x00dev
, 66, 0x38);
5235 rt2800_bbp_write(rt2x00dev
, 68, 0x0b);
5237 rt2800_bbp_write(rt2x00dev
, 69, 0x12);
5238 rt2800_bbp_write(rt2x00dev
, 73, 0x13);
5239 rt2800_bbp_write(rt2x00dev
, 75, 0x46);
5240 rt2800_bbp_write(rt2x00dev
, 76, 0x28);
5242 rt2800_bbp_write(rt2x00dev
, 77, 0x59);
5244 rt2800_bbp_write(rt2x00dev
, 70, 0x0a);
5246 rt2800_bbp_write(rt2x00dev
, 78, 0x0e);
5247 rt2800_bbp_write(rt2x00dev
, 80, 0x08);
5248 rt2800_bbp_write(rt2x00dev
, 81, 0x37);
5250 rt2800_bbp_write(rt2x00dev
, 82, 0x62);
5252 rt2800_bbp_write(rt2x00dev
, 83, 0x6a);
5254 rt2800_bbp_write(rt2x00dev
, 84, 0x99);
5256 rt2800_bbp_write(rt2x00dev
, 86, 0x38);
5258 rt2800_bbp_write(rt2x00dev
, 88, 0x90);
5260 rt2800_bbp_write(rt2x00dev
, 91, 0x04);
5262 rt2800_bbp_write(rt2x00dev
, 92, 0x02);
5264 rt2800_bbp_write(rt2x00dev
, 103, 0xc0);
5266 rt2800_bbp_write(rt2x00dev
, 104, 0x92);
5268 rt2800_bbp_write(rt2x00dev
, 105, 0x34);
5270 rt2800_bbp_write(rt2x00dev
, 106, 0x05);
5272 rt2800_bbp_write(rt2x00dev
, 120, 0x50);
5274 rt2800_bbp_write(rt2x00dev
, 137, 0x0f);
5276 rt2800_bbp_write(rt2x00dev
, 163, 0xbd);
5277 /* Set ITxBF timeout to 0x9c40=1000msec */
5278 rt2800_bbp_write(rt2x00dev
, 179, 0x02);
5279 rt2800_bbp_write(rt2x00dev
, 180, 0x00);
5280 rt2800_bbp_write(rt2x00dev
, 182, 0x40);
5281 rt2800_bbp_write(rt2x00dev
, 180, 0x01);
5282 rt2800_bbp_write(rt2x00dev
, 182, 0x9c);
5283 rt2800_bbp_write(rt2x00dev
, 179, 0x00);
5284 /* Reprogram the inband interface to put right values in RXWI */
5285 rt2800_bbp_write(rt2x00dev
, 142, 0x04);
5286 rt2800_bbp_write(rt2x00dev
, 143, 0x3b);
5287 rt2800_bbp_write(rt2x00dev
, 142, 0x06);
5288 rt2800_bbp_write(rt2x00dev
, 143, 0xa0);
5289 rt2800_bbp_write(rt2x00dev
, 142, 0x07);
5290 rt2800_bbp_write(rt2x00dev
, 143, 0xa1);
5291 rt2800_bbp_write(rt2x00dev
, 142, 0x08);
5292 rt2800_bbp_write(rt2x00dev
, 143, 0xa2);
5294 rt2800_bbp_write(rt2x00dev
, 148, 0xc8);
5297 static void rt2800_init_bbp_3390(struct rt2x00_dev
*rt2x00dev
)
5299 rt2800_bbp_write(rt2x00dev
, 65, 0x2c);
5300 rt2800_bbp_write(rt2x00dev
, 66, 0x38);
5302 rt2800_bbp_write(rt2x00dev
, 69, 0x12);
5303 rt2800_bbp_write(rt2x00dev
, 73, 0x10);
5305 rt2800_bbp_write(rt2x00dev
, 70, 0x0a);
5307 rt2800_bbp_write(rt2x00dev
, 79, 0x13);
5308 rt2800_bbp_write(rt2x00dev
, 80, 0x05);
5309 rt2800_bbp_write(rt2x00dev
, 81, 0x33);
5311 rt2800_bbp_write(rt2x00dev
, 82, 0x62);
5313 rt2800_bbp_write(rt2x00dev
, 83, 0x6a);
5315 rt2800_bbp_write(rt2x00dev
, 84, 0x99);
5317 rt2800_bbp_write(rt2x00dev
, 86, 0x00);
5319 rt2800_bbp_write(rt2x00dev
, 91, 0x04);
5321 rt2800_bbp_write(rt2x00dev
, 92, 0x00);
5323 if (rt2x00_rt_rev_gte(rt2x00dev
, RT3390
, REV_RT3390E
))
5324 rt2800_bbp_write(rt2x00dev
, 103, 0xc0);
5326 rt2800_bbp_write(rt2x00dev
, 103, 0x00);
5328 rt2800_bbp_write(rt2x00dev
, 105, 0x05);
5330 rt2800_bbp_write(rt2x00dev
, 106, 0x35);
5332 rt2800_disable_unused_dac_adc(rt2x00dev
);
5335 static void rt2800_init_bbp_3572(struct rt2x00_dev
*rt2x00dev
)
5337 rt2800_bbp_write(rt2x00dev
, 31, 0x08);
5339 rt2800_bbp_write(rt2x00dev
, 65, 0x2c);
5340 rt2800_bbp_write(rt2x00dev
, 66, 0x38);
5342 rt2800_bbp_write(rt2x00dev
, 69, 0x12);
5343 rt2800_bbp_write(rt2x00dev
, 73, 0x10);
5345 rt2800_bbp_write(rt2x00dev
, 70, 0x0a);
5347 rt2800_bbp_write(rt2x00dev
, 79, 0x13);
5348 rt2800_bbp_write(rt2x00dev
, 80, 0x05);
5349 rt2800_bbp_write(rt2x00dev
, 81, 0x33);
5351 rt2800_bbp_write(rt2x00dev
, 82, 0x62);
5353 rt2800_bbp_write(rt2x00dev
, 83, 0x6a);
5355 rt2800_bbp_write(rt2x00dev
, 84, 0x99);
5357 rt2800_bbp_write(rt2x00dev
, 86, 0x00);
5359 rt2800_bbp_write(rt2x00dev
, 91, 0x04);
5361 rt2800_bbp_write(rt2x00dev
, 92, 0x00);
5363 rt2800_bbp_write(rt2x00dev
, 103, 0xc0);
5365 rt2800_bbp_write(rt2x00dev
, 105, 0x05);
5367 rt2800_bbp_write(rt2x00dev
, 106, 0x35);
5369 rt2800_disable_unused_dac_adc(rt2x00dev
);
5372 static void rt2800_init_bbp_3593(struct rt2x00_dev
*rt2x00dev
)
5374 rt2800_init_bbp_early(rt2x00dev
);
5376 rt2800_bbp_write(rt2x00dev
, 79, 0x13);
5377 rt2800_bbp_write(rt2x00dev
, 80, 0x05);
5378 rt2800_bbp_write(rt2x00dev
, 81, 0x33);
5379 rt2800_bbp_write(rt2x00dev
, 137, 0x0f);
5381 rt2800_bbp_write(rt2x00dev
, 84, 0x19);
5383 /* Enable DC filter */
5384 if (rt2x00_rt_rev_gte(rt2x00dev
, RT3593
, REV_RT3593E
))
5385 rt2800_bbp_write(rt2x00dev
, 103, 0xc0);
5388 static void rt2800_init_bbp_53xx(struct rt2x00_dev
*rt2x00dev
)
5394 rt2800_bbp4_mac_if_ctrl(rt2x00dev
);
5396 rt2800_bbp_write(rt2x00dev
, 31, 0x08);
5398 rt2800_bbp_write(rt2x00dev
, 65, 0x2c);
5399 rt2800_bbp_write(rt2x00dev
, 66, 0x38);
5401 rt2800_bbp_write(rt2x00dev
, 68, 0x0b);
5403 rt2800_bbp_write(rt2x00dev
, 69, 0x12);
5404 rt2800_bbp_write(rt2x00dev
, 73, 0x13);
5405 rt2800_bbp_write(rt2x00dev
, 75, 0x46);
5406 rt2800_bbp_write(rt2x00dev
, 76, 0x28);
5408 rt2800_bbp_write(rt2x00dev
, 77, 0x59);
5410 rt2800_bbp_write(rt2x00dev
, 70, 0x0a);
5412 rt2800_bbp_write(rt2x00dev
, 79, 0x13);
5413 rt2800_bbp_write(rt2x00dev
, 80, 0x05);
5414 rt2800_bbp_write(rt2x00dev
, 81, 0x33);
5416 rt2800_bbp_write(rt2x00dev
, 82, 0x62);
5418 rt2800_bbp_write(rt2x00dev
, 83, 0x7a);
5420 rt2800_bbp_write(rt2x00dev
, 84, 0x9a);
5422 rt2800_bbp_write(rt2x00dev
, 86, 0x38);
5424 if (rt2x00_rt(rt2x00dev
, RT5392
))
5425 rt2800_bbp_write(rt2x00dev
, 88, 0x90);
5427 rt2800_bbp_write(rt2x00dev
, 91, 0x04);
5429 rt2800_bbp_write(rt2x00dev
, 92, 0x02);
5431 if (rt2x00_rt(rt2x00dev
, RT5392
)) {
5432 rt2800_bbp_write(rt2x00dev
, 95, 0x9a);
5433 rt2800_bbp_write(rt2x00dev
, 98, 0x12);
5436 rt2800_bbp_write(rt2x00dev
, 103, 0xc0);
5438 rt2800_bbp_write(rt2x00dev
, 104, 0x92);
5440 rt2800_bbp_write(rt2x00dev
, 105, 0x3c);
5442 if (rt2x00_rt(rt2x00dev
, RT5390
))
5443 rt2800_bbp_write(rt2x00dev
, 106, 0x03);
5444 else if (rt2x00_rt(rt2x00dev
, RT5392
))
5445 rt2800_bbp_write(rt2x00dev
, 106, 0x12);
5449 rt2800_bbp_write(rt2x00dev
, 128, 0x12);
5451 if (rt2x00_rt(rt2x00dev
, RT5392
)) {
5452 rt2800_bbp_write(rt2x00dev
, 134, 0xd0);
5453 rt2800_bbp_write(rt2x00dev
, 135, 0xf6);
5456 rt2800_disable_unused_dac_adc(rt2x00dev
);
5458 rt2800_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF1
, &eeprom
);
5459 div_mode
= rt2x00_get_field16(eeprom
,
5460 EEPROM_NIC_CONF1_ANT_DIVERSITY
);
5461 ant
= (div_mode
== 3) ? 1 : 0;
5463 /* check if this is a Bluetooth combo card */
5464 if (test_bit(CAPABILITY_BT_COEXIST
, &rt2x00dev
->cap_flags
)) {
5467 rt2800_register_read(rt2x00dev
, GPIO_CTRL
, ®
);
5468 rt2x00_set_field32(®
, GPIO_CTRL_DIR3
, 0);
5469 rt2x00_set_field32(®
, GPIO_CTRL_DIR6
, 0);
5470 rt2x00_set_field32(®
, GPIO_CTRL_VAL3
, 0);
5471 rt2x00_set_field32(®
, GPIO_CTRL_VAL6
, 0);
5473 rt2x00_set_field32(®
, GPIO_CTRL_VAL3
, 1);
5475 rt2x00_set_field32(®
, GPIO_CTRL_VAL6
, 1);
5476 rt2800_register_write(rt2x00dev
, GPIO_CTRL
, reg
);
5479 /* This chip has hardware antenna diversity*/
5480 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390R
)) {
5481 rt2800_bbp_write(rt2x00dev
, 150, 0); /* Disable Antenna Software OFDM */
5482 rt2800_bbp_write(rt2x00dev
, 151, 0); /* Disable Antenna Software CCK */
5483 rt2800_bbp_write(rt2x00dev
, 154, 0); /* Clear previously selected antenna */
5486 rt2800_bbp_read(rt2x00dev
, 152, &value
);
5488 rt2x00_set_field8(&value
, BBP152_RX_DEFAULT_ANT
, 1);
5490 rt2x00_set_field8(&value
, BBP152_RX_DEFAULT_ANT
, 0);
5491 rt2800_bbp_write(rt2x00dev
, 152, value
);
5493 rt2800_init_freq_calibration(rt2x00dev
);
5496 static void rt2800_init_bbp_5592(struct rt2x00_dev
*rt2x00dev
)
5502 rt2800_init_bbp_early(rt2x00dev
);
5504 rt2800_bbp_read(rt2x00dev
, 105, &value
);
5505 rt2x00_set_field8(&value
, BBP105_MLD
,
5506 rt2x00dev
->default_ant
.rx_chain_num
== 2);
5507 rt2800_bbp_write(rt2x00dev
, 105, value
);
5509 rt2800_bbp4_mac_if_ctrl(rt2x00dev
);
5511 rt2800_bbp_write(rt2x00dev
, 20, 0x06);
5512 rt2800_bbp_write(rt2x00dev
, 31, 0x08);
5513 rt2800_bbp_write(rt2x00dev
, 65, 0x2C);
5514 rt2800_bbp_write(rt2x00dev
, 68, 0xDD);
5515 rt2800_bbp_write(rt2x00dev
, 69, 0x1A);
5516 rt2800_bbp_write(rt2x00dev
, 70, 0x05);
5517 rt2800_bbp_write(rt2x00dev
, 73, 0x13);
5518 rt2800_bbp_write(rt2x00dev
, 74, 0x0F);
5519 rt2800_bbp_write(rt2x00dev
, 75, 0x4F);
5520 rt2800_bbp_write(rt2x00dev
, 76, 0x28);
5521 rt2800_bbp_write(rt2x00dev
, 77, 0x59);
5522 rt2800_bbp_write(rt2x00dev
, 84, 0x9A);
5523 rt2800_bbp_write(rt2x00dev
, 86, 0x38);
5524 rt2800_bbp_write(rt2x00dev
, 88, 0x90);
5525 rt2800_bbp_write(rt2x00dev
, 91, 0x04);
5526 rt2800_bbp_write(rt2x00dev
, 92, 0x02);
5527 rt2800_bbp_write(rt2x00dev
, 95, 0x9a);
5528 rt2800_bbp_write(rt2x00dev
, 98, 0x12);
5529 rt2800_bbp_write(rt2x00dev
, 103, 0xC0);
5530 rt2800_bbp_write(rt2x00dev
, 104, 0x92);
5531 /* FIXME BBP105 owerwrite */
5532 rt2800_bbp_write(rt2x00dev
, 105, 0x3C);
5533 rt2800_bbp_write(rt2x00dev
, 106, 0x35);
5534 rt2800_bbp_write(rt2x00dev
, 128, 0x12);
5535 rt2800_bbp_write(rt2x00dev
, 134, 0xD0);
5536 rt2800_bbp_write(rt2x00dev
, 135, 0xF6);
5537 rt2800_bbp_write(rt2x00dev
, 137, 0x0F);
5539 /* Initialize GLRT (Generalized Likehood Radio Test) */
5540 rt2800_init_bbp_5592_glrt(rt2x00dev
);
5542 rt2800_bbp4_mac_if_ctrl(rt2x00dev
);
5544 rt2800_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF1
, &eeprom
);
5545 div_mode
= rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF1_ANT_DIVERSITY
);
5546 ant
= (div_mode
== 3) ? 1 : 0;
5547 rt2800_bbp_read(rt2x00dev
, 152, &value
);
5550 rt2x00_set_field8(&value
, BBP152_RX_DEFAULT_ANT
, 1);
5552 /* Auxiliary antenna */
5553 rt2x00_set_field8(&value
, BBP152_RX_DEFAULT_ANT
, 0);
5555 rt2800_bbp_write(rt2x00dev
, 152, value
);
5557 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5592
, REV_RT5592C
)) {
5558 rt2800_bbp_read(rt2x00dev
, 254, &value
);
5559 rt2x00_set_field8(&value
, BBP254_BIT7
, 1);
5560 rt2800_bbp_write(rt2x00dev
, 254, value
);
5563 rt2800_init_freq_calibration(rt2x00dev
);
5565 rt2800_bbp_write(rt2x00dev
, 84, 0x19);
5566 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5592
, REV_RT5592C
))
5567 rt2800_bbp_write(rt2x00dev
, 103, 0xc0);
5570 static void rt2800_init_bbp(struct rt2x00_dev
*rt2x00dev
)
5577 if (rt2800_is_305x_soc(rt2x00dev
))
5578 rt2800_init_bbp_305x_soc(rt2x00dev
);
5580 switch (rt2x00dev
->chip
.rt
) {
5584 rt2800_init_bbp_28xx(rt2x00dev
);
5589 rt2800_init_bbp_30xx(rt2x00dev
);
5592 rt2800_init_bbp_3290(rt2x00dev
);
5595 rt2800_init_bbp_3352(rt2x00dev
);
5598 rt2800_init_bbp_3390(rt2x00dev
);
5601 rt2800_init_bbp_3572(rt2x00dev
);
5604 rt2800_init_bbp_3593(rt2x00dev
);
5608 rt2800_init_bbp_53xx(rt2x00dev
);
5611 rt2800_init_bbp_5592(rt2x00dev
);
5615 for (i
= 0; i
< EEPROM_BBP_SIZE
; i
++) {
5616 rt2800_eeprom_read_from_array(rt2x00dev
, EEPROM_BBP_START
, i
,
5619 if (eeprom
!= 0xffff && eeprom
!= 0x0000) {
5620 reg_id
= rt2x00_get_field16(eeprom
, EEPROM_BBP_REG_ID
);
5621 value
= rt2x00_get_field16(eeprom
, EEPROM_BBP_VALUE
);
5622 rt2800_bbp_write(rt2x00dev
, reg_id
, value
);
5627 static void rt2800_led_open_drain_enable(struct rt2x00_dev
*rt2x00dev
)
5631 rt2800_register_read(rt2x00dev
, OPT_14_CSR
, ®
);
5632 rt2x00_set_field32(®
, OPT_14_CSR_BIT0
, 1);
5633 rt2800_register_write(rt2x00dev
, OPT_14_CSR
, reg
);
5636 static u8
rt2800_init_rx_filter(struct rt2x00_dev
*rt2x00dev
, bool bw40
,
5645 u8 rfcsr24
= (bw40
) ? 0x27 : 0x07;
5647 rt2800_rfcsr_write(rt2x00dev
, 24, rfcsr24
);
5649 rt2800_bbp_read(rt2x00dev
, 4, &bbp
);
5650 rt2x00_set_field8(&bbp
, BBP4_BANDWIDTH
, 2 * bw40
);
5651 rt2800_bbp_write(rt2x00dev
, 4, bbp
);
5653 rt2800_rfcsr_read(rt2x00dev
, 31, &rfcsr
);
5654 rt2x00_set_field8(&rfcsr
, RFCSR31_RX_H20M
, bw40
);
5655 rt2800_rfcsr_write(rt2x00dev
, 31, rfcsr
);
5657 rt2800_rfcsr_read(rt2x00dev
, 22, &rfcsr
);
5658 rt2x00_set_field8(&rfcsr
, RFCSR22_BASEBAND_LOOPBACK
, 1);
5659 rt2800_rfcsr_write(rt2x00dev
, 22, rfcsr
);
5662 * Set power & frequency of passband test tone
5664 rt2800_bbp_write(rt2x00dev
, 24, 0);
5666 for (i
= 0; i
< 100; i
++) {
5667 rt2800_bbp_write(rt2x00dev
, 25, 0x90);
5670 rt2800_bbp_read(rt2x00dev
, 55, &passband
);
5676 * Set power & frequency of stopband test tone
5678 rt2800_bbp_write(rt2x00dev
, 24, 0x06);
5680 for (i
= 0; i
< 100; i
++) {
5681 rt2800_bbp_write(rt2x00dev
, 25, 0x90);
5684 rt2800_bbp_read(rt2x00dev
, 55, &stopband
);
5686 if ((passband
- stopband
) <= filter_target
) {
5688 overtuned
+= ((passband
- stopband
) == filter_target
);
5692 rt2800_rfcsr_write(rt2x00dev
, 24, rfcsr24
);
5695 rfcsr24
-= !!overtuned
;
5697 rt2800_rfcsr_write(rt2x00dev
, 24, rfcsr24
);
5701 static void rt2800_rf_init_calibration(struct rt2x00_dev
*rt2x00dev
,
5702 const unsigned int rf_reg
)
5706 rt2800_rfcsr_read(rt2x00dev
, rf_reg
, &rfcsr
);
5707 rt2x00_set_field8(&rfcsr
, FIELD8(0x80), 1);
5708 rt2800_rfcsr_write(rt2x00dev
, rf_reg
, rfcsr
);
5710 rt2x00_set_field8(&rfcsr
, FIELD8(0x80), 0);
5711 rt2800_rfcsr_write(rt2x00dev
, rf_reg
, rfcsr
);
5714 static void rt2800_rx_filter_calibration(struct rt2x00_dev
*rt2x00dev
)
5716 struct rt2800_drv_data
*drv_data
= rt2x00dev
->drv_data
;
5722 * TODO: sync filter_tgt values with vendor driver
5724 if (rt2x00_rt(rt2x00dev
, RT3070
)) {
5725 filter_tgt_bw20
= 0x16;
5726 filter_tgt_bw40
= 0x19;
5728 filter_tgt_bw20
= 0x13;
5729 filter_tgt_bw40
= 0x15;
5732 drv_data
->calibration_bw20
=
5733 rt2800_init_rx_filter(rt2x00dev
, false, filter_tgt_bw20
);
5734 drv_data
->calibration_bw40
=
5735 rt2800_init_rx_filter(rt2x00dev
, true, filter_tgt_bw40
);
5738 * Save BBP 25 & 26 values for later use in channel switching (for 3052)
5740 rt2800_bbp_read(rt2x00dev
, 25, &drv_data
->bbp25
);
5741 rt2800_bbp_read(rt2x00dev
, 26, &drv_data
->bbp26
);
5744 * Set back to initial state
5746 rt2800_bbp_write(rt2x00dev
, 24, 0);
5748 rt2800_rfcsr_read(rt2x00dev
, 22, &rfcsr
);
5749 rt2x00_set_field8(&rfcsr
, RFCSR22_BASEBAND_LOOPBACK
, 0);
5750 rt2800_rfcsr_write(rt2x00dev
, 22, rfcsr
);
5753 * Set BBP back to BW20
5755 rt2800_bbp_read(rt2x00dev
, 4, &bbp
);
5756 rt2x00_set_field8(&bbp
, BBP4_BANDWIDTH
, 0);
5757 rt2800_bbp_write(rt2x00dev
, 4, bbp
);
5760 static void rt2800_normal_mode_setup_3xxx(struct rt2x00_dev
*rt2x00dev
)
5762 struct rt2800_drv_data
*drv_data
= rt2x00dev
->drv_data
;
5763 u8 min_gain
, rfcsr
, bbp
;
5766 rt2800_rfcsr_read(rt2x00dev
, 17, &rfcsr
);
5768 rt2x00_set_field8(&rfcsr
, RFCSR17_TX_LO1_EN
, 0);
5769 if (rt2x00_rt(rt2x00dev
, RT3070
) ||
5770 rt2x00_rt_rev_lt(rt2x00dev
, RT3071
, REV_RT3071E
) ||
5771 rt2x00_rt_rev_lt(rt2x00dev
, RT3090
, REV_RT3090E
) ||
5772 rt2x00_rt_rev_lt(rt2x00dev
, RT3390
, REV_RT3390E
)) {
5773 if (!test_bit(CAPABILITY_EXTERNAL_LNA_BG
, &rt2x00dev
->cap_flags
))
5774 rt2x00_set_field8(&rfcsr
, RFCSR17_R
, 1);
5777 min_gain
= rt2x00_rt(rt2x00dev
, RT3070
) ? 1 : 2;
5778 if (drv_data
->txmixer_gain_24g
>= min_gain
) {
5779 rt2x00_set_field8(&rfcsr
, RFCSR17_TXMIXER_GAIN
,
5780 drv_data
->txmixer_gain_24g
);
5783 rt2800_rfcsr_write(rt2x00dev
, 17, rfcsr
);
5785 if (rt2x00_rt(rt2x00dev
, RT3090
)) {
5786 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
5787 rt2800_bbp_read(rt2x00dev
, 138, &bbp
);
5788 rt2800_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF0
, &eeprom
);
5789 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_RXPATH
) == 1)
5790 rt2x00_set_field8(&bbp
, BBP138_RX_ADC1
, 0);
5791 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_TXPATH
) == 1)
5792 rt2x00_set_field8(&bbp
, BBP138_TX_DAC1
, 1);
5793 rt2800_bbp_write(rt2x00dev
, 138, bbp
);
5796 if (rt2x00_rt(rt2x00dev
, RT3070
)) {
5797 rt2800_rfcsr_read(rt2x00dev
, 27, &rfcsr
);
5798 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070F
))
5799 rt2x00_set_field8(&rfcsr
, RFCSR27_R1
, 3);
5801 rt2x00_set_field8(&rfcsr
, RFCSR27_R1
, 0);
5802 rt2x00_set_field8(&rfcsr
, RFCSR27_R2
, 0);
5803 rt2x00_set_field8(&rfcsr
, RFCSR27_R3
, 0);
5804 rt2x00_set_field8(&rfcsr
, RFCSR27_R4
, 0);
5805 rt2800_rfcsr_write(rt2x00dev
, 27, rfcsr
);
5806 } else if (rt2x00_rt(rt2x00dev
, RT3071
) ||
5807 rt2x00_rt(rt2x00dev
, RT3090
) ||
5808 rt2x00_rt(rt2x00dev
, RT3390
)) {
5809 rt2800_rfcsr_read(rt2x00dev
, 1, &rfcsr
);
5810 rt2x00_set_field8(&rfcsr
, RFCSR1_RF_BLOCK_EN
, 1);
5811 rt2x00_set_field8(&rfcsr
, RFCSR1_RX0_PD
, 0);
5812 rt2x00_set_field8(&rfcsr
, RFCSR1_TX0_PD
, 0);
5813 rt2x00_set_field8(&rfcsr
, RFCSR1_RX1_PD
, 1);
5814 rt2x00_set_field8(&rfcsr
, RFCSR1_TX1_PD
, 1);
5815 rt2800_rfcsr_write(rt2x00dev
, 1, rfcsr
);
5817 rt2800_rfcsr_read(rt2x00dev
, 15, &rfcsr
);
5818 rt2x00_set_field8(&rfcsr
, RFCSR15_TX_LO2_EN
, 0);
5819 rt2800_rfcsr_write(rt2x00dev
, 15, rfcsr
);
5821 rt2800_rfcsr_read(rt2x00dev
, 20, &rfcsr
);
5822 rt2x00_set_field8(&rfcsr
, RFCSR20_RX_LO1_EN
, 0);
5823 rt2800_rfcsr_write(rt2x00dev
, 20, rfcsr
);
5825 rt2800_rfcsr_read(rt2x00dev
, 21, &rfcsr
);
5826 rt2x00_set_field8(&rfcsr
, RFCSR21_RX_LO2_EN
, 0);
5827 rt2800_rfcsr_write(rt2x00dev
, 21, rfcsr
);
5831 static void rt2800_normal_mode_setup_3593(struct rt2x00_dev
*rt2x00dev
)
5833 struct rt2800_drv_data
*drv_data
= rt2x00dev
->drv_data
;
5837 rt2800_rfcsr_read(rt2x00dev
, 50, &rfcsr
);
5838 rt2x00_set_field8(&rfcsr
, RFCSR50_TX_LO2_EN
, 0);
5839 rt2800_rfcsr_write(rt2x00dev
, 50, rfcsr
);
5841 rt2800_rfcsr_read(rt2x00dev
, 51, &rfcsr
);
5842 tx_gain
= rt2x00_get_field8(drv_data
->txmixer_gain_24g
,
5843 RFCSR17_TXMIXER_GAIN
);
5844 rt2x00_set_field8(&rfcsr
, RFCSR51_BITS24
, tx_gain
);
5845 rt2800_rfcsr_write(rt2x00dev
, 51, rfcsr
);
5847 rt2800_rfcsr_read(rt2x00dev
, 38, &rfcsr
);
5848 rt2x00_set_field8(&rfcsr
, RFCSR38_RX_LO1_EN
, 0);
5849 rt2800_rfcsr_write(rt2x00dev
, 38, rfcsr
);
5851 rt2800_rfcsr_read(rt2x00dev
, 39, &rfcsr
);
5852 rt2x00_set_field8(&rfcsr
, RFCSR39_RX_LO2_EN
, 0);
5853 rt2800_rfcsr_write(rt2x00dev
, 39, rfcsr
);
5855 rt2800_rfcsr_read(rt2x00dev
, 1, &rfcsr
);
5856 rt2x00_set_field8(&rfcsr
, RFCSR1_RF_BLOCK_EN
, 1);
5857 rt2x00_set_field8(&rfcsr
, RFCSR1_PLL_PD
, 1);
5858 rt2800_rfcsr_write(rt2x00dev
, 1, rfcsr
);
5860 rt2800_rfcsr_read(rt2x00dev
, 30, &rfcsr
);
5861 rt2x00_set_field8(&rfcsr
, RFCSR30_RX_VCM
, 2);
5862 rt2800_rfcsr_write(rt2x00dev
, 30, rfcsr
);
5864 /* TODO: enable stream mode */
5867 static void rt2800_normal_mode_setup_5xxx(struct rt2x00_dev
*rt2x00dev
)
5872 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
5873 rt2800_bbp_read(rt2x00dev
, 138, ®
);
5874 rt2800_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF0
, &eeprom
);
5875 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_RXPATH
) == 1)
5876 rt2x00_set_field8(®
, BBP138_RX_ADC1
, 0);
5877 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_TXPATH
) == 1)
5878 rt2x00_set_field8(®
, BBP138_TX_DAC1
, 1);
5879 rt2800_bbp_write(rt2x00dev
, 138, reg
);
5881 rt2800_rfcsr_read(rt2x00dev
, 38, ®
);
5882 rt2x00_set_field8(®
, RFCSR38_RX_LO1_EN
, 0);
5883 rt2800_rfcsr_write(rt2x00dev
, 38, reg
);
5885 rt2800_rfcsr_read(rt2x00dev
, 39, ®
);
5886 rt2x00_set_field8(®
, RFCSR39_RX_LO2_EN
, 0);
5887 rt2800_rfcsr_write(rt2x00dev
, 39, reg
);
5889 rt2800_bbp4_mac_if_ctrl(rt2x00dev
);
5891 rt2800_rfcsr_read(rt2x00dev
, 30, ®
);
5892 rt2x00_set_field8(®
, RFCSR30_RX_VCM
, 2);
5893 rt2800_rfcsr_write(rt2x00dev
, 30, reg
);
5896 static void rt2800_init_rfcsr_305x_soc(struct rt2x00_dev
*rt2x00dev
)
5898 rt2800_rf_init_calibration(rt2x00dev
, 30);
5900 rt2800_rfcsr_write(rt2x00dev
, 0, 0x50);
5901 rt2800_rfcsr_write(rt2x00dev
, 1, 0x01);
5902 rt2800_rfcsr_write(rt2x00dev
, 2, 0xf7);
5903 rt2800_rfcsr_write(rt2x00dev
, 3, 0x75);
5904 rt2800_rfcsr_write(rt2x00dev
, 4, 0x40);
5905 rt2800_rfcsr_write(rt2x00dev
, 5, 0x03);
5906 rt2800_rfcsr_write(rt2x00dev
, 6, 0x02);
5907 rt2800_rfcsr_write(rt2x00dev
, 7, 0x50);
5908 rt2800_rfcsr_write(rt2x00dev
, 8, 0x39);
5909 rt2800_rfcsr_write(rt2x00dev
, 9, 0x0f);
5910 rt2800_rfcsr_write(rt2x00dev
, 10, 0x60);
5911 rt2800_rfcsr_write(rt2x00dev
, 11, 0x21);
5912 rt2800_rfcsr_write(rt2x00dev
, 12, 0x75);
5913 rt2800_rfcsr_write(rt2x00dev
, 13, 0x75);
5914 rt2800_rfcsr_write(rt2x00dev
, 14, 0x90);
5915 rt2800_rfcsr_write(rt2x00dev
, 15, 0x58);
5916 rt2800_rfcsr_write(rt2x00dev
, 16, 0xb3);
5917 rt2800_rfcsr_write(rt2x00dev
, 17, 0x92);
5918 rt2800_rfcsr_write(rt2x00dev
, 18, 0x2c);
5919 rt2800_rfcsr_write(rt2x00dev
, 19, 0x02);
5920 rt2800_rfcsr_write(rt2x00dev
, 20, 0xba);
5921 rt2800_rfcsr_write(rt2x00dev
, 21, 0xdb);
5922 rt2800_rfcsr_write(rt2x00dev
, 22, 0x00);
5923 rt2800_rfcsr_write(rt2x00dev
, 23, 0x31);
5924 rt2800_rfcsr_write(rt2x00dev
, 24, 0x08);
5925 rt2800_rfcsr_write(rt2x00dev
, 25, 0x01);
5926 rt2800_rfcsr_write(rt2x00dev
, 26, 0x25);
5927 rt2800_rfcsr_write(rt2x00dev
, 27, 0x23);
5928 rt2800_rfcsr_write(rt2x00dev
, 28, 0x13);
5929 rt2800_rfcsr_write(rt2x00dev
, 29, 0x83);
5930 rt2800_rfcsr_write(rt2x00dev
, 30, 0x00);
5931 rt2800_rfcsr_write(rt2x00dev
, 31, 0x00);
5934 static void rt2800_init_rfcsr_30xx(struct rt2x00_dev
*rt2x00dev
)
5940 /* XXX vendor driver do this only for 3070 */
5941 rt2800_rf_init_calibration(rt2x00dev
, 30);
5943 rt2800_rfcsr_write(rt2x00dev
, 4, 0x40);
5944 rt2800_rfcsr_write(rt2x00dev
, 5, 0x03);
5945 rt2800_rfcsr_write(rt2x00dev
, 6, 0x02);
5946 rt2800_rfcsr_write(rt2x00dev
, 7, 0x60);
5947 rt2800_rfcsr_write(rt2x00dev
, 9, 0x0f);
5948 rt2800_rfcsr_write(rt2x00dev
, 10, 0x41);
5949 rt2800_rfcsr_write(rt2x00dev
, 11, 0x21);
5950 rt2800_rfcsr_write(rt2x00dev
, 12, 0x7b);
5951 rt2800_rfcsr_write(rt2x00dev
, 14, 0x90);
5952 rt2800_rfcsr_write(rt2x00dev
, 15, 0x58);
5953 rt2800_rfcsr_write(rt2x00dev
, 16, 0xb3);
5954 rt2800_rfcsr_write(rt2x00dev
, 17, 0x92);
5955 rt2800_rfcsr_write(rt2x00dev
, 18, 0x2c);
5956 rt2800_rfcsr_write(rt2x00dev
, 19, 0x02);
5957 rt2800_rfcsr_write(rt2x00dev
, 20, 0xba);
5958 rt2800_rfcsr_write(rt2x00dev
, 21, 0xdb);
5959 rt2800_rfcsr_write(rt2x00dev
, 24, 0x16);
5960 rt2800_rfcsr_write(rt2x00dev
, 25, 0x01);
5961 rt2800_rfcsr_write(rt2x00dev
, 29, 0x1f);
5963 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070F
)) {
5964 rt2800_register_read(rt2x00dev
, LDO_CFG0
, ®
);
5965 rt2x00_set_field32(®
, LDO_CFG0_BGSEL
, 1);
5966 rt2x00_set_field32(®
, LDO_CFG0_LDO_CORE_VLEVEL
, 3);
5967 rt2800_register_write(rt2x00dev
, LDO_CFG0
, reg
);
5968 } else if (rt2x00_rt(rt2x00dev
, RT3071
) ||
5969 rt2x00_rt(rt2x00dev
, RT3090
)) {
5970 rt2800_rfcsr_write(rt2x00dev
, 31, 0x14);
5972 rt2800_rfcsr_read(rt2x00dev
, 6, &rfcsr
);
5973 rt2x00_set_field8(&rfcsr
, RFCSR6_R2
, 1);
5974 rt2800_rfcsr_write(rt2x00dev
, 6, rfcsr
);
5976 rt2800_register_read(rt2x00dev
, LDO_CFG0
, ®
);
5977 rt2x00_set_field32(®
, LDO_CFG0_BGSEL
, 1);
5978 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3071
, REV_RT3071E
) ||
5979 rt2x00_rt_rev_lt(rt2x00dev
, RT3090
, REV_RT3090E
)) {
5980 rt2800_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF1
,
5982 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF1_DAC_TEST
))
5983 rt2x00_set_field32(®
, LDO_CFG0_LDO_CORE_VLEVEL
, 3);
5985 rt2x00_set_field32(®
, LDO_CFG0_LDO_CORE_VLEVEL
, 0);
5987 rt2800_register_write(rt2x00dev
, LDO_CFG0
, reg
);
5989 rt2800_register_read(rt2x00dev
, GPIO_SWITCH
, ®
);
5990 rt2x00_set_field32(®
, GPIO_SWITCH_5
, 0);
5991 rt2800_register_write(rt2x00dev
, GPIO_SWITCH
, reg
);
5994 rt2800_rx_filter_calibration(rt2x00dev
);
5996 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070F
) ||
5997 rt2x00_rt_rev_lt(rt2x00dev
, RT3071
, REV_RT3071E
) ||
5998 rt2x00_rt_rev_lt(rt2x00dev
, RT3090
, REV_RT3090E
))
5999 rt2800_rfcsr_write(rt2x00dev
, 27, 0x03);
6001 rt2800_led_open_drain_enable(rt2x00dev
);
6002 rt2800_normal_mode_setup_3xxx(rt2x00dev
);
6005 static void rt2800_init_rfcsr_3290(struct rt2x00_dev
*rt2x00dev
)
6009 rt2800_rf_init_calibration(rt2x00dev
, 2);
6011 rt2800_rfcsr_write(rt2x00dev
, 1, 0x0f);
6012 rt2800_rfcsr_write(rt2x00dev
, 2, 0x80);
6013 rt2800_rfcsr_write(rt2x00dev
, 3, 0x08);
6014 rt2800_rfcsr_write(rt2x00dev
, 4, 0x00);
6015 rt2800_rfcsr_write(rt2x00dev
, 6, 0xa0);
6016 rt2800_rfcsr_write(rt2x00dev
, 8, 0xf3);
6017 rt2800_rfcsr_write(rt2x00dev
, 9, 0x02);
6018 rt2800_rfcsr_write(rt2x00dev
, 10, 0x53);
6019 rt2800_rfcsr_write(rt2x00dev
, 11, 0x4a);
6020 rt2800_rfcsr_write(rt2x00dev
, 12, 0x46);
6021 rt2800_rfcsr_write(rt2x00dev
, 13, 0x9f);
6022 rt2800_rfcsr_write(rt2x00dev
, 18, 0x02);
6023 rt2800_rfcsr_write(rt2x00dev
, 22, 0x20);
6024 rt2800_rfcsr_write(rt2x00dev
, 25, 0x83);
6025 rt2800_rfcsr_write(rt2x00dev
, 26, 0x82);
6026 rt2800_rfcsr_write(rt2x00dev
, 27, 0x09);
6027 rt2800_rfcsr_write(rt2x00dev
, 29, 0x10);
6028 rt2800_rfcsr_write(rt2x00dev
, 30, 0x10);
6029 rt2800_rfcsr_write(rt2x00dev
, 31, 0x80);
6030 rt2800_rfcsr_write(rt2x00dev
, 32, 0x80);
6031 rt2800_rfcsr_write(rt2x00dev
, 33, 0x00);
6032 rt2800_rfcsr_write(rt2x00dev
, 34, 0x05);
6033 rt2800_rfcsr_write(rt2x00dev
, 35, 0x12);
6034 rt2800_rfcsr_write(rt2x00dev
, 36, 0x00);
6035 rt2800_rfcsr_write(rt2x00dev
, 38, 0x85);
6036 rt2800_rfcsr_write(rt2x00dev
, 39, 0x1b);
6037 rt2800_rfcsr_write(rt2x00dev
, 40, 0x0b);
6038 rt2800_rfcsr_write(rt2x00dev
, 41, 0xbb);
6039 rt2800_rfcsr_write(rt2x00dev
, 42, 0xd5);
6040 rt2800_rfcsr_write(rt2x00dev
, 43, 0x7b);
6041 rt2800_rfcsr_write(rt2x00dev
, 44, 0x0e);
6042 rt2800_rfcsr_write(rt2x00dev
, 45, 0xa2);
6043 rt2800_rfcsr_write(rt2x00dev
, 46, 0x73);
6044 rt2800_rfcsr_write(rt2x00dev
, 47, 0x00);
6045 rt2800_rfcsr_write(rt2x00dev
, 48, 0x10);
6046 rt2800_rfcsr_write(rt2x00dev
, 49, 0x98);
6047 rt2800_rfcsr_write(rt2x00dev
, 52, 0x38);
6048 rt2800_rfcsr_write(rt2x00dev
, 53, 0x00);
6049 rt2800_rfcsr_write(rt2x00dev
, 54, 0x78);
6050 rt2800_rfcsr_write(rt2x00dev
, 55, 0x43);
6051 rt2800_rfcsr_write(rt2x00dev
, 56, 0x02);
6052 rt2800_rfcsr_write(rt2x00dev
, 57, 0x80);
6053 rt2800_rfcsr_write(rt2x00dev
, 58, 0x7f);
6054 rt2800_rfcsr_write(rt2x00dev
, 59, 0x09);
6055 rt2800_rfcsr_write(rt2x00dev
, 60, 0x45);
6056 rt2800_rfcsr_write(rt2x00dev
, 61, 0xc1);
6058 rt2800_rfcsr_read(rt2x00dev
, 29, &rfcsr
);
6059 rt2x00_set_field8(&rfcsr
, RFCSR29_RSSI_GAIN
, 3);
6060 rt2800_rfcsr_write(rt2x00dev
, 29, rfcsr
);
6062 rt2800_led_open_drain_enable(rt2x00dev
);
6063 rt2800_normal_mode_setup_3xxx(rt2x00dev
);
6066 static void rt2800_init_rfcsr_3352(struct rt2x00_dev
*rt2x00dev
)
6068 rt2800_rf_init_calibration(rt2x00dev
, 30);
6070 rt2800_rfcsr_write(rt2x00dev
, 0, 0xf0);
6071 rt2800_rfcsr_write(rt2x00dev
, 1, 0x23);
6072 rt2800_rfcsr_write(rt2x00dev
, 2, 0x50);
6073 rt2800_rfcsr_write(rt2x00dev
, 3, 0x18);
6074 rt2800_rfcsr_write(rt2x00dev
, 4, 0x00);
6075 rt2800_rfcsr_write(rt2x00dev
, 5, 0x00);
6076 rt2800_rfcsr_write(rt2x00dev
, 6, 0x33);
6077 rt2800_rfcsr_write(rt2x00dev
, 7, 0x00);
6078 rt2800_rfcsr_write(rt2x00dev
, 8, 0xf1);
6079 rt2800_rfcsr_write(rt2x00dev
, 9, 0x02);
6080 rt2800_rfcsr_write(rt2x00dev
, 10, 0xd2);
6081 rt2800_rfcsr_write(rt2x00dev
, 11, 0x42);
6082 rt2800_rfcsr_write(rt2x00dev
, 12, 0x1c);
6083 rt2800_rfcsr_write(rt2x00dev
, 13, 0x00);
6084 rt2800_rfcsr_write(rt2x00dev
, 14, 0x5a);
6085 rt2800_rfcsr_write(rt2x00dev
, 15, 0x00);
6086 rt2800_rfcsr_write(rt2x00dev
, 16, 0x01);
6087 rt2800_rfcsr_write(rt2x00dev
, 18, 0x45);
6088 rt2800_rfcsr_write(rt2x00dev
, 19, 0x02);
6089 rt2800_rfcsr_write(rt2x00dev
, 20, 0x00);
6090 rt2800_rfcsr_write(rt2x00dev
, 21, 0x00);
6091 rt2800_rfcsr_write(rt2x00dev
, 22, 0x00);
6092 rt2800_rfcsr_write(rt2x00dev
, 23, 0x00);
6093 rt2800_rfcsr_write(rt2x00dev
, 24, 0x00);
6094 rt2800_rfcsr_write(rt2x00dev
, 25, 0x80);
6095 rt2800_rfcsr_write(rt2x00dev
, 26, 0x00);
6096 rt2800_rfcsr_write(rt2x00dev
, 27, 0x03);
6097 rt2800_rfcsr_write(rt2x00dev
, 28, 0x03);
6098 rt2800_rfcsr_write(rt2x00dev
, 29, 0x00);
6099 rt2800_rfcsr_write(rt2x00dev
, 30, 0x10);
6100 rt2800_rfcsr_write(rt2x00dev
, 31, 0x80);
6101 rt2800_rfcsr_write(rt2x00dev
, 32, 0x80);
6102 rt2800_rfcsr_write(rt2x00dev
, 33, 0x00);
6103 rt2800_rfcsr_write(rt2x00dev
, 34, 0x01);
6104 rt2800_rfcsr_write(rt2x00dev
, 35, 0x03);
6105 rt2800_rfcsr_write(rt2x00dev
, 36, 0xbd);
6106 rt2800_rfcsr_write(rt2x00dev
, 37, 0x3c);
6107 rt2800_rfcsr_write(rt2x00dev
, 38, 0x5f);
6108 rt2800_rfcsr_write(rt2x00dev
, 39, 0xc5);
6109 rt2800_rfcsr_write(rt2x00dev
, 40, 0x33);
6110 rt2800_rfcsr_write(rt2x00dev
, 41, 0x5b);
6111 rt2800_rfcsr_write(rt2x00dev
, 42, 0x5b);
6112 rt2800_rfcsr_write(rt2x00dev
, 43, 0xdb);
6113 rt2800_rfcsr_write(rt2x00dev
, 44, 0xdb);
6114 rt2800_rfcsr_write(rt2x00dev
, 45, 0xdb);
6115 rt2800_rfcsr_write(rt2x00dev
, 46, 0xdd);
6116 rt2800_rfcsr_write(rt2x00dev
, 47, 0x0d);
6117 rt2800_rfcsr_write(rt2x00dev
, 48, 0x14);
6118 rt2800_rfcsr_write(rt2x00dev
, 49, 0x00);
6119 rt2800_rfcsr_write(rt2x00dev
, 50, 0x2d);
6120 rt2800_rfcsr_write(rt2x00dev
, 51, 0x7f);
6121 rt2800_rfcsr_write(rt2x00dev
, 52, 0x00);
6122 rt2800_rfcsr_write(rt2x00dev
, 53, 0x52);
6123 rt2800_rfcsr_write(rt2x00dev
, 54, 0x1b);
6124 rt2800_rfcsr_write(rt2x00dev
, 55, 0x7f);
6125 rt2800_rfcsr_write(rt2x00dev
, 56, 0x00);
6126 rt2800_rfcsr_write(rt2x00dev
, 57, 0x52);
6127 rt2800_rfcsr_write(rt2x00dev
, 58, 0x1b);
6128 rt2800_rfcsr_write(rt2x00dev
, 59, 0x00);
6129 rt2800_rfcsr_write(rt2x00dev
, 60, 0x00);
6130 rt2800_rfcsr_write(rt2x00dev
, 61, 0x00);
6131 rt2800_rfcsr_write(rt2x00dev
, 62, 0x00);
6132 rt2800_rfcsr_write(rt2x00dev
, 63, 0x00);
6134 rt2800_rx_filter_calibration(rt2x00dev
);
6135 rt2800_led_open_drain_enable(rt2x00dev
);
6136 rt2800_normal_mode_setup_3xxx(rt2x00dev
);
6139 static void rt2800_init_rfcsr_3390(struct rt2x00_dev
*rt2x00dev
)
6143 rt2800_rf_init_calibration(rt2x00dev
, 30);
6145 rt2800_rfcsr_write(rt2x00dev
, 0, 0xa0);
6146 rt2800_rfcsr_write(rt2x00dev
, 1, 0xe1);
6147 rt2800_rfcsr_write(rt2x00dev
, 2, 0xf1);
6148 rt2800_rfcsr_write(rt2x00dev
, 3, 0x62);
6149 rt2800_rfcsr_write(rt2x00dev
, 4, 0x40);
6150 rt2800_rfcsr_write(rt2x00dev
, 5, 0x8b);
6151 rt2800_rfcsr_write(rt2x00dev
, 6, 0x42);
6152 rt2800_rfcsr_write(rt2x00dev
, 7, 0x34);
6153 rt2800_rfcsr_write(rt2x00dev
, 8, 0x00);
6154 rt2800_rfcsr_write(rt2x00dev
, 9, 0xc0);
6155 rt2800_rfcsr_write(rt2x00dev
, 10, 0x61);
6156 rt2800_rfcsr_write(rt2x00dev
, 11, 0x21);
6157 rt2800_rfcsr_write(rt2x00dev
, 12, 0x3b);
6158 rt2800_rfcsr_write(rt2x00dev
, 13, 0xe0);
6159 rt2800_rfcsr_write(rt2x00dev
, 14, 0x90);
6160 rt2800_rfcsr_write(rt2x00dev
, 15, 0x53);
6161 rt2800_rfcsr_write(rt2x00dev
, 16, 0xe0);
6162 rt2800_rfcsr_write(rt2x00dev
, 17, 0x94);
6163 rt2800_rfcsr_write(rt2x00dev
, 18, 0x5c);
6164 rt2800_rfcsr_write(rt2x00dev
, 19, 0x4a);
6165 rt2800_rfcsr_write(rt2x00dev
, 20, 0xb2);
6166 rt2800_rfcsr_write(rt2x00dev
, 21, 0xf6);
6167 rt2800_rfcsr_write(rt2x00dev
, 22, 0x00);
6168 rt2800_rfcsr_write(rt2x00dev
, 23, 0x14);
6169 rt2800_rfcsr_write(rt2x00dev
, 24, 0x08);
6170 rt2800_rfcsr_write(rt2x00dev
, 25, 0x3d);
6171 rt2800_rfcsr_write(rt2x00dev
, 26, 0x85);
6172 rt2800_rfcsr_write(rt2x00dev
, 27, 0x00);
6173 rt2800_rfcsr_write(rt2x00dev
, 28, 0x41);
6174 rt2800_rfcsr_write(rt2x00dev
, 29, 0x8f);
6175 rt2800_rfcsr_write(rt2x00dev
, 30, 0x20);
6176 rt2800_rfcsr_write(rt2x00dev
, 31, 0x0f);
6178 rt2800_register_read(rt2x00dev
, GPIO_SWITCH
, ®
);
6179 rt2x00_set_field32(®
, GPIO_SWITCH_5
, 0);
6180 rt2800_register_write(rt2x00dev
, GPIO_SWITCH
, reg
);
6182 rt2800_rx_filter_calibration(rt2x00dev
);
6184 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3390
, REV_RT3390E
))
6185 rt2800_rfcsr_write(rt2x00dev
, 27, 0x03);
6187 rt2800_led_open_drain_enable(rt2x00dev
);
6188 rt2800_normal_mode_setup_3xxx(rt2x00dev
);
6191 static void rt2800_init_rfcsr_3572(struct rt2x00_dev
*rt2x00dev
)
6196 rt2800_rf_init_calibration(rt2x00dev
, 30);
6198 rt2800_rfcsr_write(rt2x00dev
, 0, 0x70);
6199 rt2800_rfcsr_write(rt2x00dev
, 1, 0x81);
6200 rt2800_rfcsr_write(rt2x00dev
, 2, 0xf1);
6201 rt2800_rfcsr_write(rt2x00dev
, 3, 0x02);
6202 rt2800_rfcsr_write(rt2x00dev
, 4, 0x4c);
6203 rt2800_rfcsr_write(rt2x00dev
, 5, 0x05);
6204 rt2800_rfcsr_write(rt2x00dev
, 6, 0x4a);
6205 rt2800_rfcsr_write(rt2x00dev
, 7, 0xd8);
6206 rt2800_rfcsr_write(rt2x00dev
, 9, 0xc3);
6207 rt2800_rfcsr_write(rt2x00dev
, 10, 0xf1);
6208 rt2800_rfcsr_write(rt2x00dev
, 11, 0xb9);
6209 rt2800_rfcsr_write(rt2x00dev
, 12, 0x70);
6210 rt2800_rfcsr_write(rt2x00dev
, 13, 0x65);
6211 rt2800_rfcsr_write(rt2x00dev
, 14, 0xa0);
6212 rt2800_rfcsr_write(rt2x00dev
, 15, 0x53);
6213 rt2800_rfcsr_write(rt2x00dev
, 16, 0x4c);
6214 rt2800_rfcsr_write(rt2x00dev
, 17, 0x23);
6215 rt2800_rfcsr_write(rt2x00dev
, 18, 0xac);
6216 rt2800_rfcsr_write(rt2x00dev
, 19, 0x93);
6217 rt2800_rfcsr_write(rt2x00dev
, 20, 0xb3);
6218 rt2800_rfcsr_write(rt2x00dev
, 21, 0xd0);
6219 rt2800_rfcsr_write(rt2x00dev
, 22, 0x00);
6220 rt2800_rfcsr_write(rt2x00dev
, 23, 0x3c);
6221 rt2800_rfcsr_write(rt2x00dev
, 24, 0x16);
6222 rt2800_rfcsr_write(rt2x00dev
, 25, 0x15);
6223 rt2800_rfcsr_write(rt2x00dev
, 26, 0x85);
6224 rt2800_rfcsr_write(rt2x00dev
, 27, 0x00);
6225 rt2800_rfcsr_write(rt2x00dev
, 28, 0x00);
6226 rt2800_rfcsr_write(rt2x00dev
, 29, 0x9b);
6227 rt2800_rfcsr_write(rt2x00dev
, 30, 0x09);
6228 rt2800_rfcsr_write(rt2x00dev
, 31, 0x10);
6230 rt2800_rfcsr_read(rt2x00dev
, 6, &rfcsr
);
6231 rt2x00_set_field8(&rfcsr
, RFCSR6_R2
, 1);
6232 rt2800_rfcsr_write(rt2x00dev
, 6, rfcsr
);
6234 rt2800_register_read(rt2x00dev
, LDO_CFG0
, ®
);
6235 rt2x00_set_field32(®
, LDO_CFG0_LDO_CORE_VLEVEL
, 3);
6236 rt2x00_set_field32(®
, LDO_CFG0_BGSEL
, 1);
6237 rt2800_register_write(rt2x00dev
, LDO_CFG0
, reg
);
6239 rt2800_register_read(rt2x00dev
, LDO_CFG0
, ®
);
6240 rt2x00_set_field32(®
, LDO_CFG0_LDO_CORE_VLEVEL
, 0);
6241 rt2x00_set_field32(®
, LDO_CFG0_BGSEL
, 1);
6242 rt2800_register_write(rt2x00dev
, LDO_CFG0
, reg
);
6244 rt2800_rx_filter_calibration(rt2x00dev
);
6245 rt2800_led_open_drain_enable(rt2x00dev
);
6246 rt2800_normal_mode_setup_3xxx(rt2x00dev
);
6249 static void rt3593_post_bbp_init(struct rt2x00_dev
*rt2x00dev
)
6252 bool txbf_enabled
= false; /* FIXME */
6254 rt2800_bbp_read(rt2x00dev
, 105, &bbp
);
6255 if (rt2x00dev
->default_ant
.rx_chain_num
== 1)
6256 rt2x00_set_field8(&bbp
, BBP105_MLD
, 0);
6258 rt2x00_set_field8(&bbp
, BBP105_MLD
, 1);
6259 rt2800_bbp_write(rt2x00dev
, 105, bbp
);
6261 rt2800_bbp4_mac_if_ctrl(rt2x00dev
);
6263 rt2800_bbp_write(rt2x00dev
, 92, 0x02);
6264 rt2800_bbp_write(rt2x00dev
, 82, 0x82);
6265 rt2800_bbp_write(rt2x00dev
, 106, 0x05);
6266 rt2800_bbp_write(rt2x00dev
, 104, 0x92);
6267 rt2800_bbp_write(rt2x00dev
, 88, 0x90);
6268 rt2800_bbp_write(rt2x00dev
, 148, 0xc8);
6269 rt2800_bbp_write(rt2x00dev
, 47, 0x48);
6270 rt2800_bbp_write(rt2x00dev
, 120, 0x50);
6273 rt2800_bbp_write(rt2x00dev
, 163, 0xbd);
6275 rt2800_bbp_write(rt2x00dev
, 163, 0x9d);
6278 rt2800_bbp_write(rt2x00dev
, 142, 6);
6279 rt2800_bbp_write(rt2x00dev
, 143, 160);
6280 rt2800_bbp_write(rt2x00dev
, 142, 7);
6281 rt2800_bbp_write(rt2x00dev
, 143, 161);
6282 rt2800_bbp_write(rt2x00dev
, 142, 8);
6283 rt2800_bbp_write(rt2x00dev
, 143, 162);
6285 /* ADC/DAC control */
6286 rt2800_bbp_write(rt2x00dev
, 31, 0x08);
6288 /* RX AGC energy lower bound in log2 */
6289 rt2800_bbp_write(rt2x00dev
, 68, 0x0b);
6291 /* FIXME: BBP 105 owerwrite? */
6292 rt2800_bbp_write(rt2x00dev
, 105, 0x04);
6296 static void rt2800_init_rfcsr_3593(struct rt2x00_dev
*rt2x00dev
)
6298 struct rt2800_drv_data
*drv_data
= rt2x00dev
->drv_data
;
6302 /* Disable GPIO #4 and #7 function for LAN PE control */
6303 rt2800_register_read(rt2x00dev
, GPIO_SWITCH
, ®
);
6304 rt2x00_set_field32(®
, GPIO_SWITCH_4
, 0);
6305 rt2x00_set_field32(®
, GPIO_SWITCH_7
, 0);
6306 rt2800_register_write(rt2x00dev
, GPIO_SWITCH
, reg
);
6308 /* Initialize default register values */
6309 rt2800_rfcsr_write(rt2x00dev
, 1, 0x03);
6310 rt2800_rfcsr_write(rt2x00dev
, 3, 0x80);
6311 rt2800_rfcsr_write(rt2x00dev
, 5, 0x00);
6312 rt2800_rfcsr_write(rt2x00dev
, 6, 0x40);
6313 rt2800_rfcsr_write(rt2x00dev
, 8, 0xf1);
6314 rt2800_rfcsr_write(rt2x00dev
, 9, 0x02);
6315 rt2800_rfcsr_write(rt2x00dev
, 10, 0xd3);
6316 rt2800_rfcsr_write(rt2x00dev
, 11, 0x40);
6317 rt2800_rfcsr_write(rt2x00dev
, 12, 0x4e);
6318 rt2800_rfcsr_write(rt2x00dev
, 13, 0x12);
6319 rt2800_rfcsr_write(rt2x00dev
, 18, 0x40);
6320 rt2800_rfcsr_write(rt2x00dev
, 22, 0x20);
6321 rt2800_rfcsr_write(rt2x00dev
, 30, 0x10);
6322 rt2800_rfcsr_write(rt2x00dev
, 31, 0x80);
6323 rt2800_rfcsr_write(rt2x00dev
, 32, 0x78);
6324 rt2800_rfcsr_write(rt2x00dev
, 33, 0x3b);
6325 rt2800_rfcsr_write(rt2x00dev
, 34, 0x3c);
6326 rt2800_rfcsr_write(rt2x00dev
, 35, 0xe0);
6327 rt2800_rfcsr_write(rt2x00dev
, 38, 0x86);
6328 rt2800_rfcsr_write(rt2x00dev
, 39, 0x23);
6329 rt2800_rfcsr_write(rt2x00dev
, 44, 0xd3);
6330 rt2800_rfcsr_write(rt2x00dev
, 45, 0xbb);
6331 rt2800_rfcsr_write(rt2x00dev
, 46, 0x60);
6332 rt2800_rfcsr_write(rt2x00dev
, 49, 0x8e);
6333 rt2800_rfcsr_write(rt2x00dev
, 50, 0x86);
6334 rt2800_rfcsr_write(rt2x00dev
, 51, 0x75);
6335 rt2800_rfcsr_write(rt2x00dev
, 52, 0x45);
6336 rt2800_rfcsr_write(rt2x00dev
, 53, 0x18);
6337 rt2800_rfcsr_write(rt2x00dev
, 54, 0x18);
6338 rt2800_rfcsr_write(rt2x00dev
, 55, 0x18);
6339 rt2800_rfcsr_write(rt2x00dev
, 56, 0xdb);
6340 rt2800_rfcsr_write(rt2x00dev
, 57, 0x6e);
6342 /* Initiate calibration */
6343 /* TODO: use rt2800_rf_init_calibration ? */
6344 rt2800_rfcsr_read(rt2x00dev
, 2, &rfcsr
);
6345 rt2x00_set_field8(&rfcsr
, RFCSR2_RESCAL_EN
, 1);
6346 rt2800_rfcsr_write(rt2x00dev
, 2, rfcsr
);
6348 rt2800_adjust_freq_offset(rt2x00dev
);
6350 rt2800_rfcsr_read(rt2x00dev
, 18, &rfcsr
);
6351 rt2x00_set_field8(&rfcsr
, RFCSR18_XO_TUNE_BYPASS
, 1);
6352 rt2800_rfcsr_write(rt2x00dev
, 18, rfcsr
);
6354 rt2800_register_read(rt2x00dev
, LDO_CFG0
, ®
);
6355 rt2x00_set_field32(®
, LDO_CFG0_LDO_CORE_VLEVEL
, 3);
6356 rt2x00_set_field32(®
, LDO_CFG0_BGSEL
, 1);
6357 rt2800_register_write(rt2x00dev
, LDO_CFG0
, reg
);
6358 usleep_range(1000, 1500);
6359 rt2800_register_read(rt2x00dev
, LDO_CFG0
, ®
);
6360 rt2x00_set_field32(®
, LDO_CFG0_LDO_CORE_VLEVEL
, 0);
6361 rt2800_register_write(rt2x00dev
, LDO_CFG0
, reg
);
6363 /* Set initial values for RX filter calibration */
6364 drv_data
->calibration_bw20
= 0x1f;
6365 drv_data
->calibration_bw40
= 0x2f;
6367 /* Save BBP 25 & 26 values for later use in channel switching */
6368 rt2800_bbp_read(rt2x00dev
, 25, &drv_data
->bbp25
);
6369 rt2800_bbp_read(rt2x00dev
, 26, &drv_data
->bbp26
);
6371 rt2800_led_open_drain_enable(rt2x00dev
);
6372 rt2800_normal_mode_setup_3593(rt2x00dev
);
6374 rt3593_post_bbp_init(rt2x00dev
);
6376 /* TODO: enable stream mode support */
6379 static void rt2800_init_rfcsr_5390(struct rt2x00_dev
*rt2x00dev
)
6381 rt2800_rf_init_calibration(rt2x00dev
, 2);
6383 rt2800_rfcsr_write(rt2x00dev
, 1, 0x0f);
6384 rt2800_rfcsr_write(rt2x00dev
, 2, 0x80);
6385 rt2800_rfcsr_write(rt2x00dev
, 3, 0x88);
6386 rt2800_rfcsr_write(rt2x00dev
, 5, 0x10);
6387 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390F
))
6388 rt2800_rfcsr_write(rt2x00dev
, 6, 0xe0);
6390 rt2800_rfcsr_write(rt2x00dev
, 6, 0xa0);
6391 rt2800_rfcsr_write(rt2x00dev
, 7, 0x00);
6392 rt2800_rfcsr_write(rt2x00dev
, 10, 0x53);
6393 rt2800_rfcsr_write(rt2x00dev
, 11, 0x4a);
6394 rt2800_rfcsr_write(rt2x00dev
, 12, 0xc6);
6395 rt2800_rfcsr_write(rt2x00dev
, 13, 0x9f);
6396 rt2800_rfcsr_write(rt2x00dev
, 14, 0x00);
6397 rt2800_rfcsr_write(rt2x00dev
, 15, 0x00);
6398 rt2800_rfcsr_write(rt2x00dev
, 16, 0x00);
6399 rt2800_rfcsr_write(rt2x00dev
, 18, 0x03);
6400 rt2800_rfcsr_write(rt2x00dev
, 19, 0x00);
6402 rt2800_rfcsr_write(rt2x00dev
, 20, 0x00);
6403 rt2800_rfcsr_write(rt2x00dev
, 21, 0x00);
6404 rt2800_rfcsr_write(rt2x00dev
, 22, 0x20);
6405 rt2800_rfcsr_write(rt2x00dev
, 23, 0x00);
6406 rt2800_rfcsr_write(rt2x00dev
, 24, 0x00);
6407 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390F
))
6408 rt2800_rfcsr_write(rt2x00dev
, 25, 0x80);
6410 rt2800_rfcsr_write(rt2x00dev
, 25, 0xc0);
6411 rt2800_rfcsr_write(rt2x00dev
, 26, 0x00);
6412 rt2800_rfcsr_write(rt2x00dev
, 27, 0x09);
6413 rt2800_rfcsr_write(rt2x00dev
, 28, 0x00);
6414 rt2800_rfcsr_write(rt2x00dev
, 29, 0x10);
6416 rt2800_rfcsr_write(rt2x00dev
, 30, 0x00);
6417 rt2800_rfcsr_write(rt2x00dev
, 31, 0x80);
6418 rt2800_rfcsr_write(rt2x00dev
, 32, 0x80);
6419 rt2800_rfcsr_write(rt2x00dev
, 33, 0x00);
6420 rt2800_rfcsr_write(rt2x00dev
, 34, 0x07);
6421 rt2800_rfcsr_write(rt2x00dev
, 35, 0x12);
6422 rt2800_rfcsr_write(rt2x00dev
, 36, 0x00);
6423 rt2800_rfcsr_write(rt2x00dev
, 37, 0x08);
6424 rt2800_rfcsr_write(rt2x00dev
, 38, 0x85);
6425 rt2800_rfcsr_write(rt2x00dev
, 39, 0x1b);
6427 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390F
))
6428 rt2800_rfcsr_write(rt2x00dev
, 40, 0x0b);
6430 rt2800_rfcsr_write(rt2x00dev
, 40, 0x4b);
6431 rt2800_rfcsr_write(rt2x00dev
, 41, 0xbb);
6432 rt2800_rfcsr_write(rt2x00dev
, 42, 0xd2);
6433 rt2800_rfcsr_write(rt2x00dev
, 43, 0x9a);
6434 rt2800_rfcsr_write(rt2x00dev
, 44, 0x0e);
6435 rt2800_rfcsr_write(rt2x00dev
, 45, 0xa2);
6436 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390F
))
6437 rt2800_rfcsr_write(rt2x00dev
, 46, 0x73);
6439 rt2800_rfcsr_write(rt2x00dev
, 46, 0x7b);
6440 rt2800_rfcsr_write(rt2x00dev
, 47, 0x00);
6441 rt2800_rfcsr_write(rt2x00dev
, 48, 0x10);
6442 rt2800_rfcsr_write(rt2x00dev
, 49, 0x94);
6444 rt2800_rfcsr_write(rt2x00dev
, 52, 0x38);
6445 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390F
))
6446 rt2800_rfcsr_write(rt2x00dev
, 53, 0x00);
6448 rt2800_rfcsr_write(rt2x00dev
, 53, 0x84);
6449 rt2800_rfcsr_write(rt2x00dev
, 54, 0x78);
6450 rt2800_rfcsr_write(rt2x00dev
, 55, 0x44);
6451 rt2800_rfcsr_write(rt2x00dev
, 56, 0x22);
6452 rt2800_rfcsr_write(rt2x00dev
, 57, 0x80);
6453 rt2800_rfcsr_write(rt2x00dev
, 58, 0x7f);
6454 rt2800_rfcsr_write(rt2x00dev
, 59, 0x63);
6456 rt2800_rfcsr_write(rt2x00dev
, 60, 0x45);
6457 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390F
))
6458 rt2800_rfcsr_write(rt2x00dev
, 61, 0xd1);
6460 rt2800_rfcsr_write(rt2x00dev
, 61, 0xdd);
6461 rt2800_rfcsr_write(rt2x00dev
, 62, 0x00);
6462 rt2800_rfcsr_write(rt2x00dev
, 63, 0x00);
6464 rt2800_normal_mode_setup_5xxx(rt2x00dev
);
6466 rt2800_led_open_drain_enable(rt2x00dev
);
6469 static void rt2800_init_rfcsr_5392(struct rt2x00_dev
*rt2x00dev
)
6471 rt2800_rf_init_calibration(rt2x00dev
, 2);
6473 rt2800_rfcsr_write(rt2x00dev
, 1, 0x17);
6474 rt2800_rfcsr_write(rt2x00dev
, 2, 0x80);
6475 rt2800_rfcsr_write(rt2x00dev
, 3, 0x88);
6476 rt2800_rfcsr_write(rt2x00dev
, 5, 0x10);
6477 rt2800_rfcsr_write(rt2x00dev
, 6, 0xe0);
6478 rt2800_rfcsr_write(rt2x00dev
, 7, 0x00);
6479 rt2800_rfcsr_write(rt2x00dev
, 10, 0x53);
6480 rt2800_rfcsr_write(rt2x00dev
, 11, 0x4a);
6481 rt2800_rfcsr_write(rt2x00dev
, 12, 0x46);
6482 rt2800_rfcsr_write(rt2x00dev
, 13, 0x9f);
6483 rt2800_rfcsr_write(rt2x00dev
, 14, 0x00);
6484 rt2800_rfcsr_write(rt2x00dev
, 15, 0x00);
6485 rt2800_rfcsr_write(rt2x00dev
, 16, 0x00);
6486 rt2800_rfcsr_write(rt2x00dev
, 18, 0x03);
6487 rt2800_rfcsr_write(rt2x00dev
, 19, 0x4d);
6488 rt2800_rfcsr_write(rt2x00dev
, 20, 0x00);
6489 rt2800_rfcsr_write(rt2x00dev
, 21, 0x8d);
6490 rt2800_rfcsr_write(rt2x00dev
, 22, 0x20);
6491 rt2800_rfcsr_write(rt2x00dev
, 23, 0x0b);
6492 rt2800_rfcsr_write(rt2x00dev
, 24, 0x44);
6493 rt2800_rfcsr_write(rt2x00dev
, 25, 0x80);
6494 rt2800_rfcsr_write(rt2x00dev
, 26, 0x82);
6495 rt2800_rfcsr_write(rt2x00dev
, 27, 0x09);
6496 rt2800_rfcsr_write(rt2x00dev
, 28, 0x00);
6497 rt2800_rfcsr_write(rt2x00dev
, 29, 0x10);
6498 rt2800_rfcsr_write(rt2x00dev
, 30, 0x10);
6499 rt2800_rfcsr_write(rt2x00dev
, 31, 0x80);
6500 rt2800_rfcsr_write(rt2x00dev
, 32, 0x20);
6501 rt2800_rfcsr_write(rt2x00dev
, 33, 0xC0);
6502 rt2800_rfcsr_write(rt2x00dev
, 34, 0x07);
6503 rt2800_rfcsr_write(rt2x00dev
, 35, 0x12);
6504 rt2800_rfcsr_write(rt2x00dev
, 36, 0x00);
6505 rt2800_rfcsr_write(rt2x00dev
, 37, 0x08);
6506 rt2800_rfcsr_write(rt2x00dev
, 38, 0x89);
6507 rt2800_rfcsr_write(rt2x00dev
, 39, 0x1b);
6508 rt2800_rfcsr_write(rt2x00dev
, 40, 0x0f);
6509 rt2800_rfcsr_write(rt2x00dev
, 41, 0xbb);
6510 rt2800_rfcsr_write(rt2x00dev
, 42, 0xd5);
6511 rt2800_rfcsr_write(rt2x00dev
, 43, 0x9b);
6512 rt2800_rfcsr_write(rt2x00dev
, 44, 0x0e);
6513 rt2800_rfcsr_write(rt2x00dev
, 45, 0xa2);
6514 rt2800_rfcsr_write(rt2x00dev
, 46, 0x73);
6515 rt2800_rfcsr_write(rt2x00dev
, 47, 0x0c);
6516 rt2800_rfcsr_write(rt2x00dev
, 48, 0x10);
6517 rt2800_rfcsr_write(rt2x00dev
, 49, 0x94);
6518 rt2800_rfcsr_write(rt2x00dev
, 50, 0x94);
6519 rt2800_rfcsr_write(rt2x00dev
, 51, 0x3a);
6520 rt2800_rfcsr_write(rt2x00dev
, 52, 0x48);
6521 rt2800_rfcsr_write(rt2x00dev
, 53, 0x44);
6522 rt2800_rfcsr_write(rt2x00dev
, 54, 0x38);
6523 rt2800_rfcsr_write(rt2x00dev
, 55, 0x43);
6524 rt2800_rfcsr_write(rt2x00dev
, 56, 0xa1);
6525 rt2800_rfcsr_write(rt2x00dev
, 57, 0x00);
6526 rt2800_rfcsr_write(rt2x00dev
, 58, 0x39);
6527 rt2800_rfcsr_write(rt2x00dev
, 59, 0x07);
6528 rt2800_rfcsr_write(rt2x00dev
, 60, 0x45);
6529 rt2800_rfcsr_write(rt2x00dev
, 61, 0x91);
6530 rt2800_rfcsr_write(rt2x00dev
, 62, 0x39);
6531 rt2800_rfcsr_write(rt2x00dev
, 63, 0x07);
6533 rt2800_normal_mode_setup_5xxx(rt2x00dev
);
6535 rt2800_led_open_drain_enable(rt2x00dev
);
6538 static void rt2800_init_rfcsr_5592(struct rt2x00_dev
*rt2x00dev
)
6540 rt2800_rf_init_calibration(rt2x00dev
, 30);
6542 rt2800_rfcsr_write(rt2x00dev
, 1, 0x3F);
6543 rt2800_rfcsr_write(rt2x00dev
, 3, 0x08);
6544 rt2800_rfcsr_write(rt2x00dev
, 3, 0x08);
6545 rt2800_rfcsr_write(rt2x00dev
, 5, 0x10);
6546 rt2800_rfcsr_write(rt2x00dev
, 6, 0xE4);
6547 rt2800_rfcsr_write(rt2x00dev
, 7, 0x00);
6548 rt2800_rfcsr_write(rt2x00dev
, 14, 0x00);
6549 rt2800_rfcsr_write(rt2x00dev
, 15, 0x00);
6550 rt2800_rfcsr_write(rt2x00dev
, 16, 0x00);
6551 rt2800_rfcsr_write(rt2x00dev
, 18, 0x03);
6552 rt2800_rfcsr_write(rt2x00dev
, 19, 0x4D);
6553 rt2800_rfcsr_write(rt2x00dev
, 20, 0x10);
6554 rt2800_rfcsr_write(rt2x00dev
, 21, 0x8D);
6555 rt2800_rfcsr_write(rt2x00dev
, 26, 0x82);
6556 rt2800_rfcsr_write(rt2x00dev
, 28, 0x00);
6557 rt2800_rfcsr_write(rt2x00dev
, 29, 0x10);
6558 rt2800_rfcsr_write(rt2x00dev
, 33, 0xC0);
6559 rt2800_rfcsr_write(rt2x00dev
, 34, 0x07);
6560 rt2800_rfcsr_write(rt2x00dev
, 35, 0x12);
6561 rt2800_rfcsr_write(rt2x00dev
, 47, 0x0C);
6562 rt2800_rfcsr_write(rt2x00dev
, 53, 0x22);
6563 rt2800_rfcsr_write(rt2x00dev
, 63, 0x07);
6565 rt2800_rfcsr_write(rt2x00dev
, 2, 0x80);
6568 rt2800_adjust_freq_offset(rt2x00dev
);
6570 /* Enable DC filter */
6571 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5592
, REV_RT5592C
))
6572 rt2800_bbp_write(rt2x00dev
, 103, 0xc0);
6574 rt2800_normal_mode_setup_5xxx(rt2x00dev
);
6576 if (rt2x00_rt_rev_lt(rt2x00dev
, RT5592
, REV_RT5592C
))
6577 rt2800_rfcsr_write(rt2x00dev
, 27, 0x03);
6579 rt2800_led_open_drain_enable(rt2x00dev
);
6582 static void rt2800_init_rfcsr(struct rt2x00_dev
*rt2x00dev
)
6584 if (rt2800_is_305x_soc(rt2x00dev
)) {
6585 rt2800_init_rfcsr_305x_soc(rt2x00dev
);
6589 switch (rt2x00dev
->chip
.rt
) {
6593 rt2800_init_rfcsr_30xx(rt2x00dev
);
6596 rt2800_init_rfcsr_3290(rt2x00dev
);
6599 rt2800_init_rfcsr_3352(rt2x00dev
);
6602 rt2800_init_rfcsr_3390(rt2x00dev
);
6605 rt2800_init_rfcsr_3572(rt2x00dev
);
6608 rt2800_init_rfcsr_3593(rt2x00dev
);
6611 rt2800_init_rfcsr_5390(rt2x00dev
);
6614 rt2800_init_rfcsr_5392(rt2x00dev
);
6617 rt2800_init_rfcsr_5592(rt2x00dev
);
6622 int rt2800_enable_radio(struct rt2x00_dev
*rt2x00dev
)
6628 * Initialize all registers.
6630 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev
) ||
6631 rt2800_init_registers(rt2x00dev
)))
6635 * Send signal to firmware during boot time.
6637 rt2800_register_write(rt2x00dev
, H2M_BBP_AGENT
, 0);
6638 rt2800_register_write(rt2x00dev
, H2M_MAILBOX_CSR
, 0);
6639 if (rt2x00_is_usb(rt2x00dev
)) {
6640 rt2800_register_write(rt2x00dev
, H2M_INT_SRC
, 0);
6641 rt2800_mcu_request(rt2x00dev
, MCU_BOOT_SIGNAL
, 0, 0, 0);
6645 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev
) ||
6646 rt2800_wait_bbp_ready(rt2x00dev
)))
6649 rt2800_init_bbp(rt2x00dev
);
6650 rt2800_init_rfcsr(rt2x00dev
);
6652 if (rt2x00_is_usb(rt2x00dev
) &&
6653 (rt2x00_rt(rt2x00dev
, RT3070
) ||
6654 rt2x00_rt(rt2x00dev
, RT3071
) ||
6655 rt2x00_rt(rt2x00dev
, RT3572
))) {
6657 rt2800_mcu_request(rt2x00dev
, MCU_CURRENT
, 0, 0, 0);
6664 rt2800_register_read(rt2x00dev
, MAC_SYS_CTRL
, ®
);
6665 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_TX
, 1);
6666 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_RX
, 0);
6667 rt2800_register_write(rt2x00dev
, MAC_SYS_CTRL
, reg
);
6671 rt2800_register_read(rt2x00dev
, WPDMA_GLO_CFG
, ®
);
6672 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_TX_DMA
, 1);
6673 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_RX_DMA
, 1);
6674 rt2x00_set_field32(®
, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE
, 2);
6675 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_WRITEBACK_DONE
, 1);
6676 rt2800_register_write(rt2x00dev
, WPDMA_GLO_CFG
, reg
);
6678 rt2800_register_read(rt2x00dev
, MAC_SYS_CTRL
, ®
);
6679 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_TX
, 1);
6680 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_RX
, 1);
6681 rt2800_register_write(rt2x00dev
, MAC_SYS_CTRL
, reg
);
6684 * Initialize LED control
6686 rt2800_eeprom_read(rt2x00dev
, EEPROM_LED_AG_CONF
, &word
);
6687 rt2800_mcu_request(rt2x00dev
, MCU_LED_AG_CONF
, 0xff,
6688 word
& 0xff, (word
>> 8) & 0xff);
6690 rt2800_eeprom_read(rt2x00dev
, EEPROM_LED_ACT_CONF
, &word
);
6691 rt2800_mcu_request(rt2x00dev
, MCU_LED_ACT_CONF
, 0xff,
6692 word
& 0xff, (word
>> 8) & 0xff);
6694 rt2800_eeprom_read(rt2x00dev
, EEPROM_LED_POLARITY
, &word
);
6695 rt2800_mcu_request(rt2x00dev
, MCU_LED_LED_POLARITY
, 0xff,
6696 word
& 0xff, (word
>> 8) & 0xff);
6700 EXPORT_SYMBOL_GPL(rt2800_enable_radio
);
6702 void rt2800_disable_radio(struct rt2x00_dev
*rt2x00dev
)
6706 rt2800_disable_wpdma(rt2x00dev
);
6708 /* Wait for DMA, ignore error */
6709 rt2800_wait_wpdma_ready(rt2x00dev
);
6711 rt2800_register_read(rt2x00dev
, MAC_SYS_CTRL
, ®
);
6712 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_TX
, 0);
6713 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_RX
, 0);
6714 rt2800_register_write(rt2x00dev
, MAC_SYS_CTRL
, reg
);
6716 EXPORT_SYMBOL_GPL(rt2800_disable_radio
);
6718 int rt2800_efuse_detect(struct rt2x00_dev
*rt2x00dev
)
6723 if (rt2x00_rt(rt2x00dev
, RT3290
))
6724 efuse_ctrl_reg
= EFUSE_CTRL_3290
;
6726 efuse_ctrl_reg
= EFUSE_CTRL
;
6728 rt2800_register_read(rt2x00dev
, efuse_ctrl_reg
, ®
);
6729 return rt2x00_get_field32(reg
, EFUSE_CTRL_PRESENT
);
6731 EXPORT_SYMBOL_GPL(rt2800_efuse_detect
);
6733 static void rt2800_efuse_read(struct rt2x00_dev
*rt2x00dev
, unsigned int i
)
6737 u16 efuse_data0_reg
;
6738 u16 efuse_data1_reg
;
6739 u16 efuse_data2_reg
;
6740 u16 efuse_data3_reg
;
6742 if (rt2x00_rt(rt2x00dev
, RT3290
)) {
6743 efuse_ctrl_reg
= EFUSE_CTRL_3290
;
6744 efuse_data0_reg
= EFUSE_DATA0_3290
;
6745 efuse_data1_reg
= EFUSE_DATA1_3290
;
6746 efuse_data2_reg
= EFUSE_DATA2_3290
;
6747 efuse_data3_reg
= EFUSE_DATA3_3290
;
6749 efuse_ctrl_reg
= EFUSE_CTRL
;
6750 efuse_data0_reg
= EFUSE_DATA0
;
6751 efuse_data1_reg
= EFUSE_DATA1
;
6752 efuse_data2_reg
= EFUSE_DATA2
;
6753 efuse_data3_reg
= EFUSE_DATA3
;
6755 mutex_lock(&rt2x00dev
->csr_mutex
);
6757 rt2800_register_read_lock(rt2x00dev
, efuse_ctrl_reg
, ®
);
6758 rt2x00_set_field32(®
, EFUSE_CTRL_ADDRESS_IN
, i
);
6759 rt2x00_set_field32(®
, EFUSE_CTRL_MODE
, 0);
6760 rt2x00_set_field32(®
, EFUSE_CTRL_KICK
, 1);
6761 rt2800_register_write_lock(rt2x00dev
, efuse_ctrl_reg
, reg
);
6763 /* Wait until the EEPROM has been loaded */
6764 rt2800_regbusy_read(rt2x00dev
, efuse_ctrl_reg
, EFUSE_CTRL_KICK
, ®
);
6765 /* Apparently the data is read from end to start */
6766 rt2800_register_read_lock(rt2x00dev
, efuse_data3_reg
, ®
);
6767 /* The returned value is in CPU order, but eeprom is le */
6768 *(u32
*)&rt2x00dev
->eeprom
[i
] = cpu_to_le32(reg
);
6769 rt2800_register_read_lock(rt2x00dev
, efuse_data2_reg
, ®
);
6770 *(u32
*)&rt2x00dev
->eeprom
[i
+ 2] = cpu_to_le32(reg
);
6771 rt2800_register_read_lock(rt2x00dev
, efuse_data1_reg
, ®
);
6772 *(u32
*)&rt2x00dev
->eeprom
[i
+ 4] = cpu_to_le32(reg
);
6773 rt2800_register_read_lock(rt2x00dev
, efuse_data0_reg
, ®
);
6774 *(u32
*)&rt2x00dev
->eeprom
[i
+ 6] = cpu_to_le32(reg
);
6776 mutex_unlock(&rt2x00dev
->csr_mutex
);
6779 int rt2800_read_eeprom_efuse(struct rt2x00_dev
*rt2x00dev
)
6783 for (i
= 0; i
< EEPROM_SIZE
/ sizeof(u16
); i
+= 8)
6784 rt2800_efuse_read(rt2x00dev
, i
);
6788 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse
);
6790 static u8
rt2800_get_txmixer_gain_24g(struct rt2x00_dev
*rt2x00dev
)
6794 if (rt2x00_rt(rt2x00dev
, RT3593
))
6797 rt2800_eeprom_read(rt2x00dev
, EEPROM_TXMIXER_GAIN_BG
, &word
);
6798 if ((word
& 0x00ff) != 0x00ff)
6799 return rt2x00_get_field16(word
, EEPROM_TXMIXER_GAIN_BG_VAL
);
6804 static u8
rt2800_get_txmixer_gain_5g(struct rt2x00_dev
*rt2x00dev
)
6808 if (rt2x00_rt(rt2x00dev
, RT3593
))
6811 rt2800_eeprom_read(rt2x00dev
, EEPROM_TXMIXER_GAIN_A
, &word
);
6812 if ((word
& 0x00ff) != 0x00ff)
6813 return rt2x00_get_field16(word
, EEPROM_TXMIXER_GAIN_A_VAL
);
6818 static int rt2800_validate_eeprom(struct rt2x00_dev
*rt2x00dev
)
6820 struct rt2800_drv_data
*drv_data
= rt2x00dev
->drv_data
;
6823 u8 default_lna_gain
;
6829 retval
= rt2800_read_eeprom(rt2x00dev
);
6834 * Start validation of the data that has been read.
6836 mac
= rt2800_eeprom_addr(rt2x00dev
, EEPROM_MAC_ADDR_0
);
6837 if (!is_valid_ether_addr(mac
)) {
6838 eth_random_addr(mac
);
6839 rt2x00_eeprom_dbg(rt2x00dev
, "MAC: %pM\n", mac
);
6842 rt2800_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF0
, &word
);
6843 if (word
== 0xffff) {
6844 rt2x00_set_field16(&word
, EEPROM_NIC_CONF0_RXPATH
, 2);
6845 rt2x00_set_field16(&word
, EEPROM_NIC_CONF0_TXPATH
, 1);
6846 rt2x00_set_field16(&word
, EEPROM_NIC_CONF0_RF_TYPE
, RF2820
);
6847 rt2800_eeprom_write(rt2x00dev
, EEPROM_NIC_CONF0
, word
);
6848 rt2x00_eeprom_dbg(rt2x00dev
, "Antenna: 0x%04x\n", word
);
6849 } else if (rt2x00_rt(rt2x00dev
, RT2860
) ||
6850 rt2x00_rt(rt2x00dev
, RT2872
)) {
6852 * There is a max of 2 RX streams for RT28x0 series
6854 if (rt2x00_get_field16(word
, EEPROM_NIC_CONF0_RXPATH
) > 2)
6855 rt2x00_set_field16(&word
, EEPROM_NIC_CONF0_RXPATH
, 2);
6856 rt2800_eeprom_write(rt2x00dev
, EEPROM_NIC_CONF0
, word
);
6859 rt2800_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF1
, &word
);
6860 if (word
== 0xffff) {
6861 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_HW_RADIO
, 0);
6862 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC
, 0);
6863 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G
, 0);
6864 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G
, 0);
6865 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_CARDBUS_ACCEL
, 0);
6866 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_BW40M_SB_2G
, 0);
6867 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_BW40M_SB_5G
, 0);
6868 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_WPS_PBC
, 0);
6869 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_BW40M_2G
, 0);
6870 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_BW40M_5G
, 0);
6871 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA
, 0);
6872 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_ANT_DIVERSITY
, 0);
6873 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_INTERNAL_TX_ALC
, 0);
6874 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_BT_COEXIST
, 0);
6875 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_DAC_TEST
, 0);
6876 rt2800_eeprom_write(rt2x00dev
, EEPROM_NIC_CONF1
, word
);
6877 rt2x00_eeprom_dbg(rt2x00dev
, "NIC: 0x%04x\n", word
);
6880 rt2800_eeprom_read(rt2x00dev
, EEPROM_FREQ
, &word
);
6881 if ((word
& 0x00ff) == 0x00ff) {
6882 rt2x00_set_field16(&word
, EEPROM_FREQ_OFFSET
, 0);
6883 rt2800_eeprom_write(rt2x00dev
, EEPROM_FREQ
, word
);
6884 rt2x00_eeprom_dbg(rt2x00dev
, "Freq: 0x%04x\n", word
);
6886 if ((word
& 0xff00) == 0xff00) {
6887 rt2x00_set_field16(&word
, EEPROM_FREQ_LED_MODE
,
6888 LED_MODE_TXRX_ACTIVITY
);
6889 rt2x00_set_field16(&word
, EEPROM_FREQ_LED_POLARITY
, 0);
6890 rt2800_eeprom_write(rt2x00dev
, EEPROM_FREQ
, word
);
6891 rt2800_eeprom_write(rt2x00dev
, EEPROM_LED_AG_CONF
, 0x5555);
6892 rt2800_eeprom_write(rt2x00dev
, EEPROM_LED_ACT_CONF
, 0x2221);
6893 rt2800_eeprom_write(rt2x00dev
, EEPROM_LED_POLARITY
, 0xa9f8);
6894 rt2x00_eeprom_dbg(rt2x00dev
, "Led Mode: 0x%04x\n", word
);
6898 * During the LNA validation we are going to use
6899 * lna0 as correct value. Note that EEPROM_LNA
6900 * is never validated.
6902 rt2800_eeprom_read(rt2x00dev
, EEPROM_LNA
, &word
);
6903 default_lna_gain
= rt2x00_get_field16(word
, EEPROM_LNA_A0
);
6905 rt2800_eeprom_read(rt2x00dev
, EEPROM_RSSI_BG
, &word
);
6906 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_BG_OFFSET0
)) > 10)
6907 rt2x00_set_field16(&word
, EEPROM_RSSI_BG_OFFSET0
, 0);
6908 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_BG_OFFSET1
)) > 10)
6909 rt2x00_set_field16(&word
, EEPROM_RSSI_BG_OFFSET1
, 0);
6910 rt2800_eeprom_write(rt2x00dev
, EEPROM_RSSI_BG
, word
);
6912 drv_data
->txmixer_gain_24g
= rt2800_get_txmixer_gain_24g(rt2x00dev
);
6914 rt2800_eeprom_read(rt2x00dev
, EEPROM_RSSI_BG2
, &word
);
6915 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_BG2_OFFSET2
)) > 10)
6916 rt2x00_set_field16(&word
, EEPROM_RSSI_BG2_OFFSET2
, 0);
6917 if (!rt2x00_rt(rt2x00dev
, RT3593
)) {
6918 if (rt2x00_get_field16(word
, EEPROM_RSSI_BG2_LNA_A1
) == 0x00 ||
6919 rt2x00_get_field16(word
, EEPROM_RSSI_BG2_LNA_A1
) == 0xff)
6920 rt2x00_set_field16(&word
, EEPROM_RSSI_BG2_LNA_A1
,
6923 rt2800_eeprom_write(rt2x00dev
, EEPROM_RSSI_BG2
, word
);
6925 drv_data
->txmixer_gain_5g
= rt2800_get_txmixer_gain_5g(rt2x00dev
);
6927 rt2800_eeprom_read(rt2x00dev
, EEPROM_RSSI_A
, &word
);
6928 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_A_OFFSET0
)) > 10)
6929 rt2x00_set_field16(&word
, EEPROM_RSSI_A_OFFSET0
, 0);
6930 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_A_OFFSET1
)) > 10)
6931 rt2x00_set_field16(&word
, EEPROM_RSSI_A_OFFSET1
, 0);
6932 rt2800_eeprom_write(rt2x00dev
, EEPROM_RSSI_A
, word
);
6934 rt2800_eeprom_read(rt2x00dev
, EEPROM_RSSI_A2
, &word
);
6935 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_A2_OFFSET2
)) > 10)
6936 rt2x00_set_field16(&word
, EEPROM_RSSI_A2_OFFSET2
, 0);
6937 if (!rt2x00_rt(rt2x00dev
, RT3593
)) {
6938 if (rt2x00_get_field16(word
, EEPROM_RSSI_A2_LNA_A2
) == 0x00 ||
6939 rt2x00_get_field16(word
, EEPROM_RSSI_A2_LNA_A2
) == 0xff)
6940 rt2x00_set_field16(&word
, EEPROM_RSSI_A2_LNA_A2
,
6943 rt2800_eeprom_write(rt2x00dev
, EEPROM_RSSI_A2
, word
);
6945 if (rt2x00_rt(rt2x00dev
, RT3593
)) {
6946 rt2800_eeprom_read(rt2x00dev
, EEPROM_EXT_LNA2
, &word
);
6947 if (rt2x00_get_field16(word
, EEPROM_EXT_LNA2_A1
) == 0x00 ||
6948 rt2x00_get_field16(word
, EEPROM_EXT_LNA2_A1
) == 0xff)
6949 rt2x00_set_field16(&word
, EEPROM_EXT_LNA2_A1
,
6951 if (rt2x00_get_field16(word
, EEPROM_EXT_LNA2_A2
) == 0x00 ||
6952 rt2x00_get_field16(word
, EEPROM_EXT_LNA2_A2
) == 0xff)
6953 rt2x00_set_field16(&word
, EEPROM_EXT_LNA2_A1
,
6955 rt2800_eeprom_write(rt2x00dev
, EEPROM_EXT_LNA2
, word
);
6961 static int rt2800_init_eeprom(struct rt2x00_dev
*rt2x00dev
)
6968 * Read EEPROM word for configuration.
6970 rt2800_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF0
, &eeprom
);
6973 * Identify RF chipset by EEPROM value
6974 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
6975 * RT53xx: defined in "EEPROM_CHIP_ID" field
6977 if (rt2x00_rt(rt2x00dev
, RT3290
) ||
6978 rt2x00_rt(rt2x00dev
, RT5390
) ||
6979 rt2x00_rt(rt2x00dev
, RT5392
))
6980 rt2800_eeprom_read(rt2x00dev
, EEPROM_CHIP_ID
, &rf
);
6982 rf
= rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_RF_TYPE
);
7006 rt2x00_err(rt2x00dev
, "Invalid RF chipset 0x%04x detected\n",
7011 rt2x00_set_rf(rt2x00dev
, rf
);
7014 * Identify default antenna configuration.
7016 rt2x00dev
->default_ant
.tx_chain_num
=
7017 rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_TXPATH
);
7018 rt2x00dev
->default_ant
.rx_chain_num
=
7019 rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_RXPATH
);
7021 rt2800_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF1
, &eeprom
);
7023 if (rt2x00_rt(rt2x00dev
, RT3070
) ||
7024 rt2x00_rt(rt2x00dev
, RT3090
) ||
7025 rt2x00_rt(rt2x00dev
, RT3352
) ||
7026 rt2x00_rt(rt2x00dev
, RT3390
)) {
7027 value
= rt2x00_get_field16(eeprom
,
7028 EEPROM_NIC_CONF1_ANT_DIVERSITY
);
7033 rt2x00dev
->default_ant
.tx
= ANTENNA_A
;
7034 rt2x00dev
->default_ant
.rx
= ANTENNA_A
;
7037 rt2x00dev
->default_ant
.tx
= ANTENNA_A
;
7038 rt2x00dev
->default_ant
.rx
= ANTENNA_B
;
7042 rt2x00dev
->default_ant
.tx
= ANTENNA_A
;
7043 rt2x00dev
->default_ant
.rx
= ANTENNA_A
;
7046 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390R
)) {
7047 rt2x00dev
->default_ant
.tx
= ANTENNA_HW_DIVERSITY
; /* Unused */
7048 rt2x00dev
->default_ant
.rx
= ANTENNA_HW_DIVERSITY
; /* Unused */
7052 * Determine external LNA informations.
7054 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G
))
7055 __set_bit(CAPABILITY_EXTERNAL_LNA_A
, &rt2x00dev
->cap_flags
);
7056 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G
))
7057 __set_bit(CAPABILITY_EXTERNAL_LNA_BG
, &rt2x00dev
->cap_flags
);
7060 * Detect if this device has an hardware controlled radio.
7062 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF1_HW_RADIO
))
7063 __set_bit(CAPABILITY_HW_BUTTON
, &rt2x00dev
->cap_flags
);
7066 * Detect if this device has Bluetooth co-existence.
7068 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF1_BT_COEXIST
))
7069 __set_bit(CAPABILITY_BT_COEXIST
, &rt2x00dev
->cap_flags
);
7072 * Read frequency offset and RF programming sequence.
7074 rt2800_eeprom_read(rt2x00dev
, EEPROM_FREQ
, &eeprom
);
7075 rt2x00dev
->freq_offset
= rt2x00_get_field16(eeprom
, EEPROM_FREQ_OFFSET
);
7078 * Store led settings, for correct led behaviour.
7080 #ifdef CONFIG_RT2X00_LIB_LEDS
7081 rt2800_init_led(rt2x00dev
, &rt2x00dev
->led_radio
, LED_TYPE_RADIO
);
7082 rt2800_init_led(rt2x00dev
, &rt2x00dev
->led_assoc
, LED_TYPE_ASSOC
);
7083 rt2800_init_led(rt2x00dev
, &rt2x00dev
->led_qual
, LED_TYPE_QUALITY
);
7085 rt2x00dev
->led_mcu_reg
= eeprom
;
7086 #endif /* CONFIG_RT2X00_LIB_LEDS */
7089 * Check if support EIRP tx power limit feature.
7091 rt2800_eeprom_read(rt2x00dev
, EEPROM_EIRP_MAX_TX_POWER
, &eeprom
);
7093 if (rt2x00_get_field16(eeprom
, EEPROM_EIRP_MAX_TX_POWER_2GHZ
) <
7094 EIRP_MAX_TX_POWER_LIMIT
)
7095 __set_bit(CAPABILITY_POWER_LIMIT
, &rt2x00dev
->cap_flags
);
7101 * RF value list for rt28xx
7102 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
7104 static const struct rf_channel rf_vals
[] = {
7105 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
7106 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
7107 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
7108 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
7109 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
7110 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
7111 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
7112 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
7113 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
7114 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
7115 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
7116 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
7117 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
7118 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
7120 /* 802.11 UNI / HyperLan 2 */
7121 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
7122 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
7123 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
7124 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
7125 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
7126 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
7127 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
7128 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
7129 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
7130 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
7131 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
7132 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
7134 /* 802.11 HyperLan 2 */
7135 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
7136 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
7137 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
7138 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
7139 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
7140 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
7141 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
7142 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
7143 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
7144 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
7145 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
7146 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
7147 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
7148 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
7149 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
7150 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
7153 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
7154 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
7155 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
7156 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
7157 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
7158 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
7159 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
7160 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
7161 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
7162 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
7163 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
7166 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
7167 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
7168 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
7169 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
7170 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
7171 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
7172 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
7176 * RF value list for rt3xxx
7177 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
7179 static const struct rf_channel rf_vals_3x
[] = {
7195 /* 802.11 UNI / HyperLan 2 */
7209 /* 802.11 HyperLan 2 */
7241 static const struct rf_channel rf_vals_5592_xtal20
[] = {
7242 /* Channel, N, K, mod, R */
7252 {10, 491, 4, 10, 3},
7253 {11, 492, 4, 10, 3},
7254 {12, 493, 4, 10, 3},
7255 {13, 494, 4, 10, 3},
7256 {14, 496, 8, 10, 3},
7257 {36, 172, 8, 12, 1},
7258 {38, 173, 0, 12, 1},
7259 {40, 173, 4, 12, 1},
7260 {42, 173, 8, 12, 1},
7261 {44, 174, 0, 12, 1},
7262 {46, 174, 4, 12, 1},
7263 {48, 174, 8, 12, 1},
7264 {50, 175, 0, 12, 1},
7265 {52, 175, 4, 12, 1},
7266 {54, 175, 8, 12, 1},
7267 {56, 176, 0, 12, 1},
7268 {58, 176, 4, 12, 1},
7269 {60, 176, 8, 12, 1},
7270 {62, 177, 0, 12, 1},
7271 {64, 177, 4, 12, 1},
7272 {100, 183, 4, 12, 1},
7273 {102, 183, 8, 12, 1},
7274 {104, 184, 0, 12, 1},
7275 {106, 184, 4, 12, 1},
7276 {108, 184, 8, 12, 1},
7277 {110, 185, 0, 12, 1},
7278 {112, 185, 4, 12, 1},
7279 {114, 185, 8, 12, 1},
7280 {116, 186, 0, 12, 1},
7281 {118, 186, 4, 12, 1},
7282 {120, 186, 8, 12, 1},
7283 {122, 187, 0, 12, 1},
7284 {124, 187, 4, 12, 1},
7285 {126, 187, 8, 12, 1},
7286 {128, 188, 0, 12, 1},
7287 {130, 188, 4, 12, 1},
7288 {132, 188, 8, 12, 1},
7289 {134, 189, 0, 12, 1},
7290 {136, 189, 4, 12, 1},
7291 {138, 189, 8, 12, 1},
7292 {140, 190, 0, 12, 1},
7293 {149, 191, 6, 12, 1},
7294 {151, 191, 10, 12, 1},
7295 {153, 192, 2, 12, 1},
7296 {155, 192, 6, 12, 1},
7297 {157, 192, 10, 12, 1},
7298 {159, 193, 2, 12, 1},
7299 {161, 193, 6, 12, 1},
7300 {165, 194, 2, 12, 1},
7301 {184, 164, 0, 12, 1},
7302 {188, 164, 4, 12, 1},
7303 {192, 165, 8, 12, 1},
7304 {196, 166, 0, 12, 1},
7307 static const struct rf_channel rf_vals_5592_xtal40
[] = {
7308 /* Channel, N, K, mod, R */
7318 {10, 245, 7, 10, 3},
7319 {11, 246, 2, 10, 3},
7320 {12, 246, 7, 10, 3},
7321 {13, 247, 2, 10, 3},
7322 {14, 248, 4, 10, 3},
7326 {42, 86, 10, 12, 1},
7332 {54, 87, 10, 12, 1},
7338 {100, 91, 8, 12, 1},
7339 {102, 91, 10, 12, 1},
7340 {104, 92, 0, 12, 1},
7341 {106, 92, 2, 12, 1},
7342 {108, 92, 4, 12, 1},
7343 {110, 92, 6, 12, 1},
7344 {112, 92, 8, 12, 1},
7345 {114, 92, 10, 12, 1},
7346 {116, 93, 0, 12, 1},
7347 {118, 93, 2, 12, 1},
7348 {120, 93, 4, 12, 1},
7349 {122, 93, 6, 12, 1},
7350 {124, 93, 8, 12, 1},
7351 {126, 93, 10, 12, 1},
7352 {128, 94, 0, 12, 1},
7353 {130, 94, 2, 12, 1},
7354 {132, 94, 4, 12, 1},
7355 {134, 94, 6, 12, 1},
7356 {136, 94, 8, 12, 1},
7357 {138, 94, 10, 12, 1},
7358 {140, 95, 0, 12, 1},
7359 {149, 95, 9, 12, 1},
7360 {151, 95, 11, 12, 1},
7361 {153, 96, 1, 12, 1},
7362 {155, 96, 3, 12, 1},
7363 {157, 96, 5, 12, 1},
7364 {159, 96, 7, 12, 1},
7365 {161, 96, 9, 12, 1},
7366 {165, 97, 1, 12, 1},
7367 {184, 82, 0, 12, 1},
7368 {188, 82, 4, 12, 1},
7369 {192, 82, 8, 12, 1},
7370 {196, 83, 0, 12, 1},
7373 static const struct rf_channel rf_vals_3053
[] = {
7374 /* Channel, N, R, K */
7410 /* NOTE: Channel 114 has been removed intentionally.
7411 * The EEPROM contains no TX power values for that,
7412 * and it is disabled in the vendor driver as well.
7439 static int rt2800_probe_hw_mode(struct rt2x00_dev
*rt2x00dev
)
7441 struct hw_mode_spec
*spec
= &rt2x00dev
->spec
;
7442 struct channel_info
*info
;
7443 char *default_power1
;
7444 char *default_power2
;
7445 char *default_power3
;
7451 * Disable powersaving as default on PCI devices.
7453 if (rt2x00_is_pci(rt2x00dev
) || rt2x00_is_soc(rt2x00dev
))
7454 rt2x00dev
->hw
->wiphy
->flags
&= ~WIPHY_FLAG_PS_ON_BY_DEFAULT
;
7457 * Initialize all hw fields.
7459 rt2x00dev
->hw
->flags
=
7460 IEEE80211_HW_SIGNAL_DBM
|
7461 IEEE80211_HW_SUPPORTS_PS
|
7462 IEEE80211_HW_PS_NULLFUNC_STACK
|
7463 IEEE80211_HW_AMPDU_AGGREGATION
|
7464 IEEE80211_HW_REPORTS_TX_ACK_STATUS
;
7467 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
7468 * unless we are capable of sending the buffered frames out after the
7469 * DTIM transmission using rt2x00lib_beacondone. This will send out
7470 * multicast and broadcast traffic immediately instead of buffering it
7471 * infinitly and thus dropping it after some time.
7473 if (!rt2x00_is_usb(rt2x00dev
))
7474 rt2x00dev
->hw
->flags
|=
7475 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING
;
7477 SET_IEEE80211_DEV(rt2x00dev
->hw
, rt2x00dev
->dev
);
7478 SET_IEEE80211_PERM_ADDR(rt2x00dev
->hw
,
7479 rt2800_eeprom_addr(rt2x00dev
,
7480 EEPROM_MAC_ADDR_0
));
7483 * As rt2800 has a global fallback table we cannot specify
7484 * more then one tx rate per frame but since the hw will
7485 * try several rates (based on the fallback table) we should
7486 * initialize max_report_rates to the maximum number of rates
7487 * we are going to try. Otherwise mac80211 will truncate our
7488 * reported tx rates and the rc algortihm will end up with
7491 rt2x00dev
->hw
->max_rates
= 1;
7492 rt2x00dev
->hw
->max_report_rates
= 7;
7493 rt2x00dev
->hw
->max_rate_tries
= 1;
7495 rt2800_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF0
, &eeprom
);
7498 * Initialize hw_mode information.
7500 spec
->supported_bands
= SUPPORT_BAND_2GHZ
;
7501 spec
->supported_rates
= SUPPORT_RATE_CCK
| SUPPORT_RATE_OFDM
;
7503 if (rt2x00_rf(rt2x00dev
, RF2820
) ||
7504 rt2x00_rf(rt2x00dev
, RF2720
)) {
7505 spec
->num_channels
= 14;
7506 spec
->channels
= rf_vals
;
7507 } else if (rt2x00_rf(rt2x00dev
, RF2850
) ||
7508 rt2x00_rf(rt2x00dev
, RF2750
)) {
7509 spec
->supported_bands
|= SUPPORT_BAND_5GHZ
;
7510 spec
->num_channels
= ARRAY_SIZE(rf_vals
);
7511 spec
->channels
= rf_vals
;
7512 } else if (rt2x00_rf(rt2x00dev
, RF3020
) ||
7513 rt2x00_rf(rt2x00dev
, RF2020
) ||
7514 rt2x00_rf(rt2x00dev
, RF3021
) ||
7515 rt2x00_rf(rt2x00dev
, RF3022
) ||
7516 rt2x00_rf(rt2x00dev
, RF3290
) ||
7517 rt2x00_rf(rt2x00dev
, RF3320
) ||
7518 rt2x00_rf(rt2x00dev
, RF3322
) ||
7519 rt2x00_rf(rt2x00dev
, RF5360
) ||
7520 rt2x00_rf(rt2x00dev
, RF5370
) ||
7521 rt2x00_rf(rt2x00dev
, RF5372
) ||
7522 rt2x00_rf(rt2x00dev
, RF5390
) ||
7523 rt2x00_rf(rt2x00dev
, RF5392
)) {
7524 spec
->num_channels
= 14;
7525 spec
->channels
= rf_vals_3x
;
7526 } else if (rt2x00_rf(rt2x00dev
, RF3052
)) {
7527 spec
->supported_bands
|= SUPPORT_BAND_5GHZ
;
7528 spec
->num_channels
= ARRAY_SIZE(rf_vals_3x
);
7529 spec
->channels
= rf_vals_3x
;
7530 } else if (rt2x00_rf(rt2x00dev
, RF3053
)) {
7531 spec
->supported_bands
|= SUPPORT_BAND_5GHZ
;
7532 spec
->num_channels
= ARRAY_SIZE(rf_vals_3053
);
7533 spec
->channels
= rf_vals_3053
;
7534 } else if (rt2x00_rf(rt2x00dev
, RF5592
)) {
7535 spec
->supported_bands
|= SUPPORT_BAND_5GHZ
;
7537 rt2800_register_read(rt2x00dev
, MAC_DEBUG_INDEX
, ®
);
7538 if (rt2x00_get_field32(reg
, MAC_DEBUG_INDEX_XTAL
)) {
7539 spec
->num_channels
= ARRAY_SIZE(rf_vals_5592_xtal40
);
7540 spec
->channels
= rf_vals_5592_xtal40
;
7542 spec
->num_channels
= ARRAY_SIZE(rf_vals_5592_xtal20
);
7543 spec
->channels
= rf_vals_5592_xtal20
;
7547 if (WARN_ON_ONCE(!spec
->channels
))
7551 * Initialize HT information.
7553 if (!rt2x00_rf(rt2x00dev
, RF2020
))
7554 spec
->ht
.ht_supported
= true;
7556 spec
->ht
.ht_supported
= false;
7559 IEEE80211_HT_CAP_SUP_WIDTH_20_40
|
7560 IEEE80211_HT_CAP_GRN_FLD
|
7561 IEEE80211_HT_CAP_SGI_20
|
7562 IEEE80211_HT_CAP_SGI_40
;
7564 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_TXPATH
) >= 2)
7565 spec
->ht
.cap
|= IEEE80211_HT_CAP_TX_STBC
;
7568 rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_RXPATH
) <<
7569 IEEE80211_HT_CAP_RX_STBC_SHIFT
;
7571 spec
->ht
.ampdu_factor
= 3;
7572 spec
->ht
.ampdu_density
= 4;
7573 spec
->ht
.mcs
.tx_params
=
7574 IEEE80211_HT_MCS_TX_DEFINED
|
7575 IEEE80211_HT_MCS_TX_RX_DIFF
|
7576 ((rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_TXPATH
) - 1) <<
7577 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT
);
7579 switch (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_RXPATH
)) {
7581 spec
->ht
.mcs
.rx_mask
[2] = 0xff;
7583 spec
->ht
.mcs
.rx_mask
[1] = 0xff;
7585 spec
->ht
.mcs
.rx_mask
[0] = 0xff;
7586 spec
->ht
.mcs
.rx_mask
[4] = 0x1; /* MCS32 */
7591 * Create channel information array
7593 info
= kcalloc(spec
->num_channels
, sizeof(*info
), GFP_KERNEL
);
7597 spec
->channels_info
= info
;
7599 default_power1
= rt2800_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_BG1
);
7600 default_power2
= rt2800_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_BG2
);
7602 if (rt2x00dev
->default_ant
.tx_chain_num
> 2)
7603 default_power3
= rt2800_eeprom_addr(rt2x00dev
,
7604 EEPROM_EXT_TXPOWER_BG3
);
7606 default_power3
= NULL
;
7608 for (i
= 0; i
< 14; i
++) {
7609 info
[i
].default_power1
= default_power1
[i
];
7610 info
[i
].default_power2
= default_power2
[i
];
7612 info
[i
].default_power3
= default_power3
[i
];
7615 if (spec
->num_channels
> 14) {
7616 default_power1
= rt2800_eeprom_addr(rt2x00dev
,
7618 default_power2
= rt2800_eeprom_addr(rt2x00dev
,
7621 if (rt2x00dev
->default_ant
.tx_chain_num
> 2)
7623 rt2800_eeprom_addr(rt2x00dev
,
7624 EEPROM_EXT_TXPOWER_A3
);
7626 default_power3
= NULL
;
7628 for (i
= 14; i
< spec
->num_channels
; i
++) {
7629 info
[i
].default_power1
= default_power1
[i
- 14];
7630 info
[i
].default_power2
= default_power2
[i
- 14];
7632 info
[i
].default_power3
= default_power3
[i
- 14];
7636 switch (rt2x00dev
->chip
.rf
) {
7650 __set_bit(CAPABILITY_VCO_RECALIBRATION
, &rt2x00dev
->cap_flags
);
7657 static int rt2800_probe_rt(struct rt2x00_dev
*rt2x00dev
)
7663 if (rt2x00_rt(rt2x00dev
, RT3290
))
7664 rt2800_register_read(rt2x00dev
, MAC_CSR0_3290
, ®
);
7666 rt2800_register_read(rt2x00dev
, MAC_CSR0
, ®
);
7668 rt
= rt2x00_get_field32(reg
, MAC_CSR0_CHIPSET
);
7669 rev
= rt2x00_get_field32(reg
, MAC_CSR0_REVISION
);
7688 rt2x00_err(rt2x00dev
, "Invalid RT chipset 0x%04x, rev %04x detected\n",
7693 rt2x00_set_rt(rt2x00dev
, rt
, rev
);
7698 int rt2800_probe_hw(struct rt2x00_dev
*rt2x00dev
)
7703 retval
= rt2800_probe_rt(rt2x00dev
);
7708 * Allocate eeprom data.
7710 retval
= rt2800_validate_eeprom(rt2x00dev
);
7714 retval
= rt2800_init_eeprom(rt2x00dev
);
7719 * Enable rfkill polling by setting GPIO direction of the
7720 * rfkill switch GPIO pin correctly.
7722 rt2800_register_read(rt2x00dev
, GPIO_CTRL
, ®
);
7723 rt2x00_set_field32(®
, GPIO_CTRL_DIR2
, 1);
7724 rt2800_register_write(rt2x00dev
, GPIO_CTRL
, reg
);
7727 * Initialize hw specifications.
7729 retval
= rt2800_probe_hw_mode(rt2x00dev
);
7734 * Set device capabilities.
7736 __set_bit(CAPABILITY_CONTROL_FILTERS
, &rt2x00dev
->cap_flags
);
7737 __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL
, &rt2x00dev
->cap_flags
);
7738 if (!rt2x00_is_usb(rt2x00dev
))
7739 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT
, &rt2x00dev
->cap_flags
);
7742 * Set device requirements.
7744 if (!rt2x00_is_soc(rt2x00dev
))
7745 __set_bit(REQUIRE_FIRMWARE
, &rt2x00dev
->cap_flags
);
7746 __set_bit(REQUIRE_L2PAD
, &rt2x00dev
->cap_flags
);
7747 __set_bit(REQUIRE_TXSTATUS_FIFO
, &rt2x00dev
->cap_flags
);
7748 if (!rt2800_hwcrypt_disabled(rt2x00dev
))
7749 __set_bit(CAPABILITY_HW_CRYPTO
, &rt2x00dev
->cap_flags
);
7750 __set_bit(CAPABILITY_LINK_TUNING
, &rt2x00dev
->cap_flags
);
7751 __set_bit(REQUIRE_HT_TX_DESC
, &rt2x00dev
->cap_flags
);
7752 if (rt2x00_is_usb(rt2x00dev
))
7753 __set_bit(REQUIRE_PS_AUTOWAKE
, &rt2x00dev
->cap_flags
);
7755 __set_bit(REQUIRE_DMA
, &rt2x00dev
->cap_flags
);
7756 __set_bit(REQUIRE_TASKLET_CONTEXT
, &rt2x00dev
->cap_flags
);
7760 * Set the rssi offset.
7762 rt2x00dev
->rssi_offset
= DEFAULT_RSSI_OFFSET
;
7766 EXPORT_SYMBOL_GPL(rt2800_probe_hw
);
7769 * IEEE80211 stack callback functions.
7771 void rt2800_get_tkip_seq(struct ieee80211_hw
*hw
, u8 hw_key_idx
, u32
*iv32
,
7774 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
7775 struct mac_iveiv_entry iveiv_entry
;
7778 offset
= MAC_IVEIV_ENTRY(hw_key_idx
);
7779 rt2800_register_multiread(rt2x00dev
, offset
,
7780 &iveiv_entry
, sizeof(iveiv_entry
));
7782 memcpy(iv16
, &iveiv_entry
.iv
[0], sizeof(*iv16
));
7783 memcpy(iv32
, &iveiv_entry
.iv
[4], sizeof(*iv32
));
7785 EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq
);
7787 int rt2800_set_rts_threshold(struct ieee80211_hw
*hw
, u32 value
)
7789 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
7791 bool enabled
= (value
< IEEE80211_MAX_RTS_THRESHOLD
);
7793 rt2800_register_read(rt2x00dev
, TX_RTS_CFG
, ®
);
7794 rt2x00_set_field32(®
, TX_RTS_CFG_RTS_THRES
, value
);
7795 rt2800_register_write(rt2x00dev
, TX_RTS_CFG
, reg
);
7797 rt2800_register_read(rt2x00dev
, CCK_PROT_CFG
, ®
);
7798 rt2x00_set_field32(®
, CCK_PROT_CFG_RTS_TH_EN
, enabled
);
7799 rt2800_register_write(rt2x00dev
, CCK_PROT_CFG
, reg
);
7801 rt2800_register_read(rt2x00dev
, OFDM_PROT_CFG
, ®
);
7802 rt2x00_set_field32(®
, OFDM_PROT_CFG_RTS_TH_EN
, enabled
);
7803 rt2800_register_write(rt2x00dev
, OFDM_PROT_CFG
, reg
);
7805 rt2800_register_read(rt2x00dev
, MM20_PROT_CFG
, ®
);
7806 rt2x00_set_field32(®
, MM20_PROT_CFG_RTS_TH_EN
, enabled
);
7807 rt2800_register_write(rt2x00dev
, MM20_PROT_CFG
, reg
);
7809 rt2800_register_read(rt2x00dev
, MM40_PROT_CFG
, ®
);
7810 rt2x00_set_field32(®
, MM40_PROT_CFG_RTS_TH_EN
, enabled
);
7811 rt2800_register_write(rt2x00dev
, MM40_PROT_CFG
, reg
);
7813 rt2800_register_read(rt2x00dev
, GF20_PROT_CFG
, ®
);
7814 rt2x00_set_field32(®
, GF20_PROT_CFG_RTS_TH_EN
, enabled
);
7815 rt2800_register_write(rt2x00dev
, GF20_PROT_CFG
, reg
);
7817 rt2800_register_read(rt2x00dev
, GF40_PROT_CFG
, ®
);
7818 rt2x00_set_field32(®
, GF40_PROT_CFG_RTS_TH_EN
, enabled
);
7819 rt2800_register_write(rt2x00dev
, GF40_PROT_CFG
, reg
);
7823 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold
);
7825 int rt2800_conf_tx(struct ieee80211_hw
*hw
,
7826 struct ieee80211_vif
*vif
, u16 queue_idx
,
7827 const struct ieee80211_tx_queue_params
*params
)
7829 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
7830 struct data_queue
*queue
;
7831 struct rt2x00_field32 field
;
7837 * First pass the configuration through rt2x00lib, that will
7838 * update the queue settings and validate the input. After that
7839 * we are free to update the registers based on the value
7840 * in the queue parameter.
7842 retval
= rt2x00mac_conf_tx(hw
, vif
, queue_idx
, params
);
7847 * We only need to perform additional register initialization
7853 queue
= rt2x00queue_get_tx_queue(rt2x00dev
, queue_idx
);
7855 /* Update WMM TXOP register */
7856 offset
= WMM_TXOP0_CFG
+ (sizeof(u32
) * (!!(queue_idx
& 2)));
7857 field
.bit_offset
= (queue_idx
& 1) * 16;
7858 field
.bit_mask
= 0xffff << field
.bit_offset
;
7860 rt2800_register_read(rt2x00dev
, offset
, ®
);
7861 rt2x00_set_field32(®
, field
, queue
->txop
);
7862 rt2800_register_write(rt2x00dev
, offset
, reg
);
7864 /* Update WMM registers */
7865 field
.bit_offset
= queue_idx
* 4;
7866 field
.bit_mask
= 0xf << field
.bit_offset
;
7868 rt2800_register_read(rt2x00dev
, WMM_AIFSN_CFG
, ®
);
7869 rt2x00_set_field32(®
, field
, queue
->aifs
);
7870 rt2800_register_write(rt2x00dev
, WMM_AIFSN_CFG
, reg
);
7872 rt2800_register_read(rt2x00dev
, WMM_CWMIN_CFG
, ®
);
7873 rt2x00_set_field32(®
, field
, queue
->cw_min
);
7874 rt2800_register_write(rt2x00dev
, WMM_CWMIN_CFG
, reg
);
7876 rt2800_register_read(rt2x00dev
, WMM_CWMAX_CFG
, ®
);
7877 rt2x00_set_field32(®
, field
, queue
->cw_max
);
7878 rt2800_register_write(rt2x00dev
, WMM_CWMAX_CFG
, reg
);
7880 /* Update EDCA registers */
7881 offset
= EDCA_AC0_CFG
+ (sizeof(u32
) * queue_idx
);
7883 rt2800_register_read(rt2x00dev
, offset
, ®
);
7884 rt2x00_set_field32(®
, EDCA_AC0_CFG_TX_OP
, queue
->txop
);
7885 rt2x00_set_field32(®
, EDCA_AC0_CFG_AIFSN
, queue
->aifs
);
7886 rt2x00_set_field32(®
, EDCA_AC0_CFG_CWMIN
, queue
->cw_min
);
7887 rt2x00_set_field32(®
, EDCA_AC0_CFG_CWMAX
, queue
->cw_max
);
7888 rt2800_register_write(rt2x00dev
, offset
, reg
);
7892 EXPORT_SYMBOL_GPL(rt2800_conf_tx
);
7894 u64
rt2800_get_tsf(struct ieee80211_hw
*hw
, struct ieee80211_vif
*vif
)
7896 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
7900 rt2800_register_read(rt2x00dev
, TSF_TIMER_DW1
, ®
);
7901 tsf
= (u64
) rt2x00_get_field32(reg
, TSF_TIMER_DW1_HIGH_WORD
) << 32;
7902 rt2800_register_read(rt2x00dev
, TSF_TIMER_DW0
, ®
);
7903 tsf
|= rt2x00_get_field32(reg
, TSF_TIMER_DW0_LOW_WORD
);
7907 EXPORT_SYMBOL_GPL(rt2800_get_tsf
);
7909 int rt2800_ampdu_action(struct ieee80211_hw
*hw
, struct ieee80211_vif
*vif
,
7910 enum ieee80211_ampdu_mlme_action action
,
7911 struct ieee80211_sta
*sta
, u16 tid
, u16
*ssn
,
7914 struct rt2x00_sta
*sta_priv
= (struct rt2x00_sta
*)sta
->drv_priv
;
7918 * Don't allow aggregation for stations the hardware isn't aware
7919 * of because tx status reports for frames to an unknown station
7920 * always contain wcid=255 and thus we can't distinguish between
7921 * multiple stations which leads to unwanted situations when the
7922 * hw reorders frames due to aggregation.
7924 if (sta_priv
->wcid
< 0)
7928 case IEEE80211_AMPDU_RX_START
:
7929 case IEEE80211_AMPDU_RX_STOP
:
7931 * The hw itself takes care of setting up BlockAck mechanisms.
7932 * So, we only have to allow mac80211 to nagotiate a BlockAck
7933 * agreement. Once that is done, the hw will BlockAck incoming
7934 * AMPDUs without further setup.
7937 case IEEE80211_AMPDU_TX_START
:
7938 ieee80211_start_tx_ba_cb_irqsafe(vif
, sta
->addr
, tid
);
7940 case IEEE80211_AMPDU_TX_STOP_CONT
:
7941 case IEEE80211_AMPDU_TX_STOP_FLUSH
:
7942 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT
:
7943 ieee80211_stop_tx_ba_cb_irqsafe(vif
, sta
->addr
, tid
);
7945 case IEEE80211_AMPDU_TX_OPERATIONAL
:
7948 rt2x00_warn((struct rt2x00_dev
*)hw
->priv
,
7949 "Unknown AMPDU action\n");
7954 EXPORT_SYMBOL_GPL(rt2800_ampdu_action
);
7956 int rt2800_get_survey(struct ieee80211_hw
*hw
, int idx
,
7957 struct survey_info
*survey
)
7959 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
7960 struct ieee80211_conf
*conf
= &hw
->conf
;
7961 u32 idle
, busy
, busy_ext
;
7966 survey
->channel
= conf
->chandef
.chan
;
7968 rt2800_register_read(rt2x00dev
, CH_IDLE_STA
, &idle
);
7969 rt2800_register_read(rt2x00dev
, CH_BUSY_STA
, &busy
);
7970 rt2800_register_read(rt2x00dev
, CH_BUSY_STA_SEC
, &busy_ext
);
7973 survey
->filled
= SURVEY_INFO_CHANNEL_TIME
|
7974 SURVEY_INFO_CHANNEL_TIME_BUSY
|
7975 SURVEY_INFO_CHANNEL_TIME_EXT_BUSY
;
7977 survey
->channel_time
= (idle
+ busy
) / 1000;
7978 survey
->channel_time_busy
= busy
/ 1000;
7979 survey
->channel_time_ext_busy
= busy_ext
/ 1000;
7982 if (!(hw
->conf
.flags
& IEEE80211_CONF_OFFCHANNEL
))
7983 survey
->filled
|= SURVEY_INFO_IN_USE
;
7988 EXPORT_SYMBOL_GPL(rt2800_get_survey
);
7990 MODULE_AUTHOR(DRV_PROJECT
", Bartlomiej Zolnierkiewicz");
7991 MODULE_VERSION(DRV_VERSION
);
7992 MODULE_DESCRIPTION("Ralink RT2800 library");
7993 MODULE_LICENSE("GPL");