projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
rt2x00: rt2800lib: fix BBP1_TX_ANTENNA field configuration for 3T devices
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt2800lib.c
1 /*
2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
3 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
4 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
5 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
6
7 Based on the original rt2800pci.c and rt2800usb.c.
8 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
9 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
10 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
11 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
12 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
13 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
14 <http://rt2x00.serialmonkey.com>
15
16 This program is free software; you can redistribute it and/or modify
17 it under the terms of the GNU General Public License as published by
18 the Free Software Foundation; either version 2 of the License, or
19 (at your option) any later version.
20
21 This program is distributed in the hope that it will be useful,
22 but WITHOUT ANY WARRANTY; without even the implied warranty of
23 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 GNU General Public License for more details.
25
26 You should have received a copy of the GNU General Public License
27 along with this program; if not, write to the
28 Free Software Foundation, Inc.,
29 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32 /*
33 Module: rt2800lib
34 Abstract: rt2800 generic device routines.
35 */
36
37 #include <linux/crc-ccitt.h>
38 #include <linux/kernel.h>
39 #include <linux/module.h>
40 #include <linux/slab.h>
41
42 #include "rt2x00.h"
43 #include "rt2800lib.h"
44 #include "rt2800.h"
45
46 /*
47 * Register access.
48 * All access to the CSR registers will go through the methods
49 * rt2800_register_read and rt2800_register_write.
50 * BBP and RF register require indirect register access,
51 * and use the CSR registers BBPCSR and RFCSR to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
55 * between each attampt. When the busy bit is still set at that time,
56 * the access attempt is considered to have failed,
57 * and we will print an error.
58 * The _lock versions must be used if you already hold the csr_mutex
59 */
60 #define WAIT_FOR_BBP(__dev, __reg) \
61 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
62 #define WAIT_FOR_RFCSR(__dev, __reg) \
63 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
64 #define WAIT_FOR_RF(__dev, __reg) \
65 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
66 #define WAIT_FOR_MCU(__dev, __reg) \
67 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
68 H2M_MAILBOX_CSR_OWNER, (__reg))
69
70 static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
71 {
72 /* check for rt2872 on SoC */
73 if (!rt2x00_is_soc(rt2x00dev) ||
74 !rt2x00_rt(rt2x00dev, RT2872))
75 return false;
76
77 /* we know for sure that these rf chipsets are used on rt305x boards */
78 if (rt2x00_rf(rt2x00dev, RF3020) ||
79 rt2x00_rf(rt2x00dev, RF3021) ||
80 rt2x00_rf(rt2x00dev, RF3022))
81 return true;
82
83 rt2x00_warn(rt2x00dev, "Unknown RF chipset on rt305x\n");
84 return false;
85 }
86
87 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
88 const unsigned int word, const u8 value)
89 {
90 u32 reg;
91
92 mutex_lock(&rt2x00dev->csr_mutex);
93
94 /*
95 * Wait until the BBP becomes available, afterwards we
96 * can safely write the new data into the register.
97 */
98 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
99 reg = 0;
100 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
101 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
102 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
103 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
104 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
105
106 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
107 }
108
109 mutex_unlock(&rt2x00dev->csr_mutex);
110 }
111
112 static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
113 const unsigned int word, u8 *value)
114 {
115 u32 reg;
116
117 mutex_lock(&rt2x00dev->csr_mutex);
118
119 /*
120 * Wait until the BBP becomes available, afterwards we
121 * can safely write the read request into the register.
122 * After the data has been written, we wait until hardware
123 * returns the correct value, if at any time the register
124 * doesn't become available in time, reg will be 0xffffffff
125 * which means we return 0xff to the caller.
126 */
127 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
128 reg = 0;
129 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
130 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
131 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
132 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
133
134 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
135
136 WAIT_FOR_BBP(rt2x00dev, &reg);
137 }
138
139 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
140
141 mutex_unlock(&rt2x00dev->csr_mutex);
142 }
143
144 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
145 const unsigned int word, const u8 value)
146 {
147 u32 reg;
148
149 mutex_lock(&rt2x00dev->csr_mutex);
150
151 /*
152 * Wait until the RFCSR becomes available, afterwards we
153 * can safely write the new data into the register.
154 */
155 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
156 reg = 0;
157 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
158 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
159 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
160 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
161
162 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
163 }
164
165 mutex_unlock(&rt2x00dev->csr_mutex);
166 }
167
168 static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
169 const unsigned int word, u8 *value)
170 {
171 u32 reg;
172
173 mutex_lock(&rt2x00dev->csr_mutex);
174
175 /*
176 * Wait until the RFCSR becomes available, afterwards we
177 * can safely write the read request into the register.
178 * After the data has been written, we wait until hardware
179 * returns the correct value, if at any time the register
180 * doesn't become available in time, reg will be 0xffffffff
181 * which means we return 0xff to the caller.
182 */
183 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
184 reg = 0;
185 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
186 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
187 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
188
189 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
190
191 WAIT_FOR_RFCSR(rt2x00dev, &reg);
192 }
193
194 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
195
196 mutex_unlock(&rt2x00dev->csr_mutex);
197 }
198
199 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
200 const unsigned int word, const u32 value)
201 {
202 u32 reg;
203
204 mutex_lock(&rt2x00dev->csr_mutex);
205
206 /*
207 * Wait until the RF becomes available, afterwards we
208 * can safely write the new data into the register.
209 */
210 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
211 reg = 0;
212 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
213 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
214 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
215 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
216
217 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
218 rt2x00_rf_write(rt2x00dev, word, value);
219 }
220
221 mutex_unlock(&rt2x00dev->csr_mutex);
222 }
223
224 static const unsigned int rt2800_eeprom_map[EEPROM_WORD_COUNT] = {
225 [EEPROM_CHIP_ID] = 0x0000,
226 [EEPROM_VERSION] = 0x0001,
227 [EEPROM_MAC_ADDR_0] = 0x0002,
228 [EEPROM_MAC_ADDR_1] = 0x0003,
229 [EEPROM_MAC_ADDR_2] = 0x0004,
230 [EEPROM_NIC_CONF0] = 0x001a,
231 [EEPROM_NIC_CONF1] = 0x001b,
232 [EEPROM_FREQ] = 0x001d,
233 [EEPROM_LED_AG_CONF] = 0x001e,
234 [EEPROM_LED_ACT_CONF] = 0x001f,
235 [EEPROM_LED_POLARITY] = 0x0020,
236 [EEPROM_NIC_CONF2] = 0x0021,
237 [EEPROM_LNA] = 0x0022,
238 [EEPROM_RSSI_BG] = 0x0023,
239 [EEPROM_RSSI_BG2] = 0x0024,
240 [EEPROM_TXMIXER_GAIN_BG] = 0x0024, /* overlaps with RSSI_BG2 */
241 [EEPROM_RSSI_A] = 0x0025,
242 [EEPROM_RSSI_A2] = 0x0026,
243 [EEPROM_TXMIXER_GAIN_A] = 0x0026, /* overlaps with RSSI_A2 */
244 [EEPROM_EIRP_MAX_TX_POWER] = 0x0027,
245 [EEPROM_TXPOWER_DELTA] = 0x0028,
246 [EEPROM_TXPOWER_BG1] = 0x0029,
247 [EEPROM_TXPOWER_BG2] = 0x0030,
248 [EEPROM_TSSI_BOUND_BG1] = 0x0037,
249 [EEPROM_TSSI_BOUND_BG2] = 0x0038,
250 [EEPROM_TSSI_BOUND_BG3] = 0x0039,
251 [EEPROM_TSSI_BOUND_BG4] = 0x003a,
252 [EEPROM_TSSI_BOUND_BG5] = 0x003b,
253 [EEPROM_TXPOWER_A1] = 0x003c,
254 [EEPROM_TXPOWER_A2] = 0x0053,
255 [EEPROM_TSSI_BOUND_A1] = 0x006a,
256 [EEPROM_TSSI_BOUND_A2] = 0x006b,
257 [EEPROM_TSSI_BOUND_A3] = 0x006c,
258 [EEPROM_TSSI_BOUND_A4] = 0x006d,
259 [EEPROM_TSSI_BOUND_A5] = 0x006e,
260 [EEPROM_TXPOWER_BYRATE] = 0x006f,
261 [EEPROM_BBP_START] = 0x0078,
262 };
263
264 static const unsigned int rt2800_eeprom_map_ext[EEPROM_WORD_COUNT] = {
265 [EEPROM_CHIP_ID] = 0x0000,
266 [EEPROM_VERSION] = 0x0001,
267 [EEPROM_MAC_ADDR_0] = 0x0002,
268 [EEPROM_MAC_ADDR_1] = 0x0003,
269 [EEPROM_MAC_ADDR_2] = 0x0004,
270 [EEPROM_NIC_CONF0] = 0x001a,
271 [EEPROM_NIC_CONF1] = 0x001b,
272 [EEPROM_NIC_CONF2] = 0x001c,
273 [EEPROM_EIRP_MAX_TX_POWER] = 0x0020,
274 [EEPROM_FREQ] = 0x0022,
275 [EEPROM_LED_AG_CONF] = 0x0023,
276 [EEPROM_LED_ACT_CONF] = 0x0024,
277 [EEPROM_LED_POLARITY] = 0x0025,
278 [EEPROM_LNA] = 0x0026,
279 [EEPROM_EXT_LNA2] = 0x0027,
280 [EEPROM_RSSI_BG] = 0x0028,
281 [EEPROM_TXPOWER_DELTA] = 0x0028, /* Overlaps with RSSI_BG */
282 [EEPROM_RSSI_BG2] = 0x0029,
283 [EEPROM_TXMIXER_GAIN_BG] = 0x0029, /* Overlaps with RSSI_BG2 */
284 [EEPROM_RSSI_A] = 0x002a,
285 [EEPROM_RSSI_A2] = 0x002b,
286 [EEPROM_TXMIXER_GAIN_A] = 0x002b, /* Overlaps with RSSI_A2 */
287 [EEPROM_TXPOWER_BG1] = 0x0030,
288 [EEPROM_TXPOWER_BG2] = 0x0037,
289 [EEPROM_EXT_TXPOWER_BG3] = 0x003e,
290 [EEPROM_TSSI_BOUND_BG1] = 0x0045,
291 [EEPROM_TSSI_BOUND_BG2] = 0x0046,
292 [EEPROM_TSSI_BOUND_BG3] = 0x0047,
293 [EEPROM_TSSI_BOUND_BG4] = 0x0048,
294 [EEPROM_TSSI_BOUND_BG5] = 0x0049,
295 [EEPROM_TXPOWER_A1] = 0x004b,
296 [EEPROM_TXPOWER_A2] = 0x0065,
297 [EEPROM_EXT_TXPOWER_A3] = 0x007f,
298 [EEPROM_TSSI_BOUND_A1] = 0x009a,
299 [EEPROM_TSSI_BOUND_A2] = 0x009b,
300 [EEPROM_TSSI_BOUND_A3] = 0x009c,
301 [EEPROM_TSSI_BOUND_A4] = 0x009d,
302 [EEPROM_TSSI_BOUND_A5] = 0x009e,
303 [EEPROM_TXPOWER_BYRATE] = 0x00a0,
304 };
305
306 static unsigned int rt2800_eeprom_word_index(struct rt2x00_dev *rt2x00dev,
307 const enum rt2800_eeprom_word word)
308 {
309 const unsigned int *map;
310 unsigned int index;
311
312 if (WARN_ONCE(word >= EEPROM_WORD_COUNT,
313 "%s: invalid EEPROM word %d\n",
314 wiphy_name(rt2x00dev->hw->wiphy), word))
315 return 0;
316
317 if (rt2x00_rt(rt2x00dev, RT3593))
318 map = rt2800_eeprom_map_ext;
319 else
320 map = rt2800_eeprom_map;
321
322 index = map[word];
323
324 /* Index 0 is valid only for EEPROM_CHIP_ID.
325 * Otherwise it means that the offset of the
326 * given word is not initialized in the map,
327 * or that the field is not usable on the
328 * actual chipset.
329 */
330 WARN_ONCE(word != EEPROM_CHIP_ID && index == 0,
331 "%s: invalid access of EEPROM word %d\n",
332 wiphy_name(rt2x00dev->hw->wiphy), word);
333
334 return index;
335 }
336
337 static void *rt2800_eeprom_addr(struct rt2x00_dev *rt2x00dev,
338 const enum rt2800_eeprom_word word)
339 {
340 unsigned int index;
341
342 index = rt2800_eeprom_word_index(rt2x00dev, word);
343 return rt2x00_eeprom_addr(rt2x00dev, index);
344 }
345
346 static void rt2800_eeprom_read(struct rt2x00_dev *rt2x00dev,
347 const enum rt2800_eeprom_word word, u16 *data)
348 {
349 unsigned int index;
350
351 index = rt2800_eeprom_word_index(rt2x00dev, word);
352 rt2x00_eeprom_read(rt2x00dev, index, data);
353 }
354
355 static void rt2800_eeprom_write(struct rt2x00_dev *rt2x00dev,
356 const enum rt2800_eeprom_word word, u16 data)
357 {
358 unsigned int index;
359
360 index = rt2800_eeprom_word_index(rt2x00dev, word);
361 rt2x00_eeprom_write(rt2x00dev, index, data);
362 }
363
364 static void rt2800_eeprom_read_from_array(struct rt2x00_dev *rt2x00dev,
365 const enum rt2800_eeprom_word array,
366 unsigned int offset,
367 u16 *data)
368 {
369 unsigned int index;
370
371 index = rt2800_eeprom_word_index(rt2x00dev, array);
372 rt2x00_eeprom_read(rt2x00dev, index + offset, data);
373 }
374
375 static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev)
376 {
377 u32 reg;
378 int i, count;
379
380 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
381 if (rt2x00_get_field32(reg, WLAN_EN))
382 return 0;
383
384 rt2x00_set_field32(&reg, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff);
385 rt2x00_set_field32(&reg, FRC_WL_ANT_SET, 1);
386 rt2x00_set_field32(&reg, WLAN_CLK_EN, 0);
387 rt2x00_set_field32(&reg, WLAN_EN, 1);
388 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
389
390 udelay(REGISTER_BUSY_DELAY);
391
392 count = 0;
393 do {
394 /*
395 * Check PLL_LD & XTAL_RDY.
396 */
397 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
398 rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
399 if (rt2x00_get_field32(reg, PLL_LD) &&
400 rt2x00_get_field32(reg, XTAL_RDY))
401 break;
402 udelay(REGISTER_BUSY_DELAY);
403 }
404
405 if (i >= REGISTER_BUSY_COUNT) {
406
407 if (count >= 10)
408 return -EIO;
409
410 rt2800_register_write(rt2x00dev, 0x58, 0x018);
411 udelay(REGISTER_BUSY_DELAY);
412 rt2800_register_write(rt2x00dev, 0x58, 0x418);
413 udelay(REGISTER_BUSY_DELAY);
414 rt2800_register_write(rt2x00dev, 0x58, 0x618);
415 udelay(REGISTER_BUSY_DELAY);
416 count++;
417 } else {
418 count = 0;
419 }
420
421 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
422 rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 0);
423 rt2x00_set_field32(&reg, WLAN_CLK_EN, 1);
424 rt2x00_set_field32(&reg, WLAN_RESET, 1);
425 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
426 udelay(10);
427 rt2x00_set_field32(&reg, WLAN_RESET, 0);
428 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
429 udelay(10);
430 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, 0x7fffffff);
431 } while (count != 0);
432
433 return 0;
434 }
435
436 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
437 const u8 command, const u8 token,
438 const u8 arg0, const u8 arg1)
439 {
440 u32 reg;
441
442 /*
443 * SOC devices don't support MCU requests.
444 */
445 if (rt2x00_is_soc(rt2x00dev))
446 return;
447
448 mutex_lock(&rt2x00dev->csr_mutex);
449
450 /*
451 * Wait until the MCU becomes available, afterwards we
452 * can safely write the new data into the register.
453 */
454 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
455 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
456 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
457 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
458 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
459 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
460
461 reg = 0;
462 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
463 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
464 }
465
466 mutex_unlock(&rt2x00dev->csr_mutex);
467 }
468 EXPORT_SYMBOL_GPL(rt2800_mcu_request);
469
470 int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
471 {
472 unsigned int i = 0;
473 u32 reg;
474
475 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
476 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
477 if (reg && reg != ~0)
478 return 0;
479 msleep(1);
480 }
481
482 rt2x00_err(rt2x00dev, "Unstable hardware\n");
483 return -EBUSY;
484 }
485 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
486
487 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
488 {
489 unsigned int i;
490 u32 reg;
491
492 /*
493 * Some devices are really slow to respond here. Wait a whole second
494 * before timing out.
495 */
496 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
497 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
498 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
499 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
500 return 0;
501
502 msleep(10);
503 }
504
505 rt2x00_err(rt2x00dev, "WPDMA TX/RX busy [0x%08x]\n", reg);
506 return -EACCES;
507 }
508 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
509
510 void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev)
511 {
512 u32 reg;
513
514 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
515 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
516 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
517 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
518 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
519 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
520 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
521 }
522 EXPORT_SYMBOL_GPL(rt2800_disable_wpdma);
523
524 static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
525 {
526 u16 fw_crc;
527 u16 crc;
528
529 /*
530 * The last 2 bytes in the firmware array are the crc checksum itself,
531 * this means that we should never pass those 2 bytes to the crc
532 * algorithm.
533 */
534 fw_crc = (data[len - 2] << 8 | data[len - 1]);
535
536 /*
537 * Use the crc ccitt algorithm.
538 * This will return the same value as the legacy driver which
539 * used bit ordering reversion on the both the firmware bytes
540 * before input input as well as on the final output.
541 * Obviously using crc ccitt directly is much more efficient.
542 */
543 crc = crc_ccitt(~0, data, len - 2);
544
545 /*
546 * There is a small difference between the crc-itu-t + bitrev and
547 * the crc-ccitt crc calculation. In the latter method the 2 bytes
548 * will be swapped, use swab16 to convert the crc to the correct
549 * value.
550 */
551 crc = swab16(crc);
552
553 return fw_crc == crc;
554 }
555
556 int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
557 const u8 *data, const size_t len)
558 {
559 size_t offset = 0;
560 size_t fw_len;
561 bool multiple;
562
563 /*
564 * PCI(e) & SOC devices require firmware with a length
565 * of 8kb. USB devices require firmware files with a length
566 * of 4kb. Certain USB chipsets however require different firmware,
567 * which Ralink only provides attached to the original firmware
568 * file. Thus for USB devices, firmware files have a length
569 * which is a multiple of 4kb. The firmware for rt3290 chip also
570 * have a length which is a multiple of 4kb.
571 */
572 if (rt2x00_is_usb(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3290))
573 fw_len = 4096;
574 else
575 fw_len = 8192;
576
577 multiple = true;
578 /*
579 * Validate the firmware length
580 */
581 if (len != fw_len && (!multiple || (len % fw_len) != 0))
582 return FW_BAD_LENGTH;
583
584 /*
585 * Check if the chipset requires one of the upper parts
586 * of the firmware.
587 */
588 if (rt2x00_is_usb(rt2x00dev) &&
589 !rt2x00_rt(rt2x00dev, RT2860) &&
590 !rt2x00_rt(rt2x00dev, RT2872) &&
591 !rt2x00_rt(rt2x00dev, RT3070) &&
592 ((len / fw_len) == 1))
593 return FW_BAD_VERSION;
594
595 /*
596 * 8kb firmware files must be checked as if it were
597 * 2 separate firmware files.
598 */
599 while (offset < len) {
600 if (!rt2800_check_firmware_crc(data + offset, fw_len))
601 return FW_BAD_CRC;
602
603 offset += fw_len;
604 }
605
606 return FW_OK;
607 }
608 EXPORT_SYMBOL_GPL(rt2800_check_firmware);
609
610 int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
611 const u8 *data, const size_t len)
612 {
613 unsigned int i;
614 u32 reg;
615 int retval;
616
617 if (rt2x00_rt(rt2x00dev, RT3290)) {
618 retval = rt2800_enable_wlan_rt3290(rt2x00dev);
619 if (retval)
620 return -EBUSY;
621 }
622
623 /*
624 * If driver doesn't wake up firmware here,
625 * rt2800_load_firmware will hang forever when interface is up again.
626 */
627 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
628
629 /*
630 * Wait for stable hardware.
631 */
632 if (rt2800_wait_csr_ready(rt2x00dev))
633 return -EBUSY;
634
635 if (rt2x00_is_pci(rt2x00dev)) {
636 if (rt2x00_rt(rt2x00dev, RT3290) ||
637 rt2x00_rt(rt2x00dev, RT3572) ||
638 rt2x00_rt(rt2x00dev, RT5390) ||
639 rt2x00_rt(rt2x00dev, RT5392)) {
640 rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);
641 rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
642 rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
643 rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
644 }
645 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
646 }
647
648 rt2800_disable_wpdma(rt2x00dev);
649
650 /*
651 * Write firmware to the device.
652 */
653 rt2800_drv_write_firmware(rt2x00dev, data, len);
654
655 /*
656 * Wait for device to stabilize.
657 */
658 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
659 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
660 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
661 break;
662 msleep(1);
663 }
664
665 if (i == REGISTER_BUSY_COUNT) {
666 rt2x00_err(rt2x00dev, "PBF system register not ready\n");
667 return -EBUSY;
668 }
669
670 /*
671 * Disable DMA, will be reenabled later when enabling
672 * the radio.
673 */
674 rt2800_disable_wpdma(rt2x00dev);
675
676 /*
677 * Initialize firmware.
678 */
679 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
680 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
681 if (rt2x00_is_usb(rt2x00dev)) {
682 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
683 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
684 }
685 msleep(1);
686
687 return 0;
688 }
689 EXPORT_SYMBOL_GPL(rt2800_load_firmware);
690
691 void rt2800_write_tx_data(struct queue_entry *entry,
692 struct txentry_desc *txdesc)
693 {
694 __le32 *txwi = rt2800_drv_get_txwi(entry);
695 u32 word;
696 int i;
697
698 /*
699 * Initialize TX Info descriptor
700 */
701 rt2x00_desc_read(txwi, 0, &word);
702 rt2x00_set_field32(&word, TXWI_W0_FRAG,
703 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
704 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
705 test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
706 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
707 rt2x00_set_field32(&word, TXWI_W0_TS,
708 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
709 rt2x00_set_field32(&word, TXWI_W0_AMPDU,
710 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
711 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
712 txdesc->u.ht.mpdu_density);
713 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
714 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
715 rt2x00_set_field32(&word, TXWI_W0_BW,
716 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
717 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
718 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
719 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
720 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
721 rt2x00_desc_write(txwi, 0, word);
722
723 rt2x00_desc_read(txwi, 1, &word);
724 rt2x00_set_field32(&word, TXWI_W1_ACK,
725 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
726 rt2x00_set_field32(&word, TXWI_W1_NSEQ,
727 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
728 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
729 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
730 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
731 txdesc->key_idx : txdesc->u.ht.wcid);
732 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
733 txdesc->length);
734 rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
735 rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
736 rt2x00_desc_write(txwi, 1, word);
737
738 /*
739 * Always write 0 to IV/EIV fields (word 2 and 3), hardware will insert
740 * the IV from the IVEIV register when TXD_W3_WIV is set to 0.
741 * When TXD_W3_WIV is set to 1 it will use the IV data
742 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
743 * crypto entry in the registers should be used to encrypt the frame.
744 *
745 * Nulify all remaining words as well, we don't know how to program them.
746 */
747 for (i = 2; i < entry->queue->winfo_size / sizeof(__le32); i++)
748 _rt2x00_desc_write(txwi, i, 0);
749 }
750 EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
751
752 static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
753 {
754 s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
755 s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
756 s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
757 u16 eeprom;
758 u8 offset0;
759 u8 offset1;
760 u8 offset2;
761
762 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
763 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
764 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
765 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
766 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
767 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
768 } else {
769 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
770 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
771 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
772 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
773 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
774 }
775
776 /*
777 * Convert the value from the descriptor into the RSSI value
778 * If the value in the descriptor is 0, it is considered invalid
779 * and the default (extremely low) rssi value is assumed
780 */
781 rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
782 rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
783 rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
784
785 /*
786 * mac80211 only accepts a single RSSI value. Calculating the
787 * average doesn't deliver a fair answer either since -60:-60 would
788 * be considered equally good as -50:-70 while the second is the one
789 * which gives less energy...
790 */
791 rssi0 = max(rssi0, rssi1);
792 return (int)max(rssi0, rssi2);
793 }
794
795 void rt2800_process_rxwi(struct queue_entry *entry,
796 struct rxdone_entry_desc *rxdesc)
797 {
798 __le32 *rxwi = (__le32 *) entry->skb->data;
799 u32 word;
800
801 rt2x00_desc_read(rxwi, 0, &word);
802
803 rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
804 rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
805
806 rt2x00_desc_read(rxwi, 1, &word);
807
808 if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
809 rxdesc->flags |= RX_FLAG_SHORT_GI;
810
811 if (rt2x00_get_field32(word, RXWI_W1_BW))
812 rxdesc->flags |= RX_FLAG_40MHZ;
813
814 /*
815 * Detect RX rate, always use MCS as signal type.
816 */
817 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
818 rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
819 rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
820
821 /*
822 * Mask of 0x8 bit to remove the short preamble flag.
823 */
824 if (rxdesc->rate_mode == RATE_MODE_CCK)
825 rxdesc->signal &= ~0x8;
826
827 rt2x00_desc_read(rxwi, 2, &word);
828
829 /*
830 * Convert descriptor AGC value to RSSI value.
831 */
832 rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
833 /*
834 * Remove RXWI descriptor from start of the buffer.
835 */
836 skb_pull(entry->skb, entry->queue->winfo_size);
837 }
838 EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
839
840 void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi)
841 {
842 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
843 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
844 struct txdone_entry_desc txdesc;
845 u32 word;
846 u16 mcs, real_mcs;
847 int aggr, ampdu;
848
849 /*
850 * Obtain the status about this packet.
851 */
852 txdesc.flags = 0;
853 rt2x00_desc_read(txwi, 0, &word);
854
855 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
856 ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
857
858 real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
859 aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
860
861 /*
862 * If a frame was meant to be sent as a single non-aggregated MPDU
863 * but ended up in an aggregate the used tx rate doesn't correlate
864 * with the one specified in the TXWI as the whole aggregate is sent
865 * with the same rate.
866 *
867 * For example: two frames are sent to rt2x00, the first one sets
868 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
869 * and requests MCS15. If the hw aggregates both frames into one
870 * AMDPU the tx status for both frames will contain MCS7 although
871 * the frame was sent successfully.
872 *
873 * Hence, replace the requested rate with the real tx rate to not
874 * confuse the rate control algortihm by providing clearly wrong
875 * data.
876 */
877 if (unlikely(aggr == 1 && ampdu == 0 && real_mcs != mcs)) {
878 skbdesc->tx_rate_idx = real_mcs;
879 mcs = real_mcs;
880 }
881
882 if (aggr == 1 || ampdu == 1)
883 __set_bit(TXDONE_AMPDU, &txdesc.flags);
884
885 /*
886 * Ralink has a retry mechanism using a global fallback
887 * table. We setup this fallback table to try the immediate
888 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
889 * always contains the MCS used for the last transmission, be
890 * it successful or not.
891 */
892 if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
893 /*
894 * Transmission succeeded. The number of retries is
895 * mcs - real_mcs
896 */
897 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
898 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
899 } else {
900 /*
901 * Transmission failed. The number of retries is
902 * always 7 in this case (for a total number of 8
903 * frames sent).
904 */
905 __set_bit(TXDONE_FAILURE, &txdesc.flags);
906 txdesc.retry = rt2x00dev->long_retry;
907 }
908
909 /*
910 * the frame was retried at least once
911 * -> hw used fallback rates
912 */
913 if (txdesc.retry)
914 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
915
916 rt2x00lib_txdone(entry, &txdesc);
917 }
918 EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
919
920 void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
921 {
922 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
923 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
924 unsigned int beacon_base;
925 unsigned int padding_len;
926 u32 orig_reg, reg;
927 const int txwi_desc_size = entry->queue->winfo_size;
928
929 /*
930 * Disable beaconing while we are reloading the beacon data,
931 * otherwise we might be sending out invalid data.
932 */
933 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
934 orig_reg = reg;
935 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
936 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
937
938 /*
939 * Add space for the TXWI in front of the skb.
940 */
941 memset(skb_push(entry->skb, txwi_desc_size), 0, txwi_desc_size);
942
943 /*
944 * Register descriptor details in skb frame descriptor.
945 */
946 skbdesc->flags |= SKBDESC_DESC_IN_SKB;
947 skbdesc->desc = entry->skb->data;
948 skbdesc->desc_len = txwi_desc_size;
949
950 /*
951 * Add the TXWI for the beacon to the skb.
952 */
953 rt2800_write_tx_data(entry, txdesc);
954
955 /*
956 * Dump beacon to userspace through debugfs.
957 */
958 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
959
960 /*
961 * Write entire beacon with TXWI and padding to register.
962 */
963 padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
964 if (padding_len && skb_pad(entry->skb, padding_len)) {
965 rt2x00_err(rt2x00dev, "Failure padding beacon, aborting\n");
966 /* skb freed by skb_pad() on failure */
967 entry->skb = NULL;
968 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
969 return;
970 }
971
972 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
973 rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
974 entry->skb->len + padding_len);
975
976 /*
977 * Enable beaconing again.
978 */
979 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
980 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
981
982 /*
983 * Clean up beacon skb.
984 */
985 dev_kfree_skb_any(entry->skb);
986 entry->skb = NULL;
987 }
988 EXPORT_SYMBOL_GPL(rt2800_write_beacon);
989
990 static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
991 unsigned int beacon_base)
992 {
993 int i;
994 const int txwi_desc_size = rt2x00dev->bcn->winfo_size;
995
996 /*
997 * For the Beacon base registers we only need to clear
998 * the whole TXWI which (when set to 0) will invalidate
999 * the entire beacon.
1000 */
1001 for (i = 0; i < txwi_desc_size; i += sizeof(__le32))
1002 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
1003 }
1004
1005 void rt2800_clear_beacon(struct queue_entry *entry)
1006 {
1007 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1008 u32 reg;
1009
1010 /*
1011 * Disable beaconing while we are reloading the beacon data,
1012 * otherwise we might be sending out invalid data.
1013 */
1014 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1015 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1016 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1017
1018 /*
1019 * Clear beacon.
1020 */
1021 rt2800_clear_beacon_register(rt2x00dev,
1022 HW_BEACON_OFFSET(entry->entry_idx));
1023
1024 /*
1025 * Enabled beaconing again.
1026 */
1027 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
1028 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1029 }
1030 EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
1031
1032 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1033 const struct rt2x00debug rt2800_rt2x00debug = {
1034 .owner = THIS_MODULE,
1035 .csr = {
1036 .read = rt2800_register_read,
1037 .write = rt2800_register_write,
1038 .flags = RT2X00DEBUGFS_OFFSET,
1039 .word_base = CSR_REG_BASE,
1040 .word_size = sizeof(u32),
1041 .word_count = CSR_REG_SIZE / sizeof(u32),
1042 },
1043 .eeprom = {
1044 /* NOTE: The local EEPROM access functions can't
1045 * be used here, use the generic versions instead.
1046 */
1047 .read = rt2x00_eeprom_read,
1048 .write = rt2x00_eeprom_write,
1049 .word_base = EEPROM_BASE,
1050 .word_size = sizeof(u16),
1051 .word_count = EEPROM_SIZE / sizeof(u16),
1052 },
1053 .bbp = {
1054 .read = rt2800_bbp_read,
1055 .write = rt2800_bbp_write,
1056 .word_base = BBP_BASE,
1057 .word_size = sizeof(u8),
1058 .word_count = BBP_SIZE / sizeof(u8),
1059 },
1060 .rf = {
1061 .read = rt2x00_rf_read,
1062 .write = rt2800_rf_write,
1063 .word_base = RF_BASE,
1064 .word_size = sizeof(u32),
1065 .word_count = RF_SIZE / sizeof(u32),
1066 },
1067 .rfcsr = {
1068 .read = rt2800_rfcsr_read,
1069 .write = rt2800_rfcsr_write,
1070 .word_base = RFCSR_BASE,
1071 .word_size = sizeof(u8),
1072 .word_count = RFCSR_SIZE / sizeof(u8),
1073 },
1074 };
1075 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
1076 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1077
1078 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
1079 {
1080 u32 reg;
1081
1082 if (rt2x00_rt(rt2x00dev, RT3290)) {
1083 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
1084 return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0);
1085 } else {
1086 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
1087 return rt2x00_get_field32(reg, GPIO_CTRL_VAL2);
1088 }
1089 }
1090 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
1091
1092 #ifdef CONFIG_RT2X00_LIB_LEDS
1093 static void rt2800_brightness_set(struct led_classdev *led_cdev,
1094 enum led_brightness brightness)
1095 {
1096 struct rt2x00_led *led =
1097 container_of(led_cdev, struct rt2x00_led, led_dev);
1098 unsigned int enabled = brightness != LED_OFF;
1099 unsigned int bg_mode =
1100 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
1101 unsigned int polarity =
1102 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
1103 EEPROM_FREQ_LED_POLARITY);
1104 unsigned int ledmode =
1105 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
1106 EEPROM_FREQ_LED_MODE);
1107 u32 reg;
1108
1109 /* Check for SoC (SOC devices don't support MCU requests) */
1110 if (rt2x00_is_soc(led->rt2x00dev)) {
1111 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
1112
1113 /* Set LED Polarity */
1114 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, polarity);
1115
1116 /* Set LED Mode */
1117 if (led->type == LED_TYPE_RADIO) {
1118 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE,
1119 enabled ? 3 : 0);
1120 } else if (led->type == LED_TYPE_ASSOC) {
1121 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE,
1122 enabled ? 3 : 0);
1123 } else if (led->type == LED_TYPE_QUALITY) {
1124 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE,
1125 enabled ? 3 : 0);
1126 }
1127
1128 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
1129
1130 } else {
1131 if (led->type == LED_TYPE_RADIO) {
1132 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1133 enabled ? 0x20 : 0);
1134 } else if (led->type == LED_TYPE_ASSOC) {
1135 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1136 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
1137 } else if (led->type == LED_TYPE_QUALITY) {
1138 /*
1139 * The brightness is divided into 6 levels (0 - 5),
1140 * The specs tell us the following levels:
1141 * 0, 1 ,3, 7, 15, 31
1142 * to determine the level in a simple way we can simply
1143 * work with bitshifting:
1144 * (1 << level) - 1
1145 */
1146 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
1147 (1 << brightness / (LED_FULL / 6)) - 1,
1148 polarity);
1149 }
1150 }
1151 }
1152
1153 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
1154 struct rt2x00_led *led, enum led_type type)
1155 {
1156 led->rt2x00dev = rt2x00dev;
1157 led->type = type;
1158 led->led_dev.brightness_set = rt2800_brightness_set;
1159 led->flags = LED_INITIALIZED;
1160 }
1161 #endif /* CONFIG_RT2X00_LIB_LEDS */
1162
1163 /*
1164 * Configuration handlers.
1165 */
1166 static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev,
1167 const u8 *address,
1168 int wcid)
1169 {
1170 struct mac_wcid_entry wcid_entry;
1171 u32 offset;
1172
1173 offset = MAC_WCID_ENTRY(wcid);
1174
1175 memset(&wcid_entry, 0xff, sizeof(wcid_entry));
1176 if (address)
1177 memcpy(wcid_entry.mac, address, ETH_ALEN);
1178
1179 rt2800_register_multiwrite(rt2x00dev, offset,
1180 &wcid_entry, sizeof(wcid_entry));
1181 }
1182
1183 static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid)
1184 {
1185 u32 offset;
1186 offset = MAC_WCID_ATTR_ENTRY(wcid);
1187 rt2800_register_write(rt2x00dev, offset, 0);
1188 }
1189
1190 static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev,
1191 int wcid, u32 bssidx)
1192 {
1193 u32 offset = MAC_WCID_ATTR_ENTRY(wcid);
1194 u32 reg;
1195
1196 /*
1197 * The BSS Idx numbers is split in a main value of 3 bits,
1198 * and a extended field for adding one additional bit to the value.
1199 */
1200 rt2800_register_read(rt2x00dev, offset, &reg);
1201 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7));
1202 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
1203 (bssidx & 0x8) >> 3);
1204 rt2800_register_write(rt2x00dev, offset, reg);
1205 }
1206
1207 static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev,
1208 struct rt2x00lib_crypto *crypto,
1209 struct ieee80211_key_conf *key)
1210 {
1211 struct mac_iveiv_entry iveiv_entry;
1212 u32 offset;
1213 u32 reg;
1214
1215 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
1216
1217 if (crypto->cmd == SET_KEY) {
1218 rt2800_register_read(rt2x00dev, offset, &reg);
1219 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
1220 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
1221 /*
1222 * Both the cipher as the BSS Idx numbers are split in a main
1223 * value of 3 bits, and a extended field for adding one additional
1224 * bit to the value.
1225 */
1226 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
1227 (crypto->cipher & 0x7));
1228 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
1229 (crypto->cipher & 0x8) >> 3);
1230 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
1231 rt2800_register_write(rt2x00dev, offset, reg);
1232 } else {
1233 /* Delete the cipher without touching the bssidx */
1234 rt2800_register_read(rt2x00dev, offset, &reg);
1235 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB, 0);
1236 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER, 0);
1237 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0);
1238 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
1239 rt2800_register_write(rt2x00dev, offset, reg);
1240 }
1241
1242 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
1243
1244 memset(&iveiv_entry, 0, sizeof(iveiv_entry));
1245 if ((crypto->cipher == CIPHER_TKIP) ||
1246 (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
1247 (crypto->cipher == CIPHER_AES))
1248 iveiv_entry.iv[3] |= 0x20;
1249 iveiv_entry.iv[3] |= key->keyidx << 6;
1250 rt2800_register_multiwrite(rt2x00dev, offset,
1251 &iveiv_entry, sizeof(iveiv_entry));
1252 }
1253
1254 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1255 struct rt2x00lib_crypto *crypto,
1256 struct ieee80211_key_conf *key)
1257 {
1258 struct hw_key_entry key_entry;
1259 struct rt2x00_field32 field;
1260 u32 offset;
1261 u32 reg;
1262
1263 if (crypto->cmd == SET_KEY) {
1264 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1265
1266 memcpy(key_entry.key, crypto->key,
1267 sizeof(key_entry.key));
1268 memcpy(key_entry.tx_mic, crypto->tx_mic,
1269 sizeof(key_entry.tx_mic));
1270 memcpy(key_entry.rx_mic, crypto->rx_mic,
1271 sizeof(key_entry.rx_mic));
1272
1273 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1274 rt2800_register_multiwrite(rt2x00dev, offset,
1275 &key_entry, sizeof(key_entry));
1276 }
1277
1278 /*
1279 * The cipher types are stored over multiple registers
1280 * starting with SHARED_KEY_MODE_BASE each word will have
1281 * 32 bits and contains the cipher types for 2 bssidx each.
1282 * Using the correct defines correctly will cause overhead,
1283 * so just calculate the correct offset.
1284 */
1285 field.bit_offset = 4 * (key->hw_key_idx % 8);
1286 field.bit_mask = 0x7 << field.bit_offset;
1287
1288 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1289
1290 rt2800_register_read(rt2x00dev, offset, &reg);
1291 rt2x00_set_field32(&reg, field,
1292 (crypto->cmd == SET_KEY) * crypto->cipher);
1293 rt2800_register_write(rt2x00dev, offset, reg);
1294
1295 /*
1296 * Update WCID information
1297 */
1298 rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx);
1299 rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx,
1300 crypto->bssidx);
1301 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1302
1303 return 0;
1304 }
1305 EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1306
1307 static inline int rt2800_find_wcid(struct rt2x00_dev *rt2x00dev)
1308 {
1309 struct mac_wcid_entry wcid_entry;
1310 int idx;
1311 u32 offset;
1312
1313 /*
1314 * Search for the first free WCID entry and return the corresponding
1315 * index.
1316 *
1317 * Make sure the WCID starts _after_ the last possible shared key
1318 * entry (>32).
1319 *
1320 * Since parts of the pairwise key table might be shared with
1321 * the beacon frame buffers 6 & 7 we should only write into the
1322 * first 222 entries.
1323 */
1324 for (idx = 33; idx <= 222; idx++) {
1325 offset = MAC_WCID_ENTRY(idx);
1326 rt2800_register_multiread(rt2x00dev, offset, &wcid_entry,
1327 sizeof(wcid_entry));
1328 if (is_broadcast_ether_addr(wcid_entry.mac))
1329 return idx;
1330 }
1331
1332 /*
1333 * Use -1 to indicate that we don't have any more space in the WCID
1334 * table.
1335 */
1336 return -1;
1337 }
1338
1339 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1340 struct rt2x00lib_crypto *crypto,
1341 struct ieee80211_key_conf *key)
1342 {
1343 struct hw_key_entry key_entry;
1344 u32 offset;
1345
1346 if (crypto->cmd == SET_KEY) {
1347 /*
1348 * Allow key configuration only for STAs that are
1349 * known by the hw.
1350 */
1351 if (crypto->wcid < 0)
1352 return -ENOSPC;
1353 key->hw_key_idx = crypto->wcid;
1354
1355 memcpy(key_entry.key, crypto->key,
1356 sizeof(key_entry.key));
1357 memcpy(key_entry.tx_mic, crypto->tx_mic,
1358 sizeof(key_entry.tx_mic));
1359 memcpy(key_entry.rx_mic, crypto->rx_mic,
1360 sizeof(key_entry.rx_mic));
1361
1362 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1363 rt2800_register_multiwrite(rt2x00dev, offset,
1364 &key_entry, sizeof(key_entry));
1365 }
1366
1367 /*
1368 * Update WCID information
1369 */
1370 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1371
1372 return 0;
1373 }
1374 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1375
1376 int rt2800_sta_add(struct rt2x00_dev *rt2x00dev, struct ieee80211_vif *vif,
1377 struct ieee80211_sta *sta)
1378 {
1379 int wcid;
1380 struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
1381
1382 /*
1383 * Find next free WCID.
1384 */
1385 wcid = rt2800_find_wcid(rt2x00dev);
1386
1387 /*
1388 * Store selected wcid even if it is invalid so that we can
1389 * later decide if the STA is uploaded into the hw.
1390 */
1391 sta_priv->wcid = wcid;
1392
1393 /*
1394 * No space left in the device, however, we can still communicate
1395 * with the STA -> No error.
1396 */
1397 if (wcid < 0)
1398 return 0;
1399
1400 /*
1401 * Clean up WCID attributes and write STA address to the device.
1402 */
1403 rt2800_delete_wcid_attr(rt2x00dev, wcid);
1404 rt2800_config_wcid(rt2x00dev, sta->addr, wcid);
1405 rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid,
1406 rt2x00lib_get_bssidx(rt2x00dev, vif));
1407 return 0;
1408 }
1409 EXPORT_SYMBOL_GPL(rt2800_sta_add);
1410
1411 int rt2800_sta_remove(struct rt2x00_dev *rt2x00dev, int wcid)
1412 {
1413 /*
1414 * Remove WCID entry, no need to clean the attributes as they will
1415 * get renewed when the WCID is reused.
1416 */
1417 rt2800_config_wcid(rt2x00dev, NULL, wcid);
1418
1419 return 0;
1420 }
1421 EXPORT_SYMBOL_GPL(rt2800_sta_remove);
1422
1423 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1424 const unsigned int filter_flags)
1425 {
1426 u32 reg;
1427
1428 /*
1429 * Start configuration steps.
1430 * Note that the version error will always be dropped
1431 * and broadcast frames will always be accepted since
1432 * there is no filter for it at this time.
1433 */
1434 rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
1435 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1436 !(filter_flags & FIF_FCSFAIL));
1437 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1438 !(filter_flags & FIF_PLCPFAIL));
1439 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1440 !(filter_flags & FIF_PROMISC_IN_BSS));
1441 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1442 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1443 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1444 !(filter_flags & FIF_ALLMULTI));
1445 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1446 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1447 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1448 !(filter_flags & FIF_CONTROL));
1449 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1450 !(filter_flags & FIF_CONTROL));
1451 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1452 !(filter_flags & FIF_CONTROL));
1453 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1454 !(filter_flags & FIF_CONTROL));
1455 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1456 !(filter_flags & FIF_CONTROL));
1457 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1458 !(filter_flags & FIF_PSPOLL));
1459 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 0);
1460 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR,
1461 !(filter_flags & FIF_CONTROL));
1462 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1463 !(filter_flags & FIF_CONTROL));
1464 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1465 }
1466 EXPORT_SYMBOL_GPL(rt2800_config_filter);
1467
1468 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1469 struct rt2x00intf_conf *conf, const unsigned int flags)
1470 {
1471 u32 reg;
1472 bool update_bssid = false;
1473
1474 if (flags & CONFIG_UPDATE_TYPE) {
1475 /*
1476 * Enable synchronisation.
1477 */
1478 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1479 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
1480 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1481
1482 if (conf->sync == TSF_SYNC_AP_NONE) {
1483 /*
1484 * Tune beacon queue transmit parameters for AP mode
1485 */
1486 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1487 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 0);
1488 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 1);
1489 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1490 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 0);
1491 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1492 } else {
1493 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1494 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 4);
1495 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 2);
1496 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1497 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 16);
1498 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1499 }
1500 }
1501
1502 if (flags & CONFIG_UPDATE_MAC) {
1503 if (flags & CONFIG_UPDATE_TYPE &&
1504 conf->sync == TSF_SYNC_AP_NONE) {
1505 /*
1506 * The BSSID register has to be set to our own mac
1507 * address in AP mode.
1508 */
1509 memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1510 update_bssid = true;
1511 }
1512
1513 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1514 reg = le32_to_cpu(conf->mac[1]);
1515 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1516 conf->mac[1] = cpu_to_le32(reg);
1517 }
1518
1519 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1520 conf->mac, sizeof(conf->mac));
1521 }
1522
1523 if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
1524 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1525 reg = le32_to_cpu(conf->bssid[1]);
1526 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1527 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
1528 conf->bssid[1] = cpu_to_le32(reg);
1529 }
1530
1531 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1532 conf->bssid, sizeof(conf->bssid));
1533 }
1534 }
1535 EXPORT_SYMBOL_GPL(rt2800_config_intf);
1536
1537 static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1538 struct rt2x00lib_erp *erp)
1539 {
1540 bool any_sta_nongf = !!(erp->ht_opmode &
1541 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1542 u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1543 u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1544 u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1545 u32 reg;
1546
1547 /* default protection rate for HT20: OFDM 24M */
1548 mm20_rate = gf20_rate = 0x4004;
1549
1550 /* default protection rate for HT40: duplicate OFDM 24M */
1551 mm40_rate = gf40_rate = 0x4084;
1552
1553 switch (protection) {
1554 case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1555 /*
1556 * All STAs in this BSS are HT20/40 but there might be
1557 * STAs not supporting greenfield mode.
1558 * => Disable protection for HT transmissions.
1559 */
1560 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1561
1562 break;
1563 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1564 /*
1565 * All STAs in this BSS are HT20 or HT20/40 but there
1566 * might be STAs not supporting greenfield mode.
1567 * => Protect all HT40 transmissions.
1568 */
1569 mm20_mode = gf20_mode = 0;
1570 mm40_mode = gf40_mode = 2;
1571
1572 break;
1573 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1574 /*
1575 * Nonmember protection:
1576 * According to 802.11n we _should_ protect all
1577 * HT transmissions (but we don't have to).
1578 *
1579 * But if cts_protection is enabled we _shall_ protect
1580 * all HT transmissions using a CCK rate.
1581 *
1582 * And if any station is non GF we _shall_ protect
1583 * GF transmissions.
1584 *
1585 * We decide to protect everything
1586 * -> fall through to mixed mode.
1587 */
1588 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1589 /*
1590 * Legacy STAs are present
1591 * => Protect all HT transmissions.
1592 */
1593 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2;
1594
1595 /*
1596 * If erp protection is needed we have to protect HT
1597 * transmissions with CCK 11M long preamble.
1598 */
1599 if (erp->cts_protection) {
1600 /* don't duplicate RTS/CTS in CCK mode */
1601 mm20_rate = mm40_rate = 0x0003;
1602 gf20_rate = gf40_rate = 0x0003;
1603 }
1604 break;
1605 }
1606
1607 /* check for STAs not supporting greenfield mode */
1608 if (any_sta_nongf)
1609 gf20_mode = gf40_mode = 2;
1610
1611 /* Update HT protection config */
1612 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1613 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1614 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1615 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1616
1617 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1618 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1619 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1620 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1621
1622 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1623 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1624 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1625 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1626
1627 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1628 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1629 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1630 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1631 }
1632
1633 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1634 u32 changed)
1635 {
1636 u32 reg;
1637
1638 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1639 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1640 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
1641 !!erp->short_preamble);
1642 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1643 !!erp->short_preamble);
1644 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1645 }
1646
1647 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1648 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1649 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1650 erp->cts_protection ? 2 : 0);
1651 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1652 }
1653
1654 if (changed & BSS_CHANGED_BASIC_RATES) {
1655 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1656 erp->basic_rates);
1657 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1658 }
1659
1660 if (changed & BSS_CHANGED_ERP_SLOT) {
1661 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1662 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
1663 erp->slot_time);
1664 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1665
1666 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1667 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1668 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1669 }
1670
1671 if (changed & BSS_CHANGED_BEACON_INT) {
1672 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1673 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1674 erp->beacon_int * 16);
1675 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1676 }
1677
1678 if (changed & BSS_CHANGED_HT)
1679 rt2800_config_ht_opmode(rt2x00dev, erp);
1680 }
1681 EXPORT_SYMBOL_GPL(rt2800_config_erp);
1682
1683 static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev)
1684 {
1685 u32 reg;
1686 u16 eeprom;
1687 u8 led_ctrl, led_g_mode, led_r_mode;
1688
1689 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
1690 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
1691 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 1);
1692 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 1);
1693 } else {
1694 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 0);
1695 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 0);
1696 }
1697 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
1698
1699 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1700 led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0;
1701 led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3;
1702 if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) ||
1703 led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) {
1704 rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1705 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE);
1706 if (led_ctrl == 0 || led_ctrl > 0x40) {
1707 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, led_g_mode);
1708 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, led_r_mode);
1709 rt2800_register_write(rt2x00dev, LED_CFG, reg);
1710 } else {
1711 rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff,
1712 (led_g_mode << 2) | led_r_mode, 1);
1713 }
1714 }
1715 }
1716
1717 static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
1718 enum antenna ant)
1719 {
1720 u32 reg;
1721 u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
1722 u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
1723
1724 if (rt2x00_is_pci(rt2x00dev)) {
1725 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
1726 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
1727 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
1728 } else if (rt2x00_is_usb(rt2x00dev))
1729 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
1730 eesk_pin, 0);
1731
1732 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
1733 rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
1734 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, gpio_bit3);
1735 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
1736 }
1737
1738 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1739 {
1740 u8 r1;
1741 u8 r3;
1742 u16 eeprom;
1743
1744 rt2800_bbp_read(rt2x00dev, 1, &r1);
1745 rt2800_bbp_read(rt2x00dev, 3, &r3);
1746
1747 if (rt2x00_rt(rt2x00dev, RT3572) &&
1748 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1749 rt2800_config_3572bt_ant(rt2x00dev);
1750
1751 /*
1752 * Configure the TX antenna.
1753 */
1754 switch (ant->tx_chain_num) {
1755 case 1:
1756 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1757 break;
1758 case 2:
1759 if (rt2x00_rt(rt2x00dev, RT3572) &&
1760 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1761 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1);
1762 else
1763 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1764 break;
1765 case 3:
1766 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1767 break;
1768 }
1769
1770 /*
1771 * Configure the RX antenna.
1772 */
1773 switch (ant->rx_chain_num) {
1774 case 1:
1775 if (rt2x00_rt(rt2x00dev, RT3070) ||
1776 rt2x00_rt(rt2x00dev, RT3090) ||
1777 rt2x00_rt(rt2x00dev, RT3352) ||
1778 rt2x00_rt(rt2x00dev, RT3390)) {
1779 rt2800_eeprom_read(rt2x00dev,
1780 EEPROM_NIC_CONF1, &eeprom);
1781 if (rt2x00_get_field16(eeprom,
1782 EEPROM_NIC_CONF1_ANT_DIVERSITY))
1783 rt2800_set_ant_diversity(rt2x00dev,
1784 rt2x00dev->default_ant.rx);
1785 }
1786 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1787 break;
1788 case 2:
1789 if (rt2x00_rt(rt2x00dev, RT3572) &&
1790 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1791 rt2x00_set_field8(&r3, BBP3_RX_ADC, 1);
1792 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA,
1793 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
1794 rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B);
1795 } else {
1796 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1797 }
1798 break;
1799 case 3:
1800 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1801 break;
1802 }
1803
1804 rt2800_bbp_write(rt2x00dev, 3, r3);
1805 rt2800_bbp_write(rt2x00dev, 1, r1);
1806 }
1807 EXPORT_SYMBOL_GPL(rt2800_config_ant);
1808
1809 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1810 struct rt2x00lib_conf *libconf)
1811 {
1812 u16 eeprom;
1813 short lna_gain;
1814
1815 if (libconf->rf.channel <= 14) {
1816 rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1817 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1818 } else if (libconf->rf.channel <= 64) {
1819 rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1820 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1821 } else if (libconf->rf.channel <= 128) {
1822 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1823 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
1824 } else {
1825 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1826 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
1827 }
1828
1829 rt2x00dev->lna_gain = lna_gain;
1830 }
1831
1832 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1833 struct ieee80211_conf *conf,
1834 struct rf_channel *rf,
1835 struct channel_info *info)
1836 {
1837 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1838
1839 if (rt2x00dev->default_ant.tx_chain_num == 1)
1840 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1841
1842 if (rt2x00dev->default_ant.rx_chain_num == 1) {
1843 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1844 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1845 } else if (rt2x00dev->default_ant.rx_chain_num == 2)
1846 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1847
1848 if (rf->channel > 14) {
1849 /*
1850 * When TX power is below 0, we should increase it by 7 to
1851 * make it a positive value (Minimum value is -7).
1852 * However this means that values between 0 and 7 have
1853 * double meaning, and we should set a 7DBm boost flag.
1854 */
1855 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
1856 (info->default_power1 >= 0));
1857
1858 if (info->default_power1 < 0)
1859 info->default_power1 += 7;
1860
1861 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
1862
1863 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
1864 (info->default_power2 >= 0));
1865
1866 if (info->default_power2 < 0)
1867 info->default_power2 += 7;
1868
1869 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
1870 } else {
1871 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
1872 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
1873 }
1874
1875 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1876
1877 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1878 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1879 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1880 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1881
1882 udelay(200);
1883
1884 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1885 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1886 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1887 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1888
1889 udelay(200);
1890
1891 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1892 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1893 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1894 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1895 }
1896
1897 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1898 struct ieee80211_conf *conf,
1899 struct rf_channel *rf,
1900 struct channel_info *info)
1901 {
1902 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1903 u8 rfcsr, calib_tx, calib_rx;
1904
1905 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1906
1907 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
1908 rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3);
1909 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
1910
1911 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1912 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
1913 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1914
1915 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1916 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
1917 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1918
1919 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1920 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
1921 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1922
1923 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1924 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
1925 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
1926 rt2x00dev->default_ant.rx_chain_num <= 1);
1927 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD,
1928 rt2x00dev->default_ant.rx_chain_num <= 2);
1929 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
1930 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
1931 rt2x00dev->default_ant.tx_chain_num <= 1);
1932 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD,
1933 rt2x00dev->default_ant.tx_chain_num <= 2);
1934 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1935
1936 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1937 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1938 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1939 msleep(1);
1940 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1941 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1942
1943 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1944 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1945 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1946
1947 if (rt2x00_rt(rt2x00dev, RT3390)) {
1948 calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f;
1949 calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f;
1950 } else {
1951 if (conf_is_ht40(conf)) {
1952 calib_tx = drv_data->calibration_bw40;
1953 calib_rx = drv_data->calibration_bw40;
1954 } else {
1955 calib_tx = drv_data->calibration_bw20;
1956 calib_rx = drv_data->calibration_bw20;
1957 }
1958 }
1959
1960 rt2800_rfcsr_read(rt2x00dev, 24, &rfcsr);
1961 rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx);
1962 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr);
1963
1964 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
1965 rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx);
1966 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
1967
1968 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1969 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
1970 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1971
1972 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1973 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1974 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1975 msleep(1);
1976 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1977 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1978 }
1979
1980 static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
1981 struct ieee80211_conf *conf,
1982 struct rf_channel *rf,
1983 struct channel_info *info)
1984 {
1985 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1986 u8 rfcsr;
1987 u32 reg;
1988
1989 if (rf->channel <= 14) {
1990 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
1991 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
1992 } else {
1993 rt2800_bbp_write(rt2x00dev, 25, 0x09);
1994 rt2800_bbp_write(rt2x00dev, 26, 0xff);
1995 }
1996
1997 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1998 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
1999
2000 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
2001 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
2002 if (rf->channel <= 14)
2003 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2);
2004 else
2005 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1);
2006 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2007
2008 rt2800_rfcsr_read(rt2x00dev, 5, &rfcsr);
2009 if (rf->channel <= 14)
2010 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1);
2011 else
2012 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2);
2013 rt2800_rfcsr_write(rt2x00dev, 5, rfcsr);
2014
2015 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
2016 if (rf->channel <= 14) {
2017 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3);
2018 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
2019 info->default_power1);
2020 } else {
2021 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7);
2022 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
2023 (info->default_power1 & 0x3) |
2024 ((info->default_power1 & 0xC) << 1));
2025 }
2026 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2027
2028 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
2029 if (rf->channel <= 14) {
2030 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3);
2031 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
2032 info->default_power2);
2033 } else {
2034 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7);
2035 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
2036 (info->default_power2 & 0x3) |
2037 ((info->default_power2 & 0xC) << 1));
2038 }
2039 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
2040
2041 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2042 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2043 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2044 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2045 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2046 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2047 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2048 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
2049 if (rf->channel <= 14) {
2050 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2051 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2052 }
2053 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2054 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2055 } else {
2056 switch (rt2x00dev->default_ant.tx_chain_num) {
2057 case 1:
2058 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2059 case 2:
2060 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2061 break;
2062 }
2063
2064 switch (rt2x00dev->default_ant.rx_chain_num) {
2065 case 1:
2066 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2067 case 2:
2068 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2069 break;
2070 }
2071 }
2072 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2073
2074 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
2075 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
2076 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2077
2078 if (conf_is_ht40(conf)) {
2079 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40);
2080 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40);
2081 } else {
2082 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20);
2083 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20);
2084 }
2085
2086 if (rf->channel <= 14) {
2087 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
2088 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
2089 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
2090 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
2091 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
2092 rfcsr = 0x4c;
2093 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
2094 drv_data->txmixer_gain_24g);
2095 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
2096 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
2097 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
2098 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
2099 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
2100 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
2101 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
2102 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
2103 } else {
2104 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
2105 rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1);
2106 rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0);
2107 rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1);
2108 rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0);
2109 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2110 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
2111 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
2112 rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
2113 rt2800_rfcsr_write(rt2x00dev, 15, 0x43);
2114 rfcsr = 0x7a;
2115 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
2116 drv_data->txmixer_gain_5g);
2117 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
2118 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
2119 if (rf->channel <= 64) {
2120 rt2800_rfcsr_write(rt2x00dev, 19, 0xb7);
2121 rt2800_rfcsr_write(rt2x00dev, 20, 0xf6);
2122 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
2123 } else if (rf->channel <= 128) {
2124 rt2800_rfcsr_write(rt2x00dev, 19, 0x74);
2125 rt2800_rfcsr_write(rt2x00dev, 20, 0xf4);
2126 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2127 } else {
2128 rt2800_rfcsr_write(rt2x00dev, 19, 0x72);
2129 rt2800_rfcsr_write(rt2x00dev, 20, 0xf3);
2130 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2131 }
2132 rt2800_rfcsr_write(rt2x00dev, 26, 0x87);
2133 rt2800_rfcsr_write(rt2x00dev, 27, 0x01);
2134 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f);
2135 }
2136
2137 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
2138 rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
2139 if (rf->channel <= 14)
2140 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
2141 else
2142 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 0);
2143 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
2144
2145 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
2146 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
2147 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2148 }
2149
2150 #define POWER_BOUND 0x27
2151 #define POWER_BOUND_5G 0x2b
2152 #define FREQ_OFFSET_BOUND 0x5f
2153
2154 static void rt2800_adjust_freq_offset(struct rt2x00_dev *rt2x00dev)
2155 {
2156 u8 rfcsr;
2157
2158 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
2159 if (rt2x00dev->freq_offset > FREQ_OFFSET_BOUND)
2160 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, FREQ_OFFSET_BOUND);
2161 else
2162 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
2163 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2164 }
2165
2166 static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev,
2167 struct ieee80211_conf *conf,
2168 struct rf_channel *rf,
2169 struct channel_info *info)
2170 {
2171 u8 rfcsr;
2172
2173 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2174 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2175 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2176 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2177 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2178
2179 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2180 if (info->default_power1 > POWER_BOUND)
2181 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
2182 else
2183 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2184 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2185
2186 rt2800_adjust_freq_offset(rt2x00dev);
2187
2188 if (rf->channel <= 14) {
2189 if (rf->channel == 6)
2190 rt2800_bbp_write(rt2x00dev, 68, 0x0c);
2191 else
2192 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
2193
2194 if (rf->channel >= 1 && rf->channel <= 6)
2195 rt2800_bbp_write(rt2x00dev, 59, 0x0f);
2196 else if (rf->channel >= 7 && rf->channel <= 11)
2197 rt2800_bbp_write(rt2x00dev, 59, 0x0e);
2198 else if (rf->channel >= 12 && rf->channel <= 14)
2199 rt2800_bbp_write(rt2x00dev, 59, 0x0d);
2200 }
2201 }
2202
2203 static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev,
2204 struct ieee80211_conf *conf,
2205 struct rf_channel *rf,
2206 struct channel_info *info)
2207 {
2208 u8 rfcsr;
2209
2210 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2211 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2212
2213 rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
2214 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
2215 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
2216
2217 if (info->default_power1 > POWER_BOUND)
2218 rt2800_rfcsr_write(rt2x00dev, 47, POWER_BOUND);
2219 else
2220 rt2800_rfcsr_write(rt2x00dev, 47, info->default_power1);
2221
2222 if (info->default_power2 > POWER_BOUND)
2223 rt2800_rfcsr_write(rt2x00dev, 48, POWER_BOUND);
2224 else
2225 rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2);
2226
2227 rt2800_adjust_freq_offset(rt2x00dev);
2228
2229 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2230 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2231 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2232
2233 if ( rt2x00dev->default_ant.tx_chain_num == 2 )
2234 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2235 else
2236 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2237
2238 if ( rt2x00dev->default_ant.rx_chain_num == 2 )
2239 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2240 else
2241 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2242
2243 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2244 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2245
2246 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2247
2248 rt2800_rfcsr_write(rt2x00dev, 31, 80);
2249 }
2250
2251 static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
2252 struct ieee80211_conf *conf,
2253 struct rf_channel *rf,
2254 struct channel_info *info)
2255 {
2256 u8 rfcsr;
2257
2258 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2259 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2260 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2261 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2262 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2263
2264 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2265 if (info->default_power1 > POWER_BOUND)
2266 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
2267 else
2268 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2269 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2270
2271 if (rt2x00_rt(rt2x00dev, RT5392)) {
2272 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
2273 if (info->default_power1 > POWER_BOUND)
2274 rt2x00_set_field8(&rfcsr, RFCSR50_TX, POWER_BOUND);
2275 else
2276 rt2x00_set_field8(&rfcsr, RFCSR50_TX,
2277 info->default_power2);
2278 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2279 }
2280
2281 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2282 if (rt2x00_rt(rt2x00dev, RT5392)) {
2283 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2284 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2285 }
2286 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2287 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2288 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2289 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2290 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2291
2292 rt2800_adjust_freq_offset(rt2x00dev);
2293
2294 if (rf->channel <= 14) {
2295 int idx = rf->channel-1;
2296
2297 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
2298 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2299 /* r55/r59 value array of channel 1~14 */
2300 static const char r55_bt_rev[] = {0x83, 0x83,
2301 0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
2302 0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
2303 static const char r59_bt_rev[] = {0x0e, 0x0e,
2304 0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
2305 0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
2306
2307 rt2800_rfcsr_write(rt2x00dev, 55,
2308 r55_bt_rev[idx]);
2309 rt2800_rfcsr_write(rt2x00dev, 59,
2310 r59_bt_rev[idx]);
2311 } else {
2312 static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
2313 0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
2314 0x88, 0x88, 0x86, 0x85, 0x84};
2315
2316 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
2317 }
2318 } else {
2319 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2320 static const char r55_nonbt_rev[] = {0x23, 0x23,
2321 0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
2322 0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
2323 static const char r59_nonbt_rev[] = {0x07, 0x07,
2324 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
2325 0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
2326
2327 rt2800_rfcsr_write(rt2x00dev, 55,
2328 r55_nonbt_rev[idx]);
2329 rt2800_rfcsr_write(rt2x00dev, 59,
2330 r59_nonbt_rev[idx]);
2331 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
2332 rt2x00_rt(rt2x00dev, RT5392)) {
2333 static const char r59_non_bt[] = {0x8f, 0x8f,
2334 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
2335 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
2336
2337 rt2800_rfcsr_write(rt2x00dev, 59,
2338 r59_non_bt[idx]);
2339 }
2340 }
2341 }
2342 }
2343
2344 static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev,
2345 struct ieee80211_conf *conf,
2346 struct rf_channel *rf,
2347 struct channel_info *info)
2348 {
2349 u8 rfcsr, ep_reg;
2350 u32 reg;
2351 int power_bound;
2352
2353 /* TODO */
2354 const bool is_11b = false;
2355 const bool is_type_ep = false;
2356
2357 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
2358 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL,
2359 (rf->channel > 14 || conf_is_ht40(conf)) ? 5 : 0);
2360 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
2361
2362 /* Order of values on rf_channel entry: N, K, mod, R */
2363 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1 & 0xff);
2364
2365 rt2800_rfcsr_read(rt2x00dev, 9, &rfcsr);
2366 rt2x00_set_field8(&rfcsr, RFCSR9_K, rf->rf2 & 0xf);
2367 rt2x00_set_field8(&rfcsr, RFCSR9_N, (rf->rf1 & 0x100) >> 8);
2368 rt2x00_set_field8(&rfcsr, RFCSR9_MOD, ((rf->rf3 - 8) & 0x4) >> 2);
2369 rt2800_rfcsr_write(rt2x00dev, 9, rfcsr);
2370
2371 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2372 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf4 - 1);
2373 rt2x00_set_field8(&rfcsr, RFCSR11_MOD, (rf->rf3 - 8) & 0x3);
2374 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2375
2376 if (rf->channel <= 14) {
2377 rt2800_rfcsr_write(rt2x00dev, 10, 0x90);
2378 /* FIXME: RF11 owerwrite ? */
2379 rt2800_rfcsr_write(rt2x00dev, 11, 0x4A);
2380 rt2800_rfcsr_write(rt2x00dev, 12, 0x52);
2381 rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
2382 rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
2383 rt2800_rfcsr_write(rt2x00dev, 24, 0x4A);
2384 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
2385 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
2386 rt2800_rfcsr_write(rt2x00dev, 36, 0x80);
2387 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
2388 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
2389 rt2800_rfcsr_write(rt2x00dev, 39, 0x1B);
2390 rt2800_rfcsr_write(rt2x00dev, 40, 0x0D);
2391 rt2800_rfcsr_write(rt2x00dev, 41, 0x9B);
2392 rt2800_rfcsr_write(rt2x00dev, 42, 0xD5);
2393 rt2800_rfcsr_write(rt2x00dev, 43, 0x72);
2394 rt2800_rfcsr_write(rt2x00dev, 44, 0x0E);
2395 rt2800_rfcsr_write(rt2x00dev, 45, 0xA2);
2396 rt2800_rfcsr_write(rt2x00dev, 46, 0x6B);
2397 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
2398 rt2800_rfcsr_write(rt2x00dev, 51, 0x3E);
2399 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
2400 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
2401 rt2800_rfcsr_write(rt2x00dev, 56, 0xA1);
2402 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
2403 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
2404 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
2405 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
2406 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
2407
2408 /* TODO RF27 <- tssi */
2409
2410 rfcsr = rf->channel <= 10 ? 0x07 : 0x06;
2411 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2412 rt2800_rfcsr_write(rt2x00dev, 59, rfcsr);
2413
2414 if (is_11b) {
2415 /* CCK */
2416 rt2800_rfcsr_write(rt2x00dev, 31, 0xF8);
2417 rt2800_rfcsr_write(rt2x00dev, 32, 0xC0);
2418 if (is_type_ep)
2419 rt2800_rfcsr_write(rt2x00dev, 55, 0x06);
2420 else
2421 rt2800_rfcsr_write(rt2x00dev, 55, 0x47);
2422 } else {
2423 /* OFDM */
2424 if (is_type_ep)
2425 rt2800_rfcsr_write(rt2x00dev, 55, 0x03);
2426 else
2427 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
2428 }
2429
2430 power_bound = POWER_BOUND;
2431 ep_reg = 0x2;
2432 } else {
2433 rt2800_rfcsr_write(rt2x00dev, 10, 0x97);
2434 /* FIMXE: RF11 overwrite */
2435 rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
2436 rt2800_rfcsr_write(rt2x00dev, 25, 0xBF);
2437 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
2438 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
2439 rt2800_rfcsr_write(rt2x00dev, 37, 0x04);
2440 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
2441 rt2800_rfcsr_write(rt2x00dev, 40, 0x42);
2442 rt2800_rfcsr_write(rt2x00dev, 41, 0xBB);
2443 rt2800_rfcsr_write(rt2x00dev, 42, 0xD7);
2444 rt2800_rfcsr_write(rt2x00dev, 45, 0x41);
2445 rt2800_rfcsr_write(rt2x00dev, 48, 0x00);
2446 rt2800_rfcsr_write(rt2x00dev, 57, 0x77);
2447 rt2800_rfcsr_write(rt2x00dev, 60, 0x05);
2448 rt2800_rfcsr_write(rt2x00dev, 61, 0x01);
2449
2450 /* TODO RF27 <- tssi */
2451
2452 if (rf->channel >= 36 && rf->channel <= 64) {
2453
2454 rt2800_rfcsr_write(rt2x00dev, 12, 0x2E);
2455 rt2800_rfcsr_write(rt2x00dev, 13, 0x22);
2456 rt2800_rfcsr_write(rt2x00dev, 22, 0x60);
2457 rt2800_rfcsr_write(rt2x00dev, 23, 0x7F);
2458 if (rf->channel <= 50)
2459 rt2800_rfcsr_write(rt2x00dev, 24, 0x09);
2460 else if (rf->channel >= 52)
2461 rt2800_rfcsr_write(rt2x00dev, 24, 0x07);
2462 rt2800_rfcsr_write(rt2x00dev, 39, 0x1C);
2463 rt2800_rfcsr_write(rt2x00dev, 43, 0x5B);
2464 rt2800_rfcsr_write(rt2x00dev, 44, 0X40);
2465 rt2800_rfcsr_write(rt2x00dev, 46, 0X00);
2466 rt2800_rfcsr_write(rt2x00dev, 51, 0xFE);
2467 rt2800_rfcsr_write(rt2x00dev, 52, 0x0C);
2468 rt2800_rfcsr_write(rt2x00dev, 54, 0xF8);
2469 if (rf->channel <= 50) {
2470 rt2800_rfcsr_write(rt2x00dev, 55, 0x06),
2471 rt2800_rfcsr_write(rt2x00dev, 56, 0xD3);
2472 } else if (rf->channel >= 52) {
2473 rt2800_rfcsr_write(rt2x00dev, 55, 0x04);
2474 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
2475 }
2476
2477 rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
2478 rt2800_rfcsr_write(rt2x00dev, 59, 0x7F);
2479 rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
2480
2481 } else if (rf->channel >= 100 && rf->channel <= 165) {
2482
2483 rt2800_rfcsr_write(rt2x00dev, 12, 0x0E);
2484 rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
2485 rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
2486 if (rf->channel <= 153) {
2487 rt2800_rfcsr_write(rt2x00dev, 23, 0x3C);
2488 rt2800_rfcsr_write(rt2x00dev, 24, 0x06);
2489 } else if (rf->channel >= 155) {
2490 rt2800_rfcsr_write(rt2x00dev, 23, 0x38);
2491 rt2800_rfcsr_write(rt2x00dev, 24, 0x05);
2492 }
2493 if (rf->channel <= 138) {
2494 rt2800_rfcsr_write(rt2x00dev, 39, 0x1A);
2495 rt2800_rfcsr_write(rt2x00dev, 43, 0x3B);
2496 rt2800_rfcsr_write(rt2x00dev, 44, 0x20);
2497 rt2800_rfcsr_write(rt2x00dev, 46, 0x18);
2498 } else if (rf->channel >= 140) {
2499 rt2800_rfcsr_write(rt2x00dev, 39, 0x18);
2500 rt2800_rfcsr_write(rt2x00dev, 43, 0x1B);
2501 rt2800_rfcsr_write(rt2x00dev, 44, 0x10);
2502 rt2800_rfcsr_write(rt2x00dev, 46, 0X08);
2503 }
2504 if (rf->channel <= 124)
2505 rt2800_rfcsr_write(rt2x00dev, 51, 0xFC);
2506 else if (rf->channel >= 126)
2507 rt2800_rfcsr_write(rt2x00dev, 51, 0xEC);
2508 if (rf->channel <= 138)
2509 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
2510 else if (rf->channel >= 140)
2511 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
2512 rt2800_rfcsr_write(rt2x00dev, 54, 0xEB);
2513 if (rf->channel <= 138)
2514 rt2800_rfcsr_write(rt2x00dev, 55, 0x01);
2515 else if (rf->channel >= 140)
2516 rt2800_rfcsr_write(rt2x00dev, 55, 0x00);
2517 if (rf->channel <= 128)
2518 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
2519 else if (rf->channel >= 130)
2520 rt2800_rfcsr_write(rt2x00dev, 56, 0xAB);
2521 if (rf->channel <= 116)
2522 rt2800_rfcsr_write(rt2x00dev, 58, 0x1D);
2523 else if (rf->channel >= 118)
2524 rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
2525 if (rf->channel <= 138)
2526 rt2800_rfcsr_write(rt2x00dev, 59, 0x3F);
2527 else if (rf->channel >= 140)
2528 rt2800_rfcsr_write(rt2x00dev, 59, 0x7C);
2529 if (rf->channel <= 116)
2530 rt2800_rfcsr_write(rt2x00dev, 62, 0x1D);
2531 else if (rf->channel >= 118)
2532 rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
2533 }
2534
2535 power_bound = POWER_BOUND_5G;
2536 ep_reg = 0x3;
2537 }
2538
2539 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2540 if (info->default_power1 > power_bound)
2541 rt2x00_set_field8(&rfcsr, RFCSR49_TX, power_bound);
2542 else
2543 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2544 if (is_type_ep)
2545 rt2x00_set_field8(&rfcsr, RFCSR49_EP, ep_reg);
2546 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2547
2548 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
2549 if (info->default_power2 > power_bound)
2550 rt2x00_set_field8(&rfcsr, RFCSR50_TX, power_bound);
2551 else
2552 rt2x00_set_field8(&rfcsr, RFCSR50_TX, info->default_power2);
2553 if (is_type_ep)
2554 rt2x00_set_field8(&rfcsr, RFCSR50_EP, ep_reg);
2555 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2556
2557 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2558 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2559 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2560
2561 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD,
2562 rt2x00dev->default_ant.tx_chain_num >= 1);
2563 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
2564 rt2x00dev->default_ant.tx_chain_num == 2);
2565 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2566
2567 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD,
2568 rt2x00dev->default_ant.rx_chain_num >= 1);
2569 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
2570 rt2x00dev->default_ant.rx_chain_num == 2);
2571 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2572
2573 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2574 rt2800_rfcsr_write(rt2x00dev, 6, 0xe4);
2575
2576 if (conf_is_ht40(conf))
2577 rt2800_rfcsr_write(rt2x00dev, 30, 0x16);
2578 else
2579 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
2580
2581 if (!is_11b) {
2582 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
2583 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
2584 }
2585
2586 /* TODO proper frequency adjustment */
2587 rt2800_adjust_freq_offset(rt2x00dev);
2588
2589 /* TODO merge with others */
2590 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2591 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2592 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2593
2594 /* BBP settings */
2595 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
2596 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
2597 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
2598
2599 rt2800_bbp_write(rt2x00dev, 79, (rf->channel <= 14) ? 0x1C : 0x18);
2600 rt2800_bbp_write(rt2x00dev, 80, (rf->channel <= 14) ? 0x0E : 0x08);
2601 rt2800_bbp_write(rt2x00dev, 81, (rf->channel <= 14) ? 0x3A : 0x38);
2602 rt2800_bbp_write(rt2x00dev, 82, (rf->channel <= 14) ? 0x62 : 0x92);
2603
2604 /* GLRT band configuration */
2605 rt2800_bbp_write(rt2x00dev, 195, 128);
2606 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0xE0 : 0xF0);
2607 rt2800_bbp_write(rt2x00dev, 195, 129);
2608 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x1F : 0x1E);
2609 rt2800_bbp_write(rt2x00dev, 195, 130);
2610 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x38 : 0x28);
2611 rt2800_bbp_write(rt2x00dev, 195, 131);
2612 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x32 : 0x20);
2613 rt2800_bbp_write(rt2x00dev, 195, 133);
2614 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x28 : 0x7F);
2615 rt2800_bbp_write(rt2x00dev, 195, 124);
2616 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x19 : 0x7F);
2617 }
2618
2619 static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev *rt2x00dev,
2620 const unsigned int word,
2621 const u8 value)
2622 {
2623 u8 chain, reg;
2624
2625 for (chain = 0; chain < rt2x00dev->default_ant.rx_chain_num; chain++) {
2626 rt2800_bbp_read(rt2x00dev, 27, &reg);
2627 rt2x00_set_field8(&reg, BBP27_RX_CHAIN_SEL, chain);
2628 rt2800_bbp_write(rt2x00dev, 27, reg);
2629
2630 rt2800_bbp_write(rt2x00dev, word, value);
2631 }
2632 }
2633
2634 static void rt2800_iq_calibrate(struct rt2x00_dev *rt2x00dev, int channel)
2635 {
2636 u8 cal;
2637
2638 /* TX0 IQ Gain */
2639 rt2800_bbp_write(rt2x00dev, 158, 0x2c);
2640 if (channel <= 14)
2641 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX0_2G);
2642 else if (channel >= 36 && channel <= 64)
2643 cal = rt2x00_eeprom_byte(rt2x00dev,
2644 EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5G);
2645 else if (channel >= 100 && channel <= 138)
2646 cal = rt2x00_eeprom_byte(rt2x00dev,
2647 EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5G);
2648 else if (channel >= 140 && channel <= 165)
2649 cal = rt2x00_eeprom_byte(rt2x00dev,
2650 EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5G);
2651 else
2652 cal = 0;
2653 rt2800_bbp_write(rt2x00dev, 159, cal);
2654
2655 /* TX0 IQ Phase */
2656 rt2800_bbp_write(rt2x00dev, 158, 0x2d);
2657 if (channel <= 14)
2658 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX0_2G);
2659 else if (channel >= 36 && channel <= 64)
2660 cal = rt2x00_eeprom_byte(rt2x00dev,
2661 EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5G);
2662 else if (channel >= 100 && channel <= 138)
2663 cal = rt2x00_eeprom_byte(rt2x00dev,
2664 EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5G);
2665 else if (channel >= 140 && channel <= 165)
2666 cal = rt2x00_eeprom_byte(rt2x00dev,
2667 EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5G);
2668 else
2669 cal = 0;
2670 rt2800_bbp_write(rt2x00dev, 159, cal);
2671
2672 /* TX1 IQ Gain */
2673 rt2800_bbp_write(rt2x00dev, 158, 0x4a);
2674 if (channel <= 14)
2675 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX1_2G);
2676 else if (channel >= 36 && channel <= 64)
2677 cal = rt2x00_eeprom_byte(rt2x00dev,
2678 EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5G);
2679 else if (channel >= 100 && channel <= 138)
2680 cal = rt2x00_eeprom_byte(rt2x00dev,
2681 EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5G);
2682 else if (channel >= 140 && channel <= 165)
2683 cal = rt2x00_eeprom_byte(rt2x00dev,
2684 EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5G);
2685 else
2686 cal = 0;
2687 rt2800_bbp_write(rt2x00dev, 159, cal);
2688
2689 /* TX1 IQ Phase */
2690 rt2800_bbp_write(rt2x00dev, 158, 0x4b);
2691 if (channel <= 14)
2692 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX1_2G);
2693 else if (channel >= 36 && channel <= 64)
2694 cal = rt2x00_eeprom_byte(rt2x00dev,
2695 EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5G);
2696 else if (channel >= 100 && channel <= 138)
2697 cal = rt2x00_eeprom_byte(rt2x00dev,
2698 EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5G);
2699 else if (channel >= 140 && channel <= 165)
2700 cal = rt2x00_eeprom_byte(rt2x00dev,
2701 EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5G);
2702 else
2703 cal = 0;
2704 rt2800_bbp_write(rt2x00dev, 159, cal);
2705
2706 /* FIXME: possible RX0, RX1 callibration ? */
2707
2708 /* RF IQ compensation control */
2709 rt2800_bbp_write(rt2x00dev, 158, 0x04);
2710 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_RF_IQ_COMPENSATION_CONTROL);
2711 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
2712
2713 /* RF IQ imbalance compensation control */
2714 rt2800_bbp_write(rt2x00dev, 158, 0x03);
2715 cal = rt2x00_eeprom_byte(rt2x00dev,
2716 EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CONTROL);
2717 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
2718 }
2719
2720 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
2721 struct ieee80211_conf *conf,
2722 struct rf_channel *rf,
2723 struct channel_info *info)
2724 {
2725 u32 reg;
2726 unsigned int tx_pin;
2727 u8 bbp, rfcsr;
2728
2729 if (rf->channel <= 14) {
2730 info->default_power1 = TXPOWER_G_TO_DEV(info->default_power1);
2731 info->default_power2 = TXPOWER_G_TO_DEV(info->default_power2);
2732 } else {
2733 info->default_power1 = TXPOWER_A_TO_DEV(info->default_power1);
2734 info->default_power2 = TXPOWER_A_TO_DEV(info->default_power2);
2735 }
2736
2737 switch (rt2x00dev->chip.rf) {
2738 case RF2020:
2739 case RF3020:
2740 case RF3021:
2741 case RF3022:
2742 case RF3320:
2743 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
2744 break;
2745 case RF3052:
2746 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);
2747 break;
2748 case RF3290:
2749 rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info);
2750 break;
2751 case RF3322:
2752 rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info);
2753 break;
2754 case RF5360:
2755 case RF5370:
2756 case RF5372:
2757 case RF5390:
2758 case RF5392:
2759 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
2760 break;
2761 case RF5592:
2762 rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info);
2763 break;
2764 default:
2765 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
2766 }
2767
2768 if (rt2x00_rf(rt2x00dev, RF3290) ||
2769 rt2x00_rf(rt2x00dev, RF3322) ||
2770 rt2x00_rf(rt2x00dev, RF5360) ||
2771 rt2x00_rf(rt2x00dev, RF5370) ||
2772 rt2x00_rf(rt2x00dev, RF5372) ||
2773 rt2x00_rf(rt2x00dev, RF5390) ||
2774 rt2x00_rf(rt2x00dev, RF5392)) {
2775 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2776 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0);
2777 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0);
2778 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2779
2780 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2781 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2782 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2783 }
2784
2785 /*
2786 * Change BBP settings
2787 */
2788 if (rt2x00_rt(rt2x00dev, RT3352)) {
2789 rt2800_bbp_write(rt2x00dev, 27, 0x0);
2790 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
2791 rt2800_bbp_write(rt2x00dev, 27, 0x20);
2792 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
2793 } else {
2794 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
2795 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
2796 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
2797 rt2800_bbp_write(rt2x00dev, 86, 0);
2798 }
2799
2800 if (rf->channel <= 14) {
2801 if (!rt2x00_rt(rt2x00dev, RT5390) &&
2802 !rt2x00_rt(rt2x00dev, RT5392)) {
2803 if (test_bit(CAPABILITY_EXTERNAL_LNA_BG,
2804 &rt2x00dev->cap_flags)) {
2805 rt2800_bbp_write(rt2x00dev, 82, 0x62);
2806 rt2800_bbp_write(rt2x00dev, 75, 0x46);
2807 } else {
2808 rt2800_bbp_write(rt2x00dev, 82, 0x84);
2809 rt2800_bbp_write(rt2x00dev, 75, 0x50);
2810 }
2811 }
2812 } else {
2813 if (rt2x00_rt(rt2x00dev, RT3572))
2814 rt2800_bbp_write(rt2x00dev, 82, 0x94);
2815 else
2816 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
2817
2818 if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags))
2819 rt2800_bbp_write(rt2x00dev, 75, 0x46);
2820 else
2821 rt2800_bbp_write(rt2x00dev, 75, 0x50);
2822 }
2823
2824 rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
2825 rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
2826 rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
2827 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
2828 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
2829
2830 if (rt2x00_rt(rt2x00dev, RT3572))
2831 rt2800_rfcsr_write(rt2x00dev, 8, 0);
2832
2833 tx_pin = 0;
2834
2835 switch (rt2x00dev->default_ant.tx_chain_num) {
2836 case 3:
2837 /* Turn on tertiary PAs */
2838 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN,
2839 rf->channel > 14);
2840 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN,
2841 rf->channel <= 14);
2842 /* fall-through */
2843 case 2:
2844 /* Turn on secondary PAs */
2845 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN,
2846 rf->channel > 14);
2847 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN,
2848 rf->channel <= 14);
2849 /* fall-through */
2850 case 1:
2851 /* Turn on primary PAs */
2852 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN,
2853 rf->channel > 14);
2854 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
2855 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
2856 else
2857 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN,
2858 rf->channel <= 14);
2859 break;
2860 }
2861
2862 switch (rt2x00dev->default_ant.rx_chain_num) {
2863 case 3:
2864 /* Turn on tertiary LNAs */
2865 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A2_EN, 1);
2866 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G2_EN, 1);
2867 /* fall-through */
2868 case 2:
2869 /* Turn on secondary LNAs */
2870 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
2871 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
2872 /* fall-through */
2873 case 1:
2874 /* Turn on primary LNAs */
2875 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
2876 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
2877 break;
2878 }
2879
2880 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
2881 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
2882
2883 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
2884
2885 if (rt2x00_rt(rt2x00dev, RT3572))
2886 rt2800_rfcsr_write(rt2x00dev, 8, 0x80);
2887
2888 if (rt2x00_rt(rt2x00dev, RT5592)) {
2889 rt2800_bbp_write(rt2x00dev, 195, 141);
2890 rt2800_bbp_write(rt2x00dev, 196, conf_is_ht40(conf) ? 0x10 : 0x1a);
2891
2892 /* AGC init */
2893 reg = (rf->channel <= 14 ? 0x1c : 0x24) + 2 * rt2x00dev->lna_gain;
2894 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
2895
2896 rt2800_iq_calibrate(rt2x00dev, rf->channel);
2897 }
2898
2899 rt2800_bbp_read(rt2x00dev, 4, &bbp);
2900 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
2901 rt2800_bbp_write(rt2x00dev, 4, bbp);
2902
2903 rt2800_bbp_read(rt2x00dev, 3, &bbp);
2904 rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
2905 rt2800_bbp_write(rt2x00dev, 3, bbp);
2906
2907 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
2908 if (conf_is_ht40(conf)) {
2909 rt2800_bbp_write(rt2x00dev, 69, 0x1a);
2910 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
2911 rt2800_bbp_write(rt2x00dev, 73, 0x16);
2912 } else {
2913 rt2800_bbp_write(rt2x00dev, 69, 0x16);
2914 rt2800_bbp_write(rt2x00dev, 70, 0x08);
2915 rt2800_bbp_write(rt2x00dev, 73, 0x11);
2916 }
2917 }
2918
2919 msleep(1);
2920
2921 /*
2922 * Clear channel statistic counters
2923 */
2924 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg);
2925 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg);
2926 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
2927
2928 /*
2929 * Clear update flag
2930 */
2931 if (rt2x00_rt(rt2x00dev, RT3352)) {
2932 rt2800_bbp_read(rt2x00dev, 49, &bbp);
2933 rt2x00_set_field8(&bbp, BBP49_UPDATE_FLAG, 0);
2934 rt2800_bbp_write(rt2x00dev, 49, bbp);
2935 }
2936 }
2937
2938 static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
2939 {
2940 u8 tssi_bounds[9];
2941 u8 current_tssi;
2942 u16 eeprom;
2943 u8 step;
2944 int i;
2945
2946 /*
2947 * Read TSSI boundaries for temperature compensation from
2948 * the EEPROM.
2949 *
2950 * Array idx 0 1 2 3 4 5 6 7 8
2951 * Matching Delta value -4 -3 -2 -1 0 +1 +2 +3 +4
2952 * Example TSSI bounds 0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
2953 */
2954 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
2955 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1, &eeprom);
2956 tssi_bounds[0] = rt2x00_get_field16(eeprom,
2957 EEPROM_TSSI_BOUND_BG1_MINUS4);
2958 tssi_bounds[1] = rt2x00_get_field16(eeprom,
2959 EEPROM_TSSI_BOUND_BG1_MINUS3);
2960
2961 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2, &eeprom);
2962 tssi_bounds[2] = rt2x00_get_field16(eeprom,
2963 EEPROM_TSSI_BOUND_BG2_MINUS2);
2964 tssi_bounds[3] = rt2x00_get_field16(eeprom,
2965 EEPROM_TSSI_BOUND_BG2_MINUS1);
2966
2967 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3, &eeprom);
2968 tssi_bounds[4] = rt2x00_get_field16(eeprom,
2969 EEPROM_TSSI_BOUND_BG3_REF);
2970 tssi_bounds[5] = rt2x00_get_field16(eeprom,
2971 EEPROM_TSSI_BOUND_BG3_PLUS1);
2972
2973 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4, &eeprom);
2974 tssi_bounds[6] = rt2x00_get_field16(eeprom,
2975 EEPROM_TSSI_BOUND_BG4_PLUS2);
2976 tssi_bounds[7] = rt2x00_get_field16(eeprom,
2977 EEPROM_TSSI_BOUND_BG4_PLUS3);
2978
2979 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5, &eeprom);
2980 tssi_bounds[8] = rt2x00_get_field16(eeprom,
2981 EEPROM_TSSI_BOUND_BG5_PLUS4);
2982
2983 step = rt2x00_get_field16(eeprom,
2984 EEPROM_TSSI_BOUND_BG5_AGC_STEP);
2985 } else {
2986 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1, &eeprom);
2987 tssi_bounds[0] = rt2x00_get_field16(eeprom,
2988 EEPROM_TSSI_BOUND_A1_MINUS4);
2989 tssi_bounds[1] = rt2x00_get_field16(eeprom,
2990 EEPROM_TSSI_BOUND_A1_MINUS3);
2991
2992 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2, &eeprom);
2993 tssi_bounds[2] = rt2x00_get_field16(eeprom,
2994 EEPROM_TSSI_BOUND_A2_MINUS2);
2995 tssi_bounds[3] = rt2x00_get_field16(eeprom,
2996 EEPROM_TSSI_BOUND_A2_MINUS1);
2997
2998 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3, &eeprom);
2999 tssi_bounds[4] = rt2x00_get_field16(eeprom,
3000 EEPROM_TSSI_BOUND_A3_REF);
3001 tssi_bounds[5] = rt2x00_get_field16(eeprom,
3002 EEPROM_TSSI_BOUND_A3_PLUS1);
3003
3004 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4, &eeprom);
3005 tssi_bounds[6] = rt2x00_get_field16(eeprom,
3006 EEPROM_TSSI_BOUND_A4_PLUS2);
3007 tssi_bounds[7] = rt2x00_get_field16(eeprom,
3008 EEPROM_TSSI_BOUND_A4_PLUS3);
3009
3010 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5, &eeprom);
3011 tssi_bounds[8] = rt2x00_get_field16(eeprom,
3012 EEPROM_TSSI_BOUND_A5_PLUS4);
3013
3014 step = rt2x00_get_field16(eeprom,
3015 EEPROM_TSSI_BOUND_A5_AGC_STEP);
3016 }
3017
3018 /*
3019 * Check if temperature compensation is supported.
3020 */
3021 if (tssi_bounds[4] == 0xff || step == 0xff)
3022 return 0;
3023
3024 /*
3025 * Read current TSSI (BBP 49).
3026 */
3027 rt2800_bbp_read(rt2x00dev, 49, &current_tssi);
3028
3029 /*
3030 * Compare TSSI value (BBP49) with the compensation boundaries
3031 * from the EEPROM and increase or decrease tx power.
3032 */
3033 for (i = 0; i <= 3; i++) {
3034 if (current_tssi > tssi_bounds[i])
3035 break;
3036 }
3037
3038 if (i == 4) {
3039 for (i = 8; i >= 5; i--) {
3040 if (current_tssi < tssi_bounds[i])
3041 break;
3042 }
3043 }
3044
3045 return (i - 4) * step;
3046 }
3047
3048 static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
3049 enum ieee80211_band band)
3050 {
3051 u16 eeprom;
3052 u8 comp_en;
3053 u8 comp_type;
3054 int comp_value = 0;
3055
3056 rt2800_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom);
3057
3058 /*
3059 * HT40 compensation not required.
3060 */
3061 if (eeprom == 0xffff ||
3062 !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
3063 return 0;
3064
3065 if (band == IEEE80211_BAND_2GHZ) {
3066 comp_en = rt2x00_get_field16(eeprom,
3067 EEPROM_TXPOWER_DELTA_ENABLE_2G);
3068 if (comp_en) {
3069 comp_type = rt2x00_get_field16(eeprom,
3070 EEPROM_TXPOWER_DELTA_TYPE_2G);
3071 comp_value = rt2x00_get_field16(eeprom,
3072 EEPROM_TXPOWER_DELTA_VALUE_2G);
3073 if (!comp_type)
3074 comp_value = -comp_value;
3075 }
3076 } else {
3077 comp_en = rt2x00_get_field16(eeprom,
3078 EEPROM_TXPOWER_DELTA_ENABLE_5G);
3079 if (comp_en) {
3080 comp_type = rt2x00_get_field16(eeprom,
3081 EEPROM_TXPOWER_DELTA_TYPE_5G);
3082 comp_value = rt2x00_get_field16(eeprom,
3083 EEPROM_TXPOWER_DELTA_VALUE_5G);
3084 if (!comp_type)
3085 comp_value = -comp_value;
3086 }
3087 }
3088
3089 return comp_value;
3090 }
3091
3092 static int rt2800_get_txpower_reg_delta(struct rt2x00_dev *rt2x00dev,
3093 int power_level, int max_power)
3094 {
3095 int delta;
3096
3097 if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags))
3098 return 0;
3099
3100 /*
3101 * XXX: We don't know the maximum transmit power of our hardware since
3102 * the EEPROM doesn't expose it. We only know that we are calibrated
3103 * to 100% tx power.
3104 *
3105 * Hence, we assume the regulatory limit that cfg80211 calulated for
3106 * the current channel is our maximum and if we are requested to lower
3107 * the value we just reduce our tx power accordingly.
3108 */
3109 delta = power_level - max_power;
3110 return min(delta, 0);
3111 }
3112
3113 static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
3114 enum ieee80211_band band, int power_level,
3115 u8 txpower, int delta)
3116 {
3117 u16 eeprom;
3118 u8 criterion;
3119 u8 eirp_txpower;
3120 u8 eirp_txpower_criterion;
3121 u8 reg_limit;
3122
3123 if (rt2x00_rt(rt2x00dev, RT3593))
3124 return min_t(u8, txpower, 0xc);
3125
3126 if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags)) {
3127 /*
3128 * Check if eirp txpower exceed txpower_limit.
3129 * We use OFDM 6M as criterion and its eirp txpower
3130 * is stored at EEPROM_EIRP_MAX_TX_POWER.
3131 * .11b data rate need add additional 4dbm
3132 * when calculating eirp txpower.
3133 */
3134 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3135 1, &eeprom);
3136 criterion = rt2x00_get_field16(eeprom,
3137 EEPROM_TXPOWER_BYRATE_RATE0);
3138
3139 rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER,
3140 &eeprom);
3141
3142 if (band == IEEE80211_BAND_2GHZ)
3143 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
3144 EEPROM_EIRP_MAX_TX_POWER_2GHZ);
3145 else
3146 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
3147 EEPROM_EIRP_MAX_TX_POWER_5GHZ);
3148
3149 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
3150 (is_rate_b ? 4 : 0) + delta;
3151
3152 reg_limit = (eirp_txpower > power_level) ?
3153 (eirp_txpower - power_level) : 0;
3154 } else
3155 reg_limit = 0;
3156
3157 txpower = max(0, txpower + delta - reg_limit);
3158 return min_t(u8, txpower, 0xc);
3159 }
3160
3161
3162 enum {
3163 TX_PWR_CFG_0_IDX,
3164 TX_PWR_CFG_1_IDX,
3165 TX_PWR_CFG_2_IDX,
3166 TX_PWR_CFG_3_IDX,
3167 TX_PWR_CFG_4_IDX,
3168 TX_PWR_CFG_5_IDX,
3169 TX_PWR_CFG_6_IDX,
3170 TX_PWR_CFG_7_IDX,
3171 TX_PWR_CFG_8_IDX,
3172 TX_PWR_CFG_9_IDX,
3173 TX_PWR_CFG_0_EXT_IDX,
3174 TX_PWR_CFG_1_EXT_IDX,
3175 TX_PWR_CFG_2_EXT_IDX,
3176 TX_PWR_CFG_3_EXT_IDX,
3177 TX_PWR_CFG_4_EXT_IDX,
3178 TX_PWR_CFG_IDX_COUNT,
3179 };
3180
3181 static void rt2800_config_txpower_rt3593(struct rt2x00_dev *rt2x00dev,
3182 struct ieee80211_channel *chan,
3183 int power_level)
3184 {
3185 u8 txpower;
3186 u16 eeprom;
3187 u32 regs[TX_PWR_CFG_IDX_COUNT];
3188 unsigned int offset;
3189 enum ieee80211_band band = chan->band;
3190 int delta;
3191 int i;
3192
3193 memset(regs, '\0', sizeof(regs));
3194
3195 /* TODO: adapt TX power reduction from the rt28xx code */
3196
3197 /* calculate temperature compensation delta */
3198 delta = rt2800_get_gain_calibration_delta(rt2x00dev);
3199
3200 if (band == IEEE80211_BAND_5GHZ)
3201 offset = 16;
3202 else
3203 offset = 0;
3204
3205 if (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
3206 offset += 8;
3207
3208 /* read the next four txpower values */
3209 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3210 offset, &eeprom);
3211
3212 /* CCK 1MBS,2MBS */
3213 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3214 txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
3215 txpower, delta);
3216 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3217 TX_PWR_CFG_0_CCK1_CH0, txpower);
3218 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3219 TX_PWR_CFG_0_CCK1_CH1, txpower);
3220 rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
3221 TX_PWR_CFG_0_EXT_CCK1_CH2, txpower);
3222
3223 /* CCK 5.5MBS,11MBS */
3224 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3225 txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
3226 txpower, delta);
3227 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3228 TX_PWR_CFG_0_CCK5_CH0, txpower);
3229 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3230 TX_PWR_CFG_0_CCK5_CH1, txpower);
3231 rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
3232 TX_PWR_CFG_0_EXT_CCK5_CH2, txpower);
3233
3234 /* OFDM 6MBS,9MBS */
3235 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3236 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3237 txpower, delta);
3238 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3239 TX_PWR_CFG_0_OFDM6_CH0, txpower);
3240 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3241 TX_PWR_CFG_0_OFDM6_CH1, txpower);
3242 rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
3243 TX_PWR_CFG_0_EXT_OFDM6_CH2, txpower);
3244
3245 /* OFDM 12MBS,18MBS */
3246 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3247 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3248 txpower, delta);
3249 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3250 TX_PWR_CFG_0_OFDM12_CH0, txpower);
3251 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3252 TX_PWR_CFG_0_OFDM12_CH1, txpower);
3253 rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
3254 TX_PWR_CFG_0_EXT_OFDM12_CH2, txpower);
3255
3256 /* read the next four txpower values */
3257 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3258 offset + 1, &eeprom);
3259
3260 /* OFDM 24MBS,36MBS */
3261 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3262 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3263 txpower, delta);
3264 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3265 TX_PWR_CFG_1_OFDM24_CH0, txpower);
3266 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3267 TX_PWR_CFG_1_OFDM24_CH1, txpower);
3268 rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
3269 TX_PWR_CFG_1_EXT_OFDM24_CH2, txpower);
3270
3271 /* OFDM 48MBS */
3272 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3273 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3274 txpower, delta);
3275 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3276 TX_PWR_CFG_1_OFDM48_CH0, txpower);
3277 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3278 TX_PWR_CFG_1_OFDM48_CH1, txpower);
3279 rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
3280 TX_PWR_CFG_1_EXT_OFDM48_CH2, txpower);
3281
3282 /* OFDM 54MBS */
3283 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3284 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3285 txpower, delta);
3286 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3287 TX_PWR_CFG_7_OFDM54_CH0, txpower);
3288 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3289 TX_PWR_CFG_7_OFDM54_CH1, txpower);
3290 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3291 TX_PWR_CFG_7_OFDM54_CH2, txpower);
3292
3293 /* read the next four txpower values */
3294 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3295 offset + 2, &eeprom);
3296
3297 /* MCS 0,1 */
3298 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3299 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3300 txpower, delta);
3301 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3302 TX_PWR_CFG_1_MCS0_CH0, txpower);
3303 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3304 TX_PWR_CFG_1_MCS0_CH1, txpower);
3305 rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
3306 TX_PWR_CFG_1_EXT_MCS0_CH2, txpower);
3307
3308 /* MCS 2,3 */
3309 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3310 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3311 txpower, delta);
3312 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3313 TX_PWR_CFG_1_MCS2_CH0, txpower);
3314 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3315 TX_PWR_CFG_1_MCS2_CH1, txpower);
3316 rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
3317 TX_PWR_CFG_1_EXT_MCS2_CH2, txpower);
3318
3319 /* MCS 4,5 */
3320 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3321 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3322 txpower, delta);
3323 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3324 TX_PWR_CFG_2_MCS4_CH0, txpower);
3325 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3326 TX_PWR_CFG_2_MCS4_CH1, txpower);
3327 rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
3328 TX_PWR_CFG_2_EXT_MCS4_CH2, txpower);
3329
3330 /* MCS 6 */
3331 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3332 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3333 txpower, delta);
3334 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3335 TX_PWR_CFG_2_MCS6_CH0, txpower);
3336 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3337 TX_PWR_CFG_2_MCS6_CH1, txpower);
3338 rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
3339 TX_PWR_CFG_2_EXT_MCS6_CH2, txpower);
3340
3341 /* read the next four txpower values */
3342 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3343 offset + 3, &eeprom);
3344
3345 /* MCS 7 */
3346 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3347 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3348 txpower, delta);
3349 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3350 TX_PWR_CFG_7_MCS7_CH0, txpower);
3351 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3352 TX_PWR_CFG_7_MCS7_CH1, txpower);
3353 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3354 TX_PWR_CFG_7_MCS7_CH2, txpower);
3355
3356 /* MCS 8,9 */
3357 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3358 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3359 txpower, delta);
3360 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3361 TX_PWR_CFG_2_MCS8_CH0, txpower);
3362 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3363 TX_PWR_CFG_2_MCS8_CH1, txpower);
3364 rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
3365 TX_PWR_CFG_2_EXT_MCS8_CH2, txpower);
3366
3367 /* MCS 10,11 */
3368 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3369 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3370 txpower, delta);
3371 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3372 TX_PWR_CFG_2_MCS10_CH0, txpower);
3373 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3374 TX_PWR_CFG_2_MCS10_CH1, txpower);
3375 rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
3376 TX_PWR_CFG_2_EXT_MCS10_CH2, txpower);
3377
3378 /* MCS 12,13 */
3379 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3380 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3381 txpower, delta);
3382 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3383 TX_PWR_CFG_3_MCS12_CH0, txpower);
3384 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3385 TX_PWR_CFG_3_MCS12_CH1, txpower);
3386 rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
3387 TX_PWR_CFG_3_EXT_MCS12_CH2, txpower);
3388
3389 /* read the next four txpower values */
3390 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3391 offset + 4, &eeprom);
3392
3393 /* MCS 14 */
3394 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3395 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3396 txpower, delta);
3397 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3398 TX_PWR_CFG_3_MCS14_CH0, txpower);
3399 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3400 TX_PWR_CFG_3_MCS14_CH1, txpower);
3401 rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
3402 TX_PWR_CFG_3_EXT_MCS14_CH2, txpower);
3403
3404 /* MCS 15 */
3405 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3406 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3407 txpower, delta);
3408 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3409 TX_PWR_CFG_8_MCS15_CH0, txpower);
3410 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3411 TX_PWR_CFG_8_MCS15_CH1, txpower);
3412 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3413 TX_PWR_CFG_8_MCS15_CH2, txpower);
3414
3415 /* MCS 16,17 */
3416 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3417 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3418 txpower, delta);
3419 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3420 TX_PWR_CFG_5_MCS16_CH0, txpower);
3421 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3422 TX_PWR_CFG_5_MCS16_CH1, txpower);
3423 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3424 TX_PWR_CFG_5_MCS16_CH2, txpower);
3425
3426 /* MCS 18,19 */
3427 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3428 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3429 txpower, delta);
3430 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3431 TX_PWR_CFG_5_MCS18_CH0, txpower);
3432 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3433 TX_PWR_CFG_5_MCS18_CH1, txpower);
3434 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3435 TX_PWR_CFG_5_MCS18_CH2, txpower);
3436
3437 /* read the next four txpower values */
3438 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3439 offset + 5, &eeprom);
3440
3441 /* MCS 20,21 */
3442 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3443 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3444 txpower, delta);
3445 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3446 TX_PWR_CFG_6_MCS20_CH0, txpower);
3447 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3448 TX_PWR_CFG_6_MCS20_CH1, txpower);
3449 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3450 TX_PWR_CFG_6_MCS20_CH2, txpower);
3451
3452 /* MCS 22 */
3453 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3454 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3455 txpower, delta);
3456 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3457 TX_PWR_CFG_6_MCS22_CH0, txpower);
3458 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3459 TX_PWR_CFG_6_MCS22_CH1, txpower);
3460 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3461 TX_PWR_CFG_6_MCS22_CH2, txpower);
3462
3463 /* MCS 23 */
3464 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3465 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3466 txpower, delta);
3467 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3468 TX_PWR_CFG_8_MCS23_CH0, txpower);
3469 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3470 TX_PWR_CFG_8_MCS23_CH1, txpower);
3471 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3472 TX_PWR_CFG_8_MCS23_CH2, txpower);
3473
3474 /* read the next four txpower values */
3475 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3476 offset + 6, &eeprom);
3477
3478 /* STBC, MCS 0,1 */
3479 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3480 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3481 txpower, delta);
3482 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3483 TX_PWR_CFG_3_STBC0_CH0, txpower);
3484 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3485 TX_PWR_CFG_3_STBC0_CH1, txpower);
3486 rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
3487 TX_PWR_CFG_3_EXT_STBC0_CH2, txpower);
3488
3489 /* STBC, MCS 2,3 */
3490 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3491 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3492 txpower, delta);
3493 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3494 TX_PWR_CFG_3_STBC2_CH0, txpower);
3495 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3496 TX_PWR_CFG_3_STBC2_CH1, txpower);
3497 rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
3498 TX_PWR_CFG_3_EXT_STBC2_CH2, txpower);
3499
3500 /* STBC, MCS 4,5 */
3501 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3502 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3503 txpower, delta);
3504 rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE0, txpower);
3505 rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE1, txpower);
3506 rt2x00_set_field32(&regs[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE0,
3507 txpower);
3508
3509 /* STBC, MCS 6 */
3510 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3511 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3512 txpower, delta);
3513 rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE2, txpower);
3514 rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE3, txpower);
3515 rt2x00_set_field32(&regs[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE2,
3516 txpower);
3517
3518 /* read the next four txpower values */
3519 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3520 offset + 7, &eeprom);
3521
3522 /* STBC, MCS 7 */
3523 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3524 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3525 txpower, delta);
3526 rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
3527 TX_PWR_CFG_9_STBC7_CH0, txpower);
3528 rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
3529 TX_PWR_CFG_9_STBC7_CH1, txpower);
3530 rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
3531 TX_PWR_CFG_9_STBC7_CH2, txpower);
3532
3533 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, regs[TX_PWR_CFG_0_IDX]);
3534 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, regs[TX_PWR_CFG_1_IDX]);
3535 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, regs[TX_PWR_CFG_2_IDX]);
3536 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, regs[TX_PWR_CFG_3_IDX]);
3537 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, regs[TX_PWR_CFG_4_IDX]);
3538 rt2800_register_write(rt2x00dev, TX_PWR_CFG_5, regs[TX_PWR_CFG_5_IDX]);
3539 rt2800_register_write(rt2x00dev, TX_PWR_CFG_6, regs[TX_PWR_CFG_6_IDX]);
3540 rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, regs[TX_PWR_CFG_7_IDX]);
3541 rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, regs[TX_PWR_CFG_8_IDX]);
3542 rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, regs[TX_PWR_CFG_9_IDX]);
3543
3544 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0_EXT,
3545 regs[TX_PWR_CFG_0_EXT_IDX]);
3546 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1_EXT,
3547 regs[TX_PWR_CFG_1_EXT_IDX]);
3548 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2_EXT,
3549 regs[TX_PWR_CFG_2_EXT_IDX]);
3550 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3_EXT,
3551 regs[TX_PWR_CFG_3_EXT_IDX]);
3552 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4_EXT,
3553 regs[TX_PWR_CFG_4_EXT_IDX]);
3554
3555 for (i = 0; i < TX_PWR_CFG_IDX_COUNT; i++)
3556 rt2x00_dbg(rt2x00dev,
3557 "band:%cGHz, BW:%c0MHz, TX_PWR_CFG_%d%s = %08lx\n",
3558 (band == IEEE80211_BAND_5GHZ) ? '5' : '2',
3559 (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) ?
3560 '4' : '2',
3561 (i > TX_PWR_CFG_9_IDX) ?
3562 (i - TX_PWR_CFG_9_IDX - 1) : i,
3563 (i > TX_PWR_CFG_9_IDX) ? "_EXT" : "",
3564 (unsigned long) regs[i]);
3565 }
3566
3567 /*
3568 * We configure transmit power using MAC TX_PWR_CFG_{0,...,N} registers and
3569 * BBP R1 register. TX_PWR_CFG_X allow to configure per rate TX power values,
3570 * 4 bits for each rate (tune from 0 to 15 dBm). BBP_R1 controls transmit power
3571 * for all rates, but allow to set only 4 discrete values: -12, -6, 0 and 6 dBm.
3572 * Reference per rate transmit power values are located in the EEPROM at
3573 * EEPROM_TXPOWER_BYRATE offset. We adjust them and BBP R1 settings according to
3574 * current conditions (i.e. band, bandwidth, temperature, user settings).
3575 */
3576 static void rt2800_config_txpower_rt28xx(struct rt2x00_dev *rt2x00dev,
3577 struct ieee80211_channel *chan,
3578 int power_level)
3579 {
3580 u8 txpower, r1;
3581 u16 eeprom;
3582 u32 reg, offset;
3583 int i, is_rate_b, delta, power_ctrl;
3584 enum ieee80211_band band = chan->band;
3585
3586 /*
3587 * Calculate HT40 compensation. For 40MHz we need to add or subtract
3588 * value read from EEPROM (different for 2GHz and for 5GHz).
3589 */
3590 delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
3591
3592 /*
3593 * Calculate temperature compensation. Depends on measurement of current
3594 * TSSI (Transmitter Signal Strength Indication) we know TX power (due
3595 * to temperature or maybe other factors) is smaller or bigger than
3596 * expected. We adjust it, based on TSSI reference and boundaries values
3597 * provided in EEPROM.
3598 */
3599 delta += rt2800_get_gain_calibration_delta(rt2x00dev);
3600
3601 /*
3602 * Decrease power according to user settings, on devices with unknown
3603 * maximum tx power. For other devices we take user power_level into
3604 * consideration on rt2800_compensate_txpower().
3605 */
3606 delta += rt2800_get_txpower_reg_delta(rt2x00dev, power_level,
3607 chan->max_power);
3608
3609 /*
3610 * BBP_R1 controls TX power for all rates, it allow to set the following
3611 * gains -12, -6, 0, +6 dBm by setting values 2, 1, 0, 3 respectively.
3612 *
3613 * TODO: we do not use +6 dBm option to do not increase power beyond
3614 * regulatory limit, however this could be utilized for devices with
3615 * CAPABILITY_POWER_LIMIT.
3616 *
3617 * TODO: add different temperature compensation code for RT3290 & RT5390
3618 * to allow to use BBP_R1 for those chips.
3619 */
3620 if (!rt2x00_rt(rt2x00dev, RT3290) &&
3621 !rt2x00_rt(rt2x00dev, RT5390)) {
3622 rt2800_bbp_read(rt2x00dev, 1, &r1);
3623 if (delta <= -12) {
3624 power_ctrl = 2;
3625 delta += 12;
3626 } else if (delta <= -6) {
3627 power_ctrl = 1;
3628 delta += 6;
3629 } else {
3630 power_ctrl = 0;
3631 }
3632 rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, power_ctrl);
3633 rt2800_bbp_write(rt2x00dev, 1, r1);
3634 }
3635
3636 offset = TX_PWR_CFG_0;
3637
3638 for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
3639 /* just to be safe */
3640 if (offset > TX_PWR_CFG_4)
3641 break;
3642
3643 rt2800_register_read(rt2x00dev, offset, &reg);
3644
3645 /* read the next four txpower values */
3646 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3647 i, &eeprom);
3648
3649 is_rate_b = i ? 0 : 1;
3650 /*
3651 * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
3652 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
3653 * TX_PWR_CFG_4: unknown
3654 */
3655 txpower = rt2x00_get_field16(eeprom,
3656 EEPROM_TXPOWER_BYRATE_RATE0);
3657 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
3658 power_level, txpower, delta);
3659 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
3660
3661 /*
3662 * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
3663 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
3664 * TX_PWR_CFG_4: unknown
3665 */
3666 txpower = rt2x00_get_field16(eeprom,
3667 EEPROM_TXPOWER_BYRATE_RATE1);
3668 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
3669 power_level, txpower, delta);
3670 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
3671
3672 /*
3673 * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
3674 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14,
3675 * TX_PWR_CFG_4: unknown
3676 */
3677 txpower = rt2x00_get_field16(eeprom,
3678 EEPROM_TXPOWER_BYRATE_RATE2);
3679 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
3680 power_level, txpower, delta);
3681 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
3682
3683 /*
3684 * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
3685 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15,
3686 * TX_PWR_CFG_4: unknown
3687 */
3688 txpower = rt2x00_get_field16(eeprom,
3689 EEPROM_TXPOWER_BYRATE_RATE3);
3690 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
3691 power_level, txpower, delta);
3692 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
3693
3694 /* read the next four txpower values */
3695 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3696 i + 1, &eeprom);
3697
3698 is_rate_b = 0;
3699 /*
3700 * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
3701 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
3702 * TX_PWR_CFG_4: unknown
3703 */
3704 txpower = rt2x00_get_field16(eeprom,
3705 EEPROM_TXPOWER_BYRATE_RATE0);
3706 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
3707 power_level, txpower, delta);
3708 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
3709
3710 /*
3711 * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
3712 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
3713 * TX_PWR_CFG_4: unknown
3714 */
3715 txpower = rt2x00_get_field16(eeprom,
3716 EEPROM_TXPOWER_BYRATE_RATE1);
3717 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
3718 power_level, txpower, delta);
3719 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
3720
3721 /*
3722 * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
3723 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
3724 * TX_PWR_CFG_4: unknown
3725 */
3726 txpower = rt2x00_get_field16(eeprom,
3727 EEPROM_TXPOWER_BYRATE_RATE2);
3728 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
3729 power_level, txpower, delta);
3730 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
3731
3732 /*
3733 * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
3734 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
3735 * TX_PWR_CFG_4: unknown
3736 */
3737 txpower = rt2x00_get_field16(eeprom,
3738 EEPROM_TXPOWER_BYRATE_RATE3);
3739 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
3740 power_level, txpower, delta);
3741 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
3742
3743 rt2800_register_write(rt2x00dev, offset, reg);
3744
3745 /* next TX_PWR_CFG register */
3746 offset += 4;
3747 }
3748 }
3749
3750 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
3751 struct ieee80211_channel *chan,
3752 int power_level)
3753 {
3754 if (rt2x00_rt(rt2x00dev, RT3593))
3755 rt2800_config_txpower_rt3593(rt2x00dev, chan, power_level);
3756 else
3757 rt2800_config_txpower_rt28xx(rt2x00dev, chan, power_level);
3758 }
3759
3760 void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
3761 {
3762 rt2800_config_txpower(rt2x00dev, rt2x00dev->hw->conf.chandef.chan,
3763 rt2x00dev->tx_power);
3764 }
3765 EXPORT_SYMBOL_GPL(rt2800_gain_calibration);
3766
3767 void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev)
3768 {
3769 u32 tx_pin;
3770 u8 rfcsr;
3771
3772 /*
3773 * A voltage-controlled oscillator(VCO) is an electronic oscillator
3774 * designed to be controlled in oscillation frequency by a voltage
3775 * input. Maybe the temperature will affect the frequency of
3776 * oscillation to be shifted. The VCO calibration will be called
3777 * periodically to adjust the frequency to be precision.
3778 */
3779
3780 rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
3781 tx_pin &= TX_PIN_CFG_PA_PE_DISABLE;
3782 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
3783
3784 switch (rt2x00dev->chip.rf) {
3785 case RF2020:
3786 case RF3020:
3787 case RF3021:
3788 case RF3022:
3789 case RF3320:
3790 case RF3052:
3791 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
3792 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
3793 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
3794 break;
3795 case RF3290:
3796 case RF5360:
3797 case RF5370:
3798 case RF5372:
3799 case RF5390:
3800 case RF5392:
3801 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
3802 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
3803 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
3804 break;
3805 default:
3806 return;
3807 }
3808
3809 mdelay(1);
3810
3811 rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
3812 if (rt2x00dev->rf_channel <= 14) {
3813 switch (rt2x00dev->default_ant.tx_chain_num) {
3814 case 3:
3815 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1);
3816 /* fall through */
3817 case 2:
3818 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
3819 /* fall through */
3820 case 1:
3821 default:
3822 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
3823 break;
3824 }
3825 } else {
3826 switch (rt2x00dev->default_ant.tx_chain_num) {
3827 case 3:
3828 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1);
3829 /* fall through */
3830 case 2:
3831 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
3832 /* fall through */
3833 case 1:
3834 default:
3835 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1);
3836 break;
3837 }
3838 }
3839 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
3840
3841 }
3842 EXPORT_SYMBOL_GPL(rt2800_vco_calibration);
3843
3844 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
3845 struct rt2x00lib_conf *libconf)
3846 {
3847 u32 reg;
3848
3849 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
3850 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
3851 libconf->conf->short_frame_max_tx_count);
3852 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
3853 libconf->conf->long_frame_max_tx_count);
3854 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
3855 }
3856
3857 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
3858 struct rt2x00lib_conf *libconf)
3859 {
3860 enum dev_state state =
3861 (libconf->conf->flags & IEEE80211_CONF_PS) ?
3862 STATE_SLEEP : STATE_AWAKE;
3863 u32 reg;
3864
3865 if (state == STATE_SLEEP) {
3866 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
3867
3868 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
3869 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
3870 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
3871 libconf->conf->listen_interval - 1);
3872 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
3873 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
3874
3875 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
3876 } else {
3877 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
3878 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
3879 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
3880 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
3881 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
3882
3883 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
3884 }
3885 }
3886
3887 void rt2800_config(struct rt2x00_dev *rt2x00dev,
3888 struct rt2x00lib_conf *libconf,
3889 const unsigned int flags)
3890 {
3891 /* Always recalculate LNA gain before changing configuration */
3892 rt2800_config_lna_gain(rt2x00dev, libconf);
3893
3894 if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
3895 rt2800_config_channel(rt2x00dev, libconf->conf,
3896 &libconf->rf, &libconf->channel);
3897 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
3898 libconf->conf->power_level);
3899 }
3900 if (flags & IEEE80211_CONF_CHANGE_POWER)
3901 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
3902 libconf->conf->power_level);
3903 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
3904 rt2800_config_retry_limit(rt2x00dev, libconf);
3905 if (flags & IEEE80211_CONF_CHANGE_PS)
3906 rt2800_config_ps(rt2x00dev, libconf);
3907 }
3908 EXPORT_SYMBOL_GPL(rt2800_config);
3909
3910 /*
3911 * Link tuning
3912 */
3913 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
3914 {
3915 u32 reg;
3916
3917 /*
3918 * Update FCS error count from register.
3919 */
3920 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
3921 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
3922 }
3923 EXPORT_SYMBOL_GPL(rt2800_link_stats);
3924
3925 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
3926 {
3927 u8 vgc;
3928
3929 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
3930 if (rt2x00_rt(rt2x00dev, RT3070) ||
3931 rt2x00_rt(rt2x00dev, RT3071) ||
3932 rt2x00_rt(rt2x00dev, RT3090) ||
3933 rt2x00_rt(rt2x00dev, RT3290) ||
3934 rt2x00_rt(rt2x00dev, RT3390) ||
3935 rt2x00_rt(rt2x00dev, RT3572) ||
3936 rt2x00_rt(rt2x00dev, RT5390) ||
3937 rt2x00_rt(rt2x00dev, RT5392) ||
3938 rt2x00_rt(rt2x00dev, RT5592))
3939 vgc = 0x1c + (2 * rt2x00dev->lna_gain);
3940 else
3941 vgc = 0x2e + rt2x00dev->lna_gain;
3942 } else { /* 5GHZ band */
3943 if (rt2x00_rt(rt2x00dev, RT3572))
3944 vgc = 0x22 + (rt2x00dev->lna_gain * 5) / 3;
3945 else if (rt2x00_rt(rt2x00dev, RT5592))
3946 vgc = 0x24 + (2 * rt2x00dev->lna_gain);
3947 else {
3948 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
3949 vgc = 0x32 + (rt2x00dev->lna_gain * 5) / 3;
3950 else
3951 vgc = 0x3a + (rt2x00dev->lna_gain * 5) / 3;
3952 }
3953 }
3954
3955 return vgc;
3956 }
3957
3958 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
3959 struct link_qual *qual, u8 vgc_level)
3960 {
3961 if (qual->vgc_level != vgc_level) {
3962 if (rt2x00_rt(rt2x00dev, RT5592)) {
3963 rt2800_bbp_write(rt2x00dev, 83, qual->rssi > -65 ? 0x4a : 0x7a);
3964 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, vgc_level);
3965 } else
3966 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
3967 qual->vgc_level = vgc_level;
3968 qual->vgc_level_reg = vgc_level;
3969 }
3970 }
3971
3972 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
3973 {
3974 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
3975 }
3976 EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
3977
3978 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
3979 const u32 count)
3980 {
3981 u8 vgc;
3982
3983 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
3984 return;
3985 /*
3986 * When RSSI is better then -80 increase VGC level with 0x10, except
3987 * for rt5592 chip.
3988 */
3989
3990 vgc = rt2800_get_default_vgc(rt2x00dev);
3991
3992 if (rt2x00_rt(rt2x00dev, RT5592) && qual->rssi > -65)
3993 vgc += 0x20;
3994 else if (qual->rssi > -80)
3995 vgc += 0x10;
3996
3997 rt2800_set_vgc(rt2x00dev, qual, vgc);
3998 }
3999 EXPORT_SYMBOL_GPL(rt2800_link_tuner);
4000
4001 /*
4002 * Initialization functions.
4003 */
4004 static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
4005 {
4006 u32 reg;
4007 u16 eeprom;
4008 unsigned int i;
4009 int ret;
4010
4011 rt2800_disable_wpdma(rt2x00dev);
4012
4013 ret = rt2800_drv_init_registers(rt2x00dev);
4014 if (ret)
4015 return ret;
4016
4017 rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
4018 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
4019 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
4020 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
4021 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
4022 rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
4023
4024 rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
4025 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
4026 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
4027 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
4028 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
4029 rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
4030
4031 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
4032 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
4033
4034 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
4035
4036 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
4037 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
4038 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
4039 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
4040 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
4041 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
4042 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
4043 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
4044
4045 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
4046
4047 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
4048 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
4049 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
4050 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
4051
4052 if (rt2x00_rt(rt2x00dev, RT3290)) {
4053 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
4054 if (rt2x00_get_field32(reg, WLAN_EN) == 1) {
4055 rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 1);
4056 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
4057 }
4058
4059 rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
4060 if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) {
4061 rt2x00_set_field32(&reg, LDO0_EN, 1);
4062 rt2x00_set_field32(&reg, LDO_BGSEL, 3);
4063 rt2800_register_write(rt2x00dev, CMB_CTRL, reg);
4064 }
4065
4066 rt2800_register_read(rt2x00dev, OSC_CTRL, &reg);
4067 rt2x00_set_field32(&reg, OSC_ROSC_EN, 1);
4068 rt2x00_set_field32(&reg, OSC_CAL_REQ, 1);
4069 rt2x00_set_field32(&reg, OSC_REF_CYCLE, 0x27);
4070 rt2800_register_write(rt2x00dev, OSC_CTRL, reg);
4071
4072 rt2800_register_read(rt2x00dev, COEX_CFG0, &reg);
4073 rt2x00_set_field32(&reg, COEX_CFG_ANT, 0x5e);
4074 rt2800_register_write(rt2x00dev, COEX_CFG0, reg);
4075
4076 rt2800_register_read(rt2x00dev, COEX_CFG2, &reg);
4077 rt2x00_set_field32(&reg, BT_COEX_CFG1, 0x00);
4078 rt2x00_set_field32(&reg, BT_COEX_CFG0, 0x17);
4079 rt2x00_set_field32(&reg, WL_COEX_CFG1, 0x93);
4080 rt2x00_set_field32(&reg, WL_COEX_CFG0, 0x7f);
4081 rt2800_register_write(rt2x00dev, COEX_CFG2, reg);
4082
4083 rt2800_register_read(rt2x00dev, PLL_CTRL, &reg);
4084 rt2x00_set_field32(&reg, PLL_CONTROL, 1);
4085 rt2800_register_write(rt2x00dev, PLL_CTRL, reg);
4086 }
4087
4088 if (rt2x00_rt(rt2x00dev, RT3071) ||
4089 rt2x00_rt(rt2x00dev, RT3090) ||
4090 rt2x00_rt(rt2x00dev, RT3290) ||
4091 rt2x00_rt(rt2x00dev, RT3390)) {
4092
4093 if (rt2x00_rt(rt2x00dev, RT3290))
4094 rt2800_register_write(rt2x00dev, TX_SW_CFG0,
4095 0x00000404);
4096 else
4097 rt2800_register_write(rt2x00dev, TX_SW_CFG0,
4098 0x00000400);
4099
4100 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
4101 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
4102 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
4103 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
4104 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1,
4105 &eeprom);
4106 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
4107 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4108 0x0000002c);
4109 else
4110 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4111 0x0000000f);
4112 } else {
4113 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
4114 }
4115 } else if (rt2x00_rt(rt2x00dev, RT3070)) {
4116 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
4117
4118 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
4119 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
4120 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
4121 } else {
4122 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4123 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
4124 }
4125 } else if (rt2800_is_305x_soc(rt2x00dev)) {
4126 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
4127 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
4128 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
4129 } else if (rt2x00_rt(rt2x00dev, RT3352)) {
4130 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
4131 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4132 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
4133 } else if (rt2x00_rt(rt2x00dev, RT3572)) {
4134 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
4135 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4136 } else if (rt2x00_rt(rt2x00dev, RT3593)) {
4137 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
4138 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
4139 if (rt2x00_rt_rev_lt(rt2x00dev, RT3593, REV_RT3593E)) {
4140 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1,
4141 &eeprom);
4142 if (rt2x00_get_field16(eeprom,
4143 EEPROM_NIC_CONF1_DAC_TEST))
4144 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4145 0x0000001f);
4146 else
4147 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4148 0x0000000f);
4149 } else {
4150 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4151 0x00000000);
4152 }
4153 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
4154 rt2x00_rt(rt2x00dev, RT5392) ||
4155 rt2x00_rt(rt2x00dev, RT5592)) {
4156 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
4157 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4158 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
4159 } else {
4160 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
4161 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4162 }
4163
4164 rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
4165 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
4166 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
4167 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
4168 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
4169 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
4170 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
4171 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
4172 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
4173 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
4174
4175 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
4176 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
4177 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
4178 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
4179 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
4180
4181 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
4182 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
4183 if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
4184 rt2x00_rt(rt2x00dev, RT2883) ||
4185 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
4186 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
4187 else
4188 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
4189 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
4190 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
4191 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
4192
4193 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
4194 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
4195 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
4196 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
4197 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
4198 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
4199 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
4200 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
4201 rt2800_register_write(rt2x00dev, LED_CFG, reg);
4202
4203 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
4204
4205 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
4206 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
4207 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
4208 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
4209 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
4210 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
4211 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
4212 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
4213
4214 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
4215 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
4216 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
4217 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
4218 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
4219 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
4220 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
4221 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
4222 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
4223
4224 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
4225 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
4226 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
4227 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
4228 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4229 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4230 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4231 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
4232 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4233 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
4234 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
4235 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
4236
4237 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
4238 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
4239 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
4240 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
4241 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4242 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4243 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4244 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
4245 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4246 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
4247 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
4248 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
4249
4250 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
4251 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
4252 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
4253 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
4254 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4255 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4256 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4257 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
4258 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4259 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
4260 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
4261 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
4262
4263 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
4264 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
4265 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
4266 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
4267 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4268 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4269 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4270 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
4271 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4272 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
4273 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
4274 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
4275
4276 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
4277 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
4278 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
4279 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
4280 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4281 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4282 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4283 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
4284 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4285 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
4286 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
4287 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
4288
4289 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
4290 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
4291 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
4292 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
4293 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4294 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4295 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4296 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
4297 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4298 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
4299 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
4300 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
4301
4302 if (rt2x00_is_usb(rt2x00dev)) {
4303 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
4304
4305 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
4306 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
4307 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
4308 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
4309 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
4310 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
4311 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
4312 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
4313 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
4314 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
4315 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
4316 }
4317
4318 /*
4319 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
4320 * although it is reserved.
4321 */
4322 rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, &reg);
4323 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
4324 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
4325 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
4326 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
4327 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
4328 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
4329 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
4330 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
4331 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
4332 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
4333 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
4334
4335 reg = rt2x00_rt(rt2x00dev, RT5592) ? 0x00000082 : 0x00000002;
4336 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, reg);
4337
4338 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
4339 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
4340 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
4341 IEEE80211_MAX_RTS_THRESHOLD);
4342 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
4343 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
4344
4345 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
4346
4347 /*
4348 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
4349 * time should be set to 16. However, the original Ralink driver uses
4350 * 16 for both and indeed using a value of 10 for CCK SIFS results in
4351 * connection problems with 11g + CTS protection. Hence, use the same
4352 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
4353 */
4354 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
4355 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
4356 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
4357 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
4358 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
4359 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
4360 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
4361
4362 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
4363
4364 /*
4365 * ASIC will keep garbage value after boot, clear encryption keys.
4366 */
4367 for (i = 0; i < 4; i++)
4368 rt2800_register_write(rt2x00dev,
4369 SHARED_KEY_MODE_ENTRY(i), 0);
4370
4371 for (i = 0; i < 256; i++) {
4372 rt2800_config_wcid(rt2x00dev, NULL, i);
4373 rt2800_delete_wcid_attr(rt2x00dev, i);
4374 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
4375 }
4376
4377 /*
4378 * Clear all beacons
4379 */
4380 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE0);
4381 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE1);
4382 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE2);
4383 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE3);
4384 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE4);
4385 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE5);
4386 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE6);
4387 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE7);
4388
4389 if (rt2x00_is_usb(rt2x00dev)) {
4390 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
4391 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
4392 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
4393 } else if (rt2x00_is_pcie(rt2x00dev)) {
4394 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
4395 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
4396 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
4397 }
4398
4399 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
4400 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
4401 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
4402 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
4403 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
4404 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
4405 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
4406 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
4407 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
4408 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
4409
4410 rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
4411 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
4412 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
4413 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
4414 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
4415 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
4416 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
4417 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
4418 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
4419 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
4420
4421 rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
4422 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
4423 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
4424 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
4425 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
4426 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
4427 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
4428 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
4429 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
4430 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
4431
4432 rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
4433 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
4434 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
4435 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
4436 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
4437 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
4438
4439 /*
4440 * Do not force the BA window size, we use the TXWI to set it
4441 */
4442 rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, &reg);
4443 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
4444 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
4445 rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
4446
4447 /*
4448 * We must clear the error counters.
4449 * These registers are cleared on read,
4450 * so we may pass a useless variable to store the value.
4451 */
4452 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
4453 rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
4454 rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
4455 rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
4456 rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
4457 rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
4458
4459 /*
4460 * Setup leadtime for pre tbtt interrupt to 6ms
4461 */
4462 rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
4463 rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
4464 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
4465
4466 /*
4467 * Set up channel statistics timer
4468 */
4469 rt2800_register_read(rt2x00dev, CH_TIME_CFG, &reg);
4470 rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
4471 rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
4472 rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
4473 rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
4474 rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
4475 rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
4476
4477 return 0;
4478 }
4479
4480 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
4481 {
4482 unsigned int i;
4483 u32 reg;
4484
4485 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
4486 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
4487 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
4488 return 0;
4489
4490 udelay(REGISTER_BUSY_DELAY);
4491 }
4492
4493 rt2x00_err(rt2x00dev, "BBP/RF register access failed, aborting\n");
4494 return -EACCES;
4495 }
4496
4497 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
4498 {
4499 unsigned int i;
4500 u8 value;
4501
4502 /*
4503 * BBP was enabled after firmware was loaded,
4504 * but we need to reactivate it now.
4505 */
4506 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
4507 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
4508 msleep(1);
4509
4510 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
4511 rt2800_bbp_read(rt2x00dev, 0, &value);
4512 if ((value != 0xff) && (value != 0x00))
4513 return 0;
4514 udelay(REGISTER_BUSY_DELAY);
4515 }
4516
4517 rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n");
4518 return -EACCES;
4519 }
4520
4521 static void rt2800_bbp4_mac_if_ctrl(struct rt2x00_dev *rt2x00dev)
4522 {
4523 u8 value;
4524
4525 rt2800_bbp_read(rt2x00dev, 4, &value);
4526 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
4527 rt2800_bbp_write(rt2x00dev, 4, value);
4528 }
4529
4530 static void rt2800_init_freq_calibration(struct rt2x00_dev *rt2x00dev)
4531 {
4532 rt2800_bbp_write(rt2x00dev, 142, 1);
4533 rt2800_bbp_write(rt2x00dev, 143, 57);
4534 }
4535
4536 static void rt2800_init_bbp_5592_glrt(struct rt2x00_dev *rt2x00dev)
4537 {
4538 const u8 glrt_table[] = {
4539 0xE0, 0x1F, 0X38, 0x32, 0x08, 0x28, 0x19, 0x0A, 0xFF, 0x00, /* 128 ~ 137 */
4540 0x16, 0x10, 0x10, 0x0B, 0x36, 0x2C, 0x26, 0x24, 0x42, 0x36, /* 138 ~ 147 */
4541 0x30, 0x2D, 0x4C, 0x46, 0x3D, 0x40, 0x3E, 0x42, 0x3D, 0x40, /* 148 ~ 157 */
4542 0X3C, 0x34, 0x2C, 0x2F, 0x3C, 0x35, 0x2E, 0x2A, 0x49, 0x41, /* 158 ~ 167 */
4543 0x36, 0x31, 0x30, 0x30, 0x0E, 0x0D, 0x28, 0x21, 0x1C, 0x16, /* 168 ~ 177 */
4544 0x50, 0x4A, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, /* 178 ~ 187 */
4545 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 188 ~ 197 */
4546 0x00, 0x00, 0x7D, 0x14, 0x32, 0x2C, 0x36, 0x4C, 0x43, 0x2C, /* 198 ~ 207 */
4547 0x2E, 0x36, 0x30, 0x6E, /* 208 ~ 211 */
4548 };
4549 int i;
4550
4551 for (i = 0; i < ARRAY_SIZE(glrt_table); i++) {
4552 rt2800_bbp_write(rt2x00dev, 195, 128 + i);
4553 rt2800_bbp_write(rt2x00dev, 196, glrt_table[i]);
4554 }
4555 };
4556
4557 static void rt2800_init_bbp_early(struct rt2x00_dev *rt2x00dev)
4558 {
4559 rt2800_bbp_write(rt2x00dev, 65, 0x2C);
4560 rt2800_bbp_write(rt2x00dev, 66, 0x38);
4561 rt2800_bbp_write(rt2x00dev, 68, 0x0B);
4562 rt2800_bbp_write(rt2x00dev, 69, 0x12);
4563 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
4564 rt2800_bbp_write(rt2x00dev, 73, 0x10);
4565 rt2800_bbp_write(rt2x00dev, 81, 0x37);
4566 rt2800_bbp_write(rt2x00dev, 82, 0x62);
4567 rt2800_bbp_write(rt2x00dev, 83, 0x6A);
4568 rt2800_bbp_write(rt2x00dev, 84, 0x99);
4569 rt2800_bbp_write(rt2x00dev, 86, 0x00);
4570 rt2800_bbp_write(rt2x00dev, 91, 0x04);
4571 rt2800_bbp_write(rt2x00dev, 92, 0x00);
4572 rt2800_bbp_write(rt2x00dev, 103, 0x00);
4573 rt2800_bbp_write(rt2x00dev, 105, 0x05);
4574 rt2800_bbp_write(rt2x00dev, 106, 0x35);
4575 }
4576
4577 static void rt2800_disable_unused_dac_adc(struct rt2x00_dev *rt2x00dev)
4578 {
4579 u16 eeprom;
4580 u8 value;
4581
4582 rt2800_bbp_read(rt2x00dev, 138, &value);
4583 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
4584 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
4585 value |= 0x20;
4586 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
4587 value &= ~0x02;
4588 rt2800_bbp_write(rt2x00dev, 138, value);
4589 }
4590
4591 static void rt2800_init_bbp_305x_soc(struct rt2x00_dev *rt2x00dev)
4592 {
4593 rt2800_bbp_write(rt2x00dev, 31, 0x08);
4594
4595 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
4596 rt2800_bbp_write(rt2x00dev, 66, 0x38);
4597
4598 rt2800_bbp_write(rt2x00dev, 69, 0x12);
4599 rt2800_bbp_write(rt2x00dev, 73, 0x10);
4600
4601 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
4602
4603 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
4604 rt2800_bbp_write(rt2x00dev, 80, 0x08);
4605
4606 rt2800_bbp_write(rt2x00dev, 82, 0x62);
4607
4608 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
4609
4610 rt2800_bbp_write(rt2x00dev, 84, 0x99);
4611
4612 rt2800_bbp_write(rt2x00dev, 86, 0x00);
4613
4614 rt2800_bbp_write(rt2x00dev, 91, 0x04);
4615
4616 rt2800_bbp_write(rt2x00dev, 92, 0x00);
4617
4618 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
4619
4620 rt2800_bbp_write(rt2x00dev, 105, 0x01);
4621
4622 rt2800_bbp_write(rt2x00dev, 106, 0x35);
4623 }
4624
4625 static void rt2800_init_bbp_28xx(struct rt2x00_dev *rt2x00dev)
4626 {
4627 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
4628 rt2800_bbp_write(rt2x00dev, 66, 0x38);
4629
4630 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
4631 rt2800_bbp_write(rt2x00dev, 69, 0x16);
4632 rt2800_bbp_write(rt2x00dev, 73, 0x12);
4633 } else {
4634 rt2800_bbp_write(rt2x00dev, 69, 0x12);
4635 rt2800_bbp_write(rt2x00dev, 73, 0x10);
4636 }
4637
4638 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
4639
4640 rt2800_bbp_write(rt2x00dev, 81, 0x37);
4641
4642 rt2800_bbp_write(rt2x00dev, 82, 0x62);
4643
4644 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
4645
4646 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
4647 rt2800_bbp_write(rt2x00dev, 84, 0x19);
4648 else
4649 rt2800_bbp_write(rt2x00dev, 84, 0x99);
4650
4651 rt2800_bbp_write(rt2x00dev, 86, 0x00);
4652
4653 rt2800_bbp_write(rt2x00dev, 91, 0x04);
4654
4655 rt2800_bbp_write(rt2x00dev, 92, 0x00);
4656
4657 rt2800_bbp_write(rt2x00dev, 103, 0x00);
4658
4659 rt2800_bbp_write(rt2x00dev, 105, 0x05);
4660
4661 rt2800_bbp_write(rt2x00dev, 106, 0x35);
4662 }
4663
4664 static void rt2800_init_bbp_30xx(struct rt2x00_dev *rt2x00dev)
4665 {
4666 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
4667 rt2800_bbp_write(rt2x00dev, 66, 0x38);
4668
4669 rt2800_bbp_write(rt2x00dev, 69, 0x12);
4670 rt2800_bbp_write(rt2x00dev, 73, 0x10);
4671
4672 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
4673
4674 rt2800_bbp_write(rt2x00dev, 79, 0x13);
4675 rt2800_bbp_write(rt2x00dev, 80, 0x05);
4676 rt2800_bbp_write(rt2x00dev, 81, 0x33);
4677
4678 rt2800_bbp_write(rt2x00dev, 82, 0x62);
4679
4680 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
4681
4682 rt2800_bbp_write(rt2x00dev, 84, 0x99);
4683
4684 rt2800_bbp_write(rt2x00dev, 86, 0x00);
4685
4686 rt2800_bbp_write(rt2x00dev, 91, 0x04);
4687
4688 rt2800_bbp_write(rt2x00dev, 92, 0x00);
4689
4690 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
4691 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
4692 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E))
4693 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
4694 else
4695 rt2800_bbp_write(rt2x00dev, 103, 0x00);
4696
4697 rt2800_bbp_write(rt2x00dev, 105, 0x05);
4698
4699 rt2800_bbp_write(rt2x00dev, 106, 0x35);
4700
4701 if (rt2x00_rt(rt2x00dev, RT3071) ||
4702 rt2x00_rt(rt2x00dev, RT3090))
4703 rt2800_disable_unused_dac_adc(rt2x00dev);
4704 }
4705
4706 static void rt2800_init_bbp_3290(struct rt2x00_dev *rt2x00dev)
4707 {
4708 u8 value;
4709
4710 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
4711
4712 rt2800_bbp_write(rt2x00dev, 31, 0x08);
4713
4714 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
4715 rt2800_bbp_write(rt2x00dev, 66, 0x38);
4716
4717 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
4718
4719 rt2800_bbp_write(rt2x00dev, 69, 0x12);
4720 rt2800_bbp_write(rt2x00dev, 73, 0x13);
4721 rt2800_bbp_write(rt2x00dev, 75, 0x46);
4722 rt2800_bbp_write(rt2x00dev, 76, 0x28);
4723
4724 rt2800_bbp_write(rt2x00dev, 77, 0x58);
4725
4726 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
4727
4728 rt2800_bbp_write(rt2x00dev, 74, 0x0b);
4729 rt2800_bbp_write(rt2x00dev, 79, 0x18);
4730 rt2800_bbp_write(rt2x00dev, 80, 0x09);
4731 rt2800_bbp_write(rt2x00dev, 81, 0x33);
4732
4733 rt2800_bbp_write(rt2x00dev, 82, 0x62);
4734
4735 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
4736
4737 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
4738
4739 rt2800_bbp_write(rt2x00dev, 86, 0x38);
4740
4741 rt2800_bbp_write(rt2x00dev, 91, 0x04);
4742
4743 rt2800_bbp_write(rt2x00dev, 92, 0x02);
4744
4745 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
4746
4747 rt2800_bbp_write(rt2x00dev, 104, 0x92);
4748
4749 rt2800_bbp_write(rt2x00dev, 105, 0x1c);
4750
4751 rt2800_bbp_write(rt2x00dev, 106, 0x03);
4752
4753 rt2800_bbp_write(rt2x00dev, 128, 0x12);
4754
4755 rt2800_bbp_write(rt2x00dev, 67, 0x24);
4756 rt2800_bbp_write(rt2x00dev, 143, 0x04);
4757 rt2800_bbp_write(rt2x00dev, 142, 0x99);
4758 rt2800_bbp_write(rt2x00dev, 150, 0x30);
4759 rt2800_bbp_write(rt2x00dev, 151, 0x2e);
4760 rt2800_bbp_write(rt2x00dev, 152, 0x20);
4761 rt2800_bbp_write(rt2x00dev, 153, 0x34);
4762 rt2800_bbp_write(rt2x00dev, 154, 0x40);
4763 rt2800_bbp_write(rt2x00dev, 155, 0x3b);
4764 rt2800_bbp_write(rt2x00dev, 253, 0x04);
4765
4766 rt2800_bbp_read(rt2x00dev, 47, &value);
4767 rt2x00_set_field8(&value, BBP47_TSSI_ADC6, 1);
4768 rt2800_bbp_write(rt2x00dev, 47, value);
4769
4770 /* Use 5-bit ADC for Acquisition and 8-bit ADC for data */
4771 rt2800_bbp_read(rt2x00dev, 3, &value);
4772 rt2x00_set_field8(&value, BBP3_ADC_MODE_SWITCH, 1);
4773 rt2x00_set_field8(&value, BBP3_ADC_INIT_MODE, 1);
4774 rt2800_bbp_write(rt2x00dev, 3, value);
4775 }
4776
4777 static void rt2800_init_bbp_3352(struct rt2x00_dev *rt2x00dev)
4778 {
4779 rt2800_bbp_write(rt2x00dev, 3, 0x00);
4780 rt2800_bbp_write(rt2x00dev, 4, 0x50);
4781
4782 rt2800_bbp_write(rt2x00dev, 31, 0x08);
4783
4784 rt2800_bbp_write(rt2x00dev, 47, 0x48);
4785
4786 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
4787 rt2800_bbp_write(rt2x00dev, 66, 0x38);
4788
4789 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
4790
4791 rt2800_bbp_write(rt2x00dev, 69, 0x12);
4792 rt2800_bbp_write(rt2x00dev, 73, 0x13);
4793 rt2800_bbp_write(rt2x00dev, 75, 0x46);
4794 rt2800_bbp_write(rt2x00dev, 76, 0x28);
4795
4796 rt2800_bbp_write(rt2x00dev, 77, 0x59);
4797
4798 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
4799
4800 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
4801 rt2800_bbp_write(rt2x00dev, 80, 0x08);
4802 rt2800_bbp_write(rt2x00dev, 81, 0x37);
4803
4804 rt2800_bbp_write(rt2x00dev, 82, 0x62);
4805
4806 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
4807
4808 rt2800_bbp_write(rt2x00dev, 84, 0x99);
4809
4810 rt2800_bbp_write(rt2x00dev, 86, 0x38);
4811
4812 rt2800_bbp_write(rt2x00dev, 88, 0x90);
4813
4814 rt2800_bbp_write(rt2x00dev, 91, 0x04);
4815
4816 rt2800_bbp_write(rt2x00dev, 92, 0x02);
4817
4818 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
4819
4820 rt2800_bbp_write(rt2x00dev, 104, 0x92);
4821
4822 rt2800_bbp_write(rt2x00dev, 105, 0x34);
4823
4824 rt2800_bbp_write(rt2x00dev, 106, 0x05);
4825
4826 rt2800_bbp_write(rt2x00dev, 120, 0x50);
4827
4828 rt2800_bbp_write(rt2x00dev, 137, 0x0f);
4829
4830 rt2800_bbp_write(rt2x00dev, 163, 0xbd);
4831 /* Set ITxBF timeout to 0x9c40=1000msec */
4832 rt2800_bbp_write(rt2x00dev, 179, 0x02);
4833 rt2800_bbp_write(rt2x00dev, 180, 0x00);
4834 rt2800_bbp_write(rt2x00dev, 182, 0x40);
4835 rt2800_bbp_write(rt2x00dev, 180, 0x01);
4836 rt2800_bbp_write(rt2x00dev, 182, 0x9c);
4837 rt2800_bbp_write(rt2x00dev, 179, 0x00);
4838 /* Reprogram the inband interface to put right values in RXWI */
4839 rt2800_bbp_write(rt2x00dev, 142, 0x04);
4840 rt2800_bbp_write(rt2x00dev, 143, 0x3b);
4841 rt2800_bbp_write(rt2x00dev, 142, 0x06);
4842 rt2800_bbp_write(rt2x00dev, 143, 0xa0);
4843 rt2800_bbp_write(rt2x00dev, 142, 0x07);
4844 rt2800_bbp_write(rt2x00dev, 143, 0xa1);
4845 rt2800_bbp_write(rt2x00dev, 142, 0x08);
4846 rt2800_bbp_write(rt2x00dev, 143, 0xa2);
4847
4848 rt2800_bbp_write(rt2x00dev, 148, 0xc8);
4849 }
4850
4851 static void rt2800_init_bbp_3390(struct rt2x00_dev *rt2x00dev)
4852 {
4853 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
4854 rt2800_bbp_write(rt2x00dev, 66, 0x38);
4855
4856 rt2800_bbp_write(rt2x00dev, 69, 0x12);
4857 rt2800_bbp_write(rt2x00dev, 73, 0x10);
4858
4859 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
4860
4861 rt2800_bbp_write(rt2x00dev, 79, 0x13);
4862 rt2800_bbp_write(rt2x00dev, 80, 0x05);
4863 rt2800_bbp_write(rt2x00dev, 81, 0x33);
4864
4865 rt2800_bbp_write(rt2x00dev, 82, 0x62);
4866
4867 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
4868
4869 rt2800_bbp_write(rt2x00dev, 84, 0x99);
4870
4871 rt2800_bbp_write(rt2x00dev, 86, 0x00);
4872
4873 rt2800_bbp_write(rt2x00dev, 91, 0x04);
4874
4875 rt2800_bbp_write(rt2x00dev, 92, 0x00);
4876
4877 if (rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E))
4878 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
4879 else
4880 rt2800_bbp_write(rt2x00dev, 103, 0x00);
4881
4882 rt2800_bbp_write(rt2x00dev, 105, 0x05);
4883
4884 rt2800_bbp_write(rt2x00dev, 106, 0x35);
4885
4886 rt2800_disable_unused_dac_adc(rt2x00dev);
4887 }
4888
4889 static void rt2800_init_bbp_3572(struct rt2x00_dev *rt2x00dev)
4890 {
4891 rt2800_bbp_write(rt2x00dev, 31, 0x08);
4892
4893 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
4894 rt2800_bbp_write(rt2x00dev, 66, 0x38);
4895
4896 rt2800_bbp_write(rt2x00dev, 69, 0x12);
4897 rt2800_bbp_write(rt2x00dev, 73, 0x10);
4898
4899 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
4900
4901 rt2800_bbp_write(rt2x00dev, 79, 0x13);
4902 rt2800_bbp_write(rt2x00dev, 80, 0x05);
4903 rt2800_bbp_write(rt2x00dev, 81, 0x33);
4904
4905 rt2800_bbp_write(rt2x00dev, 82, 0x62);
4906
4907 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
4908
4909 rt2800_bbp_write(rt2x00dev, 84, 0x99);
4910
4911 rt2800_bbp_write(rt2x00dev, 86, 0x00);
4912
4913 rt2800_bbp_write(rt2x00dev, 91, 0x04);
4914
4915 rt2800_bbp_write(rt2x00dev, 92, 0x00);
4916
4917 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
4918
4919 rt2800_bbp_write(rt2x00dev, 105, 0x05);
4920
4921 rt2800_bbp_write(rt2x00dev, 106, 0x35);
4922
4923 rt2800_disable_unused_dac_adc(rt2x00dev);
4924 }
4925
4926 static void rt2800_init_bbp_3593(struct rt2x00_dev *rt2x00dev)
4927 {
4928 rt2800_init_bbp_early(rt2x00dev);
4929
4930 rt2800_bbp_write(rt2x00dev, 79, 0x13);
4931 rt2800_bbp_write(rt2x00dev, 80, 0x05);
4932 rt2800_bbp_write(rt2x00dev, 81, 0x33);
4933 rt2800_bbp_write(rt2x00dev, 137, 0x0f);
4934
4935 rt2800_bbp_write(rt2x00dev, 84, 0x19);
4936
4937 /* Enable DC filter */
4938 if (rt2x00_rt_rev_gte(rt2x00dev, RT3593, REV_RT3593E))
4939 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
4940 }
4941
4942 static void rt2800_init_bbp_53xx(struct rt2x00_dev *rt2x00dev)
4943 {
4944 int ant, div_mode;
4945 u16 eeprom;
4946 u8 value;
4947
4948 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
4949
4950 rt2800_bbp_write(rt2x00dev, 31, 0x08);
4951
4952 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
4953 rt2800_bbp_write(rt2x00dev, 66, 0x38);
4954
4955 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
4956
4957 rt2800_bbp_write(rt2x00dev, 69, 0x12);
4958 rt2800_bbp_write(rt2x00dev, 73, 0x13);
4959 rt2800_bbp_write(rt2x00dev, 75, 0x46);
4960 rt2800_bbp_write(rt2x00dev, 76, 0x28);
4961
4962 rt2800_bbp_write(rt2x00dev, 77, 0x59);
4963
4964 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
4965
4966 rt2800_bbp_write(rt2x00dev, 79, 0x13);
4967 rt2800_bbp_write(rt2x00dev, 80, 0x05);
4968 rt2800_bbp_write(rt2x00dev, 81, 0x33);
4969
4970 rt2800_bbp_write(rt2x00dev, 82, 0x62);
4971
4972 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
4973
4974 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
4975
4976 rt2800_bbp_write(rt2x00dev, 86, 0x38);
4977
4978 if (rt2x00_rt(rt2x00dev, RT5392))
4979 rt2800_bbp_write(rt2x00dev, 88, 0x90);
4980
4981 rt2800_bbp_write(rt2x00dev, 91, 0x04);
4982
4983 rt2800_bbp_write(rt2x00dev, 92, 0x02);
4984
4985 if (rt2x00_rt(rt2x00dev, RT5392)) {
4986 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
4987 rt2800_bbp_write(rt2x00dev, 98, 0x12);
4988 }
4989
4990 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
4991
4992 rt2800_bbp_write(rt2x00dev, 104, 0x92);
4993
4994 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
4995
4996 if (rt2x00_rt(rt2x00dev, RT5390))
4997 rt2800_bbp_write(rt2x00dev, 106, 0x03);
4998 else if (rt2x00_rt(rt2x00dev, RT5392))
4999 rt2800_bbp_write(rt2x00dev, 106, 0x12);
5000 else
5001 WARN_ON(1);
5002
5003 rt2800_bbp_write(rt2x00dev, 128, 0x12);
5004
5005 if (rt2x00_rt(rt2x00dev, RT5392)) {
5006 rt2800_bbp_write(rt2x00dev, 134, 0xd0);
5007 rt2800_bbp_write(rt2x00dev, 135, 0xf6);
5008 }
5009
5010 rt2800_disable_unused_dac_adc(rt2x00dev);
5011
5012 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
5013 div_mode = rt2x00_get_field16(eeprom,
5014 EEPROM_NIC_CONF1_ANT_DIVERSITY);
5015 ant = (div_mode == 3) ? 1 : 0;
5016
5017 /* check if this is a Bluetooth combo card */
5018 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
5019 u32 reg;
5020
5021 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
5022 rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
5023 rt2x00_set_field32(&reg, GPIO_CTRL_DIR6, 0);
5024 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 0);
5025 rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 0);
5026 if (ant == 0)
5027 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 1);
5028 else if (ant == 1)
5029 rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 1);
5030 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
5031 }
5032
5033 /* This chip has hardware antenna diversity*/
5034 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
5035 rt2800_bbp_write(rt2x00dev, 150, 0); /* Disable Antenna Software OFDM */
5036 rt2800_bbp_write(rt2x00dev, 151, 0); /* Disable Antenna Software CCK */
5037 rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */
5038 }
5039
5040 rt2800_bbp_read(rt2x00dev, 152, &value);
5041 if (ant == 0)
5042 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
5043 else
5044 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
5045 rt2800_bbp_write(rt2x00dev, 152, value);
5046
5047 rt2800_init_freq_calibration(rt2x00dev);
5048 }
5049
5050 static void rt2800_init_bbp_5592(struct rt2x00_dev *rt2x00dev)
5051 {
5052 int ant, div_mode;
5053 u16 eeprom;
5054 u8 value;
5055
5056 rt2800_init_bbp_early(rt2x00dev);
5057
5058 rt2800_bbp_read(rt2x00dev, 105, &value);
5059 rt2x00_set_field8(&value, BBP105_MLD,
5060 rt2x00dev->default_ant.rx_chain_num == 2);
5061 rt2800_bbp_write(rt2x00dev, 105, value);
5062
5063 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5064
5065 rt2800_bbp_write(rt2x00dev, 20, 0x06);
5066 rt2800_bbp_write(rt2x00dev, 31, 0x08);
5067 rt2800_bbp_write(rt2x00dev, 65, 0x2C);
5068 rt2800_bbp_write(rt2x00dev, 68, 0xDD);
5069 rt2800_bbp_write(rt2x00dev, 69, 0x1A);
5070 rt2800_bbp_write(rt2x00dev, 70, 0x05);
5071 rt2800_bbp_write(rt2x00dev, 73, 0x13);
5072 rt2800_bbp_write(rt2x00dev, 74, 0x0F);
5073 rt2800_bbp_write(rt2x00dev, 75, 0x4F);
5074 rt2800_bbp_write(rt2x00dev, 76, 0x28);
5075 rt2800_bbp_write(rt2x00dev, 77, 0x59);
5076 rt2800_bbp_write(rt2x00dev, 84, 0x9A);
5077 rt2800_bbp_write(rt2x00dev, 86, 0x38);
5078 rt2800_bbp_write(rt2x00dev, 88, 0x90);
5079 rt2800_bbp_write(rt2x00dev, 91, 0x04);
5080 rt2800_bbp_write(rt2x00dev, 92, 0x02);
5081 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
5082 rt2800_bbp_write(rt2x00dev, 98, 0x12);
5083 rt2800_bbp_write(rt2x00dev, 103, 0xC0);
5084 rt2800_bbp_write(rt2x00dev, 104, 0x92);
5085 /* FIXME BBP105 owerwrite */
5086 rt2800_bbp_write(rt2x00dev, 105, 0x3C);
5087 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5088 rt2800_bbp_write(rt2x00dev, 128, 0x12);
5089 rt2800_bbp_write(rt2x00dev, 134, 0xD0);
5090 rt2800_bbp_write(rt2x00dev, 135, 0xF6);
5091 rt2800_bbp_write(rt2x00dev, 137, 0x0F);
5092
5093 /* Initialize GLRT (Generalized Likehood Radio Test) */
5094 rt2800_init_bbp_5592_glrt(rt2x00dev);
5095
5096 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5097
5098 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
5099 div_mode = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_ANT_DIVERSITY);
5100 ant = (div_mode == 3) ? 1 : 0;
5101 rt2800_bbp_read(rt2x00dev, 152, &value);
5102 if (ant == 0) {
5103 /* Main antenna */
5104 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
5105 } else {
5106 /* Auxiliary antenna */
5107 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
5108 }
5109 rt2800_bbp_write(rt2x00dev, 152, value);
5110
5111 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) {
5112 rt2800_bbp_read(rt2x00dev, 254, &value);
5113 rt2x00_set_field8(&value, BBP254_BIT7, 1);
5114 rt2800_bbp_write(rt2x00dev, 254, value);
5115 }
5116
5117 rt2800_init_freq_calibration(rt2x00dev);
5118
5119 rt2800_bbp_write(rt2x00dev, 84, 0x19);
5120 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
5121 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5122 }
5123
5124 static void rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
5125 {
5126 unsigned int i;
5127 u16 eeprom;
5128 u8 reg_id;
5129 u8 value;
5130
5131 if (rt2800_is_305x_soc(rt2x00dev))
5132 rt2800_init_bbp_305x_soc(rt2x00dev);
5133
5134 switch (rt2x00dev->chip.rt) {
5135 case RT2860:
5136 case RT2872:
5137 case RT2883:
5138 rt2800_init_bbp_28xx(rt2x00dev);
5139 break;
5140 case RT3070:
5141 case RT3071:
5142 case RT3090:
5143 rt2800_init_bbp_30xx(rt2x00dev);
5144 break;
5145 case RT3290:
5146 rt2800_init_bbp_3290(rt2x00dev);
5147 break;
5148 case RT3352:
5149 rt2800_init_bbp_3352(rt2x00dev);
5150 break;
5151 case RT3390:
5152 rt2800_init_bbp_3390(rt2x00dev);
5153 break;
5154 case RT3572:
5155 rt2800_init_bbp_3572(rt2x00dev);
5156 break;
5157 case RT3593:
5158 rt2800_init_bbp_3593(rt2x00dev);
5159 return;
5160 case RT5390:
5161 case RT5392:
5162 rt2800_init_bbp_53xx(rt2x00dev);
5163 break;
5164 case RT5592:
5165 rt2800_init_bbp_5592(rt2x00dev);
5166 return;
5167 }
5168
5169 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
5170 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_BBP_START, i,
5171 &eeprom);
5172
5173 if (eeprom != 0xffff && eeprom != 0x0000) {
5174 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
5175 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
5176 rt2800_bbp_write(rt2x00dev, reg_id, value);
5177 }
5178 }
5179 }
5180
5181 static void rt2800_led_open_drain_enable(struct rt2x00_dev *rt2x00dev)
5182 {
5183 u32 reg;
5184
5185 rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
5186 rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
5187 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
5188 }
5189
5190 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev, bool bw40,
5191 u8 filter_target)
5192 {
5193 unsigned int i;
5194 u8 bbp;
5195 u8 rfcsr;
5196 u8 passband;
5197 u8 stopband;
5198 u8 overtuned = 0;
5199 u8 rfcsr24 = (bw40) ? 0x27 : 0x07;
5200
5201 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
5202
5203 rt2800_bbp_read(rt2x00dev, 4, &bbp);
5204 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
5205 rt2800_bbp_write(rt2x00dev, 4, bbp);
5206
5207 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
5208 rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
5209 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
5210
5211 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
5212 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
5213 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
5214
5215 /*
5216 * Set power & frequency of passband test tone
5217 */
5218 rt2800_bbp_write(rt2x00dev, 24, 0);
5219
5220 for (i = 0; i < 100; i++) {
5221 rt2800_bbp_write(rt2x00dev, 25, 0x90);
5222 msleep(1);
5223
5224 rt2800_bbp_read(rt2x00dev, 55, &passband);
5225 if (passband)
5226 break;
5227 }
5228
5229 /*
5230 * Set power & frequency of stopband test tone
5231 */
5232 rt2800_bbp_write(rt2x00dev, 24, 0x06);
5233
5234 for (i = 0; i < 100; i++) {
5235 rt2800_bbp_write(rt2x00dev, 25, 0x90);
5236 msleep(1);
5237
5238 rt2800_bbp_read(rt2x00dev, 55, &stopband);
5239
5240 if ((passband - stopband) <= filter_target) {
5241 rfcsr24++;
5242 overtuned += ((passband - stopband) == filter_target);
5243 } else
5244 break;
5245
5246 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
5247 }
5248
5249 rfcsr24 -= !!overtuned;
5250
5251 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
5252 return rfcsr24;
5253 }
5254
5255 static void rt2800_rf_init_calibration(struct rt2x00_dev *rt2x00dev,
5256 const unsigned int rf_reg)
5257 {
5258 u8 rfcsr;
5259
5260 rt2800_rfcsr_read(rt2x00dev, rf_reg, &rfcsr);
5261 rt2x00_set_field8(&rfcsr, FIELD8(0x80), 1);
5262 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
5263 msleep(1);
5264 rt2x00_set_field8(&rfcsr, FIELD8(0x80), 0);
5265 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
5266 }
5267
5268 static void rt2800_rx_filter_calibration(struct rt2x00_dev *rt2x00dev)
5269 {
5270 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5271 u8 filter_tgt_bw20;
5272 u8 filter_tgt_bw40;
5273 u8 rfcsr, bbp;
5274
5275 /*
5276 * TODO: sync filter_tgt values with vendor driver
5277 */
5278 if (rt2x00_rt(rt2x00dev, RT3070)) {
5279 filter_tgt_bw20 = 0x16;
5280 filter_tgt_bw40 = 0x19;
5281 } else {
5282 filter_tgt_bw20 = 0x13;
5283 filter_tgt_bw40 = 0x15;
5284 }
5285
5286 drv_data->calibration_bw20 =
5287 rt2800_init_rx_filter(rt2x00dev, false, filter_tgt_bw20);
5288 drv_data->calibration_bw40 =
5289 rt2800_init_rx_filter(rt2x00dev, true, filter_tgt_bw40);
5290
5291 /*
5292 * Save BBP 25 & 26 values for later use in channel switching (for 3052)
5293 */
5294 rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25);
5295 rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26);
5296
5297 /*
5298 * Set back to initial state
5299 */
5300 rt2800_bbp_write(rt2x00dev, 24, 0);
5301
5302 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
5303 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
5304 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
5305
5306 /*
5307 * Set BBP back to BW20
5308 */
5309 rt2800_bbp_read(rt2x00dev, 4, &bbp);
5310 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
5311 rt2800_bbp_write(rt2x00dev, 4, bbp);
5312 }
5313
5314 static void rt2800_normal_mode_setup_3xxx(struct rt2x00_dev *rt2x00dev)
5315 {
5316 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5317 u8 min_gain, rfcsr, bbp;
5318 u16 eeprom;
5319
5320 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
5321
5322 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
5323 if (rt2x00_rt(rt2x00dev, RT3070) ||
5324 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
5325 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
5326 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
5327 if (!test_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags))
5328 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
5329 }
5330
5331 min_gain = rt2x00_rt(rt2x00dev, RT3070) ? 1 : 2;
5332 if (drv_data->txmixer_gain_24g >= min_gain) {
5333 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
5334 drv_data->txmixer_gain_24g);
5335 }
5336
5337 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
5338
5339 if (rt2x00_rt(rt2x00dev, RT3090)) {
5340 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
5341 rt2800_bbp_read(rt2x00dev, 138, &bbp);
5342 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
5343 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
5344 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
5345 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
5346 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
5347 rt2800_bbp_write(rt2x00dev, 138, bbp);
5348 }
5349
5350 if (rt2x00_rt(rt2x00dev, RT3070)) {
5351 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
5352 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
5353 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
5354 else
5355 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
5356 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
5357 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
5358 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
5359 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
5360 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
5361 rt2x00_rt(rt2x00dev, RT3090) ||
5362 rt2x00_rt(rt2x00dev, RT3390)) {
5363 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
5364 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
5365 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
5366 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
5367 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
5368 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
5369 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
5370
5371 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
5372 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
5373 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
5374
5375 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
5376 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
5377 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
5378
5379 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
5380 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
5381 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
5382 }
5383 }
5384
5385 static void rt2800_normal_mode_setup_3593(struct rt2x00_dev *rt2x00dev)
5386 {
5387 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5388 u8 rfcsr;
5389 u8 tx_gain;
5390
5391 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
5392 rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO2_EN, 0);
5393 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
5394
5395 rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr);
5396 tx_gain = rt2x00_get_field8(drv_data->txmixer_gain_24g,
5397 RFCSR17_TXMIXER_GAIN);
5398 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, tx_gain);
5399 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
5400
5401 rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr);
5402 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
5403 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
5404
5405 rt2800_rfcsr_read(rt2x00dev, 39, &rfcsr);
5406 rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
5407 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
5408
5409 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
5410 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
5411 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
5412 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
5413
5414 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
5415 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
5416 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
5417
5418 /* TODO: enable stream mode */
5419 }
5420
5421 static void rt2800_normal_mode_setup_5xxx(struct rt2x00_dev *rt2x00dev)
5422 {
5423 u8 reg;
5424 u16 eeprom;
5425
5426 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
5427 rt2800_bbp_read(rt2x00dev, 138, &reg);
5428 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
5429 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
5430 rt2x00_set_field8(&reg, BBP138_RX_ADC1, 0);
5431 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
5432 rt2x00_set_field8(&reg, BBP138_TX_DAC1, 1);
5433 rt2800_bbp_write(rt2x00dev, 138, reg);
5434
5435 rt2800_rfcsr_read(rt2x00dev, 38, &reg);
5436 rt2x00_set_field8(&reg, RFCSR38_RX_LO1_EN, 0);
5437 rt2800_rfcsr_write(rt2x00dev, 38, reg);
5438
5439 rt2800_rfcsr_read(rt2x00dev, 39, &reg);
5440 rt2x00_set_field8(&reg, RFCSR39_RX_LO2_EN, 0);
5441 rt2800_rfcsr_write(rt2x00dev, 39, reg);
5442
5443 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5444
5445 rt2800_rfcsr_read(rt2x00dev, 30, &reg);
5446 rt2x00_set_field8(&reg, RFCSR30_RX_VCM, 2);
5447 rt2800_rfcsr_write(rt2x00dev, 30, reg);
5448 }
5449
5450 static void rt2800_init_rfcsr_305x_soc(struct rt2x00_dev *rt2x00dev)
5451 {
5452 rt2800_rf_init_calibration(rt2x00dev, 30);
5453
5454 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
5455 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
5456 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
5457 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
5458 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
5459 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
5460 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
5461 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
5462 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
5463 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
5464 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
5465 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
5466 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
5467 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
5468 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
5469 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
5470 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
5471 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
5472 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
5473 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
5474 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
5475 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
5476 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
5477 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
5478 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
5479 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
5480 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
5481 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
5482 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
5483 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
5484 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
5485 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
5486 }
5487
5488 static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev)
5489 {
5490 u8 rfcsr;
5491 u16 eeprom;
5492 u32 reg;
5493
5494 /* XXX vendor driver do this only for 3070 */
5495 rt2800_rf_init_calibration(rt2x00dev, 30);
5496
5497 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
5498 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
5499 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
5500 rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
5501 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
5502 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
5503 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
5504 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
5505 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
5506 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
5507 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
5508 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
5509 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
5510 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
5511 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
5512 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
5513 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
5514 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
5515 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
5516
5517 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
5518 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
5519 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
5520 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
5521 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
5522 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
5523 rt2x00_rt(rt2x00dev, RT3090)) {
5524 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
5525
5526 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
5527 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
5528 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
5529
5530 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
5531 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
5532 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
5533 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
5534 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1,
5535 &eeprom);
5536 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
5537 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
5538 else
5539 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
5540 }
5541 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
5542
5543 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
5544 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
5545 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
5546 }
5547
5548 rt2800_rx_filter_calibration(rt2x00dev);
5549
5550 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
5551 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
5552 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E))
5553 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
5554
5555 rt2800_led_open_drain_enable(rt2x00dev);
5556 rt2800_normal_mode_setup_3xxx(rt2x00dev);
5557 }
5558
5559 static void rt2800_init_rfcsr_3290(struct rt2x00_dev *rt2x00dev)
5560 {
5561 u8 rfcsr;
5562
5563 rt2800_rf_init_calibration(rt2x00dev, 2);
5564
5565 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
5566 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
5567 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
5568 rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
5569 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
5570 rt2800_rfcsr_write(rt2x00dev, 8, 0xf3);
5571 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
5572 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
5573 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
5574 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
5575 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
5576 rt2800_rfcsr_write(rt2x00dev, 18, 0x02);
5577 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
5578 rt2800_rfcsr_write(rt2x00dev, 25, 0x83);
5579 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
5580 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
5581 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
5582 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
5583 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
5584 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
5585 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
5586 rt2800_rfcsr_write(rt2x00dev, 34, 0x05);
5587 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
5588 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
5589 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
5590 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
5591 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
5592 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
5593 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
5594 rt2800_rfcsr_write(rt2x00dev, 43, 0x7b);
5595 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
5596 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
5597 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
5598 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
5599 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
5600 rt2800_rfcsr_write(rt2x00dev, 49, 0x98);
5601 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
5602 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
5603 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
5604 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
5605 rt2800_rfcsr_write(rt2x00dev, 56, 0x02);
5606 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
5607 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
5608 rt2800_rfcsr_write(rt2x00dev, 59, 0x09);
5609 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
5610 rt2800_rfcsr_write(rt2x00dev, 61, 0xc1);
5611
5612 rt2800_rfcsr_read(rt2x00dev, 29, &rfcsr);
5613 rt2x00_set_field8(&rfcsr, RFCSR29_RSSI_GAIN, 3);
5614 rt2800_rfcsr_write(rt2x00dev, 29, rfcsr);
5615
5616 rt2800_led_open_drain_enable(rt2x00dev);
5617 rt2800_normal_mode_setup_3xxx(rt2x00dev);
5618 }
5619
5620 static void rt2800_init_rfcsr_3352(struct rt2x00_dev *rt2x00dev)
5621 {
5622 rt2800_rf_init_calibration(rt2x00dev, 30);
5623
5624 rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
5625 rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
5626 rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
5627 rt2800_rfcsr_write(rt2x00dev, 3, 0x18);
5628 rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
5629 rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
5630 rt2800_rfcsr_write(rt2x00dev, 6, 0x33);
5631 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
5632 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
5633 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
5634 rt2800_rfcsr_write(rt2x00dev, 10, 0xd2);
5635 rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
5636 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
5637 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
5638 rt2800_rfcsr_write(rt2x00dev, 14, 0x5a);
5639 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
5640 rt2800_rfcsr_write(rt2x00dev, 16, 0x01);
5641 rt2800_rfcsr_write(rt2x00dev, 18, 0x45);
5642 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
5643 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
5644 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
5645 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
5646 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
5647 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
5648 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
5649 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
5650 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
5651 rt2800_rfcsr_write(rt2x00dev, 28, 0x03);
5652 rt2800_rfcsr_write(rt2x00dev, 29, 0x00);
5653 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
5654 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
5655 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
5656 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
5657 rt2800_rfcsr_write(rt2x00dev, 34, 0x01);
5658 rt2800_rfcsr_write(rt2x00dev, 35, 0x03);
5659 rt2800_rfcsr_write(rt2x00dev, 36, 0xbd);
5660 rt2800_rfcsr_write(rt2x00dev, 37, 0x3c);
5661 rt2800_rfcsr_write(rt2x00dev, 38, 0x5f);
5662 rt2800_rfcsr_write(rt2x00dev, 39, 0xc5);
5663 rt2800_rfcsr_write(rt2x00dev, 40, 0x33);
5664 rt2800_rfcsr_write(rt2x00dev, 41, 0x5b);
5665 rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
5666 rt2800_rfcsr_write(rt2x00dev, 43, 0xdb);
5667 rt2800_rfcsr_write(rt2x00dev, 44, 0xdb);
5668 rt2800_rfcsr_write(rt2x00dev, 45, 0xdb);
5669 rt2800_rfcsr_write(rt2x00dev, 46, 0xdd);
5670 rt2800_rfcsr_write(rt2x00dev, 47, 0x0d);
5671 rt2800_rfcsr_write(rt2x00dev, 48, 0x14);
5672 rt2800_rfcsr_write(rt2x00dev, 49, 0x00);
5673 rt2800_rfcsr_write(rt2x00dev, 50, 0x2d);
5674 rt2800_rfcsr_write(rt2x00dev, 51, 0x7f);
5675 rt2800_rfcsr_write(rt2x00dev, 52, 0x00);
5676 rt2800_rfcsr_write(rt2x00dev, 53, 0x52);
5677 rt2800_rfcsr_write(rt2x00dev, 54, 0x1b);
5678 rt2800_rfcsr_write(rt2x00dev, 55, 0x7f);
5679 rt2800_rfcsr_write(rt2x00dev, 56, 0x00);
5680 rt2800_rfcsr_write(rt2x00dev, 57, 0x52);
5681 rt2800_rfcsr_write(rt2x00dev, 58, 0x1b);
5682 rt2800_rfcsr_write(rt2x00dev, 59, 0x00);
5683 rt2800_rfcsr_write(rt2x00dev, 60, 0x00);
5684 rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
5685 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
5686 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
5687
5688 rt2800_rx_filter_calibration(rt2x00dev);
5689 rt2800_led_open_drain_enable(rt2x00dev);
5690 rt2800_normal_mode_setup_3xxx(rt2x00dev);
5691 }
5692
5693 static void rt2800_init_rfcsr_3390(struct rt2x00_dev *rt2x00dev)
5694 {
5695 u32 reg;
5696
5697 rt2800_rf_init_calibration(rt2x00dev, 30);
5698
5699 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
5700 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
5701 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
5702 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
5703 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
5704 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
5705 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
5706 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
5707 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
5708 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
5709 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
5710 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
5711 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
5712 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
5713 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
5714 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
5715 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
5716 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
5717 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
5718 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
5719 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
5720 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
5721 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
5722 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
5723 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
5724 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
5725 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
5726 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
5727 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
5728 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
5729 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
5730 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
5731
5732 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
5733 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
5734 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
5735
5736 rt2800_rx_filter_calibration(rt2x00dev);
5737
5738 if (rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
5739 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
5740
5741 rt2800_led_open_drain_enable(rt2x00dev);
5742 rt2800_normal_mode_setup_3xxx(rt2x00dev);
5743 }
5744
5745 static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev)
5746 {
5747 u8 rfcsr;
5748 u32 reg;
5749
5750 rt2800_rf_init_calibration(rt2x00dev, 30);
5751
5752 rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
5753 rt2800_rfcsr_write(rt2x00dev, 1, 0x81);
5754 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
5755 rt2800_rfcsr_write(rt2x00dev, 3, 0x02);
5756 rt2800_rfcsr_write(rt2x00dev, 4, 0x4c);
5757 rt2800_rfcsr_write(rt2x00dev, 5, 0x05);
5758 rt2800_rfcsr_write(rt2x00dev, 6, 0x4a);
5759 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
5760 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
5761 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
5762 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
5763 rt2800_rfcsr_write(rt2x00dev, 12, 0x70);
5764 rt2800_rfcsr_write(rt2x00dev, 13, 0x65);
5765 rt2800_rfcsr_write(rt2x00dev, 14, 0xa0);
5766 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
5767 rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
5768 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
5769 rt2800_rfcsr_write(rt2x00dev, 18, 0xac);
5770 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
5771 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
5772 rt2800_rfcsr_write(rt2x00dev, 21, 0xd0);
5773 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
5774 rt2800_rfcsr_write(rt2x00dev, 23, 0x3c);
5775 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
5776 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
5777 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
5778 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
5779 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
5780 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
5781 rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
5782 rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
5783
5784 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
5785 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
5786 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
5787
5788 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
5789 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
5790 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
5791 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
5792 msleep(1);
5793 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
5794 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
5795 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
5796 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
5797
5798 rt2800_rx_filter_calibration(rt2x00dev);
5799 rt2800_led_open_drain_enable(rt2x00dev);
5800 rt2800_normal_mode_setup_3xxx(rt2x00dev);
5801 }
5802
5803 static void rt3593_post_bbp_init(struct rt2x00_dev *rt2x00dev)
5804 {
5805 u8 bbp;
5806 bool txbf_enabled = false; /* FIXME */
5807
5808 rt2800_bbp_read(rt2x00dev, 105, &bbp);
5809 if (rt2x00dev->default_ant.rx_chain_num == 1)
5810 rt2x00_set_field8(&bbp, BBP105_MLD, 0);
5811 else
5812 rt2x00_set_field8(&bbp, BBP105_MLD, 1);
5813 rt2800_bbp_write(rt2x00dev, 105, bbp);
5814
5815 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5816
5817 rt2800_bbp_write(rt2x00dev, 92, 0x02);
5818 rt2800_bbp_write(rt2x00dev, 82, 0x82);
5819 rt2800_bbp_write(rt2x00dev, 106, 0x05);
5820 rt2800_bbp_write(rt2x00dev, 104, 0x92);
5821 rt2800_bbp_write(rt2x00dev, 88, 0x90);
5822 rt2800_bbp_write(rt2x00dev, 148, 0xc8);
5823 rt2800_bbp_write(rt2x00dev, 47, 0x48);
5824 rt2800_bbp_write(rt2x00dev, 120, 0x50);
5825
5826 if (txbf_enabled)
5827 rt2800_bbp_write(rt2x00dev, 163, 0xbd);
5828 else
5829 rt2800_bbp_write(rt2x00dev, 163, 0x9d);
5830
5831 /* SNR mapping */
5832 rt2800_bbp_write(rt2x00dev, 142, 6);
5833 rt2800_bbp_write(rt2x00dev, 143, 160);
5834 rt2800_bbp_write(rt2x00dev, 142, 7);
5835 rt2800_bbp_write(rt2x00dev, 143, 161);
5836 rt2800_bbp_write(rt2x00dev, 142, 8);
5837 rt2800_bbp_write(rt2x00dev, 143, 162);
5838
5839 /* ADC/DAC control */
5840 rt2800_bbp_write(rt2x00dev, 31, 0x08);
5841
5842 /* RX AGC energy lower bound in log2 */
5843 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
5844
5845 /* FIXME: BBP 105 owerwrite? */
5846 rt2800_bbp_write(rt2x00dev, 105, 0x04);
5847 }
5848
5849 static void rt2800_init_rfcsr_3593(struct rt2x00_dev *rt2x00dev)
5850 {
5851 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5852 u32 reg;
5853 u8 rfcsr;
5854
5855 /* Disable GPIO #4 and #7 function for LAN PE control */
5856 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
5857 rt2x00_set_field32(&reg, GPIO_SWITCH_4, 0);
5858 rt2x00_set_field32(&reg, GPIO_SWITCH_7, 0);
5859 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
5860
5861 /* Initialize default register values */
5862 rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
5863 rt2800_rfcsr_write(rt2x00dev, 3, 0x80);
5864 rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
5865 rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
5866 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
5867 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
5868 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
5869 rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
5870 rt2800_rfcsr_write(rt2x00dev, 12, 0x4e);
5871 rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
5872 rt2800_rfcsr_write(rt2x00dev, 18, 0x40);
5873 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
5874 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
5875 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
5876 rt2800_rfcsr_write(rt2x00dev, 32, 0x78);
5877 rt2800_rfcsr_write(rt2x00dev, 33, 0x3b);
5878 rt2800_rfcsr_write(rt2x00dev, 34, 0x3c);
5879 rt2800_rfcsr_write(rt2x00dev, 35, 0xe0);
5880 rt2800_rfcsr_write(rt2x00dev, 38, 0x86);
5881 rt2800_rfcsr_write(rt2x00dev, 39, 0x23);
5882 rt2800_rfcsr_write(rt2x00dev, 44, 0xd3);
5883 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
5884 rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
5885 rt2800_rfcsr_write(rt2x00dev, 49, 0x8e);
5886 rt2800_rfcsr_write(rt2x00dev, 50, 0x86);
5887 rt2800_rfcsr_write(rt2x00dev, 51, 0x75);
5888 rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
5889 rt2800_rfcsr_write(rt2x00dev, 53, 0x18);
5890 rt2800_rfcsr_write(rt2x00dev, 54, 0x18);
5891 rt2800_rfcsr_write(rt2x00dev, 55, 0x18);
5892 rt2800_rfcsr_write(rt2x00dev, 56, 0xdb);
5893 rt2800_rfcsr_write(rt2x00dev, 57, 0x6e);
5894
5895 /* Initiate calibration */
5896 /* TODO: use rt2800_rf_init_calibration ? */
5897 rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
5898 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
5899 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
5900
5901 rt2800_adjust_freq_offset(rt2x00dev);
5902
5903 rt2800_rfcsr_read(rt2x00dev, 18, &rfcsr);
5904 rt2x00_set_field8(&rfcsr, RFCSR18_XO_TUNE_BYPASS, 1);
5905 rt2800_rfcsr_write(rt2x00dev, 18, rfcsr);
5906
5907 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
5908 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
5909 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
5910 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
5911 usleep_range(1000, 1500);
5912 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
5913 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
5914 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
5915
5916 /* Set initial values for RX filter calibration */
5917 drv_data->calibration_bw20 = 0x1f;
5918 drv_data->calibration_bw40 = 0x2f;
5919
5920 /* Save BBP 25 & 26 values for later use in channel switching */
5921 rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25);
5922 rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26);
5923
5924 rt2800_led_open_drain_enable(rt2x00dev);
5925 rt2800_normal_mode_setup_3593(rt2x00dev);
5926
5927 rt3593_post_bbp_init(rt2x00dev);
5928
5929 /* TODO: enable stream mode support */
5930 }
5931
5932 static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev)
5933 {
5934 rt2800_rf_init_calibration(rt2x00dev, 2);
5935
5936 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
5937 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
5938 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
5939 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
5940 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
5941 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
5942 else
5943 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
5944 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
5945 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
5946 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
5947 rt2800_rfcsr_write(rt2x00dev, 12, 0xc6);
5948 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
5949 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
5950 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
5951 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
5952 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
5953 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
5954
5955 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
5956 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
5957 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
5958 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
5959 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
5960 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
5961 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
5962 else
5963 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
5964 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
5965 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
5966 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
5967 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
5968
5969 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
5970 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
5971 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
5972 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
5973 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
5974 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
5975 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
5976 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
5977 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
5978 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
5979
5980 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
5981 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
5982 else
5983 rt2800_rfcsr_write(rt2x00dev, 40, 0x4b);
5984 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
5985 rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
5986 rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
5987 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
5988 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
5989 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
5990 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
5991 else
5992 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
5993 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
5994 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
5995 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
5996
5997 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
5998 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
5999 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
6000 else
6001 rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
6002 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
6003 rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
6004 rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
6005 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
6006 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
6007 rt2800_rfcsr_write(rt2x00dev, 59, 0x63);
6008
6009 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
6010 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6011 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
6012 else
6013 rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
6014 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
6015 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
6016
6017 rt2800_normal_mode_setup_5xxx(rt2x00dev);
6018
6019 rt2800_led_open_drain_enable(rt2x00dev);
6020 }
6021
6022 static void rt2800_init_rfcsr_5392(struct rt2x00_dev *rt2x00dev)
6023 {
6024 rt2800_rf_init_calibration(rt2x00dev, 2);
6025
6026 rt2800_rfcsr_write(rt2x00dev, 1, 0x17);
6027 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
6028 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
6029 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
6030 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
6031 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
6032 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
6033 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
6034 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
6035 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
6036 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
6037 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
6038 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
6039 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
6040 rt2800_rfcsr_write(rt2x00dev, 19, 0x4d);
6041 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
6042 rt2800_rfcsr_write(rt2x00dev, 21, 0x8d);
6043 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
6044 rt2800_rfcsr_write(rt2x00dev, 23, 0x0b);
6045 rt2800_rfcsr_write(rt2x00dev, 24, 0x44);
6046 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
6047 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
6048 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
6049 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
6050 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
6051 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
6052 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6053 rt2800_rfcsr_write(rt2x00dev, 32, 0x20);
6054 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
6055 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
6056 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
6057 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
6058 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
6059 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
6060 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
6061 rt2800_rfcsr_write(rt2x00dev, 40, 0x0f);
6062 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
6063 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
6064 rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
6065 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
6066 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
6067 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
6068 rt2800_rfcsr_write(rt2x00dev, 47, 0x0c);
6069 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
6070 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
6071 rt2800_rfcsr_write(rt2x00dev, 50, 0x94);
6072 rt2800_rfcsr_write(rt2x00dev, 51, 0x3a);
6073 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
6074 rt2800_rfcsr_write(rt2x00dev, 53, 0x44);
6075 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
6076 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
6077 rt2800_rfcsr_write(rt2x00dev, 56, 0xa1);
6078 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
6079 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
6080 rt2800_rfcsr_write(rt2x00dev, 59, 0x07);
6081 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
6082 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
6083 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
6084 rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
6085
6086 rt2800_normal_mode_setup_5xxx(rt2x00dev);
6087
6088 rt2800_led_open_drain_enable(rt2x00dev);
6089 }
6090
6091 static void rt2800_init_rfcsr_5592(struct rt2x00_dev *rt2x00dev)
6092 {
6093 rt2800_rf_init_calibration(rt2x00dev, 30);
6094
6095 rt2800_rfcsr_write(rt2x00dev, 1, 0x3F);
6096 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
6097 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
6098 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
6099 rt2800_rfcsr_write(rt2x00dev, 6, 0xE4);
6100 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
6101 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
6102 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
6103 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
6104 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
6105 rt2800_rfcsr_write(rt2x00dev, 19, 0x4D);
6106 rt2800_rfcsr_write(rt2x00dev, 20, 0x10);
6107 rt2800_rfcsr_write(rt2x00dev, 21, 0x8D);
6108 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
6109 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
6110 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
6111 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
6112 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
6113 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
6114 rt2800_rfcsr_write(rt2x00dev, 47, 0x0C);
6115 rt2800_rfcsr_write(rt2x00dev, 53, 0x22);
6116 rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
6117
6118 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
6119 msleep(1);
6120
6121 rt2800_adjust_freq_offset(rt2x00dev);
6122
6123 /* Enable DC filter */
6124 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
6125 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6126
6127 rt2800_normal_mode_setup_5xxx(rt2x00dev);
6128
6129 if (rt2x00_rt_rev_lt(rt2x00dev, RT5592, REV_RT5592C))
6130 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
6131
6132 rt2800_led_open_drain_enable(rt2x00dev);
6133 }
6134
6135 static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
6136 {
6137 if (rt2800_is_305x_soc(rt2x00dev)) {
6138 rt2800_init_rfcsr_305x_soc(rt2x00dev);
6139 return;
6140 }
6141
6142 switch (rt2x00dev->chip.rt) {
6143 case RT3070:
6144 case RT3071:
6145 case RT3090:
6146 rt2800_init_rfcsr_30xx(rt2x00dev);
6147 break;
6148 case RT3290:
6149 rt2800_init_rfcsr_3290(rt2x00dev);
6150 break;
6151 case RT3352:
6152 rt2800_init_rfcsr_3352(rt2x00dev);
6153 break;
6154 case RT3390:
6155 rt2800_init_rfcsr_3390(rt2x00dev);
6156 break;
6157 case RT3572:
6158 rt2800_init_rfcsr_3572(rt2x00dev);
6159 break;
6160 case RT3593:
6161 rt2800_init_rfcsr_3593(rt2x00dev);
6162 break;
6163 case RT5390:
6164 rt2800_init_rfcsr_5390(rt2x00dev);
6165 break;
6166 case RT5392:
6167 rt2800_init_rfcsr_5392(rt2x00dev);
6168 break;
6169 case RT5592:
6170 rt2800_init_rfcsr_5592(rt2x00dev);
6171 break;
6172 }
6173 }
6174
6175 int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
6176 {
6177 u32 reg;
6178 u16 word;
6179
6180 /*
6181 * Initialize all registers.
6182 */
6183 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
6184 rt2800_init_registers(rt2x00dev)))
6185 return -EIO;
6186
6187 /*
6188 * Send signal to firmware during boot time.
6189 */
6190 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
6191 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
6192 if (rt2x00_is_usb(rt2x00dev)) {
6193 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
6194 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
6195 }
6196 msleep(1);
6197
6198 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
6199 rt2800_wait_bbp_ready(rt2x00dev)))
6200 return -EIO;
6201
6202 rt2800_init_bbp(rt2x00dev);
6203 rt2800_init_rfcsr(rt2x00dev);
6204
6205 if (rt2x00_is_usb(rt2x00dev) &&
6206 (rt2x00_rt(rt2x00dev, RT3070) ||
6207 rt2x00_rt(rt2x00dev, RT3071) ||
6208 rt2x00_rt(rt2x00dev, RT3572))) {
6209 udelay(200);
6210 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
6211 udelay(10);
6212 }
6213
6214 /*
6215 * Enable RX.
6216 */
6217 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
6218 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
6219 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
6220 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
6221
6222 udelay(50);
6223
6224 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
6225 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
6226 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
6227 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
6228 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
6229 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
6230
6231 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
6232 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
6233 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
6234 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
6235
6236 /*
6237 * Initialize LED control
6238 */
6239 rt2800_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word);
6240 rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
6241 word & 0xff, (word >> 8) & 0xff);
6242
6243 rt2800_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word);
6244 rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
6245 word & 0xff, (word >> 8) & 0xff);
6246
6247 rt2800_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word);
6248 rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
6249 word & 0xff, (word >> 8) & 0xff);
6250
6251 return 0;
6252 }
6253 EXPORT_SYMBOL_GPL(rt2800_enable_radio);
6254
6255 void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
6256 {
6257 u32 reg;
6258
6259 rt2800_disable_wpdma(rt2x00dev);
6260
6261 /* Wait for DMA, ignore error */
6262 rt2800_wait_wpdma_ready(rt2x00dev);
6263
6264 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
6265 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
6266 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
6267 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
6268 }
6269 EXPORT_SYMBOL_GPL(rt2800_disable_radio);
6270
6271 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
6272 {
6273 u32 reg;
6274 u16 efuse_ctrl_reg;
6275
6276 if (rt2x00_rt(rt2x00dev, RT3290))
6277 efuse_ctrl_reg = EFUSE_CTRL_3290;
6278 else
6279 efuse_ctrl_reg = EFUSE_CTRL;
6280
6281 rt2800_register_read(rt2x00dev, efuse_ctrl_reg, &reg);
6282 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
6283 }
6284 EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
6285
6286 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
6287 {
6288 u32 reg;
6289 u16 efuse_ctrl_reg;
6290 u16 efuse_data0_reg;
6291 u16 efuse_data1_reg;
6292 u16 efuse_data2_reg;
6293 u16 efuse_data3_reg;
6294
6295 if (rt2x00_rt(rt2x00dev, RT3290)) {
6296 efuse_ctrl_reg = EFUSE_CTRL_3290;
6297 efuse_data0_reg = EFUSE_DATA0_3290;
6298 efuse_data1_reg = EFUSE_DATA1_3290;
6299 efuse_data2_reg = EFUSE_DATA2_3290;
6300 efuse_data3_reg = EFUSE_DATA3_3290;
6301 } else {
6302 efuse_ctrl_reg = EFUSE_CTRL;
6303 efuse_data0_reg = EFUSE_DATA0;
6304 efuse_data1_reg = EFUSE_DATA1;
6305 efuse_data2_reg = EFUSE_DATA2;
6306 efuse_data3_reg = EFUSE_DATA3;
6307 }
6308 mutex_lock(&rt2x00dev->csr_mutex);
6309
6310 rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg, &reg);
6311 rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
6312 rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
6313 rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
6314 rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg);
6315
6316 /* Wait until the EEPROM has been loaded */
6317 rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, &reg);
6318 /* Apparently the data is read from end to start */
6319 rt2800_register_read_lock(rt2x00dev, efuse_data3_reg, &reg);
6320 /* The returned value is in CPU order, but eeprom is le */
6321 *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg);
6322 rt2800_register_read_lock(rt2x00dev, efuse_data2_reg, &reg);
6323 *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg);
6324 rt2800_register_read_lock(rt2x00dev, efuse_data1_reg, &reg);
6325 *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg);
6326 rt2800_register_read_lock(rt2x00dev, efuse_data0_reg, &reg);
6327 *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg);
6328
6329 mutex_unlock(&rt2x00dev->csr_mutex);
6330 }
6331
6332 int rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
6333 {
6334 unsigned int i;
6335
6336 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
6337 rt2800_efuse_read(rt2x00dev, i);
6338
6339 return 0;
6340 }
6341 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
6342
6343 static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
6344 {
6345 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
6346 u16 word;
6347 u8 *mac;
6348 u8 default_lna_gain;
6349 int retval;
6350
6351 /*
6352 * Read the EEPROM.
6353 */
6354 retval = rt2800_read_eeprom(rt2x00dev);
6355 if (retval)
6356 return retval;
6357
6358 /*
6359 * Start validation of the data that has been read.
6360 */
6361 mac = rt2800_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
6362 if (!is_valid_ether_addr(mac)) {
6363 eth_random_addr(mac);
6364 rt2x00_eeprom_dbg(rt2x00dev, "MAC: %pM\n", mac);
6365 }
6366
6367 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word);
6368 if (word == 0xffff) {
6369 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
6370 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
6371 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
6372 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
6373 rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word);
6374 } else if (rt2x00_rt(rt2x00dev, RT2860) ||
6375 rt2x00_rt(rt2x00dev, RT2872)) {
6376 /*
6377 * There is a max of 2 RX streams for RT28x0 series
6378 */
6379 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
6380 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
6381 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
6382 }
6383
6384 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
6385 if (word == 0xffff) {
6386 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
6387 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
6388 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
6389 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
6390 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
6391 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
6392 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
6393 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
6394 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
6395 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
6396 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
6397 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
6398 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
6399 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
6400 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
6401 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
6402 rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word);
6403 }
6404
6405 rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
6406 if ((word & 0x00ff) == 0x00ff) {
6407 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
6408 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
6409 rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word);
6410 }
6411 if ((word & 0xff00) == 0xff00) {
6412 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
6413 LED_MODE_TXRX_ACTIVITY);
6414 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
6415 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
6416 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
6417 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
6418 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
6419 rt2x00_eeprom_dbg(rt2x00dev, "Led Mode: 0x%04x\n", word);
6420 }
6421
6422 /*
6423 * During the LNA validation we are going to use
6424 * lna0 as correct value. Note that EEPROM_LNA
6425 * is never validated.
6426 */
6427 rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
6428 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
6429
6430 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
6431 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
6432 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
6433 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
6434 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
6435 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
6436
6437 rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &word);
6438 if ((word & 0x00ff) != 0x00ff) {
6439 drv_data->txmixer_gain_24g =
6440 rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL);
6441 } else {
6442 drv_data->txmixer_gain_24g = 0;
6443 }
6444
6445 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
6446 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
6447 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
6448 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
6449 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
6450 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
6451 default_lna_gain);
6452 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
6453
6454 rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A, &word);
6455 if ((word & 0x00ff) != 0x00ff) {
6456 drv_data->txmixer_gain_5g =
6457 rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL);
6458 } else {
6459 drv_data->txmixer_gain_5g = 0;
6460 }
6461
6462 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
6463 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
6464 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
6465 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
6466 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
6467 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
6468
6469 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
6470 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
6471 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
6472 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
6473 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
6474 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
6475 default_lna_gain);
6476 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
6477
6478 return 0;
6479 }
6480
6481 static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
6482 {
6483 u16 value;
6484 u16 eeprom;
6485 u16 rf;
6486
6487 /*
6488 * Read EEPROM word for configuration.
6489 */
6490 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
6491
6492 /*
6493 * Identify RF chipset by EEPROM value
6494 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
6495 * RT53xx: defined in "EEPROM_CHIP_ID" field
6496 */
6497 if (rt2x00_rt(rt2x00dev, RT3290) ||
6498 rt2x00_rt(rt2x00dev, RT5390) ||
6499 rt2x00_rt(rt2x00dev, RT5392))
6500 rt2800_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &rf);
6501 else
6502 rf = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
6503
6504 switch (rf) {
6505 case RF2820:
6506 case RF2850:
6507 case RF2720:
6508 case RF2750:
6509 case RF3020:
6510 case RF2020:
6511 case RF3021:
6512 case RF3022:
6513 case RF3052:
6514 case RF3290:
6515 case RF3320:
6516 case RF3322:
6517 case RF5360:
6518 case RF5370:
6519 case RF5372:
6520 case RF5390:
6521 case RF5392:
6522 case RF5592:
6523 break;
6524 default:
6525 rt2x00_err(rt2x00dev, "Invalid RF chipset 0x%04x detected\n",
6526 rf);
6527 return -ENODEV;
6528 }
6529
6530 rt2x00_set_rf(rt2x00dev, rf);
6531
6532 /*
6533 * Identify default antenna configuration.
6534 */
6535 rt2x00dev->default_ant.tx_chain_num =
6536 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
6537 rt2x00dev->default_ant.rx_chain_num =
6538 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
6539
6540 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
6541
6542 if (rt2x00_rt(rt2x00dev, RT3070) ||
6543 rt2x00_rt(rt2x00dev, RT3090) ||
6544 rt2x00_rt(rt2x00dev, RT3352) ||
6545 rt2x00_rt(rt2x00dev, RT3390)) {
6546 value = rt2x00_get_field16(eeprom,
6547 EEPROM_NIC_CONF1_ANT_DIVERSITY);
6548 switch (value) {
6549 case 0:
6550 case 1:
6551 case 2:
6552 rt2x00dev->default_ant.tx = ANTENNA_A;
6553 rt2x00dev->default_ant.rx = ANTENNA_A;
6554 break;
6555 case 3:
6556 rt2x00dev->default_ant.tx = ANTENNA_A;
6557 rt2x00dev->default_ant.rx = ANTENNA_B;
6558 break;
6559 }
6560 } else {
6561 rt2x00dev->default_ant.tx = ANTENNA_A;
6562 rt2x00dev->default_ant.rx = ANTENNA_A;
6563 }
6564
6565 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
6566 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; /* Unused */
6567 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; /* Unused */
6568 }
6569
6570 /*
6571 * Determine external LNA informations.
6572 */
6573 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
6574 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
6575 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
6576 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
6577
6578 /*
6579 * Detect if this device has an hardware controlled radio.
6580 */
6581 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
6582 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
6583
6584 /*
6585 * Detect if this device has Bluetooth co-existence.
6586 */
6587 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST))
6588 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags);
6589
6590 /*
6591 * Read frequency offset and RF programming sequence.
6592 */
6593 rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
6594 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
6595
6596 /*
6597 * Store led settings, for correct led behaviour.
6598 */
6599 #ifdef CONFIG_RT2X00_LIB_LEDS
6600 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
6601 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
6602 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
6603
6604 rt2x00dev->led_mcu_reg = eeprom;
6605 #endif /* CONFIG_RT2X00_LIB_LEDS */
6606
6607 /*
6608 * Check if support EIRP tx power limit feature.
6609 */
6610 rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom);
6611
6612 if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
6613 EIRP_MAX_TX_POWER_LIMIT)
6614 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
6615
6616 return 0;
6617 }
6618
6619 /*
6620 * RF value list for rt28xx
6621 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
6622 */
6623 static const struct rf_channel rf_vals[] = {
6624 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
6625 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
6626 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
6627 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
6628 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
6629 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
6630 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
6631 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
6632 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
6633 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
6634 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
6635 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
6636 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
6637 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
6638
6639 /* 802.11 UNI / HyperLan 2 */
6640 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
6641 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
6642 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
6643 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
6644 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
6645 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
6646 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
6647 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
6648 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
6649 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
6650 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
6651 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
6652
6653 /* 802.11 HyperLan 2 */
6654 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
6655 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
6656 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
6657 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
6658 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
6659 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
6660 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
6661 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
6662 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
6663 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
6664 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
6665 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
6666 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
6667 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
6668 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
6669 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
6670
6671 /* 802.11 UNII */
6672 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
6673 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
6674 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
6675 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
6676 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
6677 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
6678 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
6679 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
6680 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
6681 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
6682 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
6683
6684 /* 802.11 Japan */
6685 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
6686 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
6687 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
6688 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
6689 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
6690 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
6691 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
6692 };
6693
6694 /*
6695 * RF value list for rt3xxx
6696 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
6697 */
6698 static const struct rf_channel rf_vals_3x[] = {
6699 {1, 241, 2, 2 },
6700 {2, 241, 2, 7 },
6701 {3, 242, 2, 2 },
6702 {4, 242, 2, 7 },
6703 {5, 243, 2, 2 },
6704 {6, 243, 2, 7 },
6705 {7, 244, 2, 2 },
6706 {8, 244, 2, 7 },
6707 {9, 245, 2, 2 },
6708 {10, 245, 2, 7 },
6709 {11, 246, 2, 2 },
6710 {12, 246, 2, 7 },
6711 {13, 247, 2, 2 },
6712 {14, 248, 2, 4 },
6713
6714 /* 802.11 UNI / HyperLan 2 */
6715 {36, 0x56, 0, 4},
6716 {38, 0x56, 0, 6},
6717 {40, 0x56, 0, 8},
6718 {44, 0x57, 0, 0},
6719 {46, 0x57, 0, 2},
6720 {48, 0x57, 0, 4},
6721 {52, 0x57, 0, 8},
6722 {54, 0x57, 0, 10},
6723 {56, 0x58, 0, 0},
6724 {60, 0x58, 0, 4},
6725 {62, 0x58, 0, 6},
6726 {64, 0x58, 0, 8},
6727
6728 /* 802.11 HyperLan 2 */
6729 {100, 0x5b, 0, 8},
6730 {102, 0x5b, 0, 10},
6731 {104, 0x5c, 0, 0},
6732 {108, 0x5c, 0, 4},
6733 {110, 0x5c, 0, 6},
6734 {112, 0x5c, 0, 8},
6735 {116, 0x5d, 0, 0},
6736 {118, 0x5d, 0, 2},
6737 {120, 0x5d, 0, 4},
6738 {124, 0x5d, 0, 8},
6739 {126, 0x5d, 0, 10},
6740 {128, 0x5e, 0, 0},
6741 {132, 0x5e, 0, 4},
6742 {134, 0x5e, 0, 6},
6743 {136, 0x5e, 0, 8},
6744 {140, 0x5f, 0, 0},
6745
6746 /* 802.11 UNII */
6747 {149, 0x5f, 0, 9},
6748 {151, 0x5f, 0, 11},
6749 {153, 0x60, 0, 1},
6750 {157, 0x60, 0, 5},
6751 {159, 0x60, 0, 7},
6752 {161, 0x60, 0, 9},
6753 {165, 0x61, 0, 1},
6754 {167, 0x61, 0, 3},
6755 {169, 0x61, 0, 5},
6756 {171, 0x61, 0, 7},
6757 {173, 0x61, 0, 9},
6758 };
6759
6760 static const struct rf_channel rf_vals_5592_xtal20[] = {
6761 /* Channel, N, K, mod, R */
6762 {1, 482, 4, 10, 3},
6763 {2, 483, 4, 10, 3},
6764 {3, 484, 4, 10, 3},
6765 {4, 485, 4, 10, 3},
6766 {5, 486, 4, 10, 3},
6767 {6, 487, 4, 10, 3},
6768 {7, 488, 4, 10, 3},
6769 {8, 489, 4, 10, 3},
6770 {9, 490, 4, 10, 3},
6771 {10, 491, 4, 10, 3},
6772 {11, 492, 4, 10, 3},
6773 {12, 493, 4, 10, 3},
6774 {13, 494, 4, 10, 3},
6775 {14, 496, 8, 10, 3},
6776 {36, 172, 8, 12, 1},
6777 {38, 173, 0, 12, 1},
6778 {40, 173, 4, 12, 1},
6779 {42, 173, 8, 12, 1},
6780 {44, 174, 0, 12, 1},
6781 {46, 174, 4, 12, 1},
6782 {48, 174, 8, 12, 1},
6783 {50, 175, 0, 12, 1},
6784 {52, 175, 4, 12, 1},
6785 {54, 175, 8, 12, 1},
6786 {56, 176, 0, 12, 1},
6787 {58, 176, 4, 12, 1},
6788 {60, 176, 8, 12, 1},
6789 {62, 177, 0, 12, 1},
6790 {64, 177, 4, 12, 1},
6791 {100, 183, 4, 12, 1},
6792 {102, 183, 8, 12, 1},
6793 {104, 184, 0, 12, 1},
6794 {106, 184, 4, 12, 1},
6795 {108, 184, 8, 12, 1},
6796 {110, 185, 0, 12, 1},
6797 {112, 185, 4, 12, 1},
6798 {114, 185, 8, 12, 1},
6799 {116, 186, 0, 12, 1},
6800 {118, 186, 4, 12, 1},
6801 {120, 186, 8, 12, 1},
6802 {122, 187, 0, 12, 1},
6803 {124, 187, 4, 12, 1},
6804 {126, 187, 8, 12, 1},
6805 {128, 188, 0, 12, 1},
6806 {130, 188, 4, 12, 1},
6807 {132, 188, 8, 12, 1},
6808 {134, 189, 0, 12, 1},
6809 {136, 189, 4, 12, 1},
6810 {138, 189, 8, 12, 1},
6811 {140, 190, 0, 12, 1},
6812 {149, 191, 6, 12, 1},
6813 {151, 191, 10, 12, 1},
6814 {153, 192, 2, 12, 1},
6815 {155, 192, 6, 12, 1},
6816 {157, 192, 10, 12, 1},
6817 {159, 193, 2, 12, 1},
6818 {161, 193, 6, 12, 1},
6819 {165, 194, 2, 12, 1},
6820 {184, 164, 0, 12, 1},
6821 {188, 164, 4, 12, 1},
6822 {192, 165, 8, 12, 1},
6823 {196, 166, 0, 12, 1},
6824 };
6825
6826 static const struct rf_channel rf_vals_5592_xtal40[] = {
6827 /* Channel, N, K, mod, R */
6828 {1, 241, 2, 10, 3},
6829 {2, 241, 7, 10, 3},
6830 {3, 242, 2, 10, 3},
6831 {4, 242, 7, 10, 3},
6832 {5, 243, 2, 10, 3},
6833 {6, 243, 7, 10, 3},
6834 {7, 244, 2, 10, 3},
6835 {8, 244, 7, 10, 3},
6836 {9, 245, 2, 10, 3},
6837 {10, 245, 7, 10, 3},
6838 {11, 246, 2, 10, 3},
6839 {12, 246, 7, 10, 3},
6840 {13, 247, 2, 10, 3},
6841 {14, 248, 4, 10, 3},
6842 {36, 86, 4, 12, 1},
6843 {38, 86, 6, 12, 1},
6844 {40, 86, 8, 12, 1},
6845 {42, 86, 10, 12, 1},
6846 {44, 87, 0, 12, 1},
6847 {46, 87, 2, 12, 1},
6848 {48, 87, 4, 12, 1},
6849 {50, 87, 6, 12, 1},
6850 {52, 87, 8, 12, 1},
6851 {54, 87, 10, 12, 1},
6852 {56, 88, 0, 12, 1},
6853 {58, 88, 2, 12, 1},
6854 {60, 88, 4, 12, 1},
6855 {62, 88, 6, 12, 1},
6856 {64, 88, 8, 12, 1},
6857 {100, 91, 8, 12, 1},
6858 {102, 91, 10, 12, 1},
6859 {104, 92, 0, 12, 1},
6860 {106, 92, 2, 12, 1},
6861 {108, 92, 4, 12, 1},
6862 {110, 92, 6, 12, 1},
6863 {112, 92, 8, 12, 1},
6864 {114, 92, 10, 12, 1},
6865 {116, 93, 0, 12, 1},
6866 {118, 93, 2, 12, 1},
6867 {120, 93, 4, 12, 1},
6868 {122, 93, 6, 12, 1},
6869 {124, 93, 8, 12, 1},
6870 {126, 93, 10, 12, 1},
6871 {128, 94, 0, 12, 1},
6872 {130, 94, 2, 12, 1},
6873 {132, 94, 4, 12, 1},
6874 {134, 94, 6, 12, 1},
6875 {136, 94, 8, 12, 1},
6876 {138, 94, 10, 12, 1},
6877 {140, 95, 0, 12, 1},
6878 {149, 95, 9, 12, 1},
6879 {151, 95, 11, 12, 1},
6880 {153, 96, 1, 12, 1},
6881 {155, 96, 3, 12, 1},
6882 {157, 96, 5, 12, 1},
6883 {159, 96, 7, 12, 1},
6884 {161, 96, 9, 12, 1},
6885 {165, 97, 1, 12, 1},
6886 {184, 82, 0, 12, 1},
6887 {188, 82, 4, 12, 1},
6888 {192, 82, 8, 12, 1},
6889 {196, 83, 0, 12, 1},
6890 };
6891
6892 static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
6893 {
6894 struct hw_mode_spec *spec = &rt2x00dev->spec;
6895 struct channel_info *info;
6896 char *default_power1;
6897 char *default_power2;
6898 unsigned int i;
6899 u16 eeprom;
6900 u32 reg;
6901
6902 /*
6903 * Disable powersaving as default on PCI devices.
6904 */
6905 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
6906 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
6907
6908 /*
6909 * Initialize all hw fields.
6910 */
6911 rt2x00dev->hw->flags =
6912 IEEE80211_HW_SIGNAL_DBM |
6913 IEEE80211_HW_SUPPORTS_PS |
6914 IEEE80211_HW_PS_NULLFUNC_STACK |
6915 IEEE80211_HW_AMPDU_AGGREGATION |
6916 IEEE80211_HW_REPORTS_TX_ACK_STATUS;
6917
6918 /*
6919 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
6920 * unless we are capable of sending the buffered frames out after the
6921 * DTIM transmission using rt2x00lib_beacondone. This will send out
6922 * multicast and broadcast traffic immediately instead of buffering it
6923 * infinitly and thus dropping it after some time.
6924 */
6925 if (!rt2x00_is_usb(rt2x00dev))
6926 rt2x00dev->hw->flags |=
6927 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
6928
6929 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
6930 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
6931 rt2800_eeprom_addr(rt2x00dev,
6932 EEPROM_MAC_ADDR_0));
6933
6934 /*
6935 * As rt2800 has a global fallback table we cannot specify
6936 * more then one tx rate per frame but since the hw will
6937 * try several rates (based on the fallback table) we should
6938 * initialize max_report_rates to the maximum number of rates
6939 * we are going to try. Otherwise mac80211 will truncate our
6940 * reported tx rates and the rc algortihm will end up with
6941 * incorrect data.
6942 */
6943 rt2x00dev->hw->max_rates = 1;
6944 rt2x00dev->hw->max_report_rates = 7;
6945 rt2x00dev->hw->max_rate_tries = 1;
6946
6947 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
6948
6949 /*
6950 * Initialize hw_mode information.
6951 */
6952 spec->supported_bands = SUPPORT_BAND_2GHZ;
6953 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
6954
6955 if (rt2x00_rf(rt2x00dev, RF2820) ||
6956 rt2x00_rf(rt2x00dev, RF2720)) {
6957 spec->num_channels = 14;
6958 spec->channels = rf_vals;
6959 } else if (rt2x00_rf(rt2x00dev, RF2850) ||
6960 rt2x00_rf(rt2x00dev, RF2750)) {
6961 spec->supported_bands |= SUPPORT_BAND_5GHZ;
6962 spec->num_channels = ARRAY_SIZE(rf_vals);
6963 spec->channels = rf_vals;
6964 } else if (rt2x00_rf(rt2x00dev, RF3020) ||
6965 rt2x00_rf(rt2x00dev, RF2020) ||
6966 rt2x00_rf(rt2x00dev, RF3021) ||
6967 rt2x00_rf(rt2x00dev, RF3022) ||
6968 rt2x00_rf(rt2x00dev, RF3290) ||
6969 rt2x00_rf(rt2x00dev, RF3320) ||
6970 rt2x00_rf(rt2x00dev, RF3322) ||
6971 rt2x00_rf(rt2x00dev, RF5360) ||
6972 rt2x00_rf(rt2x00dev, RF5370) ||
6973 rt2x00_rf(rt2x00dev, RF5372) ||
6974 rt2x00_rf(rt2x00dev, RF5390) ||
6975 rt2x00_rf(rt2x00dev, RF5392)) {
6976 spec->num_channels = 14;
6977 spec->channels = rf_vals_3x;
6978 } else if (rt2x00_rf(rt2x00dev, RF3052)) {
6979 spec->supported_bands |= SUPPORT_BAND_5GHZ;
6980 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
6981 spec->channels = rf_vals_3x;
6982 } else if (rt2x00_rf(rt2x00dev, RF5592)) {
6983 spec->supported_bands |= SUPPORT_BAND_5GHZ;
6984
6985 rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX, &reg);
6986 if (rt2x00_get_field32(reg, MAC_DEBUG_INDEX_XTAL)) {
6987 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal40);
6988 spec->channels = rf_vals_5592_xtal40;
6989 } else {
6990 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal20);
6991 spec->channels = rf_vals_5592_xtal20;
6992 }
6993 }
6994
6995 if (WARN_ON_ONCE(!spec->channels))
6996 return -ENODEV;
6997
6998 /*
6999 * Initialize HT information.
7000 */
7001 if (!rt2x00_rf(rt2x00dev, RF2020))
7002 spec->ht.ht_supported = true;
7003 else
7004 spec->ht.ht_supported = false;
7005
7006 spec->ht.cap =
7007 IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
7008 IEEE80211_HT_CAP_GRN_FLD |
7009 IEEE80211_HT_CAP_SGI_20 |
7010 IEEE80211_HT_CAP_SGI_40;
7011
7012 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) >= 2)
7013 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
7014
7015 spec->ht.cap |=
7016 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) <<
7017 IEEE80211_HT_CAP_RX_STBC_SHIFT;
7018
7019 spec->ht.ampdu_factor = 3;
7020 spec->ht.ampdu_density = 4;
7021 spec->ht.mcs.tx_params =
7022 IEEE80211_HT_MCS_TX_DEFINED |
7023 IEEE80211_HT_MCS_TX_RX_DIFF |
7024 ((rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) - 1) <<
7025 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
7026
7027 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH)) {
7028 case 3:
7029 spec->ht.mcs.rx_mask[2] = 0xff;
7030 case 2:
7031 spec->ht.mcs.rx_mask[1] = 0xff;
7032 case 1:
7033 spec->ht.mcs.rx_mask[0] = 0xff;
7034 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
7035 break;
7036 }
7037
7038 /*
7039 * Create channel information array
7040 */
7041 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
7042 if (!info)
7043 return -ENOMEM;
7044
7045 spec->channels_info = info;
7046
7047 default_power1 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
7048 default_power2 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
7049
7050 for (i = 0; i < 14; i++) {
7051 info[i].default_power1 = default_power1[i];
7052 info[i].default_power2 = default_power2[i];
7053 }
7054
7055 if (spec->num_channels > 14) {
7056 default_power1 = rt2800_eeprom_addr(rt2x00dev,
7057 EEPROM_TXPOWER_A1);
7058 default_power2 = rt2800_eeprom_addr(rt2x00dev,
7059 EEPROM_TXPOWER_A2);
7060
7061 for (i = 14; i < spec->num_channels; i++) {
7062 info[i].default_power1 = default_power1[i - 14];
7063 info[i].default_power2 = default_power2[i - 14];
7064 }
7065 }
7066
7067 switch (rt2x00dev->chip.rf) {
7068 case RF2020:
7069 case RF3020:
7070 case RF3021:
7071 case RF3022:
7072 case RF3320:
7073 case RF3052:
7074 case RF3290:
7075 case RF5360:
7076 case RF5370:
7077 case RF5372:
7078 case RF5390:
7079 case RF5392:
7080 __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags);
7081 break;
7082 }
7083
7084 return 0;
7085 }
7086
7087 static int rt2800_probe_rt(struct rt2x00_dev *rt2x00dev)
7088 {
7089 u32 reg;
7090 u32 rt;
7091 u32 rev;
7092
7093 if (rt2x00_rt(rt2x00dev, RT3290))
7094 rt2800_register_read(rt2x00dev, MAC_CSR0_3290, &reg);
7095 else
7096 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
7097
7098 rt = rt2x00_get_field32(reg, MAC_CSR0_CHIPSET);
7099 rev = rt2x00_get_field32(reg, MAC_CSR0_REVISION);
7100
7101 switch (rt) {
7102 case RT2860:
7103 case RT2872:
7104 case RT2883:
7105 case RT3070:
7106 case RT3071:
7107 case RT3090:
7108 case RT3290:
7109 case RT3352:
7110 case RT3390:
7111 case RT3572:
7112 case RT5390:
7113 case RT5392:
7114 case RT5592:
7115 break;
7116 default:
7117 rt2x00_err(rt2x00dev, "Invalid RT chipset 0x%04x, rev %04x detected\n",
7118 rt, rev);
7119 return -ENODEV;
7120 }
7121
7122 rt2x00_set_rt(rt2x00dev, rt, rev);
7123
7124 return 0;
7125 }
7126
7127 int rt2800_probe_hw(struct rt2x00_dev *rt2x00dev)
7128 {
7129 int retval;
7130 u32 reg;
7131
7132 retval = rt2800_probe_rt(rt2x00dev);
7133 if (retval)
7134 return retval;
7135
7136 /*
7137 * Allocate eeprom data.
7138 */
7139 retval = rt2800_validate_eeprom(rt2x00dev);
7140 if (retval)
7141 return retval;
7142
7143 retval = rt2800_init_eeprom(rt2x00dev);
7144 if (retval)
7145 return retval;
7146
7147 /*
7148 * Enable rfkill polling by setting GPIO direction of the
7149 * rfkill switch GPIO pin correctly.
7150 */
7151 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
7152 rt2x00_set_field32(&reg, GPIO_CTRL_DIR2, 1);
7153 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
7154
7155 /*
7156 * Initialize hw specifications.
7157 */
7158 retval = rt2800_probe_hw_mode(rt2x00dev);
7159 if (retval)
7160 return retval;
7161
7162 /*
7163 * Set device capabilities.
7164 */
7165 __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
7166 __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags);
7167 if (!rt2x00_is_usb(rt2x00dev))
7168 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags);
7169
7170 /*
7171 * Set device requirements.
7172 */
7173 if (!rt2x00_is_soc(rt2x00dev))
7174 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
7175 __set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags);
7176 __set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags);
7177 if (!rt2800_hwcrypt_disabled(rt2x00dev))
7178 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
7179 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
7180 __set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags);
7181 if (rt2x00_is_usb(rt2x00dev))
7182 __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags);
7183 else {
7184 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
7185 __set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags);
7186 }
7187
7188 /*
7189 * Set the rssi offset.
7190 */
7191 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
7192
7193 return 0;
7194 }
7195 EXPORT_SYMBOL_GPL(rt2800_probe_hw);
7196
7197 /*
7198 * IEEE80211 stack callback functions.
7199 */
7200 void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
7201 u16 *iv16)
7202 {
7203 struct rt2x00_dev *rt2x00dev = hw->priv;
7204 struct mac_iveiv_entry iveiv_entry;
7205 u32 offset;
7206
7207 offset = MAC_IVEIV_ENTRY(hw_key_idx);
7208 rt2800_register_multiread(rt2x00dev, offset,
7209 &iveiv_entry, sizeof(iveiv_entry));
7210
7211 memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
7212 memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
7213 }
7214 EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
7215
7216 int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
7217 {
7218 struct rt2x00_dev *rt2x00dev = hw->priv;
7219 u32 reg;
7220 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
7221
7222 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
7223 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
7224 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
7225
7226 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
7227 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
7228 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
7229
7230 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
7231 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
7232 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
7233
7234 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
7235 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
7236 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
7237
7238 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
7239 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
7240 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
7241
7242 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
7243 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
7244 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
7245
7246 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
7247 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
7248 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
7249
7250 return 0;
7251 }
7252 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
7253
7254 int rt2800_conf_tx(struct ieee80211_hw *hw,
7255 struct ieee80211_vif *vif, u16 queue_idx,
7256 const struct ieee80211_tx_queue_params *params)
7257 {
7258 struct rt2x00_dev *rt2x00dev = hw->priv;
7259 struct data_queue *queue;
7260 struct rt2x00_field32 field;
7261 int retval;
7262 u32 reg;
7263 u32 offset;
7264
7265 /*
7266 * First pass the configuration through rt2x00lib, that will
7267 * update the queue settings and validate the input. After that
7268 * we are free to update the registers based on the value
7269 * in the queue parameter.
7270 */
7271 retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params);
7272 if (retval)
7273 return retval;
7274
7275 /*
7276 * We only need to perform additional register initialization
7277 * for WMM queues/
7278 */
7279 if (queue_idx >= 4)
7280 return 0;
7281
7282 queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
7283
7284 /* Update WMM TXOP register */
7285 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
7286 field.bit_offset = (queue_idx & 1) * 16;
7287 field.bit_mask = 0xffff << field.bit_offset;
7288
7289 rt2800_register_read(rt2x00dev, offset, &reg);
7290 rt2x00_set_field32(&reg, field, queue->txop);
7291 rt2800_register_write(rt2x00dev, offset, reg);
7292
7293 /* Update WMM registers */
7294 field.bit_offset = queue_idx * 4;
7295 field.bit_mask = 0xf << field.bit_offset;
7296
7297 rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
7298 rt2x00_set_field32(&reg, field, queue->aifs);
7299 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
7300
7301 rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
7302 rt2x00_set_field32(&reg, field, queue->cw_min);
7303 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
7304
7305 rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
7306 rt2x00_set_field32(&reg, field, queue->cw_max);
7307 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
7308
7309 /* Update EDCA registers */
7310 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
7311
7312 rt2800_register_read(rt2x00dev, offset, &reg);
7313 rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
7314 rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
7315 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
7316 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
7317 rt2800_register_write(rt2x00dev, offset, reg);
7318
7319 return 0;
7320 }
7321 EXPORT_SYMBOL_GPL(rt2800_conf_tx);
7322
7323 u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
7324 {
7325 struct rt2x00_dev *rt2x00dev = hw->priv;
7326 u64 tsf;
7327 u32 reg;
7328
7329 rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
7330 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
7331 rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
7332 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
7333
7334 return tsf;
7335 }
7336 EXPORT_SYMBOL_GPL(rt2800_get_tsf);
7337
7338 int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
7339 enum ieee80211_ampdu_mlme_action action,
7340 struct ieee80211_sta *sta, u16 tid, u16 *ssn,
7341 u8 buf_size)
7342 {
7343 struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv;
7344 int ret = 0;
7345
7346 /*
7347 * Don't allow aggregation for stations the hardware isn't aware
7348 * of because tx status reports for frames to an unknown station
7349 * always contain wcid=255 and thus we can't distinguish between
7350 * multiple stations which leads to unwanted situations when the
7351 * hw reorders frames due to aggregation.
7352 */
7353 if (sta_priv->wcid < 0)
7354 return 1;
7355
7356 switch (action) {
7357 case IEEE80211_AMPDU_RX_START:
7358 case IEEE80211_AMPDU_RX_STOP:
7359 /*
7360 * The hw itself takes care of setting up BlockAck mechanisms.
7361 * So, we only have to allow mac80211 to nagotiate a BlockAck
7362 * agreement. Once that is done, the hw will BlockAck incoming
7363 * AMPDUs without further setup.
7364 */
7365 break;
7366 case IEEE80211_AMPDU_TX_START:
7367 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
7368 break;
7369 case IEEE80211_AMPDU_TX_STOP_CONT:
7370 case IEEE80211_AMPDU_TX_STOP_FLUSH:
7371 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
7372 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
7373 break;
7374 case IEEE80211_AMPDU_TX_OPERATIONAL:
7375 break;
7376 default:
7377 rt2x00_warn((struct rt2x00_dev *)hw->priv,
7378 "Unknown AMPDU action\n");
7379 }
7380
7381 return ret;
7382 }
7383 EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
7384
7385 int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
7386 struct survey_info *survey)
7387 {
7388 struct rt2x00_dev *rt2x00dev = hw->priv;
7389 struct ieee80211_conf *conf = &hw->conf;
7390 u32 idle, busy, busy_ext;
7391
7392 if (idx != 0)
7393 return -ENOENT;
7394
7395 survey->channel = conf->chandef.chan;
7396
7397 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle);
7398 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy);
7399 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext);
7400
7401 if (idle || busy) {
7402 survey->filled = SURVEY_INFO_CHANNEL_TIME |
7403 SURVEY_INFO_CHANNEL_TIME_BUSY |
7404 SURVEY_INFO_CHANNEL_TIME_EXT_BUSY;
7405
7406 survey->channel_time = (idle + busy) / 1000;
7407 survey->channel_time_busy = busy / 1000;
7408 survey->channel_time_ext_busy = busy_ext / 1000;
7409 }
7410
7411 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
7412 survey->filled |= SURVEY_INFO_IN_USE;
7413
7414 return 0;
7415
7416 }
7417 EXPORT_SYMBOL_GPL(rt2800_get_survey);
7418
7419 MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
7420 MODULE_VERSION(DRV_VERSION);
7421 MODULE_DESCRIPTION("Ralink RT2800 library");
7422 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
This page took 0.216809 seconds and 6 git commands to generate.