2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
3 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
4 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
5 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
7 Based on the original rt2800pci.c and rt2800usb.c.
8 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
9 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
10 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
11 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
12 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
13 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
14 <http://rt2x00.serialmonkey.com>
16 This program is free software; you can redistribute it and/or modify
17 it under the terms of the GNU General Public License as published by
18 the Free Software Foundation; either version 2 of the License, or
19 (at your option) any later version.
21 This program is distributed in the hope that it will be useful,
22 but WITHOUT ANY WARRANTY; without even the implied warranty of
23 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 GNU General Public License for more details.
26 You should have received a copy of the GNU General Public License
27 along with this program; if not, write to the
28 Free Software Foundation, Inc.,
29 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
34 Abstract: rt2800 generic device routines.
37 #include <linux/crc-ccitt.h>
38 #include <linux/kernel.h>
39 #include <linux/module.h>
40 #include <linux/slab.h>
43 #include "rt2800lib.h"
48 * All access to the CSR registers will go through the methods
49 * rt2800_register_read and rt2800_register_write.
50 * BBP and RF register require indirect register access,
51 * and use the CSR registers BBPCSR and RFCSR to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
55 * between each attampt. When the busy bit is still set at that time,
56 * the access attempt is considered to have failed,
57 * and we will print an error.
58 * The _lock versions must be used if you already hold the csr_mutex
60 #define WAIT_FOR_BBP(__dev, __reg) \
61 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
62 #define WAIT_FOR_RFCSR(__dev, __reg) \
63 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
64 #define WAIT_FOR_RF(__dev, __reg) \
65 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
66 #define WAIT_FOR_MCU(__dev, __reg) \
67 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
68 H2M_MAILBOX_CSR_OWNER, (__reg))
70 static inline bool rt2800_is_305x_soc(struct rt2x00_dev
*rt2x00dev
)
72 /* check for rt2872 on SoC */
73 if (!rt2x00_is_soc(rt2x00dev
) ||
74 !rt2x00_rt(rt2x00dev
, RT2872
))
77 /* we know for sure that these rf chipsets are used on rt305x boards */
78 if (rt2x00_rf(rt2x00dev
, RF3020
) ||
79 rt2x00_rf(rt2x00dev
, RF3021
) ||
80 rt2x00_rf(rt2x00dev
, RF3022
))
83 rt2x00_warn(rt2x00dev
, "Unknown RF chipset on rt305x\n");
87 static void rt2800_bbp_write(struct rt2x00_dev
*rt2x00dev
,
88 const unsigned int word
, const u8 value
)
92 mutex_lock(&rt2x00dev
->csr_mutex
);
95 * Wait until the BBP becomes available, afterwards we
96 * can safely write the new data into the register.
98 if (WAIT_FOR_BBP(rt2x00dev
, ®
)) {
100 rt2x00_set_field32(®
, BBP_CSR_CFG_VALUE
, value
);
101 rt2x00_set_field32(®
, BBP_CSR_CFG_REGNUM
, word
);
102 rt2x00_set_field32(®
, BBP_CSR_CFG_BUSY
, 1);
103 rt2x00_set_field32(®
, BBP_CSR_CFG_READ_CONTROL
, 0);
104 rt2x00_set_field32(®
, BBP_CSR_CFG_BBP_RW_MODE
, 1);
106 rt2800_register_write_lock(rt2x00dev
, BBP_CSR_CFG
, reg
);
109 mutex_unlock(&rt2x00dev
->csr_mutex
);
112 static void rt2800_bbp_read(struct rt2x00_dev
*rt2x00dev
,
113 const unsigned int word
, u8
*value
)
117 mutex_lock(&rt2x00dev
->csr_mutex
);
120 * Wait until the BBP becomes available, afterwards we
121 * can safely write the read request into the register.
122 * After the data has been written, we wait until hardware
123 * returns the correct value, if at any time the register
124 * doesn't become available in time, reg will be 0xffffffff
125 * which means we return 0xff to the caller.
127 if (WAIT_FOR_BBP(rt2x00dev
, ®
)) {
129 rt2x00_set_field32(®
, BBP_CSR_CFG_REGNUM
, word
);
130 rt2x00_set_field32(®
, BBP_CSR_CFG_BUSY
, 1);
131 rt2x00_set_field32(®
, BBP_CSR_CFG_READ_CONTROL
, 1);
132 rt2x00_set_field32(®
, BBP_CSR_CFG_BBP_RW_MODE
, 1);
134 rt2800_register_write_lock(rt2x00dev
, BBP_CSR_CFG
, reg
);
136 WAIT_FOR_BBP(rt2x00dev
, ®
);
139 *value
= rt2x00_get_field32(reg
, BBP_CSR_CFG_VALUE
);
141 mutex_unlock(&rt2x00dev
->csr_mutex
);
144 static void rt2800_rfcsr_write(struct rt2x00_dev
*rt2x00dev
,
145 const unsigned int word
, const u8 value
)
149 mutex_lock(&rt2x00dev
->csr_mutex
);
152 * Wait until the RFCSR becomes available, afterwards we
153 * can safely write the new data into the register.
155 if (WAIT_FOR_RFCSR(rt2x00dev
, ®
)) {
157 rt2x00_set_field32(®
, RF_CSR_CFG_DATA
, value
);
158 rt2x00_set_field32(®
, RF_CSR_CFG_REGNUM
, word
);
159 rt2x00_set_field32(®
, RF_CSR_CFG_WRITE
, 1);
160 rt2x00_set_field32(®
, RF_CSR_CFG_BUSY
, 1);
162 rt2800_register_write_lock(rt2x00dev
, RF_CSR_CFG
, reg
);
165 mutex_unlock(&rt2x00dev
->csr_mutex
);
168 static void rt2800_rfcsr_read(struct rt2x00_dev
*rt2x00dev
,
169 const unsigned int word
, u8
*value
)
173 mutex_lock(&rt2x00dev
->csr_mutex
);
176 * Wait until the RFCSR becomes available, afterwards we
177 * can safely write the read request into the register.
178 * After the data has been written, we wait until hardware
179 * returns the correct value, if at any time the register
180 * doesn't become available in time, reg will be 0xffffffff
181 * which means we return 0xff to the caller.
183 if (WAIT_FOR_RFCSR(rt2x00dev
, ®
)) {
185 rt2x00_set_field32(®
, RF_CSR_CFG_REGNUM
, word
);
186 rt2x00_set_field32(®
, RF_CSR_CFG_WRITE
, 0);
187 rt2x00_set_field32(®
, RF_CSR_CFG_BUSY
, 1);
189 rt2800_register_write_lock(rt2x00dev
, RF_CSR_CFG
, reg
);
191 WAIT_FOR_RFCSR(rt2x00dev
, ®
);
194 *value
= rt2x00_get_field32(reg
, RF_CSR_CFG_DATA
);
196 mutex_unlock(&rt2x00dev
->csr_mutex
);
199 static void rt2800_rf_write(struct rt2x00_dev
*rt2x00dev
,
200 const unsigned int word
, const u32 value
)
204 mutex_lock(&rt2x00dev
->csr_mutex
);
207 * Wait until the RF becomes available, afterwards we
208 * can safely write the new data into the register.
210 if (WAIT_FOR_RF(rt2x00dev
, ®
)) {
212 rt2x00_set_field32(®
, RF_CSR_CFG0_REG_VALUE_BW
, value
);
213 rt2x00_set_field32(®
, RF_CSR_CFG0_STANDBYMODE
, 0);
214 rt2x00_set_field32(®
, RF_CSR_CFG0_SEL
, 0);
215 rt2x00_set_field32(®
, RF_CSR_CFG0_BUSY
, 1);
217 rt2800_register_write_lock(rt2x00dev
, RF_CSR_CFG0
, reg
);
218 rt2x00_rf_write(rt2x00dev
, word
, value
);
221 mutex_unlock(&rt2x00dev
->csr_mutex
);
224 static const unsigned int rt2800_eeprom_map
[EEPROM_WORD_COUNT
] = {
225 [EEPROM_CHIP_ID
] = 0x0000,
226 [EEPROM_VERSION
] = 0x0001,
227 [EEPROM_MAC_ADDR_0
] = 0x0002,
228 [EEPROM_MAC_ADDR_1
] = 0x0003,
229 [EEPROM_MAC_ADDR_2
] = 0x0004,
230 [EEPROM_NIC_CONF0
] = 0x001a,
231 [EEPROM_NIC_CONF1
] = 0x001b,
232 [EEPROM_FREQ
] = 0x001d,
233 [EEPROM_LED_AG_CONF
] = 0x001e,
234 [EEPROM_LED_ACT_CONF
] = 0x001f,
235 [EEPROM_LED_POLARITY
] = 0x0020,
236 [EEPROM_NIC_CONF2
] = 0x0021,
237 [EEPROM_LNA
] = 0x0022,
238 [EEPROM_RSSI_BG
] = 0x0023,
239 [EEPROM_RSSI_BG2
] = 0x0024,
240 [EEPROM_TXMIXER_GAIN_BG
] = 0x0024, /* overlaps with RSSI_BG2 */
241 [EEPROM_RSSI_A
] = 0x0025,
242 [EEPROM_RSSI_A2
] = 0x0026,
243 [EEPROM_TXMIXER_GAIN_A
] = 0x0026, /* overlaps with RSSI_A2 */
244 [EEPROM_EIRP_MAX_TX_POWER
] = 0x0027,
245 [EEPROM_TXPOWER_DELTA
] = 0x0028,
246 [EEPROM_TXPOWER_BG1
] = 0x0029,
247 [EEPROM_TXPOWER_BG2
] = 0x0030,
248 [EEPROM_TSSI_BOUND_BG1
] = 0x0037,
249 [EEPROM_TSSI_BOUND_BG2
] = 0x0038,
250 [EEPROM_TSSI_BOUND_BG3
] = 0x0039,
251 [EEPROM_TSSI_BOUND_BG4
] = 0x003a,
252 [EEPROM_TSSI_BOUND_BG5
] = 0x003b,
253 [EEPROM_TXPOWER_A1
] = 0x003c,
254 [EEPROM_TXPOWER_A2
] = 0x0053,
255 [EEPROM_TSSI_BOUND_A1
] = 0x006a,
256 [EEPROM_TSSI_BOUND_A2
] = 0x006b,
257 [EEPROM_TSSI_BOUND_A3
] = 0x006c,
258 [EEPROM_TSSI_BOUND_A4
] = 0x006d,
259 [EEPROM_TSSI_BOUND_A5
] = 0x006e,
260 [EEPROM_TXPOWER_BYRATE
] = 0x006f,
261 [EEPROM_BBP_START
] = 0x0078,
264 static const unsigned int rt2800_eeprom_map_ext
[EEPROM_WORD_COUNT
] = {
265 [EEPROM_CHIP_ID
] = 0x0000,
266 [EEPROM_VERSION
] = 0x0001,
267 [EEPROM_MAC_ADDR_0
] = 0x0002,
268 [EEPROM_MAC_ADDR_1
] = 0x0003,
269 [EEPROM_MAC_ADDR_2
] = 0x0004,
270 [EEPROM_NIC_CONF0
] = 0x001a,
271 [EEPROM_NIC_CONF1
] = 0x001b,
272 [EEPROM_NIC_CONF2
] = 0x001c,
273 [EEPROM_EIRP_MAX_TX_POWER
] = 0x0020,
274 [EEPROM_FREQ
] = 0x0022,
275 [EEPROM_LED_AG_CONF
] = 0x0023,
276 [EEPROM_LED_ACT_CONF
] = 0x0024,
277 [EEPROM_LED_POLARITY
] = 0x0025,
278 [EEPROM_LNA
] = 0x0026,
279 [EEPROM_EXT_LNA2
] = 0x0027,
280 [EEPROM_RSSI_BG
] = 0x0028,
281 [EEPROM_RSSI_BG2
] = 0x0029,
282 [EEPROM_RSSI_A
] = 0x002a,
283 [EEPROM_RSSI_A2
] = 0x002b,
284 [EEPROM_TXPOWER_BG1
] = 0x0030,
285 [EEPROM_TXPOWER_BG2
] = 0x0037,
286 [EEPROM_EXT_TXPOWER_BG3
] = 0x003e,
287 [EEPROM_TSSI_BOUND_BG1
] = 0x0045,
288 [EEPROM_TSSI_BOUND_BG2
] = 0x0046,
289 [EEPROM_TSSI_BOUND_BG3
] = 0x0047,
290 [EEPROM_TSSI_BOUND_BG4
] = 0x0048,
291 [EEPROM_TSSI_BOUND_BG5
] = 0x0049,
292 [EEPROM_TXPOWER_A1
] = 0x004b,
293 [EEPROM_TXPOWER_A2
] = 0x0065,
294 [EEPROM_EXT_TXPOWER_A3
] = 0x007f,
295 [EEPROM_TSSI_BOUND_A1
] = 0x009a,
296 [EEPROM_TSSI_BOUND_A2
] = 0x009b,
297 [EEPROM_TSSI_BOUND_A3
] = 0x009c,
298 [EEPROM_TSSI_BOUND_A4
] = 0x009d,
299 [EEPROM_TSSI_BOUND_A5
] = 0x009e,
300 [EEPROM_TXPOWER_BYRATE
] = 0x00a0,
303 static unsigned int rt2800_eeprom_word_index(struct rt2x00_dev
*rt2x00dev
,
304 const enum rt2800_eeprom_word word
)
306 const unsigned int *map
;
309 if (WARN_ONCE(word
>= EEPROM_WORD_COUNT
,
310 "%s: invalid EEPROM word %d\n",
311 wiphy_name(rt2x00dev
->hw
->wiphy
), word
))
314 if (rt2x00_rt(rt2x00dev
, RT3593
))
315 map
= rt2800_eeprom_map_ext
;
317 map
= rt2800_eeprom_map
;
321 /* Index 0 is valid only for EEPROM_CHIP_ID.
322 * Otherwise it means that the offset of the
323 * given word is not initialized in the map,
324 * or that the field is not usable on the
327 WARN_ONCE(word
!= EEPROM_CHIP_ID
&& index
== 0,
328 "%s: invalid access of EEPROM word %d\n",
329 wiphy_name(rt2x00dev
->hw
->wiphy
), word
);
334 static void *rt2800_eeprom_addr(struct rt2x00_dev
*rt2x00dev
,
335 const enum rt2800_eeprom_word word
)
339 index
= rt2800_eeprom_word_index(rt2x00dev
, word
);
340 return rt2x00_eeprom_addr(rt2x00dev
, index
);
343 static void rt2800_eeprom_read(struct rt2x00_dev
*rt2x00dev
,
344 const enum rt2800_eeprom_word word
, u16
*data
)
348 index
= rt2800_eeprom_word_index(rt2x00dev
, word
);
349 rt2x00_eeprom_read(rt2x00dev
, index
, data
);
352 static void rt2800_eeprom_write(struct rt2x00_dev
*rt2x00dev
,
353 const enum rt2800_eeprom_word word
, u16 data
)
357 index
= rt2800_eeprom_word_index(rt2x00dev
, word
);
358 rt2x00_eeprom_write(rt2x00dev
, index
, data
);
361 static void rt2800_eeprom_read_from_array(struct rt2x00_dev
*rt2x00dev
,
362 const enum rt2800_eeprom_word array
,
368 index
= rt2800_eeprom_word_index(rt2x00dev
, array
);
369 rt2x00_eeprom_read(rt2x00dev
, index
+ offset
, data
);
372 static int rt2800_enable_wlan_rt3290(struct rt2x00_dev
*rt2x00dev
)
377 rt2800_register_read(rt2x00dev
, WLAN_FUN_CTRL
, ®
);
378 if (rt2x00_get_field32(reg
, WLAN_EN
))
381 rt2x00_set_field32(®
, WLAN_GPIO_OUT_OE_BIT_ALL
, 0xff);
382 rt2x00_set_field32(®
, FRC_WL_ANT_SET
, 1);
383 rt2x00_set_field32(®
, WLAN_CLK_EN
, 0);
384 rt2x00_set_field32(®
, WLAN_EN
, 1);
385 rt2800_register_write(rt2x00dev
, WLAN_FUN_CTRL
, reg
);
387 udelay(REGISTER_BUSY_DELAY
);
392 * Check PLL_LD & XTAL_RDY.
394 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
395 rt2800_register_read(rt2x00dev
, CMB_CTRL
, ®
);
396 if (rt2x00_get_field32(reg
, PLL_LD
) &&
397 rt2x00_get_field32(reg
, XTAL_RDY
))
399 udelay(REGISTER_BUSY_DELAY
);
402 if (i
>= REGISTER_BUSY_COUNT
) {
407 rt2800_register_write(rt2x00dev
, 0x58, 0x018);
408 udelay(REGISTER_BUSY_DELAY
);
409 rt2800_register_write(rt2x00dev
, 0x58, 0x418);
410 udelay(REGISTER_BUSY_DELAY
);
411 rt2800_register_write(rt2x00dev
, 0x58, 0x618);
412 udelay(REGISTER_BUSY_DELAY
);
418 rt2800_register_read(rt2x00dev
, WLAN_FUN_CTRL
, ®
);
419 rt2x00_set_field32(®
, PCIE_APP0_CLK_REQ
, 0);
420 rt2x00_set_field32(®
, WLAN_CLK_EN
, 1);
421 rt2x00_set_field32(®
, WLAN_RESET
, 1);
422 rt2800_register_write(rt2x00dev
, WLAN_FUN_CTRL
, reg
);
424 rt2x00_set_field32(®
, WLAN_RESET
, 0);
425 rt2800_register_write(rt2x00dev
, WLAN_FUN_CTRL
, reg
);
427 rt2800_register_write(rt2x00dev
, INT_SOURCE_CSR
, 0x7fffffff);
428 } while (count
!= 0);
433 void rt2800_mcu_request(struct rt2x00_dev
*rt2x00dev
,
434 const u8 command
, const u8 token
,
435 const u8 arg0
, const u8 arg1
)
440 * SOC devices don't support MCU requests.
442 if (rt2x00_is_soc(rt2x00dev
))
445 mutex_lock(&rt2x00dev
->csr_mutex
);
448 * Wait until the MCU becomes available, afterwards we
449 * can safely write the new data into the register.
451 if (WAIT_FOR_MCU(rt2x00dev
, ®
)) {
452 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_OWNER
, 1);
453 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_CMD_TOKEN
, token
);
454 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_ARG0
, arg0
);
455 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_ARG1
, arg1
);
456 rt2800_register_write_lock(rt2x00dev
, H2M_MAILBOX_CSR
, reg
);
459 rt2x00_set_field32(®
, HOST_CMD_CSR_HOST_COMMAND
, command
);
460 rt2800_register_write_lock(rt2x00dev
, HOST_CMD_CSR
, reg
);
463 mutex_unlock(&rt2x00dev
->csr_mutex
);
465 EXPORT_SYMBOL_GPL(rt2800_mcu_request
);
467 int rt2800_wait_csr_ready(struct rt2x00_dev
*rt2x00dev
)
472 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
473 rt2800_register_read(rt2x00dev
, MAC_CSR0
, ®
);
474 if (reg
&& reg
!= ~0)
479 rt2x00_err(rt2x00dev
, "Unstable hardware\n");
482 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready
);
484 int rt2800_wait_wpdma_ready(struct rt2x00_dev
*rt2x00dev
)
490 * Some devices are really slow to respond here. Wait a whole second
493 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
494 rt2800_register_read(rt2x00dev
, WPDMA_GLO_CFG
, ®
);
495 if (!rt2x00_get_field32(reg
, WPDMA_GLO_CFG_TX_DMA_BUSY
) &&
496 !rt2x00_get_field32(reg
, WPDMA_GLO_CFG_RX_DMA_BUSY
))
502 rt2x00_err(rt2x00dev
, "WPDMA TX/RX busy [0x%08x]\n", reg
);
505 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready
);
507 void rt2800_disable_wpdma(struct rt2x00_dev
*rt2x00dev
)
511 rt2800_register_read(rt2x00dev
, WPDMA_GLO_CFG
, ®
);
512 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_TX_DMA
, 0);
513 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_DMA_BUSY
, 0);
514 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_RX_DMA
, 0);
515 rt2x00_set_field32(®
, WPDMA_GLO_CFG_RX_DMA_BUSY
, 0);
516 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_WRITEBACK_DONE
, 1);
517 rt2800_register_write(rt2x00dev
, WPDMA_GLO_CFG
, reg
);
519 EXPORT_SYMBOL_GPL(rt2800_disable_wpdma
);
521 void rt2800_get_txwi_rxwi_size(struct rt2x00_dev
*rt2x00dev
,
522 unsigned short *txwi_size
,
523 unsigned short *rxwi_size
)
525 switch (rt2x00dev
->chip
.rt
) {
527 *txwi_size
= TXWI_DESC_SIZE_4WORDS
;
528 *rxwi_size
= RXWI_DESC_SIZE_5WORDS
;
532 *txwi_size
= TXWI_DESC_SIZE_5WORDS
;
533 *rxwi_size
= RXWI_DESC_SIZE_6WORDS
;
537 *txwi_size
= TXWI_DESC_SIZE_4WORDS
;
538 *rxwi_size
= RXWI_DESC_SIZE_4WORDS
;
542 EXPORT_SYMBOL_GPL(rt2800_get_txwi_rxwi_size
);
544 static bool rt2800_check_firmware_crc(const u8
*data
, const size_t len
)
550 * The last 2 bytes in the firmware array are the crc checksum itself,
551 * this means that we should never pass those 2 bytes to the crc
554 fw_crc
= (data
[len
- 2] << 8 | data
[len
- 1]);
557 * Use the crc ccitt algorithm.
558 * This will return the same value as the legacy driver which
559 * used bit ordering reversion on the both the firmware bytes
560 * before input input as well as on the final output.
561 * Obviously using crc ccitt directly is much more efficient.
563 crc
= crc_ccitt(~0, data
, len
- 2);
566 * There is a small difference between the crc-itu-t + bitrev and
567 * the crc-ccitt crc calculation. In the latter method the 2 bytes
568 * will be swapped, use swab16 to convert the crc to the correct
573 return fw_crc
== crc
;
576 int rt2800_check_firmware(struct rt2x00_dev
*rt2x00dev
,
577 const u8
*data
, const size_t len
)
584 * PCI(e) & SOC devices require firmware with a length
585 * of 8kb. USB devices require firmware files with a length
586 * of 4kb. Certain USB chipsets however require different firmware,
587 * which Ralink only provides attached to the original firmware
588 * file. Thus for USB devices, firmware files have a length
589 * which is a multiple of 4kb. The firmware for rt3290 chip also
590 * have a length which is a multiple of 4kb.
592 if (rt2x00_is_usb(rt2x00dev
) || rt2x00_rt(rt2x00dev
, RT3290
))
599 * Validate the firmware length
601 if (len
!= fw_len
&& (!multiple
|| (len
% fw_len
) != 0))
602 return FW_BAD_LENGTH
;
605 * Check if the chipset requires one of the upper parts
608 if (rt2x00_is_usb(rt2x00dev
) &&
609 !rt2x00_rt(rt2x00dev
, RT2860
) &&
610 !rt2x00_rt(rt2x00dev
, RT2872
) &&
611 !rt2x00_rt(rt2x00dev
, RT3070
) &&
612 ((len
/ fw_len
) == 1))
613 return FW_BAD_VERSION
;
616 * 8kb firmware files must be checked as if it were
617 * 2 separate firmware files.
619 while (offset
< len
) {
620 if (!rt2800_check_firmware_crc(data
+ offset
, fw_len
))
628 EXPORT_SYMBOL_GPL(rt2800_check_firmware
);
630 int rt2800_load_firmware(struct rt2x00_dev
*rt2x00dev
,
631 const u8
*data
, const size_t len
)
637 if (rt2x00_rt(rt2x00dev
, RT3290
)) {
638 retval
= rt2800_enable_wlan_rt3290(rt2x00dev
);
644 * If driver doesn't wake up firmware here,
645 * rt2800_load_firmware will hang forever when interface is up again.
647 rt2800_register_write(rt2x00dev
, AUTOWAKEUP_CFG
, 0x00000000);
650 * Wait for stable hardware.
652 if (rt2800_wait_csr_ready(rt2x00dev
))
655 if (rt2x00_is_pci(rt2x00dev
)) {
656 if (rt2x00_rt(rt2x00dev
, RT3290
) ||
657 rt2x00_rt(rt2x00dev
, RT3572
) ||
658 rt2x00_rt(rt2x00dev
, RT5390
) ||
659 rt2x00_rt(rt2x00dev
, RT5392
)) {
660 rt2800_register_read(rt2x00dev
, AUX_CTRL
, ®
);
661 rt2x00_set_field32(®
, AUX_CTRL_FORCE_PCIE_CLK
, 1);
662 rt2x00_set_field32(®
, AUX_CTRL_WAKE_PCIE_EN
, 1);
663 rt2800_register_write(rt2x00dev
, AUX_CTRL
, reg
);
665 rt2800_register_write(rt2x00dev
, PWR_PIN_CFG
, 0x00000002);
668 rt2800_disable_wpdma(rt2x00dev
);
671 * Write firmware to the device.
673 rt2800_drv_write_firmware(rt2x00dev
, data
, len
);
676 * Wait for device to stabilize.
678 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
679 rt2800_register_read(rt2x00dev
, PBF_SYS_CTRL
, ®
);
680 if (rt2x00_get_field32(reg
, PBF_SYS_CTRL_READY
))
685 if (i
== REGISTER_BUSY_COUNT
) {
686 rt2x00_err(rt2x00dev
, "PBF system register not ready\n");
691 * Disable DMA, will be reenabled later when enabling
694 rt2800_disable_wpdma(rt2x00dev
);
697 * Initialize firmware.
699 rt2800_register_write(rt2x00dev
, H2M_BBP_AGENT
, 0);
700 rt2800_register_write(rt2x00dev
, H2M_MAILBOX_CSR
, 0);
701 if (rt2x00_is_usb(rt2x00dev
)) {
702 rt2800_register_write(rt2x00dev
, H2M_INT_SRC
, 0);
703 rt2800_mcu_request(rt2x00dev
, MCU_BOOT_SIGNAL
, 0, 0, 0);
709 EXPORT_SYMBOL_GPL(rt2800_load_firmware
);
711 void rt2800_write_tx_data(struct queue_entry
*entry
,
712 struct txentry_desc
*txdesc
)
714 __le32
*txwi
= rt2800_drv_get_txwi(entry
);
719 * Initialize TX Info descriptor
721 rt2x00_desc_read(txwi
, 0, &word
);
722 rt2x00_set_field32(&word
, TXWI_W0_FRAG
,
723 test_bit(ENTRY_TXD_MORE_FRAG
, &txdesc
->flags
));
724 rt2x00_set_field32(&word
, TXWI_W0_MIMO_PS
,
725 test_bit(ENTRY_TXD_HT_MIMO_PS
, &txdesc
->flags
));
726 rt2x00_set_field32(&word
, TXWI_W0_CF_ACK
, 0);
727 rt2x00_set_field32(&word
, TXWI_W0_TS
,
728 test_bit(ENTRY_TXD_REQ_TIMESTAMP
, &txdesc
->flags
));
729 rt2x00_set_field32(&word
, TXWI_W0_AMPDU
,
730 test_bit(ENTRY_TXD_HT_AMPDU
, &txdesc
->flags
));
731 rt2x00_set_field32(&word
, TXWI_W0_MPDU_DENSITY
,
732 txdesc
->u
.ht
.mpdu_density
);
733 rt2x00_set_field32(&word
, TXWI_W0_TX_OP
, txdesc
->u
.ht
.txop
);
734 rt2x00_set_field32(&word
, TXWI_W0_MCS
, txdesc
->u
.ht
.mcs
);
735 rt2x00_set_field32(&word
, TXWI_W0_BW
,
736 test_bit(ENTRY_TXD_HT_BW_40
, &txdesc
->flags
));
737 rt2x00_set_field32(&word
, TXWI_W0_SHORT_GI
,
738 test_bit(ENTRY_TXD_HT_SHORT_GI
, &txdesc
->flags
));
739 rt2x00_set_field32(&word
, TXWI_W0_STBC
, txdesc
->u
.ht
.stbc
);
740 rt2x00_set_field32(&word
, TXWI_W0_PHYMODE
, txdesc
->rate_mode
);
741 rt2x00_desc_write(txwi
, 0, word
);
743 rt2x00_desc_read(txwi
, 1, &word
);
744 rt2x00_set_field32(&word
, TXWI_W1_ACK
,
745 test_bit(ENTRY_TXD_ACK
, &txdesc
->flags
));
746 rt2x00_set_field32(&word
, TXWI_W1_NSEQ
,
747 test_bit(ENTRY_TXD_GENERATE_SEQ
, &txdesc
->flags
));
748 rt2x00_set_field32(&word
, TXWI_W1_BW_WIN_SIZE
, txdesc
->u
.ht
.ba_size
);
749 rt2x00_set_field32(&word
, TXWI_W1_WIRELESS_CLI_ID
,
750 test_bit(ENTRY_TXD_ENCRYPT
, &txdesc
->flags
) ?
751 txdesc
->key_idx
: txdesc
->u
.ht
.wcid
);
752 rt2x00_set_field32(&word
, TXWI_W1_MPDU_TOTAL_BYTE_COUNT
,
754 rt2x00_set_field32(&word
, TXWI_W1_PACKETID_QUEUE
, entry
->queue
->qid
);
755 rt2x00_set_field32(&word
, TXWI_W1_PACKETID_ENTRY
, (entry
->entry_idx
% 3) + 1);
756 rt2x00_desc_write(txwi
, 1, word
);
759 * Always write 0 to IV/EIV fields (word 2 and 3), hardware will insert
760 * the IV from the IVEIV register when TXD_W3_WIV is set to 0.
761 * When TXD_W3_WIV is set to 1 it will use the IV data
762 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
763 * crypto entry in the registers should be used to encrypt the frame.
765 * Nulify all remaining words as well, we don't know how to program them.
767 for (i
= 2; i
< entry
->queue
->winfo_size
/ sizeof(__le32
); i
++)
768 _rt2x00_desc_write(txwi
, i
, 0);
770 EXPORT_SYMBOL_GPL(rt2800_write_tx_data
);
772 static int rt2800_agc_to_rssi(struct rt2x00_dev
*rt2x00dev
, u32 rxwi_w2
)
774 s8 rssi0
= rt2x00_get_field32(rxwi_w2
, RXWI_W2_RSSI0
);
775 s8 rssi1
= rt2x00_get_field32(rxwi_w2
, RXWI_W2_RSSI1
);
776 s8 rssi2
= rt2x00_get_field32(rxwi_w2
, RXWI_W2_RSSI2
);
782 if (rt2x00dev
->curr_band
== IEEE80211_BAND_2GHZ
) {
783 rt2800_eeprom_read(rt2x00dev
, EEPROM_RSSI_BG
, &eeprom
);
784 offset0
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_BG_OFFSET0
);
785 offset1
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_BG_OFFSET1
);
786 rt2800_eeprom_read(rt2x00dev
, EEPROM_RSSI_BG2
, &eeprom
);
787 offset2
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_BG2_OFFSET2
);
789 rt2800_eeprom_read(rt2x00dev
, EEPROM_RSSI_A
, &eeprom
);
790 offset0
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_A_OFFSET0
);
791 offset1
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_A_OFFSET1
);
792 rt2800_eeprom_read(rt2x00dev
, EEPROM_RSSI_A2
, &eeprom
);
793 offset2
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_A2_OFFSET2
);
797 * Convert the value from the descriptor into the RSSI value
798 * If the value in the descriptor is 0, it is considered invalid
799 * and the default (extremely low) rssi value is assumed
801 rssi0
= (rssi0
) ? (-12 - offset0
- rt2x00dev
->lna_gain
- rssi0
) : -128;
802 rssi1
= (rssi1
) ? (-12 - offset1
- rt2x00dev
->lna_gain
- rssi1
) : -128;
803 rssi2
= (rssi2
) ? (-12 - offset2
- rt2x00dev
->lna_gain
- rssi2
) : -128;
806 * mac80211 only accepts a single RSSI value. Calculating the
807 * average doesn't deliver a fair answer either since -60:-60 would
808 * be considered equally good as -50:-70 while the second is the one
809 * which gives less energy...
811 rssi0
= max(rssi0
, rssi1
);
812 return (int)max(rssi0
, rssi2
);
815 void rt2800_process_rxwi(struct queue_entry
*entry
,
816 struct rxdone_entry_desc
*rxdesc
)
818 __le32
*rxwi
= (__le32
*) entry
->skb
->data
;
821 rt2x00_desc_read(rxwi
, 0, &word
);
823 rxdesc
->cipher
= rt2x00_get_field32(word
, RXWI_W0_UDF
);
824 rxdesc
->size
= rt2x00_get_field32(word
, RXWI_W0_MPDU_TOTAL_BYTE_COUNT
);
826 rt2x00_desc_read(rxwi
, 1, &word
);
828 if (rt2x00_get_field32(word
, RXWI_W1_SHORT_GI
))
829 rxdesc
->flags
|= RX_FLAG_SHORT_GI
;
831 if (rt2x00_get_field32(word
, RXWI_W1_BW
))
832 rxdesc
->flags
|= RX_FLAG_40MHZ
;
835 * Detect RX rate, always use MCS as signal type.
837 rxdesc
->dev_flags
|= RXDONE_SIGNAL_MCS
;
838 rxdesc
->signal
= rt2x00_get_field32(word
, RXWI_W1_MCS
);
839 rxdesc
->rate_mode
= rt2x00_get_field32(word
, RXWI_W1_PHYMODE
);
842 * Mask of 0x8 bit to remove the short preamble flag.
844 if (rxdesc
->rate_mode
== RATE_MODE_CCK
)
845 rxdesc
->signal
&= ~0x8;
847 rt2x00_desc_read(rxwi
, 2, &word
);
850 * Convert descriptor AGC value to RSSI value.
852 rxdesc
->rssi
= rt2800_agc_to_rssi(entry
->queue
->rt2x00dev
, word
);
854 * Remove RXWI descriptor from start of the buffer.
856 skb_pull(entry
->skb
, entry
->queue
->winfo_size
);
858 EXPORT_SYMBOL_GPL(rt2800_process_rxwi
);
860 void rt2800_txdone_entry(struct queue_entry
*entry
, u32 status
, __le32
*txwi
)
862 struct rt2x00_dev
*rt2x00dev
= entry
->queue
->rt2x00dev
;
863 struct skb_frame_desc
*skbdesc
= get_skb_frame_desc(entry
->skb
);
864 struct txdone_entry_desc txdesc
;
870 * Obtain the status about this packet.
873 rt2x00_desc_read(txwi
, 0, &word
);
875 mcs
= rt2x00_get_field32(word
, TXWI_W0_MCS
);
876 ampdu
= rt2x00_get_field32(word
, TXWI_W0_AMPDU
);
878 real_mcs
= rt2x00_get_field32(status
, TX_STA_FIFO_MCS
);
879 aggr
= rt2x00_get_field32(status
, TX_STA_FIFO_TX_AGGRE
);
882 * If a frame was meant to be sent as a single non-aggregated MPDU
883 * but ended up in an aggregate the used tx rate doesn't correlate
884 * with the one specified in the TXWI as the whole aggregate is sent
885 * with the same rate.
887 * For example: two frames are sent to rt2x00, the first one sets
888 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
889 * and requests MCS15. If the hw aggregates both frames into one
890 * AMDPU the tx status for both frames will contain MCS7 although
891 * the frame was sent successfully.
893 * Hence, replace the requested rate with the real tx rate to not
894 * confuse the rate control algortihm by providing clearly wrong
897 if (unlikely(aggr
== 1 && ampdu
== 0 && real_mcs
!= mcs
)) {
898 skbdesc
->tx_rate_idx
= real_mcs
;
902 if (aggr
== 1 || ampdu
== 1)
903 __set_bit(TXDONE_AMPDU
, &txdesc
.flags
);
906 * Ralink has a retry mechanism using a global fallback
907 * table. We setup this fallback table to try the immediate
908 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
909 * always contains the MCS used for the last transmission, be
910 * it successful or not.
912 if (rt2x00_get_field32(status
, TX_STA_FIFO_TX_SUCCESS
)) {
914 * Transmission succeeded. The number of retries is
917 __set_bit(TXDONE_SUCCESS
, &txdesc
.flags
);
918 txdesc
.retry
= ((mcs
> real_mcs
) ? mcs
- real_mcs
: 0);
921 * Transmission failed. The number of retries is
922 * always 7 in this case (for a total number of 8
925 __set_bit(TXDONE_FAILURE
, &txdesc
.flags
);
926 txdesc
.retry
= rt2x00dev
->long_retry
;
930 * the frame was retried at least once
931 * -> hw used fallback rates
934 __set_bit(TXDONE_FALLBACK
, &txdesc
.flags
);
936 rt2x00lib_txdone(entry
, &txdesc
);
938 EXPORT_SYMBOL_GPL(rt2800_txdone_entry
);
940 static unsigned int rt2800_hw_beacon_base(struct rt2x00_dev
*rt2x00dev
,
943 return HW_BEACON_BASE(index
);
946 static inline u8
rt2800_get_beacon_offset(struct rt2x00_dev
*rt2x00dev
,
949 return BEACON_BASE_TO_OFFSET(rt2800_hw_beacon_base(rt2x00dev
, index
));
952 void rt2800_write_beacon(struct queue_entry
*entry
, struct txentry_desc
*txdesc
)
954 struct rt2x00_dev
*rt2x00dev
= entry
->queue
->rt2x00dev
;
955 struct skb_frame_desc
*skbdesc
= get_skb_frame_desc(entry
->skb
);
956 unsigned int beacon_base
;
957 unsigned int padding_len
;
959 const int txwi_desc_size
= entry
->queue
->winfo_size
;
962 * Disable beaconing while we are reloading the beacon data,
963 * otherwise we might be sending out invalid data.
965 rt2800_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
967 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_GEN
, 0);
968 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
971 * Add space for the TXWI in front of the skb.
973 memset(skb_push(entry
->skb
, txwi_desc_size
), 0, txwi_desc_size
);
976 * Register descriptor details in skb frame descriptor.
978 skbdesc
->flags
|= SKBDESC_DESC_IN_SKB
;
979 skbdesc
->desc
= entry
->skb
->data
;
980 skbdesc
->desc_len
= txwi_desc_size
;
983 * Add the TXWI for the beacon to the skb.
985 rt2800_write_tx_data(entry
, txdesc
);
988 * Dump beacon to userspace through debugfs.
990 rt2x00debug_dump_frame(rt2x00dev
, DUMP_FRAME_BEACON
, entry
->skb
);
993 * Write entire beacon with TXWI and padding to register.
995 padding_len
= roundup(entry
->skb
->len
, 4) - entry
->skb
->len
;
996 if (padding_len
&& skb_pad(entry
->skb
, padding_len
)) {
997 rt2x00_err(rt2x00dev
, "Failure padding beacon, aborting\n");
998 /* skb freed by skb_pad() on failure */
1000 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, orig_reg
);
1004 beacon_base
= rt2800_hw_beacon_base(rt2x00dev
, entry
->entry_idx
);
1006 rt2800_register_multiwrite(rt2x00dev
, beacon_base
, entry
->skb
->data
,
1007 entry
->skb
->len
+ padding_len
);
1010 * Enable beaconing again.
1012 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_GEN
, 1);
1013 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
1016 * Clean up beacon skb.
1018 dev_kfree_skb_any(entry
->skb
);
1021 EXPORT_SYMBOL_GPL(rt2800_write_beacon
);
1023 static inline void rt2800_clear_beacon_register(struct rt2x00_dev
*rt2x00dev
,
1027 const int txwi_desc_size
= rt2x00dev
->bcn
->winfo_size
;
1028 unsigned int beacon_base
;
1030 beacon_base
= rt2800_hw_beacon_base(rt2x00dev
, index
);
1033 * For the Beacon base registers we only need to clear
1034 * the whole TXWI which (when set to 0) will invalidate
1035 * the entire beacon.
1037 for (i
= 0; i
< txwi_desc_size
; i
+= sizeof(__le32
))
1038 rt2800_register_write(rt2x00dev
, beacon_base
+ i
, 0);
1041 void rt2800_clear_beacon(struct queue_entry
*entry
)
1043 struct rt2x00_dev
*rt2x00dev
= entry
->queue
->rt2x00dev
;
1047 * Disable beaconing while we are reloading the beacon data,
1048 * otherwise we might be sending out invalid data.
1050 rt2800_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
1051 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_GEN
, 0);
1052 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
1057 rt2800_clear_beacon_register(rt2x00dev
, entry
->entry_idx
);
1060 * Enabled beaconing again.
1062 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_GEN
, 1);
1063 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
1065 EXPORT_SYMBOL_GPL(rt2800_clear_beacon
);
1067 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1068 const struct rt2x00debug rt2800_rt2x00debug
= {
1069 .owner
= THIS_MODULE
,
1071 .read
= rt2800_register_read
,
1072 .write
= rt2800_register_write
,
1073 .flags
= RT2X00DEBUGFS_OFFSET
,
1074 .word_base
= CSR_REG_BASE
,
1075 .word_size
= sizeof(u32
),
1076 .word_count
= CSR_REG_SIZE
/ sizeof(u32
),
1079 /* NOTE: The local EEPROM access functions can't
1080 * be used here, use the generic versions instead.
1082 .read
= rt2x00_eeprom_read
,
1083 .write
= rt2x00_eeprom_write
,
1084 .word_base
= EEPROM_BASE
,
1085 .word_size
= sizeof(u16
),
1086 .word_count
= EEPROM_SIZE
/ sizeof(u16
),
1089 .read
= rt2800_bbp_read
,
1090 .write
= rt2800_bbp_write
,
1091 .word_base
= BBP_BASE
,
1092 .word_size
= sizeof(u8
),
1093 .word_count
= BBP_SIZE
/ sizeof(u8
),
1096 .read
= rt2x00_rf_read
,
1097 .write
= rt2800_rf_write
,
1098 .word_base
= RF_BASE
,
1099 .word_size
= sizeof(u32
),
1100 .word_count
= RF_SIZE
/ sizeof(u32
),
1103 .read
= rt2800_rfcsr_read
,
1104 .write
= rt2800_rfcsr_write
,
1105 .word_base
= RFCSR_BASE
,
1106 .word_size
= sizeof(u8
),
1107 .word_count
= RFCSR_SIZE
/ sizeof(u8
),
1110 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug
);
1111 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1113 int rt2800_rfkill_poll(struct rt2x00_dev
*rt2x00dev
)
1117 if (rt2x00_rt(rt2x00dev
, RT3290
)) {
1118 rt2800_register_read(rt2x00dev
, WLAN_FUN_CTRL
, ®
);
1119 return rt2x00_get_field32(reg
, WLAN_GPIO_IN_BIT0
);
1121 rt2800_register_read(rt2x00dev
, GPIO_CTRL
, ®
);
1122 return rt2x00_get_field32(reg
, GPIO_CTRL_VAL2
);
1125 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll
);
1127 #ifdef CONFIG_RT2X00_LIB_LEDS
1128 static void rt2800_brightness_set(struct led_classdev
*led_cdev
,
1129 enum led_brightness brightness
)
1131 struct rt2x00_led
*led
=
1132 container_of(led_cdev
, struct rt2x00_led
, led_dev
);
1133 unsigned int enabled
= brightness
!= LED_OFF
;
1134 unsigned int bg_mode
=
1135 (enabled
&& led
->rt2x00dev
->curr_band
== IEEE80211_BAND_2GHZ
);
1136 unsigned int polarity
=
1137 rt2x00_get_field16(led
->rt2x00dev
->led_mcu_reg
,
1138 EEPROM_FREQ_LED_POLARITY
);
1139 unsigned int ledmode
=
1140 rt2x00_get_field16(led
->rt2x00dev
->led_mcu_reg
,
1141 EEPROM_FREQ_LED_MODE
);
1144 /* Check for SoC (SOC devices don't support MCU requests) */
1145 if (rt2x00_is_soc(led
->rt2x00dev
)) {
1146 rt2800_register_read(led
->rt2x00dev
, LED_CFG
, ®
);
1148 /* Set LED Polarity */
1149 rt2x00_set_field32(®
, LED_CFG_LED_POLAR
, polarity
);
1152 if (led
->type
== LED_TYPE_RADIO
) {
1153 rt2x00_set_field32(®
, LED_CFG_G_LED_MODE
,
1155 } else if (led
->type
== LED_TYPE_ASSOC
) {
1156 rt2x00_set_field32(®
, LED_CFG_Y_LED_MODE
,
1158 } else if (led
->type
== LED_TYPE_QUALITY
) {
1159 rt2x00_set_field32(®
, LED_CFG_R_LED_MODE
,
1163 rt2800_register_write(led
->rt2x00dev
, LED_CFG
, reg
);
1166 if (led
->type
== LED_TYPE_RADIO
) {
1167 rt2800_mcu_request(led
->rt2x00dev
, MCU_LED
, 0xff, ledmode
,
1168 enabled
? 0x20 : 0);
1169 } else if (led
->type
== LED_TYPE_ASSOC
) {
1170 rt2800_mcu_request(led
->rt2x00dev
, MCU_LED
, 0xff, ledmode
,
1171 enabled
? (bg_mode
? 0x60 : 0xa0) : 0x20);
1172 } else if (led
->type
== LED_TYPE_QUALITY
) {
1174 * The brightness is divided into 6 levels (0 - 5),
1175 * The specs tell us the following levels:
1176 * 0, 1 ,3, 7, 15, 31
1177 * to determine the level in a simple way we can simply
1178 * work with bitshifting:
1181 rt2800_mcu_request(led
->rt2x00dev
, MCU_LED_STRENGTH
, 0xff,
1182 (1 << brightness
/ (LED_FULL
/ 6)) - 1,
1188 static void rt2800_init_led(struct rt2x00_dev
*rt2x00dev
,
1189 struct rt2x00_led
*led
, enum led_type type
)
1191 led
->rt2x00dev
= rt2x00dev
;
1193 led
->led_dev
.brightness_set
= rt2800_brightness_set
;
1194 led
->flags
= LED_INITIALIZED
;
1196 #endif /* CONFIG_RT2X00_LIB_LEDS */
1199 * Configuration handlers.
1201 static void rt2800_config_wcid(struct rt2x00_dev
*rt2x00dev
,
1205 struct mac_wcid_entry wcid_entry
;
1208 offset
= MAC_WCID_ENTRY(wcid
);
1210 memset(&wcid_entry
, 0xff, sizeof(wcid_entry
));
1212 memcpy(wcid_entry
.mac
, address
, ETH_ALEN
);
1214 rt2800_register_multiwrite(rt2x00dev
, offset
,
1215 &wcid_entry
, sizeof(wcid_entry
));
1218 static void rt2800_delete_wcid_attr(struct rt2x00_dev
*rt2x00dev
, int wcid
)
1221 offset
= MAC_WCID_ATTR_ENTRY(wcid
);
1222 rt2800_register_write(rt2x00dev
, offset
, 0);
1225 static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev
*rt2x00dev
,
1226 int wcid
, u32 bssidx
)
1228 u32 offset
= MAC_WCID_ATTR_ENTRY(wcid
);
1232 * The BSS Idx numbers is split in a main value of 3 bits,
1233 * and a extended field for adding one additional bit to the value.
1235 rt2800_register_read(rt2x00dev
, offset
, ®
);
1236 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_BSS_IDX
, (bssidx
& 0x7));
1237 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT
,
1238 (bssidx
& 0x8) >> 3);
1239 rt2800_register_write(rt2x00dev
, offset
, reg
);
1242 static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev
*rt2x00dev
,
1243 struct rt2x00lib_crypto
*crypto
,
1244 struct ieee80211_key_conf
*key
)
1246 struct mac_iveiv_entry iveiv_entry
;
1250 offset
= MAC_WCID_ATTR_ENTRY(key
->hw_key_idx
);
1252 if (crypto
->cmd
== SET_KEY
) {
1253 rt2800_register_read(rt2x00dev
, offset
, ®
);
1254 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_KEYTAB
,
1255 !!(key
->flags
& IEEE80211_KEY_FLAG_PAIRWISE
));
1257 * Both the cipher as the BSS Idx numbers are split in a main
1258 * value of 3 bits, and a extended field for adding one additional
1261 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_CIPHER
,
1262 (crypto
->cipher
& 0x7));
1263 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_CIPHER_EXT
,
1264 (crypto
->cipher
& 0x8) >> 3);
1265 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_RX_WIUDF
, crypto
->cipher
);
1266 rt2800_register_write(rt2x00dev
, offset
, reg
);
1268 /* Delete the cipher without touching the bssidx */
1269 rt2800_register_read(rt2x00dev
, offset
, ®
);
1270 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_KEYTAB
, 0);
1271 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_CIPHER
, 0);
1272 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_CIPHER_EXT
, 0);
1273 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_RX_WIUDF
, 0);
1274 rt2800_register_write(rt2x00dev
, offset
, reg
);
1277 offset
= MAC_IVEIV_ENTRY(key
->hw_key_idx
);
1279 memset(&iveiv_entry
, 0, sizeof(iveiv_entry
));
1280 if ((crypto
->cipher
== CIPHER_TKIP
) ||
1281 (crypto
->cipher
== CIPHER_TKIP_NO_MIC
) ||
1282 (crypto
->cipher
== CIPHER_AES
))
1283 iveiv_entry
.iv
[3] |= 0x20;
1284 iveiv_entry
.iv
[3] |= key
->keyidx
<< 6;
1285 rt2800_register_multiwrite(rt2x00dev
, offset
,
1286 &iveiv_entry
, sizeof(iveiv_entry
));
1289 int rt2800_config_shared_key(struct rt2x00_dev
*rt2x00dev
,
1290 struct rt2x00lib_crypto
*crypto
,
1291 struct ieee80211_key_conf
*key
)
1293 struct hw_key_entry key_entry
;
1294 struct rt2x00_field32 field
;
1298 if (crypto
->cmd
== SET_KEY
) {
1299 key
->hw_key_idx
= (4 * crypto
->bssidx
) + key
->keyidx
;
1301 memcpy(key_entry
.key
, crypto
->key
,
1302 sizeof(key_entry
.key
));
1303 memcpy(key_entry
.tx_mic
, crypto
->tx_mic
,
1304 sizeof(key_entry
.tx_mic
));
1305 memcpy(key_entry
.rx_mic
, crypto
->rx_mic
,
1306 sizeof(key_entry
.rx_mic
));
1308 offset
= SHARED_KEY_ENTRY(key
->hw_key_idx
);
1309 rt2800_register_multiwrite(rt2x00dev
, offset
,
1310 &key_entry
, sizeof(key_entry
));
1314 * The cipher types are stored over multiple registers
1315 * starting with SHARED_KEY_MODE_BASE each word will have
1316 * 32 bits and contains the cipher types for 2 bssidx each.
1317 * Using the correct defines correctly will cause overhead,
1318 * so just calculate the correct offset.
1320 field
.bit_offset
= 4 * (key
->hw_key_idx
% 8);
1321 field
.bit_mask
= 0x7 << field
.bit_offset
;
1323 offset
= SHARED_KEY_MODE_ENTRY(key
->hw_key_idx
/ 8);
1325 rt2800_register_read(rt2x00dev
, offset
, ®
);
1326 rt2x00_set_field32(®
, field
,
1327 (crypto
->cmd
== SET_KEY
) * crypto
->cipher
);
1328 rt2800_register_write(rt2x00dev
, offset
, reg
);
1331 * Update WCID information
1333 rt2800_config_wcid(rt2x00dev
, crypto
->address
, key
->hw_key_idx
);
1334 rt2800_config_wcid_attr_bssidx(rt2x00dev
, key
->hw_key_idx
,
1336 rt2800_config_wcid_attr_cipher(rt2x00dev
, crypto
, key
);
1340 EXPORT_SYMBOL_GPL(rt2800_config_shared_key
);
1342 static inline int rt2800_find_wcid(struct rt2x00_dev
*rt2x00dev
)
1344 struct mac_wcid_entry wcid_entry
;
1349 * Search for the first free WCID entry and return the corresponding
1352 * Make sure the WCID starts _after_ the last possible shared key
1355 * Since parts of the pairwise key table might be shared with
1356 * the beacon frame buffers 6 & 7 we should only write into the
1357 * first 222 entries.
1359 for (idx
= 33; idx
<= 222; idx
++) {
1360 offset
= MAC_WCID_ENTRY(idx
);
1361 rt2800_register_multiread(rt2x00dev
, offset
, &wcid_entry
,
1362 sizeof(wcid_entry
));
1363 if (is_broadcast_ether_addr(wcid_entry
.mac
))
1368 * Use -1 to indicate that we don't have any more space in the WCID
1374 int rt2800_config_pairwise_key(struct rt2x00_dev
*rt2x00dev
,
1375 struct rt2x00lib_crypto
*crypto
,
1376 struct ieee80211_key_conf
*key
)
1378 struct hw_key_entry key_entry
;
1381 if (crypto
->cmd
== SET_KEY
) {
1383 * Allow key configuration only for STAs that are
1386 if (crypto
->wcid
< 0)
1388 key
->hw_key_idx
= crypto
->wcid
;
1390 memcpy(key_entry
.key
, crypto
->key
,
1391 sizeof(key_entry
.key
));
1392 memcpy(key_entry
.tx_mic
, crypto
->tx_mic
,
1393 sizeof(key_entry
.tx_mic
));
1394 memcpy(key_entry
.rx_mic
, crypto
->rx_mic
,
1395 sizeof(key_entry
.rx_mic
));
1397 offset
= PAIRWISE_KEY_ENTRY(key
->hw_key_idx
);
1398 rt2800_register_multiwrite(rt2x00dev
, offset
,
1399 &key_entry
, sizeof(key_entry
));
1403 * Update WCID information
1405 rt2800_config_wcid_attr_cipher(rt2x00dev
, crypto
, key
);
1409 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key
);
1411 int rt2800_sta_add(struct rt2x00_dev
*rt2x00dev
, struct ieee80211_vif
*vif
,
1412 struct ieee80211_sta
*sta
)
1415 struct rt2x00_sta
*sta_priv
= sta_to_rt2x00_sta(sta
);
1418 * Find next free WCID.
1420 wcid
= rt2800_find_wcid(rt2x00dev
);
1423 * Store selected wcid even if it is invalid so that we can
1424 * later decide if the STA is uploaded into the hw.
1426 sta_priv
->wcid
= wcid
;
1429 * No space left in the device, however, we can still communicate
1430 * with the STA -> No error.
1436 * Clean up WCID attributes and write STA address to the device.
1438 rt2800_delete_wcid_attr(rt2x00dev
, wcid
);
1439 rt2800_config_wcid(rt2x00dev
, sta
->addr
, wcid
);
1440 rt2800_config_wcid_attr_bssidx(rt2x00dev
, wcid
,
1441 rt2x00lib_get_bssidx(rt2x00dev
, vif
));
1444 EXPORT_SYMBOL_GPL(rt2800_sta_add
);
1446 int rt2800_sta_remove(struct rt2x00_dev
*rt2x00dev
, int wcid
)
1449 * Remove WCID entry, no need to clean the attributes as they will
1450 * get renewed when the WCID is reused.
1452 rt2800_config_wcid(rt2x00dev
, NULL
, wcid
);
1456 EXPORT_SYMBOL_GPL(rt2800_sta_remove
);
1458 void rt2800_config_filter(struct rt2x00_dev
*rt2x00dev
,
1459 const unsigned int filter_flags
)
1464 * Start configuration steps.
1465 * Note that the version error will always be dropped
1466 * and broadcast frames will always be accepted since
1467 * there is no filter for it at this time.
1469 rt2800_register_read(rt2x00dev
, RX_FILTER_CFG
, ®
);
1470 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CRC_ERROR
,
1471 !(filter_flags
& FIF_FCSFAIL
));
1472 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_PHY_ERROR
,
1473 !(filter_flags
& FIF_PLCPFAIL
));
1474 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_NOT_TO_ME
,
1475 !(filter_flags
& FIF_PROMISC_IN_BSS
));
1476 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_NOT_MY_BSSD
, 0);
1477 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_VER_ERROR
, 1);
1478 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_MULTICAST
,
1479 !(filter_flags
& FIF_ALLMULTI
));
1480 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_BROADCAST
, 0);
1481 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_DUPLICATE
, 1);
1482 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CF_END_ACK
,
1483 !(filter_flags
& FIF_CONTROL
));
1484 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CF_END
,
1485 !(filter_flags
& FIF_CONTROL
));
1486 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_ACK
,
1487 !(filter_flags
& FIF_CONTROL
));
1488 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CTS
,
1489 !(filter_flags
& FIF_CONTROL
));
1490 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_RTS
,
1491 !(filter_flags
& FIF_CONTROL
));
1492 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_PSPOLL
,
1493 !(filter_flags
& FIF_PSPOLL
));
1494 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_BA
, 0);
1495 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_BAR
,
1496 !(filter_flags
& FIF_CONTROL
));
1497 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CNTL
,
1498 !(filter_flags
& FIF_CONTROL
));
1499 rt2800_register_write(rt2x00dev
, RX_FILTER_CFG
, reg
);
1501 EXPORT_SYMBOL_GPL(rt2800_config_filter
);
1503 void rt2800_config_intf(struct rt2x00_dev
*rt2x00dev
, struct rt2x00_intf
*intf
,
1504 struct rt2x00intf_conf
*conf
, const unsigned int flags
)
1507 bool update_bssid
= false;
1509 if (flags
& CONFIG_UPDATE_TYPE
) {
1511 * Enable synchronisation.
1513 rt2800_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
1514 rt2x00_set_field32(®
, BCN_TIME_CFG_TSF_SYNC
, conf
->sync
);
1515 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
1517 if (conf
->sync
== TSF_SYNC_AP_NONE
) {
1519 * Tune beacon queue transmit parameters for AP mode
1521 rt2800_register_read(rt2x00dev
, TBTT_SYNC_CFG
, ®
);
1522 rt2x00_set_field32(®
, TBTT_SYNC_CFG_BCN_CWMIN
, 0);
1523 rt2x00_set_field32(®
, TBTT_SYNC_CFG_BCN_AIFSN
, 1);
1524 rt2x00_set_field32(®
, TBTT_SYNC_CFG_BCN_EXP_WIN
, 32);
1525 rt2x00_set_field32(®
, TBTT_SYNC_CFG_TBTT_ADJUST
, 0);
1526 rt2800_register_write(rt2x00dev
, TBTT_SYNC_CFG
, reg
);
1528 rt2800_register_read(rt2x00dev
, TBTT_SYNC_CFG
, ®
);
1529 rt2x00_set_field32(®
, TBTT_SYNC_CFG_BCN_CWMIN
, 4);
1530 rt2x00_set_field32(®
, TBTT_SYNC_CFG_BCN_AIFSN
, 2);
1531 rt2x00_set_field32(®
, TBTT_SYNC_CFG_BCN_EXP_WIN
, 32);
1532 rt2x00_set_field32(®
, TBTT_SYNC_CFG_TBTT_ADJUST
, 16);
1533 rt2800_register_write(rt2x00dev
, TBTT_SYNC_CFG
, reg
);
1537 if (flags
& CONFIG_UPDATE_MAC
) {
1538 if (flags
& CONFIG_UPDATE_TYPE
&&
1539 conf
->sync
== TSF_SYNC_AP_NONE
) {
1541 * The BSSID register has to be set to our own mac
1542 * address in AP mode.
1544 memcpy(conf
->bssid
, conf
->mac
, sizeof(conf
->mac
));
1545 update_bssid
= true;
1548 if (!is_zero_ether_addr((const u8
*)conf
->mac
)) {
1549 reg
= le32_to_cpu(conf
->mac
[1]);
1550 rt2x00_set_field32(®
, MAC_ADDR_DW1_UNICAST_TO_ME_MASK
, 0xff);
1551 conf
->mac
[1] = cpu_to_le32(reg
);
1554 rt2800_register_multiwrite(rt2x00dev
, MAC_ADDR_DW0
,
1555 conf
->mac
, sizeof(conf
->mac
));
1558 if ((flags
& CONFIG_UPDATE_BSSID
) || update_bssid
) {
1559 if (!is_zero_ether_addr((const u8
*)conf
->bssid
)) {
1560 reg
= le32_to_cpu(conf
->bssid
[1]);
1561 rt2x00_set_field32(®
, MAC_BSSID_DW1_BSS_ID_MASK
, 3);
1562 rt2x00_set_field32(®
, MAC_BSSID_DW1_BSS_BCN_NUM
, 7);
1563 conf
->bssid
[1] = cpu_to_le32(reg
);
1566 rt2800_register_multiwrite(rt2x00dev
, MAC_BSSID_DW0
,
1567 conf
->bssid
, sizeof(conf
->bssid
));
1570 EXPORT_SYMBOL_GPL(rt2800_config_intf
);
1572 static void rt2800_config_ht_opmode(struct rt2x00_dev
*rt2x00dev
,
1573 struct rt2x00lib_erp
*erp
)
1575 bool any_sta_nongf
= !!(erp
->ht_opmode
&
1576 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT
);
1577 u8 protection
= erp
->ht_opmode
& IEEE80211_HT_OP_MODE_PROTECTION
;
1578 u8 mm20_mode
, mm40_mode
, gf20_mode
, gf40_mode
;
1579 u16 mm20_rate
, mm40_rate
, gf20_rate
, gf40_rate
;
1582 /* default protection rate for HT20: OFDM 24M */
1583 mm20_rate
= gf20_rate
= 0x4004;
1585 /* default protection rate for HT40: duplicate OFDM 24M */
1586 mm40_rate
= gf40_rate
= 0x4084;
1588 switch (protection
) {
1589 case IEEE80211_HT_OP_MODE_PROTECTION_NONE
:
1591 * All STAs in this BSS are HT20/40 but there might be
1592 * STAs not supporting greenfield mode.
1593 * => Disable protection for HT transmissions.
1595 mm20_mode
= mm40_mode
= gf20_mode
= gf40_mode
= 0;
1598 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ
:
1600 * All STAs in this BSS are HT20 or HT20/40 but there
1601 * might be STAs not supporting greenfield mode.
1602 * => Protect all HT40 transmissions.
1604 mm20_mode
= gf20_mode
= 0;
1605 mm40_mode
= gf40_mode
= 2;
1608 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER
:
1610 * Nonmember protection:
1611 * According to 802.11n we _should_ protect all
1612 * HT transmissions (but we don't have to).
1614 * But if cts_protection is enabled we _shall_ protect
1615 * all HT transmissions using a CCK rate.
1617 * And if any station is non GF we _shall_ protect
1620 * We decide to protect everything
1621 * -> fall through to mixed mode.
1623 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED
:
1625 * Legacy STAs are present
1626 * => Protect all HT transmissions.
1628 mm20_mode
= mm40_mode
= gf20_mode
= gf40_mode
= 2;
1631 * If erp protection is needed we have to protect HT
1632 * transmissions with CCK 11M long preamble.
1634 if (erp
->cts_protection
) {
1635 /* don't duplicate RTS/CTS in CCK mode */
1636 mm20_rate
= mm40_rate
= 0x0003;
1637 gf20_rate
= gf40_rate
= 0x0003;
1642 /* check for STAs not supporting greenfield mode */
1644 gf20_mode
= gf40_mode
= 2;
1646 /* Update HT protection config */
1647 rt2800_register_read(rt2x00dev
, MM20_PROT_CFG
, ®
);
1648 rt2x00_set_field32(®
, MM20_PROT_CFG_PROTECT_RATE
, mm20_rate
);
1649 rt2x00_set_field32(®
, MM20_PROT_CFG_PROTECT_CTRL
, mm20_mode
);
1650 rt2800_register_write(rt2x00dev
, MM20_PROT_CFG
, reg
);
1652 rt2800_register_read(rt2x00dev
, MM40_PROT_CFG
, ®
);
1653 rt2x00_set_field32(®
, MM40_PROT_CFG_PROTECT_RATE
, mm40_rate
);
1654 rt2x00_set_field32(®
, MM40_PROT_CFG_PROTECT_CTRL
, mm40_mode
);
1655 rt2800_register_write(rt2x00dev
, MM40_PROT_CFG
, reg
);
1657 rt2800_register_read(rt2x00dev
, GF20_PROT_CFG
, ®
);
1658 rt2x00_set_field32(®
, GF20_PROT_CFG_PROTECT_RATE
, gf20_rate
);
1659 rt2x00_set_field32(®
, GF20_PROT_CFG_PROTECT_CTRL
, gf20_mode
);
1660 rt2800_register_write(rt2x00dev
, GF20_PROT_CFG
, reg
);
1662 rt2800_register_read(rt2x00dev
, GF40_PROT_CFG
, ®
);
1663 rt2x00_set_field32(®
, GF40_PROT_CFG_PROTECT_RATE
, gf40_rate
);
1664 rt2x00_set_field32(®
, GF40_PROT_CFG_PROTECT_CTRL
, gf40_mode
);
1665 rt2800_register_write(rt2x00dev
, GF40_PROT_CFG
, reg
);
1668 void rt2800_config_erp(struct rt2x00_dev
*rt2x00dev
, struct rt2x00lib_erp
*erp
,
1673 if (changed
& BSS_CHANGED_ERP_PREAMBLE
) {
1674 rt2800_register_read(rt2x00dev
, AUTO_RSP_CFG
, ®
);
1675 rt2x00_set_field32(®
, AUTO_RSP_CFG_BAC_ACK_POLICY
,
1676 !!erp
->short_preamble
);
1677 rt2x00_set_field32(®
, AUTO_RSP_CFG_AR_PREAMBLE
,
1678 !!erp
->short_preamble
);
1679 rt2800_register_write(rt2x00dev
, AUTO_RSP_CFG
, reg
);
1682 if (changed
& BSS_CHANGED_ERP_CTS_PROT
) {
1683 rt2800_register_read(rt2x00dev
, OFDM_PROT_CFG
, ®
);
1684 rt2x00_set_field32(®
, OFDM_PROT_CFG_PROTECT_CTRL
,
1685 erp
->cts_protection
? 2 : 0);
1686 rt2800_register_write(rt2x00dev
, OFDM_PROT_CFG
, reg
);
1689 if (changed
& BSS_CHANGED_BASIC_RATES
) {
1690 rt2800_register_write(rt2x00dev
, LEGACY_BASIC_RATE
,
1692 rt2800_register_write(rt2x00dev
, HT_BASIC_RATE
, 0x00008003);
1695 if (changed
& BSS_CHANGED_ERP_SLOT
) {
1696 rt2800_register_read(rt2x00dev
, BKOFF_SLOT_CFG
, ®
);
1697 rt2x00_set_field32(®
, BKOFF_SLOT_CFG_SLOT_TIME
,
1699 rt2800_register_write(rt2x00dev
, BKOFF_SLOT_CFG
, reg
);
1701 rt2800_register_read(rt2x00dev
, XIFS_TIME_CFG
, ®
);
1702 rt2x00_set_field32(®
, XIFS_TIME_CFG_EIFS
, erp
->eifs
);
1703 rt2800_register_write(rt2x00dev
, XIFS_TIME_CFG
, reg
);
1706 if (changed
& BSS_CHANGED_BEACON_INT
) {
1707 rt2800_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
1708 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_INTERVAL
,
1709 erp
->beacon_int
* 16);
1710 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
1713 if (changed
& BSS_CHANGED_HT
)
1714 rt2800_config_ht_opmode(rt2x00dev
, erp
);
1716 EXPORT_SYMBOL_GPL(rt2800_config_erp
);
1718 static void rt2800_config_3572bt_ant(struct rt2x00_dev
*rt2x00dev
)
1722 u8 led_ctrl
, led_g_mode
, led_r_mode
;
1724 rt2800_register_read(rt2x00dev
, GPIO_SWITCH
, ®
);
1725 if (rt2x00dev
->curr_band
== IEEE80211_BAND_5GHZ
) {
1726 rt2x00_set_field32(®
, GPIO_SWITCH_0
, 1);
1727 rt2x00_set_field32(®
, GPIO_SWITCH_1
, 1);
1729 rt2x00_set_field32(®
, GPIO_SWITCH_0
, 0);
1730 rt2x00_set_field32(®
, GPIO_SWITCH_1
, 0);
1732 rt2800_register_write(rt2x00dev
, GPIO_SWITCH
, reg
);
1734 rt2800_register_read(rt2x00dev
, LED_CFG
, ®
);
1735 led_g_mode
= rt2x00_get_field32(reg
, LED_CFG_LED_POLAR
) ? 3 : 0;
1736 led_r_mode
= rt2x00_get_field32(reg
, LED_CFG_LED_POLAR
) ? 0 : 3;
1737 if (led_g_mode
!= rt2x00_get_field32(reg
, LED_CFG_G_LED_MODE
) ||
1738 led_r_mode
!= rt2x00_get_field32(reg
, LED_CFG_R_LED_MODE
)) {
1739 rt2800_eeprom_read(rt2x00dev
, EEPROM_FREQ
, &eeprom
);
1740 led_ctrl
= rt2x00_get_field16(eeprom
, EEPROM_FREQ_LED_MODE
);
1741 if (led_ctrl
== 0 || led_ctrl
> 0x40) {
1742 rt2x00_set_field32(®
, LED_CFG_G_LED_MODE
, led_g_mode
);
1743 rt2x00_set_field32(®
, LED_CFG_R_LED_MODE
, led_r_mode
);
1744 rt2800_register_write(rt2x00dev
, LED_CFG
, reg
);
1746 rt2800_mcu_request(rt2x00dev
, MCU_BAND_SELECT
, 0xff,
1747 (led_g_mode
<< 2) | led_r_mode
, 1);
1752 static void rt2800_set_ant_diversity(struct rt2x00_dev
*rt2x00dev
,
1756 u8 eesk_pin
= (ant
== ANTENNA_A
) ? 1 : 0;
1757 u8 gpio_bit3
= (ant
== ANTENNA_A
) ? 0 : 1;
1759 if (rt2x00_is_pci(rt2x00dev
)) {
1760 rt2800_register_read(rt2x00dev
, E2PROM_CSR
, ®
);
1761 rt2x00_set_field32(®
, E2PROM_CSR_DATA_CLOCK
, eesk_pin
);
1762 rt2800_register_write(rt2x00dev
, E2PROM_CSR
, reg
);
1763 } else if (rt2x00_is_usb(rt2x00dev
))
1764 rt2800_mcu_request(rt2x00dev
, MCU_ANT_SELECT
, 0xff,
1767 rt2800_register_read(rt2x00dev
, GPIO_CTRL
, ®
);
1768 rt2x00_set_field32(®
, GPIO_CTRL_DIR3
, 0);
1769 rt2x00_set_field32(®
, GPIO_CTRL_VAL3
, gpio_bit3
);
1770 rt2800_register_write(rt2x00dev
, GPIO_CTRL
, reg
);
1773 void rt2800_config_ant(struct rt2x00_dev
*rt2x00dev
, struct antenna_setup
*ant
)
1779 rt2800_bbp_read(rt2x00dev
, 1, &r1
);
1780 rt2800_bbp_read(rt2x00dev
, 3, &r3
);
1782 if (rt2x00_rt(rt2x00dev
, RT3572
) &&
1783 rt2x00_has_cap_bt_coexist(rt2x00dev
))
1784 rt2800_config_3572bt_ant(rt2x00dev
);
1787 * Configure the TX antenna.
1789 switch (ant
->tx_chain_num
) {
1791 rt2x00_set_field8(&r1
, BBP1_TX_ANTENNA
, 0);
1794 if (rt2x00_rt(rt2x00dev
, RT3572
) &&
1795 rt2x00_has_cap_bt_coexist(rt2x00dev
))
1796 rt2x00_set_field8(&r1
, BBP1_TX_ANTENNA
, 1);
1798 rt2x00_set_field8(&r1
, BBP1_TX_ANTENNA
, 2);
1801 rt2x00_set_field8(&r1
, BBP1_TX_ANTENNA
, 2);
1806 * Configure the RX antenna.
1808 switch (ant
->rx_chain_num
) {
1810 if (rt2x00_rt(rt2x00dev
, RT3070
) ||
1811 rt2x00_rt(rt2x00dev
, RT3090
) ||
1812 rt2x00_rt(rt2x00dev
, RT3352
) ||
1813 rt2x00_rt(rt2x00dev
, RT3390
)) {
1814 rt2800_eeprom_read(rt2x00dev
,
1815 EEPROM_NIC_CONF1
, &eeprom
);
1816 if (rt2x00_get_field16(eeprom
,
1817 EEPROM_NIC_CONF1_ANT_DIVERSITY
))
1818 rt2800_set_ant_diversity(rt2x00dev
,
1819 rt2x00dev
->default_ant
.rx
);
1821 rt2x00_set_field8(&r3
, BBP3_RX_ANTENNA
, 0);
1824 if (rt2x00_rt(rt2x00dev
, RT3572
) &&
1825 rt2x00_has_cap_bt_coexist(rt2x00dev
)) {
1826 rt2x00_set_field8(&r3
, BBP3_RX_ADC
, 1);
1827 rt2x00_set_field8(&r3
, BBP3_RX_ANTENNA
,
1828 rt2x00dev
->curr_band
== IEEE80211_BAND_5GHZ
);
1829 rt2800_set_ant_diversity(rt2x00dev
, ANTENNA_B
);
1831 rt2x00_set_field8(&r3
, BBP3_RX_ANTENNA
, 1);
1835 rt2x00_set_field8(&r3
, BBP3_RX_ANTENNA
, 2);
1839 rt2800_bbp_write(rt2x00dev
, 3, r3
);
1840 rt2800_bbp_write(rt2x00dev
, 1, r1
);
1842 if (rt2x00_rt(rt2x00dev
, RT3593
)) {
1843 if (ant
->rx_chain_num
== 1)
1844 rt2800_bbp_write(rt2x00dev
, 86, 0x00);
1846 rt2800_bbp_write(rt2x00dev
, 86, 0x46);
1849 EXPORT_SYMBOL_GPL(rt2800_config_ant
);
1851 static void rt2800_config_lna_gain(struct rt2x00_dev
*rt2x00dev
,
1852 struct rt2x00lib_conf
*libconf
)
1857 if (libconf
->rf
.channel
<= 14) {
1858 rt2800_eeprom_read(rt2x00dev
, EEPROM_LNA
, &eeprom
);
1859 lna_gain
= rt2x00_get_field16(eeprom
, EEPROM_LNA_BG
);
1860 } else if (libconf
->rf
.channel
<= 64) {
1861 rt2800_eeprom_read(rt2x00dev
, EEPROM_LNA
, &eeprom
);
1862 lna_gain
= rt2x00_get_field16(eeprom
, EEPROM_LNA_A0
);
1863 } else if (libconf
->rf
.channel
<= 128) {
1864 if (rt2x00_rt(rt2x00dev
, RT3593
)) {
1865 rt2800_eeprom_read(rt2x00dev
, EEPROM_EXT_LNA2
, &eeprom
);
1866 lna_gain
= rt2x00_get_field16(eeprom
,
1867 EEPROM_EXT_LNA2_A1
);
1869 rt2800_eeprom_read(rt2x00dev
, EEPROM_RSSI_BG2
, &eeprom
);
1870 lna_gain
= rt2x00_get_field16(eeprom
,
1871 EEPROM_RSSI_BG2_LNA_A1
);
1874 if (rt2x00_rt(rt2x00dev
, RT3593
)) {
1875 rt2800_eeprom_read(rt2x00dev
, EEPROM_EXT_LNA2
, &eeprom
);
1876 lna_gain
= rt2x00_get_field16(eeprom
,
1877 EEPROM_EXT_LNA2_A2
);
1879 rt2800_eeprom_read(rt2x00dev
, EEPROM_RSSI_A2
, &eeprom
);
1880 lna_gain
= rt2x00_get_field16(eeprom
,
1881 EEPROM_RSSI_A2_LNA_A2
);
1885 rt2x00dev
->lna_gain
= lna_gain
;
1888 #define FREQ_OFFSET_BOUND 0x5f
1890 static void rt2800_adjust_freq_offset(struct rt2x00_dev
*rt2x00dev
)
1892 u8 freq_offset
, prev_freq_offset
;
1893 u8 rfcsr
, prev_rfcsr
;
1895 freq_offset
= rt2x00_get_field8(rt2x00dev
->freq_offset
, RFCSR17_CODE
);
1896 freq_offset
= min_t(u8
, freq_offset
, FREQ_OFFSET_BOUND
);
1898 rt2800_rfcsr_read(rt2x00dev
, 17, &rfcsr
);
1901 rt2x00_set_field8(&rfcsr
, RFCSR17_CODE
, freq_offset
);
1902 if (rfcsr
== prev_rfcsr
)
1905 if (rt2x00_is_usb(rt2x00dev
)) {
1906 rt2800_mcu_request(rt2x00dev
, MCU_FREQ_OFFSET
, 0xff,
1907 freq_offset
, prev_rfcsr
);
1911 prev_freq_offset
= rt2x00_get_field8(prev_rfcsr
, RFCSR17_CODE
);
1912 while (prev_freq_offset
!= freq_offset
) {
1913 if (prev_freq_offset
< freq_offset
)
1918 rt2x00_set_field8(&rfcsr
, RFCSR17_CODE
, prev_freq_offset
);
1919 rt2800_rfcsr_write(rt2x00dev
, 17, rfcsr
);
1921 usleep_range(1000, 1500);
1925 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev
*rt2x00dev
,
1926 struct ieee80211_conf
*conf
,
1927 struct rf_channel
*rf
,
1928 struct channel_info
*info
)
1930 rt2x00_set_field32(&rf
->rf4
, RF4_FREQ_OFFSET
, rt2x00dev
->freq_offset
);
1932 if (rt2x00dev
->default_ant
.tx_chain_num
== 1)
1933 rt2x00_set_field32(&rf
->rf2
, RF2_ANTENNA_TX1
, 1);
1935 if (rt2x00dev
->default_ant
.rx_chain_num
== 1) {
1936 rt2x00_set_field32(&rf
->rf2
, RF2_ANTENNA_RX1
, 1);
1937 rt2x00_set_field32(&rf
->rf2
, RF2_ANTENNA_RX2
, 1);
1938 } else if (rt2x00dev
->default_ant
.rx_chain_num
== 2)
1939 rt2x00_set_field32(&rf
->rf2
, RF2_ANTENNA_RX2
, 1);
1941 if (rf
->channel
> 14) {
1943 * When TX power is below 0, we should increase it by 7 to
1944 * make it a positive value (Minimum value is -7).
1945 * However this means that values between 0 and 7 have
1946 * double meaning, and we should set a 7DBm boost flag.
1948 rt2x00_set_field32(&rf
->rf3
, RF3_TXPOWER_A_7DBM_BOOST
,
1949 (info
->default_power1
>= 0));
1951 if (info
->default_power1
< 0)
1952 info
->default_power1
+= 7;
1954 rt2x00_set_field32(&rf
->rf3
, RF3_TXPOWER_A
, info
->default_power1
);
1956 rt2x00_set_field32(&rf
->rf4
, RF4_TXPOWER_A_7DBM_BOOST
,
1957 (info
->default_power2
>= 0));
1959 if (info
->default_power2
< 0)
1960 info
->default_power2
+= 7;
1962 rt2x00_set_field32(&rf
->rf4
, RF4_TXPOWER_A
, info
->default_power2
);
1964 rt2x00_set_field32(&rf
->rf3
, RF3_TXPOWER_G
, info
->default_power1
);
1965 rt2x00_set_field32(&rf
->rf4
, RF4_TXPOWER_G
, info
->default_power2
);
1968 rt2x00_set_field32(&rf
->rf4
, RF4_HT40
, conf_is_ht40(conf
));
1970 rt2800_rf_write(rt2x00dev
, 1, rf
->rf1
);
1971 rt2800_rf_write(rt2x00dev
, 2, rf
->rf2
);
1972 rt2800_rf_write(rt2x00dev
, 3, rf
->rf3
& ~0x00000004);
1973 rt2800_rf_write(rt2x00dev
, 4, rf
->rf4
);
1977 rt2800_rf_write(rt2x00dev
, 1, rf
->rf1
);
1978 rt2800_rf_write(rt2x00dev
, 2, rf
->rf2
);
1979 rt2800_rf_write(rt2x00dev
, 3, rf
->rf3
| 0x00000004);
1980 rt2800_rf_write(rt2x00dev
, 4, rf
->rf4
);
1984 rt2800_rf_write(rt2x00dev
, 1, rf
->rf1
);
1985 rt2800_rf_write(rt2x00dev
, 2, rf
->rf2
);
1986 rt2800_rf_write(rt2x00dev
, 3, rf
->rf3
& ~0x00000004);
1987 rt2800_rf_write(rt2x00dev
, 4, rf
->rf4
);
1990 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev
*rt2x00dev
,
1991 struct ieee80211_conf
*conf
,
1992 struct rf_channel
*rf
,
1993 struct channel_info
*info
)
1995 struct rt2800_drv_data
*drv_data
= rt2x00dev
->drv_data
;
1996 u8 rfcsr
, calib_tx
, calib_rx
;
1998 rt2800_rfcsr_write(rt2x00dev
, 2, rf
->rf1
);
2000 rt2800_rfcsr_read(rt2x00dev
, 3, &rfcsr
);
2001 rt2x00_set_field8(&rfcsr
, RFCSR3_K
, rf
->rf3
);
2002 rt2800_rfcsr_write(rt2x00dev
, 3, rfcsr
);
2004 rt2800_rfcsr_read(rt2x00dev
, 6, &rfcsr
);
2005 rt2x00_set_field8(&rfcsr
, RFCSR6_R1
, rf
->rf2
);
2006 rt2800_rfcsr_write(rt2x00dev
, 6, rfcsr
);
2008 rt2800_rfcsr_read(rt2x00dev
, 12, &rfcsr
);
2009 rt2x00_set_field8(&rfcsr
, RFCSR12_TX_POWER
, info
->default_power1
);
2010 rt2800_rfcsr_write(rt2x00dev
, 12, rfcsr
);
2012 rt2800_rfcsr_read(rt2x00dev
, 13, &rfcsr
);
2013 rt2x00_set_field8(&rfcsr
, RFCSR13_TX_POWER
, info
->default_power2
);
2014 rt2800_rfcsr_write(rt2x00dev
, 13, rfcsr
);
2016 rt2800_rfcsr_read(rt2x00dev
, 1, &rfcsr
);
2017 rt2x00_set_field8(&rfcsr
, RFCSR1_RX0_PD
, 0);
2018 rt2x00_set_field8(&rfcsr
, RFCSR1_RX1_PD
,
2019 rt2x00dev
->default_ant
.rx_chain_num
<= 1);
2020 rt2x00_set_field8(&rfcsr
, RFCSR1_RX2_PD
,
2021 rt2x00dev
->default_ant
.rx_chain_num
<= 2);
2022 rt2x00_set_field8(&rfcsr
, RFCSR1_TX0_PD
, 0);
2023 rt2x00_set_field8(&rfcsr
, RFCSR1_TX1_PD
,
2024 rt2x00dev
->default_ant
.tx_chain_num
<= 1);
2025 rt2x00_set_field8(&rfcsr
, RFCSR1_TX2_PD
,
2026 rt2x00dev
->default_ant
.tx_chain_num
<= 2);
2027 rt2800_rfcsr_write(rt2x00dev
, 1, rfcsr
);
2029 rt2800_rfcsr_read(rt2x00dev
, 23, &rfcsr
);
2030 rt2x00_set_field8(&rfcsr
, RFCSR23_FREQ_OFFSET
, rt2x00dev
->freq_offset
);
2031 rt2800_rfcsr_write(rt2x00dev
, 23, rfcsr
);
2033 if (rt2x00_rt(rt2x00dev
, RT3390
)) {
2034 calib_tx
= conf_is_ht40(conf
) ? 0x68 : 0x4f;
2035 calib_rx
= conf_is_ht40(conf
) ? 0x6f : 0x4f;
2037 if (conf_is_ht40(conf
)) {
2038 calib_tx
= drv_data
->calibration_bw40
;
2039 calib_rx
= drv_data
->calibration_bw40
;
2041 calib_tx
= drv_data
->calibration_bw20
;
2042 calib_rx
= drv_data
->calibration_bw20
;
2046 rt2800_rfcsr_read(rt2x00dev
, 24, &rfcsr
);
2047 rt2x00_set_field8(&rfcsr
, RFCSR24_TX_CALIB
, calib_tx
);
2048 rt2800_rfcsr_write(rt2x00dev
, 24, rfcsr
);
2050 rt2800_rfcsr_read(rt2x00dev
, 31, &rfcsr
);
2051 rt2x00_set_field8(&rfcsr
, RFCSR31_RX_CALIB
, calib_rx
);
2052 rt2800_rfcsr_write(rt2x00dev
, 31, rfcsr
);
2054 rt2800_rfcsr_read(rt2x00dev
, 7, &rfcsr
);
2055 rt2x00_set_field8(&rfcsr
, RFCSR7_RF_TUNING
, 1);
2056 rt2800_rfcsr_write(rt2x00dev
, 7, rfcsr
);
2058 rt2800_rfcsr_read(rt2x00dev
, 30, &rfcsr
);
2059 rt2x00_set_field8(&rfcsr
, RFCSR30_RF_CALIBRATION
, 1);
2060 rt2800_rfcsr_write(rt2x00dev
, 30, rfcsr
);
2062 rt2x00_set_field8(&rfcsr
, RFCSR30_RF_CALIBRATION
, 0);
2063 rt2800_rfcsr_write(rt2x00dev
, 30, rfcsr
);
2066 static void rt2800_config_channel_rf3052(struct rt2x00_dev
*rt2x00dev
,
2067 struct ieee80211_conf
*conf
,
2068 struct rf_channel
*rf
,
2069 struct channel_info
*info
)
2071 struct rt2800_drv_data
*drv_data
= rt2x00dev
->drv_data
;
2075 if (rf
->channel
<= 14) {
2076 rt2800_bbp_write(rt2x00dev
, 25, drv_data
->bbp25
);
2077 rt2800_bbp_write(rt2x00dev
, 26, drv_data
->bbp26
);
2079 rt2800_bbp_write(rt2x00dev
, 25, 0x09);
2080 rt2800_bbp_write(rt2x00dev
, 26, 0xff);
2083 rt2800_rfcsr_write(rt2x00dev
, 2, rf
->rf1
);
2084 rt2800_rfcsr_write(rt2x00dev
, 3, rf
->rf3
);
2086 rt2800_rfcsr_read(rt2x00dev
, 6, &rfcsr
);
2087 rt2x00_set_field8(&rfcsr
, RFCSR6_R1
, rf
->rf2
);
2088 if (rf
->channel
<= 14)
2089 rt2x00_set_field8(&rfcsr
, RFCSR6_TXDIV
, 2);
2091 rt2x00_set_field8(&rfcsr
, RFCSR6_TXDIV
, 1);
2092 rt2800_rfcsr_write(rt2x00dev
, 6, rfcsr
);
2094 rt2800_rfcsr_read(rt2x00dev
, 5, &rfcsr
);
2095 if (rf
->channel
<= 14)
2096 rt2x00_set_field8(&rfcsr
, RFCSR5_R1
, 1);
2098 rt2x00_set_field8(&rfcsr
, RFCSR5_R1
, 2);
2099 rt2800_rfcsr_write(rt2x00dev
, 5, rfcsr
);
2101 rt2800_rfcsr_read(rt2x00dev
, 12, &rfcsr
);
2102 if (rf
->channel
<= 14) {
2103 rt2x00_set_field8(&rfcsr
, RFCSR12_DR0
, 3);
2104 rt2x00_set_field8(&rfcsr
, RFCSR12_TX_POWER
,
2105 info
->default_power1
);
2107 rt2x00_set_field8(&rfcsr
, RFCSR12_DR0
, 7);
2108 rt2x00_set_field8(&rfcsr
, RFCSR12_TX_POWER
,
2109 (info
->default_power1
& 0x3) |
2110 ((info
->default_power1
& 0xC) << 1));
2112 rt2800_rfcsr_write(rt2x00dev
, 12, rfcsr
);
2114 rt2800_rfcsr_read(rt2x00dev
, 13, &rfcsr
);
2115 if (rf
->channel
<= 14) {
2116 rt2x00_set_field8(&rfcsr
, RFCSR13_DR0
, 3);
2117 rt2x00_set_field8(&rfcsr
, RFCSR13_TX_POWER
,
2118 info
->default_power2
);
2120 rt2x00_set_field8(&rfcsr
, RFCSR13_DR0
, 7);
2121 rt2x00_set_field8(&rfcsr
, RFCSR13_TX_POWER
,
2122 (info
->default_power2
& 0x3) |
2123 ((info
->default_power2
& 0xC) << 1));
2125 rt2800_rfcsr_write(rt2x00dev
, 13, rfcsr
);
2127 rt2800_rfcsr_read(rt2x00dev
, 1, &rfcsr
);
2128 rt2x00_set_field8(&rfcsr
, RFCSR1_RX0_PD
, 0);
2129 rt2x00_set_field8(&rfcsr
, RFCSR1_TX0_PD
, 0);
2130 rt2x00_set_field8(&rfcsr
, RFCSR1_RX1_PD
, 0);
2131 rt2x00_set_field8(&rfcsr
, RFCSR1_TX1_PD
, 0);
2132 rt2x00_set_field8(&rfcsr
, RFCSR1_RX2_PD
, 0);
2133 rt2x00_set_field8(&rfcsr
, RFCSR1_TX2_PD
, 0);
2134 if (rt2x00_has_cap_bt_coexist(rt2x00dev
)) {
2135 if (rf
->channel
<= 14) {
2136 rt2x00_set_field8(&rfcsr
, RFCSR1_RX0_PD
, 1);
2137 rt2x00_set_field8(&rfcsr
, RFCSR1_TX0_PD
, 1);
2139 rt2x00_set_field8(&rfcsr
, RFCSR1_RX2_PD
, 1);
2140 rt2x00_set_field8(&rfcsr
, RFCSR1_TX2_PD
, 1);
2142 switch (rt2x00dev
->default_ant
.tx_chain_num
) {
2144 rt2x00_set_field8(&rfcsr
, RFCSR1_TX1_PD
, 1);
2146 rt2x00_set_field8(&rfcsr
, RFCSR1_TX2_PD
, 1);
2150 switch (rt2x00dev
->default_ant
.rx_chain_num
) {
2152 rt2x00_set_field8(&rfcsr
, RFCSR1_RX1_PD
, 1);
2154 rt2x00_set_field8(&rfcsr
, RFCSR1_RX2_PD
, 1);
2158 rt2800_rfcsr_write(rt2x00dev
, 1, rfcsr
);
2160 rt2800_rfcsr_read(rt2x00dev
, 23, &rfcsr
);
2161 rt2x00_set_field8(&rfcsr
, RFCSR23_FREQ_OFFSET
, rt2x00dev
->freq_offset
);
2162 rt2800_rfcsr_write(rt2x00dev
, 23, rfcsr
);
2164 if (conf_is_ht40(conf
)) {
2165 rt2800_rfcsr_write(rt2x00dev
, 24, drv_data
->calibration_bw40
);
2166 rt2800_rfcsr_write(rt2x00dev
, 31, drv_data
->calibration_bw40
);
2168 rt2800_rfcsr_write(rt2x00dev
, 24, drv_data
->calibration_bw20
);
2169 rt2800_rfcsr_write(rt2x00dev
, 31, drv_data
->calibration_bw20
);
2172 if (rf
->channel
<= 14) {
2173 rt2800_rfcsr_write(rt2x00dev
, 7, 0xd8);
2174 rt2800_rfcsr_write(rt2x00dev
, 9, 0xc3);
2175 rt2800_rfcsr_write(rt2x00dev
, 10, 0xf1);
2176 rt2800_rfcsr_write(rt2x00dev
, 11, 0xb9);
2177 rt2800_rfcsr_write(rt2x00dev
, 15, 0x53);
2179 rt2x00_set_field8(&rfcsr
, RFCSR16_TXMIXER_GAIN
,
2180 drv_data
->txmixer_gain_24g
);
2181 rt2800_rfcsr_write(rt2x00dev
, 16, rfcsr
);
2182 rt2800_rfcsr_write(rt2x00dev
, 17, 0x23);
2183 rt2800_rfcsr_write(rt2x00dev
, 19, 0x93);
2184 rt2800_rfcsr_write(rt2x00dev
, 20, 0xb3);
2185 rt2800_rfcsr_write(rt2x00dev
, 25, 0x15);
2186 rt2800_rfcsr_write(rt2x00dev
, 26, 0x85);
2187 rt2800_rfcsr_write(rt2x00dev
, 27, 0x00);
2188 rt2800_rfcsr_write(rt2x00dev
, 29, 0x9b);
2190 rt2800_rfcsr_read(rt2x00dev
, 7, &rfcsr
);
2191 rt2x00_set_field8(&rfcsr
, RFCSR7_BIT2
, 1);
2192 rt2x00_set_field8(&rfcsr
, RFCSR7_BIT3
, 0);
2193 rt2x00_set_field8(&rfcsr
, RFCSR7_BIT4
, 1);
2194 rt2x00_set_field8(&rfcsr
, RFCSR7_BITS67
, 0);
2195 rt2800_rfcsr_write(rt2x00dev
, 7, rfcsr
);
2196 rt2800_rfcsr_write(rt2x00dev
, 9, 0xc0);
2197 rt2800_rfcsr_write(rt2x00dev
, 10, 0xf1);
2198 rt2800_rfcsr_write(rt2x00dev
, 11, 0x00);
2199 rt2800_rfcsr_write(rt2x00dev
, 15, 0x43);
2201 rt2x00_set_field8(&rfcsr
, RFCSR16_TXMIXER_GAIN
,
2202 drv_data
->txmixer_gain_5g
);
2203 rt2800_rfcsr_write(rt2x00dev
, 16, rfcsr
);
2204 rt2800_rfcsr_write(rt2x00dev
, 17, 0x23);
2205 if (rf
->channel
<= 64) {
2206 rt2800_rfcsr_write(rt2x00dev
, 19, 0xb7);
2207 rt2800_rfcsr_write(rt2x00dev
, 20, 0xf6);
2208 rt2800_rfcsr_write(rt2x00dev
, 25, 0x3d);
2209 } else if (rf
->channel
<= 128) {
2210 rt2800_rfcsr_write(rt2x00dev
, 19, 0x74);
2211 rt2800_rfcsr_write(rt2x00dev
, 20, 0xf4);
2212 rt2800_rfcsr_write(rt2x00dev
, 25, 0x01);
2214 rt2800_rfcsr_write(rt2x00dev
, 19, 0x72);
2215 rt2800_rfcsr_write(rt2x00dev
, 20, 0xf3);
2216 rt2800_rfcsr_write(rt2x00dev
, 25, 0x01);
2218 rt2800_rfcsr_write(rt2x00dev
, 26, 0x87);
2219 rt2800_rfcsr_write(rt2x00dev
, 27, 0x01);
2220 rt2800_rfcsr_write(rt2x00dev
, 29, 0x9f);
2223 rt2800_register_read(rt2x00dev
, GPIO_CTRL
, ®
);
2224 rt2x00_set_field32(®
, GPIO_CTRL_DIR7
, 0);
2225 if (rf
->channel
<= 14)
2226 rt2x00_set_field32(®
, GPIO_CTRL_VAL7
, 1);
2228 rt2x00_set_field32(®
, GPIO_CTRL_VAL7
, 0);
2229 rt2800_register_write(rt2x00dev
, GPIO_CTRL
, reg
);
2231 rt2800_rfcsr_read(rt2x00dev
, 7, &rfcsr
);
2232 rt2x00_set_field8(&rfcsr
, RFCSR7_RF_TUNING
, 1);
2233 rt2800_rfcsr_write(rt2x00dev
, 7, rfcsr
);
2236 static void rt2800_config_channel_rf3053(struct rt2x00_dev
*rt2x00dev
,
2237 struct ieee80211_conf
*conf
,
2238 struct rf_channel
*rf
,
2239 struct channel_info
*info
)
2241 struct rt2800_drv_data
*drv_data
= rt2x00dev
->drv_data
;
2246 const bool txbf_enabled
= false; /* TODO */
2248 /* TODO: use TX{0,1,2}FinePowerControl values from EEPROM */
2249 rt2800_bbp_read(rt2x00dev
, 109, &bbp
);
2250 rt2x00_set_field8(&bbp
, BBP109_TX0_POWER
, 0);
2251 rt2x00_set_field8(&bbp
, BBP109_TX1_POWER
, 0);
2252 rt2800_bbp_write(rt2x00dev
, 109, bbp
);
2254 rt2800_bbp_read(rt2x00dev
, 110, &bbp
);
2255 rt2x00_set_field8(&bbp
, BBP110_TX2_POWER
, 0);
2256 rt2800_bbp_write(rt2x00dev
, 110, bbp
);
2258 if (rf
->channel
<= 14) {
2259 /* Restore BBP 25 & 26 for 2.4 GHz */
2260 rt2800_bbp_write(rt2x00dev
, 25, drv_data
->bbp25
);
2261 rt2800_bbp_write(rt2x00dev
, 26, drv_data
->bbp26
);
2263 /* Hard code BBP 25 & 26 for 5GHz */
2265 /* Enable IQ Phase correction */
2266 rt2800_bbp_write(rt2x00dev
, 25, 0x09);
2267 /* Setup IQ Phase correction value */
2268 rt2800_bbp_write(rt2x00dev
, 26, 0xff);
2271 rt2800_rfcsr_write(rt2x00dev
, 8, rf
->rf1
);
2272 rt2800_rfcsr_write(rt2x00dev
, 9, rf
->rf3
& 0xf);
2274 rt2800_rfcsr_read(rt2x00dev
, 11, &rfcsr
);
2275 rt2x00_set_field8(&rfcsr
, RFCSR11_R
, (rf
->rf2
& 0x3));
2276 rt2800_rfcsr_write(rt2x00dev
, 11, rfcsr
);
2278 rt2800_rfcsr_read(rt2x00dev
, 11, &rfcsr
);
2279 rt2x00_set_field8(&rfcsr
, RFCSR11_PLL_IDOH
, 1);
2280 if (rf
->channel
<= 14)
2281 rt2x00_set_field8(&rfcsr
, RFCSR11_PLL_MOD
, 1);
2283 rt2x00_set_field8(&rfcsr
, RFCSR11_PLL_MOD
, 2);
2284 rt2800_rfcsr_write(rt2x00dev
, 11, rfcsr
);
2286 rt2800_rfcsr_read(rt2x00dev
, 53, &rfcsr
);
2287 if (rf
->channel
<= 14) {
2289 rt2x00_set_field8(&rfcsr
, RFCSR53_TX_POWER
,
2290 info
->default_power1
& 0x1f);
2292 if (rt2x00_is_usb(rt2x00dev
))
2295 rt2x00_set_field8(&rfcsr
, RFCSR53_TX_POWER
,
2296 ((info
->default_power1
& 0x18) << 1) |
2297 (info
->default_power1
& 7));
2299 rt2800_rfcsr_write(rt2x00dev
, 53, rfcsr
);
2301 rt2800_rfcsr_read(rt2x00dev
, 55, &rfcsr
);
2302 if (rf
->channel
<= 14) {
2304 rt2x00_set_field8(&rfcsr
, RFCSR55_TX_POWER
,
2305 info
->default_power2
& 0x1f);
2307 if (rt2x00_is_usb(rt2x00dev
))
2310 rt2x00_set_field8(&rfcsr
, RFCSR55_TX_POWER
,
2311 ((info
->default_power2
& 0x18) << 1) |
2312 (info
->default_power2
& 7));
2314 rt2800_rfcsr_write(rt2x00dev
, 55, rfcsr
);
2316 rt2800_rfcsr_read(rt2x00dev
, 54, &rfcsr
);
2317 if (rf
->channel
<= 14) {
2319 rt2x00_set_field8(&rfcsr
, RFCSR54_TX_POWER
,
2320 info
->default_power3
& 0x1f);
2322 if (rt2x00_is_usb(rt2x00dev
))
2325 rt2x00_set_field8(&rfcsr
, RFCSR54_TX_POWER
,
2326 ((info
->default_power3
& 0x18) << 1) |
2327 (info
->default_power3
& 7));
2329 rt2800_rfcsr_write(rt2x00dev
, 54, rfcsr
);
2331 rt2800_rfcsr_read(rt2x00dev
, 1, &rfcsr
);
2332 rt2x00_set_field8(&rfcsr
, RFCSR1_RX0_PD
, 0);
2333 rt2x00_set_field8(&rfcsr
, RFCSR1_TX0_PD
, 0);
2334 rt2x00_set_field8(&rfcsr
, RFCSR1_RX1_PD
, 0);
2335 rt2x00_set_field8(&rfcsr
, RFCSR1_TX1_PD
, 0);
2336 rt2x00_set_field8(&rfcsr
, RFCSR1_RX2_PD
, 0);
2337 rt2x00_set_field8(&rfcsr
, RFCSR1_TX2_PD
, 0);
2338 rt2x00_set_field8(&rfcsr
, RFCSR1_RF_BLOCK_EN
, 1);
2339 rt2x00_set_field8(&rfcsr
, RFCSR1_PLL_PD
, 1);
2341 switch (rt2x00dev
->default_ant
.tx_chain_num
) {
2343 rt2x00_set_field8(&rfcsr
, RFCSR1_TX2_PD
, 1);
2346 rt2x00_set_field8(&rfcsr
, RFCSR1_TX1_PD
, 1);
2349 rt2x00_set_field8(&rfcsr
, RFCSR1_TX0_PD
, 1);
2353 switch (rt2x00dev
->default_ant
.rx_chain_num
) {
2355 rt2x00_set_field8(&rfcsr
, RFCSR1_RX2_PD
, 1);
2358 rt2x00_set_field8(&rfcsr
, RFCSR1_RX1_PD
, 1);
2361 rt2x00_set_field8(&rfcsr
, RFCSR1_RX0_PD
, 1);
2364 rt2800_rfcsr_write(rt2x00dev
, 1, rfcsr
);
2366 rt2800_adjust_freq_offset(rt2x00dev
);
2368 if (conf_is_ht40(conf
)) {
2369 txrx_agc_fc
= rt2x00_get_field8(drv_data
->calibration_bw40
,
2371 txrx_h20m
= rt2x00_get_field8(drv_data
->calibration_bw40
,
2374 txrx_agc_fc
= rt2x00_get_field8(drv_data
->calibration_bw20
,
2376 txrx_h20m
= rt2x00_get_field8(drv_data
->calibration_bw20
,
2380 /* NOTE: the reference driver does not writes the new value
2383 rt2800_rfcsr_read(rt2x00dev
, 32, &rfcsr
);
2384 rt2x00_set_field8(&rfcsr
, RFCSR32_TX_AGC_FC
, txrx_agc_fc
);
2386 if (rf
->channel
<= 14)
2390 rt2800_rfcsr_write(rt2x00dev
, 31, rfcsr
);
2392 rt2800_rfcsr_read(rt2x00dev
, 30, &rfcsr
);
2393 rt2x00_set_field8(&rfcsr
, RFCSR30_TX_H20M
, txrx_h20m
);
2394 rt2x00_set_field8(&rfcsr
, RFCSR30_RX_H20M
, txrx_h20m
);
2395 rt2800_rfcsr_write(rt2x00dev
, 30, rfcsr
);
2397 /* Band selection */
2398 rt2800_rfcsr_read(rt2x00dev
, 36, &rfcsr
);
2399 if (rf
->channel
<= 14)
2400 rt2x00_set_field8(&rfcsr
, RFCSR36_RF_BS
, 1);
2402 rt2x00_set_field8(&rfcsr
, RFCSR36_RF_BS
, 0);
2403 rt2800_rfcsr_write(rt2x00dev
, 36, rfcsr
);
2405 rt2800_rfcsr_read(rt2x00dev
, 34, &rfcsr
);
2406 if (rf
->channel
<= 14)
2410 rt2800_rfcsr_write(rt2x00dev
, 34, rfcsr
);
2412 rt2800_rfcsr_read(rt2x00dev
, 12, &rfcsr
);
2413 if (rf
->channel
<= 14)
2417 rt2800_rfcsr_write(rt2x00dev
, 12, rfcsr
);
2419 rt2800_rfcsr_read(rt2x00dev
, 6, &rfcsr
);
2420 if (rf
->channel
>= 1 && rf
->channel
<= 14)
2421 rt2x00_set_field8(&rfcsr
, RFCSR6_VCO_IC
, 1);
2422 else if (rf
->channel
>= 36 && rf
->channel
<= 64)
2423 rt2x00_set_field8(&rfcsr
, RFCSR6_VCO_IC
, 2);
2424 else if (rf
->channel
>= 100 && rf
->channel
<= 128)
2425 rt2x00_set_field8(&rfcsr
, RFCSR6_VCO_IC
, 2);
2427 rt2x00_set_field8(&rfcsr
, RFCSR6_VCO_IC
, 1);
2428 rt2800_rfcsr_write(rt2x00dev
, 6, rfcsr
);
2430 rt2800_rfcsr_read(rt2x00dev
, 30, &rfcsr
);
2431 rt2x00_set_field8(&rfcsr
, RFCSR30_RX_VCM
, 2);
2432 rt2800_rfcsr_write(rt2x00dev
, 30, rfcsr
);
2434 rt2800_rfcsr_write(rt2x00dev
, 46, 0x60);
2436 if (rf
->channel
<= 14) {
2437 rt2800_rfcsr_write(rt2x00dev
, 10, 0xd3);
2438 rt2800_rfcsr_write(rt2x00dev
, 13, 0x12);
2440 rt2800_rfcsr_write(rt2x00dev
, 10, 0xd8);
2441 rt2800_rfcsr_write(rt2x00dev
, 13, 0x23);
2444 rt2800_rfcsr_read(rt2x00dev
, 51, &rfcsr
);
2445 rt2x00_set_field8(&rfcsr
, RFCSR51_BITS01
, 1);
2446 rt2800_rfcsr_write(rt2x00dev
, 51, rfcsr
);
2448 rt2800_rfcsr_read(rt2x00dev
, 51, &rfcsr
);
2449 if (rf
->channel
<= 14) {
2450 rt2x00_set_field8(&rfcsr
, RFCSR51_BITS24
, 5);
2451 rt2x00_set_field8(&rfcsr
, RFCSR51_BITS57
, 3);
2453 rt2x00_set_field8(&rfcsr
, RFCSR51_BITS24
, 4);
2454 rt2x00_set_field8(&rfcsr
, RFCSR51_BITS57
, 2);
2456 rt2800_rfcsr_write(rt2x00dev
, 51, rfcsr
);
2458 rt2800_rfcsr_read(rt2x00dev
, 49, &rfcsr
);
2459 if (rf
->channel
<= 14)
2460 rt2x00_set_field8(&rfcsr
, RFCSR49_TX_LO1_IC
, 3);
2462 rt2x00_set_field8(&rfcsr
, RFCSR49_TX_LO1_IC
, 2);
2465 rt2x00_set_field8(&rfcsr
, RFCSR49_TX_DIV
, 1);
2467 rt2800_rfcsr_write(rt2x00dev
, 49, rfcsr
);
2469 rt2800_rfcsr_read(rt2x00dev
, 50, &rfcsr
);
2470 rt2x00_set_field8(&rfcsr
, RFCSR50_TX_LO1_EN
, 0);
2471 rt2800_rfcsr_write(rt2x00dev
, 50, rfcsr
);
2473 rt2800_rfcsr_read(rt2x00dev
, 57, &rfcsr
);
2474 if (rf
->channel
<= 14)
2475 rt2x00_set_field8(&rfcsr
, RFCSR57_DRV_CC
, 0x1b);
2477 rt2x00_set_field8(&rfcsr
, RFCSR57_DRV_CC
, 0x0f);
2478 rt2800_rfcsr_write(rt2x00dev
, 57, rfcsr
);
2480 if (rf
->channel
<= 14) {
2481 rt2800_rfcsr_write(rt2x00dev
, 44, 0x93);
2482 rt2800_rfcsr_write(rt2x00dev
, 52, 0x45);
2484 rt2800_rfcsr_write(rt2x00dev
, 44, 0x9b);
2485 rt2800_rfcsr_write(rt2x00dev
, 52, 0x05);
2488 /* Initiate VCO calibration */
2489 rt2800_rfcsr_read(rt2x00dev
, 3, &rfcsr
);
2490 if (rf
->channel
<= 14) {
2491 rt2x00_set_field8(&rfcsr
, RFCSR3_VCOCAL_EN
, 1);
2493 rt2x00_set_field8(&rfcsr
, RFCSR3_BIT1
, 1);
2494 rt2x00_set_field8(&rfcsr
, RFCSR3_BIT2
, 1);
2495 rt2x00_set_field8(&rfcsr
, RFCSR3_BIT3
, 1);
2496 rt2x00_set_field8(&rfcsr
, RFCSR3_BIT4
, 1);
2497 rt2x00_set_field8(&rfcsr
, RFCSR3_BIT5
, 1);
2498 rt2x00_set_field8(&rfcsr
, RFCSR3_VCOCAL_EN
, 1);
2500 rt2800_rfcsr_write(rt2x00dev
, 3, rfcsr
);
2502 if (rf
->channel
>= 1 && rf
->channel
<= 14) {
2505 rt2x00_set_field8(&rfcsr
, RFCSR39_RX_DIV
, 1);
2506 rt2800_rfcsr_write(rt2x00dev
, 39, rfcsr
);
2508 rt2800_rfcsr_write(rt2x00dev
, 45, 0xbb);
2509 } else if (rf
->channel
>= 36 && rf
->channel
<= 64) {
2512 rt2x00_set_field8(&rfcsr
, RFCSR39_RX_DIV
, 1);
2513 rt2800_rfcsr_write(rt2x00dev
, 39, 0x36);
2515 rt2800_rfcsr_write(rt2x00dev
, 45, 0xeb);
2516 } else if (rf
->channel
>= 100 && rf
->channel
<= 128) {
2519 rt2x00_set_field8(&rfcsr
, RFCSR39_RX_DIV
, 1);
2520 rt2800_rfcsr_write(rt2x00dev
, 39, rfcsr
);
2522 rt2800_rfcsr_write(rt2x00dev
, 45, 0xb3);
2526 rt2x00_set_field8(&rfcsr
, RFCSR39_RX_DIV
, 1);
2527 rt2800_rfcsr_write(rt2x00dev
, 39, rfcsr
);
2529 rt2800_rfcsr_write(rt2x00dev
, 45, 0x9b);
2533 #define POWER_BOUND 0x27
2534 #define POWER_BOUND_5G 0x2b
2536 static void rt2800_config_channel_rf3290(struct rt2x00_dev
*rt2x00dev
,
2537 struct ieee80211_conf
*conf
,
2538 struct rf_channel
*rf
,
2539 struct channel_info
*info
)
2543 rt2800_rfcsr_write(rt2x00dev
, 8, rf
->rf1
);
2544 rt2800_rfcsr_write(rt2x00dev
, 9, rf
->rf3
);
2545 rt2800_rfcsr_read(rt2x00dev
, 11, &rfcsr
);
2546 rt2x00_set_field8(&rfcsr
, RFCSR11_R
, rf
->rf2
);
2547 rt2800_rfcsr_write(rt2x00dev
, 11, rfcsr
);
2549 rt2800_rfcsr_read(rt2x00dev
, 49, &rfcsr
);
2550 if (info
->default_power1
> POWER_BOUND
)
2551 rt2x00_set_field8(&rfcsr
, RFCSR49_TX
, POWER_BOUND
);
2553 rt2x00_set_field8(&rfcsr
, RFCSR49_TX
, info
->default_power1
);
2554 rt2800_rfcsr_write(rt2x00dev
, 49, rfcsr
);
2556 rt2800_adjust_freq_offset(rt2x00dev
);
2558 if (rf
->channel
<= 14) {
2559 if (rf
->channel
== 6)
2560 rt2800_bbp_write(rt2x00dev
, 68, 0x0c);
2562 rt2800_bbp_write(rt2x00dev
, 68, 0x0b);
2564 if (rf
->channel
>= 1 && rf
->channel
<= 6)
2565 rt2800_bbp_write(rt2x00dev
, 59, 0x0f);
2566 else if (rf
->channel
>= 7 && rf
->channel
<= 11)
2567 rt2800_bbp_write(rt2x00dev
, 59, 0x0e);
2568 else if (rf
->channel
>= 12 && rf
->channel
<= 14)
2569 rt2800_bbp_write(rt2x00dev
, 59, 0x0d);
2573 static void rt2800_config_channel_rf3322(struct rt2x00_dev
*rt2x00dev
,
2574 struct ieee80211_conf
*conf
,
2575 struct rf_channel
*rf
,
2576 struct channel_info
*info
)
2580 rt2800_rfcsr_write(rt2x00dev
, 8, rf
->rf1
);
2581 rt2800_rfcsr_write(rt2x00dev
, 9, rf
->rf3
);
2583 rt2800_rfcsr_write(rt2x00dev
, 11, 0x42);
2584 rt2800_rfcsr_write(rt2x00dev
, 12, 0x1c);
2585 rt2800_rfcsr_write(rt2x00dev
, 13, 0x00);
2587 if (info
->default_power1
> POWER_BOUND
)
2588 rt2800_rfcsr_write(rt2x00dev
, 47, POWER_BOUND
);
2590 rt2800_rfcsr_write(rt2x00dev
, 47, info
->default_power1
);
2592 if (info
->default_power2
> POWER_BOUND
)
2593 rt2800_rfcsr_write(rt2x00dev
, 48, POWER_BOUND
);
2595 rt2800_rfcsr_write(rt2x00dev
, 48, info
->default_power2
);
2597 rt2800_adjust_freq_offset(rt2x00dev
);
2599 rt2800_rfcsr_read(rt2x00dev
, 1, &rfcsr
);
2600 rt2x00_set_field8(&rfcsr
, RFCSR1_RX0_PD
, 1);
2601 rt2x00_set_field8(&rfcsr
, RFCSR1_TX0_PD
, 1);
2603 if ( rt2x00dev
->default_ant
.tx_chain_num
== 2 )
2604 rt2x00_set_field8(&rfcsr
, RFCSR1_TX1_PD
, 1);
2606 rt2x00_set_field8(&rfcsr
, RFCSR1_TX1_PD
, 0);
2608 if ( rt2x00dev
->default_ant
.rx_chain_num
== 2 )
2609 rt2x00_set_field8(&rfcsr
, RFCSR1_RX1_PD
, 1);
2611 rt2x00_set_field8(&rfcsr
, RFCSR1_RX1_PD
, 0);
2613 rt2x00_set_field8(&rfcsr
, RFCSR1_RX2_PD
, 0);
2614 rt2x00_set_field8(&rfcsr
, RFCSR1_TX2_PD
, 0);
2616 rt2800_rfcsr_write(rt2x00dev
, 1, rfcsr
);
2618 rt2800_rfcsr_write(rt2x00dev
, 31, 80);
2621 static void rt2800_config_channel_rf53xx(struct rt2x00_dev
*rt2x00dev
,
2622 struct ieee80211_conf
*conf
,
2623 struct rf_channel
*rf
,
2624 struct channel_info
*info
)
2628 rt2800_rfcsr_write(rt2x00dev
, 8, rf
->rf1
);
2629 rt2800_rfcsr_write(rt2x00dev
, 9, rf
->rf3
);
2630 rt2800_rfcsr_read(rt2x00dev
, 11, &rfcsr
);
2631 rt2x00_set_field8(&rfcsr
, RFCSR11_R
, rf
->rf2
);
2632 rt2800_rfcsr_write(rt2x00dev
, 11, rfcsr
);
2634 rt2800_rfcsr_read(rt2x00dev
, 49, &rfcsr
);
2635 if (info
->default_power1
> POWER_BOUND
)
2636 rt2x00_set_field8(&rfcsr
, RFCSR49_TX
, POWER_BOUND
);
2638 rt2x00_set_field8(&rfcsr
, RFCSR49_TX
, info
->default_power1
);
2639 rt2800_rfcsr_write(rt2x00dev
, 49, rfcsr
);
2641 if (rt2x00_rt(rt2x00dev
, RT5392
)) {
2642 rt2800_rfcsr_read(rt2x00dev
, 50, &rfcsr
);
2643 if (info
->default_power2
> POWER_BOUND
)
2644 rt2x00_set_field8(&rfcsr
, RFCSR50_TX
, POWER_BOUND
);
2646 rt2x00_set_field8(&rfcsr
, RFCSR50_TX
,
2647 info
->default_power2
);
2648 rt2800_rfcsr_write(rt2x00dev
, 50, rfcsr
);
2651 rt2800_rfcsr_read(rt2x00dev
, 1, &rfcsr
);
2652 if (rt2x00_rt(rt2x00dev
, RT5392
)) {
2653 rt2x00_set_field8(&rfcsr
, RFCSR1_RX1_PD
, 1);
2654 rt2x00_set_field8(&rfcsr
, RFCSR1_TX1_PD
, 1);
2656 rt2x00_set_field8(&rfcsr
, RFCSR1_RF_BLOCK_EN
, 1);
2657 rt2x00_set_field8(&rfcsr
, RFCSR1_PLL_PD
, 1);
2658 rt2x00_set_field8(&rfcsr
, RFCSR1_RX0_PD
, 1);
2659 rt2x00_set_field8(&rfcsr
, RFCSR1_TX0_PD
, 1);
2660 rt2800_rfcsr_write(rt2x00dev
, 1, rfcsr
);
2662 rt2800_adjust_freq_offset(rt2x00dev
);
2664 if (rf
->channel
<= 14) {
2665 int idx
= rf
->channel
-1;
2667 if (rt2x00_has_cap_bt_coexist(rt2x00dev
)) {
2668 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390F
)) {
2669 /* r55/r59 value array of channel 1~14 */
2670 static const char r55_bt_rev
[] = {0x83, 0x83,
2671 0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
2672 0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
2673 static const char r59_bt_rev
[] = {0x0e, 0x0e,
2674 0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
2675 0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
2677 rt2800_rfcsr_write(rt2x00dev
, 55,
2679 rt2800_rfcsr_write(rt2x00dev
, 59,
2682 static const char r59_bt
[] = {0x8b, 0x8b, 0x8b,
2683 0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
2684 0x88, 0x88, 0x86, 0x85, 0x84};
2686 rt2800_rfcsr_write(rt2x00dev
, 59, r59_bt
[idx
]);
2689 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390F
)) {
2690 static const char r55_nonbt_rev
[] = {0x23, 0x23,
2691 0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
2692 0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
2693 static const char r59_nonbt_rev
[] = {0x07, 0x07,
2694 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
2695 0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
2697 rt2800_rfcsr_write(rt2x00dev
, 55,
2698 r55_nonbt_rev
[idx
]);
2699 rt2800_rfcsr_write(rt2x00dev
, 59,
2700 r59_nonbt_rev
[idx
]);
2701 } else if (rt2x00_rt(rt2x00dev
, RT5390
) ||
2702 rt2x00_rt(rt2x00dev
, RT5392
)) {
2703 static const char r59_non_bt
[] = {0x8f, 0x8f,
2704 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
2705 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
2707 rt2800_rfcsr_write(rt2x00dev
, 59,
2714 static void rt2800_config_channel_rf55xx(struct rt2x00_dev
*rt2x00dev
,
2715 struct ieee80211_conf
*conf
,
2716 struct rf_channel
*rf
,
2717 struct channel_info
*info
)
2724 const bool is_11b
= false;
2725 const bool is_type_ep
= false;
2727 rt2800_register_read(rt2x00dev
, LDO_CFG0
, ®
);
2728 rt2x00_set_field32(®
, LDO_CFG0_LDO_CORE_VLEVEL
,
2729 (rf
->channel
> 14 || conf_is_ht40(conf
)) ? 5 : 0);
2730 rt2800_register_write(rt2x00dev
, LDO_CFG0
, reg
);
2732 /* Order of values on rf_channel entry: N, K, mod, R */
2733 rt2800_rfcsr_write(rt2x00dev
, 8, rf
->rf1
& 0xff);
2735 rt2800_rfcsr_read(rt2x00dev
, 9, &rfcsr
);
2736 rt2x00_set_field8(&rfcsr
, RFCSR9_K
, rf
->rf2
& 0xf);
2737 rt2x00_set_field8(&rfcsr
, RFCSR9_N
, (rf
->rf1
& 0x100) >> 8);
2738 rt2x00_set_field8(&rfcsr
, RFCSR9_MOD
, ((rf
->rf3
- 8) & 0x4) >> 2);
2739 rt2800_rfcsr_write(rt2x00dev
, 9, rfcsr
);
2741 rt2800_rfcsr_read(rt2x00dev
, 11, &rfcsr
);
2742 rt2x00_set_field8(&rfcsr
, RFCSR11_R
, rf
->rf4
- 1);
2743 rt2x00_set_field8(&rfcsr
, RFCSR11_MOD
, (rf
->rf3
- 8) & 0x3);
2744 rt2800_rfcsr_write(rt2x00dev
, 11, rfcsr
);
2746 if (rf
->channel
<= 14) {
2747 rt2800_rfcsr_write(rt2x00dev
, 10, 0x90);
2748 /* FIXME: RF11 owerwrite ? */
2749 rt2800_rfcsr_write(rt2x00dev
, 11, 0x4A);
2750 rt2800_rfcsr_write(rt2x00dev
, 12, 0x52);
2751 rt2800_rfcsr_write(rt2x00dev
, 13, 0x42);
2752 rt2800_rfcsr_write(rt2x00dev
, 22, 0x40);
2753 rt2800_rfcsr_write(rt2x00dev
, 24, 0x4A);
2754 rt2800_rfcsr_write(rt2x00dev
, 25, 0x80);
2755 rt2800_rfcsr_write(rt2x00dev
, 27, 0x42);
2756 rt2800_rfcsr_write(rt2x00dev
, 36, 0x80);
2757 rt2800_rfcsr_write(rt2x00dev
, 37, 0x08);
2758 rt2800_rfcsr_write(rt2x00dev
, 38, 0x89);
2759 rt2800_rfcsr_write(rt2x00dev
, 39, 0x1B);
2760 rt2800_rfcsr_write(rt2x00dev
, 40, 0x0D);
2761 rt2800_rfcsr_write(rt2x00dev
, 41, 0x9B);
2762 rt2800_rfcsr_write(rt2x00dev
, 42, 0xD5);
2763 rt2800_rfcsr_write(rt2x00dev
, 43, 0x72);
2764 rt2800_rfcsr_write(rt2x00dev
, 44, 0x0E);
2765 rt2800_rfcsr_write(rt2x00dev
, 45, 0xA2);
2766 rt2800_rfcsr_write(rt2x00dev
, 46, 0x6B);
2767 rt2800_rfcsr_write(rt2x00dev
, 48, 0x10);
2768 rt2800_rfcsr_write(rt2x00dev
, 51, 0x3E);
2769 rt2800_rfcsr_write(rt2x00dev
, 52, 0x48);
2770 rt2800_rfcsr_write(rt2x00dev
, 54, 0x38);
2771 rt2800_rfcsr_write(rt2x00dev
, 56, 0xA1);
2772 rt2800_rfcsr_write(rt2x00dev
, 57, 0x00);
2773 rt2800_rfcsr_write(rt2x00dev
, 58, 0x39);
2774 rt2800_rfcsr_write(rt2x00dev
, 60, 0x45);
2775 rt2800_rfcsr_write(rt2x00dev
, 61, 0x91);
2776 rt2800_rfcsr_write(rt2x00dev
, 62, 0x39);
2778 /* TODO RF27 <- tssi */
2780 rfcsr
= rf
->channel
<= 10 ? 0x07 : 0x06;
2781 rt2800_rfcsr_write(rt2x00dev
, 23, rfcsr
);
2782 rt2800_rfcsr_write(rt2x00dev
, 59, rfcsr
);
2786 rt2800_rfcsr_write(rt2x00dev
, 31, 0xF8);
2787 rt2800_rfcsr_write(rt2x00dev
, 32, 0xC0);
2789 rt2800_rfcsr_write(rt2x00dev
, 55, 0x06);
2791 rt2800_rfcsr_write(rt2x00dev
, 55, 0x47);
2795 rt2800_rfcsr_write(rt2x00dev
, 55, 0x03);
2797 rt2800_rfcsr_write(rt2x00dev
, 55, 0x43);
2800 power_bound
= POWER_BOUND
;
2803 rt2800_rfcsr_write(rt2x00dev
, 10, 0x97);
2804 /* FIMXE: RF11 overwrite */
2805 rt2800_rfcsr_write(rt2x00dev
, 11, 0x40);
2806 rt2800_rfcsr_write(rt2x00dev
, 25, 0xBF);
2807 rt2800_rfcsr_write(rt2x00dev
, 27, 0x42);
2808 rt2800_rfcsr_write(rt2x00dev
, 36, 0x00);
2809 rt2800_rfcsr_write(rt2x00dev
, 37, 0x04);
2810 rt2800_rfcsr_write(rt2x00dev
, 38, 0x85);
2811 rt2800_rfcsr_write(rt2x00dev
, 40, 0x42);
2812 rt2800_rfcsr_write(rt2x00dev
, 41, 0xBB);
2813 rt2800_rfcsr_write(rt2x00dev
, 42, 0xD7);
2814 rt2800_rfcsr_write(rt2x00dev
, 45, 0x41);
2815 rt2800_rfcsr_write(rt2x00dev
, 48, 0x00);
2816 rt2800_rfcsr_write(rt2x00dev
, 57, 0x77);
2817 rt2800_rfcsr_write(rt2x00dev
, 60, 0x05);
2818 rt2800_rfcsr_write(rt2x00dev
, 61, 0x01);
2820 /* TODO RF27 <- tssi */
2822 if (rf
->channel
>= 36 && rf
->channel
<= 64) {
2824 rt2800_rfcsr_write(rt2x00dev
, 12, 0x2E);
2825 rt2800_rfcsr_write(rt2x00dev
, 13, 0x22);
2826 rt2800_rfcsr_write(rt2x00dev
, 22, 0x60);
2827 rt2800_rfcsr_write(rt2x00dev
, 23, 0x7F);
2828 if (rf
->channel
<= 50)
2829 rt2800_rfcsr_write(rt2x00dev
, 24, 0x09);
2830 else if (rf
->channel
>= 52)
2831 rt2800_rfcsr_write(rt2x00dev
, 24, 0x07);
2832 rt2800_rfcsr_write(rt2x00dev
, 39, 0x1C);
2833 rt2800_rfcsr_write(rt2x00dev
, 43, 0x5B);
2834 rt2800_rfcsr_write(rt2x00dev
, 44, 0X40);
2835 rt2800_rfcsr_write(rt2x00dev
, 46, 0X00);
2836 rt2800_rfcsr_write(rt2x00dev
, 51, 0xFE);
2837 rt2800_rfcsr_write(rt2x00dev
, 52, 0x0C);
2838 rt2800_rfcsr_write(rt2x00dev
, 54, 0xF8);
2839 if (rf
->channel
<= 50) {
2840 rt2800_rfcsr_write(rt2x00dev
, 55, 0x06),
2841 rt2800_rfcsr_write(rt2x00dev
, 56, 0xD3);
2842 } else if (rf
->channel
>= 52) {
2843 rt2800_rfcsr_write(rt2x00dev
, 55, 0x04);
2844 rt2800_rfcsr_write(rt2x00dev
, 56, 0xBB);
2847 rt2800_rfcsr_write(rt2x00dev
, 58, 0x15);
2848 rt2800_rfcsr_write(rt2x00dev
, 59, 0x7F);
2849 rt2800_rfcsr_write(rt2x00dev
, 62, 0x15);
2851 } else if (rf
->channel
>= 100 && rf
->channel
<= 165) {
2853 rt2800_rfcsr_write(rt2x00dev
, 12, 0x0E);
2854 rt2800_rfcsr_write(rt2x00dev
, 13, 0x42);
2855 rt2800_rfcsr_write(rt2x00dev
, 22, 0x40);
2856 if (rf
->channel
<= 153) {
2857 rt2800_rfcsr_write(rt2x00dev
, 23, 0x3C);
2858 rt2800_rfcsr_write(rt2x00dev
, 24, 0x06);
2859 } else if (rf
->channel
>= 155) {
2860 rt2800_rfcsr_write(rt2x00dev
, 23, 0x38);
2861 rt2800_rfcsr_write(rt2x00dev
, 24, 0x05);
2863 if (rf
->channel
<= 138) {
2864 rt2800_rfcsr_write(rt2x00dev
, 39, 0x1A);
2865 rt2800_rfcsr_write(rt2x00dev
, 43, 0x3B);
2866 rt2800_rfcsr_write(rt2x00dev
, 44, 0x20);
2867 rt2800_rfcsr_write(rt2x00dev
, 46, 0x18);
2868 } else if (rf
->channel
>= 140) {
2869 rt2800_rfcsr_write(rt2x00dev
, 39, 0x18);
2870 rt2800_rfcsr_write(rt2x00dev
, 43, 0x1B);
2871 rt2800_rfcsr_write(rt2x00dev
, 44, 0x10);
2872 rt2800_rfcsr_write(rt2x00dev
, 46, 0X08);
2874 if (rf
->channel
<= 124)
2875 rt2800_rfcsr_write(rt2x00dev
, 51, 0xFC);
2876 else if (rf
->channel
>= 126)
2877 rt2800_rfcsr_write(rt2x00dev
, 51, 0xEC);
2878 if (rf
->channel
<= 138)
2879 rt2800_rfcsr_write(rt2x00dev
, 52, 0x06);
2880 else if (rf
->channel
>= 140)
2881 rt2800_rfcsr_write(rt2x00dev
, 52, 0x06);
2882 rt2800_rfcsr_write(rt2x00dev
, 54, 0xEB);
2883 if (rf
->channel
<= 138)
2884 rt2800_rfcsr_write(rt2x00dev
, 55, 0x01);
2885 else if (rf
->channel
>= 140)
2886 rt2800_rfcsr_write(rt2x00dev
, 55, 0x00);
2887 if (rf
->channel
<= 128)
2888 rt2800_rfcsr_write(rt2x00dev
, 56, 0xBB);
2889 else if (rf
->channel
>= 130)
2890 rt2800_rfcsr_write(rt2x00dev
, 56, 0xAB);
2891 if (rf
->channel
<= 116)
2892 rt2800_rfcsr_write(rt2x00dev
, 58, 0x1D);
2893 else if (rf
->channel
>= 118)
2894 rt2800_rfcsr_write(rt2x00dev
, 58, 0x15);
2895 if (rf
->channel
<= 138)
2896 rt2800_rfcsr_write(rt2x00dev
, 59, 0x3F);
2897 else if (rf
->channel
>= 140)
2898 rt2800_rfcsr_write(rt2x00dev
, 59, 0x7C);
2899 if (rf
->channel
<= 116)
2900 rt2800_rfcsr_write(rt2x00dev
, 62, 0x1D);
2901 else if (rf
->channel
>= 118)
2902 rt2800_rfcsr_write(rt2x00dev
, 62, 0x15);
2905 power_bound
= POWER_BOUND_5G
;
2909 rt2800_rfcsr_read(rt2x00dev
, 49, &rfcsr
);
2910 if (info
->default_power1
> power_bound
)
2911 rt2x00_set_field8(&rfcsr
, RFCSR49_TX
, power_bound
);
2913 rt2x00_set_field8(&rfcsr
, RFCSR49_TX
, info
->default_power1
);
2915 rt2x00_set_field8(&rfcsr
, RFCSR49_EP
, ep_reg
);
2916 rt2800_rfcsr_write(rt2x00dev
, 49, rfcsr
);
2918 rt2800_rfcsr_read(rt2x00dev
, 50, &rfcsr
);
2919 if (info
->default_power2
> power_bound
)
2920 rt2x00_set_field8(&rfcsr
, RFCSR50_TX
, power_bound
);
2922 rt2x00_set_field8(&rfcsr
, RFCSR50_TX
, info
->default_power2
);
2924 rt2x00_set_field8(&rfcsr
, RFCSR50_EP
, ep_reg
);
2925 rt2800_rfcsr_write(rt2x00dev
, 50, rfcsr
);
2927 rt2800_rfcsr_read(rt2x00dev
, 1, &rfcsr
);
2928 rt2x00_set_field8(&rfcsr
, RFCSR1_RF_BLOCK_EN
, 1);
2929 rt2x00_set_field8(&rfcsr
, RFCSR1_PLL_PD
, 1);
2931 rt2x00_set_field8(&rfcsr
, RFCSR1_TX0_PD
,
2932 rt2x00dev
->default_ant
.tx_chain_num
>= 1);
2933 rt2x00_set_field8(&rfcsr
, RFCSR1_TX1_PD
,
2934 rt2x00dev
->default_ant
.tx_chain_num
== 2);
2935 rt2x00_set_field8(&rfcsr
, RFCSR1_TX2_PD
, 0);
2937 rt2x00_set_field8(&rfcsr
, RFCSR1_RX0_PD
,
2938 rt2x00dev
->default_ant
.rx_chain_num
>= 1);
2939 rt2x00_set_field8(&rfcsr
, RFCSR1_RX1_PD
,
2940 rt2x00dev
->default_ant
.rx_chain_num
== 2);
2941 rt2x00_set_field8(&rfcsr
, RFCSR1_RX2_PD
, 0);
2943 rt2800_rfcsr_write(rt2x00dev
, 1, rfcsr
);
2944 rt2800_rfcsr_write(rt2x00dev
, 6, 0xe4);
2946 if (conf_is_ht40(conf
))
2947 rt2800_rfcsr_write(rt2x00dev
, 30, 0x16);
2949 rt2800_rfcsr_write(rt2x00dev
, 30, 0x10);
2952 rt2800_rfcsr_write(rt2x00dev
, 31, 0x80);
2953 rt2800_rfcsr_write(rt2x00dev
, 32, 0x80);
2956 /* TODO proper frequency adjustment */
2957 rt2800_adjust_freq_offset(rt2x00dev
);
2959 /* TODO merge with others */
2960 rt2800_rfcsr_read(rt2x00dev
, 3, &rfcsr
);
2961 rt2x00_set_field8(&rfcsr
, RFCSR3_VCOCAL_EN
, 1);
2962 rt2800_rfcsr_write(rt2x00dev
, 3, rfcsr
);
2965 rt2800_bbp_write(rt2x00dev
, 62, 0x37 - rt2x00dev
->lna_gain
);
2966 rt2800_bbp_write(rt2x00dev
, 63, 0x37 - rt2x00dev
->lna_gain
);
2967 rt2800_bbp_write(rt2x00dev
, 64, 0x37 - rt2x00dev
->lna_gain
);
2969 rt2800_bbp_write(rt2x00dev
, 79, (rf
->channel
<= 14) ? 0x1C : 0x18);
2970 rt2800_bbp_write(rt2x00dev
, 80, (rf
->channel
<= 14) ? 0x0E : 0x08);
2971 rt2800_bbp_write(rt2x00dev
, 81, (rf
->channel
<= 14) ? 0x3A : 0x38);
2972 rt2800_bbp_write(rt2x00dev
, 82, (rf
->channel
<= 14) ? 0x62 : 0x92);
2974 /* GLRT band configuration */
2975 rt2800_bbp_write(rt2x00dev
, 195, 128);
2976 rt2800_bbp_write(rt2x00dev
, 196, (rf
->channel
<= 14) ? 0xE0 : 0xF0);
2977 rt2800_bbp_write(rt2x00dev
, 195, 129);
2978 rt2800_bbp_write(rt2x00dev
, 196, (rf
->channel
<= 14) ? 0x1F : 0x1E);
2979 rt2800_bbp_write(rt2x00dev
, 195, 130);
2980 rt2800_bbp_write(rt2x00dev
, 196, (rf
->channel
<= 14) ? 0x38 : 0x28);
2981 rt2800_bbp_write(rt2x00dev
, 195, 131);
2982 rt2800_bbp_write(rt2x00dev
, 196, (rf
->channel
<= 14) ? 0x32 : 0x20);
2983 rt2800_bbp_write(rt2x00dev
, 195, 133);
2984 rt2800_bbp_write(rt2x00dev
, 196, (rf
->channel
<= 14) ? 0x28 : 0x7F);
2985 rt2800_bbp_write(rt2x00dev
, 195, 124);
2986 rt2800_bbp_write(rt2x00dev
, 196, (rf
->channel
<= 14) ? 0x19 : 0x7F);
2989 static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev
*rt2x00dev
,
2990 const unsigned int word
,
2995 for (chain
= 0; chain
< rt2x00dev
->default_ant
.rx_chain_num
; chain
++) {
2996 rt2800_bbp_read(rt2x00dev
, 27, ®
);
2997 rt2x00_set_field8(®
, BBP27_RX_CHAIN_SEL
, chain
);
2998 rt2800_bbp_write(rt2x00dev
, 27, reg
);
3000 rt2800_bbp_write(rt2x00dev
, word
, value
);
3004 static void rt2800_iq_calibrate(struct rt2x00_dev
*rt2x00dev
, int channel
)
3009 rt2800_bbp_write(rt2x00dev
, 158, 0x2c);
3011 cal
= rt2x00_eeprom_byte(rt2x00dev
, EEPROM_IQ_GAIN_CAL_TX0_2G
);
3012 else if (channel
>= 36 && channel
<= 64)
3013 cal
= rt2x00_eeprom_byte(rt2x00dev
,
3014 EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5G
);
3015 else if (channel
>= 100 && channel
<= 138)
3016 cal
= rt2x00_eeprom_byte(rt2x00dev
,
3017 EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5G
);
3018 else if (channel
>= 140 && channel
<= 165)
3019 cal
= rt2x00_eeprom_byte(rt2x00dev
,
3020 EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5G
);
3023 rt2800_bbp_write(rt2x00dev
, 159, cal
);
3026 rt2800_bbp_write(rt2x00dev
, 158, 0x2d);
3028 cal
= rt2x00_eeprom_byte(rt2x00dev
, EEPROM_IQ_PHASE_CAL_TX0_2G
);
3029 else if (channel
>= 36 && channel
<= 64)
3030 cal
= rt2x00_eeprom_byte(rt2x00dev
,
3031 EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5G
);
3032 else if (channel
>= 100 && channel
<= 138)
3033 cal
= rt2x00_eeprom_byte(rt2x00dev
,
3034 EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5G
);
3035 else if (channel
>= 140 && channel
<= 165)
3036 cal
= rt2x00_eeprom_byte(rt2x00dev
,
3037 EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5G
);
3040 rt2800_bbp_write(rt2x00dev
, 159, cal
);
3043 rt2800_bbp_write(rt2x00dev
, 158, 0x4a);
3045 cal
= rt2x00_eeprom_byte(rt2x00dev
, EEPROM_IQ_GAIN_CAL_TX1_2G
);
3046 else if (channel
>= 36 && channel
<= 64)
3047 cal
= rt2x00_eeprom_byte(rt2x00dev
,
3048 EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5G
);
3049 else if (channel
>= 100 && channel
<= 138)
3050 cal
= rt2x00_eeprom_byte(rt2x00dev
,
3051 EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5G
);
3052 else if (channel
>= 140 && channel
<= 165)
3053 cal
= rt2x00_eeprom_byte(rt2x00dev
,
3054 EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5G
);
3057 rt2800_bbp_write(rt2x00dev
, 159, cal
);
3060 rt2800_bbp_write(rt2x00dev
, 158, 0x4b);
3062 cal
= rt2x00_eeprom_byte(rt2x00dev
, EEPROM_IQ_PHASE_CAL_TX1_2G
);
3063 else if (channel
>= 36 && channel
<= 64)
3064 cal
= rt2x00_eeprom_byte(rt2x00dev
,
3065 EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5G
);
3066 else if (channel
>= 100 && channel
<= 138)
3067 cal
= rt2x00_eeprom_byte(rt2x00dev
,
3068 EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5G
);
3069 else if (channel
>= 140 && channel
<= 165)
3070 cal
= rt2x00_eeprom_byte(rt2x00dev
,
3071 EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5G
);
3074 rt2800_bbp_write(rt2x00dev
, 159, cal
);
3076 /* FIXME: possible RX0, RX1 callibration ? */
3078 /* RF IQ compensation control */
3079 rt2800_bbp_write(rt2x00dev
, 158, 0x04);
3080 cal
= rt2x00_eeprom_byte(rt2x00dev
, EEPROM_RF_IQ_COMPENSATION_CONTROL
);
3081 rt2800_bbp_write(rt2x00dev
, 159, cal
!= 0xff ? cal
: 0);
3083 /* RF IQ imbalance compensation control */
3084 rt2800_bbp_write(rt2x00dev
, 158, 0x03);
3085 cal
= rt2x00_eeprom_byte(rt2x00dev
,
3086 EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CONTROL
);
3087 rt2800_bbp_write(rt2x00dev
, 159, cal
!= 0xff ? cal
: 0);
3090 static char rt2800_txpower_to_dev(struct rt2x00_dev
*rt2x00dev
,
3091 unsigned int channel
,
3094 if (rt2x00_rt(rt2x00dev
, RT3593
))
3095 txpower
= rt2x00_get_field8(txpower
, EEPROM_TXPOWER_ALC
);
3098 return clamp_t(char, txpower
, MIN_G_TXPOWER
, MAX_G_TXPOWER
);
3100 if (rt2x00_rt(rt2x00dev
, RT3593
))
3101 return clamp_t(char, txpower
, MIN_A_TXPOWER_3593
,
3102 MAX_A_TXPOWER_3593
);
3104 return clamp_t(char, txpower
, MIN_A_TXPOWER
, MAX_A_TXPOWER
);
3107 static void rt2800_config_channel(struct rt2x00_dev
*rt2x00dev
,
3108 struct ieee80211_conf
*conf
,
3109 struct rf_channel
*rf
,
3110 struct channel_info
*info
)
3113 unsigned int tx_pin
;
3116 info
->default_power1
= rt2800_txpower_to_dev(rt2x00dev
, rf
->channel
,
3117 info
->default_power1
);
3118 info
->default_power2
= rt2800_txpower_to_dev(rt2x00dev
, rf
->channel
,
3119 info
->default_power2
);
3120 if (rt2x00dev
->default_ant
.tx_chain_num
> 2)
3121 info
->default_power3
=
3122 rt2800_txpower_to_dev(rt2x00dev
, rf
->channel
,
3123 info
->default_power3
);
3125 switch (rt2x00dev
->chip
.rf
) {
3131 rt2800_config_channel_rf3xxx(rt2x00dev
, conf
, rf
, info
);
3134 rt2800_config_channel_rf3052(rt2x00dev
, conf
, rf
, info
);
3137 rt2800_config_channel_rf3053(rt2x00dev
, conf
, rf
, info
);
3140 rt2800_config_channel_rf3290(rt2x00dev
, conf
, rf
, info
);
3143 rt2800_config_channel_rf3322(rt2x00dev
, conf
, rf
, info
);
3151 rt2800_config_channel_rf53xx(rt2x00dev
, conf
, rf
, info
);
3154 rt2800_config_channel_rf55xx(rt2x00dev
, conf
, rf
, info
);
3157 rt2800_config_channel_rf2xxx(rt2x00dev
, conf
, rf
, info
);
3160 if (rt2x00_rf(rt2x00dev
, RF3070
) ||
3161 rt2x00_rf(rt2x00dev
, RF3290
) ||
3162 rt2x00_rf(rt2x00dev
, RF3322
) ||
3163 rt2x00_rf(rt2x00dev
, RF5360
) ||
3164 rt2x00_rf(rt2x00dev
, RF5370
) ||
3165 rt2x00_rf(rt2x00dev
, RF5372
) ||
3166 rt2x00_rf(rt2x00dev
, RF5390
) ||
3167 rt2x00_rf(rt2x00dev
, RF5392
)) {
3168 rt2800_rfcsr_read(rt2x00dev
, 30, &rfcsr
);
3169 rt2x00_set_field8(&rfcsr
, RFCSR30_TX_H20M
, 0);
3170 rt2x00_set_field8(&rfcsr
, RFCSR30_RX_H20M
, 0);
3171 rt2800_rfcsr_write(rt2x00dev
, 30, rfcsr
);
3173 rt2800_rfcsr_read(rt2x00dev
, 3, &rfcsr
);
3174 rt2x00_set_field8(&rfcsr
, RFCSR3_VCOCAL_EN
, 1);
3175 rt2800_rfcsr_write(rt2x00dev
, 3, rfcsr
);
3179 * Change BBP settings
3181 if (rt2x00_rt(rt2x00dev
, RT3352
)) {
3182 rt2800_bbp_write(rt2x00dev
, 27, 0x0);
3183 rt2800_bbp_write(rt2x00dev
, 66, 0x26 + rt2x00dev
->lna_gain
);
3184 rt2800_bbp_write(rt2x00dev
, 27, 0x20);
3185 rt2800_bbp_write(rt2x00dev
, 66, 0x26 + rt2x00dev
->lna_gain
);
3186 } else if (rt2x00_rt(rt2x00dev
, RT3593
)) {
3187 if (rf
->channel
> 14) {
3188 /* Disable CCK Packet detection on 5GHz */
3189 rt2800_bbp_write(rt2x00dev
, 70, 0x00);
3191 rt2800_bbp_write(rt2x00dev
, 70, 0x0a);
3194 if (conf_is_ht40(conf
))
3195 rt2800_bbp_write(rt2x00dev
, 105, 0x04);
3197 rt2800_bbp_write(rt2x00dev
, 105, 0x34);
3199 rt2800_bbp_write(rt2x00dev
, 62, 0x37 - rt2x00dev
->lna_gain
);
3200 rt2800_bbp_write(rt2x00dev
, 63, 0x37 - rt2x00dev
->lna_gain
);
3201 rt2800_bbp_write(rt2x00dev
, 64, 0x37 - rt2x00dev
->lna_gain
);
3202 rt2800_bbp_write(rt2x00dev
, 77, 0x98);
3204 rt2800_bbp_write(rt2x00dev
, 62, 0x37 - rt2x00dev
->lna_gain
);
3205 rt2800_bbp_write(rt2x00dev
, 63, 0x37 - rt2x00dev
->lna_gain
);
3206 rt2800_bbp_write(rt2x00dev
, 64, 0x37 - rt2x00dev
->lna_gain
);
3207 rt2800_bbp_write(rt2x00dev
, 86, 0);
3210 if (rf
->channel
<= 14) {
3211 if (!rt2x00_rt(rt2x00dev
, RT5390
) &&
3212 !rt2x00_rt(rt2x00dev
, RT5392
)) {
3213 if (rt2x00_has_cap_external_lna_bg(rt2x00dev
)) {
3214 rt2800_bbp_write(rt2x00dev
, 82, 0x62);
3215 rt2800_bbp_write(rt2x00dev
, 75, 0x46);
3217 if (rt2x00_rt(rt2x00dev
, RT3593
))
3218 rt2800_bbp_write(rt2x00dev
, 82, 0x62);
3220 rt2800_bbp_write(rt2x00dev
, 82, 0x84);
3221 rt2800_bbp_write(rt2x00dev
, 75, 0x50);
3223 if (rt2x00_rt(rt2x00dev
, RT3593
))
3224 rt2800_bbp_write(rt2x00dev
, 83, 0x8a);
3228 if (rt2x00_rt(rt2x00dev
, RT3572
))
3229 rt2800_bbp_write(rt2x00dev
, 82, 0x94);
3230 else if (rt2x00_rt(rt2x00dev
, RT3593
))
3231 rt2800_bbp_write(rt2x00dev
, 82, 0x82);
3233 rt2800_bbp_write(rt2x00dev
, 82, 0xf2);
3235 if (rt2x00_rt(rt2x00dev
, RT3593
))
3236 rt2800_bbp_write(rt2x00dev
, 83, 0x9a);
3238 if (rt2x00_has_cap_external_lna_a(rt2x00dev
))
3239 rt2800_bbp_write(rt2x00dev
, 75, 0x46);
3241 rt2800_bbp_write(rt2x00dev
, 75, 0x50);
3244 rt2800_register_read(rt2x00dev
, TX_BAND_CFG
, ®
);
3245 rt2x00_set_field32(®
, TX_BAND_CFG_HT40_MINUS
, conf_is_ht40_minus(conf
));
3246 rt2x00_set_field32(®
, TX_BAND_CFG_A
, rf
->channel
> 14);
3247 rt2x00_set_field32(®
, TX_BAND_CFG_BG
, rf
->channel
<= 14);
3248 rt2800_register_write(rt2x00dev
, TX_BAND_CFG
, reg
);
3250 if (rt2x00_rt(rt2x00dev
, RT3572
))
3251 rt2800_rfcsr_write(rt2x00dev
, 8, 0);
3255 switch (rt2x00dev
->default_ant
.tx_chain_num
) {
3257 /* Turn on tertiary PAs */
3258 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_A2_EN
,
3260 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_G2_EN
,
3264 /* Turn on secondary PAs */
3265 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_A1_EN
,
3267 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_G1_EN
,
3271 /* Turn on primary PAs */
3272 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_A0_EN
,
3274 if (rt2x00_has_cap_bt_coexist(rt2x00dev
))
3275 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_G0_EN
, 1);
3277 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_G0_EN
,
3282 switch (rt2x00dev
->default_ant
.rx_chain_num
) {
3284 /* Turn on tertiary LNAs */
3285 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_LNA_PE_A2_EN
, 1);
3286 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_LNA_PE_G2_EN
, 1);
3289 /* Turn on secondary LNAs */
3290 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_LNA_PE_A1_EN
, 1);
3291 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_LNA_PE_G1_EN
, 1);
3294 /* Turn on primary LNAs */
3295 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_LNA_PE_A0_EN
, 1);
3296 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_LNA_PE_G0_EN
, 1);
3300 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_RFTR_EN
, 1);
3301 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_TRSW_EN
, 1);
3303 rt2800_register_write(rt2x00dev
, TX_PIN_CFG
, tx_pin
);
3305 if (rt2x00_rt(rt2x00dev
, RT3572
)) {
3306 rt2800_rfcsr_write(rt2x00dev
, 8, 0x80);
3309 if (rf
->channel
<= 14)
3310 reg
= 0x1c + (2 * rt2x00dev
->lna_gain
);
3312 reg
= 0x22 + ((rt2x00dev
->lna_gain
* 5) / 3);
3314 rt2800_bbp_write_with_rx_chain(rt2x00dev
, 66, reg
);
3317 if (rt2x00_rt(rt2x00dev
, RT3593
)) {
3318 rt2800_register_read(rt2x00dev
, GPIO_CTRL
, ®
);
3320 /* Band selection */
3321 if (rt2x00_is_usb(rt2x00dev
) ||
3322 rt2x00_is_pcie(rt2x00dev
)) {
3323 /* GPIO #8 controls all paths */
3324 rt2x00_set_field32(®
, GPIO_CTRL_DIR8
, 0);
3325 if (rf
->channel
<= 14)
3326 rt2x00_set_field32(®
, GPIO_CTRL_VAL8
, 1);
3328 rt2x00_set_field32(®
, GPIO_CTRL_VAL8
, 0);
3331 /* LNA PE control. */
3332 if (rt2x00_is_usb(rt2x00dev
)) {
3333 /* GPIO #4 controls PE0 and PE1,
3334 * GPIO #7 controls PE2
3336 rt2x00_set_field32(®
, GPIO_CTRL_DIR4
, 0);
3337 rt2x00_set_field32(®
, GPIO_CTRL_DIR7
, 0);
3339 rt2x00_set_field32(®
, GPIO_CTRL_VAL4
, 1);
3340 rt2x00_set_field32(®
, GPIO_CTRL_VAL7
, 1);
3341 } else if (rt2x00_is_pcie(rt2x00dev
)) {
3342 /* GPIO #4 controls PE0, PE1 and PE2 */
3343 rt2x00_set_field32(®
, GPIO_CTRL_DIR4
, 0);
3344 rt2x00_set_field32(®
, GPIO_CTRL_VAL4
, 1);
3347 rt2800_register_write(rt2x00dev
, GPIO_CTRL
, reg
);
3350 if (rf
->channel
<= 14)
3351 reg
= 0x1c + 2 * rt2x00dev
->lna_gain
;
3353 reg
= 0x22 + ((rt2x00dev
->lna_gain
* 5) / 3);
3355 rt2800_bbp_write_with_rx_chain(rt2x00dev
, 66, reg
);
3357 usleep_range(1000, 1500);
3360 if (rt2x00_rt(rt2x00dev
, RT5592
)) {
3361 rt2800_bbp_write(rt2x00dev
, 195, 141);
3362 rt2800_bbp_write(rt2x00dev
, 196, conf_is_ht40(conf
) ? 0x10 : 0x1a);
3365 reg
= (rf
->channel
<= 14 ? 0x1c : 0x24) + 2 * rt2x00dev
->lna_gain
;
3366 rt2800_bbp_write_with_rx_chain(rt2x00dev
, 66, reg
);
3368 rt2800_iq_calibrate(rt2x00dev
, rf
->channel
);
3371 rt2800_bbp_read(rt2x00dev
, 4, &bbp
);
3372 rt2x00_set_field8(&bbp
, BBP4_BANDWIDTH
, 2 * conf_is_ht40(conf
));
3373 rt2800_bbp_write(rt2x00dev
, 4, bbp
);
3375 rt2800_bbp_read(rt2x00dev
, 3, &bbp
);
3376 rt2x00_set_field8(&bbp
, BBP3_HT40_MINUS
, conf_is_ht40_minus(conf
));
3377 rt2800_bbp_write(rt2x00dev
, 3, bbp
);
3379 if (rt2x00_rt_rev(rt2x00dev
, RT2860
, REV_RT2860C
)) {
3380 if (conf_is_ht40(conf
)) {
3381 rt2800_bbp_write(rt2x00dev
, 69, 0x1a);
3382 rt2800_bbp_write(rt2x00dev
, 70, 0x0a);
3383 rt2800_bbp_write(rt2x00dev
, 73, 0x16);
3385 rt2800_bbp_write(rt2x00dev
, 69, 0x16);
3386 rt2800_bbp_write(rt2x00dev
, 70, 0x08);
3387 rt2800_bbp_write(rt2x00dev
, 73, 0x11);
3394 * Clear channel statistic counters
3396 rt2800_register_read(rt2x00dev
, CH_IDLE_STA
, ®
);
3397 rt2800_register_read(rt2x00dev
, CH_BUSY_STA
, ®
);
3398 rt2800_register_read(rt2x00dev
, CH_BUSY_STA_SEC
, ®
);
3403 if (rt2x00_rt(rt2x00dev
, RT3352
)) {
3404 rt2800_bbp_read(rt2x00dev
, 49, &bbp
);
3405 rt2x00_set_field8(&bbp
, BBP49_UPDATE_FLAG
, 0);
3406 rt2800_bbp_write(rt2x00dev
, 49, bbp
);
3410 static int rt2800_get_gain_calibration_delta(struct rt2x00_dev
*rt2x00dev
)
3419 * First check if temperature compensation is supported.
3421 rt2800_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF1
, &eeprom
);
3422 if (!rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC
))
3426 * Read TSSI boundaries for temperature compensation from
3429 * Array idx 0 1 2 3 4 5 6 7 8
3430 * Matching Delta value -4 -3 -2 -1 0 +1 +2 +3 +4
3431 * Example TSSI bounds 0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
3433 if (rt2x00dev
->curr_band
== IEEE80211_BAND_2GHZ
) {
3434 rt2800_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_BG1
, &eeprom
);
3435 tssi_bounds
[0] = rt2x00_get_field16(eeprom
,
3436 EEPROM_TSSI_BOUND_BG1_MINUS4
);
3437 tssi_bounds
[1] = rt2x00_get_field16(eeprom
,
3438 EEPROM_TSSI_BOUND_BG1_MINUS3
);
3440 rt2800_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_BG2
, &eeprom
);
3441 tssi_bounds
[2] = rt2x00_get_field16(eeprom
,
3442 EEPROM_TSSI_BOUND_BG2_MINUS2
);
3443 tssi_bounds
[3] = rt2x00_get_field16(eeprom
,
3444 EEPROM_TSSI_BOUND_BG2_MINUS1
);
3446 rt2800_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_BG3
, &eeprom
);
3447 tssi_bounds
[4] = rt2x00_get_field16(eeprom
,
3448 EEPROM_TSSI_BOUND_BG3_REF
);
3449 tssi_bounds
[5] = rt2x00_get_field16(eeprom
,
3450 EEPROM_TSSI_BOUND_BG3_PLUS1
);
3452 rt2800_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_BG4
, &eeprom
);
3453 tssi_bounds
[6] = rt2x00_get_field16(eeprom
,
3454 EEPROM_TSSI_BOUND_BG4_PLUS2
);
3455 tssi_bounds
[7] = rt2x00_get_field16(eeprom
,
3456 EEPROM_TSSI_BOUND_BG4_PLUS3
);
3458 rt2800_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_BG5
, &eeprom
);
3459 tssi_bounds
[8] = rt2x00_get_field16(eeprom
,
3460 EEPROM_TSSI_BOUND_BG5_PLUS4
);
3462 step
= rt2x00_get_field16(eeprom
,
3463 EEPROM_TSSI_BOUND_BG5_AGC_STEP
);
3465 rt2800_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_A1
, &eeprom
);
3466 tssi_bounds
[0] = rt2x00_get_field16(eeprom
,
3467 EEPROM_TSSI_BOUND_A1_MINUS4
);
3468 tssi_bounds
[1] = rt2x00_get_field16(eeprom
,
3469 EEPROM_TSSI_BOUND_A1_MINUS3
);
3471 rt2800_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_A2
, &eeprom
);
3472 tssi_bounds
[2] = rt2x00_get_field16(eeprom
,
3473 EEPROM_TSSI_BOUND_A2_MINUS2
);
3474 tssi_bounds
[3] = rt2x00_get_field16(eeprom
,
3475 EEPROM_TSSI_BOUND_A2_MINUS1
);
3477 rt2800_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_A3
, &eeprom
);
3478 tssi_bounds
[4] = rt2x00_get_field16(eeprom
,
3479 EEPROM_TSSI_BOUND_A3_REF
);
3480 tssi_bounds
[5] = rt2x00_get_field16(eeprom
,
3481 EEPROM_TSSI_BOUND_A3_PLUS1
);
3483 rt2800_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_A4
, &eeprom
);
3484 tssi_bounds
[6] = rt2x00_get_field16(eeprom
,
3485 EEPROM_TSSI_BOUND_A4_PLUS2
);
3486 tssi_bounds
[7] = rt2x00_get_field16(eeprom
,
3487 EEPROM_TSSI_BOUND_A4_PLUS3
);
3489 rt2800_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_A5
, &eeprom
);
3490 tssi_bounds
[8] = rt2x00_get_field16(eeprom
,
3491 EEPROM_TSSI_BOUND_A5_PLUS4
);
3493 step
= rt2x00_get_field16(eeprom
,
3494 EEPROM_TSSI_BOUND_A5_AGC_STEP
);
3498 * Check if temperature compensation is supported.
3500 if (tssi_bounds
[4] == 0xff || step
== 0xff)
3504 * Read current TSSI (BBP 49).
3506 rt2800_bbp_read(rt2x00dev
, 49, ¤t_tssi
);
3509 * Compare TSSI value (BBP49) with the compensation boundaries
3510 * from the EEPROM and increase or decrease tx power.
3512 for (i
= 0; i
<= 3; i
++) {
3513 if (current_tssi
> tssi_bounds
[i
])
3518 for (i
= 8; i
>= 5; i
--) {
3519 if (current_tssi
< tssi_bounds
[i
])
3524 return (i
- 4) * step
;
3527 static int rt2800_get_txpower_bw_comp(struct rt2x00_dev
*rt2x00dev
,
3528 enum ieee80211_band band
)
3535 rt2800_eeprom_read(rt2x00dev
, EEPROM_TXPOWER_DELTA
, &eeprom
);
3538 * HT40 compensation not required.
3540 if (eeprom
== 0xffff ||
3541 !test_bit(CONFIG_CHANNEL_HT40
, &rt2x00dev
->flags
))
3544 if (band
== IEEE80211_BAND_2GHZ
) {
3545 comp_en
= rt2x00_get_field16(eeprom
,
3546 EEPROM_TXPOWER_DELTA_ENABLE_2G
);
3548 comp_type
= rt2x00_get_field16(eeprom
,
3549 EEPROM_TXPOWER_DELTA_TYPE_2G
);
3550 comp_value
= rt2x00_get_field16(eeprom
,
3551 EEPROM_TXPOWER_DELTA_VALUE_2G
);
3553 comp_value
= -comp_value
;
3556 comp_en
= rt2x00_get_field16(eeprom
,
3557 EEPROM_TXPOWER_DELTA_ENABLE_5G
);
3559 comp_type
= rt2x00_get_field16(eeprom
,
3560 EEPROM_TXPOWER_DELTA_TYPE_5G
);
3561 comp_value
= rt2x00_get_field16(eeprom
,
3562 EEPROM_TXPOWER_DELTA_VALUE_5G
);
3564 comp_value
= -comp_value
;
3571 static int rt2800_get_txpower_reg_delta(struct rt2x00_dev
*rt2x00dev
,
3572 int power_level
, int max_power
)
3576 if (rt2x00_has_cap_power_limit(rt2x00dev
))
3580 * XXX: We don't know the maximum transmit power of our hardware since
3581 * the EEPROM doesn't expose it. We only know that we are calibrated
3584 * Hence, we assume the regulatory limit that cfg80211 calulated for
3585 * the current channel is our maximum and if we are requested to lower
3586 * the value we just reduce our tx power accordingly.
3588 delta
= power_level
- max_power
;
3589 return min(delta
, 0);
3592 static u8
rt2800_compensate_txpower(struct rt2x00_dev
*rt2x00dev
, int is_rate_b
,
3593 enum ieee80211_band band
, int power_level
,
3594 u8 txpower
, int delta
)
3599 u8 eirp_txpower_criterion
;
3602 if (rt2x00_rt(rt2x00dev
, RT3593
))
3603 return min_t(u8
, txpower
, 0xc);
3605 if (rt2x00_has_cap_power_limit(rt2x00dev
)) {
3607 * Check if eirp txpower exceed txpower_limit.
3608 * We use OFDM 6M as criterion and its eirp txpower
3609 * is stored at EEPROM_EIRP_MAX_TX_POWER.
3610 * .11b data rate need add additional 4dbm
3611 * when calculating eirp txpower.
3613 rt2800_eeprom_read_from_array(rt2x00dev
, EEPROM_TXPOWER_BYRATE
,
3615 criterion
= rt2x00_get_field16(eeprom
,
3616 EEPROM_TXPOWER_BYRATE_RATE0
);
3618 rt2800_eeprom_read(rt2x00dev
, EEPROM_EIRP_MAX_TX_POWER
,
3621 if (band
== IEEE80211_BAND_2GHZ
)
3622 eirp_txpower_criterion
= rt2x00_get_field16(eeprom
,
3623 EEPROM_EIRP_MAX_TX_POWER_2GHZ
);
3625 eirp_txpower_criterion
= rt2x00_get_field16(eeprom
,
3626 EEPROM_EIRP_MAX_TX_POWER_5GHZ
);
3628 eirp_txpower
= eirp_txpower_criterion
+ (txpower
- criterion
) +
3629 (is_rate_b
? 4 : 0) + delta
;
3631 reg_limit
= (eirp_txpower
> power_level
) ?
3632 (eirp_txpower
- power_level
) : 0;
3636 txpower
= max(0, txpower
+ delta
- reg_limit
);
3637 return min_t(u8
, txpower
, 0xc);
3652 TX_PWR_CFG_0_EXT_IDX
,
3653 TX_PWR_CFG_1_EXT_IDX
,
3654 TX_PWR_CFG_2_EXT_IDX
,
3655 TX_PWR_CFG_3_EXT_IDX
,
3656 TX_PWR_CFG_4_EXT_IDX
,
3657 TX_PWR_CFG_IDX_COUNT
,
3660 static void rt2800_config_txpower_rt3593(struct rt2x00_dev
*rt2x00dev
,
3661 struct ieee80211_channel
*chan
,
3666 u32 regs
[TX_PWR_CFG_IDX_COUNT
];
3667 unsigned int offset
;
3668 enum ieee80211_band band
= chan
->band
;
3672 memset(regs
, '\0', sizeof(regs
));
3674 /* TODO: adapt TX power reduction from the rt28xx code */
3676 /* calculate temperature compensation delta */
3677 delta
= rt2800_get_gain_calibration_delta(rt2x00dev
);
3679 if (band
== IEEE80211_BAND_5GHZ
)
3684 if (test_bit(CONFIG_CHANNEL_HT40
, &rt2x00dev
->flags
))
3687 /* read the next four txpower values */
3688 rt2800_eeprom_read_from_array(rt2x00dev
, EEPROM_TXPOWER_BYRATE
,
3692 txpower
= rt2x00_get_field16(eeprom
, EEPROM_TXPOWER_BYRATE_RATE0
);
3693 txpower
= rt2800_compensate_txpower(rt2x00dev
, 1, band
, power_level
,
3695 rt2x00_set_field32(®s
[TX_PWR_CFG_0_IDX
],
3696 TX_PWR_CFG_0_CCK1_CH0
, txpower
);
3697 rt2x00_set_field32(®s
[TX_PWR_CFG_0_IDX
],
3698 TX_PWR_CFG_0_CCK1_CH1
, txpower
);
3699 rt2x00_set_field32(®s
[TX_PWR_CFG_0_EXT_IDX
],
3700 TX_PWR_CFG_0_EXT_CCK1_CH2
, txpower
);
3702 /* CCK 5.5MBS,11MBS */
3703 txpower
= rt2x00_get_field16(eeprom
, EEPROM_TXPOWER_BYRATE_RATE1
);
3704 txpower
= rt2800_compensate_txpower(rt2x00dev
, 1, band
, power_level
,
3706 rt2x00_set_field32(®s
[TX_PWR_CFG_0_IDX
],
3707 TX_PWR_CFG_0_CCK5_CH0
, txpower
);
3708 rt2x00_set_field32(®s
[TX_PWR_CFG_0_IDX
],
3709 TX_PWR_CFG_0_CCK5_CH1
, txpower
);
3710 rt2x00_set_field32(®s
[TX_PWR_CFG_0_EXT_IDX
],
3711 TX_PWR_CFG_0_EXT_CCK5_CH2
, txpower
);
3713 /* OFDM 6MBS,9MBS */
3714 txpower
= rt2x00_get_field16(eeprom
, EEPROM_TXPOWER_BYRATE_RATE2
);
3715 txpower
= rt2800_compensate_txpower(rt2x00dev
, 0, band
, power_level
,
3717 rt2x00_set_field32(®s
[TX_PWR_CFG_0_IDX
],
3718 TX_PWR_CFG_0_OFDM6_CH0
, txpower
);
3719 rt2x00_set_field32(®s
[TX_PWR_CFG_0_IDX
],
3720 TX_PWR_CFG_0_OFDM6_CH1
, txpower
);
3721 rt2x00_set_field32(®s
[TX_PWR_CFG_0_EXT_IDX
],
3722 TX_PWR_CFG_0_EXT_OFDM6_CH2
, txpower
);
3724 /* OFDM 12MBS,18MBS */
3725 txpower
= rt2x00_get_field16(eeprom
, EEPROM_TXPOWER_BYRATE_RATE3
);
3726 txpower
= rt2800_compensate_txpower(rt2x00dev
, 0, band
, power_level
,
3728 rt2x00_set_field32(®s
[TX_PWR_CFG_0_IDX
],
3729 TX_PWR_CFG_0_OFDM12_CH0
, txpower
);
3730 rt2x00_set_field32(®s
[TX_PWR_CFG_0_IDX
],
3731 TX_PWR_CFG_0_OFDM12_CH1
, txpower
);
3732 rt2x00_set_field32(®s
[TX_PWR_CFG_0_EXT_IDX
],
3733 TX_PWR_CFG_0_EXT_OFDM12_CH2
, txpower
);
3735 /* read the next four txpower values */
3736 rt2800_eeprom_read_from_array(rt2x00dev
, EEPROM_TXPOWER_BYRATE
,
3737 offset
+ 1, &eeprom
);
3739 /* OFDM 24MBS,36MBS */
3740 txpower
= rt2x00_get_field16(eeprom
, EEPROM_TXPOWER_BYRATE_RATE0
);
3741 txpower
= rt2800_compensate_txpower(rt2x00dev
, 0, band
, power_level
,
3743 rt2x00_set_field32(®s
[TX_PWR_CFG_1_IDX
],
3744 TX_PWR_CFG_1_OFDM24_CH0
, txpower
);
3745 rt2x00_set_field32(®s
[TX_PWR_CFG_1_IDX
],
3746 TX_PWR_CFG_1_OFDM24_CH1
, txpower
);
3747 rt2x00_set_field32(®s
[TX_PWR_CFG_1_EXT_IDX
],
3748 TX_PWR_CFG_1_EXT_OFDM24_CH2
, txpower
);
3751 txpower
= rt2x00_get_field16(eeprom
, EEPROM_TXPOWER_BYRATE_RATE1
);
3752 txpower
= rt2800_compensate_txpower(rt2x00dev
, 0, band
, power_level
,
3754 rt2x00_set_field32(®s
[TX_PWR_CFG_1_IDX
],
3755 TX_PWR_CFG_1_OFDM48_CH0
, txpower
);
3756 rt2x00_set_field32(®s
[TX_PWR_CFG_1_IDX
],
3757 TX_PWR_CFG_1_OFDM48_CH1
, txpower
);
3758 rt2x00_set_field32(®s
[TX_PWR_CFG_1_EXT_IDX
],
3759 TX_PWR_CFG_1_EXT_OFDM48_CH2
, txpower
);
3762 txpower
= rt2x00_get_field16(eeprom
, EEPROM_TXPOWER_BYRATE_RATE2
);
3763 txpower
= rt2800_compensate_txpower(rt2x00dev
, 0, band
, power_level
,
3765 rt2x00_set_field32(®s
[TX_PWR_CFG_7_IDX
],
3766 TX_PWR_CFG_7_OFDM54_CH0
, txpower
);
3767 rt2x00_set_field32(®s
[TX_PWR_CFG_7_IDX
],
3768 TX_PWR_CFG_7_OFDM54_CH1
, txpower
);
3769 rt2x00_set_field32(®s
[TX_PWR_CFG_7_IDX
],
3770 TX_PWR_CFG_7_OFDM54_CH2
, txpower
);
3772 /* read the next four txpower values */
3773 rt2800_eeprom_read_from_array(rt2x00dev
, EEPROM_TXPOWER_BYRATE
,
3774 offset
+ 2, &eeprom
);
3777 txpower
= rt2x00_get_field16(eeprom
, EEPROM_TXPOWER_BYRATE_RATE0
);
3778 txpower
= rt2800_compensate_txpower(rt2x00dev
, 0, band
, power_level
,
3780 rt2x00_set_field32(®s
[TX_PWR_CFG_1_IDX
],
3781 TX_PWR_CFG_1_MCS0_CH0
, txpower
);
3782 rt2x00_set_field32(®s
[TX_PWR_CFG_1_IDX
],
3783 TX_PWR_CFG_1_MCS0_CH1
, txpower
);
3784 rt2x00_set_field32(®s
[TX_PWR_CFG_1_EXT_IDX
],
3785 TX_PWR_CFG_1_EXT_MCS0_CH2
, txpower
);
3788 txpower
= rt2x00_get_field16(eeprom
, EEPROM_TXPOWER_BYRATE_RATE1
);
3789 txpower
= rt2800_compensate_txpower(rt2x00dev
, 0, band
, power_level
,
3791 rt2x00_set_field32(®s
[TX_PWR_CFG_1_IDX
],
3792 TX_PWR_CFG_1_MCS2_CH0
, txpower
);
3793 rt2x00_set_field32(®s
[TX_PWR_CFG_1_IDX
],
3794 TX_PWR_CFG_1_MCS2_CH1
, txpower
);
3795 rt2x00_set_field32(®s
[TX_PWR_CFG_1_EXT_IDX
],
3796 TX_PWR_CFG_1_EXT_MCS2_CH2
, txpower
);
3799 txpower
= rt2x00_get_field16(eeprom
, EEPROM_TXPOWER_BYRATE_RATE2
);
3800 txpower
= rt2800_compensate_txpower(rt2x00dev
, 0, band
, power_level
,
3802 rt2x00_set_field32(®s
[TX_PWR_CFG_2_IDX
],
3803 TX_PWR_CFG_2_MCS4_CH0
, txpower
);
3804 rt2x00_set_field32(®s
[TX_PWR_CFG_2_IDX
],
3805 TX_PWR_CFG_2_MCS4_CH1
, txpower
);
3806 rt2x00_set_field32(®s
[TX_PWR_CFG_2_EXT_IDX
],
3807 TX_PWR_CFG_2_EXT_MCS4_CH2
, txpower
);
3810 txpower
= rt2x00_get_field16(eeprom
, EEPROM_TXPOWER_BYRATE_RATE3
);
3811 txpower
= rt2800_compensate_txpower(rt2x00dev
, 0, band
, power_level
,
3813 rt2x00_set_field32(®s
[TX_PWR_CFG_2_IDX
],
3814 TX_PWR_CFG_2_MCS6_CH0
, txpower
);
3815 rt2x00_set_field32(®s
[TX_PWR_CFG_2_IDX
],
3816 TX_PWR_CFG_2_MCS6_CH1
, txpower
);
3817 rt2x00_set_field32(®s
[TX_PWR_CFG_2_EXT_IDX
],
3818 TX_PWR_CFG_2_EXT_MCS6_CH2
, txpower
);
3820 /* read the next four txpower values */
3821 rt2800_eeprom_read_from_array(rt2x00dev
, EEPROM_TXPOWER_BYRATE
,
3822 offset
+ 3, &eeprom
);
3825 txpower
= rt2x00_get_field16(eeprom
, EEPROM_TXPOWER_BYRATE_RATE0
);
3826 txpower
= rt2800_compensate_txpower(rt2x00dev
, 0, band
, power_level
,
3828 rt2x00_set_field32(®s
[TX_PWR_CFG_7_IDX
],
3829 TX_PWR_CFG_7_MCS7_CH0
, txpower
);
3830 rt2x00_set_field32(®s
[TX_PWR_CFG_7_IDX
],
3831 TX_PWR_CFG_7_MCS7_CH1
, txpower
);
3832 rt2x00_set_field32(®s
[TX_PWR_CFG_7_IDX
],
3833 TX_PWR_CFG_7_MCS7_CH2
, txpower
);
3836 txpower
= rt2x00_get_field16(eeprom
, EEPROM_TXPOWER_BYRATE_RATE1
);
3837 txpower
= rt2800_compensate_txpower(rt2x00dev
, 0, band
, power_level
,
3839 rt2x00_set_field32(®s
[TX_PWR_CFG_2_IDX
],
3840 TX_PWR_CFG_2_MCS8_CH0
, txpower
);
3841 rt2x00_set_field32(®s
[TX_PWR_CFG_2_IDX
],
3842 TX_PWR_CFG_2_MCS8_CH1
, txpower
);
3843 rt2x00_set_field32(®s
[TX_PWR_CFG_2_EXT_IDX
],
3844 TX_PWR_CFG_2_EXT_MCS8_CH2
, txpower
);
3847 txpower
= rt2x00_get_field16(eeprom
, EEPROM_TXPOWER_BYRATE_RATE2
);
3848 txpower
= rt2800_compensate_txpower(rt2x00dev
, 0, band
, power_level
,
3850 rt2x00_set_field32(®s
[TX_PWR_CFG_2_IDX
],
3851 TX_PWR_CFG_2_MCS10_CH0
, txpower
);
3852 rt2x00_set_field32(®s
[TX_PWR_CFG_2_IDX
],
3853 TX_PWR_CFG_2_MCS10_CH1
, txpower
);
3854 rt2x00_set_field32(®s
[TX_PWR_CFG_2_EXT_IDX
],
3855 TX_PWR_CFG_2_EXT_MCS10_CH2
, txpower
);
3858 txpower
= rt2x00_get_field16(eeprom
, EEPROM_TXPOWER_BYRATE_RATE3
);
3859 txpower
= rt2800_compensate_txpower(rt2x00dev
, 0, band
, power_level
,
3861 rt2x00_set_field32(®s
[TX_PWR_CFG_3_IDX
],
3862 TX_PWR_CFG_3_MCS12_CH0
, txpower
);
3863 rt2x00_set_field32(®s
[TX_PWR_CFG_3_IDX
],
3864 TX_PWR_CFG_3_MCS12_CH1
, txpower
);
3865 rt2x00_set_field32(®s
[TX_PWR_CFG_3_EXT_IDX
],
3866 TX_PWR_CFG_3_EXT_MCS12_CH2
, txpower
);
3868 /* read the next four txpower values */
3869 rt2800_eeprom_read_from_array(rt2x00dev
, EEPROM_TXPOWER_BYRATE
,
3870 offset
+ 4, &eeprom
);
3873 txpower
= rt2x00_get_field16(eeprom
, EEPROM_TXPOWER_BYRATE_RATE0
);
3874 txpower
= rt2800_compensate_txpower(rt2x00dev
, 0, band
, power_level
,
3876 rt2x00_set_field32(®s
[TX_PWR_CFG_3_IDX
],
3877 TX_PWR_CFG_3_MCS14_CH0
, txpower
);
3878 rt2x00_set_field32(®s
[TX_PWR_CFG_3_IDX
],
3879 TX_PWR_CFG_3_MCS14_CH1
, txpower
);
3880 rt2x00_set_field32(®s
[TX_PWR_CFG_3_EXT_IDX
],
3881 TX_PWR_CFG_3_EXT_MCS14_CH2
, txpower
);
3884 txpower
= rt2x00_get_field16(eeprom
, EEPROM_TXPOWER_BYRATE_RATE1
);
3885 txpower
= rt2800_compensate_txpower(rt2x00dev
, 0, band
, power_level
,
3887 rt2x00_set_field32(®s
[TX_PWR_CFG_8_IDX
],
3888 TX_PWR_CFG_8_MCS15_CH0
, txpower
);
3889 rt2x00_set_field32(®s
[TX_PWR_CFG_8_IDX
],
3890 TX_PWR_CFG_8_MCS15_CH1
, txpower
);
3891 rt2x00_set_field32(®s
[TX_PWR_CFG_8_IDX
],
3892 TX_PWR_CFG_8_MCS15_CH2
, txpower
);
3895 txpower
= rt2x00_get_field16(eeprom
, EEPROM_TXPOWER_BYRATE_RATE2
);
3896 txpower
= rt2800_compensate_txpower(rt2x00dev
, 0, band
, power_level
,
3898 rt2x00_set_field32(®s
[TX_PWR_CFG_5_IDX
],
3899 TX_PWR_CFG_5_MCS16_CH0
, txpower
);
3900 rt2x00_set_field32(®s
[TX_PWR_CFG_5_IDX
],
3901 TX_PWR_CFG_5_MCS16_CH1
, txpower
);
3902 rt2x00_set_field32(®s
[TX_PWR_CFG_5_IDX
],
3903 TX_PWR_CFG_5_MCS16_CH2
, txpower
);
3906 txpower
= rt2x00_get_field16(eeprom
, EEPROM_TXPOWER_BYRATE_RATE3
);
3907 txpower
= rt2800_compensate_txpower(rt2x00dev
, 0, band
, power_level
,
3909 rt2x00_set_field32(®s
[TX_PWR_CFG_5_IDX
],
3910 TX_PWR_CFG_5_MCS18_CH0
, txpower
);
3911 rt2x00_set_field32(®s
[TX_PWR_CFG_5_IDX
],
3912 TX_PWR_CFG_5_MCS18_CH1
, txpower
);
3913 rt2x00_set_field32(®s
[TX_PWR_CFG_5_IDX
],
3914 TX_PWR_CFG_5_MCS18_CH2
, txpower
);
3916 /* read the next four txpower values */
3917 rt2800_eeprom_read_from_array(rt2x00dev
, EEPROM_TXPOWER_BYRATE
,
3918 offset
+ 5, &eeprom
);
3921 txpower
= rt2x00_get_field16(eeprom
, EEPROM_TXPOWER_BYRATE_RATE0
);
3922 txpower
= rt2800_compensate_txpower(rt2x00dev
, 0, band
, power_level
,
3924 rt2x00_set_field32(®s
[TX_PWR_CFG_6_IDX
],
3925 TX_PWR_CFG_6_MCS20_CH0
, txpower
);
3926 rt2x00_set_field32(®s
[TX_PWR_CFG_6_IDX
],
3927 TX_PWR_CFG_6_MCS20_CH1
, txpower
);
3928 rt2x00_set_field32(®s
[TX_PWR_CFG_6_IDX
],
3929 TX_PWR_CFG_6_MCS20_CH2
, txpower
);
3932 txpower
= rt2x00_get_field16(eeprom
, EEPROM_TXPOWER_BYRATE_RATE1
);
3933 txpower
= rt2800_compensate_txpower(rt2x00dev
, 0, band
, power_level
,
3935 rt2x00_set_field32(®s
[TX_PWR_CFG_6_IDX
],
3936 TX_PWR_CFG_6_MCS22_CH0
, txpower
);
3937 rt2x00_set_field32(®s
[TX_PWR_CFG_6_IDX
],
3938 TX_PWR_CFG_6_MCS22_CH1
, txpower
);
3939 rt2x00_set_field32(®s
[TX_PWR_CFG_6_IDX
],
3940 TX_PWR_CFG_6_MCS22_CH2
, txpower
);
3943 txpower
= rt2x00_get_field16(eeprom
, EEPROM_TXPOWER_BYRATE_RATE2
);
3944 txpower
= rt2800_compensate_txpower(rt2x00dev
, 0, band
, power_level
,
3946 rt2x00_set_field32(®s
[TX_PWR_CFG_8_IDX
],
3947 TX_PWR_CFG_8_MCS23_CH0
, txpower
);
3948 rt2x00_set_field32(®s
[TX_PWR_CFG_8_IDX
],
3949 TX_PWR_CFG_8_MCS23_CH1
, txpower
);
3950 rt2x00_set_field32(®s
[TX_PWR_CFG_8_IDX
],
3951 TX_PWR_CFG_8_MCS23_CH2
, txpower
);
3953 /* read the next four txpower values */
3954 rt2800_eeprom_read_from_array(rt2x00dev
, EEPROM_TXPOWER_BYRATE
,
3955 offset
+ 6, &eeprom
);
3958 txpower
= rt2x00_get_field16(eeprom
, EEPROM_TXPOWER_BYRATE_RATE0
);
3959 txpower
= rt2800_compensate_txpower(rt2x00dev
, 0, band
, power_level
,
3961 rt2x00_set_field32(®s
[TX_PWR_CFG_3_IDX
],
3962 TX_PWR_CFG_3_STBC0_CH0
, txpower
);
3963 rt2x00_set_field32(®s
[TX_PWR_CFG_3_IDX
],
3964 TX_PWR_CFG_3_STBC0_CH1
, txpower
);
3965 rt2x00_set_field32(®s
[TX_PWR_CFG_3_EXT_IDX
],
3966 TX_PWR_CFG_3_EXT_STBC0_CH2
, txpower
);
3969 txpower
= rt2x00_get_field16(eeprom
, EEPROM_TXPOWER_BYRATE_RATE1
);
3970 txpower
= rt2800_compensate_txpower(rt2x00dev
, 0, band
, power_level
,
3972 rt2x00_set_field32(®s
[TX_PWR_CFG_3_IDX
],
3973 TX_PWR_CFG_3_STBC2_CH0
, txpower
);
3974 rt2x00_set_field32(®s
[TX_PWR_CFG_3_IDX
],
3975 TX_PWR_CFG_3_STBC2_CH1
, txpower
);
3976 rt2x00_set_field32(®s
[TX_PWR_CFG_3_EXT_IDX
],
3977 TX_PWR_CFG_3_EXT_STBC2_CH2
, txpower
);
3980 txpower
= rt2x00_get_field16(eeprom
, EEPROM_TXPOWER_BYRATE_RATE2
);
3981 txpower
= rt2800_compensate_txpower(rt2x00dev
, 0, band
, power_level
,
3983 rt2x00_set_field32(®s
[TX_PWR_CFG_4_IDX
], TX_PWR_CFG_RATE0
, txpower
);
3984 rt2x00_set_field32(®s
[TX_PWR_CFG_4_IDX
], TX_PWR_CFG_RATE1
, txpower
);
3985 rt2x00_set_field32(®s
[TX_PWR_CFG_4_EXT_IDX
], TX_PWR_CFG_RATE0
,
3989 txpower
= rt2x00_get_field16(eeprom
, EEPROM_TXPOWER_BYRATE_RATE3
);
3990 txpower
= rt2800_compensate_txpower(rt2x00dev
, 0, band
, power_level
,
3992 rt2x00_set_field32(®s
[TX_PWR_CFG_4_IDX
], TX_PWR_CFG_RATE2
, txpower
);
3993 rt2x00_set_field32(®s
[TX_PWR_CFG_4_IDX
], TX_PWR_CFG_RATE3
, txpower
);
3994 rt2x00_set_field32(®s
[TX_PWR_CFG_4_EXT_IDX
], TX_PWR_CFG_RATE2
,
3997 /* read the next four txpower values */
3998 rt2800_eeprom_read_from_array(rt2x00dev
, EEPROM_TXPOWER_BYRATE
,
3999 offset
+ 7, &eeprom
);
4002 txpower
= rt2x00_get_field16(eeprom
, EEPROM_TXPOWER_BYRATE_RATE0
);
4003 txpower
= rt2800_compensate_txpower(rt2x00dev
, 0, band
, power_level
,
4005 rt2x00_set_field32(®s
[TX_PWR_CFG_9_IDX
],
4006 TX_PWR_CFG_9_STBC7_CH0
, txpower
);
4007 rt2x00_set_field32(®s
[TX_PWR_CFG_9_IDX
],
4008 TX_PWR_CFG_9_STBC7_CH1
, txpower
);
4009 rt2x00_set_field32(®s
[TX_PWR_CFG_9_IDX
],
4010 TX_PWR_CFG_9_STBC7_CH2
, txpower
);
4012 rt2800_register_write(rt2x00dev
, TX_PWR_CFG_0
, regs
[TX_PWR_CFG_0_IDX
]);
4013 rt2800_register_write(rt2x00dev
, TX_PWR_CFG_1
, regs
[TX_PWR_CFG_1_IDX
]);
4014 rt2800_register_write(rt2x00dev
, TX_PWR_CFG_2
, regs
[TX_PWR_CFG_2_IDX
]);
4015 rt2800_register_write(rt2x00dev
, TX_PWR_CFG_3
, regs
[TX_PWR_CFG_3_IDX
]);
4016 rt2800_register_write(rt2x00dev
, TX_PWR_CFG_4
, regs
[TX_PWR_CFG_4_IDX
]);
4017 rt2800_register_write(rt2x00dev
, TX_PWR_CFG_5
, regs
[TX_PWR_CFG_5_IDX
]);
4018 rt2800_register_write(rt2x00dev
, TX_PWR_CFG_6
, regs
[TX_PWR_CFG_6_IDX
]);
4019 rt2800_register_write(rt2x00dev
, TX_PWR_CFG_7
, regs
[TX_PWR_CFG_7_IDX
]);
4020 rt2800_register_write(rt2x00dev
, TX_PWR_CFG_8
, regs
[TX_PWR_CFG_8_IDX
]);
4021 rt2800_register_write(rt2x00dev
, TX_PWR_CFG_9
, regs
[TX_PWR_CFG_9_IDX
]);
4023 rt2800_register_write(rt2x00dev
, TX_PWR_CFG_0_EXT
,
4024 regs
[TX_PWR_CFG_0_EXT_IDX
]);
4025 rt2800_register_write(rt2x00dev
, TX_PWR_CFG_1_EXT
,
4026 regs
[TX_PWR_CFG_1_EXT_IDX
]);
4027 rt2800_register_write(rt2x00dev
, TX_PWR_CFG_2_EXT
,
4028 regs
[TX_PWR_CFG_2_EXT_IDX
]);
4029 rt2800_register_write(rt2x00dev
, TX_PWR_CFG_3_EXT
,
4030 regs
[TX_PWR_CFG_3_EXT_IDX
]);
4031 rt2800_register_write(rt2x00dev
, TX_PWR_CFG_4_EXT
,
4032 regs
[TX_PWR_CFG_4_EXT_IDX
]);
4034 for (i
= 0; i
< TX_PWR_CFG_IDX_COUNT
; i
++)
4035 rt2x00_dbg(rt2x00dev
,
4036 "band:%cGHz, BW:%c0MHz, TX_PWR_CFG_%d%s = %08lx\n",
4037 (band
== IEEE80211_BAND_5GHZ
) ? '5' : '2',
4038 (test_bit(CONFIG_CHANNEL_HT40
, &rt2x00dev
->flags
)) ?
4040 (i
> TX_PWR_CFG_9_IDX
) ?
4041 (i
- TX_PWR_CFG_9_IDX
- 1) : i
,
4042 (i
> TX_PWR_CFG_9_IDX
) ? "_EXT" : "",
4043 (unsigned long) regs
[i
]);
4047 * We configure transmit power using MAC TX_PWR_CFG_{0,...,N} registers and
4048 * BBP R1 register. TX_PWR_CFG_X allow to configure per rate TX power values,
4049 * 4 bits for each rate (tune from 0 to 15 dBm). BBP_R1 controls transmit power
4050 * for all rates, but allow to set only 4 discrete values: -12, -6, 0 and 6 dBm.
4051 * Reference per rate transmit power values are located in the EEPROM at
4052 * EEPROM_TXPOWER_BYRATE offset. We adjust them and BBP R1 settings according to
4053 * current conditions (i.e. band, bandwidth, temperature, user settings).
4055 static void rt2800_config_txpower_rt28xx(struct rt2x00_dev
*rt2x00dev
,
4056 struct ieee80211_channel
*chan
,
4062 int i
, is_rate_b
, delta
, power_ctrl
;
4063 enum ieee80211_band band
= chan
->band
;
4066 * Calculate HT40 compensation. For 40MHz we need to add or subtract
4067 * value read from EEPROM (different for 2GHz and for 5GHz).
4069 delta
= rt2800_get_txpower_bw_comp(rt2x00dev
, band
);
4072 * Calculate temperature compensation. Depends on measurement of current
4073 * TSSI (Transmitter Signal Strength Indication) we know TX power (due
4074 * to temperature or maybe other factors) is smaller or bigger than
4075 * expected. We adjust it, based on TSSI reference and boundaries values
4076 * provided in EEPROM.
4078 delta
+= rt2800_get_gain_calibration_delta(rt2x00dev
);
4081 * Decrease power according to user settings, on devices with unknown
4082 * maximum tx power. For other devices we take user power_level into
4083 * consideration on rt2800_compensate_txpower().
4085 delta
+= rt2800_get_txpower_reg_delta(rt2x00dev
, power_level
,
4089 * BBP_R1 controls TX power for all rates, it allow to set the following
4090 * gains -12, -6, 0, +6 dBm by setting values 2, 1, 0, 3 respectively.
4092 * TODO: we do not use +6 dBm option to do not increase power beyond
4093 * regulatory limit, however this could be utilized for devices with
4094 * CAPABILITY_POWER_LIMIT.
4096 * TODO: add different temperature compensation code for RT3290 & RT5390
4097 * to allow to use BBP_R1 for those chips.
4099 if (!rt2x00_rt(rt2x00dev
, RT3290
) &&
4100 !rt2x00_rt(rt2x00dev
, RT5390
)) {
4101 rt2800_bbp_read(rt2x00dev
, 1, &r1
);
4105 } else if (delta
<= -6) {
4111 rt2x00_set_field8(&r1
, BBP1_TX_POWER_CTRL
, power_ctrl
);
4112 rt2800_bbp_write(rt2x00dev
, 1, r1
);
4115 offset
= TX_PWR_CFG_0
;
4117 for (i
= 0; i
< EEPROM_TXPOWER_BYRATE_SIZE
; i
+= 2) {
4118 /* just to be safe */
4119 if (offset
> TX_PWR_CFG_4
)
4122 rt2800_register_read(rt2x00dev
, offset
, ®
);
4124 /* read the next four txpower values */
4125 rt2800_eeprom_read_from_array(rt2x00dev
, EEPROM_TXPOWER_BYRATE
,
4128 is_rate_b
= i
? 0 : 1;
4130 * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
4131 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
4132 * TX_PWR_CFG_4: unknown
4134 txpower
= rt2x00_get_field16(eeprom
,
4135 EEPROM_TXPOWER_BYRATE_RATE0
);
4136 txpower
= rt2800_compensate_txpower(rt2x00dev
, is_rate_b
, band
,
4137 power_level
, txpower
, delta
);
4138 rt2x00_set_field32(®
, TX_PWR_CFG_RATE0
, txpower
);
4141 * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
4142 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
4143 * TX_PWR_CFG_4: unknown
4145 txpower
= rt2x00_get_field16(eeprom
,
4146 EEPROM_TXPOWER_BYRATE_RATE1
);
4147 txpower
= rt2800_compensate_txpower(rt2x00dev
, is_rate_b
, band
,
4148 power_level
, txpower
, delta
);
4149 rt2x00_set_field32(®
, TX_PWR_CFG_RATE1
, txpower
);
4152 * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
4153 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14,
4154 * TX_PWR_CFG_4: unknown
4156 txpower
= rt2x00_get_field16(eeprom
,
4157 EEPROM_TXPOWER_BYRATE_RATE2
);
4158 txpower
= rt2800_compensate_txpower(rt2x00dev
, is_rate_b
, band
,
4159 power_level
, txpower
, delta
);
4160 rt2x00_set_field32(®
, TX_PWR_CFG_RATE2
, txpower
);
4163 * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
4164 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15,
4165 * TX_PWR_CFG_4: unknown
4167 txpower
= rt2x00_get_field16(eeprom
,
4168 EEPROM_TXPOWER_BYRATE_RATE3
);
4169 txpower
= rt2800_compensate_txpower(rt2x00dev
, is_rate_b
, band
,
4170 power_level
, txpower
, delta
);
4171 rt2x00_set_field32(®
, TX_PWR_CFG_RATE3
, txpower
);
4173 /* read the next four txpower values */
4174 rt2800_eeprom_read_from_array(rt2x00dev
, EEPROM_TXPOWER_BYRATE
,
4179 * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
4180 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
4181 * TX_PWR_CFG_4: unknown
4183 txpower
= rt2x00_get_field16(eeprom
,
4184 EEPROM_TXPOWER_BYRATE_RATE0
);
4185 txpower
= rt2800_compensate_txpower(rt2x00dev
, is_rate_b
, band
,
4186 power_level
, txpower
, delta
);
4187 rt2x00_set_field32(®
, TX_PWR_CFG_RATE4
, txpower
);
4190 * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
4191 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
4192 * TX_PWR_CFG_4: unknown
4194 txpower
= rt2x00_get_field16(eeprom
,
4195 EEPROM_TXPOWER_BYRATE_RATE1
);
4196 txpower
= rt2800_compensate_txpower(rt2x00dev
, is_rate_b
, band
,
4197 power_level
, txpower
, delta
);
4198 rt2x00_set_field32(®
, TX_PWR_CFG_RATE5
, txpower
);
4201 * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
4202 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
4203 * TX_PWR_CFG_4: unknown
4205 txpower
= rt2x00_get_field16(eeprom
,
4206 EEPROM_TXPOWER_BYRATE_RATE2
);
4207 txpower
= rt2800_compensate_txpower(rt2x00dev
, is_rate_b
, band
,
4208 power_level
, txpower
, delta
);
4209 rt2x00_set_field32(®
, TX_PWR_CFG_RATE6
, txpower
);
4212 * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
4213 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
4214 * TX_PWR_CFG_4: unknown
4216 txpower
= rt2x00_get_field16(eeprom
,
4217 EEPROM_TXPOWER_BYRATE_RATE3
);
4218 txpower
= rt2800_compensate_txpower(rt2x00dev
, is_rate_b
, band
,
4219 power_level
, txpower
, delta
);
4220 rt2x00_set_field32(®
, TX_PWR_CFG_RATE7
, txpower
);
4222 rt2800_register_write(rt2x00dev
, offset
, reg
);
4224 /* next TX_PWR_CFG register */
4229 static void rt2800_config_txpower(struct rt2x00_dev
*rt2x00dev
,
4230 struct ieee80211_channel
*chan
,
4233 if (rt2x00_rt(rt2x00dev
, RT3593
))
4234 rt2800_config_txpower_rt3593(rt2x00dev
, chan
, power_level
);
4236 rt2800_config_txpower_rt28xx(rt2x00dev
, chan
, power_level
);
4239 void rt2800_gain_calibration(struct rt2x00_dev
*rt2x00dev
)
4241 rt2800_config_txpower(rt2x00dev
, rt2x00dev
->hw
->conf
.chandef
.chan
,
4242 rt2x00dev
->tx_power
);
4244 EXPORT_SYMBOL_GPL(rt2800_gain_calibration
);
4246 void rt2800_vco_calibration(struct rt2x00_dev
*rt2x00dev
)
4252 * A voltage-controlled oscillator(VCO) is an electronic oscillator
4253 * designed to be controlled in oscillation frequency by a voltage
4254 * input. Maybe the temperature will affect the frequency of
4255 * oscillation to be shifted. The VCO calibration will be called
4256 * periodically to adjust the frequency to be precision.
4259 rt2800_register_read(rt2x00dev
, TX_PIN_CFG
, &tx_pin
);
4260 tx_pin
&= TX_PIN_CFG_PA_PE_DISABLE
;
4261 rt2800_register_write(rt2x00dev
, TX_PIN_CFG
, tx_pin
);
4263 switch (rt2x00dev
->chip
.rf
) {
4270 rt2800_rfcsr_read(rt2x00dev
, 7, &rfcsr
);
4271 rt2x00_set_field8(&rfcsr
, RFCSR7_RF_TUNING
, 1);
4272 rt2800_rfcsr_write(rt2x00dev
, 7, rfcsr
);
4282 rt2800_rfcsr_read(rt2x00dev
, 3, &rfcsr
);
4283 rt2x00_set_field8(&rfcsr
, RFCSR3_VCOCAL_EN
, 1);
4284 rt2800_rfcsr_write(rt2x00dev
, 3, rfcsr
);
4292 rt2800_register_read(rt2x00dev
, TX_PIN_CFG
, &tx_pin
);
4293 if (rt2x00dev
->rf_channel
<= 14) {
4294 switch (rt2x00dev
->default_ant
.tx_chain_num
) {
4296 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_G2_EN
, 1);
4299 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_G1_EN
, 1);
4303 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_G0_EN
, 1);
4307 switch (rt2x00dev
->default_ant
.tx_chain_num
) {
4309 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_A2_EN
, 1);
4312 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_A1_EN
, 1);
4316 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_A0_EN
, 1);
4320 rt2800_register_write(rt2x00dev
, TX_PIN_CFG
, tx_pin
);
4323 EXPORT_SYMBOL_GPL(rt2800_vco_calibration
);
4325 static void rt2800_config_retry_limit(struct rt2x00_dev
*rt2x00dev
,
4326 struct rt2x00lib_conf
*libconf
)
4330 rt2800_register_read(rt2x00dev
, TX_RTY_CFG
, ®
);
4331 rt2x00_set_field32(®
, TX_RTY_CFG_SHORT_RTY_LIMIT
,
4332 libconf
->conf
->short_frame_max_tx_count
);
4333 rt2x00_set_field32(®
, TX_RTY_CFG_LONG_RTY_LIMIT
,
4334 libconf
->conf
->long_frame_max_tx_count
);
4335 rt2800_register_write(rt2x00dev
, TX_RTY_CFG
, reg
);
4338 static void rt2800_config_ps(struct rt2x00_dev
*rt2x00dev
,
4339 struct rt2x00lib_conf
*libconf
)
4341 enum dev_state state
=
4342 (libconf
->conf
->flags
& IEEE80211_CONF_PS
) ?
4343 STATE_SLEEP
: STATE_AWAKE
;
4346 if (state
== STATE_SLEEP
) {
4347 rt2800_register_write(rt2x00dev
, AUTOWAKEUP_CFG
, 0);
4349 rt2800_register_read(rt2x00dev
, AUTOWAKEUP_CFG
, ®
);
4350 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_AUTO_LEAD_TIME
, 5);
4351 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE
,
4352 libconf
->conf
->listen_interval
- 1);
4353 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_AUTOWAKE
, 1);
4354 rt2800_register_write(rt2x00dev
, AUTOWAKEUP_CFG
, reg
);
4356 rt2x00dev
->ops
->lib
->set_device_state(rt2x00dev
, state
);
4358 rt2800_register_read(rt2x00dev
, AUTOWAKEUP_CFG
, ®
);
4359 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_AUTO_LEAD_TIME
, 0);
4360 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE
, 0);
4361 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_AUTOWAKE
, 0);
4362 rt2800_register_write(rt2x00dev
, AUTOWAKEUP_CFG
, reg
);
4364 rt2x00dev
->ops
->lib
->set_device_state(rt2x00dev
, state
);
4368 void rt2800_config(struct rt2x00_dev
*rt2x00dev
,
4369 struct rt2x00lib_conf
*libconf
,
4370 const unsigned int flags
)
4372 /* Always recalculate LNA gain before changing configuration */
4373 rt2800_config_lna_gain(rt2x00dev
, libconf
);
4375 if (flags
& IEEE80211_CONF_CHANGE_CHANNEL
) {
4376 rt2800_config_channel(rt2x00dev
, libconf
->conf
,
4377 &libconf
->rf
, &libconf
->channel
);
4378 rt2800_config_txpower(rt2x00dev
, libconf
->conf
->chandef
.chan
,
4379 libconf
->conf
->power_level
);
4381 if (flags
& IEEE80211_CONF_CHANGE_POWER
)
4382 rt2800_config_txpower(rt2x00dev
, libconf
->conf
->chandef
.chan
,
4383 libconf
->conf
->power_level
);
4384 if (flags
& IEEE80211_CONF_CHANGE_RETRY_LIMITS
)
4385 rt2800_config_retry_limit(rt2x00dev
, libconf
);
4386 if (flags
& IEEE80211_CONF_CHANGE_PS
)
4387 rt2800_config_ps(rt2x00dev
, libconf
);
4389 EXPORT_SYMBOL_GPL(rt2800_config
);
4394 void rt2800_link_stats(struct rt2x00_dev
*rt2x00dev
, struct link_qual
*qual
)
4399 * Update FCS error count from register.
4401 rt2800_register_read(rt2x00dev
, RX_STA_CNT0
, ®
);
4402 qual
->rx_failed
= rt2x00_get_field32(reg
, RX_STA_CNT0_CRC_ERR
);
4404 EXPORT_SYMBOL_GPL(rt2800_link_stats
);
4406 static u8
rt2800_get_default_vgc(struct rt2x00_dev
*rt2x00dev
)
4410 if (rt2x00dev
->curr_band
== IEEE80211_BAND_2GHZ
) {
4411 if (rt2x00_rt(rt2x00dev
, RT3070
) ||
4412 rt2x00_rt(rt2x00dev
, RT3071
) ||
4413 rt2x00_rt(rt2x00dev
, RT3090
) ||
4414 rt2x00_rt(rt2x00dev
, RT3290
) ||
4415 rt2x00_rt(rt2x00dev
, RT3390
) ||
4416 rt2x00_rt(rt2x00dev
, RT3572
) ||
4417 rt2x00_rt(rt2x00dev
, RT3593
) ||
4418 rt2x00_rt(rt2x00dev
, RT5390
) ||
4419 rt2x00_rt(rt2x00dev
, RT5392
) ||
4420 rt2x00_rt(rt2x00dev
, RT5592
))
4421 vgc
= 0x1c + (2 * rt2x00dev
->lna_gain
);
4423 vgc
= 0x2e + rt2x00dev
->lna_gain
;
4424 } else { /* 5GHZ band */
4425 if (rt2x00_rt(rt2x00dev
, RT3593
))
4426 vgc
= 0x20 + (rt2x00dev
->lna_gain
* 5) / 3;
4427 else if (rt2x00_rt(rt2x00dev
, RT5592
))
4428 vgc
= 0x24 + (2 * rt2x00dev
->lna_gain
);
4430 if (!test_bit(CONFIG_CHANNEL_HT40
, &rt2x00dev
->flags
))
4431 vgc
= 0x32 + (rt2x00dev
->lna_gain
* 5) / 3;
4433 vgc
= 0x3a + (rt2x00dev
->lna_gain
* 5) / 3;
4440 static inline void rt2800_set_vgc(struct rt2x00_dev
*rt2x00dev
,
4441 struct link_qual
*qual
, u8 vgc_level
)
4443 if (qual
->vgc_level
!= vgc_level
) {
4444 if (rt2x00_rt(rt2x00dev
, RT3572
) ||
4445 rt2x00_rt(rt2x00dev
, RT3593
)) {
4446 rt2800_bbp_write_with_rx_chain(rt2x00dev
, 66,
4448 } else if (rt2x00_rt(rt2x00dev
, RT5592
)) {
4449 rt2800_bbp_write(rt2x00dev
, 83, qual
->rssi
> -65 ? 0x4a : 0x7a);
4450 rt2800_bbp_write_with_rx_chain(rt2x00dev
, 66, vgc_level
);
4452 rt2800_bbp_write(rt2x00dev
, 66, vgc_level
);
4455 qual
->vgc_level
= vgc_level
;
4456 qual
->vgc_level_reg
= vgc_level
;
4460 void rt2800_reset_tuner(struct rt2x00_dev
*rt2x00dev
, struct link_qual
*qual
)
4462 rt2800_set_vgc(rt2x00dev
, qual
, rt2800_get_default_vgc(rt2x00dev
));
4464 EXPORT_SYMBOL_GPL(rt2800_reset_tuner
);
4466 void rt2800_link_tuner(struct rt2x00_dev
*rt2x00dev
, struct link_qual
*qual
,
4471 if (rt2x00_rt_rev(rt2x00dev
, RT2860
, REV_RT2860C
))
4474 /* When RSSI is better than a certain threshold, increase VGC
4475 * with a chip specific value in order to improve the balance
4476 * between sensibility and noise isolation.
4479 vgc
= rt2800_get_default_vgc(rt2x00dev
);
4481 switch (rt2x00dev
->chip
.rt
) {
4484 if (qual
->rssi
> -65) {
4485 if (rt2x00dev
->curr_band
== IEEE80211_BAND_2GHZ
)
4493 if (qual
->rssi
> -65)
4498 if (qual
->rssi
> -80)
4503 rt2800_set_vgc(rt2x00dev
, qual
, vgc
);
4505 EXPORT_SYMBOL_GPL(rt2800_link_tuner
);
4508 * Initialization functions.
4510 static int rt2800_init_registers(struct rt2x00_dev
*rt2x00dev
)
4517 rt2800_disable_wpdma(rt2x00dev
);
4519 ret
= rt2800_drv_init_registers(rt2x00dev
);
4523 rt2800_register_read(rt2x00dev
, BCN_OFFSET0
, ®
);
4524 rt2x00_set_field32(®
, BCN_OFFSET0_BCN0
,
4525 rt2800_get_beacon_offset(rt2x00dev
, 0));
4526 rt2x00_set_field32(®
, BCN_OFFSET0_BCN1
,
4527 rt2800_get_beacon_offset(rt2x00dev
, 1));
4528 rt2x00_set_field32(®
, BCN_OFFSET0_BCN2
,
4529 rt2800_get_beacon_offset(rt2x00dev
, 2));
4530 rt2x00_set_field32(®
, BCN_OFFSET0_BCN3
,
4531 rt2800_get_beacon_offset(rt2x00dev
, 3));
4532 rt2800_register_write(rt2x00dev
, BCN_OFFSET0
, reg
);
4534 rt2800_register_read(rt2x00dev
, BCN_OFFSET1
, ®
);
4535 rt2x00_set_field32(®
, BCN_OFFSET1_BCN4
,
4536 rt2800_get_beacon_offset(rt2x00dev
, 4));
4537 rt2x00_set_field32(®
, BCN_OFFSET1_BCN5
,
4538 rt2800_get_beacon_offset(rt2x00dev
, 5));
4539 rt2x00_set_field32(®
, BCN_OFFSET1_BCN6
,
4540 rt2800_get_beacon_offset(rt2x00dev
, 6));
4541 rt2x00_set_field32(®
, BCN_OFFSET1_BCN7
,
4542 rt2800_get_beacon_offset(rt2x00dev
, 7));
4543 rt2800_register_write(rt2x00dev
, BCN_OFFSET1
, reg
);
4545 rt2800_register_write(rt2x00dev
, LEGACY_BASIC_RATE
, 0x0000013f);
4546 rt2800_register_write(rt2x00dev
, HT_BASIC_RATE
, 0x00008003);
4548 rt2800_register_write(rt2x00dev
, MAC_SYS_CTRL
, 0x00000000);
4550 rt2800_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
4551 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_INTERVAL
, 1600);
4552 rt2x00_set_field32(®
, BCN_TIME_CFG_TSF_TICKING
, 0);
4553 rt2x00_set_field32(®
, BCN_TIME_CFG_TSF_SYNC
, 0);
4554 rt2x00_set_field32(®
, BCN_TIME_CFG_TBTT_ENABLE
, 0);
4555 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_GEN
, 0);
4556 rt2x00_set_field32(®
, BCN_TIME_CFG_TX_TIME_COMPENSATE
, 0);
4557 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
4559 rt2800_config_filter(rt2x00dev
, FIF_ALLMULTI
);
4561 rt2800_register_read(rt2x00dev
, BKOFF_SLOT_CFG
, ®
);
4562 rt2x00_set_field32(®
, BKOFF_SLOT_CFG_SLOT_TIME
, 9);
4563 rt2x00_set_field32(®
, BKOFF_SLOT_CFG_CC_DELAY_TIME
, 2);
4564 rt2800_register_write(rt2x00dev
, BKOFF_SLOT_CFG
, reg
);
4566 if (rt2x00_rt(rt2x00dev
, RT3290
)) {
4567 rt2800_register_read(rt2x00dev
, WLAN_FUN_CTRL
, ®
);
4568 if (rt2x00_get_field32(reg
, WLAN_EN
) == 1) {
4569 rt2x00_set_field32(®
, PCIE_APP0_CLK_REQ
, 1);
4570 rt2800_register_write(rt2x00dev
, WLAN_FUN_CTRL
, reg
);
4573 rt2800_register_read(rt2x00dev
, CMB_CTRL
, ®
);
4574 if (!(rt2x00_get_field32(reg
, LDO0_EN
) == 1)) {
4575 rt2x00_set_field32(®
, LDO0_EN
, 1);
4576 rt2x00_set_field32(®
, LDO_BGSEL
, 3);
4577 rt2800_register_write(rt2x00dev
, CMB_CTRL
, reg
);
4580 rt2800_register_read(rt2x00dev
, OSC_CTRL
, ®
);
4581 rt2x00_set_field32(®
, OSC_ROSC_EN
, 1);
4582 rt2x00_set_field32(®
, OSC_CAL_REQ
, 1);
4583 rt2x00_set_field32(®
, OSC_REF_CYCLE
, 0x27);
4584 rt2800_register_write(rt2x00dev
, OSC_CTRL
, reg
);
4586 rt2800_register_read(rt2x00dev
, COEX_CFG0
, ®
);
4587 rt2x00_set_field32(®
, COEX_CFG_ANT
, 0x5e);
4588 rt2800_register_write(rt2x00dev
, COEX_CFG0
, reg
);
4590 rt2800_register_read(rt2x00dev
, COEX_CFG2
, ®
);
4591 rt2x00_set_field32(®
, BT_COEX_CFG1
, 0x00);
4592 rt2x00_set_field32(®
, BT_COEX_CFG0
, 0x17);
4593 rt2x00_set_field32(®
, WL_COEX_CFG1
, 0x93);
4594 rt2x00_set_field32(®
, WL_COEX_CFG0
, 0x7f);
4595 rt2800_register_write(rt2x00dev
, COEX_CFG2
, reg
);
4597 rt2800_register_read(rt2x00dev
, PLL_CTRL
, ®
);
4598 rt2x00_set_field32(®
, PLL_CONTROL
, 1);
4599 rt2800_register_write(rt2x00dev
, PLL_CTRL
, reg
);
4602 if (rt2x00_rt(rt2x00dev
, RT3071
) ||
4603 rt2x00_rt(rt2x00dev
, RT3090
) ||
4604 rt2x00_rt(rt2x00dev
, RT3290
) ||
4605 rt2x00_rt(rt2x00dev
, RT3390
)) {
4607 if (rt2x00_rt(rt2x00dev
, RT3290
))
4608 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
,
4611 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
,
4614 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00000000);
4615 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3071
, REV_RT3071E
) ||
4616 rt2x00_rt_rev_lt(rt2x00dev
, RT3090
, REV_RT3090E
) ||
4617 rt2x00_rt_rev_lt(rt2x00dev
, RT3390
, REV_RT3390E
)) {
4618 rt2800_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF1
,
4620 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF1_DAC_TEST
))
4621 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
,
4624 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
,
4627 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
, 0x00000000);
4629 } else if (rt2x00_rt(rt2x00dev
, RT3070
)) {
4630 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000400);
4632 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070F
)) {
4633 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00000000);
4634 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
, 0x0000002c);
4636 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00080606);
4637 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
, 0x00000000);
4639 } else if (rt2800_is_305x_soc(rt2x00dev
)) {
4640 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000400);
4641 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00000000);
4642 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
, 0x00000030);
4643 } else if (rt2x00_rt(rt2x00dev
, RT3352
)) {
4644 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000402);
4645 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00080606);
4646 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
, 0x00000000);
4647 } else if (rt2x00_rt(rt2x00dev
, RT3572
)) {
4648 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000400);
4649 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00080606);
4650 } else if (rt2x00_rt(rt2x00dev
, RT3593
)) {
4651 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000402);
4652 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00000000);
4653 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3593
, REV_RT3593E
)) {
4654 rt2800_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF1
,
4656 if (rt2x00_get_field16(eeprom
,
4657 EEPROM_NIC_CONF1_DAC_TEST
))
4658 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
,
4661 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
,
4664 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
,
4667 } else if (rt2x00_rt(rt2x00dev
, RT5390
) ||
4668 rt2x00_rt(rt2x00dev
, RT5392
) ||
4669 rt2x00_rt(rt2x00dev
, RT5592
)) {
4670 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000404);
4671 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00080606);
4672 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
, 0x00000000);
4674 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000000);
4675 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00080606);
4678 rt2800_register_read(rt2x00dev
, TX_LINK_CFG
, ®
);
4679 rt2x00_set_field32(®
, TX_LINK_CFG_REMOTE_MFB_LIFETIME
, 32);
4680 rt2x00_set_field32(®
, TX_LINK_CFG_MFB_ENABLE
, 0);
4681 rt2x00_set_field32(®
, TX_LINK_CFG_REMOTE_UMFS_ENABLE
, 0);
4682 rt2x00_set_field32(®
, TX_LINK_CFG_TX_MRQ_EN
, 0);
4683 rt2x00_set_field32(®
, TX_LINK_CFG_TX_RDG_EN
, 0);
4684 rt2x00_set_field32(®
, TX_LINK_CFG_TX_CF_ACK_EN
, 1);
4685 rt2x00_set_field32(®
, TX_LINK_CFG_REMOTE_MFB
, 0);
4686 rt2x00_set_field32(®
, TX_LINK_CFG_REMOTE_MFS
, 0);
4687 rt2800_register_write(rt2x00dev
, TX_LINK_CFG
, reg
);
4689 rt2800_register_read(rt2x00dev
, TX_TIMEOUT_CFG
, ®
);
4690 rt2x00_set_field32(®
, TX_TIMEOUT_CFG_MPDU_LIFETIME
, 9);
4691 rt2x00_set_field32(®
, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT
, 32);
4692 rt2x00_set_field32(®
, TX_TIMEOUT_CFG_TX_OP_TIMEOUT
, 10);
4693 rt2800_register_write(rt2x00dev
, TX_TIMEOUT_CFG
, reg
);
4695 rt2800_register_read(rt2x00dev
, MAX_LEN_CFG
, ®
);
4696 rt2x00_set_field32(®
, MAX_LEN_CFG_MAX_MPDU
, AGGREGATION_SIZE
);
4697 if (rt2x00_rt_rev_gte(rt2x00dev
, RT2872
, REV_RT2872E
) ||
4698 rt2x00_rt(rt2x00dev
, RT2883
) ||
4699 rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070E
))
4700 rt2x00_set_field32(®
, MAX_LEN_CFG_MAX_PSDU
, 2);
4702 rt2x00_set_field32(®
, MAX_LEN_CFG_MAX_PSDU
, 1);
4703 rt2x00_set_field32(®
, MAX_LEN_CFG_MIN_PSDU
, 0);
4704 rt2x00_set_field32(®
, MAX_LEN_CFG_MIN_MPDU
, 0);
4705 rt2800_register_write(rt2x00dev
, MAX_LEN_CFG
, reg
);
4707 rt2800_register_read(rt2x00dev
, LED_CFG
, ®
);
4708 rt2x00_set_field32(®
, LED_CFG_ON_PERIOD
, 70);
4709 rt2x00_set_field32(®
, LED_CFG_OFF_PERIOD
, 30);
4710 rt2x00_set_field32(®
, LED_CFG_SLOW_BLINK_PERIOD
, 3);
4711 rt2x00_set_field32(®
, LED_CFG_R_LED_MODE
, 3);
4712 rt2x00_set_field32(®
, LED_CFG_G_LED_MODE
, 3);
4713 rt2x00_set_field32(®
, LED_CFG_Y_LED_MODE
, 3);
4714 rt2x00_set_field32(®
, LED_CFG_LED_POLAR
, 1);
4715 rt2800_register_write(rt2x00dev
, LED_CFG
, reg
);
4717 rt2800_register_write(rt2x00dev
, PBF_MAX_PCNT
, 0x1f3fbf9f);
4719 rt2800_register_read(rt2x00dev
, TX_RTY_CFG
, ®
);
4720 rt2x00_set_field32(®
, TX_RTY_CFG_SHORT_RTY_LIMIT
, 15);
4721 rt2x00_set_field32(®
, TX_RTY_CFG_LONG_RTY_LIMIT
, 31);
4722 rt2x00_set_field32(®
, TX_RTY_CFG_LONG_RTY_THRE
, 2000);
4723 rt2x00_set_field32(®
, TX_RTY_CFG_NON_AGG_RTY_MODE
, 0);
4724 rt2x00_set_field32(®
, TX_RTY_CFG_AGG_RTY_MODE
, 0);
4725 rt2x00_set_field32(®
, TX_RTY_CFG_TX_AUTO_FB_ENABLE
, 1);
4726 rt2800_register_write(rt2x00dev
, TX_RTY_CFG
, reg
);
4728 rt2800_register_read(rt2x00dev
, AUTO_RSP_CFG
, ®
);
4729 rt2x00_set_field32(®
, AUTO_RSP_CFG_AUTORESPONDER
, 1);
4730 rt2x00_set_field32(®
, AUTO_RSP_CFG_BAC_ACK_POLICY
, 1);
4731 rt2x00_set_field32(®
, AUTO_RSP_CFG_CTS_40_MMODE
, 0);
4732 rt2x00_set_field32(®
, AUTO_RSP_CFG_CTS_40_MREF
, 0);
4733 rt2x00_set_field32(®
, AUTO_RSP_CFG_AR_PREAMBLE
, 1);
4734 rt2x00_set_field32(®
, AUTO_RSP_CFG_DUAL_CTS_EN
, 0);
4735 rt2x00_set_field32(®
, AUTO_RSP_CFG_ACK_CTS_PSM_BIT
, 0);
4736 rt2800_register_write(rt2x00dev
, AUTO_RSP_CFG
, reg
);
4738 rt2800_register_read(rt2x00dev
, CCK_PROT_CFG
, ®
);
4739 rt2x00_set_field32(®
, CCK_PROT_CFG_PROTECT_RATE
, 3);
4740 rt2x00_set_field32(®
, CCK_PROT_CFG_PROTECT_CTRL
, 0);
4741 rt2x00_set_field32(®
, CCK_PROT_CFG_PROTECT_NAV_SHORT
, 1);
4742 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
4743 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
4744 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
4745 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_MM40
, 0);
4746 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
4747 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_GF40
, 0);
4748 rt2x00_set_field32(®
, CCK_PROT_CFG_RTS_TH_EN
, 1);
4749 rt2800_register_write(rt2x00dev
, CCK_PROT_CFG
, reg
);
4751 rt2800_register_read(rt2x00dev
, OFDM_PROT_CFG
, ®
);
4752 rt2x00_set_field32(®
, OFDM_PROT_CFG_PROTECT_RATE
, 3);
4753 rt2x00_set_field32(®
, OFDM_PROT_CFG_PROTECT_CTRL
, 0);
4754 rt2x00_set_field32(®
, OFDM_PROT_CFG_PROTECT_NAV_SHORT
, 1);
4755 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
4756 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
4757 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
4758 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_MM40
, 0);
4759 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
4760 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_GF40
, 0);
4761 rt2x00_set_field32(®
, OFDM_PROT_CFG_RTS_TH_EN
, 1);
4762 rt2800_register_write(rt2x00dev
, OFDM_PROT_CFG
, reg
);
4764 rt2800_register_read(rt2x00dev
, MM20_PROT_CFG
, ®
);
4765 rt2x00_set_field32(®
, MM20_PROT_CFG_PROTECT_RATE
, 0x4004);
4766 rt2x00_set_field32(®
, MM20_PROT_CFG_PROTECT_CTRL
, 0);
4767 rt2x00_set_field32(®
, MM20_PROT_CFG_PROTECT_NAV_SHORT
, 1);
4768 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
4769 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
4770 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
4771 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_MM40
, 0);
4772 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
4773 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_GF40
, 0);
4774 rt2x00_set_field32(®
, MM20_PROT_CFG_RTS_TH_EN
, 0);
4775 rt2800_register_write(rt2x00dev
, MM20_PROT_CFG
, reg
);
4777 rt2800_register_read(rt2x00dev
, MM40_PROT_CFG
, ®
);
4778 rt2x00_set_field32(®
, MM40_PROT_CFG_PROTECT_RATE
, 0x4084);
4779 rt2x00_set_field32(®
, MM40_PROT_CFG_PROTECT_CTRL
, 0);
4780 rt2x00_set_field32(®
, MM40_PROT_CFG_PROTECT_NAV_SHORT
, 1);
4781 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
4782 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
4783 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
4784 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_MM40
, 1);
4785 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
4786 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_GF40
, 1);
4787 rt2x00_set_field32(®
, MM40_PROT_CFG_RTS_TH_EN
, 0);
4788 rt2800_register_write(rt2x00dev
, MM40_PROT_CFG
, reg
);
4790 rt2800_register_read(rt2x00dev
, GF20_PROT_CFG
, ®
);
4791 rt2x00_set_field32(®
, GF20_PROT_CFG_PROTECT_RATE
, 0x4004);
4792 rt2x00_set_field32(®
, GF20_PROT_CFG_PROTECT_CTRL
, 0);
4793 rt2x00_set_field32(®
, GF20_PROT_CFG_PROTECT_NAV_SHORT
, 1);
4794 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
4795 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
4796 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
4797 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_MM40
, 0);
4798 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
4799 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_GF40
, 0);
4800 rt2x00_set_field32(®
, GF20_PROT_CFG_RTS_TH_EN
, 0);
4801 rt2800_register_write(rt2x00dev
, GF20_PROT_CFG
, reg
);
4803 rt2800_register_read(rt2x00dev
, GF40_PROT_CFG
, ®
);
4804 rt2x00_set_field32(®
, GF40_PROT_CFG_PROTECT_RATE
, 0x4084);
4805 rt2x00_set_field32(®
, GF40_PROT_CFG_PROTECT_CTRL
, 0);
4806 rt2x00_set_field32(®
, GF40_PROT_CFG_PROTECT_NAV_SHORT
, 1);
4807 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
4808 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
4809 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
4810 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_MM40
, 1);
4811 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
4812 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_GF40
, 1);
4813 rt2x00_set_field32(®
, GF40_PROT_CFG_RTS_TH_EN
, 0);
4814 rt2800_register_write(rt2x00dev
, GF40_PROT_CFG
, reg
);
4816 if (rt2x00_is_usb(rt2x00dev
)) {
4817 rt2800_register_write(rt2x00dev
, PBF_CFG
, 0xf40006);
4819 rt2800_register_read(rt2x00dev
, WPDMA_GLO_CFG
, ®
);
4820 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_TX_DMA
, 0);
4821 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_DMA_BUSY
, 0);
4822 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_RX_DMA
, 0);
4823 rt2x00_set_field32(®
, WPDMA_GLO_CFG_RX_DMA_BUSY
, 0);
4824 rt2x00_set_field32(®
, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE
, 3);
4825 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_WRITEBACK_DONE
, 0);
4826 rt2x00_set_field32(®
, WPDMA_GLO_CFG_BIG_ENDIAN
, 0);
4827 rt2x00_set_field32(®
, WPDMA_GLO_CFG_RX_HDR_SCATTER
, 0);
4828 rt2x00_set_field32(®
, WPDMA_GLO_CFG_HDR_SEG_LEN
, 0);
4829 rt2800_register_write(rt2x00dev
, WPDMA_GLO_CFG
, reg
);
4833 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
4834 * although it is reserved.
4836 rt2800_register_read(rt2x00dev
, TXOP_CTRL_CFG
, ®
);
4837 rt2x00_set_field32(®
, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN
, 1);
4838 rt2x00_set_field32(®
, TXOP_CTRL_CFG_AC_TRUN_EN
, 1);
4839 rt2x00_set_field32(®
, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN
, 1);
4840 rt2x00_set_field32(®
, TXOP_CTRL_CFG_USER_MODE_TRUN_EN
, 1);
4841 rt2x00_set_field32(®
, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN
, 1);
4842 rt2x00_set_field32(®
, TXOP_CTRL_CFG_RESERVED_TRUN_EN
, 1);
4843 rt2x00_set_field32(®
, TXOP_CTRL_CFG_LSIG_TXOP_EN
, 0);
4844 rt2x00_set_field32(®
, TXOP_CTRL_CFG_EXT_CCA_EN
, 0);
4845 rt2x00_set_field32(®
, TXOP_CTRL_CFG_EXT_CCA_DLY
, 88);
4846 rt2x00_set_field32(®
, TXOP_CTRL_CFG_EXT_CWMIN
, 0);
4847 rt2800_register_write(rt2x00dev
, TXOP_CTRL_CFG
, reg
);
4849 reg
= rt2x00_rt(rt2x00dev
, RT5592
) ? 0x00000082 : 0x00000002;
4850 rt2800_register_write(rt2x00dev
, TXOP_HLDR_ET
, reg
);
4852 rt2800_register_read(rt2x00dev
, TX_RTS_CFG
, ®
);
4853 rt2x00_set_field32(®
, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT
, 32);
4854 rt2x00_set_field32(®
, TX_RTS_CFG_RTS_THRES
,
4855 IEEE80211_MAX_RTS_THRESHOLD
);
4856 rt2x00_set_field32(®
, TX_RTS_CFG_RTS_FBK_EN
, 0);
4857 rt2800_register_write(rt2x00dev
, TX_RTS_CFG
, reg
);
4859 rt2800_register_write(rt2x00dev
, EXP_ACK_TIME
, 0x002400ca);
4862 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
4863 * time should be set to 16. However, the original Ralink driver uses
4864 * 16 for both and indeed using a value of 10 for CCK SIFS results in
4865 * connection problems with 11g + CTS protection. Hence, use the same
4866 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
4868 rt2800_register_read(rt2x00dev
, XIFS_TIME_CFG
, ®
);
4869 rt2x00_set_field32(®
, XIFS_TIME_CFG_CCKM_SIFS_TIME
, 16);
4870 rt2x00_set_field32(®
, XIFS_TIME_CFG_OFDM_SIFS_TIME
, 16);
4871 rt2x00_set_field32(®
, XIFS_TIME_CFG_OFDM_XIFS_TIME
, 4);
4872 rt2x00_set_field32(®
, XIFS_TIME_CFG_EIFS
, 314);
4873 rt2x00_set_field32(®
, XIFS_TIME_CFG_BB_RXEND_ENABLE
, 1);
4874 rt2800_register_write(rt2x00dev
, XIFS_TIME_CFG
, reg
);
4876 rt2800_register_write(rt2x00dev
, PWR_PIN_CFG
, 0x00000003);
4879 * ASIC will keep garbage value after boot, clear encryption keys.
4881 for (i
= 0; i
< 4; i
++)
4882 rt2800_register_write(rt2x00dev
,
4883 SHARED_KEY_MODE_ENTRY(i
), 0);
4885 for (i
= 0; i
< 256; i
++) {
4886 rt2800_config_wcid(rt2x00dev
, NULL
, i
);
4887 rt2800_delete_wcid_attr(rt2x00dev
, i
);
4888 rt2800_register_write(rt2x00dev
, MAC_IVEIV_ENTRY(i
), 0);
4894 for (i
= 0; i
< 8; i
++)
4895 rt2800_clear_beacon_register(rt2x00dev
, i
);
4897 if (rt2x00_is_usb(rt2x00dev
)) {
4898 rt2800_register_read(rt2x00dev
, US_CYC_CNT
, ®
);
4899 rt2x00_set_field32(®
, US_CYC_CNT_CLOCK_CYCLE
, 30);
4900 rt2800_register_write(rt2x00dev
, US_CYC_CNT
, reg
);
4901 } else if (rt2x00_is_pcie(rt2x00dev
)) {
4902 rt2800_register_read(rt2x00dev
, US_CYC_CNT
, ®
);
4903 rt2x00_set_field32(®
, US_CYC_CNT_CLOCK_CYCLE
, 125);
4904 rt2800_register_write(rt2x00dev
, US_CYC_CNT
, reg
);
4907 rt2800_register_read(rt2x00dev
, HT_FBK_CFG0
, ®
);
4908 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS0FBK
, 0);
4909 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS1FBK
, 0);
4910 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS2FBK
, 1);
4911 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS3FBK
, 2);
4912 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS4FBK
, 3);
4913 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS5FBK
, 4);
4914 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS6FBK
, 5);
4915 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS7FBK
, 6);
4916 rt2800_register_write(rt2x00dev
, HT_FBK_CFG0
, reg
);
4918 rt2800_register_read(rt2x00dev
, HT_FBK_CFG1
, ®
);
4919 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS8FBK
, 8);
4920 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS9FBK
, 8);
4921 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS10FBK
, 9);
4922 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS11FBK
, 10);
4923 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS12FBK
, 11);
4924 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS13FBK
, 12);
4925 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS14FBK
, 13);
4926 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS15FBK
, 14);
4927 rt2800_register_write(rt2x00dev
, HT_FBK_CFG1
, reg
);
4929 rt2800_register_read(rt2x00dev
, LG_FBK_CFG0
, ®
);
4930 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS0FBK
, 8);
4931 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS1FBK
, 8);
4932 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS2FBK
, 9);
4933 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS3FBK
, 10);
4934 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS4FBK
, 11);
4935 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS5FBK
, 12);
4936 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS6FBK
, 13);
4937 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS7FBK
, 14);
4938 rt2800_register_write(rt2x00dev
, LG_FBK_CFG0
, reg
);
4940 rt2800_register_read(rt2x00dev
, LG_FBK_CFG1
, ®
);
4941 rt2x00_set_field32(®
, LG_FBK_CFG0_CCKMCS0FBK
, 0);
4942 rt2x00_set_field32(®
, LG_FBK_CFG0_CCKMCS1FBK
, 0);
4943 rt2x00_set_field32(®
, LG_FBK_CFG0_CCKMCS2FBK
, 1);
4944 rt2x00_set_field32(®
, LG_FBK_CFG0_CCKMCS3FBK
, 2);
4945 rt2800_register_write(rt2x00dev
, LG_FBK_CFG1
, reg
);
4948 * Do not force the BA window size, we use the TXWI to set it
4950 rt2800_register_read(rt2x00dev
, AMPDU_BA_WINSIZE
, ®
);
4951 rt2x00_set_field32(®
, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE
, 0);
4952 rt2x00_set_field32(®
, AMPDU_BA_WINSIZE_FORCE_WINSIZE
, 0);
4953 rt2800_register_write(rt2x00dev
, AMPDU_BA_WINSIZE
, reg
);
4956 * We must clear the error counters.
4957 * These registers are cleared on read,
4958 * so we may pass a useless variable to store the value.
4960 rt2800_register_read(rt2x00dev
, RX_STA_CNT0
, ®
);
4961 rt2800_register_read(rt2x00dev
, RX_STA_CNT1
, ®
);
4962 rt2800_register_read(rt2x00dev
, RX_STA_CNT2
, ®
);
4963 rt2800_register_read(rt2x00dev
, TX_STA_CNT0
, ®
);
4964 rt2800_register_read(rt2x00dev
, TX_STA_CNT1
, ®
);
4965 rt2800_register_read(rt2x00dev
, TX_STA_CNT2
, ®
);
4968 * Setup leadtime for pre tbtt interrupt to 6ms
4970 rt2800_register_read(rt2x00dev
, INT_TIMER_CFG
, ®
);
4971 rt2x00_set_field32(®
, INT_TIMER_CFG_PRE_TBTT_TIMER
, 6 << 4);
4972 rt2800_register_write(rt2x00dev
, INT_TIMER_CFG
, reg
);
4975 * Set up channel statistics timer
4977 rt2800_register_read(rt2x00dev
, CH_TIME_CFG
, ®
);
4978 rt2x00_set_field32(®
, CH_TIME_CFG_EIFS_BUSY
, 1);
4979 rt2x00_set_field32(®
, CH_TIME_CFG_NAV_BUSY
, 1);
4980 rt2x00_set_field32(®
, CH_TIME_CFG_RX_BUSY
, 1);
4981 rt2x00_set_field32(®
, CH_TIME_CFG_TX_BUSY
, 1);
4982 rt2x00_set_field32(®
, CH_TIME_CFG_TMR_EN
, 1);
4983 rt2800_register_write(rt2x00dev
, CH_TIME_CFG
, reg
);
4988 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev
*rt2x00dev
)
4993 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
4994 rt2800_register_read(rt2x00dev
, MAC_STATUS_CFG
, ®
);
4995 if (!rt2x00_get_field32(reg
, MAC_STATUS_CFG_BBP_RF_BUSY
))
4998 udelay(REGISTER_BUSY_DELAY
);
5001 rt2x00_err(rt2x00dev
, "BBP/RF register access failed, aborting\n");
5005 static int rt2800_wait_bbp_ready(struct rt2x00_dev
*rt2x00dev
)
5011 * BBP was enabled after firmware was loaded,
5012 * but we need to reactivate it now.
5014 rt2800_register_write(rt2x00dev
, H2M_BBP_AGENT
, 0);
5015 rt2800_register_write(rt2x00dev
, H2M_MAILBOX_CSR
, 0);
5018 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
5019 rt2800_bbp_read(rt2x00dev
, 0, &value
);
5020 if ((value
!= 0xff) && (value
!= 0x00))
5022 udelay(REGISTER_BUSY_DELAY
);
5025 rt2x00_err(rt2x00dev
, "BBP register access failed, aborting\n");
5029 static void rt2800_bbp4_mac_if_ctrl(struct rt2x00_dev
*rt2x00dev
)
5033 rt2800_bbp_read(rt2x00dev
, 4, &value
);
5034 rt2x00_set_field8(&value
, BBP4_MAC_IF_CTRL
, 1);
5035 rt2800_bbp_write(rt2x00dev
, 4, value
);
5038 static void rt2800_init_freq_calibration(struct rt2x00_dev
*rt2x00dev
)
5040 rt2800_bbp_write(rt2x00dev
, 142, 1);
5041 rt2800_bbp_write(rt2x00dev
, 143, 57);
5044 static void rt2800_init_bbp_5592_glrt(struct rt2x00_dev
*rt2x00dev
)
5046 const u8 glrt_table
[] = {
5047 0xE0, 0x1F, 0X38, 0x32, 0x08, 0x28, 0x19, 0x0A, 0xFF, 0x00, /* 128 ~ 137 */
5048 0x16, 0x10, 0x10, 0x0B, 0x36, 0x2C, 0x26, 0x24, 0x42, 0x36, /* 138 ~ 147 */
5049 0x30, 0x2D, 0x4C, 0x46, 0x3D, 0x40, 0x3E, 0x42, 0x3D, 0x40, /* 148 ~ 157 */
5050 0X3C, 0x34, 0x2C, 0x2F, 0x3C, 0x35, 0x2E, 0x2A, 0x49, 0x41, /* 158 ~ 167 */
5051 0x36, 0x31, 0x30, 0x30, 0x0E, 0x0D, 0x28, 0x21, 0x1C, 0x16, /* 168 ~ 177 */
5052 0x50, 0x4A, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, /* 178 ~ 187 */
5053 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 188 ~ 197 */
5054 0x00, 0x00, 0x7D, 0x14, 0x32, 0x2C, 0x36, 0x4C, 0x43, 0x2C, /* 198 ~ 207 */
5055 0x2E, 0x36, 0x30, 0x6E, /* 208 ~ 211 */
5059 for (i
= 0; i
< ARRAY_SIZE(glrt_table
); i
++) {
5060 rt2800_bbp_write(rt2x00dev
, 195, 128 + i
);
5061 rt2800_bbp_write(rt2x00dev
, 196, glrt_table
[i
]);
5065 static void rt2800_init_bbp_early(struct rt2x00_dev
*rt2x00dev
)
5067 rt2800_bbp_write(rt2x00dev
, 65, 0x2C);
5068 rt2800_bbp_write(rt2x00dev
, 66, 0x38);
5069 rt2800_bbp_write(rt2x00dev
, 68, 0x0B);
5070 rt2800_bbp_write(rt2x00dev
, 69, 0x12);
5071 rt2800_bbp_write(rt2x00dev
, 70, 0x0a);
5072 rt2800_bbp_write(rt2x00dev
, 73, 0x10);
5073 rt2800_bbp_write(rt2x00dev
, 81, 0x37);
5074 rt2800_bbp_write(rt2x00dev
, 82, 0x62);
5075 rt2800_bbp_write(rt2x00dev
, 83, 0x6A);
5076 rt2800_bbp_write(rt2x00dev
, 84, 0x99);
5077 rt2800_bbp_write(rt2x00dev
, 86, 0x00);
5078 rt2800_bbp_write(rt2x00dev
, 91, 0x04);
5079 rt2800_bbp_write(rt2x00dev
, 92, 0x00);
5080 rt2800_bbp_write(rt2x00dev
, 103, 0x00);
5081 rt2800_bbp_write(rt2x00dev
, 105, 0x05);
5082 rt2800_bbp_write(rt2x00dev
, 106, 0x35);
5085 static void rt2800_disable_unused_dac_adc(struct rt2x00_dev
*rt2x00dev
)
5090 rt2800_bbp_read(rt2x00dev
, 138, &value
);
5091 rt2800_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF0
, &eeprom
);
5092 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_TXPATH
) == 1)
5094 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_RXPATH
) == 1)
5096 rt2800_bbp_write(rt2x00dev
, 138, value
);
5099 static void rt2800_init_bbp_305x_soc(struct rt2x00_dev
*rt2x00dev
)
5101 rt2800_bbp_write(rt2x00dev
, 31, 0x08);
5103 rt2800_bbp_write(rt2x00dev
, 65, 0x2c);
5104 rt2800_bbp_write(rt2x00dev
, 66, 0x38);
5106 rt2800_bbp_write(rt2x00dev
, 69, 0x12);
5107 rt2800_bbp_write(rt2x00dev
, 73, 0x10);
5109 rt2800_bbp_write(rt2x00dev
, 70, 0x0a);
5111 rt2800_bbp_write(rt2x00dev
, 78, 0x0e);
5112 rt2800_bbp_write(rt2x00dev
, 80, 0x08);
5114 rt2800_bbp_write(rt2x00dev
, 82, 0x62);
5116 rt2800_bbp_write(rt2x00dev
, 83, 0x6a);
5118 rt2800_bbp_write(rt2x00dev
, 84, 0x99);
5120 rt2800_bbp_write(rt2x00dev
, 86, 0x00);
5122 rt2800_bbp_write(rt2x00dev
, 91, 0x04);
5124 rt2800_bbp_write(rt2x00dev
, 92, 0x00);
5126 rt2800_bbp_write(rt2x00dev
, 103, 0xc0);
5128 rt2800_bbp_write(rt2x00dev
, 105, 0x01);
5130 rt2800_bbp_write(rt2x00dev
, 106, 0x35);
5133 static void rt2800_init_bbp_28xx(struct rt2x00_dev
*rt2x00dev
)
5135 rt2800_bbp_write(rt2x00dev
, 65, 0x2c);
5136 rt2800_bbp_write(rt2x00dev
, 66, 0x38);
5138 if (rt2x00_rt_rev(rt2x00dev
, RT2860
, REV_RT2860C
)) {
5139 rt2800_bbp_write(rt2x00dev
, 69, 0x16);
5140 rt2800_bbp_write(rt2x00dev
, 73, 0x12);
5142 rt2800_bbp_write(rt2x00dev
, 69, 0x12);
5143 rt2800_bbp_write(rt2x00dev
, 73, 0x10);
5146 rt2800_bbp_write(rt2x00dev
, 70, 0x0a);
5148 rt2800_bbp_write(rt2x00dev
, 81, 0x37);
5150 rt2800_bbp_write(rt2x00dev
, 82, 0x62);
5152 rt2800_bbp_write(rt2x00dev
, 83, 0x6a);
5154 if (rt2x00_rt_rev(rt2x00dev
, RT2860
, REV_RT2860D
))
5155 rt2800_bbp_write(rt2x00dev
, 84, 0x19);
5157 rt2800_bbp_write(rt2x00dev
, 84, 0x99);
5159 rt2800_bbp_write(rt2x00dev
, 86, 0x00);
5161 rt2800_bbp_write(rt2x00dev
, 91, 0x04);
5163 rt2800_bbp_write(rt2x00dev
, 92, 0x00);
5165 rt2800_bbp_write(rt2x00dev
, 103, 0x00);
5167 rt2800_bbp_write(rt2x00dev
, 105, 0x05);
5169 rt2800_bbp_write(rt2x00dev
, 106, 0x35);
5172 static void rt2800_init_bbp_30xx(struct rt2x00_dev
*rt2x00dev
)
5174 rt2800_bbp_write(rt2x00dev
, 65, 0x2c);
5175 rt2800_bbp_write(rt2x00dev
, 66, 0x38);
5177 rt2800_bbp_write(rt2x00dev
, 69, 0x12);
5178 rt2800_bbp_write(rt2x00dev
, 73, 0x10);
5180 rt2800_bbp_write(rt2x00dev
, 70, 0x0a);
5182 rt2800_bbp_write(rt2x00dev
, 79, 0x13);
5183 rt2800_bbp_write(rt2x00dev
, 80, 0x05);
5184 rt2800_bbp_write(rt2x00dev
, 81, 0x33);
5186 rt2800_bbp_write(rt2x00dev
, 82, 0x62);
5188 rt2800_bbp_write(rt2x00dev
, 83, 0x6a);
5190 rt2800_bbp_write(rt2x00dev
, 84, 0x99);
5192 rt2800_bbp_write(rt2x00dev
, 86, 0x00);
5194 rt2800_bbp_write(rt2x00dev
, 91, 0x04);
5196 rt2800_bbp_write(rt2x00dev
, 92, 0x00);
5198 if (rt2x00_rt_rev_gte(rt2x00dev
, RT3070
, REV_RT3070F
) ||
5199 rt2x00_rt_rev_gte(rt2x00dev
, RT3071
, REV_RT3071E
) ||
5200 rt2x00_rt_rev_gte(rt2x00dev
, RT3090
, REV_RT3090E
))
5201 rt2800_bbp_write(rt2x00dev
, 103, 0xc0);
5203 rt2800_bbp_write(rt2x00dev
, 103, 0x00);
5205 rt2800_bbp_write(rt2x00dev
, 105, 0x05);
5207 rt2800_bbp_write(rt2x00dev
, 106, 0x35);
5209 if (rt2x00_rt(rt2x00dev
, RT3071
) ||
5210 rt2x00_rt(rt2x00dev
, RT3090
))
5211 rt2800_disable_unused_dac_adc(rt2x00dev
);
5214 static void rt2800_init_bbp_3290(struct rt2x00_dev
*rt2x00dev
)
5218 rt2800_bbp4_mac_if_ctrl(rt2x00dev
);
5220 rt2800_bbp_write(rt2x00dev
, 31, 0x08);
5222 rt2800_bbp_write(rt2x00dev
, 65, 0x2c);
5223 rt2800_bbp_write(rt2x00dev
, 66, 0x38);
5225 rt2800_bbp_write(rt2x00dev
, 68, 0x0b);
5227 rt2800_bbp_write(rt2x00dev
, 69, 0x12);
5228 rt2800_bbp_write(rt2x00dev
, 73, 0x13);
5229 rt2800_bbp_write(rt2x00dev
, 75, 0x46);
5230 rt2800_bbp_write(rt2x00dev
, 76, 0x28);
5232 rt2800_bbp_write(rt2x00dev
, 77, 0x58);
5234 rt2800_bbp_write(rt2x00dev
, 70, 0x0a);
5236 rt2800_bbp_write(rt2x00dev
, 74, 0x0b);
5237 rt2800_bbp_write(rt2x00dev
, 79, 0x18);
5238 rt2800_bbp_write(rt2x00dev
, 80, 0x09);
5239 rt2800_bbp_write(rt2x00dev
, 81, 0x33);
5241 rt2800_bbp_write(rt2x00dev
, 82, 0x62);
5243 rt2800_bbp_write(rt2x00dev
, 83, 0x7a);
5245 rt2800_bbp_write(rt2x00dev
, 84, 0x9a);
5247 rt2800_bbp_write(rt2x00dev
, 86, 0x38);
5249 rt2800_bbp_write(rt2x00dev
, 91, 0x04);
5251 rt2800_bbp_write(rt2x00dev
, 92, 0x02);
5253 rt2800_bbp_write(rt2x00dev
, 103, 0xc0);
5255 rt2800_bbp_write(rt2x00dev
, 104, 0x92);
5257 rt2800_bbp_write(rt2x00dev
, 105, 0x1c);
5259 rt2800_bbp_write(rt2x00dev
, 106, 0x03);
5261 rt2800_bbp_write(rt2x00dev
, 128, 0x12);
5263 rt2800_bbp_write(rt2x00dev
, 67, 0x24);
5264 rt2800_bbp_write(rt2x00dev
, 143, 0x04);
5265 rt2800_bbp_write(rt2x00dev
, 142, 0x99);
5266 rt2800_bbp_write(rt2x00dev
, 150, 0x30);
5267 rt2800_bbp_write(rt2x00dev
, 151, 0x2e);
5268 rt2800_bbp_write(rt2x00dev
, 152, 0x20);
5269 rt2800_bbp_write(rt2x00dev
, 153, 0x34);
5270 rt2800_bbp_write(rt2x00dev
, 154, 0x40);
5271 rt2800_bbp_write(rt2x00dev
, 155, 0x3b);
5272 rt2800_bbp_write(rt2x00dev
, 253, 0x04);
5274 rt2800_bbp_read(rt2x00dev
, 47, &value
);
5275 rt2x00_set_field8(&value
, BBP47_TSSI_ADC6
, 1);
5276 rt2800_bbp_write(rt2x00dev
, 47, value
);
5278 /* Use 5-bit ADC for Acquisition and 8-bit ADC for data */
5279 rt2800_bbp_read(rt2x00dev
, 3, &value
);
5280 rt2x00_set_field8(&value
, BBP3_ADC_MODE_SWITCH
, 1);
5281 rt2x00_set_field8(&value
, BBP3_ADC_INIT_MODE
, 1);
5282 rt2800_bbp_write(rt2x00dev
, 3, value
);
5285 static void rt2800_init_bbp_3352(struct rt2x00_dev
*rt2x00dev
)
5287 rt2800_bbp_write(rt2x00dev
, 3, 0x00);
5288 rt2800_bbp_write(rt2x00dev
, 4, 0x50);
5290 rt2800_bbp_write(rt2x00dev
, 31, 0x08);
5292 rt2800_bbp_write(rt2x00dev
, 47, 0x48);
5294 rt2800_bbp_write(rt2x00dev
, 65, 0x2c);
5295 rt2800_bbp_write(rt2x00dev
, 66, 0x38);
5297 rt2800_bbp_write(rt2x00dev
, 68, 0x0b);
5299 rt2800_bbp_write(rt2x00dev
, 69, 0x12);
5300 rt2800_bbp_write(rt2x00dev
, 73, 0x13);
5301 rt2800_bbp_write(rt2x00dev
, 75, 0x46);
5302 rt2800_bbp_write(rt2x00dev
, 76, 0x28);
5304 rt2800_bbp_write(rt2x00dev
, 77, 0x59);
5306 rt2800_bbp_write(rt2x00dev
, 70, 0x0a);
5308 rt2800_bbp_write(rt2x00dev
, 78, 0x0e);
5309 rt2800_bbp_write(rt2x00dev
, 80, 0x08);
5310 rt2800_bbp_write(rt2x00dev
, 81, 0x37);
5312 rt2800_bbp_write(rt2x00dev
, 82, 0x62);
5314 rt2800_bbp_write(rt2x00dev
, 83, 0x6a);
5316 rt2800_bbp_write(rt2x00dev
, 84, 0x99);
5318 rt2800_bbp_write(rt2x00dev
, 86, 0x38);
5320 rt2800_bbp_write(rt2x00dev
, 88, 0x90);
5322 rt2800_bbp_write(rt2x00dev
, 91, 0x04);
5324 rt2800_bbp_write(rt2x00dev
, 92, 0x02);
5326 rt2800_bbp_write(rt2x00dev
, 103, 0xc0);
5328 rt2800_bbp_write(rt2x00dev
, 104, 0x92);
5330 rt2800_bbp_write(rt2x00dev
, 105, 0x34);
5332 rt2800_bbp_write(rt2x00dev
, 106, 0x05);
5334 rt2800_bbp_write(rt2x00dev
, 120, 0x50);
5336 rt2800_bbp_write(rt2x00dev
, 137, 0x0f);
5338 rt2800_bbp_write(rt2x00dev
, 163, 0xbd);
5339 /* Set ITxBF timeout to 0x9c40=1000msec */
5340 rt2800_bbp_write(rt2x00dev
, 179, 0x02);
5341 rt2800_bbp_write(rt2x00dev
, 180, 0x00);
5342 rt2800_bbp_write(rt2x00dev
, 182, 0x40);
5343 rt2800_bbp_write(rt2x00dev
, 180, 0x01);
5344 rt2800_bbp_write(rt2x00dev
, 182, 0x9c);
5345 rt2800_bbp_write(rt2x00dev
, 179, 0x00);
5346 /* Reprogram the inband interface to put right values in RXWI */
5347 rt2800_bbp_write(rt2x00dev
, 142, 0x04);
5348 rt2800_bbp_write(rt2x00dev
, 143, 0x3b);
5349 rt2800_bbp_write(rt2x00dev
, 142, 0x06);
5350 rt2800_bbp_write(rt2x00dev
, 143, 0xa0);
5351 rt2800_bbp_write(rt2x00dev
, 142, 0x07);
5352 rt2800_bbp_write(rt2x00dev
, 143, 0xa1);
5353 rt2800_bbp_write(rt2x00dev
, 142, 0x08);
5354 rt2800_bbp_write(rt2x00dev
, 143, 0xa2);
5356 rt2800_bbp_write(rt2x00dev
, 148, 0xc8);
5359 static void rt2800_init_bbp_3390(struct rt2x00_dev
*rt2x00dev
)
5361 rt2800_bbp_write(rt2x00dev
, 65, 0x2c);
5362 rt2800_bbp_write(rt2x00dev
, 66, 0x38);
5364 rt2800_bbp_write(rt2x00dev
, 69, 0x12);
5365 rt2800_bbp_write(rt2x00dev
, 73, 0x10);
5367 rt2800_bbp_write(rt2x00dev
, 70, 0x0a);
5369 rt2800_bbp_write(rt2x00dev
, 79, 0x13);
5370 rt2800_bbp_write(rt2x00dev
, 80, 0x05);
5371 rt2800_bbp_write(rt2x00dev
, 81, 0x33);
5373 rt2800_bbp_write(rt2x00dev
, 82, 0x62);
5375 rt2800_bbp_write(rt2x00dev
, 83, 0x6a);
5377 rt2800_bbp_write(rt2x00dev
, 84, 0x99);
5379 rt2800_bbp_write(rt2x00dev
, 86, 0x00);
5381 rt2800_bbp_write(rt2x00dev
, 91, 0x04);
5383 rt2800_bbp_write(rt2x00dev
, 92, 0x00);
5385 if (rt2x00_rt_rev_gte(rt2x00dev
, RT3390
, REV_RT3390E
))
5386 rt2800_bbp_write(rt2x00dev
, 103, 0xc0);
5388 rt2800_bbp_write(rt2x00dev
, 103, 0x00);
5390 rt2800_bbp_write(rt2x00dev
, 105, 0x05);
5392 rt2800_bbp_write(rt2x00dev
, 106, 0x35);
5394 rt2800_disable_unused_dac_adc(rt2x00dev
);
5397 static void rt2800_init_bbp_3572(struct rt2x00_dev
*rt2x00dev
)
5399 rt2800_bbp_write(rt2x00dev
, 31, 0x08);
5401 rt2800_bbp_write(rt2x00dev
, 65, 0x2c);
5402 rt2800_bbp_write(rt2x00dev
, 66, 0x38);
5404 rt2800_bbp_write(rt2x00dev
, 69, 0x12);
5405 rt2800_bbp_write(rt2x00dev
, 73, 0x10);
5407 rt2800_bbp_write(rt2x00dev
, 70, 0x0a);
5409 rt2800_bbp_write(rt2x00dev
, 79, 0x13);
5410 rt2800_bbp_write(rt2x00dev
, 80, 0x05);
5411 rt2800_bbp_write(rt2x00dev
, 81, 0x33);
5413 rt2800_bbp_write(rt2x00dev
, 82, 0x62);
5415 rt2800_bbp_write(rt2x00dev
, 83, 0x6a);
5417 rt2800_bbp_write(rt2x00dev
, 84, 0x99);
5419 rt2800_bbp_write(rt2x00dev
, 86, 0x00);
5421 rt2800_bbp_write(rt2x00dev
, 91, 0x04);
5423 rt2800_bbp_write(rt2x00dev
, 92, 0x00);
5425 rt2800_bbp_write(rt2x00dev
, 103, 0xc0);
5427 rt2800_bbp_write(rt2x00dev
, 105, 0x05);
5429 rt2800_bbp_write(rt2x00dev
, 106, 0x35);
5431 rt2800_disable_unused_dac_adc(rt2x00dev
);
5434 static void rt2800_init_bbp_3593(struct rt2x00_dev
*rt2x00dev
)
5436 rt2800_init_bbp_early(rt2x00dev
);
5438 rt2800_bbp_write(rt2x00dev
, 79, 0x13);
5439 rt2800_bbp_write(rt2x00dev
, 80, 0x05);
5440 rt2800_bbp_write(rt2x00dev
, 81, 0x33);
5441 rt2800_bbp_write(rt2x00dev
, 137, 0x0f);
5443 rt2800_bbp_write(rt2x00dev
, 84, 0x19);
5445 /* Enable DC filter */
5446 if (rt2x00_rt_rev_gte(rt2x00dev
, RT3593
, REV_RT3593E
))
5447 rt2800_bbp_write(rt2x00dev
, 103, 0xc0);
5450 static void rt2800_init_bbp_53xx(struct rt2x00_dev
*rt2x00dev
)
5456 rt2800_bbp4_mac_if_ctrl(rt2x00dev
);
5458 rt2800_bbp_write(rt2x00dev
, 31, 0x08);
5460 rt2800_bbp_write(rt2x00dev
, 65, 0x2c);
5461 rt2800_bbp_write(rt2x00dev
, 66, 0x38);
5463 rt2800_bbp_write(rt2x00dev
, 68, 0x0b);
5465 rt2800_bbp_write(rt2x00dev
, 69, 0x12);
5466 rt2800_bbp_write(rt2x00dev
, 73, 0x13);
5467 rt2800_bbp_write(rt2x00dev
, 75, 0x46);
5468 rt2800_bbp_write(rt2x00dev
, 76, 0x28);
5470 rt2800_bbp_write(rt2x00dev
, 77, 0x59);
5472 rt2800_bbp_write(rt2x00dev
, 70, 0x0a);
5474 rt2800_bbp_write(rt2x00dev
, 79, 0x13);
5475 rt2800_bbp_write(rt2x00dev
, 80, 0x05);
5476 rt2800_bbp_write(rt2x00dev
, 81, 0x33);
5478 rt2800_bbp_write(rt2x00dev
, 82, 0x62);
5480 rt2800_bbp_write(rt2x00dev
, 83, 0x7a);
5482 rt2800_bbp_write(rt2x00dev
, 84, 0x9a);
5484 rt2800_bbp_write(rt2x00dev
, 86, 0x38);
5486 if (rt2x00_rt(rt2x00dev
, RT5392
))
5487 rt2800_bbp_write(rt2x00dev
, 88, 0x90);
5489 rt2800_bbp_write(rt2x00dev
, 91, 0x04);
5491 rt2800_bbp_write(rt2x00dev
, 92, 0x02);
5493 if (rt2x00_rt(rt2x00dev
, RT5392
)) {
5494 rt2800_bbp_write(rt2x00dev
, 95, 0x9a);
5495 rt2800_bbp_write(rt2x00dev
, 98, 0x12);
5498 rt2800_bbp_write(rt2x00dev
, 103, 0xc0);
5500 rt2800_bbp_write(rt2x00dev
, 104, 0x92);
5502 rt2800_bbp_write(rt2x00dev
, 105, 0x3c);
5504 if (rt2x00_rt(rt2x00dev
, RT5390
))
5505 rt2800_bbp_write(rt2x00dev
, 106, 0x03);
5506 else if (rt2x00_rt(rt2x00dev
, RT5392
))
5507 rt2800_bbp_write(rt2x00dev
, 106, 0x12);
5511 rt2800_bbp_write(rt2x00dev
, 128, 0x12);
5513 if (rt2x00_rt(rt2x00dev
, RT5392
)) {
5514 rt2800_bbp_write(rt2x00dev
, 134, 0xd0);
5515 rt2800_bbp_write(rt2x00dev
, 135, 0xf6);
5518 rt2800_disable_unused_dac_adc(rt2x00dev
);
5520 rt2800_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF1
, &eeprom
);
5521 div_mode
= rt2x00_get_field16(eeprom
,
5522 EEPROM_NIC_CONF1_ANT_DIVERSITY
);
5523 ant
= (div_mode
== 3) ? 1 : 0;
5525 /* check if this is a Bluetooth combo card */
5526 if (rt2x00_has_cap_bt_coexist(rt2x00dev
)) {
5529 rt2800_register_read(rt2x00dev
, GPIO_CTRL
, ®
);
5530 rt2x00_set_field32(®
, GPIO_CTRL_DIR3
, 0);
5531 rt2x00_set_field32(®
, GPIO_CTRL_DIR6
, 0);
5532 rt2x00_set_field32(®
, GPIO_CTRL_VAL3
, 0);
5533 rt2x00_set_field32(®
, GPIO_CTRL_VAL6
, 0);
5535 rt2x00_set_field32(®
, GPIO_CTRL_VAL3
, 1);
5537 rt2x00_set_field32(®
, GPIO_CTRL_VAL6
, 1);
5538 rt2800_register_write(rt2x00dev
, GPIO_CTRL
, reg
);
5541 /* This chip has hardware antenna diversity*/
5542 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390R
)) {
5543 rt2800_bbp_write(rt2x00dev
, 150, 0); /* Disable Antenna Software OFDM */
5544 rt2800_bbp_write(rt2x00dev
, 151, 0); /* Disable Antenna Software CCK */
5545 rt2800_bbp_write(rt2x00dev
, 154, 0); /* Clear previously selected antenna */
5548 rt2800_bbp_read(rt2x00dev
, 152, &value
);
5550 rt2x00_set_field8(&value
, BBP152_RX_DEFAULT_ANT
, 1);
5552 rt2x00_set_field8(&value
, BBP152_RX_DEFAULT_ANT
, 0);
5553 rt2800_bbp_write(rt2x00dev
, 152, value
);
5555 rt2800_init_freq_calibration(rt2x00dev
);
5558 static void rt2800_init_bbp_5592(struct rt2x00_dev
*rt2x00dev
)
5564 rt2800_init_bbp_early(rt2x00dev
);
5566 rt2800_bbp_read(rt2x00dev
, 105, &value
);
5567 rt2x00_set_field8(&value
, BBP105_MLD
,
5568 rt2x00dev
->default_ant
.rx_chain_num
== 2);
5569 rt2800_bbp_write(rt2x00dev
, 105, value
);
5571 rt2800_bbp4_mac_if_ctrl(rt2x00dev
);
5573 rt2800_bbp_write(rt2x00dev
, 20, 0x06);
5574 rt2800_bbp_write(rt2x00dev
, 31, 0x08);
5575 rt2800_bbp_write(rt2x00dev
, 65, 0x2C);
5576 rt2800_bbp_write(rt2x00dev
, 68, 0xDD);
5577 rt2800_bbp_write(rt2x00dev
, 69, 0x1A);
5578 rt2800_bbp_write(rt2x00dev
, 70, 0x05);
5579 rt2800_bbp_write(rt2x00dev
, 73, 0x13);
5580 rt2800_bbp_write(rt2x00dev
, 74, 0x0F);
5581 rt2800_bbp_write(rt2x00dev
, 75, 0x4F);
5582 rt2800_bbp_write(rt2x00dev
, 76, 0x28);
5583 rt2800_bbp_write(rt2x00dev
, 77, 0x59);
5584 rt2800_bbp_write(rt2x00dev
, 84, 0x9A);
5585 rt2800_bbp_write(rt2x00dev
, 86, 0x38);
5586 rt2800_bbp_write(rt2x00dev
, 88, 0x90);
5587 rt2800_bbp_write(rt2x00dev
, 91, 0x04);
5588 rt2800_bbp_write(rt2x00dev
, 92, 0x02);
5589 rt2800_bbp_write(rt2x00dev
, 95, 0x9a);
5590 rt2800_bbp_write(rt2x00dev
, 98, 0x12);
5591 rt2800_bbp_write(rt2x00dev
, 103, 0xC0);
5592 rt2800_bbp_write(rt2x00dev
, 104, 0x92);
5593 /* FIXME BBP105 owerwrite */
5594 rt2800_bbp_write(rt2x00dev
, 105, 0x3C);
5595 rt2800_bbp_write(rt2x00dev
, 106, 0x35);
5596 rt2800_bbp_write(rt2x00dev
, 128, 0x12);
5597 rt2800_bbp_write(rt2x00dev
, 134, 0xD0);
5598 rt2800_bbp_write(rt2x00dev
, 135, 0xF6);
5599 rt2800_bbp_write(rt2x00dev
, 137, 0x0F);
5601 /* Initialize GLRT (Generalized Likehood Radio Test) */
5602 rt2800_init_bbp_5592_glrt(rt2x00dev
);
5604 rt2800_bbp4_mac_if_ctrl(rt2x00dev
);
5606 rt2800_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF1
, &eeprom
);
5607 div_mode
= rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF1_ANT_DIVERSITY
);
5608 ant
= (div_mode
== 3) ? 1 : 0;
5609 rt2800_bbp_read(rt2x00dev
, 152, &value
);
5612 rt2x00_set_field8(&value
, BBP152_RX_DEFAULT_ANT
, 1);
5614 /* Auxiliary antenna */
5615 rt2x00_set_field8(&value
, BBP152_RX_DEFAULT_ANT
, 0);
5617 rt2800_bbp_write(rt2x00dev
, 152, value
);
5619 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5592
, REV_RT5592C
)) {
5620 rt2800_bbp_read(rt2x00dev
, 254, &value
);
5621 rt2x00_set_field8(&value
, BBP254_BIT7
, 1);
5622 rt2800_bbp_write(rt2x00dev
, 254, value
);
5625 rt2800_init_freq_calibration(rt2x00dev
);
5627 rt2800_bbp_write(rt2x00dev
, 84, 0x19);
5628 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5592
, REV_RT5592C
))
5629 rt2800_bbp_write(rt2x00dev
, 103, 0xc0);
5632 static void rt2800_init_bbp(struct rt2x00_dev
*rt2x00dev
)
5639 if (rt2800_is_305x_soc(rt2x00dev
))
5640 rt2800_init_bbp_305x_soc(rt2x00dev
);
5642 switch (rt2x00dev
->chip
.rt
) {
5646 rt2800_init_bbp_28xx(rt2x00dev
);
5651 rt2800_init_bbp_30xx(rt2x00dev
);
5654 rt2800_init_bbp_3290(rt2x00dev
);
5657 rt2800_init_bbp_3352(rt2x00dev
);
5660 rt2800_init_bbp_3390(rt2x00dev
);
5663 rt2800_init_bbp_3572(rt2x00dev
);
5666 rt2800_init_bbp_3593(rt2x00dev
);
5670 rt2800_init_bbp_53xx(rt2x00dev
);
5673 rt2800_init_bbp_5592(rt2x00dev
);
5677 for (i
= 0; i
< EEPROM_BBP_SIZE
; i
++) {
5678 rt2800_eeprom_read_from_array(rt2x00dev
, EEPROM_BBP_START
, i
,
5681 if (eeprom
!= 0xffff && eeprom
!= 0x0000) {
5682 reg_id
= rt2x00_get_field16(eeprom
, EEPROM_BBP_REG_ID
);
5683 value
= rt2x00_get_field16(eeprom
, EEPROM_BBP_VALUE
);
5684 rt2800_bbp_write(rt2x00dev
, reg_id
, value
);
5689 static void rt2800_led_open_drain_enable(struct rt2x00_dev
*rt2x00dev
)
5693 rt2800_register_read(rt2x00dev
, OPT_14_CSR
, ®
);
5694 rt2x00_set_field32(®
, OPT_14_CSR_BIT0
, 1);
5695 rt2800_register_write(rt2x00dev
, OPT_14_CSR
, reg
);
5698 static u8
rt2800_init_rx_filter(struct rt2x00_dev
*rt2x00dev
, bool bw40
,
5707 u8 rfcsr24
= (bw40
) ? 0x27 : 0x07;
5709 rt2800_rfcsr_write(rt2x00dev
, 24, rfcsr24
);
5711 rt2800_bbp_read(rt2x00dev
, 4, &bbp
);
5712 rt2x00_set_field8(&bbp
, BBP4_BANDWIDTH
, 2 * bw40
);
5713 rt2800_bbp_write(rt2x00dev
, 4, bbp
);
5715 rt2800_rfcsr_read(rt2x00dev
, 31, &rfcsr
);
5716 rt2x00_set_field8(&rfcsr
, RFCSR31_RX_H20M
, bw40
);
5717 rt2800_rfcsr_write(rt2x00dev
, 31, rfcsr
);
5719 rt2800_rfcsr_read(rt2x00dev
, 22, &rfcsr
);
5720 rt2x00_set_field8(&rfcsr
, RFCSR22_BASEBAND_LOOPBACK
, 1);
5721 rt2800_rfcsr_write(rt2x00dev
, 22, rfcsr
);
5724 * Set power & frequency of passband test tone
5726 rt2800_bbp_write(rt2x00dev
, 24, 0);
5728 for (i
= 0; i
< 100; i
++) {
5729 rt2800_bbp_write(rt2x00dev
, 25, 0x90);
5732 rt2800_bbp_read(rt2x00dev
, 55, &passband
);
5738 * Set power & frequency of stopband test tone
5740 rt2800_bbp_write(rt2x00dev
, 24, 0x06);
5742 for (i
= 0; i
< 100; i
++) {
5743 rt2800_bbp_write(rt2x00dev
, 25, 0x90);
5746 rt2800_bbp_read(rt2x00dev
, 55, &stopband
);
5748 if ((passband
- stopband
) <= filter_target
) {
5750 overtuned
+= ((passband
- stopband
) == filter_target
);
5754 rt2800_rfcsr_write(rt2x00dev
, 24, rfcsr24
);
5757 rfcsr24
-= !!overtuned
;
5759 rt2800_rfcsr_write(rt2x00dev
, 24, rfcsr24
);
5763 static void rt2800_rf_init_calibration(struct rt2x00_dev
*rt2x00dev
,
5764 const unsigned int rf_reg
)
5768 rt2800_rfcsr_read(rt2x00dev
, rf_reg
, &rfcsr
);
5769 rt2x00_set_field8(&rfcsr
, FIELD8(0x80), 1);
5770 rt2800_rfcsr_write(rt2x00dev
, rf_reg
, rfcsr
);
5772 rt2x00_set_field8(&rfcsr
, FIELD8(0x80), 0);
5773 rt2800_rfcsr_write(rt2x00dev
, rf_reg
, rfcsr
);
5776 static void rt2800_rx_filter_calibration(struct rt2x00_dev
*rt2x00dev
)
5778 struct rt2800_drv_data
*drv_data
= rt2x00dev
->drv_data
;
5784 * TODO: sync filter_tgt values with vendor driver
5786 if (rt2x00_rt(rt2x00dev
, RT3070
)) {
5787 filter_tgt_bw20
= 0x16;
5788 filter_tgt_bw40
= 0x19;
5790 filter_tgt_bw20
= 0x13;
5791 filter_tgt_bw40
= 0x15;
5794 drv_data
->calibration_bw20
=
5795 rt2800_init_rx_filter(rt2x00dev
, false, filter_tgt_bw20
);
5796 drv_data
->calibration_bw40
=
5797 rt2800_init_rx_filter(rt2x00dev
, true, filter_tgt_bw40
);
5800 * Save BBP 25 & 26 values for later use in channel switching (for 3052)
5802 rt2800_bbp_read(rt2x00dev
, 25, &drv_data
->bbp25
);
5803 rt2800_bbp_read(rt2x00dev
, 26, &drv_data
->bbp26
);
5806 * Set back to initial state
5808 rt2800_bbp_write(rt2x00dev
, 24, 0);
5810 rt2800_rfcsr_read(rt2x00dev
, 22, &rfcsr
);
5811 rt2x00_set_field8(&rfcsr
, RFCSR22_BASEBAND_LOOPBACK
, 0);
5812 rt2800_rfcsr_write(rt2x00dev
, 22, rfcsr
);
5815 * Set BBP back to BW20
5817 rt2800_bbp_read(rt2x00dev
, 4, &bbp
);
5818 rt2x00_set_field8(&bbp
, BBP4_BANDWIDTH
, 0);
5819 rt2800_bbp_write(rt2x00dev
, 4, bbp
);
5822 static void rt2800_normal_mode_setup_3xxx(struct rt2x00_dev
*rt2x00dev
)
5824 struct rt2800_drv_data
*drv_data
= rt2x00dev
->drv_data
;
5825 u8 min_gain
, rfcsr
, bbp
;
5828 rt2800_rfcsr_read(rt2x00dev
, 17, &rfcsr
);
5830 rt2x00_set_field8(&rfcsr
, RFCSR17_TX_LO1_EN
, 0);
5831 if (rt2x00_rt(rt2x00dev
, RT3070
) ||
5832 rt2x00_rt_rev_lt(rt2x00dev
, RT3071
, REV_RT3071E
) ||
5833 rt2x00_rt_rev_lt(rt2x00dev
, RT3090
, REV_RT3090E
) ||
5834 rt2x00_rt_rev_lt(rt2x00dev
, RT3390
, REV_RT3390E
)) {
5835 if (!rt2x00_has_cap_external_lna_bg(rt2x00dev
))
5836 rt2x00_set_field8(&rfcsr
, RFCSR17_R
, 1);
5839 min_gain
= rt2x00_rt(rt2x00dev
, RT3070
) ? 1 : 2;
5840 if (drv_data
->txmixer_gain_24g
>= min_gain
) {
5841 rt2x00_set_field8(&rfcsr
, RFCSR17_TXMIXER_GAIN
,
5842 drv_data
->txmixer_gain_24g
);
5845 rt2800_rfcsr_write(rt2x00dev
, 17, rfcsr
);
5847 if (rt2x00_rt(rt2x00dev
, RT3090
)) {
5848 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
5849 rt2800_bbp_read(rt2x00dev
, 138, &bbp
);
5850 rt2800_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF0
, &eeprom
);
5851 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_RXPATH
) == 1)
5852 rt2x00_set_field8(&bbp
, BBP138_RX_ADC1
, 0);
5853 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_TXPATH
) == 1)
5854 rt2x00_set_field8(&bbp
, BBP138_TX_DAC1
, 1);
5855 rt2800_bbp_write(rt2x00dev
, 138, bbp
);
5858 if (rt2x00_rt(rt2x00dev
, RT3070
)) {
5859 rt2800_rfcsr_read(rt2x00dev
, 27, &rfcsr
);
5860 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070F
))
5861 rt2x00_set_field8(&rfcsr
, RFCSR27_R1
, 3);
5863 rt2x00_set_field8(&rfcsr
, RFCSR27_R1
, 0);
5864 rt2x00_set_field8(&rfcsr
, RFCSR27_R2
, 0);
5865 rt2x00_set_field8(&rfcsr
, RFCSR27_R3
, 0);
5866 rt2x00_set_field8(&rfcsr
, RFCSR27_R4
, 0);
5867 rt2800_rfcsr_write(rt2x00dev
, 27, rfcsr
);
5868 } else if (rt2x00_rt(rt2x00dev
, RT3071
) ||
5869 rt2x00_rt(rt2x00dev
, RT3090
) ||
5870 rt2x00_rt(rt2x00dev
, RT3390
)) {
5871 rt2800_rfcsr_read(rt2x00dev
, 1, &rfcsr
);
5872 rt2x00_set_field8(&rfcsr
, RFCSR1_RF_BLOCK_EN
, 1);
5873 rt2x00_set_field8(&rfcsr
, RFCSR1_RX0_PD
, 0);
5874 rt2x00_set_field8(&rfcsr
, RFCSR1_TX0_PD
, 0);
5875 rt2x00_set_field8(&rfcsr
, RFCSR1_RX1_PD
, 1);
5876 rt2x00_set_field8(&rfcsr
, RFCSR1_TX1_PD
, 1);
5877 rt2800_rfcsr_write(rt2x00dev
, 1, rfcsr
);
5879 rt2800_rfcsr_read(rt2x00dev
, 15, &rfcsr
);
5880 rt2x00_set_field8(&rfcsr
, RFCSR15_TX_LO2_EN
, 0);
5881 rt2800_rfcsr_write(rt2x00dev
, 15, rfcsr
);
5883 rt2800_rfcsr_read(rt2x00dev
, 20, &rfcsr
);
5884 rt2x00_set_field8(&rfcsr
, RFCSR20_RX_LO1_EN
, 0);
5885 rt2800_rfcsr_write(rt2x00dev
, 20, rfcsr
);
5887 rt2800_rfcsr_read(rt2x00dev
, 21, &rfcsr
);
5888 rt2x00_set_field8(&rfcsr
, RFCSR21_RX_LO2_EN
, 0);
5889 rt2800_rfcsr_write(rt2x00dev
, 21, rfcsr
);
5893 static void rt2800_normal_mode_setup_3593(struct rt2x00_dev
*rt2x00dev
)
5895 struct rt2800_drv_data
*drv_data
= rt2x00dev
->drv_data
;
5899 rt2800_rfcsr_read(rt2x00dev
, 50, &rfcsr
);
5900 rt2x00_set_field8(&rfcsr
, RFCSR50_TX_LO2_EN
, 0);
5901 rt2800_rfcsr_write(rt2x00dev
, 50, rfcsr
);
5903 rt2800_rfcsr_read(rt2x00dev
, 51, &rfcsr
);
5904 tx_gain
= rt2x00_get_field8(drv_data
->txmixer_gain_24g
,
5905 RFCSR17_TXMIXER_GAIN
);
5906 rt2x00_set_field8(&rfcsr
, RFCSR51_BITS24
, tx_gain
);
5907 rt2800_rfcsr_write(rt2x00dev
, 51, rfcsr
);
5909 rt2800_rfcsr_read(rt2x00dev
, 38, &rfcsr
);
5910 rt2x00_set_field8(&rfcsr
, RFCSR38_RX_LO1_EN
, 0);
5911 rt2800_rfcsr_write(rt2x00dev
, 38, rfcsr
);
5913 rt2800_rfcsr_read(rt2x00dev
, 39, &rfcsr
);
5914 rt2x00_set_field8(&rfcsr
, RFCSR39_RX_LO2_EN
, 0);
5915 rt2800_rfcsr_write(rt2x00dev
, 39, rfcsr
);
5917 rt2800_rfcsr_read(rt2x00dev
, 1, &rfcsr
);
5918 rt2x00_set_field8(&rfcsr
, RFCSR1_RF_BLOCK_EN
, 1);
5919 rt2x00_set_field8(&rfcsr
, RFCSR1_PLL_PD
, 1);
5920 rt2800_rfcsr_write(rt2x00dev
, 1, rfcsr
);
5922 rt2800_rfcsr_read(rt2x00dev
, 30, &rfcsr
);
5923 rt2x00_set_field8(&rfcsr
, RFCSR30_RX_VCM
, 2);
5924 rt2800_rfcsr_write(rt2x00dev
, 30, rfcsr
);
5926 /* TODO: enable stream mode */
5929 static void rt2800_normal_mode_setup_5xxx(struct rt2x00_dev
*rt2x00dev
)
5934 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
5935 rt2800_bbp_read(rt2x00dev
, 138, ®
);
5936 rt2800_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF0
, &eeprom
);
5937 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_RXPATH
) == 1)
5938 rt2x00_set_field8(®
, BBP138_RX_ADC1
, 0);
5939 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_TXPATH
) == 1)
5940 rt2x00_set_field8(®
, BBP138_TX_DAC1
, 1);
5941 rt2800_bbp_write(rt2x00dev
, 138, reg
);
5943 rt2800_rfcsr_read(rt2x00dev
, 38, ®
);
5944 rt2x00_set_field8(®
, RFCSR38_RX_LO1_EN
, 0);
5945 rt2800_rfcsr_write(rt2x00dev
, 38, reg
);
5947 rt2800_rfcsr_read(rt2x00dev
, 39, ®
);
5948 rt2x00_set_field8(®
, RFCSR39_RX_LO2_EN
, 0);
5949 rt2800_rfcsr_write(rt2x00dev
, 39, reg
);
5951 rt2800_bbp4_mac_if_ctrl(rt2x00dev
);
5953 rt2800_rfcsr_read(rt2x00dev
, 30, ®
);
5954 rt2x00_set_field8(®
, RFCSR30_RX_VCM
, 2);
5955 rt2800_rfcsr_write(rt2x00dev
, 30, reg
);
5958 static void rt2800_init_rfcsr_305x_soc(struct rt2x00_dev
*rt2x00dev
)
5960 rt2800_rf_init_calibration(rt2x00dev
, 30);
5962 rt2800_rfcsr_write(rt2x00dev
, 0, 0x50);
5963 rt2800_rfcsr_write(rt2x00dev
, 1, 0x01);
5964 rt2800_rfcsr_write(rt2x00dev
, 2, 0xf7);
5965 rt2800_rfcsr_write(rt2x00dev
, 3, 0x75);
5966 rt2800_rfcsr_write(rt2x00dev
, 4, 0x40);
5967 rt2800_rfcsr_write(rt2x00dev
, 5, 0x03);
5968 rt2800_rfcsr_write(rt2x00dev
, 6, 0x02);
5969 rt2800_rfcsr_write(rt2x00dev
, 7, 0x50);
5970 rt2800_rfcsr_write(rt2x00dev
, 8, 0x39);
5971 rt2800_rfcsr_write(rt2x00dev
, 9, 0x0f);
5972 rt2800_rfcsr_write(rt2x00dev
, 10, 0x60);
5973 rt2800_rfcsr_write(rt2x00dev
, 11, 0x21);
5974 rt2800_rfcsr_write(rt2x00dev
, 12, 0x75);
5975 rt2800_rfcsr_write(rt2x00dev
, 13, 0x75);
5976 rt2800_rfcsr_write(rt2x00dev
, 14, 0x90);
5977 rt2800_rfcsr_write(rt2x00dev
, 15, 0x58);
5978 rt2800_rfcsr_write(rt2x00dev
, 16, 0xb3);
5979 rt2800_rfcsr_write(rt2x00dev
, 17, 0x92);
5980 rt2800_rfcsr_write(rt2x00dev
, 18, 0x2c);
5981 rt2800_rfcsr_write(rt2x00dev
, 19, 0x02);
5982 rt2800_rfcsr_write(rt2x00dev
, 20, 0xba);
5983 rt2800_rfcsr_write(rt2x00dev
, 21, 0xdb);
5984 rt2800_rfcsr_write(rt2x00dev
, 22, 0x00);
5985 rt2800_rfcsr_write(rt2x00dev
, 23, 0x31);
5986 rt2800_rfcsr_write(rt2x00dev
, 24, 0x08);
5987 rt2800_rfcsr_write(rt2x00dev
, 25, 0x01);
5988 rt2800_rfcsr_write(rt2x00dev
, 26, 0x25);
5989 rt2800_rfcsr_write(rt2x00dev
, 27, 0x23);
5990 rt2800_rfcsr_write(rt2x00dev
, 28, 0x13);
5991 rt2800_rfcsr_write(rt2x00dev
, 29, 0x83);
5992 rt2800_rfcsr_write(rt2x00dev
, 30, 0x00);
5993 rt2800_rfcsr_write(rt2x00dev
, 31, 0x00);
5996 static void rt2800_init_rfcsr_30xx(struct rt2x00_dev
*rt2x00dev
)
6002 /* XXX vendor driver do this only for 3070 */
6003 rt2800_rf_init_calibration(rt2x00dev
, 30);
6005 rt2800_rfcsr_write(rt2x00dev
, 4, 0x40);
6006 rt2800_rfcsr_write(rt2x00dev
, 5, 0x03);
6007 rt2800_rfcsr_write(rt2x00dev
, 6, 0x02);
6008 rt2800_rfcsr_write(rt2x00dev
, 7, 0x60);
6009 rt2800_rfcsr_write(rt2x00dev
, 9, 0x0f);
6010 rt2800_rfcsr_write(rt2x00dev
, 10, 0x41);
6011 rt2800_rfcsr_write(rt2x00dev
, 11, 0x21);
6012 rt2800_rfcsr_write(rt2x00dev
, 12, 0x7b);
6013 rt2800_rfcsr_write(rt2x00dev
, 14, 0x90);
6014 rt2800_rfcsr_write(rt2x00dev
, 15, 0x58);
6015 rt2800_rfcsr_write(rt2x00dev
, 16, 0xb3);
6016 rt2800_rfcsr_write(rt2x00dev
, 17, 0x92);
6017 rt2800_rfcsr_write(rt2x00dev
, 18, 0x2c);
6018 rt2800_rfcsr_write(rt2x00dev
, 19, 0x02);
6019 rt2800_rfcsr_write(rt2x00dev
, 20, 0xba);
6020 rt2800_rfcsr_write(rt2x00dev
, 21, 0xdb);
6021 rt2800_rfcsr_write(rt2x00dev
, 24, 0x16);
6022 rt2800_rfcsr_write(rt2x00dev
, 25, 0x03);
6023 rt2800_rfcsr_write(rt2x00dev
, 29, 0x1f);
6025 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070F
)) {
6026 rt2800_register_read(rt2x00dev
, LDO_CFG0
, ®
);
6027 rt2x00_set_field32(®
, LDO_CFG0_BGSEL
, 1);
6028 rt2x00_set_field32(®
, LDO_CFG0_LDO_CORE_VLEVEL
, 3);
6029 rt2800_register_write(rt2x00dev
, LDO_CFG0
, reg
);
6030 } else if (rt2x00_rt(rt2x00dev
, RT3071
) ||
6031 rt2x00_rt(rt2x00dev
, RT3090
)) {
6032 rt2800_rfcsr_write(rt2x00dev
, 31, 0x14);
6034 rt2800_rfcsr_read(rt2x00dev
, 6, &rfcsr
);
6035 rt2x00_set_field8(&rfcsr
, RFCSR6_R2
, 1);
6036 rt2800_rfcsr_write(rt2x00dev
, 6, rfcsr
);
6038 rt2800_register_read(rt2x00dev
, LDO_CFG0
, ®
);
6039 rt2x00_set_field32(®
, LDO_CFG0_BGSEL
, 1);
6040 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3071
, REV_RT3071E
) ||
6041 rt2x00_rt_rev_lt(rt2x00dev
, RT3090
, REV_RT3090E
)) {
6042 rt2800_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF1
,
6044 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF1_DAC_TEST
))
6045 rt2x00_set_field32(®
, LDO_CFG0_LDO_CORE_VLEVEL
, 3);
6047 rt2x00_set_field32(®
, LDO_CFG0_LDO_CORE_VLEVEL
, 0);
6049 rt2800_register_write(rt2x00dev
, LDO_CFG0
, reg
);
6051 rt2800_register_read(rt2x00dev
, GPIO_SWITCH
, ®
);
6052 rt2x00_set_field32(®
, GPIO_SWITCH_5
, 0);
6053 rt2800_register_write(rt2x00dev
, GPIO_SWITCH
, reg
);
6056 rt2800_rx_filter_calibration(rt2x00dev
);
6058 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070F
) ||
6059 rt2x00_rt_rev_lt(rt2x00dev
, RT3071
, REV_RT3071E
) ||
6060 rt2x00_rt_rev_lt(rt2x00dev
, RT3090
, REV_RT3090E
))
6061 rt2800_rfcsr_write(rt2x00dev
, 27, 0x03);
6063 rt2800_led_open_drain_enable(rt2x00dev
);
6064 rt2800_normal_mode_setup_3xxx(rt2x00dev
);
6067 static void rt2800_init_rfcsr_3290(struct rt2x00_dev
*rt2x00dev
)
6071 rt2800_rf_init_calibration(rt2x00dev
, 2);
6073 rt2800_rfcsr_write(rt2x00dev
, 1, 0x0f);
6074 rt2800_rfcsr_write(rt2x00dev
, 2, 0x80);
6075 rt2800_rfcsr_write(rt2x00dev
, 3, 0x08);
6076 rt2800_rfcsr_write(rt2x00dev
, 4, 0x00);
6077 rt2800_rfcsr_write(rt2x00dev
, 6, 0xa0);
6078 rt2800_rfcsr_write(rt2x00dev
, 8, 0xf3);
6079 rt2800_rfcsr_write(rt2x00dev
, 9, 0x02);
6080 rt2800_rfcsr_write(rt2x00dev
, 10, 0x53);
6081 rt2800_rfcsr_write(rt2x00dev
, 11, 0x4a);
6082 rt2800_rfcsr_write(rt2x00dev
, 12, 0x46);
6083 rt2800_rfcsr_write(rt2x00dev
, 13, 0x9f);
6084 rt2800_rfcsr_write(rt2x00dev
, 18, 0x02);
6085 rt2800_rfcsr_write(rt2x00dev
, 22, 0x20);
6086 rt2800_rfcsr_write(rt2x00dev
, 25, 0x83);
6087 rt2800_rfcsr_write(rt2x00dev
, 26, 0x82);
6088 rt2800_rfcsr_write(rt2x00dev
, 27, 0x09);
6089 rt2800_rfcsr_write(rt2x00dev
, 29, 0x10);
6090 rt2800_rfcsr_write(rt2x00dev
, 30, 0x10);
6091 rt2800_rfcsr_write(rt2x00dev
, 31, 0x80);
6092 rt2800_rfcsr_write(rt2x00dev
, 32, 0x80);
6093 rt2800_rfcsr_write(rt2x00dev
, 33, 0x00);
6094 rt2800_rfcsr_write(rt2x00dev
, 34, 0x05);
6095 rt2800_rfcsr_write(rt2x00dev
, 35, 0x12);
6096 rt2800_rfcsr_write(rt2x00dev
, 36, 0x00);
6097 rt2800_rfcsr_write(rt2x00dev
, 38, 0x85);
6098 rt2800_rfcsr_write(rt2x00dev
, 39, 0x1b);
6099 rt2800_rfcsr_write(rt2x00dev
, 40, 0x0b);
6100 rt2800_rfcsr_write(rt2x00dev
, 41, 0xbb);
6101 rt2800_rfcsr_write(rt2x00dev
, 42, 0xd5);
6102 rt2800_rfcsr_write(rt2x00dev
, 43, 0x7b);
6103 rt2800_rfcsr_write(rt2x00dev
, 44, 0x0e);
6104 rt2800_rfcsr_write(rt2x00dev
, 45, 0xa2);
6105 rt2800_rfcsr_write(rt2x00dev
, 46, 0x73);
6106 rt2800_rfcsr_write(rt2x00dev
, 47, 0x00);
6107 rt2800_rfcsr_write(rt2x00dev
, 48, 0x10);
6108 rt2800_rfcsr_write(rt2x00dev
, 49, 0x98);
6109 rt2800_rfcsr_write(rt2x00dev
, 52, 0x38);
6110 rt2800_rfcsr_write(rt2x00dev
, 53, 0x00);
6111 rt2800_rfcsr_write(rt2x00dev
, 54, 0x78);
6112 rt2800_rfcsr_write(rt2x00dev
, 55, 0x43);
6113 rt2800_rfcsr_write(rt2x00dev
, 56, 0x02);
6114 rt2800_rfcsr_write(rt2x00dev
, 57, 0x80);
6115 rt2800_rfcsr_write(rt2x00dev
, 58, 0x7f);
6116 rt2800_rfcsr_write(rt2x00dev
, 59, 0x09);
6117 rt2800_rfcsr_write(rt2x00dev
, 60, 0x45);
6118 rt2800_rfcsr_write(rt2x00dev
, 61, 0xc1);
6120 rt2800_rfcsr_read(rt2x00dev
, 29, &rfcsr
);
6121 rt2x00_set_field8(&rfcsr
, RFCSR29_RSSI_GAIN
, 3);
6122 rt2800_rfcsr_write(rt2x00dev
, 29, rfcsr
);
6124 rt2800_led_open_drain_enable(rt2x00dev
);
6125 rt2800_normal_mode_setup_3xxx(rt2x00dev
);
6128 static void rt2800_init_rfcsr_3352(struct rt2x00_dev
*rt2x00dev
)
6130 rt2800_rf_init_calibration(rt2x00dev
, 30);
6132 rt2800_rfcsr_write(rt2x00dev
, 0, 0xf0);
6133 rt2800_rfcsr_write(rt2x00dev
, 1, 0x23);
6134 rt2800_rfcsr_write(rt2x00dev
, 2, 0x50);
6135 rt2800_rfcsr_write(rt2x00dev
, 3, 0x18);
6136 rt2800_rfcsr_write(rt2x00dev
, 4, 0x00);
6137 rt2800_rfcsr_write(rt2x00dev
, 5, 0x00);
6138 rt2800_rfcsr_write(rt2x00dev
, 6, 0x33);
6139 rt2800_rfcsr_write(rt2x00dev
, 7, 0x00);
6140 rt2800_rfcsr_write(rt2x00dev
, 8, 0xf1);
6141 rt2800_rfcsr_write(rt2x00dev
, 9, 0x02);
6142 rt2800_rfcsr_write(rt2x00dev
, 10, 0xd2);
6143 rt2800_rfcsr_write(rt2x00dev
, 11, 0x42);
6144 rt2800_rfcsr_write(rt2x00dev
, 12, 0x1c);
6145 rt2800_rfcsr_write(rt2x00dev
, 13, 0x00);
6146 rt2800_rfcsr_write(rt2x00dev
, 14, 0x5a);
6147 rt2800_rfcsr_write(rt2x00dev
, 15, 0x00);
6148 rt2800_rfcsr_write(rt2x00dev
, 16, 0x01);
6149 rt2800_rfcsr_write(rt2x00dev
, 18, 0x45);
6150 rt2800_rfcsr_write(rt2x00dev
, 19, 0x02);
6151 rt2800_rfcsr_write(rt2x00dev
, 20, 0x00);
6152 rt2800_rfcsr_write(rt2x00dev
, 21, 0x00);
6153 rt2800_rfcsr_write(rt2x00dev
, 22, 0x00);
6154 rt2800_rfcsr_write(rt2x00dev
, 23, 0x00);
6155 rt2800_rfcsr_write(rt2x00dev
, 24, 0x00);
6156 rt2800_rfcsr_write(rt2x00dev
, 25, 0x80);
6157 rt2800_rfcsr_write(rt2x00dev
, 26, 0x00);
6158 rt2800_rfcsr_write(rt2x00dev
, 27, 0x03);
6159 rt2800_rfcsr_write(rt2x00dev
, 28, 0x03);
6160 rt2800_rfcsr_write(rt2x00dev
, 29, 0x00);
6161 rt2800_rfcsr_write(rt2x00dev
, 30, 0x10);
6162 rt2800_rfcsr_write(rt2x00dev
, 31, 0x80);
6163 rt2800_rfcsr_write(rt2x00dev
, 32, 0x80);
6164 rt2800_rfcsr_write(rt2x00dev
, 33, 0x00);
6165 rt2800_rfcsr_write(rt2x00dev
, 34, 0x01);
6166 rt2800_rfcsr_write(rt2x00dev
, 35, 0x03);
6167 rt2800_rfcsr_write(rt2x00dev
, 36, 0xbd);
6168 rt2800_rfcsr_write(rt2x00dev
, 37, 0x3c);
6169 rt2800_rfcsr_write(rt2x00dev
, 38, 0x5f);
6170 rt2800_rfcsr_write(rt2x00dev
, 39, 0xc5);
6171 rt2800_rfcsr_write(rt2x00dev
, 40, 0x33);
6172 rt2800_rfcsr_write(rt2x00dev
, 41, 0x5b);
6173 rt2800_rfcsr_write(rt2x00dev
, 42, 0x5b);
6174 rt2800_rfcsr_write(rt2x00dev
, 43, 0xdb);
6175 rt2800_rfcsr_write(rt2x00dev
, 44, 0xdb);
6176 rt2800_rfcsr_write(rt2x00dev
, 45, 0xdb);
6177 rt2800_rfcsr_write(rt2x00dev
, 46, 0xdd);
6178 rt2800_rfcsr_write(rt2x00dev
, 47, 0x0d);
6179 rt2800_rfcsr_write(rt2x00dev
, 48, 0x14);
6180 rt2800_rfcsr_write(rt2x00dev
, 49, 0x00);
6181 rt2800_rfcsr_write(rt2x00dev
, 50, 0x2d);
6182 rt2800_rfcsr_write(rt2x00dev
, 51, 0x7f);
6183 rt2800_rfcsr_write(rt2x00dev
, 52, 0x00);
6184 rt2800_rfcsr_write(rt2x00dev
, 53, 0x52);
6185 rt2800_rfcsr_write(rt2x00dev
, 54, 0x1b);
6186 rt2800_rfcsr_write(rt2x00dev
, 55, 0x7f);
6187 rt2800_rfcsr_write(rt2x00dev
, 56, 0x00);
6188 rt2800_rfcsr_write(rt2x00dev
, 57, 0x52);
6189 rt2800_rfcsr_write(rt2x00dev
, 58, 0x1b);
6190 rt2800_rfcsr_write(rt2x00dev
, 59, 0x00);
6191 rt2800_rfcsr_write(rt2x00dev
, 60, 0x00);
6192 rt2800_rfcsr_write(rt2x00dev
, 61, 0x00);
6193 rt2800_rfcsr_write(rt2x00dev
, 62, 0x00);
6194 rt2800_rfcsr_write(rt2x00dev
, 63, 0x00);
6196 rt2800_rx_filter_calibration(rt2x00dev
);
6197 rt2800_led_open_drain_enable(rt2x00dev
);
6198 rt2800_normal_mode_setup_3xxx(rt2x00dev
);
6201 static void rt2800_init_rfcsr_3390(struct rt2x00_dev
*rt2x00dev
)
6205 rt2800_rf_init_calibration(rt2x00dev
, 30);
6207 rt2800_rfcsr_write(rt2x00dev
, 0, 0xa0);
6208 rt2800_rfcsr_write(rt2x00dev
, 1, 0xe1);
6209 rt2800_rfcsr_write(rt2x00dev
, 2, 0xf1);
6210 rt2800_rfcsr_write(rt2x00dev
, 3, 0x62);
6211 rt2800_rfcsr_write(rt2x00dev
, 4, 0x40);
6212 rt2800_rfcsr_write(rt2x00dev
, 5, 0x8b);
6213 rt2800_rfcsr_write(rt2x00dev
, 6, 0x42);
6214 rt2800_rfcsr_write(rt2x00dev
, 7, 0x34);
6215 rt2800_rfcsr_write(rt2x00dev
, 8, 0x00);
6216 rt2800_rfcsr_write(rt2x00dev
, 9, 0xc0);
6217 rt2800_rfcsr_write(rt2x00dev
, 10, 0x61);
6218 rt2800_rfcsr_write(rt2x00dev
, 11, 0x21);
6219 rt2800_rfcsr_write(rt2x00dev
, 12, 0x3b);
6220 rt2800_rfcsr_write(rt2x00dev
, 13, 0xe0);
6221 rt2800_rfcsr_write(rt2x00dev
, 14, 0x90);
6222 rt2800_rfcsr_write(rt2x00dev
, 15, 0x53);
6223 rt2800_rfcsr_write(rt2x00dev
, 16, 0xe0);
6224 rt2800_rfcsr_write(rt2x00dev
, 17, 0x94);
6225 rt2800_rfcsr_write(rt2x00dev
, 18, 0x5c);
6226 rt2800_rfcsr_write(rt2x00dev
, 19, 0x4a);
6227 rt2800_rfcsr_write(rt2x00dev
, 20, 0xb2);
6228 rt2800_rfcsr_write(rt2x00dev
, 21, 0xf6);
6229 rt2800_rfcsr_write(rt2x00dev
, 22, 0x00);
6230 rt2800_rfcsr_write(rt2x00dev
, 23, 0x14);
6231 rt2800_rfcsr_write(rt2x00dev
, 24, 0x08);
6232 rt2800_rfcsr_write(rt2x00dev
, 25, 0x3d);
6233 rt2800_rfcsr_write(rt2x00dev
, 26, 0x85);
6234 rt2800_rfcsr_write(rt2x00dev
, 27, 0x00);
6235 rt2800_rfcsr_write(rt2x00dev
, 28, 0x41);
6236 rt2800_rfcsr_write(rt2x00dev
, 29, 0x8f);
6237 rt2800_rfcsr_write(rt2x00dev
, 30, 0x20);
6238 rt2800_rfcsr_write(rt2x00dev
, 31, 0x0f);
6240 rt2800_register_read(rt2x00dev
, GPIO_SWITCH
, ®
);
6241 rt2x00_set_field32(®
, GPIO_SWITCH_5
, 0);
6242 rt2800_register_write(rt2x00dev
, GPIO_SWITCH
, reg
);
6244 rt2800_rx_filter_calibration(rt2x00dev
);
6246 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3390
, REV_RT3390E
))
6247 rt2800_rfcsr_write(rt2x00dev
, 27, 0x03);
6249 rt2800_led_open_drain_enable(rt2x00dev
);
6250 rt2800_normal_mode_setup_3xxx(rt2x00dev
);
6253 static void rt2800_init_rfcsr_3572(struct rt2x00_dev
*rt2x00dev
)
6258 rt2800_rf_init_calibration(rt2x00dev
, 30);
6260 rt2800_rfcsr_write(rt2x00dev
, 0, 0x70);
6261 rt2800_rfcsr_write(rt2x00dev
, 1, 0x81);
6262 rt2800_rfcsr_write(rt2x00dev
, 2, 0xf1);
6263 rt2800_rfcsr_write(rt2x00dev
, 3, 0x02);
6264 rt2800_rfcsr_write(rt2x00dev
, 4, 0x4c);
6265 rt2800_rfcsr_write(rt2x00dev
, 5, 0x05);
6266 rt2800_rfcsr_write(rt2x00dev
, 6, 0x4a);
6267 rt2800_rfcsr_write(rt2x00dev
, 7, 0xd8);
6268 rt2800_rfcsr_write(rt2x00dev
, 9, 0xc3);
6269 rt2800_rfcsr_write(rt2x00dev
, 10, 0xf1);
6270 rt2800_rfcsr_write(rt2x00dev
, 11, 0xb9);
6271 rt2800_rfcsr_write(rt2x00dev
, 12, 0x70);
6272 rt2800_rfcsr_write(rt2x00dev
, 13, 0x65);
6273 rt2800_rfcsr_write(rt2x00dev
, 14, 0xa0);
6274 rt2800_rfcsr_write(rt2x00dev
, 15, 0x53);
6275 rt2800_rfcsr_write(rt2x00dev
, 16, 0x4c);
6276 rt2800_rfcsr_write(rt2x00dev
, 17, 0x23);
6277 rt2800_rfcsr_write(rt2x00dev
, 18, 0xac);
6278 rt2800_rfcsr_write(rt2x00dev
, 19, 0x93);
6279 rt2800_rfcsr_write(rt2x00dev
, 20, 0xb3);
6280 rt2800_rfcsr_write(rt2x00dev
, 21, 0xd0);
6281 rt2800_rfcsr_write(rt2x00dev
, 22, 0x00);
6282 rt2800_rfcsr_write(rt2x00dev
, 23, 0x3c);
6283 rt2800_rfcsr_write(rt2x00dev
, 24, 0x16);
6284 rt2800_rfcsr_write(rt2x00dev
, 25, 0x15);
6285 rt2800_rfcsr_write(rt2x00dev
, 26, 0x85);
6286 rt2800_rfcsr_write(rt2x00dev
, 27, 0x00);
6287 rt2800_rfcsr_write(rt2x00dev
, 28, 0x00);
6288 rt2800_rfcsr_write(rt2x00dev
, 29, 0x9b);
6289 rt2800_rfcsr_write(rt2x00dev
, 30, 0x09);
6290 rt2800_rfcsr_write(rt2x00dev
, 31, 0x10);
6292 rt2800_rfcsr_read(rt2x00dev
, 6, &rfcsr
);
6293 rt2x00_set_field8(&rfcsr
, RFCSR6_R2
, 1);
6294 rt2800_rfcsr_write(rt2x00dev
, 6, rfcsr
);
6296 rt2800_register_read(rt2x00dev
, LDO_CFG0
, ®
);
6297 rt2x00_set_field32(®
, LDO_CFG0_LDO_CORE_VLEVEL
, 3);
6298 rt2x00_set_field32(®
, LDO_CFG0_BGSEL
, 1);
6299 rt2800_register_write(rt2x00dev
, LDO_CFG0
, reg
);
6301 rt2800_register_read(rt2x00dev
, LDO_CFG0
, ®
);
6302 rt2x00_set_field32(®
, LDO_CFG0_LDO_CORE_VLEVEL
, 0);
6303 rt2x00_set_field32(®
, LDO_CFG0_BGSEL
, 1);
6304 rt2800_register_write(rt2x00dev
, LDO_CFG0
, reg
);
6306 rt2800_rx_filter_calibration(rt2x00dev
);
6307 rt2800_led_open_drain_enable(rt2x00dev
);
6308 rt2800_normal_mode_setup_3xxx(rt2x00dev
);
6311 static void rt3593_post_bbp_init(struct rt2x00_dev
*rt2x00dev
)
6314 bool txbf_enabled
= false; /* FIXME */
6316 rt2800_bbp_read(rt2x00dev
, 105, &bbp
);
6317 if (rt2x00dev
->default_ant
.rx_chain_num
== 1)
6318 rt2x00_set_field8(&bbp
, BBP105_MLD
, 0);
6320 rt2x00_set_field8(&bbp
, BBP105_MLD
, 1);
6321 rt2800_bbp_write(rt2x00dev
, 105, bbp
);
6323 rt2800_bbp4_mac_if_ctrl(rt2x00dev
);
6325 rt2800_bbp_write(rt2x00dev
, 92, 0x02);
6326 rt2800_bbp_write(rt2x00dev
, 82, 0x82);
6327 rt2800_bbp_write(rt2x00dev
, 106, 0x05);
6328 rt2800_bbp_write(rt2x00dev
, 104, 0x92);
6329 rt2800_bbp_write(rt2x00dev
, 88, 0x90);
6330 rt2800_bbp_write(rt2x00dev
, 148, 0xc8);
6331 rt2800_bbp_write(rt2x00dev
, 47, 0x48);
6332 rt2800_bbp_write(rt2x00dev
, 120, 0x50);
6335 rt2800_bbp_write(rt2x00dev
, 163, 0xbd);
6337 rt2800_bbp_write(rt2x00dev
, 163, 0x9d);
6340 rt2800_bbp_write(rt2x00dev
, 142, 6);
6341 rt2800_bbp_write(rt2x00dev
, 143, 160);
6342 rt2800_bbp_write(rt2x00dev
, 142, 7);
6343 rt2800_bbp_write(rt2x00dev
, 143, 161);
6344 rt2800_bbp_write(rt2x00dev
, 142, 8);
6345 rt2800_bbp_write(rt2x00dev
, 143, 162);
6347 /* ADC/DAC control */
6348 rt2800_bbp_write(rt2x00dev
, 31, 0x08);
6350 /* RX AGC energy lower bound in log2 */
6351 rt2800_bbp_write(rt2x00dev
, 68, 0x0b);
6353 /* FIXME: BBP 105 owerwrite? */
6354 rt2800_bbp_write(rt2x00dev
, 105, 0x04);
6358 static void rt2800_init_rfcsr_3593(struct rt2x00_dev
*rt2x00dev
)
6360 struct rt2800_drv_data
*drv_data
= rt2x00dev
->drv_data
;
6364 /* Disable GPIO #4 and #7 function for LAN PE control */
6365 rt2800_register_read(rt2x00dev
, GPIO_SWITCH
, ®
);
6366 rt2x00_set_field32(®
, GPIO_SWITCH_4
, 0);
6367 rt2x00_set_field32(®
, GPIO_SWITCH_7
, 0);
6368 rt2800_register_write(rt2x00dev
, GPIO_SWITCH
, reg
);
6370 /* Initialize default register values */
6371 rt2800_rfcsr_write(rt2x00dev
, 1, 0x03);
6372 rt2800_rfcsr_write(rt2x00dev
, 3, 0x80);
6373 rt2800_rfcsr_write(rt2x00dev
, 5, 0x00);
6374 rt2800_rfcsr_write(rt2x00dev
, 6, 0x40);
6375 rt2800_rfcsr_write(rt2x00dev
, 8, 0xf1);
6376 rt2800_rfcsr_write(rt2x00dev
, 9, 0x02);
6377 rt2800_rfcsr_write(rt2x00dev
, 10, 0xd3);
6378 rt2800_rfcsr_write(rt2x00dev
, 11, 0x40);
6379 rt2800_rfcsr_write(rt2x00dev
, 12, 0x4e);
6380 rt2800_rfcsr_write(rt2x00dev
, 13, 0x12);
6381 rt2800_rfcsr_write(rt2x00dev
, 18, 0x40);
6382 rt2800_rfcsr_write(rt2x00dev
, 22, 0x20);
6383 rt2800_rfcsr_write(rt2x00dev
, 30, 0x10);
6384 rt2800_rfcsr_write(rt2x00dev
, 31, 0x80);
6385 rt2800_rfcsr_write(rt2x00dev
, 32, 0x78);
6386 rt2800_rfcsr_write(rt2x00dev
, 33, 0x3b);
6387 rt2800_rfcsr_write(rt2x00dev
, 34, 0x3c);
6388 rt2800_rfcsr_write(rt2x00dev
, 35, 0xe0);
6389 rt2800_rfcsr_write(rt2x00dev
, 38, 0x86);
6390 rt2800_rfcsr_write(rt2x00dev
, 39, 0x23);
6391 rt2800_rfcsr_write(rt2x00dev
, 44, 0xd3);
6392 rt2800_rfcsr_write(rt2x00dev
, 45, 0xbb);
6393 rt2800_rfcsr_write(rt2x00dev
, 46, 0x60);
6394 rt2800_rfcsr_write(rt2x00dev
, 49, 0x8e);
6395 rt2800_rfcsr_write(rt2x00dev
, 50, 0x86);
6396 rt2800_rfcsr_write(rt2x00dev
, 51, 0x75);
6397 rt2800_rfcsr_write(rt2x00dev
, 52, 0x45);
6398 rt2800_rfcsr_write(rt2x00dev
, 53, 0x18);
6399 rt2800_rfcsr_write(rt2x00dev
, 54, 0x18);
6400 rt2800_rfcsr_write(rt2x00dev
, 55, 0x18);
6401 rt2800_rfcsr_write(rt2x00dev
, 56, 0xdb);
6402 rt2800_rfcsr_write(rt2x00dev
, 57, 0x6e);
6404 /* Initiate calibration */
6405 /* TODO: use rt2800_rf_init_calibration ? */
6406 rt2800_rfcsr_read(rt2x00dev
, 2, &rfcsr
);
6407 rt2x00_set_field8(&rfcsr
, RFCSR2_RESCAL_EN
, 1);
6408 rt2800_rfcsr_write(rt2x00dev
, 2, rfcsr
);
6410 rt2800_adjust_freq_offset(rt2x00dev
);
6412 rt2800_rfcsr_read(rt2x00dev
, 18, &rfcsr
);
6413 rt2x00_set_field8(&rfcsr
, RFCSR18_XO_TUNE_BYPASS
, 1);
6414 rt2800_rfcsr_write(rt2x00dev
, 18, rfcsr
);
6416 rt2800_register_read(rt2x00dev
, LDO_CFG0
, ®
);
6417 rt2x00_set_field32(®
, LDO_CFG0_LDO_CORE_VLEVEL
, 3);
6418 rt2x00_set_field32(®
, LDO_CFG0_BGSEL
, 1);
6419 rt2800_register_write(rt2x00dev
, LDO_CFG0
, reg
);
6420 usleep_range(1000, 1500);
6421 rt2800_register_read(rt2x00dev
, LDO_CFG0
, ®
);
6422 rt2x00_set_field32(®
, LDO_CFG0_LDO_CORE_VLEVEL
, 0);
6423 rt2800_register_write(rt2x00dev
, LDO_CFG0
, reg
);
6425 /* Set initial values for RX filter calibration */
6426 drv_data
->calibration_bw20
= 0x1f;
6427 drv_data
->calibration_bw40
= 0x2f;
6429 /* Save BBP 25 & 26 values for later use in channel switching */
6430 rt2800_bbp_read(rt2x00dev
, 25, &drv_data
->bbp25
);
6431 rt2800_bbp_read(rt2x00dev
, 26, &drv_data
->bbp26
);
6433 rt2800_led_open_drain_enable(rt2x00dev
);
6434 rt2800_normal_mode_setup_3593(rt2x00dev
);
6436 rt3593_post_bbp_init(rt2x00dev
);
6438 /* TODO: enable stream mode support */
6441 static void rt2800_init_rfcsr_5390(struct rt2x00_dev
*rt2x00dev
)
6443 rt2800_rf_init_calibration(rt2x00dev
, 2);
6445 rt2800_rfcsr_write(rt2x00dev
, 1, 0x0f);
6446 rt2800_rfcsr_write(rt2x00dev
, 2, 0x80);
6447 rt2800_rfcsr_write(rt2x00dev
, 3, 0x88);
6448 rt2800_rfcsr_write(rt2x00dev
, 5, 0x10);
6449 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390F
))
6450 rt2800_rfcsr_write(rt2x00dev
, 6, 0xe0);
6452 rt2800_rfcsr_write(rt2x00dev
, 6, 0xa0);
6453 rt2800_rfcsr_write(rt2x00dev
, 7, 0x00);
6454 rt2800_rfcsr_write(rt2x00dev
, 10, 0x53);
6455 rt2800_rfcsr_write(rt2x00dev
, 11, 0x4a);
6456 rt2800_rfcsr_write(rt2x00dev
, 12, 0xc6);
6457 rt2800_rfcsr_write(rt2x00dev
, 13, 0x9f);
6458 rt2800_rfcsr_write(rt2x00dev
, 14, 0x00);
6459 rt2800_rfcsr_write(rt2x00dev
, 15, 0x00);
6460 rt2800_rfcsr_write(rt2x00dev
, 16, 0x00);
6461 rt2800_rfcsr_write(rt2x00dev
, 18, 0x03);
6462 rt2800_rfcsr_write(rt2x00dev
, 19, 0x00);
6464 rt2800_rfcsr_write(rt2x00dev
, 20, 0x00);
6465 rt2800_rfcsr_write(rt2x00dev
, 21, 0x00);
6466 rt2800_rfcsr_write(rt2x00dev
, 22, 0x20);
6467 rt2800_rfcsr_write(rt2x00dev
, 23, 0x00);
6468 rt2800_rfcsr_write(rt2x00dev
, 24, 0x00);
6469 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390F
))
6470 rt2800_rfcsr_write(rt2x00dev
, 25, 0x80);
6472 rt2800_rfcsr_write(rt2x00dev
, 25, 0xc0);
6473 rt2800_rfcsr_write(rt2x00dev
, 26, 0x00);
6474 rt2800_rfcsr_write(rt2x00dev
, 27, 0x09);
6475 rt2800_rfcsr_write(rt2x00dev
, 28, 0x00);
6476 rt2800_rfcsr_write(rt2x00dev
, 29, 0x10);
6478 rt2800_rfcsr_write(rt2x00dev
, 30, 0x10);
6479 rt2800_rfcsr_write(rt2x00dev
, 31, 0x80);
6480 rt2800_rfcsr_write(rt2x00dev
, 32, 0x80);
6481 rt2800_rfcsr_write(rt2x00dev
, 33, 0x00);
6482 rt2800_rfcsr_write(rt2x00dev
, 34, 0x07);
6483 rt2800_rfcsr_write(rt2x00dev
, 35, 0x12);
6484 rt2800_rfcsr_write(rt2x00dev
, 36, 0x00);
6485 rt2800_rfcsr_write(rt2x00dev
, 37, 0x08);
6486 rt2800_rfcsr_write(rt2x00dev
, 38, 0x85);
6487 rt2800_rfcsr_write(rt2x00dev
, 39, 0x1b);
6489 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390F
))
6490 rt2800_rfcsr_write(rt2x00dev
, 40, 0x0b);
6492 rt2800_rfcsr_write(rt2x00dev
, 40, 0x4b);
6493 rt2800_rfcsr_write(rt2x00dev
, 41, 0xbb);
6494 rt2800_rfcsr_write(rt2x00dev
, 42, 0xd2);
6495 rt2800_rfcsr_write(rt2x00dev
, 43, 0x9a);
6496 rt2800_rfcsr_write(rt2x00dev
, 44, 0x0e);
6497 rt2800_rfcsr_write(rt2x00dev
, 45, 0xa2);
6498 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390F
))
6499 rt2800_rfcsr_write(rt2x00dev
, 46, 0x73);
6501 rt2800_rfcsr_write(rt2x00dev
, 46, 0x7b);
6502 rt2800_rfcsr_write(rt2x00dev
, 47, 0x00);
6503 rt2800_rfcsr_write(rt2x00dev
, 48, 0x10);
6504 rt2800_rfcsr_write(rt2x00dev
, 49, 0x94);
6506 rt2800_rfcsr_write(rt2x00dev
, 52, 0x38);
6507 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390F
))
6508 rt2800_rfcsr_write(rt2x00dev
, 53, 0x00);
6510 rt2800_rfcsr_write(rt2x00dev
, 53, 0x84);
6511 rt2800_rfcsr_write(rt2x00dev
, 54, 0x78);
6512 rt2800_rfcsr_write(rt2x00dev
, 55, 0x44);
6513 rt2800_rfcsr_write(rt2x00dev
, 56, 0x22);
6514 rt2800_rfcsr_write(rt2x00dev
, 57, 0x80);
6515 rt2800_rfcsr_write(rt2x00dev
, 58, 0x7f);
6516 rt2800_rfcsr_write(rt2x00dev
, 59, 0x8f);
6518 rt2800_rfcsr_write(rt2x00dev
, 60, 0x45);
6519 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390F
))
6520 rt2800_rfcsr_write(rt2x00dev
, 61, 0xd1);
6522 rt2800_rfcsr_write(rt2x00dev
, 61, 0xdd);
6523 rt2800_rfcsr_write(rt2x00dev
, 62, 0x00);
6524 rt2800_rfcsr_write(rt2x00dev
, 63, 0x00);
6526 rt2800_normal_mode_setup_5xxx(rt2x00dev
);
6528 rt2800_led_open_drain_enable(rt2x00dev
);
6531 static void rt2800_init_rfcsr_5392(struct rt2x00_dev
*rt2x00dev
)
6533 rt2800_rf_init_calibration(rt2x00dev
, 2);
6535 rt2800_rfcsr_write(rt2x00dev
, 1, 0x17);
6536 rt2800_rfcsr_write(rt2x00dev
, 3, 0x88);
6537 rt2800_rfcsr_write(rt2x00dev
, 5, 0x10);
6538 rt2800_rfcsr_write(rt2x00dev
, 6, 0xe0);
6539 rt2800_rfcsr_write(rt2x00dev
, 7, 0x00);
6540 rt2800_rfcsr_write(rt2x00dev
, 10, 0x53);
6541 rt2800_rfcsr_write(rt2x00dev
, 11, 0x4a);
6542 rt2800_rfcsr_write(rt2x00dev
, 12, 0x46);
6543 rt2800_rfcsr_write(rt2x00dev
, 13, 0x9f);
6544 rt2800_rfcsr_write(rt2x00dev
, 14, 0x00);
6545 rt2800_rfcsr_write(rt2x00dev
, 15, 0x00);
6546 rt2800_rfcsr_write(rt2x00dev
, 16, 0x00);
6547 rt2800_rfcsr_write(rt2x00dev
, 18, 0x03);
6548 rt2800_rfcsr_write(rt2x00dev
, 19, 0x4d);
6549 rt2800_rfcsr_write(rt2x00dev
, 20, 0x00);
6550 rt2800_rfcsr_write(rt2x00dev
, 21, 0x8d);
6551 rt2800_rfcsr_write(rt2x00dev
, 22, 0x20);
6552 rt2800_rfcsr_write(rt2x00dev
, 23, 0x0b);
6553 rt2800_rfcsr_write(rt2x00dev
, 24, 0x44);
6554 rt2800_rfcsr_write(rt2x00dev
, 25, 0x80);
6555 rt2800_rfcsr_write(rt2x00dev
, 26, 0x82);
6556 rt2800_rfcsr_write(rt2x00dev
, 27, 0x09);
6557 rt2800_rfcsr_write(rt2x00dev
, 28, 0x00);
6558 rt2800_rfcsr_write(rt2x00dev
, 29, 0x10);
6559 rt2800_rfcsr_write(rt2x00dev
, 30, 0x10);
6560 rt2800_rfcsr_write(rt2x00dev
, 31, 0x80);
6561 rt2800_rfcsr_write(rt2x00dev
, 32, 0x20);
6562 rt2800_rfcsr_write(rt2x00dev
, 33, 0xC0);
6563 rt2800_rfcsr_write(rt2x00dev
, 34, 0x07);
6564 rt2800_rfcsr_write(rt2x00dev
, 35, 0x12);
6565 rt2800_rfcsr_write(rt2x00dev
, 36, 0x00);
6566 rt2800_rfcsr_write(rt2x00dev
, 37, 0x08);
6567 rt2800_rfcsr_write(rt2x00dev
, 38, 0x89);
6568 rt2800_rfcsr_write(rt2x00dev
, 39, 0x1b);
6569 rt2800_rfcsr_write(rt2x00dev
, 40, 0x0f);
6570 rt2800_rfcsr_write(rt2x00dev
, 41, 0xbb);
6571 rt2800_rfcsr_write(rt2x00dev
, 42, 0xd5);
6572 rt2800_rfcsr_write(rt2x00dev
, 43, 0x9b);
6573 rt2800_rfcsr_write(rt2x00dev
, 44, 0x0e);
6574 rt2800_rfcsr_write(rt2x00dev
, 45, 0xa2);
6575 rt2800_rfcsr_write(rt2x00dev
, 46, 0x73);
6576 rt2800_rfcsr_write(rt2x00dev
, 47, 0x0c);
6577 rt2800_rfcsr_write(rt2x00dev
, 48, 0x10);
6578 rt2800_rfcsr_write(rt2x00dev
, 49, 0x94);
6579 rt2800_rfcsr_write(rt2x00dev
, 50, 0x94);
6580 rt2800_rfcsr_write(rt2x00dev
, 51, 0x3a);
6581 rt2800_rfcsr_write(rt2x00dev
, 52, 0x48);
6582 rt2800_rfcsr_write(rt2x00dev
, 53, 0x44);
6583 rt2800_rfcsr_write(rt2x00dev
, 54, 0x38);
6584 rt2800_rfcsr_write(rt2x00dev
, 55, 0x43);
6585 rt2800_rfcsr_write(rt2x00dev
, 56, 0xa1);
6586 rt2800_rfcsr_write(rt2x00dev
, 57, 0x00);
6587 rt2800_rfcsr_write(rt2x00dev
, 58, 0x39);
6588 rt2800_rfcsr_write(rt2x00dev
, 59, 0x07);
6589 rt2800_rfcsr_write(rt2x00dev
, 60, 0x45);
6590 rt2800_rfcsr_write(rt2x00dev
, 61, 0x91);
6591 rt2800_rfcsr_write(rt2x00dev
, 62, 0x39);
6592 rt2800_rfcsr_write(rt2x00dev
, 63, 0x07);
6594 rt2800_normal_mode_setup_5xxx(rt2x00dev
);
6596 rt2800_led_open_drain_enable(rt2x00dev
);
6599 static void rt2800_init_rfcsr_5592(struct rt2x00_dev
*rt2x00dev
)
6601 rt2800_rf_init_calibration(rt2x00dev
, 30);
6603 rt2800_rfcsr_write(rt2x00dev
, 1, 0x3F);
6604 rt2800_rfcsr_write(rt2x00dev
, 3, 0x08);
6605 rt2800_rfcsr_write(rt2x00dev
, 3, 0x08);
6606 rt2800_rfcsr_write(rt2x00dev
, 5, 0x10);
6607 rt2800_rfcsr_write(rt2x00dev
, 6, 0xE4);
6608 rt2800_rfcsr_write(rt2x00dev
, 7, 0x00);
6609 rt2800_rfcsr_write(rt2x00dev
, 14, 0x00);
6610 rt2800_rfcsr_write(rt2x00dev
, 15, 0x00);
6611 rt2800_rfcsr_write(rt2x00dev
, 16, 0x00);
6612 rt2800_rfcsr_write(rt2x00dev
, 18, 0x03);
6613 rt2800_rfcsr_write(rt2x00dev
, 19, 0x4D);
6614 rt2800_rfcsr_write(rt2x00dev
, 20, 0x10);
6615 rt2800_rfcsr_write(rt2x00dev
, 21, 0x8D);
6616 rt2800_rfcsr_write(rt2x00dev
, 26, 0x82);
6617 rt2800_rfcsr_write(rt2x00dev
, 28, 0x00);
6618 rt2800_rfcsr_write(rt2x00dev
, 29, 0x10);
6619 rt2800_rfcsr_write(rt2x00dev
, 33, 0xC0);
6620 rt2800_rfcsr_write(rt2x00dev
, 34, 0x07);
6621 rt2800_rfcsr_write(rt2x00dev
, 35, 0x12);
6622 rt2800_rfcsr_write(rt2x00dev
, 47, 0x0C);
6623 rt2800_rfcsr_write(rt2x00dev
, 53, 0x22);
6624 rt2800_rfcsr_write(rt2x00dev
, 63, 0x07);
6626 rt2800_rfcsr_write(rt2x00dev
, 2, 0x80);
6629 rt2800_adjust_freq_offset(rt2x00dev
);
6631 /* Enable DC filter */
6632 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5592
, REV_RT5592C
))
6633 rt2800_bbp_write(rt2x00dev
, 103, 0xc0);
6635 rt2800_normal_mode_setup_5xxx(rt2x00dev
);
6637 if (rt2x00_rt_rev_lt(rt2x00dev
, RT5592
, REV_RT5592C
))
6638 rt2800_rfcsr_write(rt2x00dev
, 27, 0x03);
6640 rt2800_led_open_drain_enable(rt2x00dev
);
6643 static void rt2800_init_rfcsr(struct rt2x00_dev
*rt2x00dev
)
6645 if (rt2800_is_305x_soc(rt2x00dev
)) {
6646 rt2800_init_rfcsr_305x_soc(rt2x00dev
);
6650 switch (rt2x00dev
->chip
.rt
) {
6654 rt2800_init_rfcsr_30xx(rt2x00dev
);
6657 rt2800_init_rfcsr_3290(rt2x00dev
);
6660 rt2800_init_rfcsr_3352(rt2x00dev
);
6663 rt2800_init_rfcsr_3390(rt2x00dev
);
6666 rt2800_init_rfcsr_3572(rt2x00dev
);
6669 rt2800_init_rfcsr_3593(rt2x00dev
);
6672 rt2800_init_rfcsr_5390(rt2x00dev
);
6675 rt2800_init_rfcsr_5392(rt2x00dev
);
6678 rt2800_init_rfcsr_5592(rt2x00dev
);
6683 int rt2800_enable_radio(struct rt2x00_dev
*rt2x00dev
)
6689 * Initialize MAC registers.
6691 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev
) ||
6692 rt2800_init_registers(rt2x00dev
)))
6696 * Wait BBP/RF to wake up.
6698 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev
)))
6702 * Send signal during boot time to initialize firmware.
6704 rt2800_register_write(rt2x00dev
, H2M_BBP_AGENT
, 0);
6705 rt2800_register_write(rt2x00dev
, H2M_MAILBOX_CSR
, 0);
6706 if (rt2x00_is_usb(rt2x00dev
))
6707 rt2800_register_write(rt2x00dev
, H2M_INT_SRC
, 0);
6708 rt2800_mcu_request(rt2x00dev
, MCU_BOOT_SIGNAL
, 0, 0, 0);
6712 * Make sure BBP is up and running.
6714 if (unlikely(rt2800_wait_bbp_ready(rt2x00dev
)))
6718 * Initialize BBP/RF registers.
6720 rt2800_init_bbp(rt2x00dev
);
6721 rt2800_init_rfcsr(rt2x00dev
);
6723 if (rt2x00_is_usb(rt2x00dev
) &&
6724 (rt2x00_rt(rt2x00dev
, RT3070
) ||
6725 rt2x00_rt(rt2x00dev
, RT3071
) ||
6726 rt2x00_rt(rt2x00dev
, RT3572
))) {
6728 rt2800_mcu_request(rt2x00dev
, MCU_CURRENT
, 0, 0, 0);
6735 rt2800_register_read(rt2x00dev
, MAC_SYS_CTRL
, ®
);
6736 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_TX
, 1);
6737 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_RX
, 0);
6738 rt2800_register_write(rt2x00dev
, MAC_SYS_CTRL
, reg
);
6742 rt2800_register_read(rt2x00dev
, WPDMA_GLO_CFG
, ®
);
6743 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_TX_DMA
, 1);
6744 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_RX_DMA
, 1);
6745 rt2x00_set_field32(®
, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE
, 2);
6746 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_WRITEBACK_DONE
, 1);
6747 rt2800_register_write(rt2x00dev
, WPDMA_GLO_CFG
, reg
);
6749 rt2800_register_read(rt2x00dev
, MAC_SYS_CTRL
, ®
);
6750 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_TX
, 1);
6751 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_RX
, 1);
6752 rt2800_register_write(rt2x00dev
, MAC_SYS_CTRL
, reg
);
6755 * Initialize LED control
6757 rt2800_eeprom_read(rt2x00dev
, EEPROM_LED_AG_CONF
, &word
);
6758 rt2800_mcu_request(rt2x00dev
, MCU_LED_AG_CONF
, 0xff,
6759 word
& 0xff, (word
>> 8) & 0xff);
6761 rt2800_eeprom_read(rt2x00dev
, EEPROM_LED_ACT_CONF
, &word
);
6762 rt2800_mcu_request(rt2x00dev
, MCU_LED_ACT_CONF
, 0xff,
6763 word
& 0xff, (word
>> 8) & 0xff);
6765 rt2800_eeprom_read(rt2x00dev
, EEPROM_LED_POLARITY
, &word
);
6766 rt2800_mcu_request(rt2x00dev
, MCU_LED_LED_POLARITY
, 0xff,
6767 word
& 0xff, (word
>> 8) & 0xff);
6771 EXPORT_SYMBOL_GPL(rt2800_enable_radio
);
6773 void rt2800_disable_radio(struct rt2x00_dev
*rt2x00dev
)
6777 rt2800_disable_wpdma(rt2x00dev
);
6779 /* Wait for DMA, ignore error */
6780 rt2800_wait_wpdma_ready(rt2x00dev
);
6782 rt2800_register_read(rt2x00dev
, MAC_SYS_CTRL
, ®
);
6783 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_TX
, 0);
6784 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_RX
, 0);
6785 rt2800_register_write(rt2x00dev
, MAC_SYS_CTRL
, reg
);
6787 EXPORT_SYMBOL_GPL(rt2800_disable_radio
);
6789 int rt2800_efuse_detect(struct rt2x00_dev
*rt2x00dev
)
6794 if (rt2x00_rt(rt2x00dev
, RT3290
))
6795 efuse_ctrl_reg
= EFUSE_CTRL_3290
;
6797 efuse_ctrl_reg
= EFUSE_CTRL
;
6799 rt2800_register_read(rt2x00dev
, efuse_ctrl_reg
, ®
);
6800 return rt2x00_get_field32(reg
, EFUSE_CTRL_PRESENT
);
6802 EXPORT_SYMBOL_GPL(rt2800_efuse_detect
);
6804 static void rt2800_efuse_read(struct rt2x00_dev
*rt2x00dev
, unsigned int i
)
6808 u16 efuse_data0_reg
;
6809 u16 efuse_data1_reg
;
6810 u16 efuse_data2_reg
;
6811 u16 efuse_data3_reg
;
6813 if (rt2x00_rt(rt2x00dev
, RT3290
)) {
6814 efuse_ctrl_reg
= EFUSE_CTRL_3290
;
6815 efuse_data0_reg
= EFUSE_DATA0_3290
;
6816 efuse_data1_reg
= EFUSE_DATA1_3290
;
6817 efuse_data2_reg
= EFUSE_DATA2_3290
;
6818 efuse_data3_reg
= EFUSE_DATA3_3290
;
6820 efuse_ctrl_reg
= EFUSE_CTRL
;
6821 efuse_data0_reg
= EFUSE_DATA0
;
6822 efuse_data1_reg
= EFUSE_DATA1
;
6823 efuse_data2_reg
= EFUSE_DATA2
;
6824 efuse_data3_reg
= EFUSE_DATA3
;
6826 mutex_lock(&rt2x00dev
->csr_mutex
);
6828 rt2800_register_read_lock(rt2x00dev
, efuse_ctrl_reg
, ®
);
6829 rt2x00_set_field32(®
, EFUSE_CTRL_ADDRESS_IN
, i
);
6830 rt2x00_set_field32(®
, EFUSE_CTRL_MODE
, 0);
6831 rt2x00_set_field32(®
, EFUSE_CTRL_KICK
, 1);
6832 rt2800_register_write_lock(rt2x00dev
, efuse_ctrl_reg
, reg
);
6834 /* Wait until the EEPROM has been loaded */
6835 rt2800_regbusy_read(rt2x00dev
, efuse_ctrl_reg
, EFUSE_CTRL_KICK
, ®
);
6836 /* Apparently the data is read from end to start */
6837 rt2800_register_read_lock(rt2x00dev
, efuse_data3_reg
, ®
);
6838 /* The returned value is in CPU order, but eeprom is le */
6839 *(u32
*)&rt2x00dev
->eeprom
[i
] = cpu_to_le32(reg
);
6840 rt2800_register_read_lock(rt2x00dev
, efuse_data2_reg
, ®
);
6841 *(u32
*)&rt2x00dev
->eeprom
[i
+ 2] = cpu_to_le32(reg
);
6842 rt2800_register_read_lock(rt2x00dev
, efuse_data1_reg
, ®
);
6843 *(u32
*)&rt2x00dev
->eeprom
[i
+ 4] = cpu_to_le32(reg
);
6844 rt2800_register_read_lock(rt2x00dev
, efuse_data0_reg
, ®
);
6845 *(u32
*)&rt2x00dev
->eeprom
[i
+ 6] = cpu_to_le32(reg
);
6847 mutex_unlock(&rt2x00dev
->csr_mutex
);
6850 int rt2800_read_eeprom_efuse(struct rt2x00_dev
*rt2x00dev
)
6854 for (i
= 0; i
< EEPROM_SIZE
/ sizeof(u16
); i
+= 8)
6855 rt2800_efuse_read(rt2x00dev
, i
);
6859 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse
);
6861 static u8
rt2800_get_txmixer_gain_24g(struct rt2x00_dev
*rt2x00dev
)
6865 if (rt2x00_rt(rt2x00dev
, RT3593
))
6868 rt2800_eeprom_read(rt2x00dev
, EEPROM_TXMIXER_GAIN_BG
, &word
);
6869 if ((word
& 0x00ff) != 0x00ff)
6870 return rt2x00_get_field16(word
, EEPROM_TXMIXER_GAIN_BG_VAL
);
6875 static u8
rt2800_get_txmixer_gain_5g(struct rt2x00_dev
*rt2x00dev
)
6879 if (rt2x00_rt(rt2x00dev
, RT3593
))
6882 rt2800_eeprom_read(rt2x00dev
, EEPROM_TXMIXER_GAIN_A
, &word
);
6883 if ((word
& 0x00ff) != 0x00ff)
6884 return rt2x00_get_field16(word
, EEPROM_TXMIXER_GAIN_A_VAL
);
6889 static int rt2800_validate_eeprom(struct rt2x00_dev
*rt2x00dev
)
6891 struct rt2800_drv_data
*drv_data
= rt2x00dev
->drv_data
;
6894 u8 default_lna_gain
;
6900 retval
= rt2800_read_eeprom(rt2x00dev
);
6905 * Start validation of the data that has been read.
6907 mac
= rt2800_eeprom_addr(rt2x00dev
, EEPROM_MAC_ADDR_0
);
6908 if (!is_valid_ether_addr(mac
)) {
6909 eth_random_addr(mac
);
6910 rt2x00_eeprom_dbg(rt2x00dev
, "MAC: %pM\n", mac
);
6913 rt2800_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF0
, &word
);
6914 if (word
== 0xffff) {
6915 rt2x00_set_field16(&word
, EEPROM_NIC_CONF0_RXPATH
, 2);
6916 rt2x00_set_field16(&word
, EEPROM_NIC_CONF0_TXPATH
, 1);
6917 rt2x00_set_field16(&word
, EEPROM_NIC_CONF0_RF_TYPE
, RF2820
);
6918 rt2800_eeprom_write(rt2x00dev
, EEPROM_NIC_CONF0
, word
);
6919 rt2x00_eeprom_dbg(rt2x00dev
, "Antenna: 0x%04x\n", word
);
6920 } else if (rt2x00_rt(rt2x00dev
, RT2860
) ||
6921 rt2x00_rt(rt2x00dev
, RT2872
)) {
6923 * There is a max of 2 RX streams for RT28x0 series
6925 if (rt2x00_get_field16(word
, EEPROM_NIC_CONF0_RXPATH
) > 2)
6926 rt2x00_set_field16(&word
, EEPROM_NIC_CONF0_RXPATH
, 2);
6927 rt2800_eeprom_write(rt2x00dev
, EEPROM_NIC_CONF0
, word
);
6930 rt2800_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF1
, &word
);
6931 if (word
== 0xffff) {
6932 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_HW_RADIO
, 0);
6933 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC
, 0);
6934 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G
, 0);
6935 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G
, 0);
6936 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_CARDBUS_ACCEL
, 0);
6937 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_BW40M_SB_2G
, 0);
6938 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_BW40M_SB_5G
, 0);
6939 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_WPS_PBC
, 0);
6940 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_BW40M_2G
, 0);
6941 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_BW40M_5G
, 0);
6942 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA
, 0);
6943 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_ANT_DIVERSITY
, 0);
6944 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_INTERNAL_TX_ALC
, 0);
6945 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_BT_COEXIST
, 0);
6946 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_DAC_TEST
, 0);
6947 rt2800_eeprom_write(rt2x00dev
, EEPROM_NIC_CONF1
, word
);
6948 rt2x00_eeprom_dbg(rt2x00dev
, "NIC: 0x%04x\n", word
);
6951 rt2800_eeprom_read(rt2x00dev
, EEPROM_FREQ
, &word
);
6952 if ((word
& 0x00ff) == 0x00ff) {
6953 rt2x00_set_field16(&word
, EEPROM_FREQ_OFFSET
, 0);
6954 rt2800_eeprom_write(rt2x00dev
, EEPROM_FREQ
, word
);
6955 rt2x00_eeprom_dbg(rt2x00dev
, "Freq: 0x%04x\n", word
);
6957 if ((word
& 0xff00) == 0xff00) {
6958 rt2x00_set_field16(&word
, EEPROM_FREQ_LED_MODE
,
6959 LED_MODE_TXRX_ACTIVITY
);
6960 rt2x00_set_field16(&word
, EEPROM_FREQ_LED_POLARITY
, 0);
6961 rt2800_eeprom_write(rt2x00dev
, EEPROM_FREQ
, word
);
6962 rt2800_eeprom_write(rt2x00dev
, EEPROM_LED_AG_CONF
, 0x5555);
6963 rt2800_eeprom_write(rt2x00dev
, EEPROM_LED_ACT_CONF
, 0x2221);
6964 rt2800_eeprom_write(rt2x00dev
, EEPROM_LED_POLARITY
, 0xa9f8);
6965 rt2x00_eeprom_dbg(rt2x00dev
, "Led Mode: 0x%04x\n", word
);
6969 * During the LNA validation we are going to use
6970 * lna0 as correct value. Note that EEPROM_LNA
6971 * is never validated.
6973 rt2800_eeprom_read(rt2x00dev
, EEPROM_LNA
, &word
);
6974 default_lna_gain
= rt2x00_get_field16(word
, EEPROM_LNA_A0
);
6976 rt2800_eeprom_read(rt2x00dev
, EEPROM_RSSI_BG
, &word
);
6977 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_BG_OFFSET0
)) > 10)
6978 rt2x00_set_field16(&word
, EEPROM_RSSI_BG_OFFSET0
, 0);
6979 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_BG_OFFSET1
)) > 10)
6980 rt2x00_set_field16(&word
, EEPROM_RSSI_BG_OFFSET1
, 0);
6981 rt2800_eeprom_write(rt2x00dev
, EEPROM_RSSI_BG
, word
);
6983 drv_data
->txmixer_gain_24g
= rt2800_get_txmixer_gain_24g(rt2x00dev
);
6985 rt2800_eeprom_read(rt2x00dev
, EEPROM_RSSI_BG2
, &word
);
6986 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_BG2_OFFSET2
)) > 10)
6987 rt2x00_set_field16(&word
, EEPROM_RSSI_BG2_OFFSET2
, 0);
6988 if (!rt2x00_rt(rt2x00dev
, RT3593
)) {
6989 if (rt2x00_get_field16(word
, EEPROM_RSSI_BG2_LNA_A1
) == 0x00 ||
6990 rt2x00_get_field16(word
, EEPROM_RSSI_BG2_LNA_A1
) == 0xff)
6991 rt2x00_set_field16(&word
, EEPROM_RSSI_BG2_LNA_A1
,
6994 rt2800_eeprom_write(rt2x00dev
, EEPROM_RSSI_BG2
, word
);
6996 drv_data
->txmixer_gain_5g
= rt2800_get_txmixer_gain_5g(rt2x00dev
);
6998 rt2800_eeprom_read(rt2x00dev
, EEPROM_RSSI_A
, &word
);
6999 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_A_OFFSET0
)) > 10)
7000 rt2x00_set_field16(&word
, EEPROM_RSSI_A_OFFSET0
, 0);
7001 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_A_OFFSET1
)) > 10)
7002 rt2x00_set_field16(&word
, EEPROM_RSSI_A_OFFSET1
, 0);
7003 rt2800_eeprom_write(rt2x00dev
, EEPROM_RSSI_A
, word
);
7005 rt2800_eeprom_read(rt2x00dev
, EEPROM_RSSI_A2
, &word
);
7006 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_A2_OFFSET2
)) > 10)
7007 rt2x00_set_field16(&word
, EEPROM_RSSI_A2_OFFSET2
, 0);
7008 if (!rt2x00_rt(rt2x00dev
, RT3593
)) {
7009 if (rt2x00_get_field16(word
, EEPROM_RSSI_A2_LNA_A2
) == 0x00 ||
7010 rt2x00_get_field16(word
, EEPROM_RSSI_A2_LNA_A2
) == 0xff)
7011 rt2x00_set_field16(&word
, EEPROM_RSSI_A2_LNA_A2
,
7014 rt2800_eeprom_write(rt2x00dev
, EEPROM_RSSI_A2
, word
);
7016 if (rt2x00_rt(rt2x00dev
, RT3593
)) {
7017 rt2800_eeprom_read(rt2x00dev
, EEPROM_EXT_LNA2
, &word
);
7018 if (rt2x00_get_field16(word
, EEPROM_EXT_LNA2_A1
) == 0x00 ||
7019 rt2x00_get_field16(word
, EEPROM_EXT_LNA2_A1
) == 0xff)
7020 rt2x00_set_field16(&word
, EEPROM_EXT_LNA2_A1
,
7022 if (rt2x00_get_field16(word
, EEPROM_EXT_LNA2_A2
) == 0x00 ||
7023 rt2x00_get_field16(word
, EEPROM_EXT_LNA2_A2
) == 0xff)
7024 rt2x00_set_field16(&word
, EEPROM_EXT_LNA2_A1
,
7026 rt2800_eeprom_write(rt2x00dev
, EEPROM_EXT_LNA2
, word
);
7032 static int rt2800_init_eeprom(struct rt2x00_dev
*rt2x00dev
)
7039 * Read EEPROM word for configuration.
7041 rt2800_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF0
, &eeprom
);
7044 * Identify RF chipset by EEPROM value
7045 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
7046 * RT53xx: defined in "EEPROM_CHIP_ID" field
7048 if (rt2x00_rt(rt2x00dev
, RT3290
) ||
7049 rt2x00_rt(rt2x00dev
, RT5390
) ||
7050 rt2x00_rt(rt2x00dev
, RT5392
))
7051 rt2800_eeprom_read(rt2x00dev
, EEPROM_CHIP_ID
, &rf
);
7053 rf
= rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_RF_TYPE
);
7078 rt2x00_err(rt2x00dev
, "Invalid RF chipset 0x%04x detected\n",
7083 rt2x00_set_rf(rt2x00dev
, rf
);
7086 * Identify default antenna configuration.
7088 rt2x00dev
->default_ant
.tx_chain_num
=
7089 rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_TXPATH
);
7090 rt2x00dev
->default_ant
.rx_chain_num
=
7091 rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_RXPATH
);
7093 rt2800_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF1
, &eeprom
);
7095 if (rt2x00_rt(rt2x00dev
, RT3070
) ||
7096 rt2x00_rt(rt2x00dev
, RT3090
) ||
7097 rt2x00_rt(rt2x00dev
, RT3352
) ||
7098 rt2x00_rt(rt2x00dev
, RT3390
)) {
7099 value
= rt2x00_get_field16(eeprom
,
7100 EEPROM_NIC_CONF1_ANT_DIVERSITY
);
7105 rt2x00dev
->default_ant
.tx
= ANTENNA_A
;
7106 rt2x00dev
->default_ant
.rx
= ANTENNA_A
;
7109 rt2x00dev
->default_ant
.tx
= ANTENNA_A
;
7110 rt2x00dev
->default_ant
.rx
= ANTENNA_B
;
7114 rt2x00dev
->default_ant
.tx
= ANTENNA_A
;
7115 rt2x00dev
->default_ant
.rx
= ANTENNA_A
;
7118 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390R
)) {
7119 rt2x00dev
->default_ant
.tx
= ANTENNA_HW_DIVERSITY
; /* Unused */
7120 rt2x00dev
->default_ant
.rx
= ANTENNA_HW_DIVERSITY
; /* Unused */
7124 * Determine external LNA informations.
7126 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G
))
7127 __set_bit(CAPABILITY_EXTERNAL_LNA_A
, &rt2x00dev
->cap_flags
);
7128 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G
))
7129 __set_bit(CAPABILITY_EXTERNAL_LNA_BG
, &rt2x00dev
->cap_flags
);
7132 * Detect if this device has an hardware controlled radio.
7134 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF1_HW_RADIO
))
7135 __set_bit(CAPABILITY_HW_BUTTON
, &rt2x00dev
->cap_flags
);
7138 * Detect if this device has Bluetooth co-existence.
7140 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF1_BT_COEXIST
))
7141 __set_bit(CAPABILITY_BT_COEXIST
, &rt2x00dev
->cap_flags
);
7144 * Read frequency offset and RF programming sequence.
7146 rt2800_eeprom_read(rt2x00dev
, EEPROM_FREQ
, &eeprom
);
7147 rt2x00dev
->freq_offset
= rt2x00_get_field16(eeprom
, EEPROM_FREQ_OFFSET
);
7150 * Store led settings, for correct led behaviour.
7152 #ifdef CONFIG_RT2X00_LIB_LEDS
7153 rt2800_init_led(rt2x00dev
, &rt2x00dev
->led_radio
, LED_TYPE_RADIO
);
7154 rt2800_init_led(rt2x00dev
, &rt2x00dev
->led_assoc
, LED_TYPE_ASSOC
);
7155 rt2800_init_led(rt2x00dev
, &rt2x00dev
->led_qual
, LED_TYPE_QUALITY
);
7157 rt2x00dev
->led_mcu_reg
= eeprom
;
7158 #endif /* CONFIG_RT2X00_LIB_LEDS */
7161 * Check if support EIRP tx power limit feature.
7163 rt2800_eeprom_read(rt2x00dev
, EEPROM_EIRP_MAX_TX_POWER
, &eeprom
);
7165 if (rt2x00_get_field16(eeprom
, EEPROM_EIRP_MAX_TX_POWER_2GHZ
) <
7166 EIRP_MAX_TX_POWER_LIMIT
)
7167 __set_bit(CAPABILITY_POWER_LIMIT
, &rt2x00dev
->cap_flags
);
7173 * RF value list for rt28xx
7174 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
7176 static const struct rf_channel rf_vals
[] = {
7177 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
7178 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
7179 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
7180 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
7181 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
7182 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
7183 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
7184 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
7185 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
7186 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
7187 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
7188 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
7189 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
7190 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
7192 /* 802.11 UNI / HyperLan 2 */
7193 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
7194 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
7195 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
7196 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
7197 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
7198 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
7199 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
7200 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
7201 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
7202 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
7203 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
7204 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
7206 /* 802.11 HyperLan 2 */
7207 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
7208 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
7209 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
7210 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
7211 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
7212 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
7213 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
7214 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
7215 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
7216 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
7217 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
7218 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
7219 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
7220 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
7221 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
7222 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
7225 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
7226 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
7227 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
7228 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
7229 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
7230 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
7231 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
7232 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
7233 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
7234 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
7235 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
7238 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
7239 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
7240 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
7241 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
7242 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
7243 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
7244 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
7248 * RF value list for rt3xxx
7249 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052 & RF3053)
7251 static const struct rf_channel rf_vals_3x
[] = {
7267 /* 802.11 UNI / HyperLan 2 */
7281 /* 802.11 HyperLan 2 */
7313 static const struct rf_channel rf_vals_5592_xtal20
[] = {
7314 /* Channel, N, K, mod, R */
7324 {10, 491, 4, 10, 3},
7325 {11, 492, 4, 10, 3},
7326 {12, 493, 4, 10, 3},
7327 {13, 494, 4, 10, 3},
7328 {14, 496, 8, 10, 3},
7329 {36, 172, 8, 12, 1},
7330 {38, 173, 0, 12, 1},
7331 {40, 173, 4, 12, 1},
7332 {42, 173, 8, 12, 1},
7333 {44, 174, 0, 12, 1},
7334 {46, 174, 4, 12, 1},
7335 {48, 174, 8, 12, 1},
7336 {50, 175, 0, 12, 1},
7337 {52, 175, 4, 12, 1},
7338 {54, 175, 8, 12, 1},
7339 {56, 176, 0, 12, 1},
7340 {58, 176, 4, 12, 1},
7341 {60, 176, 8, 12, 1},
7342 {62, 177, 0, 12, 1},
7343 {64, 177, 4, 12, 1},
7344 {100, 183, 4, 12, 1},
7345 {102, 183, 8, 12, 1},
7346 {104, 184, 0, 12, 1},
7347 {106, 184, 4, 12, 1},
7348 {108, 184, 8, 12, 1},
7349 {110, 185, 0, 12, 1},
7350 {112, 185, 4, 12, 1},
7351 {114, 185, 8, 12, 1},
7352 {116, 186, 0, 12, 1},
7353 {118, 186, 4, 12, 1},
7354 {120, 186, 8, 12, 1},
7355 {122, 187, 0, 12, 1},
7356 {124, 187, 4, 12, 1},
7357 {126, 187, 8, 12, 1},
7358 {128, 188, 0, 12, 1},
7359 {130, 188, 4, 12, 1},
7360 {132, 188, 8, 12, 1},
7361 {134, 189, 0, 12, 1},
7362 {136, 189, 4, 12, 1},
7363 {138, 189, 8, 12, 1},
7364 {140, 190, 0, 12, 1},
7365 {149, 191, 6, 12, 1},
7366 {151, 191, 10, 12, 1},
7367 {153, 192, 2, 12, 1},
7368 {155, 192, 6, 12, 1},
7369 {157, 192, 10, 12, 1},
7370 {159, 193, 2, 12, 1},
7371 {161, 193, 6, 12, 1},
7372 {165, 194, 2, 12, 1},
7373 {184, 164, 0, 12, 1},
7374 {188, 164, 4, 12, 1},
7375 {192, 165, 8, 12, 1},
7376 {196, 166, 0, 12, 1},
7379 static const struct rf_channel rf_vals_5592_xtal40
[] = {
7380 /* Channel, N, K, mod, R */
7390 {10, 245, 7, 10, 3},
7391 {11, 246, 2, 10, 3},
7392 {12, 246, 7, 10, 3},
7393 {13, 247, 2, 10, 3},
7394 {14, 248, 4, 10, 3},
7398 {42, 86, 10, 12, 1},
7404 {54, 87, 10, 12, 1},
7410 {100, 91, 8, 12, 1},
7411 {102, 91, 10, 12, 1},
7412 {104, 92, 0, 12, 1},
7413 {106, 92, 2, 12, 1},
7414 {108, 92, 4, 12, 1},
7415 {110, 92, 6, 12, 1},
7416 {112, 92, 8, 12, 1},
7417 {114, 92, 10, 12, 1},
7418 {116, 93, 0, 12, 1},
7419 {118, 93, 2, 12, 1},
7420 {120, 93, 4, 12, 1},
7421 {122, 93, 6, 12, 1},
7422 {124, 93, 8, 12, 1},
7423 {126, 93, 10, 12, 1},
7424 {128, 94, 0, 12, 1},
7425 {130, 94, 2, 12, 1},
7426 {132, 94, 4, 12, 1},
7427 {134, 94, 6, 12, 1},
7428 {136, 94, 8, 12, 1},
7429 {138, 94, 10, 12, 1},
7430 {140, 95, 0, 12, 1},
7431 {149, 95, 9, 12, 1},
7432 {151, 95, 11, 12, 1},
7433 {153, 96, 1, 12, 1},
7434 {155, 96, 3, 12, 1},
7435 {157, 96, 5, 12, 1},
7436 {159, 96, 7, 12, 1},
7437 {161, 96, 9, 12, 1},
7438 {165, 97, 1, 12, 1},
7439 {184, 82, 0, 12, 1},
7440 {188, 82, 4, 12, 1},
7441 {192, 82, 8, 12, 1},
7442 {196, 83, 0, 12, 1},
7445 static int rt2800_probe_hw_mode(struct rt2x00_dev
*rt2x00dev
)
7447 struct hw_mode_spec
*spec
= &rt2x00dev
->spec
;
7448 struct channel_info
*info
;
7449 char *default_power1
;
7450 char *default_power2
;
7451 char *default_power3
;
7456 * Disable powersaving as default on PCI devices.
7458 if (rt2x00_is_pci(rt2x00dev
) || rt2x00_is_soc(rt2x00dev
))
7459 rt2x00dev
->hw
->wiphy
->flags
&= ~WIPHY_FLAG_PS_ON_BY_DEFAULT
;
7462 * Initialize all hw fields.
7464 rt2x00dev
->hw
->flags
=
7465 IEEE80211_HW_SIGNAL_DBM
|
7466 IEEE80211_HW_SUPPORTS_PS
|
7467 IEEE80211_HW_PS_NULLFUNC_STACK
|
7468 IEEE80211_HW_AMPDU_AGGREGATION
|
7469 IEEE80211_HW_REPORTS_TX_ACK_STATUS
|
7470 IEEE80211_HW_SUPPORTS_HT_CCK_RATES
;
7473 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
7474 * unless we are capable of sending the buffered frames out after the
7475 * DTIM transmission using rt2x00lib_beacondone. This will send out
7476 * multicast and broadcast traffic immediately instead of buffering it
7477 * infinitly and thus dropping it after some time.
7479 if (!rt2x00_is_usb(rt2x00dev
))
7480 rt2x00dev
->hw
->flags
|=
7481 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING
;
7483 SET_IEEE80211_DEV(rt2x00dev
->hw
, rt2x00dev
->dev
);
7484 SET_IEEE80211_PERM_ADDR(rt2x00dev
->hw
,
7485 rt2800_eeprom_addr(rt2x00dev
,
7486 EEPROM_MAC_ADDR_0
));
7489 * As rt2800 has a global fallback table we cannot specify
7490 * more then one tx rate per frame but since the hw will
7491 * try several rates (based on the fallback table) we should
7492 * initialize max_report_rates to the maximum number of rates
7493 * we are going to try. Otherwise mac80211 will truncate our
7494 * reported tx rates and the rc algortihm will end up with
7497 rt2x00dev
->hw
->max_rates
= 1;
7498 rt2x00dev
->hw
->max_report_rates
= 7;
7499 rt2x00dev
->hw
->max_rate_tries
= 1;
7502 * Initialize hw_mode information.
7504 spec
->supported_rates
= SUPPORT_RATE_CCK
| SUPPORT_RATE_OFDM
;
7506 switch (rt2x00dev
->chip
.rf
) {
7509 spec
->num_channels
= 14;
7510 spec
->channels
= rf_vals
;
7515 spec
->num_channels
= ARRAY_SIZE(rf_vals
);
7516 spec
->channels
= rf_vals
;
7532 spec
->num_channels
= 14;
7533 spec
->channels
= rf_vals_3x
;
7538 spec
->num_channels
= ARRAY_SIZE(rf_vals_3x
);
7539 spec
->channels
= rf_vals_3x
;
7543 rt2800_register_read(rt2x00dev
, MAC_DEBUG_INDEX
, ®
);
7544 if (rt2x00_get_field32(reg
, MAC_DEBUG_INDEX_XTAL
)) {
7545 spec
->num_channels
= ARRAY_SIZE(rf_vals_5592_xtal40
);
7546 spec
->channels
= rf_vals_5592_xtal40
;
7548 spec
->num_channels
= ARRAY_SIZE(rf_vals_5592_xtal20
);
7549 spec
->channels
= rf_vals_5592_xtal20
;
7554 if (WARN_ON_ONCE(!spec
->channels
))
7557 spec
->supported_bands
= SUPPORT_BAND_2GHZ
;
7558 if (spec
->num_channels
> 14)
7559 spec
->supported_bands
|= SUPPORT_BAND_5GHZ
;
7562 * Initialize HT information.
7564 if (!rt2x00_rf(rt2x00dev
, RF2020
))
7565 spec
->ht
.ht_supported
= true;
7567 spec
->ht
.ht_supported
= false;
7570 IEEE80211_HT_CAP_SUP_WIDTH_20_40
|
7571 IEEE80211_HT_CAP_GRN_FLD
|
7572 IEEE80211_HT_CAP_SGI_20
|
7573 IEEE80211_HT_CAP_SGI_40
;
7575 if (rt2x00dev
->default_ant
.tx_chain_num
>= 2)
7576 spec
->ht
.cap
|= IEEE80211_HT_CAP_TX_STBC
;
7578 spec
->ht
.cap
|= rt2x00dev
->default_ant
.rx_chain_num
<<
7579 IEEE80211_HT_CAP_RX_STBC_SHIFT
;
7581 spec
->ht
.ampdu_factor
= 3;
7582 spec
->ht
.ampdu_density
= 4;
7583 spec
->ht
.mcs
.tx_params
=
7584 IEEE80211_HT_MCS_TX_DEFINED
|
7585 IEEE80211_HT_MCS_TX_RX_DIFF
|
7586 ((rt2x00dev
->default_ant
.tx_chain_num
- 1) <<
7587 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT
);
7589 switch (rt2x00dev
->default_ant
.rx_chain_num
) {
7591 spec
->ht
.mcs
.rx_mask
[2] = 0xff;
7593 spec
->ht
.mcs
.rx_mask
[1] = 0xff;
7595 spec
->ht
.mcs
.rx_mask
[0] = 0xff;
7596 spec
->ht
.mcs
.rx_mask
[4] = 0x1; /* MCS32 */
7601 * Create channel information array
7603 info
= kcalloc(spec
->num_channels
, sizeof(*info
), GFP_KERNEL
);
7607 spec
->channels_info
= info
;
7609 default_power1
= rt2800_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_BG1
);
7610 default_power2
= rt2800_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_BG2
);
7612 if (rt2x00dev
->default_ant
.tx_chain_num
> 2)
7613 default_power3
= rt2800_eeprom_addr(rt2x00dev
,
7614 EEPROM_EXT_TXPOWER_BG3
);
7616 default_power3
= NULL
;
7618 for (i
= 0; i
< 14; i
++) {
7619 info
[i
].default_power1
= default_power1
[i
];
7620 info
[i
].default_power2
= default_power2
[i
];
7622 info
[i
].default_power3
= default_power3
[i
];
7625 if (spec
->num_channels
> 14) {
7626 default_power1
= rt2800_eeprom_addr(rt2x00dev
,
7628 default_power2
= rt2800_eeprom_addr(rt2x00dev
,
7631 if (rt2x00dev
->default_ant
.tx_chain_num
> 2)
7633 rt2800_eeprom_addr(rt2x00dev
,
7634 EEPROM_EXT_TXPOWER_A3
);
7636 default_power3
= NULL
;
7638 for (i
= 14; i
< spec
->num_channels
; i
++) {
7639 info
[i
].default_power1
= default_power1
[i
- 14];
7640 info
[i
].default_power2
= default_power2
[i
- 14];
7642 info
[i
].default_power3
= default_power3
[i
- 14];
7646 switch (rt2x00dev
->chip
.rf
) {
7661 __set_bit(CAPABILITY_VCO_RECALIBRATION
, &rt2x00dev
->cap_flags
);
7668 static int rt2800_probe_rt(struct rt2x00_dev
*rt2x00dev
)
7674 if (rt2x00_rt(rt2x00dev
, RT3290
))
7675 rt2800_register_read(rt2x00dev
, MAC_CSR0_3290
, ®
);
7677 rt2800_register_read(rt2x00dev
, MAC_CSR0
, ®
);
7679 rt
= rt2x00_get_field32(reg
, MAC_CSR0_CHIPSET
);
7680 rev
= rt2x00_get_field32(reg
, MAC_CSR0_REVISION
);
7699 rt2x00_err(rt2x00dev
, "Invalid RT chipset 0x%04x, rev %04x detected\n",
7704 rt2x00_set_rt(rt2x00dev
, rt
, rev
);
7709 int rt2800_probe_hw(struct rt2x00_dev
*rt2x00dev
)
7714 retval
= rt2800_probe_rt(rt2x00dev
);
7719 * Allocate eeprom data.
7721 retval
= rt2800_validate_eeprom(rt2x00dev
);
7725 retval
= rt2800_init_eeprom(rt2x00dev
);
7730 * Enable rfkill polling by setting GPIO direction of the
7731 * rfkill switch GPIO pin correctly.
7733 rt2800_register_read(rt2x00dev
, GPIO_CTRL
, ®
);
7734 rt2x00_set_field32(®
, GPIO_CTRL_DIR2
, 1);
7735 rt2800_register_write(rt2x00dev
, GPIO_CTRL
, reg
);
7738 * Initialize hw specifications.
7740 retval
= rt2800_probe_hw_mode(rt2x00dev
);
7745 * Set device capabilities.
7747 __set_bit(CAPABILITY_CONTROL_FILTERS
, &rt2x00dev
->cap_flags
);
7748 __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL
, &rt2x00dev
->cap_flags
);
7749 if (!rt2x00_is_usb(rt2x00dev
))
7750 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT
, &rt2x00dev
->cap_flags
);
7753 * Set device requirements.
7755 if (!rt2x00_is_soc(rt2x00dev
))
7756 __set_bit(REQUIRE_FIRMWARE
, &rt2x00dev
->cap_flags
);
7757 __set_bit(REQUIRE_L2PAD
, &rt2x00dev
->cap_flags
);
7758 __set_bit(REQUIRE_TXSTATUS_FIFO
, &rt2x00dev
->cap_flags
);
7759 if (!rt2800_hwcrypt_disabled(rt2x00dev
))
7760 __set_bit(CAPABILITY_HW_CRYPTO
, &rt2x00dev
->cap_flags
);
7761 __set_bit(CAPABILITY_LINK_TUNING
, &rt2x00dev
->cap_flags
);
7762 __set_bit(REQUIRE_HT_TX_DESC
, &rt2x00dev
->cap_flags
);
7763 if (rt2x00_is_usb(rt2x00dev
))
7764 __set_bit(REQUIRE_PS_AUTOWAKE
, &rt2x00dev
->cap_flags
);
7766 __set_bit(REQUIRE_DMA
, &rt2x00dev
->cap_flags
);
7767 __set_bit(REQUIRE_TASKLET_CONTEXT
, &rt2x00dev
->cap_flags
);
7771 * Set the rssi offset.
7773 rt2x00dev
->rssi_offset
= DEFAULT_RSSI_OFFSET
;
7777 EXPORT_SYMBOL_GPL(rt2800_probe_hw
);
7780 * IEEE80211 stack callback functions.
7782 void rt2800_get_tkip_seq(struct ieee80211_hw
*hw
, u8 hw_key_idx
, u32
*iv32
,
7785 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
7786 struct mac_iveiv_entry iveiv_entry
;
7789 offset
= MAC_IVEIV_ENTRY(hw_key_idx
);
7790 rt2800_register_multiread(rt2x00dev
, offset
,
7791 &iveiv_entry
, sizeof(iveiv_entry
));
7793 memcpy(iv16
, &iveiv_entry
.iv
[0], sizeof(*iv16
));
7794 memcpy(iv32
, &iveiv_entry
.iv
[4], sizeof(*iv32
));
7796 EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq
);
7798 int rt2800_set_rts_threshold(struct ieee80211_hw
*hw
, u32 value
)
7800 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
7802 bool enabled
= (value
< IEEE80211_MAX_RTS_THRESHOLD
);
7804 rt2800_register_read(rt2x00dev
, TX_RTS_CFG
, ®
);
7805 rt2x00_set_field32(®
, TX_RTS_CFG_RTS_THRES
, value
);
7806 rt2800_register_write(rt2x00dev
, TX_RTS_CFG
, reg
);
7808 rt2800_register_read(rt2x00dev
, CCK_PROT_CFG
, ®
);
7809 rt2x00_set_field32(®
, CCK_PROT_CFG_RTS_TH_EN
, enabled
);
7810 rt2800_register_write(rt2x00dev
, CCK_PROT_CFG
, reg
);
7812 rt2800_register_read(rt2x00dev
, OFDM_PROT_CFG
, ®
);
7813 rt2x00_set_field32(®
, OFDM_PROT_CFG_RTS_TH_EN
, enabled
);
7814 rt2800_register_write(rt2x00dev
, OFDM_PROT_CFG
, reg
);
7816 rt2800_register_read(rt2x00dev
, MM20_PROT_CFG
, ®
);
7817 rt2x00_set_field32(®
, MM20_PROT_CFG_RTS_TH_EN
, enabled
);
7818 rt2800_register_write(rt2x00dev
, MM20_PROT_CFG
, reg
);
7820 rt2800_register_read(rt2x00dev
, MM40_PROT_CFG
, ®
);
7821 rt2x00_set_field32(®
, MM40_PROT_CFG_RTS_TH_EN
, enabled
);
7822 rt2800_register_write(rt2x00dev
, MM40_PROT_CFG
, reg
);
7824 rt2800_register_read(rt2x00dev
, GF20_PROT_CFG
, ®
);
7825 rt2x00_set_field32(®
, GF20_PROT_CFG_RTS_TH_EN
, enabled
);
7826 rt2800_register_write(rt2x00dev
, GF20_PROT_CFG
, reg
);
7828 rt2800_register_read(rt2x00dev
, GF40_PROT_CFG
, ®
);
7829 rt2x00_set_field32(®
, GF40_PROT_CFG_RTS_TH_EN
, enabled
);
7830 rt2800_register_write(rt2x00dev
, GF40_PROT_CFG
, reg
);
7834 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold
);
7836 int rt2800_conf_tx(struct ieee80211_hw
*hw
,
7837 struct ieee80211_vif
*vif
, u16 queue_idx
,
7838 const struct ieee80211_tx_queue_params
*params
)
7840 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
7841 struct data_queue
*queue
;
7842 struct rt2x00_field32 field
;
7848 * First pass the configuration through rt2x00lib, that will
7849 * update the queue settings and validate the input. After that
7850 * we are free to update the registers based on the value
7851 * in the queue parameter.
7853 retval
= rt2x00mac_conf_tx(hw
, vif
, queue_idx
, params
);
7858 * We only need to perform additional register initialization
7864 queue
= rt2x00queue_get_tx_queue(rt2x00dev
, queue_idx
);
7866 /* Update WMM TXOP register */
7867 offset
= WMM_TXOP0_CFG
+ (sizeof(u32
) * (!!(queue_idx
& 2)));
7868 field
.bit_offset
= (queue_idx
& 1) * 16;
7869 field
.bit_mask
= 0xffff << field
.bit_offset
;
7871 rt2800_register_read(rt2x00dev
, offset
, ®
);
7872 rt2x00_set_field32(®
, field
, queue
->txop
);
7873 rt2800_register_write(rt2x00dev
, offset
, reg
);
7875 /* Update WMM registers */
7876 field
.bit_offset
= queue_idx
* 4;
7877 field
.bit_mask
= 0xf << field
.bit_offset
;
7879 rt2800_register_read(rt2x00dev
, WMM_AIFSN_CFG
, ®
);
7880 rt2x00_set_field32(®
, field
, queue
->aifs
);
7881 rt2800_register_write(rt2x00dev
, WMM_AIFSN_CFG
, reg
);
7883 rt2800_register_read(rt2x00dev
, WMM_CWMIN_CFG
, ®
);
7884 rt2x00_set_field32(®
, field
, queue
->cw_min
);
7885 rt2800_register_write(rt2x00dev
, WMM_CWMIN_CFG
, reg
);
7887 rt2800_register_read(rt2x00dev
, WMM_CWMAX_CFG
, ®
);
7888 rt2x00_set_field32(®
, field
, queue
->cw_max
);
7889 rt2800_register_write(rt2x00dev
, WMM_CWMAX_CFG
, reg
);
7891 /* Update EDCA registers */
7892 offset
= EDCA_AC0_CFG
+ (sizeof(u32
) * queue_idx
);
7894 rt2800_register_read(rt2x00dev
, offset
, ®
);
7895 rt2x00_set_field32(®
, EDCA_AC0_CFG_TX_OP
, queue
->txop
);
7896 rt2x00_set_field32(®
, EDCA_AC0_CFG_AIFSN
, queue
->aifs
);
7897 rt2x00_set_field32(®
, EDCA_AC0_CFG_CWMIN
, queue
->cw_min
);
7898 rt2x00_set_field32(®
, EDCA_AC0_CFG_CWMAX
, queue
->cw_max
);
7899 rt2800_register_write(rt2x00dev
, offset
, reg
);
7903 EXPORT_SYMBOL_GPL(rt2800_conf_tx
);
7905 u64
rt2800_get_tsf(struct ieee80211_hw
*hw
, struct ieee80211_vif
*vif
)
7907 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
7911 rt2800_register_read(rt2x00dev
, TSF_TIMER_DW1
, ®
);
7912 tsf
= (u64
) rt2x00_get_field32(reg
, TSF_TIMER_DW1_HIGH_WORD
) << 32;
7913 rt2800_register_read(rt2x00dev
, TSF_TIMER_DW0
, ®
);
7914 tsf
|= rt2x00_get_field32(reg
, TSF_TIMER_DW0_LOW_WORD
);
7918 EXPORT_SYMBOL_GPL(rt2800_get_tsf
);
7920 int rt2800_ampdu_action(struct ieee80211_hw
*hw
, struct ieee80211_vif
*vif
,
7921 enum ieee80211_ampdu_mlme_action action
,
7922 struct ieee80211_sta
*sta
, u16 tid
, u16
*ssn
,
7925 struct rt2x00_sta
*sta_priv
= (struct rt2x00_sta
*)sta
->drv_priv
;
7929 * Don't allow aggregation for stations the hardware isn't aware
7930 * of because tx status reports for frames to an unknown station
7931 * always contain wcid=255 and thus we can't distinguish between
7932 * multiple stations which leads to unwanted situations when the
7933 * hw reorders frames due to aggregation.
7935 if (sta_priv
->wcid
< 0)
7939 case IEEE80211_AMPDU_RX_START
:
7940 case IEEE80211_AMPDU_RX_STOP
:
7942 * The hw itself takes care of setting up BlockAck mechanisms.
7943 * So, we only have to allow mac80211 to nagotiate a BlockAck
7944 * agreement. Once that is done, the hw will BlockAck incoming
7945 * AMPDUs without further setup.
7948 case IEEE80211_AMPDU_TX_START
:
7949 ieee80211_start_tx_ba_cb_irqsafe(vif
, sta
->addr
, tid
);
7951 case IEEE80211_AMPDU_TX_STOP_CONT
:
7952 case IEEE80211_AMPDU_TX_STOP_FLUSH
:
7953 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT
:
7954 ieee80211_stop_tx_ba_cb_irqsafe(vif
, sta
->addr
, tid
);
7956 case IEEE80211_AMPDU_TX_OPERATIONAL
:
7959 rt2x00_warn((struct rt2x00_dev
*)hw
->priv
,
7960 "Unknown AMPDU action\n");
7965 EXPORT_SYMBOL_GPL(rt2800_ampdu_action
);
7967 int rt2800_get_survey(struct ieee80211_hw
*hw
, int idx
,
7968 struct survey_info
*survey
)
7970 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
7971 struct ieee80211_conf
*conf
= &hw
->conf
;
7972 u32 idle
, busy
, busy_ext
;
7977 survey
->channel
= conf
->chandef
.chan
;
7979 rt2800_register_read(rt2x00dev
, CH_IDLE_STA
, &idle
);
7980 rt2800_register_read(rt2x00dev
, CH_BUSY_STA
, &busy
);
7981 rt2800_register_read(rt2x00dev
, CH_BUSY_STA_SEC
, &busy_ext
);
7984 survey
->filled
= SURVEY_INFO_CHANNEL_TIME
|
7985 SURVEY_INFO_CHANNEL_TIME_BUSY
|
7986 SURVEY_INFO_CHANNEL_TIME_EXT_BUSY
;
7988 survey
->channel_time
= (idle
+ busy
) / 1000;
7989 survey
->channel_time_busy
= busy
/ 1000;
7990 survey
->channel_time_ext_busy
= busy_ext
/ 1000;
7993 if (!(hw
->conf
.flags
& IEEE80211_CONF_OFFCHANNEL
))
7994 survey
->filled
|= SURVEY_INFO_IN_USE
;
7999 EXPORT_SYMBOL_GPL(rt2800_get_survey
);
8001 MODULE_AUTHOR(DRV_PROJECT
", Bartlomiej Zolnierkiewicz");
8002 MODULE_VERSION(DRV_VERSION
);
8003 MODULE_DESCRIPTION("Ralink RT2800 library");
8004 MODULE_LICENSE("GPL");