2 Copyright (C) 2009 Ivo van Doorn <IvDoorn@gmail.com>
3 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
4 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
6 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
7 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
8 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
9 Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
10 <http://rt2x00.serialmonkey.com>
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the
24 Free Software Foundation, Inc.,
25 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 Abstract: rt2800pci device specific routines.
31 Supported chipsets: RT2800E & RT2800ED.
34 #include <linux/delay.h>
35 #include <linux/etherdevice.h>
36 #include <linux/init.h>
37 #include <linux/kernel.h>
38 #include <linux/module.h>
39 #include <linux/pci.h>
40 #include <linux/platform_device.h>
41 #include <linux/eeprom_93cx6.h>
44 #include "rt2x00pci.h"
45 #include "rt2x00soc.h"
46 #include "rt2800lib.h"
48 #include "rt2800pci.h"
51 * Allow hardware encryption to be disabled.
53 static int modparam_nohwcrypt
= 0;
54 module_param_named(nohwcrypt
, modparam_nohwcrypt
, bool, S_IRUGO
);
55 MODULE_PARM_DESC(nohwcrypt
, "Disable hardware encryption.");
57 static void rt2800pci_mcu_status(struct rt2x00_dev
*rt2x00dev
, const u8 token
)
63 * SOC devices don't support MCU requests.
65 if (rt2x00_is_soc(rt2x00dev
))
68 for (i
= 0; i
< 200; i
++) {
69 rt2800_register_read(rt2x00dev
, H2M_MAILBOX_CID
, ®
);
71 if ((rt2x00_get_field32(reg
, H2M_MAILBOX_CID_CMD0
) == token
) ||
72 (rt2x00_get_field32(reg
, H2M_MAILBOX_CID_CMD1
) == token
) ||
73 (rt2x00_get_field32(reg
, H2M_MAILBOX_CID_CMD2
) == token
) ||
74 (rt2x00_get_field32(reg
, H2M_MAILBOX_CID_CMD3
) == token
))
77 udelay(REGISTER_BUSY_DELAY
);
81 ERROR(rt2x00dev
, "MCU request failed, no response from hardware\n");
83 rt2800_register_write(rt2x00dev
, H2M_MAILBOX_STATUS
, ~0);
84 rt2800_register_write(rt2x00dev
, H2M_MAILBOX_CID
, ~0);
87 #ifdef CONFIG_RT2800PCI_SOC
88 static void rt2800pci_read_eeprom_soc(struct rt2x00_dev
*rt2x00dev
)
90 u32
*base_addr
= (u32
*) KSEG1ADDR(0x1F040000); /* XXX for RT3052 */
92 memcpy_fromio(rt2x00dev
->eeprom
, base_addr
, EEPROM_SIZE
);
95 static inline void rt2800pci_read_eeprom_soc(struct rt2x00_dev
*rt2x00dev
)
98 #endif /* CONFIG_RT2800PCI_SOC */
100 #ifdef CONFIG_RT2800PCI_PCI
101 static void rt2800pci_eepromregister_read(struct eeprom_93cx6
*eeprom
)
103 struct rt2x00_dev
*rt2x00dev
= eeprom
->data
;
106 rt2800_register_read(rt2x00dev
, E2PROM_CSR
, ®
);
108 eeprom
->reg_data_in
= !!rt2x00_get_field32(reg
, E2PROM_CSR_DATA_IN
);
109 eeprom
->reg_data_out
= !!rt2x00_get_field32(reg
, E2PROM_CSR_DATA_OUT
);
110 eeprom
->reg_data_clock
=
111 !!rt2x00_get_field32(reg
, E2PROM_CSR_DATA_CLOCK
);
112 eeprom
->reg_chip_select
=
113 !!rt2x00_get_field32(reg
, E2PROM_CSR_CHIP_SELECT
);
116 static void rt2800pci_eepromregister_write(struct eeprom_93cx6
*eeprom
)
118 struct rt2x00_dev
*rt2x00dev
= eeprom
->data
;
121 rt2x00_set_field32(®
, E2PROM_CSR_DATA_IN
, !!eeprom
->reg_data_in
);
122 rt2x00_set_field32(®
, E2PROM_CSR_DATA_OUT
, !!eeprom
->reg_data_out
);
123 rt2x00_set_field32(®
, E2PROM_CSR_DATA_CLOCK
,
124 !!eeprom
->reg_data_clock
);
125 rt2x00_set_field32(®
, E2PROM_CSR_CHIP_SELECT
,
126 !!eeprom
->reg_chip_select
);
128 rt2800_register_write(rt2x00dev
, E2PROM_CSR
, reg
);
131 static void rt2800pci_read_eeprom_pci(struct rt2x00_dev
*rt2x00dev
)
133 struct eeprom_93cx6 eeprom
;
136 rt2800_register_read(rt2x00dev
, E2PROM_CSR
, ®
);
138 eeprom
.data
= rt2x00dev
;
139 eeprom
.register_read
= rt2800pci_eepromregister_read
;
140 eeprom
.register_write
= rt2800pci_eepromregister_write
;
141 switch (rt2x00_get_field32(reg
, E2PROM_CSR_TYPE
))
144 eeprom
.width
= PCI_EEPROM_WIDTH_93C46
;
147 eeprom
.width
= PCI_EEPROM_WIDTH_93C66
;
150 eeprom
.width
= PCI_EEPROM_WIDTH_93C86
;
153 eeprom
.reg_data_in
= 0;
154 eeprom
.reg_data_out
= 0;
155 eeprom
.reg_data_clock
= 0;
156 eeprom
.reg_chip_select
= 0;
158 eeprom_93cx6_multiread(&eeprom
, EEPROM_BASE
, rt2x00dev
->eeprom
,
159 EEPROM_SIZE
/ sizeof(u16
));
162 static int rt2800pci_efuse_detect(struct rt2x00_dev
*rt2x00dev
)
164 return rt2800_efuse_detect(rt2x00dev
);
167 static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev
*rt2x00dev
)
169 rt2800_read_eeprom_efuse(rt2x00dev
);
172 static inline void rt2800pci_read_eeprom_pci(struct rt2x00_dev
*rt2x00dev
)
176 static inline int rt2800pci_efuse_detect(struct rt2x00_dev
*rt2x00dev
)
181 static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev
*rt2x00dev
)
184 #endif /* CONFIG_RT2800PCI_PCI */
189 static char *rt2800pci_get_firmware_name(struct rt2x00_dev
*rt2x00dev
)
191 return FIRMWARE_RT2860
;
194 static int rt2800pci_write_firmware(struct rt2x00_dev
*rt2x00dev
,
195 const u8
*data
, const size_t len
)
199 rt2800_register_write(rt2x00dev
, AUTOWAKEUP_CFG
, 0x00000000);
202 * enable Host program ram write selection
205 rt2x00_set_field32(®
, PBF_SYS_CTRL_HOST_RAM_WRITE
, 1);
206 rt2800_register_write(rt2x00dev
, PBF_SYS_CTRL
, reg
);
209 * Write firmware to device.
211 rt2800_register_multiwrite(rt2x00dev
, FIRMWARE_IMAGE_BASE
,
214 rt2800_register_write(rt2x00dev
, PBF_SYS_CTRL
, 0x00000);
215 rt2800_register_write(rt2x00dev
, PBF_SYS_CTRL
, 0x00001);
217 rt2800_register_write(rt2x00dev
, H2M_BBP_AGENT
, 0);
218 rt2800_register_write(rt2x00dev
, H2M_MAILBOX_CSR
, 0);
224 * Initialization functions.
226 static bool rt2800pci_get_entry_state(struct queue_entry
*entry
)
228 struct queue_entry_priv_pci
*entry_priv
= entry
->priv_data
;
231 if (entry
->queue
->qid
== QID_RX
) {
232 rt2x00_desc_read(entry_priv
->desc
, 1, &word
);
234 return (!rt2x00_get_field32(word
, RXD_W1_DMA_DONE
));
236 rt2x00_desc_read(entry_priv
->desc
, 1, &word
);
238 return (!rt2x00_get_field32(word
, TXD_W1_DMA_DONE
));
242 static void rt2800pci_clear_entry(struct queue_entry
*entry
)
244 struct queue_entry_priv_pci
*entry_priv
= entry
->priv_data
;
245 struct skb_frame_desc
*skbdesc
= get_skb_frame_desc(entry
->skb
);
248 if (entry
->queue
->qid
== QID_RX
) {
249 rt2x00_desc_read(entry_priv
->desc
, 0, &word
);
250 rt2x00_set_field32(&word
, RXD_W0_SDP0
, skbdesc
->skb_dma
);
251 rt2x00_desc_write(entry_priv
->desc
, 0, word
);
253 rt2x00_desc_read(entry_priv
->desc
, 1, &word
);
254 rt2x00_set_field32(&word
, RXD_W1_DMA_DONE
, 0);
255 rt2x00_desc_write(entry_priv
->desc
, 1, word
);
257 rt2x00_desc_read(entry_priv
->desc
, 1, &word
);
258 rt2x00_set_field32(&word
, TXD_W1_DMA_DONE
, 1);
259 rt2x00_desc_write(entry_priv
->desc
, 1, word
);
263 static int rt2800pci_init_queues(struct rt2x00_dev
*rt2x00dev
)
265 struct queue_entry_priv_pci
*entry_priv
;
269 * Initialize registers.
271 entry_priv
= rt2x00dev
->tx
[0].entries
[0].priv_data
;
272 rt2800_register_write(rt2x00dev
, TX_BASE_PTR0
, entry_priv
->desc_dma
);
273 rt2800_register_write(rt2x00dev
, TX_MAX_CNT0
, rt2x00dev
->tx
[0].limit
);
274 rt2800_register_write(rt2x00dev
, TX_CTX_IDX0
, 0);
275 rt2800_register_write(rt2x00dev
, TX_DTX_IDX0
, 0);
277 entry_priv
= rt2x00dev
->tx
[1].entries
[0].priv_data
;
278 rt2800_register_write(rt2x00dev
, TX_BASE_PTR1
, entry_priv
->desc_dma
);
279 rt2800_register_write(rt2x00dev
, TX_MAX_CNT1
, rt2x00dev
->tx
[1].limit
);
280 rt2800_register_write(rt2x00dev
, TX_CTX_IDX1
, 0);
281 rt2800_register_write(rt2x00dev
, TX_DTX_IDX1
, 0);
283 entry_priv
= rt2x00dev
->tx
[2].entries
[0].priv_data
;
284 rt2800_register_write(rt2x00dev
, TX_BASE_PTR2
, entry_priv
->desc_dma
);
285 rt2800_register_write(rt2x00dev
, TX_MAX_CNT2
, rt2x00dev
->tx
[2].limit
);
286 rt2800_register_write(rt2x00dev
, TX_CTX_IDX2
, 0);
287 rt2800_register_write(rt2x00dev
, TX_DTX_IDX2
, 0);
289 entry_priv
= rt2x00dev
->tx
[3].entries
[0].priv_data
;
290 rt2800_register_write(rt2x00dev
, TX_BASE_PTR3
, entry_priv
->desc_dma
);
291 rt2800_register_write(rt2x00dev
, TX_MAX_CNT3
, rt2x00dev
->tx
[3].limit
);
292 rt2800_register_write(rt2x00dev
, TX_CTX_IDX3
, 0);
293 rt2800_register_write(rt2x00dev
, TX_DTX_IDX3
, 0);
295 entry_priv
= rt2x00dev
->rx
->entries
[0].priv_data
;
296 rt2800_register_write(rt2x00dev
, RX_BASE_PTR
, entry_priv
->desc_dma
);
297 rt2800_register_write(rt2x00dev
, RX_MAX_CNT
, rt2x00dev
->rx
[0].limit
);
298 rt2800_register_write(rt2x00dev
, RX_CRX_IDX
, rt2x00dev
->rx
[0].limit
- 1);
299 rt2800_register_write(rt2x00dev
, RX_DRX_IDX
, 0);
302 * Enable global DMA configuration
304 rt2800_register_read(rt2x00dev
, WPDMA_GLO_CFG
, ®
);
305 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_TX_DMA
, 0);
306 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_RX_DMA
, 0);
307 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_WRITEBACK_DONE
, 1);
308 rt2800_register_write(rt2x00dev
, WPDMA_GLO_CFG
, reg
);
310 rt2800_register_write(rt2x00dev
, DELAY_INT_CFG
, 0);
316 * Device state switch handlers.
318 static void rt2800pci_toggle_rx(struct rt2x00_dev
*rt2x00dev
,
319 enum dev_state state
)
323 rt2800_register_read(rt2x00dev
, MAC_SYS_CTRL
, ®
);
324 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_RX
,
325 (state
== STATE_RADIO_RX_ON
) ||
326 (state
== STATE_RADIO_RX_ON_LINK
));
327 rt2800_register_write(rt2x00dev
, MAC_SYS_CTRL
, reg
);
330 static void rt2800pci_toggle_irq(struct rt2x00_dev
*rt2x00dev
,
331 enum dev_state state
)
333 int mask
= (state
== STATE_RADIO_IRQ_ON
) ||
334 (state
== STATE_RADIO_IRQ_ON_ISR
);
338 * When interrupts are being enabled, the interrupt registers
339 * should clear the register to assure a clean state.
341 if (state
== STATE_RADIO_IRQ_ON
) {
342 rt2800_register_read(rt2x00dev
, INT_SOURCE_CSR
, ®
);
343 rt2800_register_write(rt2x00dev
, INT_SOURCE_CSR
, reg
);
346 rt2800_register_read(rt2x00dev
, INT_MASK_CSR
, ®
);
347 rt2x00_set_field32(®
, INT_MASK_CSR_RXDELAYINT
, mask
);
348 rt2x00_set_field32(®
, INT_MASK_CSR_TXDELAYINT
, mask
);
349 rt2x00_set_field32(®
, INT_MASK_CSR_RX_DONE
, mask
);
350 rt2x00_set_field32(®
, INT_MASK_CSR_AC0_DMA_DONE
, mask
);
351 rt2x00_set_field32(®
, INT_MASK_CSR_AC1_DMA_DONE
, mask
);
352 rt2x00_set_field32(®
, INT_MASK_CSR_AC2_DMA_DONE
, mask
);
353 rt2x00_set_field32(®
, INT_MASK_CSR_AC3_DMA_DONE
, mask
);
354 rt2x00_set_field32(®
, INT_MASK_CSR_HCCA_DMA_DONE
, mask
);
355 rt2x00_set_field32(®
, INT_MASK_CSR_MGMT_DMA_DONE
, mask
);
356 rt2x00_set_field32(®
, INT_MASK_CSR_MCU_COMMAND
, mask
);
357 rt2x00_set_field32(®
, INT_MASK_CSR_RXTX_COHERENT
, mask
);
358 rt2x00_set_field32(®
, INT_MASK_CSR_TBTT
, mask
);
359 rt2x00_set_field32(®
, INT_MASK_CSR_PRE_TBTT
, mask
);
360 rt2x00_set_field32(®
, INT_MASK_CSR_TX_FIFO_STATUS
, mask
);
361 rt2x00_set_field32(®
, INT_MASK_CSR_AUTO_WAKEUP
, mask
);
362 rt2x00_set_field32(®
, INT_MASK_CSR_GPTIMER
, mask
);
363 rt2x00_set_field32(®
, INT_MASK_CSR_RX_COHERENT
, mask
);
364 rt2x00_set_field32(®
, INT_MASK_CSR_TX_COHERENT
, mask
);
365 rt2800_register_write(rt2x00dev
, INT_MASK_CSR
, reg
);
368 static int rt2800pci_init_registers(struct rt2x00_dev
*rt2x00dev
)
375 rt2800_register_read(rt2x00dev
, WPDMA_RST_IDX
, ®
);
376 rt2x00_set_field32(®
, WPDMA_RST_IDX_DTX_IDX0
, 1);
377 rt2x00_set_field32(®
, WPDMA_RST_IDX_DTX_IDX1
, 1);
378 rt2x00_set_field32(®
, WPDMA_RST_IDX_DTX_IDX2
, 1);
379 rt2x00_set_field32(®
, WPDMA_RST_IDX_DTX_IDX3
, 1);
380 rt2x00_set_field32(®
, WPDMA_RST_IDX_DTX_IDX4
, 1);
381 rt2x00_set_field32(®
, WPDMA_RST_IDX_DTX_IDX5
, 1);
382 rt2x00_set_field32(®
, WPDMA_RST_IDX_DRX_IDX0
, 1);
383 rt2800_register_write(rt2x00dev
, WPDMA_RST_IDX
, reg
);
385 rt2800_register_write(rt2x00dev
, PBF_SYS_CTRL
, 0x00000e1f);
386 rt2800_register_write(rt2x00dev
, PBF_SYS_CTRL
, 0x00000e00);
388 rt2800_register_write(rt2x00dev
, PWR_PIN_CFG
, 0x00000003);
390 rt2800_register_read(rt2x00dev
, MAC_SYS_CTRL
, ®
);
391 rt2x00_set_field32(®
, MAC_SYS_CTRL_RESET_CSR
, 1);
392 rt2x00_set_field32(®
, MAC_SYS_CTRL_RESET_BBP
, 1);
393 rt2800_register_write(rt2x00dev
, MAC_SYS_CTRL
, reg
);
395 rt2800_register_write(rt2x00dev
, MAC_SYS_CTRL
, 0x00000000);
400 static int rt2800pci_enable_radio(struct rt2x00_dev
*rt2x00dev
)
406 * Initialize all registers.
408 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev
) ||
409 rt2800pci_init_queues(rt2x00dev
) ||
410 rt2800_init_registers(rt2x00dev
) ||
411 rt2800_wait_wpdma_ready(rt2x00dev
) ||
412 rt2800_init_bbp(rt2x00dev
) ||
413 rt2800_init_rfcsr(rt2x00dev
)))
417 * Send signal to firmware during boot time.
419 rt2800_mcu_request(rt2x00dev
, MCU_BOOT_SIGNAL
, 0, 0, 0);
424 rt2800_register_read(rt2x00dev
, MAC_SYS_CTRL
, ®
);
425 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_TX
, 1);
426 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_RX
, 0);
427 rt2800_register_write(rt2x00dev
, MAC_SYS_CTRL
, reg
);
429 rt2800_register_read(rt2x00dev
, WPDMA_GLO_CFG
, ®
);
430 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_TX_DMA
, 1);
431 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_RX_DMA
, 1);
432 rt2x00_set_field32(®
, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE
, 2);
433 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_WRITEBACK_DONE
, 1);
434 rt2800_register_write(rt2x00dev
, WPDMA_GLO_CFG
, reg
);
436 rt2800_register_read(rt2x00dev
, MAC_SYS_CTRL
, ®
);
437 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_TX
, 1);
438 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_RX
, 1);
439 rt2800_register_write(rt2x00dev
, MAC_SYS_CTRL
, reg
);
442 * Initialize LED control
444 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LED1
, &word
);
445 rt2800_mcu_request(rt2x00dev
, MCU_LED_1
, 0xff,
446 word
& 0xff, (word
>> 8) & 0xff);
448 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LED2
, &word
);
449 rt2800_mcu_request(rt2x00dev
, MCU_LED_2
, 0xff,
450 word
& 0xff, (word
>> 8) & 0xff);
452 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LED3
, &word
);
453 rt2800_mcu_request(rt2x00dev
, MCU_LED_3
, 0xff,
454 word
& 0xff, (word
>> 8) & 0xff);
459 static void rt2800pci_disable_radio(struct rt2x00_dev
*rt2x00dev
)
463 rt2800_register_read(rt2x00dev
, WPDMA_GLO_CFG
, ®
);
464 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_TX_DMA
, 0);
465 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_DMA_BUSY
, 0);
466 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_RX_DMA
, 0);
467 rt2x00_set_field32(®
, WPDMA_GLO_CFG_RX_DMA_BUSY
, 0);
468 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_WRITEBACK_DONE
, 1);
469 rt2800_register_write(rt2x00dev
, WPDMA_GLO_CFG
, reg
);
471 rt2800_register_write(rt2x00dev
, MAC_SYS_CTRL
, 0);
472 rt2800_register_write(rt2x00dev
, PWR_PIN_CFG
, 0);
473 rt2800_register_write(rt2x00dev
, TX_PIN_CFG
, 0);
475 rt2800_register_write(rt2x00dev
, PBF_SYS_CTRL
, 0x00001280);
477 rt2800_register_read(rt2x00dev
, WPDMA_RST_IDX
, ®
);
478 rt2x00_set_field32(®
, WPDMA_RST_IDX_DTX_IDX0
, 1);
479 rt2x00_set_field32(®
, WPDMA_RST_IDX_DTX_IDX1
, 1);
480 rt2x00_set_field32(®
, WPDMA_RST_IDX_DTX_IDX2
, 1);
481 rt2x00_set_field32(®
, WPDMA_RST_IDX_DTX_IDX3
, 1);
482 rt2x00_set_field32(®
, WPDMA_RST_IDX_DTX_IDX4
, 1);
483 rt2x00_set_field32(®
, WPDMA_RST_IDX_DTX_IDX5
, 1);
484 rt2x00_set_field32(®
, WPDMA_RST_IDX_DRX_IDX0
, 1);
485 rt2800_register_write(rt2x00dev
, WPDMA_RST_IDX
, reg
);
487 rt2800_register_write(rt2x00dev
, PBF_SYS_CTRL
, 0x00000e1f);
488 rt2800_register_write(rt2x00dev
, PBF_SYS_CTRL
, 0x00000e00);
490 /* Wait for DMA, ignore error */
491 rt2800_wait_wpdma_ready(rt2x00dev
);
494 static int rt2800pci_set_state(struct rt2x00_dev
*rt2x00dev
,
495 enum dev_state state
)
498 * Always put the device to sleep (even when we intend to wakeup!)
499 * if the device is booting and wasn't asleep it will return
500 * failure when attempting to wakeup.
502 rt2800_mcu_request(rt2x00dev
, MCU_SLEEP
, 0xff, 0, 2);
504 if (state
== STATE_AWAKE
) {
505 rt2800_mcu_request(rt2x00dev
, MCU_WAKEUP
, TOKEN_WAKUP
, 0, 0);
506 rt2800pci_mcu_status(rt2x00dev
, TOKEN_WAKUP
);
512 static int rt2800pci_set_device_state(struct rt2x00_dev
*rt2x00dev
,
513 enum dev_state state
)
520 * Before the radio can be enabled, the device first has
521 * to be woken up. After that it needs a bit of time
522 * to be fully awake and then the radio can be enabled.
524 rt2800pci_set_state(rt2x00dev
, STATE_AWAKE
);
526 retval
= rt2800pci_enable_radio(rt2x00dev
);
528 case STATE_RADIO_OFF
:
530 * After the radio has been disabled, the device should
531 * be put to sleep for powersaving.
533 rt2800pci_disable_radio(rt2x00dev
);
534 rt2800pci_set_state(rt2x00dev
, STATE_SLEEP
);
536 case STATE_RADIO_RX_ON
:
537 case STATE_RADIO_RX_ON_LINK
:
538 case STATE_RADIO_RX_OFF
:
539 case STATE_RADIO_RX_OFF_LINK
:
540 rt2800pci_toggle_rx(rt2x00dev
, state
);
542 case STATE_RADIO_IRQ_ON
:
543 case STATE_RADIO_IRQ_ON_ISR
:
544 case STATE_RADIO_IRQ_OFF
:
545 case STATE_RADIO_IRQ_OFF_ISR
:
546 rt2800pci_toggle_irq(rt2x00dev
, state
);
548 case STATE_DEEP_SLEEP
:
552 retval
= rt2800pci_set_state(rt2x00dev
, state
);
559 if (unlikely(retval
))
560 ERROR(rt2x00dev
, "Device failed to enter state %d (%d).\n",
567 * TX descriptor initialization
569 static void rt2800pci_write_tx_data(struct queue_entry
* entry
,
570 struct txentry_desc
*txdesc
)
572 __le32
*txwi
= (__le32
*) entry
->skb
->data
;
574 rt2800_write_txwi(txwi
, txdesc
);
578 static void rt2800pci_write_tx_desc(struct rt2x00_dev
*rt2x00dev
,
580 struct txentry_desc
*txdesc
)
582 struct skb_frame_desc
*skbdesc
= get_skb_frame_desc(skb
);
583 struct queue_entry_priv_pci
*entry_priv
= skbdesc
->entry
->priv_data
;
584 __le32
*txd
= entry_priv
->desc
;
588 * The buffers pointed by SD_PTR0/SD_LEN0 and SD_PTR1/SD_LEN1
589 * must contains a TXWI structure + 802.11 header + padding + 802.11
590 * data. We choose to have SD_PTR0/SD_LEN0 only contains TXWI and
591 * SD_PTR1/SD_LEN1 contains 802.11 header + padding + 802.11
592 * data. It means that LAST_SEC0 is always 0.
596 * Initialize TX descriptor
598 rt2x00_desc_read(txd
, 0, &word
);
599 rt2x00_set_field32(&word
, TXD_W0_SD_PTR0
, skbdesc
->skb_dma
);
600 rt2x00_desc_write(txd
, 0, word
);
602 rt2x00_desc_read(txd
, 1, &word
);
603 rt2x00_set_field32(&word
, TXD_W1_SD_LEN1
, skb
->len
);
604 rt2x00_set_field32(&word
, TXD_W1_LAST_SEC1
,
605 !test_bit(ENTRY_TXD_MORE_FRAG
, &txdesc
->flags
));
606 rt2x00_set_field32(&word
, TXD_W1_BURST
,
607 test_bit(ENTRY_TXD_BURST
, &txdesc
->flags
));
608 rt2x00_set_field32(&word
, TXD_W1_SD_LEN0
, TXWI_DESC_SIZE
);
609 rt2x00_set_field32(&word
, TXD_W1_LAST_SEC0
, 0);
610 rt2x00_set_field32(&word
, TXD_W1_DMA_DONE
, 0);
611 rt2x00_desc_write(txd
, 1, word
);
613 rt2x00_desc_read(txd
, 2, &word
);
614 rt2x00_set_field32(&word
, TXD_W2_SD_PTR1
,
615 skbdesc
->skb_dma
+ TXWI_DESC_SIZE
);
616 rt2x00_desc_write(txd
, 2, word
);
618 rt2x00_desc_read(txd
, 3, &word
);
619 rt2x00_set_field32(&word
, TXD_W3_WIV
,
620 !test_bit(ENTRY_TXD_ENCRYPT_IV
, &txdesc
->flags
));
621 rt2x00_set_field32(&word
, TXD_W3_QSEL
, 2);
622 rt2x00_desc_write(txd
, 3, word
);
625 * Register descriptor details in skb frame descriptor.
628 skbdesc
->desc_len
= TXD_DESC_SIZE
;
632 * TX data initialization
634 static void rt2800pci_kick_tx_queue(struct rt2x00_dev
*rt2x00dev
,
635 const enum data_queue_qid queue_idx
)
637 struct data_queue
*queue
;
638 unsigned int idx
, qidx
= 0;
640 if (queue_idx
> QID_HCCA
&& queue_idx
!= QID_MGMT
)
643 queue
= rt2x00queue_get_queue(rt2x00dev
, queue_idx
);
644 idx
= queue
->index
[Q_INDEX
];
646 if (queue_idx
== QID_MGMT
)
651 rt2800_register_write(rt2x00dev
, TX_CTX_IDX(qidx
), idx
);
654 static void rt2800pci_kill_tx_queue(struct rt2x00_dev
*rt2x00dev
,
655 const enum data_queue_qid qid
)
659 if (qid
== QID_BEACON
) {
660 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, 0);
664 rt2800_register_read(rt2x00dev
, WPDMA_RST_IDX
, ®
);
665 rt2x00_set_field32(®
, WPDMA_RST_IDX_DTX_IDX0
, (qid
== QID_AC_BE
));
666 rt2x00_set_field32(®
, WPDMA_RST_IDX_DTX_IDX1
, (qid
== QID_AC_BK
));
667 rt2x00_set_field32(®
, WPDMA_RST_IDX_DTX_IDX2
, (qid
== QID_AC_VI
));
668 rt2x00_set_field32(®
, WPDMA_RST_IDX_DTX_IDX3
, (qid
== QID_AC_VO
));
669 rt2800_register_write(rt2x00dev
, WPDMA_RST_IDX
, reg
);
673 * RX control handlers
675 static void rt2800pci_fill_rxdone(struct queue_entry
*entry
,
676 struct rxdone_entry_desc
*rxdesc
)
678 struct rt2x00_dev
*rt2x00dev
= entry
->queue
->rt2x00dev
;
679 struct queue_entry_priv_pci
*entry_priv
= entry
->priv_data
;
680 __le32
*rxd
= entry_priv
->desc
;
683 rt2x00_desc_read(rxd
, 3, &word
);
685 if (rt2x00_get_field32(word
, RXD_W3_CRC_ERROR
))
686 rxdesc
->flags
|= RX_FLAG_FAILED_FCS_CRC
;
689 * Unfortunately we don't know the cipher type used during
690 * decryption. This prevents us from correct providing
691 * correct statistics through debugfs.
693 rxdesc
->cipher_status
= rt2x00_get_field32(word
, RXD_W3_CIPHER_ERROR
);
695 if (rt2x00_get_field32(word
, RXD_W3_DECRYPTED
)) {
697 * Hardware has stripped IV/EIV data from 802.11 frame during
698 * decryption. Unfortunately the descriptor doesn't contain
699 * any fields with the EIV/IV data either, so they can't
700 * be restored by rt2x00lib.
702 rxdesc
->flags
|= RX_FLAG_IV_STRIPPED
;
704 if (rxdesc
->cipher_status
== RX_CRYPTO_SUCCESS
)
705 rxdesc
->flags
|= RX_FLAG_DECRYPTED
;
706 else if (rxdesc
->cipher_status
== RX_CRYPTO_FAIL_MIC
)
707 rxdesc
->flags
|= RX_FLAG_MMIC_ERROR
;
710 if (rt2x00_get_field32(word
, RXD_W3_MY_BSS
))
711 rxdesc
->dev_flags
|= RXDONE_MY_BSS
;
713 if (rt2x00_get_field32(word
, RXD_W3_L2PAD
))
714 rxdesc
->dev_flags
|= RXDONE_L2PAD
;
717 * Process the RXWI structure that is at the start of the buffer.
719 rt2800_process_rxwi(entry
, rxdesc
);
722 * Set RX IDX in register to inform hardware that we have handled
723 * this entry and it is available for reuse again.
725 rt2800_register_write(rt2x00dev
, RX_CRX_IDX
, entry
->entry_idx
);
729 * Interrupt functions.
731 static void rt2800pci_txdone(struct rt2x00_dev
*rt2x00dev
)
733 struct data_queue
*queue
;
734 struct queue_entry
*entry
;
736 struct txdone_entry_desc txdesc
;
739 int wcid
, ack
, pid
, tx_wcid
, tx_ack
, tx_pid
;
744 * TX_STA_FIFO is a stack of X entries, hence read TX_STA_FIFO
745 * at most X times and also stop processing once the TX_STA_FIFO_VALID
746 * flag is not set anymore.
748 * The legacy drivers use X=TX_RING_SIZE but state in a comment
749 * that the TX_STA_FIFO stack has a size of 16. We stick to our
750 * tx ring size for now.
752 for (i
= 0; i
< TX_ENTRIES
; i
++) {
753 rt2800_register_read(rt2x00dev
, TX_STA_FIFO
, ®
);
754 if (!rt2x00_get_field32(reg
, TX_STA_FIFO_VALID
))
757 wcid
= rt2x00_get_field32(reg
, TX_STA_FIFO_WCID
);
758 ack
= rt2x00_get_field32(reg
, TX_STA_FIFO_TX_ACK_REQUIRED
);
759 pid
= rt2x00_get_field32(reg
, TX_STA_FIFO_PID_TYPE
);
762 * Skip this entry when it contains an invalid
763 * queue identication number.
765 if (pid
<= 0 || pid
> QID_RX
)
768 queue
= rt2x00queue_get_queue(rt2x00dev
, pid
- 1);
769 if (unlikely(!queue
))
773 * Inside each queue, we process each entry in a chronological
774 * order. We first check that the queue is not empty.
776 if (rt2x00queue_empty(queue
))
778 entry
= rt2x00queue_get_entry(queue
, Q_INDEX_DONE
);
780 /* Check if we got a match by looking at WCID/ACK/PID
782 txwi
= (__le32
*) entry
->skb
->data
;
784 rt2x00_desc_read(txwi
, 1, &word
);
785 tx_wcid
= rt2x00_get_field32(word
, TXWI_W1_WIRELESS_CLI_ID
);
786 tx_ack
= rt2x00_get_field32(word
, TXWI_W1_ACK
);
787 tx_pid
= rt2x00_get_field32(word
, TXWI_W1_PACKETID
);
789 if ((wcid
!= tx_wcid
) || (ack
!= tx_ack
) || (pid
!= tx_pid
))
790 WARNING(rt2x00dev
, "invalid TX_STA_FIFO content\n");
793 * Obtain the status about this packet.
796 rt2x00_desc_read(txwi
, 0, &word
);
797 mcs
= rt2x00_get_field32(word
, TXWI_W0_MCS
);
798 real_mcs
= rt2x00_get_field32(reg
, TX_STA_FIFO_MCS
);
801 * Ralink has a retry mechanism using a global fallback
802 * table. We setup this fallback table to try the immediate
803 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
804 * always contains the MCS used for the last transmission, be
805 * it successful or not.
807 if (rt2x00_get_field32(reg
, TX_STA_FIFO_TX_SUCCESS
)) {
809 * Transmission succeeded. The number of retries is
812 __set_bit(TXDONE_SUCCESS
, &txdesc
.flags
);
813 txdesc
.retry
= ((mcs
> real_mcs
) ? mcs
- real_mcs
: 0);
816 * Transmission failed. The number of retries is
817 * always 7 in this case (for a total number of 8
820 __set_bit(TXDONE_FAILURE
, &txdesc
.flags
);
825 * the frame was retried at least once
826 * -> hw used fallback rates
829 __set_bit(TXDONE_FALLBACK
, &txdesc
.flags
);
831 rt2x00lib_txdone(entry
, &txdesc
);
835 static void rt2800pci_wakeup(struct rt2x00_dev
*rt2x00dev
)
837 struct ieee80211_conf conf
= { .flags
= 0 };
838 struct rt2x00lib_conf libconf
= { .conf
= &conf
};
840 rt2800_config(rt2x00dev
, &libconf
, IEEE80211_CONF_CHANGE_PS
);
843 static irqreturn_t
rt2800pci_interrupt_thread(int irq
, void *dev_instance
)
845 struct rt2x00_dev
*rt2x00dev
= dev_instance
;
846 u32 reg
= rt2x00dev
->irqvalue
[0];
849 * 1 - Pre TBTT interrupt.
851 if (rt2x00_get_field32(reg
, INT_SOURCE_CSR_PRE_TBTT
))
852 rt2x00lib_pretbtt(rt2x00dev
);
855 * 2 - Beacondone interrupt.
857 if (rt2x00_get_field32(reg
, INT_SOURCE_CSR_TBTT
))
858 rt2x00lib_beacondone(rt2x00dev
);
861 * 3 - Rx ring done interrupt.
863 if (rt2x00_get_field32(reg
, INT_SOURCE_CSR_RX_DONE
))
864 rt2x00pci_rxdone(rt2x00dev
);
867 * 4 - Tx done interrupt.
869 if (rt2x00_get_field32(reg
, INT_SOURCE_CSR_TX_FIFO_STATUS
))
870 rt2800pci_txdone(rt2x00dev
);
873 * 5 - Auto wakeup interrupt.
875 if (rt2x00_get_field32(reg
, INT_SOURCE_CSR_AUTO_WAKEUP
))
876 rt2800pci_wakeup(rt2x00dev
);
878 /* Enable interrupts again. */
879 rt2x00dev
->ops
->lib
->set_device_state(rt2x00dev
,
880 STATE_RADIO_IRQ_ON_ISR
);
885 static irqreturn_t
rt2800pci_interrupt(int irq
, void *dev_instance
)
887 struct rt2x00_dev
*rt2x00dev
= dev_instance
;
890 /* Read status and ACK all interrupts */
891 rt2800_register_read(rt2x00dev
, INT_SOURCE_CSR
, ®
);
892 rt2800_register_write(rt2x00dev
, INT_SOURCE_CSR
, reg
);
897 if (!test_bit(DEVICE_STATE_ENABLED_RADIO
, &rt2x00dev
->flags
))
900 /* Store irqvalue for use in the interrupt thread. */
901 rt2x00dev
->irqvalue
[0] = reg
;
903 /* Disable interrupts, will be enabled again in the interrupt thread. */
904 rt2x00dev
->ops
->lib
->set_device_state(rt2x00dev
,
905 STATE_RADIO_IRQ_OFF_ISR
);
908 return IRQ_WAKE_THREAD
;
912 * Device probe functions.
914 static int rt2800pci_validate_eeprom(struct rt2x00_dev
*rt2x00dev
)
917 * Read EEPROM into buffer
919 if (rt2x00_is_soc(rt2x00dev
))
920 rt2800pci_read_eeprom_soc(rt2x00dev
);
921 else if (rt2800pci_efuse_detect(rt2x00dev
))
922 rt2800pci_read_eeprom_efuse(rt2x00dev
);
924 rt2800pci_read_eeprom_pci(rt2x00dev
);
926 return rt2800_validate_eeprom(rt2x00dev
);
929 static int rt2800pci_probe_hw(struct rt2x00_dev
*rt2x00dev
)
934 * Allocate eeprom data.
936 retval
= rt2800pci_validate_eeprom(rt2x00dev
);
940 retval
= rt2800_init_eeprom(rt2x00dev
);
945 * Initialize hw specifications.
947 retval
= rt2800_probe_hw_mode(rt2x00dev
);
952 * This device has multiple filters for control frames
953 * and has a separate filter for PS Poll frames.
955 __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS
, &rt2x00dev
->flags
);
956 __set_bit(DRIVER_SUPPORT_CONTROL_FILTER_PSPOLL
, &rt2x00dev
->flags
);
959 * This device has a pre tbtt interrupt and thus fetches
960 * a new beacon directly prior to transmission.
962 __set_bit(DRIVER_SUPPORT_PRE_TBTT_INTERRUPT
, &rt2x00dev
->flags
);
965 * This device requires firmware.
967 if (!rt2x00_is_soc(rt2x00dev
))
968 __set_bit(DRIVER_REQUIRE_FIRMWARE
, &rt2x00dev
->flags
);
969 __set_bit(DRIVER_REQUIRE_DMA
, &rt2x00dev
->flags
);
970 __set_bit(DRIVER_REQUIRE_L2PAD
, &rt2x00dev
->flags
);
971 if (!modparam_nohwcrypt
)
972 __set_bit(CONFIG_SUPPORT_HW_CRYPTO
, &rt2x00dev
->flags
);
973 __set_bit(DRIVER_SUPPORT_LINK_TUNING
, &rt2x00dev
->flags
);
976 * Set the rssi offset.
978 rt2x00dev
->rssi_offset
= DEFAULT_RSSI_OFFSET
;
983 static const struct ieee80211_ops rt2800pci_mac80211_ops
= {
985 .start
= rt2x00mac_start
,
986 .stop
= rt2x00mac_stop
,
987 .add_interface
= rt2x00mac_add_interface
,
988 .remove_interface
= rt2x00mac_remove_interface
,
989 .config
= rt2x00mac_config
,
990 .configure_filter
= rt2x00mac_configure_filter
,
991 .set_key
= rt2x00mac_set_key
,
992 .sw_scan_start
= rt2x00mac_sw_scan_start
,
993 .sw_scan_complete
= rt2x00mac_sw_scan_complete
,
994 .get_stats
= rt2x00mac_get_stats
,
995 .get_tkip_seq
= rt2800_get_tkip_seq
,
996 .set_rts_threshold
= rt2800_set_rts_threshold
,
997 .bss_info_changed
= rt2x00mac_bss_info_changed
,
998 .conf_tx
= rt2800_conf_tx
,
999 .get_tsf
= rt2800_get_tsf
,
1000 .rfkill_poll
= rt2x00mac_rfkill_poll
,
1001 .ampdu_action
= rt2800_ampdu_action
,
1004 static const struct rt2800_ops rt2800pci_rt2800_ops
= {
1005 .register_read
= rt2x00pci_register_read
,
1006 .register_read_lock
= rt2x00pci_register_read
, /* same for PCI */
1007 .register_write
= rt2x00pci_register_write
,
1008 .register_write_lock
= rt2x00pci_register_write
, /* same for PCI */
1009 .register_multiread
= rt2x00pci_register_multiread
,
1010 .register_multiwrite
= rt2x00pci_register_multiwrite
,
1011 .regbusy_read
= rt2x00pci_regbusy_read
,
1012 .drv_write_firmware
= rt2800pci_write_firmware
,
1013 .drv_init_registers
= rt2800pci_init_registers
,
1016 static const struct rt2x00lib_ops rt2800pci_rt2x00_ops
= {
1017 .irq_handler
= rt2800pci_interrupt
,
1018 .irq_handler_thread
= rt2800pci_interrupt_thread
,
1019 .probe_hw
= rt2800pci_probe_hw
,
1020 .get_firmware_name
= rt2800pci_get_firmware_name
,
1021 .check_firmware
= rt2800_check_firmware
,
1022 .load_firmware
= rt2800_load_firmware
,
1023 .initialize
= rt2x00pci_initialize
,
1024 .uninitialize
= rt2x00pci_uninitialize
,
1025 .get_entry_state
= rt2800pci_get_entry_state
,
1026 .clear_entry
= rt2800pci_clear_entry
,
1027 .set_device_state
= rt2800pci_set_device_state
,
1028 .rfkill_poll
= rt2800_rfkill_poll
,
1029 .link_stats
= rt2800_link_stats
,
1030 .reset_tuner
= rt2800_reset_tuner
,
1031 .link_tuner
= rt2800_link_tuner
,
1032 .write_tx_desc
= rt2800pci_write_tx_desc
,
1033 .write_tx_data
= rt2800pci_write_tx_data
,
1034 .write_beacon
= rt2800_write_beacon
,
1035 .kick_tx_queue
= rt2800pci_kick_tx_queue
,
1036 .kill_tx_queue
= rt2800pci_kill_tx_queue
,
1037 .fill_rxdone
= rt2800pci_fill_rxdone
,
1038 .config_shared_key
= rt2800_config_shared_key
,
1039 .config_pairwise_key
= rt2800_config_pairwise_key
,
1040 .config_filter
= rt2800_config_filter
,
1041 .config_intf
= rt2800_config_intf
,
1042 .config_erp
= rt2800_config_erp
,
1043 .config_ant
= rt2800_config_ant
,
1044 .config
= rt2800_config
,
1047 static const struct data_queue_desc rt2800pci_queue_rx
= {
1048 .entry_num
= RX_ENTRIES
,
1049 .data_size
= AGGREGATION_SIZE
,
1050 .desc_size
= RXD_DESC_SIZE
,
1051 .priv_size
= sizeof(struct queue_entry_priv_pci
),
1054 static const struct data_queue_desc rt2800pci_queue_tx
= {
1055 .entry_num
= TX_ENTRIES
,
1056 .data_size
= AGGREGATION_SIZE
,
1057 .desc_size
= TXD_DESC_SIZE
,
1058 .priv_size
= sizeof(struct queue_entry_priv_pci
),
1061 static const struct data_queue_desc rt2800pci_queue_bcn
= {
1062 .entry_num
= 8 * BEACON_ENTRIES
,
1063 .data_size
= 0, /* No DMA required for beacons */
1064 .desc_size
= TXWI_DESC_SIZE
,
1065 .priv_size
= sizeof(struct queue_entry_priv_pci
),
1068 static const struct rt2x00_ops rt2800pci_ops
= {
1069 .name
= KBUILD_MODNAME
,
1072 .eeprom_size
= EEPROM_SIZE
,
1074 .tx_queues
= NUM_TX_QUEUES
,
1075 .extra_tx_headroom
= TXWI_DESC_SIZE
,
1076 .rx
= &rt2800pci_queue_rx
,
1077 .tx
= &rt2800pci_queue_tx
,
1078 .bcn
= &rt2800pci_queue_bcn
,
1079 .lib
= &rt2800pci_rt2x00_ops
,
1080 .drv
= &rt2800pci_rt2800_ops
,
1081 .hw
= &rt2800pci_mac80211_ops
,
1082 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1083 .debugfs
= &rt2800_rt2x00debug
,
1084 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1088 * RT2800pci module information.
1090 #ifdef CONFIG_RT2800PCI_PCI
1091 static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table
) = {
1092 { PCI_DEVICE(0x1814, 0x0601), PCI_DEVICE_DATA(&rt2800pci_ops
) },
1093 { PCI_DEVICE(0x1814, 0x0681), PCI_DEVICE_DATA(&rt2800pci_ops
) },
1094 { PCI_DEVICE(0x1814, 0x0701), PCI_DEVICE_DATA(&rt2800pci_ops
) },
1095 { PCI_DEVICE(0x1814, 0x0781), PCI_DEVICE_DATA(&rt2800pci_ops
) },
1096 { PCI_DEVICE(0x1432, 0x7708), PCI_DEVICE_DATA(&rt2800pci_ops
) },
1097 { PCI_DEVICE(0x1432, 0x7727), PCI_DEVICE_DATA(&rt2800pci_ops
) },
1098 { PCI_DEVICE(0x1432, 0x7728), PCI_DEVICE_DATA(&rt2800pci_ops
) },
1099 { PCI_DEVICE(0x1432, 0x7738), PCI_DEVICE_DATA(&rt2800pci_ops
) },
1100 { PCI_DEVICE(0x1432, 0x7748), PCI_DEVICE_DATA(&rt2800pci_ops
) },
1101 { PCI_DEVICE(0x1432, 0x7758), PCI_DEVICE_DATA(&rt2800pci_ops
) },
1102 { PCI_DEVICE(0x1432, 0x7768), PCI_DEVICE_DATA(&rt2800pci_ops
) },
1103 { PCI_DEVICE(0x1a3b, 0x1059), PCI_DEVICE_DATA(&rt2800pci_ops
) },
1104 #ifdef CONFIG_RT2800PCI_RT30XX
1105 { PCI_DEVICE(0x1814, 0x3090), PCI_DEVICE_DATA(&rt2800pci_ops
) },
1106 { PCI_DEVICE(0x1814, 0x3091), PCI_DEVICE_DATA(&rt2800pci_ops
) },
1107 { PCI_DEVICE(0x1814, 0x3092), PCI_DEVICE_DATA(&rt2800pci_ops
) },
1108 { PCI_DEVICE(0x1462, 0x891a), PCI_DEVICE_DATA(&rt2800pci_ops
) },
1110 #ifdef CONFIG_RT2800PCI_RT35XX
1111 { PCI_DEVICE(0x1814, 0x3060), PCI_DEVICE_DATA(&rt2800pci_ops
) },
1112 { PCI_DEVICE(0x1814, 0x3062), PCI_DEVICE_DATA(&rt2800pci_ops
) },
1113 { PCI_DEVICE(0x1814, 0x3562), PCI_DEVICE_DATA(&rt2800pci_ops
) },
1114 { PCI_DEVICE(0x1814, 0x3592), PCI_DEVICE_DATA(&rt2800pci_ops
) },
1115 { PCI_DEVICE(0x1814, 0x3593), PCI_DEVICE_DATA(&rt2800pci_ops
) },
1119 #endif /* CONFIG_RT2800PCI_PCI */
1121 MODULE_AUTHOR(DRV_PROJECT
);
1122 MODULE_VERSION(DRV_VERSION
);
1123 MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
1124 MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
1125 #ifdef CONFIG_RT2800PCI_PCI
1126 MODULE_FIRMWARE(FIRMWARE_RT2860
);
1127 MODULE_DEVICE_TABLE(pci
, rt2800pci_device_table
);
1128 #endif /* CONFIG_RT2800PCI_PCI */
1129 MODULE_LICENSE("GPL");
1131 #ifdef CONFIG_RT2800PCI_SOC
1132 static int rt2800soc_probe(struct platform_device
*pdev
)
1134 return rt2x00soc_probe(pdev
, &rt2800pci_ops
);
1137 static struct platform_driver rt2800soc_driver
= {
1139 .name
= "rt2800_wmac",
1140 .owner
= THIS_MODULE
,
1141 .mod_name
= KBUILD_MODNAME
,
1143 .probe
= rt2800soc_probe
,
1144 .remove
= __devexit_p(rt2x00soc_remove
),
1145 .suspend
= rt2x00soc_suspend
,
1146 .resume
= rt2x00soc_resume
,
1148 #endif /* CONFIG_RT2800PCI_SOC */
1150 #ifdef CONFIG_RT2800PCI_PCI
1151 static struct pci_driver rt2800pci_driver
= {
1152 .name
= KBUILD_MODNAME
,
1153 .id_table
= rt2800pci_device_table
,
1154 .probe
= rt2x00pci_probe
,
1155 .remove
= __devexit_p(rt2x00pci_remove
),
1156 .suspend
= rt2x00pci_suspend
,
1157 .resume
= rt2x00pci_resume
,
1159 #endif /* CONFIG_RT2800PCI_PCI */
1161 static int __init
rt2800pci_init(void)
1165 #ifdef CONFIG_RT2800PCI_SOC
1166 ret
= platform_driver_register(&rt2800soc_driver
);
1170 #ifdef CONFIG_RT2800PCI_PCI
1171 ret
= pci_register_driver(&rt2800pci_driver
);
1173 #ifdef CONFIG_RT2800PCI_SOC
1174 platform_driver_unregister(&rt2800soc_driver
);
1183 static void __exit
rt2800pci_exit(void)
1185 #ifdef CONFIG_RT2800PCI_PCI
1186 pci_unregister_driver(&rt2800pci_driver
);
1188 #ifdef CONFIG_RT2800PCI_SOC
1189 platform_driver_unregister(&rt2800soc_driver
);
1193 module_init(rt2800pci_init
);
1194 module_exit(rt2800pci_exit
);