2 Copyright (C) 2009 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
3 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
4 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
6 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
7 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
8 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
9 Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
10 <http://rt2x00.serialmonkey.com>
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the
24 Free Software Foundation, Inc.,
25 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 Abstract: rt2800pci device specific routines.
31 Supported chipsets: RT2800E & RT2800ED.
34 #include <linux/delay.h>
35 #include <linux/etherdevice.h>
36 #include <linux/init.h>
37 #include <linux/kernel.h>
38 #include <linux/module.h>
39 #include <linux/pci.h>
40 #include <linux/platform_device.h>
41 #include <linux/eeprom_93cx6.h>
44 #include "rt2x00pci.h"
45 #include "rt2x00soc.h"
46 #include "rt2800lib.h"
48 #include "rt2800pci.h"
51 * Allow hardware encryption to be disabled.
53 static bool modparam_nohwcrypt
= false;
54 module_param_named(nohwcrypt
, modparam_nohwcrypt
, bool, S_IRUGO
);
55 MODULE_PARM_DESC(nohwcrypt
, "Disable hardware encryption.");
57 static void rt2800pci_mcu_status(struct rt2x00_dev
*rt2x00dev
, const u8 token
)
63 * SOC devices don't support MCU requests.
65 if (rt2x00_is_soc(rt2x00dev
))
68 for (i
= 0; i
< 200; i
++) {
69 rt2x00pci_register_read(rt2x00dev
, H2M_MAILBOX_CID
, ®
);
71 if ((rt2x00_get_field32(reg
, H2M_MAILBOX_CID_CMD0
) == token
) ||
72 (rt2x00_get_field32(reg
, H2M_MAILBOX_CID_CMD1
) == token
) ||
73 (rt2x00_get_field32(reg
, H2M_MAILBOX_CID_CMD2
) == token
) ||
74 (rt2x00_get_field32(reg
, H2M_MAILBOX_CID_CMD3
) == token
))
77 udelay(REGISTER_BUSY_DELAY
);
81 ERROR(rt2x00dev
, "MCU request failed, no response from hardware\n");
83 rt2x00pci_register_write(rt2x00dev
, H2M_MAILBOX_STATUS
, ~0);
84 rt2x00pci_register_write(rt2x00dev
, H2M_MAILBOX_CID
, ~0);
87 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
88 static void rt2800pci_read_eeprom_soc(struct rt2x00_dev
*rt2x00dev
)
90 void __iomem
*base_addr
= ioremap(0x1F040000, EEPROM_SIZE
);
92 memcpy_fromio(rt2x00dev
->eeprom
, base_addr
, EEPROM_SIZE
);
97 static inline void rt2800pci_read_eeprom_soc(struct rt2x00_dev
*rt2x00dev
)
100 #endif /* CONFIG_RALINK_RT288X || CONFIG_RALINK_RT305X */
103 static void rt2800pci_eepromregister_read(struct eeprom_93cx6
*eeprom
)
105 struct rt2x00_dev
*rt2x00dev
= eeprom
->data
;
108 rt2x00pci_register_read(rt2x00dev
, E2PROM_CSR
, ®
);
110 eeprom
->reg_data_in
= !!rt2x00_get_field32(reg
, E2PROM_CSR_DATA_IN
);
111 eeprom
->reg_data_out
= !!rt2x00_get_field32(reg
, E2PROM_CSR_DATA_OUT
);
112 eeprom
->reg_data_clock
=
113 !!rt2x00_get_field32(reg
, E2PROM_CSR_DATA_CLOCK
);
114 eeprom
->reg_chip_select
=
115 !!rt2x00_get_field32(reg
, E2PROM_CSR_CHIP_SELECT
);
118 static void rt2800pci_eepromregister_write(struct eeprom_93cx6
*eeprom
)
120 struct rt2x00_dev
*rt2x00dev
= eeprom
->data
;
123 rt2x00_set_field32(®
, E2PROM_CSR_DATA_IN
, !!eeprom
->reg_data_in
);
124 rt2x00_set_field32(®
, E2PROM_CSR_DATA_OUT
, !!eeprom
->reg_data_out
);
125 rt2x00_set_field32(®
, E2PROM_CSR_DATA_CLOCK
,
126 !!eeprom
->reg_data_clock
);
127 rt2x00_set_field32(®
, E2PROM_CSR_CHIP_SELECT
,
128 !!eeprom
->reg_chip_select
);
130 rt2x00pci_register_write(rt2x00dev
, E2PROM_CSR
, reg
);
133 static void rt2800pci_read_eeprom_pci(struct rt2x00_dev
*rt2x00dev
)
135 struct eeprom_93cx6 eeprom
;
138 rt2x00pci_register_read(rt2x00dev
, E2PROM_CSR
, ®
);
140 eeprom
.data
= rt2x00dev
;
141 eeprom
.register_read
= rt2800pci_eepromregister_read
;
142 eeprom
.register_write
= rt2800pci_eepromregister_write
;
143 switch (rt2x00_get_field32(reg
, E2PROM_CSR_TYPE
))
146 eeprom
.width
= PCI_EEPROM_WIDTH_93C46
;
149 eeprom
.width
= PCI_EEPROM_WIDTH_93C66
;
152 eeprom
.width
= PCI_EEPROM_WIDTH_93C86
;
155 eeprom
.reg_data_in
= 0;
156 eeprom
.reg_data_out
= 0;
157 eeprom
.reg_data_clock
= 0;
158 eeprom
.reg_chip_select
= 0;
160 eeprom_93cx6_multiread(&eeprom
, EEPROM_BASE
, rt2x00dev
->eeprom
,
161 EEPROM_SIZE
/ sizeof(u16
));
164 static int rt2800pci_efuse_detect(struct rt2x00_dev
*rt2x00dev
)
166 return rt2800_efuse_detect(rt2x00dev
);
169 static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev
*rt2x00dev
)
171 rt2800_read_eeprom_efuse(rt2x00dev
);
174 static inline void rt2800pci_read_eeprom_pci(struct rt2x00_dev
*rt2x00dev
)
178 static inline int rt2800pci_efuse_detect(struct rt2x00_dev
*rt2x00dev
)
183 static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev
*rt2x00dev
)
186 #endif /* CONFIG_PCI */
191 static void rt2800pci_start_queue(struct data_queue
*queue
)
193 struct rt2x00_dev
*rt2x00dev
= queue
->rt2x00dev
;
196 switch (queue
->qid
) {
198 rt2x00pci_register_read(rt2x00dev
, MAC_SYS_CTRL
, ®
);
199 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_RX
, 1);
200 rt2x00pci_register_write(rt2x00dev
, MAC_SYS_CTRL
, reg
);
203 rt2x00pci_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
204 rt2x00_set_field32(®
, BCN_TIME_CFG_TSF_TICKING
, 1);
205 rt2x00_set_field32(®
, BCN_TIME_CFG_TBTT_ENABLE
, 1);
206 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_GEN
, 1);
207 rt2x00pci_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
209 rt2x00pci_register_read(rt2x00dev
, INT_TIMER_EN
, ®
);
210 rt2x00_set_field32(®
, INT_TIMER_EN_PRE_TBTT_TIMER
, 1);
211 rt2x00pci_register_write(rt2x00dev
, INT_TIMER_EN
, reg
);
218 static void rt2800pci_kick_queue(struct data_queue
*queue
)
220 struct rt2x00_dev
*rt2x00dev
= queue
->rt2x00dev
;
221 struct queue_entry
*entry
;
223 switch (queue
->qid
) {
228 entry
= rt2x00queue_get_entry(queue
, Q_INDEX
);
229 rt2x00pci_register_write(rt2x00dev
, TX_CTX_IDX(queue
->qid
),
233 entry
= rt2x00queue_get_entry(queue
, Q_INDEX
);
234 rt2x00pci_register_write(rt2x00dev
, TX_CTX_IDX(5),
242 static void rt2800pci_stop_queue(struct data_queue
*queue
)
244 struct rt2x00_dev
*rt2x00dev
= queue
->rt2x00dev
;
247 switch (queue
->qid
) {
249 rt2x00pci_register_read(rt2x00dev
, MAC_SYS_CTRL
, ®
);
250 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_RX
, 0);
251 rt2x00pci_register_write(rt2x00dev
, MAC_SYS_CTRL
, reg
);
254 rt2x00pci_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
255 rt2x00_set_field32(®
, BCN_TIME_CFG_TSF_TICKING
, 0);
256 rt2x00_set_field32(®
, BCN_TIME_CFG_TBTT_ENABLE
, 0);
257 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_GEN
, 0);
258 rt2x00pci_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
260 rt2x00pci_register_read(rt2x00dev
, INT_TIMER_EN
, ®
);
261 rt2x00_set_field32(®
, INT_TIMER_EN_PRE_TBTT_TIMER
, 0);
262 rt2x00pci_register_write(rt2x00dev
, INT_TIMER_EN
, reg
);
265 * Wait for current invocation to finish. The tasklet
266 * won't be scheduled anymore afterwards since we disabled
267 * the TBTT and PRE TBTT timer.
269 tasklet_kill(&rt2x00dev
->tbtt_tasklet
);
270 tasklet_kill(&rt2x00dev
->pretbtt_tasklet
);
281 static char *rt2800pci_get_firmware_name(struct rt2x00_dev
*rt2x00dev
)
283 return FIRMWARE_RT2860
;
286 static int rt2800pci_write_firmware(struct rt2x00_dev
*rt2x00dev
,
287 const u8
*data
, const size_t len
)
292 * enable Host program ram write selection
295 rt2x00_set_field32(®
, PBF_SYS_CTRL_HOST_RAM_WRITE
, 1);
296 rt2x00pci_register_write(rt2x00dev
, PBF_SYS_CTRL
, reg
);
299 * Write firmware to device.
301 rt2x00pci_register_multiwrite(rt2x00dev
, FIRMWARE_IMAGE_BASE
,
304 rt2x00pci_register_write(rt2x00dev
, PBF_SYS_CTRL
, 0x00000);
305 rt2x00pci_register_write(rt2x00dev
, PBF_SYS_CTRL
, 0x00001);
307 rt2x00pci_register_write(rt2x00dev
, H2M_BBP_AGENT
, 0);
308 rt2x00pci_register_write(rt2x00dev
, H2M_MAILBOX_CSR
, 0);
314 * Initialization functions.
316 static bool rt2800pci_get_entry_state(struct queue_entry
*entry
)
318 struct queue_entry_priv_pci
*entry_priv
= entry
->priv_data
;
321 if (entry
->queue
->qid
== QID_RX
) {
322 rt2x00_desc_read(entry_priv
->desc
, 1, &word
);
324 return (!rt2x00_get_field32(word
, RXD_W1_DMA_DONE
));
326 rt2x00_desc_read(entry_priv
->desc
, 1, &word
);
328 return (!rt2x00_get_field32(word
, TXD_W1_DMA_DONE
));
332 static void rt2800pci_clear_entry(struct queue_entry
*entry
)
334 struct queue_entry_priv_pci
*entry_priv
= entry
->priv_data
;
335 struct skb_frame_desc
*skbdesc
= get_skb_frame_desc(entry
->skb
);
336 struct rt2x00_dev
*rt2x00dev
= entry
->queue
->rt2x00dev
;
339 if (entry
->queue
->qid
== QID_RX
) {
340 rt2x00_desc_read(entry_priv
->desc
, 0, &word
);
341 rt2x00_set_field32(&word
, RXD_W0_SDP0
, skbdesc
->skb_dma
);
342 rt2x00_desc_write(entry_priv
->desc
, 0, word
);
344 rt2x00_desc_read(entry_priv
->desc
, 1, &word
);
345 rt2x00_set_field32(&word
, RXD_W1_DMA_DONE
, 0);
346 rt2x00_desc_write(entry_priv
->desc
, 1, word
);
349 * Set RX IDX in register to inform hardware that we have
350 * handled this entry and it is available for reuse again.
352 rt2x00pci_register_write(rt2x00dev
, RX_CRX_IDX
,
355 rt2x00_desc_read(entry_priv
->desc
, 1, &word
);
356 rt2x00_set_field32(&word
, TXD_W1_DMA_DONE
, 1);
357 rt2x00_desc_write(entry_priv
->desc
, 1, word
);
361 static int rt2800pci_init_queues(struct rt2x00_dev
*rt2x00dev
)
363 struct queue_entry_priv_pci
*entry_priv
;
366 * Initialize registers.
368 entry_priv
= rt2x00dev
->tx
[0].entries
[0].priv_data
;
369 rt2x00pci_register_write(rt2x00dev
, TX_BASE_PTR0
, entry_priv
->desc_dma
);
370 rt2x00pci_register_write(rt2x00dev
, TX_MAX_CNT0
,
371 rt2x00dev
->tx
[0].limit
);
372 rt2x00pci_register_write(rt2x00dev
, TX_CTX_IDX0
, 0);
373 rt2x00pci_register_write(rt2x00dev
, TX_DTX_IDX0
, 0);
375 entry_priv
= rt2x00dev
->tx
[1].entries
[0].priv_data
;
376 rt2x00pci_register_write(rt2x00dev
, TX_BASE_PTR1
, entry_priv
->desc_dma
);
377 rt2x00pci_register_write(rt2x00dev
, TX_MAX_CNT1
,
378 rt2x00dev
->tx
[1].limit
);
379 rt2x00pci_register_write(rt2x00dev
, TX_CTX_IDX1
, 0);
380 rt2x00pci_register_write(rt2x00dev
, TX_DTX_IDX1
, 0);
382 entry_priv
= rt2x00dev
->tx
[2].entries
[0].priv_data
;
383 rt2x00pci_register_write(rt2x00dev
, TX_BASE_PTR2
, entry_priv
->desc_dma
);
384 rt2x00pci_register_write(rt2x00dev
, TX_MAX_CNT2
,
385 rt2x00dev
->tx
[2].limit
);
386 rt2x00pci_register_write(rt2x00dev
, TX_CTX_IDX2
, 0);
387 rt2x00pci_register_write(rt2x00dev
, TX_DTX_IDX2
, 0);
389 entry_priv
= rt2x00dev
->tx
[3].entries
[0].priv_data
;
390 rt2x00pci_register_write(rt2x00dev
, TX_BASE_PTR3
, entry_priv
->desc_dma
);
391 rt2x00pci_register_write(rt2x00dev
, TX_MAX_CNT3
,
392 rt2x00dev
->tx
[3].limit
);
393 rt2x00pci_register_write(rt2x00dev
, TX_CTX_IDX3
, 0);
394 rt2x00pci_register_write(rt2x00dev
, TX_DTX_IDX3
, 0);
396 entry_priv
= rt2x00dev
->rx
->entries
[0].priv_data
;
397 rt2x00pci_register_write(rt2x00dev
, RX_BASE_PTR
, entry_priv
->desc_dma
);
398 rt2x00pci_register_write(rt2x00dev
, RX_MAX_CNT
,
399 rt2x00dev
->rx
[0].limit
);
400 rt2x00pci_register_write(rt2x00dev
, RX_CRX_IDX
,
401 rt2x00dev
->rx
[0].limit
- 1);
402 rt2x00pci_register_write(rt2x00dev
, RX_DRX_IDX
, 0);
404 rt2800_disable_wpdma(rt2x00dev
);
406 rt2x00pci_register_write(rt2x00dev
, DELAY_INT_CFG
, 0);
412 * Device state switch handlers.
414 static void rt2800pci_toggle_irq(struct rt2x00_dev
*rt2x00dev
,
415 enum dev_state state
)
421 * When interrupts are being enabled, the interrupt registers
422 * should clear the register to assure a clean state.
424 if (state
== STATE_RADIO_IRQ_ON
) {
425 rt2x00pci_register_read(rt2x00dev
, INT_SOURCE_CSR
, ®
);
426 rt2x00pci_register_write(rt2x00dev
, INT_SOURCE_CSR
, reg
);
429 spin_lock_irqsave(&rt2x00dev
->irqmask_lock
, flags
);
431 if (state
== STATE_RADIO_IRQ_ON
) {
432 rt2x00_set_field32(®
, INT_MASK_CSR_RX_DONE
, 1);
433 rt2x00_set_field32(®
, INT_MASK_CSR_TBTT
, 1);
434 rt2x00_set_field32(®
, INT_MASK_CSR_PRE_TBTT
, 1);
435 rt2x00_set_field32(®
, INT_MASK_CSR_TX_FIFO_STATUS
, 1);
436 rt2x00_set_field32(®
, INT_MASK_CSR_AUTO_WAKEUP
, 1);
438 rt2x00pci_register_write(rt2x00dev
, INT_MASK_CSR
, reg
);
439 spin_unlock_irqrestore(&rt2x00dev
->irqmask_lock
, flags
);
441 if (state
== STATE_RADIO_IRQ_OFF
) {
443 * Wait for possibly running tasklets to finish.
445 tasklet_kill(&rt2x00dev
->txstatus_tasklet
);
446 tasklet_kill(&rt2x00dev
->rxdone_tasklet
);
447 tasklet_kill(&rt2x00dev
->autowake_tasklet
);
448 tasklet_kill(&rt2x00dev
->tbtt_tasklet
);
449 tasklet_kill(&rt2x00dev
->pretbtt_tasklet
);
453 static int rt2800pci_init_registers(struct rt2x00_dev
*rt2x00dev
)
460 rt2x00pci_register_read(rt2x00dev
, WPDMA_RST_IDX
, ®
);
461 rt2x00_set_field32(®
, WPDMA_RST_IDX_DTX_IDX0
, 1);
462 rt2x00_set_field32(®
, WPDMA_RST_IDX_DTX_IDX1
, 1);
463 rt2x00_set_field32(®
, WPDMA_RST_IDX_DTX_IDX2
, 1);
464 rt2x00_set_field32(®
, WPDMA_RST_IDX_DTX_IDX3
, 1);
465 rt2x00_set_field32(®
, WPDMA_RST_IDX_DTX_IDX4
, 1);
466 rt2x00_set_field32(®
, WPDMA_RST_IDX_DTX_IDX5
, 1);
467 rt2x00_set_field32(®
, WPDMA_RST_IDX_DRX_IDX0
, 1);
468 rt2x00pci_register_write(rt2x00dev
, WPDMA_RST_IDX
, reg
);
470 rt2x00pci_register_write(rt2x00dev
, PBF_SYS_CTRL
, 0x00000e1f);
471 rt2x00pci_register_write(rt2x00dev
, PBF_SYS_CTRL
, 0x00000e00);
473 if (rt2x00_is_pcie(rt2x00dev
) &&
474 (rt2x00_rt(rt2x00dev
, RT3572
) ||
475 rt2x00_rt(rt2x00dev
, RT5390
) ||
476 rt2x00_rt(rt2x00dev
, RT5392
))) {
477 rt2x00pci_register_read(rt2x00dev
, AUX_CTRL
, ®
);
478 rt2x00_set_field32(®
, AUX_CTRL_FORCE_PCIE_CLK
, 1);
479 rt2x00_set_field32(®
, AUX_CTRL_WAKE_PCIE_EN
, 1);
480 rt2x00pci_register_write(rt2x00dev
, AUX_CTRL
, reg
);
483 rt2x00pci_register_write(rt2x00dev
, PWR_PIN_CFG
, 0x00000003);
486 rt2x00_set_field32(®
, MAC_SYS_CTRL_RESET_CSR
, 1);
487 rt2x00_set_field32(®
, MAC_SYS_CTRL_RESET_BBP
, 1);
488 rt2x00pci_register_write(rt2x00dev
, MAC_SYS_CTRL
, reg
);
490 rt2x00pci_register_write(rt2x00dev
, MAC_SYS_CTRL
, 0x00000000);
495 static int rt2800pci_enable_radio(struct rt2x00_dev
*rt2x00dev
)
499 /* Wait for DMA, ignore error until we initialize queues. */
500 rt2800_wait_wpdma_ready(rt2x00dev
);
502 if (unlikely(rt2800pci_init_queues(rt2x00dev
)))
505 retval
= rt2800_enable_radio(rt2x00dev
);
509 /* After resume MCU_BOOT_SIGNAL will trash these. */
510 rt2x00pci_register_write(rt2x00dev
, H2M_MAILBOX_STATUS
, ~0);
511 rt2x00pci_register_write(rt2x00dev
, H2M_MAILBOX_CID
, ~0);
513 rt2800_mcu_request(rt2x00dev
, MCU_SLEEP
, TOKEN_RADIO_OFF
, 0xff, 0x02);
514 rt2800pci_mcu_status(rt2x00dev
, TOKEN_RADIO_OFF
);
516 rt2800_mcu_request(rt2x00dev
, MCU_WAKEUP
, TOKEN_WAKEUP
, 0, 0);
517 rt2800pci_mcu_status(rt2x00dev
, TOKEN_WAKEUP
);
522 static void rt2800pci_disable_radio(struct rt2x00_dev
*rt2x00dev
)
524 if (rt2x00_is_soc(rt2x00dev
)) {
525 rt2800_disable_radio(rt2x00dev
);
526 rt2x00pci_register_write(rt2x00dev
, PWR_PIN_CFG
, 0);
527 rt2x00pci_register_write(rt2x00dev
, TX_PIN_CFG
, 0);
531 static int rt2800pci_set_state(struct rt2x00_dev
*rt2x00dev
,
532 enum dev_state state
)
534 if (state
== STATE_AWAKE
) {
535 rt2800_mcu_request(rt2x00dev
, MCU_WAKEUP
, TOKEN_WAKEUP
,
537 rt2800pci_mcu_status(rt2x00dev
, TOKEN_WAKEUP
);
538 } else if (state
== STATE_SLEEP
) {
539 rt2x00pci_register_write(rt2x00dev
, H2M_MAILBOX_STATUS
,
541 rt2x00pci_register_write(rt2x00dev
, H2M_MAILBOX_CID
,
543 rt2800_mcu_request(rt2x00dev
, MCU_SLEEP
, TOKEN_SLEEP
,
550 static int rt2800pci_set_device_state(struct rt2x00_dev
*rt2x00dev
,
551 enum dev_state state
)
557 retval
= rt2800pci_enable_radio(rt2x00dev
);
559 case STATE_RADIO_OFF
:
561 * After the radio has been disabled, the device should
562 * be put to sleep for powersaving.
564 rt2800pci_disable_radio(rt2x00dev
);
565 rt2800pci_set_state(rt2x00dev
, STATE_SLEEP
);
567 case STATE_RADIO_IRQ_ON
:
568 case STATE_RADIO_IRQ_OFF
:
569 rt2800pci_toggle_irq(rt2x00dev
, state
);
571 case STATE_DEEP_SLEEP
:
575 retval
= rt2800pci_set_state(rt2x00dev
, state
);
582 if (unlikely(retval
))
583 ERROR(rt2x00dev
, "Device failed to enter state %d (%d).\n",
590 * TX descriptor initialization
592 static __le32
*rt2800pci_get_txwi(struct queue_entry
*entry
)
594 return (__le32
*) entry
->skb
->data
;
597 static void rt2800pci_write_tx_desc(struct queue_entry
*entry
,
598 struct txentry_desc
*txdesc
)
600 struct skb_frame_desc
*skbdesc
= get_skb_frame_desc(entry
->skb
);
601 struct queue_entry_priv_pci
*entry_priv
= entry
->priv_data
;
602 __le32
*txd
= entry_priv
->desc
;
606 * The buffers pointed by SD_PTR0/SD_LEN0 and SD_PTR1/SD_LEN1
607 * must contains a TXWI structure + 802.11 header + padding + 802.11
608 * data. We choose to have SD_PTR0/SD_LEN0 only contains TXWI and
609 * SD_PTR1/SD_LEN1 contains 802.11 header + padding + 802.11
610 * data. It means that LAST_SEC0 is always 0.
614 * Initialize TX descriptor
617 rt2x00_set_field32(&word
, TXD_W0_SD_PTR0
, skbdesc
->skb_dma
);
618 rt2x00_desc_write(txd
, 0, word
);
621 rt2x00_set_field32(&word
, TXD_W1_SD_LEN1
, entry
->skb
->len
);
622 rt2x00_set_field32(&word
, TXD_W1_LAST_SEC1
,
623 !test_bit(ENTRY_TXD_MORE_FRAG
, &txdesc
->flags
));
624 rt2x00_set_field32(&word
, TXD_W1_BURST
,
625 test_bit(ENTRY_TXD_BURST
, &txdesc
->flags
));
626 rt2x00_set_field32(&word
, TXD_W1_SD_LEN0
, TXWI_DESC_SIZE
);
627 rt2x00_set_field32(&word
, TXD_W1_LAST_SEC0
, 0);
628 rt2x00_set_field32(&word
, TXD_W1_DMA_DONE
, 0);
629 rt2x00_desc_write(txd
, 1, word
);
632 rt2x00_set_field32(&word
, TXD_W2_SD_PTR1
,
633 skbdesc
->skb_dma
+ TXWI_DESC_SIZE
);
634 rt2x00_desc_write(txd
, 2, word
);
637 rt2x00_set_field32(&word
, TXD_W3_WIV
,
638 !test_bit(ENTRY_TXD_ENCRYPT_IV
, &txdesc
->flags
));
639 rt2x00_set_field32(&word
, TXD_W3_QSEL
, 2);
640 rt2x00_desc_write(txd
, 3, word
);
643 * Register descriptor details in skb frame descriptor.
646 skbdesc
->desc_len
= TXD_DESC_SIZE
;
650 * RX control handlers
652 static void rt2800pci_fill_rxdone(struct queue_entry
*entry
,
653 struct rxdone_entry_desc
*rxdesc
)
655 struct queue_entry_priv_pci
*entry_priv
= entry
->priv_data
;
656 __le32
*rxd
= entry_priv
->desc
;
659 rt2x00_desc_read(rxd
, 3, &word
);
661 if (rt2x00_get_field32(word
, RXD_W3_CRC_ERROR
))
662 rxdesc
->flags
|= RX_FLAG_FAILED_FCS_CRC
;
665 * Unfortunately we don't know the cipher type used during
666 * decryption. This prevents us from correct providing
667 * correct statistics through debugfs.
669 rxdesc
->cipher_status
= rt2x00_get_field32(word
, RXD_W3_CIPHER_ERROR
);
671 if (rt2x00_get_field32(word
, RXD_W3_DECRYPTED
)) {
673 * Hardware has stripped IV/EIV data from 802.11 frame during
674 * decryption. Unfortunately the descriptor doesn't contain
675 * any fields with the EIV/IV data either, so they can't
676 * be restored by rt2x00lib.
678 rxdesc
->flags
|= RX_FLAG_IV_STRIPPED
;
681 * The hardware has already checked the Michael Mic and has
682 * stripped it from the frame. Signal this to mac80211.
684 rxdesc
->flags
|= RX_FLAG_MMIC_STRIPPED
;
686 if (rxdesc
->cipher_status
== RX_CRYPTO_SUCCESS
)
687 rxdesc
->flags
|= RX_FLAG_DECRYPTED
;
688 else if (rxdesc
->cipher_status
== RX_CRYPTO_FAIL_MIC
)
689 rxdesc
->flags
|= RX_FLAG_MMIC_ERROR
;
692 if (rt2x00_get_field32(word
, RXD_W3_MY_BSS
))
693 rxdesc
->dev_flags
|= RXDONE_MY_BSS
;
695 if (rt2x00_get_field32(word
, RXD_W3_L2PAD
))
696 rxdesc
->dev_flags
|= RXDONE_L2PAD
;
699 * Process the RXWI structure that is at the start of the buffer.
701 rt2800_process_rxwi(entry
, rxdesc
);
705 * Interrupt functions.
707 static void rt2800pci_wakeup(struct rt2x00_dev
*rt2x00dev
)
709 struct ieee80211_conf conf
= { .flags
= 0 };
710 struct rt2x00lib_conf libconf
= { .conf
= &conf
};
712 rt2800_config(rt2x00dev
, &libconf
, IEEE80211_CONF_CHANGE_PS
);
715 static bool rt2800pci_txdone(struct rt2x00_dev
*rt2x00dev
)
717 struct data_queue
*queue
;
718 struct queue_entry
*entry
;
721 int max_tx_done
= 16;
723 while (kfifo_get(&rt2x00dev
->txstatus_fifo
, &status
)) {
724 qid
= rt2x00_get_field32(status
, TX_STA_FIFO_PID_QUEUE
);
725 if (unlikely(qid
>= QID_RX
)) {
727 * Unknown queue, this shouldn't happen. Just drop
730 WARNING(rt2x00dev
, "Got TX status report with "
731 "unexpected pid %u, dropping\n", qid
);
735 queue
= rt2x00queue_get_tx_queue(rt2x00dev
, qid
);
736 if (unlikely(queue
== NULL
)) {
738 * The queue is NULL, this shouldn't happen. Stop
739 * processing here and drop the tx status
741 WARNING(rt2x00dev
, "Got TX status for an unavailable "
742 "queue %u, dropping\n", qid
);
746 if (unlikely(rt2x00queue_empty(queue
))) {
748 * The queue is empty. Stop processing here
749 * and drop the tx status.
751 WARNING(rt2x00dev
, "Got TX status for an empty "
752 "queue %u, dropping\n", qid
);
756 entry
= rt2x00queue_get_entry(queue
, Q_INDEX_DONE
);
757 rt2800_txdone_entry(entry
, status
, rt2800pci_get_txwi(entry
));
759 if (--max_tx_done
== 0)
766 static inline void rt2800pci_enable_interrupt(struct rt2x00_dev
*rt2x00dev
,
767 struct rt2x00_field32 irq_field
)
772 * Enable a single interrupt. The interrupt mask register
773 * access needs locking.
775 spin_lock_irq(&rt2x00dev
->irqmask_lock
);
776 rt2x00pci_register_read(rt2x00dev
, INT_MASK_CSR
, ®
);
777 rt2x00_set_field32(®
, irq_field
, 1);
778 rt2x00pci_register_write(rt2x00dev
, INT_MASK_CSR
, reg
);
779 spin_unlock_irq(&rt2x00dev
->irqmask_lock
);
782 static void rt2800pci_txstatus_tasklet(unsigned long data
)
784 struct rt2x00_dev
*rt2x00dev
= (struct rt2x00_dev
*)data
;
785 if (rt2800pci_txdone(rt2x00dev
))
786 tasklet_schedule(&rt2x00dev
->txstatus_tasklet
);
789 * No need to enable the tx status interrupt here as we always
790 * leave it enabled to minimize the possibility of a tx status
791 * register overflow. See comment in interrupt handler.
795 static void rt2800pci_pretbtt_tasklet(unsigned long data
)
797 struct rt2x00_dev
*rt2x00dev
= (struct rt2x00_dev
*)data
;
798 rt2x00lib_pretbtt(rt2x00dev
);
799 if (test_bit(DEVICE_STATE_ENABLED_RADIO
, &rt2x00dev
->flags
))
800 rt2800pci_enable_interrupt(rt2x00dev
, INT_MASK_CSR_PRE_TBTT
);
803 static void rt2800pci_tbtt_tasklet(unsigned long data
)
805 struct rt2x00_dev
*rt2x00dev
= (struct rt2x00_dev
*)data
;
806 struct rt2800_drv_data
*drv_data
= rt2x00dev
->drv_data
;
809 rt2x00lib_beacondone(rt2x00dev
);
811 if (rt2x00dev
->intf_ap_count
) {
813 * The rt2800pci hardware tbtt timer is off by 1us per tbtt
814 * causing beacon skew and as a result causing problems with
815 * some powersaving clients over time. Shorten the beacon
816 * interval every 64 beacons by 64us to mitigate this effect.
818 if (drv_data
->tbtt_tick
== (BCN_TBTT_OFFSET
- 2)) {
819 rt2x00pci_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
820 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_INTERVAL
,
821 (rt2x00dev
->beacon_int
* 16) - 1);
822 rt2x00pci_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
823 } else if (drv_data
->tbtt_tick
== (BCN_TBTT_OFFSET
- 1)) {
824 rt2x00pci_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
825 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_INTERVAL
,
826 (rt2x00dev
->beacon_int
* 16));
827 rt2x00pci_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
829 drv_data
->tbtt_tick
++;
830 drv_data
->tbtt_tick
%= BCN_TBTT_OFFSET
;
833 if (test_bit(DEVICE_STATE_ENABLED_RADIO
, &rt2x00dev
->flags
))
834 rt2800pci_enable_interrupt(rt2x00dev
, INT_MASK_CSR_TBTT
);
837 static void rt2800pci_rxdone_tasklet(unsigned long data
)
839 struct rt2x00_dev
*rt2x00dev
= (struct rt2x00_dev
*)data
;
840 if (rt2x00pci_rxdone(rt2x00dev
))
841 tasklet_schedule(&rt2x00dev
->rxdone_tasklet
);
842 else if (test_bit(DEVICE_STATE_ENABLED_RADIO
, &rt2x00dev
->flags
))
843 rt2800pci_enable_interrupt(rt2x00dev
, INT_MASK_CSR_RX_DONE
);
846 static void rt2800pci_autowake_tasklet(unsigned long data
)
848 struct rt2x00_dev
*rt2x00dev
= (struct rt2x00_dev
*)data
;
849 rt2800pci_wakeup(rt2x00dev
);
850 if (test_bit(DEVICE_STATE_ENABLED_RADIO
, &rt2x00dev
->flags
))
851 rt2800pci_enable_interrupt(rt2x00dev
, INT_MASK_CSR_AUTO_WAKEUP
);
854 static void rt2800pci_txstatus_interrupt(struct rt2x00_dev
*rt2x00dev
)
860 * The TX_FIFO_STATUS interrupt needs special care. We should
861 * read TX_STA_FIFO but we should do it immediately as otherwise
862 * the register can overflow and we would lose status reports.
864 * Hence, read the TX_STA_FIFO register and copy all tx status
865 * reports into a kernel FIFO which is handled in the txstatus
866 * tasklet. We use a tasklet to process the tx status reports
867 * because we can schedule the tasklet multiple times (when the
868 * interrupt fires again during tx status processing).
870 * Furthermore we don't disable the TX_FIFO_STATUS
871 * interrupt here but leave it enabled so that the TX_STA_FIFO
872 * can also be read while the tx status tasklet gets executed.
874 * Since we have only one producer and one consumer we don't
875 * need to lock the kfifo.
877 for (i
= 0; i
< rt2x00dev
->ops
->tx
->entry_num
; i
++) {
878 rt2x00pci_register_read(rt2x00dev
, TX_STA_FIFO
, &status
);
880 if (!rt2x00_get_field32(status
, TX_STA_FIFO_VALID
))
883 if (!kfifo_put(&rt2x00dev
->txstatus_fifo
, &status
)) {
884 WARNING(rt2x00dev
, "TX status FIFO overrun,"
885 "drop tx status report.\n");
890 /* Schedule the tasklet for processing the tx status. */
891 tasklet_schedule(&rt2x00dev
->txstatus_tasklet
);
894 static irqreturn_t
rt2800pci_interrupt(int irq
, void *dev_instance
)
896 struct rt2x00_dev
*rt2x00dev
= dev_instance
;
899 /* Read status and ACK all interrupts */
900 rt2x00pci_register_read(rt2x00dev
, INT_SOURCE_CSR
, ®
);
901 rt2x00pci_register_write(rt2x00dev
, INT_SOURCE_CSR
, reg
);
906 if (!test_bit(DEVICE_STATE_ENABLED_RADIO
, &rt2x00dev
->flags
))
910 * Since INT_MASK_CSR and INT_SOURCE_CSR use the same bits
911 * for interrupts and interrupt masks we can just use the value of
912 * INT_SOURCE_CSR to create the interrupt mask.
916 if (rt2x00_get_field32(reg
, INT_SOURCE_CSR_TX_FIFO_STATUS
)) {
917 rt2800pci_txstatus_interrupt(rt2x00dev
);
919 * Never disable the TX_FIFO_STATUS interrupt.
921 rt2x00_set_field32(&mask
, INT_MASK_CSR_TX_FIFO_STATUS
, 1);
924 if (rt2x00_get_field32(reg
, INT_SOURCE_CSR_PRE_TBTT
))
925 tasklet_hi_schedule(&rt2x00dev
->pretbtt_tasklet
);
927 if (rt2x00_get_field32(reg
, INT_SOURCE_CSR_TBTT
))
928 tasklet_hi_schedule(&rt2x00dev
->tbtt_tasklet
);
930 if (rt2x00_get_field32(reg
, INT_SOURCE_CSR_RX_DONE
))
931 tasklet_schedule(&rt2x00dev
->rxdone_tasklet
);
933 if (rt2x00_get_field32(reg
, INT_SOURCE_CSR_AUTO_WAKEUP
))
934 tasklet_schedule(&rt2x00dev
->autowake_tasklet
);
937 * Disable all interrupts for which a tasklet was scheduled right now,
938 * the tasklet will reenable the appropriate interrupts.
940 spin_lock(&rt2x00dev
->irqmask_lock
);
941 rt2x00pci_register_read(rt2x00dev
, INT_MASK_CSR
, ®
);
943 rt2x00pci_register_write(rt2x00dev
, INT_MASK_CSR
, reg
);
944 spin_unlock(&rt2x00dev
->irqmask_lock
);
950 * Device probe functions.
952 static int rt2800pci_validate_eeprom(struct rt2x00_dev
*rt2x00dev
)
955 * Read EEPROM into buffer
957 if (rt2x00_is_soc(rt2x00dev
))
958 rt2800pci_read_eeprom_soc(rt2x00dev
);
959 else if (rt2800pci_efuse_detect(rt2x00dev
))
960 rt2800pci_read_eeprom_efuse(rt2x00dev
);
962 rt2800pci_read_eeprom_pci(rt2x00dev
);
964 return rt2800_validate_eeprom(rt2x00dev
);
967 static int rt2800pci_probe_hw(struct rt2x00_dev
*rt2x00dev
)
972 * Allocate eeprom data.
974 retval
= rt2800pci_validate_eeprom(rt2x00dev
);
978 retval
= rt2800_init_eeprom(rt2x00dev
);
983 * Initialize hw specifications.
985 retval
= rt2800_probe_hw_mode(rt2x00dev
);
990 * This device has multiple filters for control frames
991 * and has a separate filter for PS Poll frames.
993 __set_bit(CAPABILITY_CONTROL_FILTERS
, &rt2x00dev
->cap_flags
);
994 __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL
, &rt2x00dev
->cap_flags
);
997 * This device has a pre tbtt interrupt and thus fetches
998 * a new beacon directly prior to transmission.
1000 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT
, &rt2x00dev
->cap_flags
);
1003 * This device requires firmware.
1005 if (!rt2x00_is_soc(rt2x00dev
))
1006 __set_bit(REQUIRE_FIRMWARE
, &rt2x00dev
->cap_flags
);
1007 __set_bit(REQUIRE_DMA
, &rt2x00dev
->cap_flags
);
1008 __set_bit(REQUIRE_L2PAD
, &rt2x00dev
->cap_flags
);
1009 __set_bit(REQUIRE_TXSTATUS_FIFO
, &rt2x00dev
->cap_flags
);
1010 __set_bit(REQUIRE_TASKLET_CONTEXT
, &rt2x00dev
->cap_flags
);
1011 if (!modparam_nohwcrypt
)
1012 __set_bit(CAPABILITY_HW_CRYPTO
, &rt2x00dev
->cap_flags
);
1013 __set_bit(CAPABILITY_LINK_TUNING
, &rt2x00dev
->cap_flags
);
1014 __set_bit(REQUIRE_HT_TX_DESC
, &rt2x00dev
->cap_flags
);
1017 * Set the rssi offset.
1019 rt2x00dev
->rssi_offset
= DEFAULT_RSSI_OFFSET
;
1024 static const struct ieee80211_ops rt2800pci_mac80211_ops
= {
1026 .start
= rt2x00mac_start
,
1027 .stop
= rt2x00mac_stop
,
1028 .add_interface
= rt2x00mac_add_interface
,
1029 .remove_interface
= rt2x00mac_remove_interface
,
1030 .config
= rt2x00mac_config
,
1031 .configure_filter
= rt2x00mac_configure_filter
,
1032 .set_key
= rt2x00mac_set_key
,
1033 .sw_scan_start
= rt2x00mac_sw_scan_start
,
1034 .sw_scan_complete
= rt2x00mac_sw_scan_complete
,
1035 .get_stats
= rt2x00mac_get_stats
,
1036 .get_tkip_seq
= rt2800_get_tkip_seq
,
1037 .set_rts_threshold
= rt2800_set_rts_threshold
,
1038 .sta_add
= rt2x00mac_sta_add
,
1039 .sta_remove
= rt2x00mac_sta_remove
,
1040 .bss_info_changed
= rt2x00mac_bss_info_changed
,
1041 .conf_tx
= rt2800_conf_tx
,
1042 .get_tsf
= rt2800_get_tsf
,
1043 .rfkill_poll
= rt2x00mac_rfkill_poll
,
1044 .ampdu_action
= rt2800_ampdu_action
,
1045 .flush
= rt2x00mac_flush
,
1046 .get_survey
= rt2800_get_survey
,
1047 .get_ringparam
= rt2x00mac_get_ringparam
,
1048 .tx_frames_pending
= rt2x00mac_tx_frames_pending
,
1051 static const struct rt2800_ops rt2800pci_rt2800_ops
= {
1052 .register_read
= rt2x00pci_register_read
,
1053 .register_read_lock
= rt2x00pci_register_read
, /* same for PCI */
1054 .register_write
= rt2x00pci_register_write
,
1055 .register_write_lock
= rt2x00pci_register_write
, /* same for PCI */
1056 .register_multiread
= rt2x00pci_register_multiread
,
1057 .register_multiwrite
= rt2x00pci_register_multiwrite
,
1058 .regbusy_read
= rt2x00pci_regbusy_read
,
1059 .drv_write_firmware
= rt2800pci_write_firmware
,
1060 .drv_init_registers
= rt2800pci_init_registers
,
1061 .drv_get_txwi
= rt2800pci_get_txwi
,
1064 static const struct rt2x00lib_ops rt2800pci_rt2x00_ops
= {
1065 .irq_handler
= rt2800pci_interrupt
,
1066 .txstatus_tasklet
= rt2800pci_txstatus_tasklet
,
1067 .pretbtt_tasklet
= rt2800pci_pretbtt_tasklet
,
1068 .tbtt_tasklet
= rt2800pci_tbtt_tasklet
,
1069 .rxdone_tasklet
= rt2800pci_rxdone_tasklet
,
1070 .autowake_tasklet
= rt2800pci_autowake_tasklet
,
1071 .probe_hw
= rt2800pci_probe_hw
,
1072 .get_firmware_name
= rt2800pci_get_firmware_name
,
1073 .check_firmware
= rt2800_check_firmware
,
1074 .load_firmware
= rt2800_load_firmware
,
1075 .initialize
= rt2x00pci_initialize
,
1076 .uninitialize
= rt2x00pci_uninitialize
,
1077 .get_entry_state
= rt2800pci_get_entry_state
,
1078 .clear_entry
= rt2800pci_clear_entry
,
1079 .set_device_state
= rt2800pci_set_device_state
,
1080 .rfkill_poll
= rt2800_rfkill_poll
,
1081 .link_stats
= rt2800_link_stats
,
1082 .reset_tuner
= rt2800_reset_tuner
,
1083 .link_tuner
= rt2800_link_tuner
,
1084 .gain_calibration
= rt2800_gain_calibration
,
1085 .vco_calibration
= rt2800_vco_calibration
,
1086 .start_queue
= rt2800pci_start_queue
,
1087 .kick_queue
= rt2800pci_kick_queue
,
1088 .stop_queue
= rt2800pci_stop_queue
,
1089 .flush_queue
= rt2x00pci_flush_queue
,
1090 .write_tx_desc
= rt2800pci_write_tx_desc
,
1091 .write_tx_data
= rt2800_write_tx_data
,
1092 .write_beacon
= rt2800_write_beacon
,
1093 .clear_beacon
= rt2800_clear_beacon
,
1094 .fill_rxdone
= rt2800pci_fill_rxdone
,
1095 .config_shared_key
= rt2800_config_shared_key
,
1096 .config_pairwise_key
= rt2800_config_pairwise_key
,
1097 .config_filter
= rt2800_config_filter
,
1098 .config_intf
= rt2800_config_intf
,
1099 .config_erp
= rt2800_config_erp
,
1100 .config_ant
= rt2800_config_ant
,
1101 .config
= rt2800_config
,
1102 .sta_add
= rt2800_sta_add
,
1103 .sta_remove
= rt2800_sta_remove
,
1106 static const struct data_queue_desc rt2800pci_queue_rx
= {
1108 .data_size
= AGGREGATION_SIZE
,
1109 .desc_size
= RXD_DESC_SIZE
,
1110 .priv_size
= sizeof(struct queue_entry_priv_pci
),
1113 static const struct data_queue_desc rt2800pci_queue_tx
= {
1115 .data_size
= AGGREGATION_SIZE
,
1116 .desc_size
= TXD_DESC_SIZE
,
1117 .priv_size
= sizeof(struct queue_entry_priv_pci
),
1120 static const struct data_queue_desc rt2800pci_queue_bcn
= {
1122 .data_size
= 0, /* No DMA required for beacons */
1123 .desc_size
= TXWI_DESC_SIZE
,
1124 .priv_size
= sizeof(struct queue_entry_priv_pci
),
1127 static const struct rt2x00_ops rt2800pci_ops
= {
1128 .name
= KBUILD_MODNAME
,
1129 .drv_data_size
= sizeof(struct rt2800_drv_data
),
1132 .eeprom_size
= EEPROM_SIZE
,
1134 .tx_queues
= NUM_TX_QUEUES
,
1135 .extra_tx_headroom
= TXWI_DESC_SIZE
,
1136 .rx
= &rt2800pci_queue_rx
,
1137 .tx
= &rt2800pci_queue_tx
,
1138 .bcn
= &rt2800pci_queue_bcn
,
1139 .lib
= &rt2800pci_rt2x00_ops
,
1140 .drv
= &rt2800pci_rt2800_ops
,
1141 .hw
= &rt2800pci_mac80211_ops
,
1142 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1143 .debugfs
= &rt2800_rt2x00debug
,
1144 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1148 * RT2800pci module information.
1151 static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table
) = {
1152 { PCI_DEVICE(0x1814, 0x0601) },
1153 { PCI_DEVICE(0x1814, 0x0681) },
1154 { PCI_DEVICE(0x1814, 0x0701) },
1155 { PCI_DEVICE(0x1814, 0x0781) },
1156 { PCI_DEVICE(0x1814, 0x3090) },
1157 { PCI_DEVICE(0x1814, 0x3091) },
1158 { PCI_DEVICE(0x1814, 0x3092) },
1159 { PCI_DEVICE(0x1432, 0x7708) },
1160 { PCI_DEVICE(0x1432, 0x7727) },
1161 { PCI_DEVICE(0x1432, 0x7728) },
1162 { PCI_DEVICE(0x1432, 0x7738) },
1163 { PCI_DEVICE(0x1432, 0x7748) },
1164 { PCI_DEVICE(0x1432, 0x7758) },
1165 { PCI_DEVICE(0x1432, 0x7768) },
1166 { PCI_DEVICE(0x1462, 0x891a) },
1167 { PCI_DEVICE(0x1a3b, 0x1059) },
1168 #ifdef CONFIG_RT2800PCI_RT33XX
1169 { PCI_DEVICE(0x1814, 0x3390) },
1171 #ifdef CONFIG_RT2800PCI_RT35XX
1172 { PCI_DEVICE(0x1432, 0x7711) },
1173 { PCI_DEVICE(0x1432, 0x7722) },
1174 { PCI_DEVICE(0x1814, 0x3060) },
1175 { PCI_DEVICE(0x1814, 0x3062) },
1176 { PCI_DEVICE(0x1814, 0x3562) },
1177 { PCI_DEVICE(0x1814, 0x3592) },
1178 { PCI_DEVICE(0x1814, 0x3593) },
1180 #ifdef CONFIG_RT2800PCI_RT53XX
1181 { PCI_DEVICE(0x1814, 0x5390) },
1182 { PCI_DEVICE(0x1814, 0x539a) },
1183 { PCI_DEVICE(0x1814, 0x539f) },
1187 #endif /* CONFIG_PCI */
1189 MODULE_AUTHOR(DRV_PROJECT
);
1190 MODULE_VERSION(DRV_VERSION
);
1191 MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
1192 MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
1194 MODULE_FIRMWARE(FIRMWARE_RT2860
);
1195 MODULE_DEVICE_TABLE(pci
, rt2800pci_device_table
);
1196 #endif /* CONFIG_PCI */
1197 MODULE_LICENSE("GPL");
1199 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
1200 static int rt2800soc_probe(struct platform_device
*pdev
)
1202 return rt2x00soc_probe(pdev
, &rt2800pci_ops
);
1205 static struct platform_driver rt2800soc_driver
= {
1207 .name
= "rt2800_wmac",
1208 .owner
= THIS_MODULE
,
1209 .mod_name
= KBUILD_MODNAME
,
1211 .probe
= rt2800soc_probe
,
1212 .remove
= __devexit_p(rt2x00soc_remove
),
1213 .suspend
= rt2x00soc_suspend
,
1214 .resume
= rt2x00soc_resume
,
1216 #endif /* CONFIG_RALINK_RT288X || CONFIG_RALINK_RT305X */
1219 static int rt2800pci_probe(struct pci_dev
*pci_dev
,
1220 const struct pci_device_id
*id
)
1222 return rt2x00pci_probe(pci_dev
, &rt2800pci_ops
);
1225 static struct pci_driver rt2800pci_driver
= {
1226 .name
= KBUILD_MODNAME
,
1227 .id_table
= rt2800pci_device_table
,
1228 .probe
= rt2800pci_probe
,
1229 .remove
= __devexit_p(rt2x00pci_remove
),
1230 .suspend
= rt2x00pci_suspend
,
1231 .resume
= rt2x00pci_resume
,
1233 #endif /* CONFIG_PCI */
1235 static int __init
rt2800pci_init(void)
1239 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
1240 ret
= platform_driver_register(&rt2800soc_driver
);
1245 ret
= pci_register_driver(&rt2800pci_driver
);
1247 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
1248 platform_driver_unregister(&rt2800soc_driver
);
1257 static void __exit
rt2800pci_exit(void)
1260 pci_unregister_driver(&rt2800pci_driver
);
1262 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
1263 platform_driver_unregister(&rt2800soc_driver
);
1267 module_init(rt2800pci_init
);
1268 module_exit(rt2800pci_exit
);