2 Copyright (C) 2009 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
3 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
4 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
6 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
7 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
8 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
9 Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
10 <http://rt2x00.serialmonkey.com>
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the
24 Free Software Foundation, Inc.,
25 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 Abstract: rt2800pci device specific routines.
31 Supported chipsets: RT2800E & RT2800ED.
34 #include <linux/delay.h>
35 #include <linux/etherdevice.h>
36 #include <linux/init.h>
37 #include <linux/kernel.h>
38 #include <linux/module.h>
39 #include <linux/pci.h>
40 #include <linux/platform_device.h>
41 #include <linux/eeprom_93cx6.h>
44 #include "rt2x00pci.h"
45 #include "rt2x00soc.h"
46 #include "rt2800lib.h"
48 #include "rt2800pci.h"
51 * Allow hardware encryption to be disabled.
53 static bool modparam_nohwcrypt
= false;
54 module_param_named(nohwcrypt
, modparam_nohwcrypt
, bool, S_IRUGO
);
55 MODULE_PARM_DESC(nohwcrypt
, "Disable hardware encryption.");
57 static void rt2800pci_mcu_status(struct rt2x00_dev
*rt2x00dev
, const u8 token
)
63 * SOC devices don't support MCU requests.
65 if (rt2x00_is_soc(rt2x00dev
))
68 for (i
= 0; i
< 200; i
++) {
69 rt2x00pci_register_read(rt2x00dev
, H2M_MAILBOX_CID
, ®
);
71 if ((rt2x00_get_field32(reg
, H2M_MAILBOX_CID_CMD0
) == token
) ||
72 (rt2x00_get_field32(reg
, H2M_MAILBOX_CID_CMD1
) == token
) ||
73 (rt2x00_get_field32(reg
, H2M_MAILBOX_CID_CMD2
) == token
) ||
74 (rt2x00_get_field32(reg
, H2M_MAILBOX_CID_CMD3
) == token
))
77 udelay(REGISTER_BUSY_DELAY
);
81 ERROR(rt2x00dev
, "MCU request failed, no response from hardware\n");
83 rt2x00pci_register_write(rt2x00dev
, H2M_MAILBOX_STATUS
, ~0);
84 rt2x00pci_register_write(rt2x00dev
, H2M_MAILBOX_CID
, ~0);
87 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
88 static void rt2800pci_read_eeprom_soc(struct rt2x00_dev
*rt2x00dev
)
90 void __iomem
*base_addr
= ioremap(0x1F040000, EEPROM_SIZE
);
92 memcpy_fromio(rt2x00dev
->eeprom
, base_addr
, EEPROM_SIZE
);
97 static inline void rt2800pci_read_eeprom_soc(struct rt2x00_dev
*rt2x00dev
)
100 #endif /* CONFIG_RALINK_RT288X || CONFIG_RALINK_RT305X */
103 static void rt2800pci_eepromregister_read(struct eeprom_93cx6
*eeprom
)
105 struct rt2x00_dev
*rt2x00dev
= eeprom
->data
;
108 rt2x00pci_register_read(rt2x00dev
, E2PROM_CSR
, ®
);
110 eeprom
->reg_data_in
= !!rt2x00_get_field32(reg
, E2PROM_CSR_DATA_IN
);
111 eeprom
->reg_data_out
= !!rt2x00_get_field32(reg
, E2PROM_CSR_DATA_OUT
);
112 eeprom
->reg_data_clock
=
113 !!rt2x00_get_field32(reg
, E2PROM_CSR_DATA_CLOCK
);
114 eeprom
->reg_chip_select
=
115 !!rt2x00_get_field32(reg
, E2PROM_CSR_CHIP_SELECT
);
118 static void rt2800pci_eepromregister_write(struct eeprom_93cx6
*eeprom
)
120 struct rt2x00_dev
*rt2x00dev
= eeprom
->data
;
123 rt2x00_set_field32(®
, E2PROM_CSR_DATA_IN
, !!eeprom
->reg_data_in
);
124 rt2x00_set_field32(®
, E2PROM_CSR_DATA_OUT
, !!eeprom
->reg_data_out
);
125 rt2x00_set_field32(®
, E2PROM_CSR_DATA_CLOCK
,
126 !!eeprom
->reg_data_clock
);
127 rt2x00_set_field32(®
, E2PROM_CSR_CHIP_SELECT
,
128 !!eeprom
->reg_chip_select
);
130 rt2x00pci_register_write(rt2x00dev
, E2PROM_CSR
, reg
);
133 static void rt2800pci_read_eeprom_pci(struct rt2x00_dev
*rt2x00dev
)
135 struct eeprom_93cx6 eeprom
;
138 rt2x00pci_register_read(rt2x00dev
, E2PROM_CSR
, ®
);
140 eeprom
.data
= rt2x00dev
;
141 eeprom
.register_read
= rt2800pci_eepromregister_read
;
142 eeprom
.register_write
= rt2800pci_eepromregister_write
;
143 switch (rt2x00_get_field32(reg
, E2PROM_CSR_TYPE
))
146 eeprom
.width
= PCI_EEPROM_WIDTH_93C46
;
149 eeprom
.width
= PCI_EEPROM_WIDTH_93C66
;
152 eeprom
.width
= PCI_EEPROM_WIDTH_93C86
;
155 eeprom
.reg_data_in
= 0;
156 eeprom
.reg_data_out
= 0;
157 eeprom
.reg_data_clock
= 0;
158 eeprom
.reg_chip_select
= 0;
160 eeprom_93cx6_multiread(&eeprom
, EEPROM_BASE
, rt2x00dev
->eeprom
,
161 EEPROM_SIZE
/ sizeof(u16
));
164 static int rt2800pci_efuse_detect(struct rt2x00_dev
*rt2x00dev
)
166 return rt2800_efuse_detect(rt2x00dev
);
169 static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev
*rt2x00dev
)
171 rt2800_read_eeprom_efuse(rt2x00dev
);
174 static inline void rt2800pci_read_eeprom_pci(struct rt2x00_dev
*rt2x00dev
)
178 static inline int rt2800pci_efuse_detect(struct rt2x00_dev
*rt2x00dev
)
183 static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev
*rt2x00dev
)
186 #endif /* CONFIG_PCI */
191 static void rt2800pci_start_queue(struct data_queue
*queue
)
193 struct rt2x00_dev
*rt2x00dev
= queue
->rt2x00dev
;
196 switch (queue
->qid
) {
198 rt2x00pci_register_read(rt2x00dev
, MAC_SYS_CTRL
, ®
);
199 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_RX
, 1);
200 rt2x00pci_register_write(rt2x00dev
, MAC_SYS_CTRL
, reg
);
203 rt2x00pci_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
204 rt2x00_set_field32(®
, BCN_TIME_CFG_TSF_TICKING
, 1);
205 rt2x00_set_field32(®
, BCN_TIME_CFG_TBTT_ENABLE
, 1);
206 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_GEN
, 1);
207 rt2x00pci_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
209 rt2x00pci_register_read(rt2x00dev
, INT_TIMER_EN
, ®
);
210 rt2x00_set_field32(®
, INT_TIMER_EN_PRE_TBTT_TIMER
, 1);
211 rt2x00pci_register_write(rt2x00dev
, INT_TIMER_EN
, reg
);
218 static void rt2800pci_kick_queue(struct data_queue
*queue
)
220 struct rt2x00_dev
*rt2x00dev
= queue
->rt2x00dev
;
221 struct queue_entry
*entry
;
223 switch (queue
->qid
) {
228 entry
= rt2x00queue_get_entry(queue
, Q_INDEX
);
229 rt2x00pci_register_write(rt2x00dev
, TX_CTX_IDX(queue
->qid
),
233 entry
= rt2x00queue_get_entry(queue
, Q_INDEX
);
234 rt2x00pci_register_write(rt2x00dev
, TX_CTX_IDX(5),
242 static void rt2800pci_stop_queue(struct data_queue
*queue
)
244 struct rt2x00_dev
*rt2x00dev
= queue
->rt2x00dev
;
247 switch (queue
->qid
) {
249 rt2x00pci_register_read(rt2x00dev
, MAC_SYS_CTRL
, ®
);
250 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_RX
, 0);
251 rt2x00pci_register_write(rt2x00dev
, MAC_SYS_CTRL
, reg
);
254 rt2x00pci_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
255 rt2x00_set_field32(®
, BCN_TIME_CFG_TSF_TICKING
, 0);
256 rt2x00_set_field32(®
, BCN_TIME_CFG_TBTT_ENABLE
, 0);
257 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_GEN
, 0);
258 rt2x00pci_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
260 rt2x00pci_register_read(rt2x00dev
, INT_TIMER_EN
, ®
);
261 rt2x00_set_field32(®
, INT_TIMER_EN_PRE_TBTT_TIMER
, 0);
262 rt2x00pci_register_write(rt2x00dev
, INT_TIMER_EN
, reg
);
265 * Wait for current invocation to finish. The tasklet
266 * won't be scheduled anymore afterwards since we disabled
267 * the TBTT and PRE TBTT timer.
269 tasklet_kill(&rt2x00dev
->tbtt_tasklet
);
270 tasklet_kill(&rt2x00dev
->pretbtt_tasklet
);
281 static char *rt2800pci_get_firmware_name(struct rt2x00_dev
*rt2x00dev
)
284 * Chip rt3290 use specific 4KB firmware named rt3290.bin.
286 if (rt2x00_rt(rt2x00dev
, RT3290
))
287 return FIRMWARE_RT3290
;
289 return FIRMWARE_RT2860
;
292 static int rt2800pci_write_firmware(struct rt2x00_dev
*rt2x00dev
,
293 const u8
*data
, const size_t len
)
298 * enable Host program ram write selection
301 rt2x00_set_field32(®
, PBF_SYS_CTRL_HOST_RAM_WRITE
, 1);
302 rt2x00pci_register_write(rt2x00dev
, PBF_SYS_CTRL
, reg
);
305 * Write firmware to device.
307 rt2x00pci_register_multiwrite(rt2x00dev
, FIRMWARE_IMAGE_BASE
,
310 rt2x00pci_register_write(rt2x00dev
, PBF_SYS_CTRL
, 0x00000);
311 rt2x00pci_register_write(rt2x00dev
, PBF_SYS_CTRL
, 0x00001);
313 rt2x00pci_register_write(rt2x00dev
, H2M_BBP_AGENT
, 0);
314 rt2x00pci_register_write(rt2x00dev
, H2M_MAILBOX_CSR
, 0);
320 * Initialization functions.
322 static bool rt2800pci_get_entry_state(struct queue_entry
*entry
)
324 struct queue_entry_priv_pci
*entry_priv
= entry
->priv_data
;
327 if (entry
->queue
->qid
== QID_RX
) {
328 rt2x00_desc_read(entry_priv
->desc
, 1, &word
);
330 return (!rt2x00_get_field32(word
, RXD_W1_DMA_DONE
));
332 rt2x00_desc_read(entry_priv
->desc
, 1, &word
);
334 return (!rt2x00_get_field32(word
, TXD_W1_DMA_DONE
));
338 static void rt2800pci_clear_entry(struct queue_entry
*entry
)
340 struct queue_entry_priv_pci
*entry_priv
= entry
->priv_data
;
341 struct skb_frame_desc
*skbdesc
= get_skb_frame_desc(entry
->skb
);
342 struct rt2x00_dev
*rt2x00dev
= entry
->queue
->rt2x00dev
;
345 if (entry
->queue
->qid
== QID_RX
) {
346 rt2x00_desc_read(entry_priv
->desc
, 0, &word
);
347 rt2x00_set_field32(&word
, RXD_W0_SDP0
, skbdesc
->skb_dma
);
348 rt2x00_desc_write(entry_priv
->desc
, 0, word
);
350 rt2x00_desc_read(entry_priv
->desc
, 1, &word
);
351 rt2x00_set_field32(&word
, RXD_W1_DMA_DONE
, 0);
352 rt2x00_desc_write(entry_priv
->desc
, 1, word
);
355 * Set RX IDX in register to inform hardware that we have
356 * handled this entry and it is available for reuse again.
358 rt2x00pci_register_write(rt2x00dev
, RX_CRX_IDX
,
361 rt2x00_desc_read(entry_priv
->desc
, 1, &word
);
362 rt2x00_set_field32(&word
, TXD_W1_DMA_DONE
, 1);
363 rt2x00_desc_write(entry_priv
->desc
, 1, word
);
367 static int rt2800pci_init_queues(struct rt2x00_dev
*rt2x00dev
)
369 struct queue_entry_priv_pci
*entry_priv
;
372 * Initialize registers.
374 entry_priv
= rt2x00dev
->tx
[0].entries
[0].priv_data
;
375 rt2x00pci_register_write(rt2x00dev
, TX_BASE_PTR0
, entry_priv
->desc_dma
);
376 rt2x00pci_register_write(rt2x00dev
, TX_MAX_CNT0
,
377 rt2x00dev
->tx
[0].limit
);
378 rt2x00pci_register_write(rt2x00dev
, TX_CTX_IDX0
, 0);
379 rt2x00pci_register_write(rt2x00dev
, TX_DTX_IDX0
, 0);
381 entry_priv
= rt2x00dev
->tx
[1].entries
[0].priv_data
;
382 rt2x00pci_register_write(rt2x00dev
, TX_BASE_PTR1
, entry_priv
->desc_dma
);
383 rt2x00pci_register_write(rt2x00dev
, TX_MAX_CNT1
,
384 rt2x00dev
->tx
[1].limit
);
385 rt2x00pci_register_write(rt2x00dev
, TX_CTX_IDX1
, 0);
386 rt2x00pci_register_write(rt2x00dev
, TX_DTX_IDX1
, 0);
388 entry_priv
= rt2x00dev
->tx
[2].entries
[0].priv_data
;
389 rt2x00pci_register_write(rt2x00dev
, TX_BASE_PTR2
, entry_priv
->desc_dma
);
390 rt2x00pci_register_write(rt2x00dev
, TX_MAX_CNT2
,
391 rt2x00dev
->tx
[2].limit
);
392 rt2x00pci_register_write(rt2x00dev
, TX_CTX_IDX2
, 0);
393 rt2x00pci_register_write(rt2x00dev
, TX_DTX_IDX2
, 0);
395 entry_priv
= rt2x00dev
->tx
[3].entries
[0].priv_data
;
396 rt2x00pci_register_write(rt2x00dev
, TX_BASE_PTR3
, entry_priv
->desc_dma
);
397 rt2x00pci_register_write(rt2x00dev
, TX_MAX_CNT3
,
398 rt2x00dev
->tx
[3].limit
);
399 rt2x00pci_register_write(rt2x00dev
, TX_CTX_IDX3
, 0);
400 rt2x00pci_register_write(rt2x00dev
, TX_DTX_IDX3
, 0);
402 rt2x00pci_register_write(rt2x00dev
, TX_BASE_PTR4
, 0);
403 rt2x00pci_register_write(rt2x00dev
, TX_MAX_CNT4
, 0);
404 rt2x00pci_register_write(rt2x00dev
, TX_CTX_IDX4
, 0);
405 rt2x00pci_register_write(rt2x00dev
, TX_DTX_IDX4
, 0);
407 rt2x00pci_register_write(rt2x00dev
, TX_BASE_PTR5
, 0);
408 rt2x00pci_register_write(rt2x00dev
, TX_MAX_CNT5
, 0);
409 rt2x00pci_register_write(rt2x00dev
, TX_CTX_IDX5
, 0);
410 rt2x00pci_register_write(rt2x00dev
, TX_DTX_IDX5
, 0);
412 entry_priv
= rt2x00dev
->rx
->entries
[0].priv_data
;
413 rt2x00pci_register_write(rt2x00dev
, RX_BASE_PTR
, entry_priv
->desc_dma
);
414 rt2x00pci_register_write(rt2x00dev
, RX_MAX_CNT
,
415 rt2x00dev
->rx
[0].limit
);
416 rt2x00pci_register_write(rt2x00dev
, RX_CRX_IDX
,
417 rt2x00dev
->rx
[0].limit
- 1);
418 rt2x00pci_register_write(rt2x00dev
, RX_DRX_IDX
, 0);
420 rt2800_disable_wpdma(rt2x00dev
);
422 rt2x00pci_register_write(rt2x00dev
, DELAY_INT_CFG
, 0);
428 * Device state switch handlers.
430 static void rt2800pci_toggle_irq(struct rt2x00_dev
*rt2x00dev
,
431 enum dev_state state
)
437 * When interrupts are being enabled, the interrupt registers
438 * should clear the register to assure a clean state.
440 if (state
== STATE_RADIO_IRQ_ON
) {
441 rt2x00pci_register_read(rt2x00dev
, INT_SOURCE_CSR
, ®
);
442 rt2x00pci_register_write(rt2x00dev
, INT_SOURCE_CSR
, reg
);
445 spin_lock_irqsave(&rt2x00dev
->irqmask_lock
, flags
);
447 if (state
== STATE_RADIO_IRQ_ON
) {
448 rt2x00_set_field32(®
, INT_MASK_CSR_RX_DONE
, 1);
449 rt2x00_set_field32(®
, INT_MASK_CSR_TBTT
, 1);
450 rt2x00_set_field32(®
, INT_MASK_CSR_PRE_TBTT
, 1);
451 rt2x00_set_field32(®
, INT_MASK_CSR_TX_FIFO_STATUS
, 1);
452 rt2x00_set_field32(®
, INT_MASK_CSR_AUTO_WAKEUP
, 1);
454 rt2x00pci_register_write(rt2x00dev
, INT_MASK_CSR
, reg
);
455 spin_unlock_irqrestore(&rt2x00dev
->irqmask_lock
, flags
);
457 if (state
== STATE_RADIO_IRQ_OFF
) {
459 * Wait for possibly running tasklets to finish.
461 tasklet_kill(&rt2x00dev
->txstatus_tasklet
);
462 tasklet_kill(&rt2x00dev
->rxdone_tasklet
);
463 tasklet_kill(&rt2x00dev
->autowake_tasklet
);
464 tasklet_kill(&rt2x00dev
->tbtt_tasklet
);
465 tasklet_kill(&rt2x00dev
->pretbtt_tasklet
);
469 static int rt2800pci_init_registers(struct rt2x00_dev
*rt2x00dev
)
476 rt2x00pci_register_read(rt2x00dev
, WPDMA_RST_IDX
, ®
);
477 rt2x00_set_field32(®
, WPDMA_RST_IDX_DTX_IDX0
, 1);
478 rt2x00_set_field32(®
, WPDMA_RST_IDX_DTX_IDX1
, 1);
479 rt2x00_set_field32(®
, WPDMA_RST_IDX_DTX_IDX2
, 1);
480 rt2x00_set_field32(®
, WPDMA_RST_IDX_DTX_IDX3
, 1);
481 rt2x00_set_field32(®
, WPDMA_RST_IDX_DTX_IDX4
, 1);
482 rt2x00_set_field32(®
, WPDMA_RST_IDX_DTX_IDX5
, 1);
483 rt2x00_set_field32(®
, WPDMA_RST_IDX_DRX_IDX0
, 1);
484 rt2x00pci_register_write(rt2x00dev
, WPDMA_RST_IDX
, reg
);
486 rt2x00pci_register_write(rt2x00dev
, PBF_SYS_CTRL
, 0x00000e1f);
487 rt2x00pci_register_write(rt2x00dev
, PBF_SYS_CTRL
, 0x00000e00);
489 if (rt2x00_is_pcie(rt2x00dev
) &&
490 (rt2x00_rt(rt2x00dev
, RT3572
) ||
491 rt2x00_rt(rt2x00dev
, RT5390
) ||
492 rt2x00_rt(rt2x00dev
, RT5392
))) {
493 rt2x00pci_register_read(rt2x00dev
, AUX_CTRL
, ®
);
494 rt2x00_set_field32(®
, AUX_CTRL_FORCE_PCIE_CLK
, 1);
495 rt2x00_set_field32(®
, AUX_CTRL_WAKE_PCIE_EN
, 1);
496 rt2x00pci_register_write(rt2x00dev
, AUX_CTRL
, reg
);
499 rt2x00pci_register_write(rt2x00dev
, PWR_PIN_CFG
, 0x00000003);
502 rt2x00_set_field32(®
, MAC_SYS_CTRL_RESET_CSR
, 1);
503 rt2x00_set_field32(®
, MAC_SYS_CTRL_RESET_BBP
, 1);
504 rt2x00pci_register_write(rt2x00dev
, MAC_SYS_CTRL
, reg
);
506 rt2x00pci_register_write(rt2x00dev
, MAC_SYS_CTRL
, 0x00000000);
511 static int rt2800pci_enable_radio(struct rt2x00_dev
*rt2x00dev
)
515 /* Wait for DMA, ignore error until we initialize queues. */
516 rt2800_wait_wpdma_ready(rt2x00dev
);
518 if (unlikely(rt2800pci_init_queues(rt2x00dev
)))
521 retval
= rt2800_enable_radio(rt2x00dev
);
525 /* After resume MCU_BOOT_SIGNAL will trash these. */
526 rt2x00pci_register_write(rt2x00dev
, H2M_MAILBOX_STATUS
, ~0);
527 rt2x00pci_register_write(rt2x00dev
, H2M_MAILBOX_CID
, ~0);
529 rt2800_mcu_request(rt2x00dev
, MCU_SLEEP
, TOKEN_RADIO_OFF
, 0xff, 0x02);
530 rt2800pci_mcu_status(rt2x00dev
, TOKEN_RADIO_OFF
);
532 rt2800_mcu_request(rt2x00dev
, MCU_WAKEUP
, TOKEN_WAKEUP
, 0, 0);
533 rt2800pci_mcu_status(rt2x00dev
, TOKEN_WAKEUP
);
538 static void rt2800pci_disable_radio(struct rt2x00_dev
*rt2x00dev
)
540 if (rt2x00_is_soc(rt2x00dev
)) {
541 rt2800_disable_radio(rt2x00dev
);
542 rt2x00pci_register_write(rt2x00dev
, PWR_PIN_CFG
, 0);
543 rt2x00pci_register_write(rt2x00dev
, TX_PIN_CFG
, 0);
547 static int rt2800pci_set_state(struct rt2x00_dev
*rt2x00dev
,
548 enum dev_state state
)
550 if (state
== STATE_AWAKE
) {
551 rt2800_mcu_request(rt2x00dev
, MCU_WAKEUP
, TOKEN_WAKEUP
,
553 rt2800pci_mcu_status(rt2x00dev
, TOKEN_WAKEUP
);
554 } else if (state
== STATE_SLEEP
) {
555 rt2x00pci_register_write(rt2x00dev
, H2M_MAILBOX_STATUS
,
557 rt2x00pci_register_write(rt2x00dev
, H2M_MAILBOX_CID
,
559 rt2800_mcu_request(rt2x00dev
, MCU_SLEEP
, TOKEN_SLEEP
,
566 static int rt2800pci_set_device_state(struct rt2x00_dev
*rt2x00dev
,
567 enum dev_state state
)
573 retval
= rt2800pci_enable_radio(rt2x00dev
);
575 case STATE_RADIO_OFF
:
577 * After the radio has been disabled, the device should
578 * be put to sleep for powersaving.
580 rt2800pci_disable_radio(rt2x00dev
);
581 rt2800pci_set_state(rt2x00dev
, STATE_SLEEP
);
583 case STATE_RADIO_IRQ_ON
:
584 case STATE_RADIO_IRQ_OFF
:
585 rt2800pci_toggle_irq(rt2x00dev
, state
);
587 case STATE_DEEP_SLEEP
:
591 retval
= rt2800pci_set_state(rt2x00dev
, state
);
598 if (unlikely(retval
))
599 ERROR(rt2x00dev
, "Device failed to enter state %d (%d).\n",
606 * TX descriptor initialization
608 static __le32
*rt2800pci_get_txwi(struct queue_entry
*entry
)
610 return (__le32
*) entry
->skb
->data
;
613 static void rt2800pci_write_tx_desc(struct queue_entry
*entry
,
614 struct txentry_desc
*txdesc
)
616 struct skb_frame_desc
*skbdesc
= get_skb_frame_desc(entry
->skb
);
617 struct queue_entry_priv_pci
*entry_priv
= entry
->priv_data
;
618 __le32
*txd
= entry_priv
->desc
;
622 * The buffers pointed by SD_PTR0/SD_LEN0 and SD_PTR1/SD_LEN1
623 * must contains a TXWI structure + 802.11 header + padding + 802.11
624 * data. We choose to have SD_PTR0/SD_LEN0 only contains TXWI and
625 * SD_PTR1/SD_LEN1 contains 802.11 header + padding + 802.11
626 * data. It means that LAST_SEC0 is always 0.
630 * Initialize TX descriptor
633 rt2x00_set_field32(&word
, TXD_W0_SD_PTR0
, skbdesc
->skb_dma
);
634 rt2x00_desc_write(txd
, 0, word
);
637 rt2x00_set_field32(&word
, TXD_W1_SD_LEN1
, entry
->skb
->len
);
638 rt2x00_set_field32(&word
, TXD_W1_LAST_SEC1
,
639 !test_bit(ENTRY_TXD_MORE_FRAG
, &txdesc
->flags
));
640 rt2x00_set_field32(&word
, TXD_W1_BURST
,
641 test_bit(ENTRY_TXD_BURST
, &txdesc
->flags
));
642 rt2x00_set_field32(&word
, TXD_W1_SD_LEN0
, TXWI_DESC_SIZE
);
643 rt2x00_set_field32(&word
, TXD_W1_LAST_SEC0
, 0);
644 rt2x00_set_field32(&word
, TXD_W1_DMA_DONE
, 0);
645 rt2x00_desc_write(txd
, 1, word
);
648 rt2x00_set_field32(&word
, TXD_W2_SD_PTR1
,
649 skbdesc
->skb_dma
+ TXWI_DESC_SIZE
);
650 rt2x00_desc_write(txd
, 2, word
);
653 rt2x00_set_field32(&word
, TXD_W3_WIV
,
654 !test_bit(ENTRY_TXD_ENCRYPT_IV
, &txdesc
->flags
));
655 rt2x00_set_field32(&word
, TXD_W3_QSEL
, 2);
656 rt2x00_desc_write(txd
, 3, word
);
659 * Register descriptor details in skb frame descriptor.
662 skbdesc
->desc_len
= TXD_DESC_SIZE
;
666 * RX control handlers
668 static void rt2800pci_fill_rxdone(struct queue_entry
*entry
,
669 struct rxdone_entry_desc
*rxdesc
)
671 struct queue_entry_priv_pci
*entry_priv
= entry
->priv_data
;
672 __le32
*rxd
= entry_priv
->desc
;
675 rt2x00_desc_read(rxd
, 3, &word
);
677 if (rt2x00_get_field32(word
, RXD_W3_CRC_ERROR
))
678 rxdesc
->flags
|= RX_FLAG_FAILED_FCS_CRC
;
681 * Unfortunately we don't know the cipher type used during
682 * decryption. This prevents us from correct providing
683 * correct statistics through debugfs.
685 rxdesc
->cipher_status
= rt2x00_get_field32(word
, RXD_W3_CIPHER_ERROR
);
687 if (rt2x00_get_field32(word
, RXD_W3_DECRYPTED
)) {
689 * Hardware has stripped IV/EIV data from 802.11 frame during
690 * decryption. Unfortunately the descriptor doesn't contain
691 * any fields with the EIV/IV data either, so they can't
692 * be restored by rt2x00lib.
694 rxdesc
->flags
|= RX_FLAG_IV_STRIPPED
;
697 * The hardware has already checked the Michael Mic and has
698 * stripped it from the frame. Signal this to mac80211.
700 rxdesc
->flags
|= RX_FLAG_MMIC_STRIPPED
;
702 if (rxdesc
->cipher_status
== RX_CRYPTO_SUCCESS
)
703 rxdesc
->flags
|= RX_FLAG_DECRYPTED
;
704 else if (rxdesc
->cipher_status
== RX_CRYPTO_FAIL_MIC
)
705 rxdesc
->flags
|= RX_FLAG_MMIC_ERROR
;
708 if (rt2x00_get_field32(word
, RXD_W3_MY_BSS
))
709 rxdesc
->dev_flags
|= RXDONE_MY_BSS
;
711 if (rt2x00_get_field32(word
, RXD_W3_L2PAD
))
712 rxdesc
->dev_flags
|= RXDONE_L2PAD
;
715 * Process the RXWI structure that is at the start of the buffer.
717 rt2800_process_rxwi(entry
, rxdesc
);
721 * Interrupt functions.
723 static void rt2800pci_wakeup(struct rt2x00_dev
*rt2x00dev
)
725 struct ieee80211_conf conf
= { .flags
= 0 };
726 struct rt2x00lib_conf libconf
= { .conf
= &conf
};
728 rt2800_config(rt2x00dev
, &libconf
, IEEE80211_CONF_CHANGE_PS
);
731 static bool rt2800pci_txdone(struct rt2x00_dev
*rt2x00dev
)
733 struct data_queue
*queue
;
734 struct queue_entry
*entry
;
737 int max_tx_done
= 16;
739 while (kfifo_get(&rt2x00dev
->txstatus_fifo
, &status
)) {
740 qid
= rt2x00_get_field32(status
, TX_STA_FIFO_PID_QUEUE
);
741 if (unlikely(qid
>= QID_RX
)) {
743 * Unknown queue, this shouldn't happen. Just drop
746 WARNING(rt2x00dev
, "Got TX status report with "
747 "unexpected pid %u, dropping\n", qid
);
751 queue
= rt2x00queue_get_tx_queue(rt2x00dev
, qid
);
752 if (unlikely(queue
== NULL
)) {
754 * The queue is NULL, this shouldn't happen. Stop
755 * processing here and drop the tx status
757 WARNING(rt2x00dev
, "Got TX status for an unavailable "
758 "queue %u, dropping\n", qid
);
762 if (unlikely(rt2x00queue_empty(queue
))) {
764 * The queue is empty. Stop processing here
765 * and drop the tx status.
767 WARNING(rt2x00dev
, "Got TX status for an empty "
768 "queue %u, dropping\n", qid
);
772 entry
= rt2x00queue_get_entry(queue
, Q_INDEX_DONE
);
773 rt2800_txdone_entry(entry
, status
, rt2800pci_get_txwi(entry
));
775 if (--max_tx_done
== 0)
782 static inline void rt2800pci_enable_interrupt(struct rt2x00_dev
*rt2x00dev
,
783 struct rt2x00_field32 irq_field
)
788 * Enable a single interrupt. The interrupt mask register
789 * access needs locking.
791 spin_lock_irq(&rt2x00dev
->irqmask_lock
);
792 rt2x00pci_register_read(rt2x00dev
, INT_MASK_CSR
, ®
);
793 rt2x00_set_field32(®
, irq_field
, 1);
794 rt2x00pci_register_write(rt2x00dev
, INT_MASK_CSR
, reg
);
795 spin_unlock_irq(&rt2x00dev
->irqmask_lock
);
798 static void rt2800pci_txstatus_tasklet(unsigned long data
)
800 struct rt2x00_dev
*rt2x00dev
= (struct rt2x00_dev
*)data
;
801 if (rt2800pci_txdone(rt2x00dev
))
802 tasklet_schedule(&rt2x00dev
->txstatus_tasklet
);
805 * No need to enable the tx status interrupt here as we always
806 * leave it enabled to minimize the possibility of a tx status
807 * register overflow. See comment in interrupt handler.
811 static void rt2800pci_pretbtt_tasklet(unsigned long data
)
813 struct rt2x00_dev
*rt2x00dev
= (struct rt2x00_dev
*)data
;
814 rt2x00lib_pretbtt(rt2x00dev
);
815 if (test_bit(DEVICE_STATE_ENABLED_RADIO
, &rt2x00dev
->flags
))
816 rt2800pci_enable_interrupt(rt2x00dev
, INT_MASK_CSR_PRE_TBTT
);
819 static void rt2800pci_tbtt_tasklet(unsigned long data
)
821 struct rt2x00_dev
*rt2x00dev
= (struct rt2x00_dev
*)data
;
822 struct rt2800_drv_data
*drv_data
= rt2x00dev
->drv_data
;
825 rt2x00lib_beacondone(rt2x00dev
);
827 if (rt2x00dev
->intf_ap_count
) {
829 * The rt2800pci hardware tbtt timer is off by 1us per tbtt
830 * causing beacon skew and as a result causing problems with
831 * some powersaving clients over time. Shorten the beacon
832 * interval every 64 beacons by 64us to mitigate this effect.
834 if (drv_data
->tbtt_tick
== (BCN_TBTT_OFFSET
- 2)) {
835 rt2x00pci_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
836 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_INTERVAL
,
837 (rt2x00dev
->beacon_int
* 16) - 1);
838 rt2x00pci_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
839 } else if (drv_data
->tbtt_tick
== (BCN_TBTT_OFFSET
- 1)) {
840 rt2x00pci_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
841 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_INTERVAL
,
842 (rt2x00dev
->beacon_int
* 16));
843 rt2x00pci_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
845 drv_data
->tbtt_tick
++;
846 drv_data
->tbtt_tick
%= BCN_TBTT_OFFSET
;
849 if (test_bit(DEVICE_STATE_ENABLED_RADIO
, &rt2x00dev
->flags
))
850 rt2800pci_enable_interrupt(rt2x00dev
, INT_MASK_CSR_TBTT
);
853 static void rt2800pci_rxdone_tasklet(unsigned long data
)
855 struct rt2x00_dev
*rt2x00dev
= (struct rt2x00_dev
*)data
;
856 if (rt2x00pci_rxdone(rt2x00dev
))
857 tasklet_schedule(&rt2x00dev
->rxdone_tasklet
);
858 else if (test_bit(DEVICE_STATE_ENABLED_RADIO
, &rt2x00dev
->flags
))
859 rt2800pci_enable_interrupt(rt2x00dev
, INT_MASK_CSR_RX_DONE
);
862 static void rt2800pci_autowake_tasklet(unsigned long data
)
864 struct rt2x00_dev
*rt2x00dev
= (struct rt2x00_dev
*)data
;
865 rt2800pci_wakeup(rt2x00dev
);
866 if (test_bit(DEVICE_STATE_ENABLED_RADIO
, &rt2x00dev
->flags
))
867 rt2800pci_enable_interrupt(rt2x00dev
, INT_MASK_CSR_AUTO_WAKEUP
);
870 static void rt2800pci_txstatus_interrupt(struct rt2x00_dev
*rt2x00dev
)
876 * The TX_FIFO_STATUS interrupt needs special care. We should
877 * read TX_STA_FIFO but we should do it immediately as otherwise
878 * the register can overflow and we would lose status reports.
880 * Hence, read the TX_STA_FIFO register and copy all tx status
881 * reports into a kernel FIFO which is handled in the txstatus
882 * tasklet. We use a tasklet to process the tx status reports
883 * because we can schedule the tasklet multiple times (when the
884 * interrupt fires again during tx status processing).
886 * Furthermore we don't disable the TX_FIFO_STATUS
887 * interrupt here but leave it enabled so that the TX_STA_FIFO
888 * can also be read while the tx status tasklet gets executed.
890 * Since we have only one producer and one consumer we don't
891 * need to lock the kfifo.
893 for (i
= 0; i
< rt2x00dev
->ops
->tx
->entry_num
; i
++) {
894 rt2x00pci_register_read(rt2x00dev
, TX_STA_FIFO
, &status
);
896 if (!rt2x00_get_field32(status
, TX_STA_FIFO_VALID
))
899 if (!kfifo_put(&rt2x00dev
->txstatus_fifo
, &status
)) {
900 WARNING(rt2x00dev
, "TX status FIFO overrun,"
901 "drop tx status report.\n");
906 /* Schedule the tasklet for processing the tx status. */
907 tasklet_schedule(&rt2x00dev
->txstatus_tasklet
);
910 static irqreturn_t
rt2800pci_interrupt(int irq
, void *dev_instance
)
912 struct rt2x00_dev
*rt2x00dev
= dev_instance
;
915 /* Read status and ACK all interrupts */
916 rt2x00pci_register_read(rt2x00dev
, INT_SOURCE_CSR
, ®
);
917 rt2x00pci_register_write(rt2x00dev
, INT_SOURCE_CSR
, reg
);
922 if (!test_bit(DEVICE_STATE_ENABLED_RADIO
, &rt2x00dev
->flags
))
926 * Since INT_MASK_CSR and INT_SOURCE_CSR use the same bits
927 * for interrupts and interrupt masks we can just use the value of
928 * INT_SOURCE_CSR to create the interrupt mask.
932 if (rt2x00_get_field32(reg
, INT_SOURCE_CSR_TX_FIFO_STATUS
)) {
933 rt2800pci_txstatus_interrupt(rt2x00dev
);
935 * Never disable the TX_FIFO_STATUS interrupt.
937 rt2x00_set_field32(&mask
, INT_MASK_CSR_TX_FIFO_STATUS
, 1);
940 if (rt2x00_get_field32(reg
, INT_SOURCE_CSR_PRE_TBTT
))
941 tasklet_hi_schedule(&rt2x00dev
->pretbtt_tasklet
);
943 if (rt2x00_get_field32(reg
, INT_SOURCE_CSR_TBTT
))
944 tasklet_hi_schedule(&rt2x00dev
->tbtt_tasklet
);
946 if (rt2x00_get_field32(reg
, INT_SOURCE_CSR_RX_DONE
))
947 tasklet_schedule(&rt2x00dev
->rxdone_tasklet
);
949 if (rt2x00_get_field32(reg
, INT_SOURCE_CSR_AUTO_WAKEUP
))
950 tasklet_schedule(&rt2x00dev
->autowake_tasklet
);
953 * Disable all interrupts for which a tasklet was scheduled right now,
954 * the tasklet will reenable the appropriate interrupts.
956 spin_lock(&rt2x00dev
->irqmask_lock
);
957 rt2x00pci_register_read(rt2x00dev
, INT_MASK_CSR
, ®
);
959 rt2x00pci_register_write(rt2x00dev
, INT_MASK_CSR
, reg
);
960 spin_unlock(&rt2x00dev
->irqmask_lock
);
966 * Device probe functions.
968 static int rt2800pci_validate_eeprom(struct rt2x00_dev
*rt2x00dev
)
971 * Read EEPROM into buffer
973 if (rt2x00_is_soc(rt2x00dev
))
974 rt2800pci_read_eeprom_soc(rt2x00dev
);
975 else if (rt2800pci_efuse_detect(rt2x00dev
))
976 rt2800pci_read_eeprom_efuse(rt2x00dev
);
978 rt2800pci_read_eeprom_pci(rt2x00dev
);
980 return rt2800_validate_eeprom(rt2x00dev
);
983 static int rt2800pci_probe_hw(struct rt2x00_dev
*rt2x00dev
)
989 * Allocate eeprom data.
991 retval
= rt2800pci_validate_eeprom(rt2x00dev
);
995 retval
= rt2800_init_eeprom(rt2x00dev
);
1000 * Enable rfkill polling by setting GPIO direction of the
1001 * rfkill switch GPIO pin correctly.
1003 rt2x00pci_register_read(rt2x00dev
, GPIO_CTRL_CFG
, ®
);
1004 rt2x00_set_field32(®
, GPIO_CTRL_CFG_GPIOD_BIT2
, 1);
1005 rt2x00pci_register_write(rt2x00dev
, GPIO_CTRL_CFG
, reg
);
1008 * Initialize hw specifications.
1010 retval
= rt2800_probe_hw_mode(rt2x00dev
);
1015 * This device has multiple filters for control frames
1016 * and has a separate filter for PS Poll frames.
1018 __set_bit(CAPABILITY_CONTROL_FILTERS
, &rt2x00dev
->cap_flags
);
1019 __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL
, &rt2x00dev
->cap_flags
);
1022 * This device has a pre tbtt interrupt and thus fetches
1023 * a new beacon directly prior to transmission.
1025 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT
, &rt2x00dev
->cap_flags
);
1028 * This device requires firmware.
1030 if (!rt2x00_is_soc(rt2x00dev
))
1031 __set_bit(REQUIRE_FIRMWARE
, &rt2x00dev
->cap_flags
);
1032 __set_bit(REQUIRE_DMA
, &rt2x00dev
->cap_flags
);
1033 __set_bit(REQUIRE_L2PAD
, &rt2x00dev
->cap_flags
);
1034 __set_bit(REQUIRE_TXSTATUS_FIFO
, &rt2x00dev
->cap_flags
);
1035 __set_bit(REQUIRE_TASKLET_CONTEXT
, &rt2x00dev
->cap_flags
);
1036 if (!modparam_nohwcrypt
)
1037 __set_bit(CAPABILITY_HW_CRYPTO
, &rt2x00dev
->cap_flags
);
1038 __set_bit(CAPABILITY_LINK_TUNING
, &rt2x00dev
->cap_flags
);
1039 __set_bit(REQUIRE_HT_TX_DESC
, &rt2x00dev
->cap_flags
);
1042 * Set the rssi offset.
1044 rt2x00dev
->rssi_offset
= DEFAULT_RSSI_OFFSET
;
1049 static const struct ieee80211_ops rt2800pci_mac80211_ops
= {
1051 .start
= rt2x00mac_start
,
1052 .stop
= rt2x00mac_stop
,
1053 .add_interface
= rt2x00mac_add_interface
,
1054 .remove_interface
= rt2x00mac_remove_interface
,
1055 .config
= rt2x00mac_config
,
1056 .configure_filter
= rt2x00mac_configure_filter
,
1057 .set_key
= rt2x00mac_set_key
,
1058 .sw_scan_start
= rt2x00mac_sw_scan_start
,
1059 .sw_scan_complete
= rt2x00mac_sw_scan_complete
,
1060 .get_stats
= rt2x00mac_get_stats
,
1061 .get_tkip_seq
= rt2800_get_tkip_seq
,
1062 .set_rts_threshold
= rt2800_set_rts_threshold
,
1063 .sta_add
= rt2x00mac_sta_add
,
1064 .sta_remove
= rt2x00mac_sta_remove
,
1065 .bss_info_changed
= rt2x00mac_bss_info_changed
,
1066 .conf_tx
= rt2800_conf_tx
,
1067 .get_tsf
= rt2800_get_tsf
,
1068 .rfkill_poll
= rt2x00mac_rfkill_poll
,
1069 .ampdu_action
= rt2800_ampdu_action
,
1070 .flush
= rt2x00mac_flush
,
1071 .get_survey
= rt2800_get_survey
,
1072 .get_ringparam
= rt2x00mac_get_ringparam
,
1073 .tx_frames_pending
= rt2x00mac_tx_frames_pending
,
1076 static const struct rt2800_ops rt2800pci_rt2800_ops
= {
1077 .register_read
= rt2x00pci_register_read
,
1078 .register_read_lock
= rt2x00pci_register_read
, /* same for PCI */
1079 .register_write
= rt2x00pci_register_write
,
1080 .register_write_lock
= rt2x00pci_register_write
, /* same for PCI */
1081 .register_multiread
= rt2x00pci_register_multiread
,
1082 .register_multiwrite
= rt2x00pci_register_multiwrite
,
1083 .regbusy_read
= rt2x00pci_regbusy_read
,
1084 .drv_write_firmware
= rt2800pci_write_firmware
,
1085 .drv_init_registers
= rt2800pci_init_registers
,
1086 .drv_get_txwi
= rt2800pci_get_txwi
,
1089 static const struct rt2x00lib_ops rt2800pci_rt2x00_ops
= {
1090 .irq_handler
= rt2800pci_interrupt
,
1091 .txstatus_tasklet
= rt2800pci_txstatus_tasklet
,
1092 .pretbtt_tasklet
= rt2800pci_pretbtt_tasklet
,
1093 .tbtt_tasklet
= rt2800pci_tbtt_tasklet
,
1094 .rxdone_tasklet
= rt2800pci_rxdone_tasklet
,
1095 .autowake_tasklet
= rt2800pci_autowake_tasklet
,
1096 .probe_hw
= rt2800pci_probe_hw
,
1097 .get_firmware_name
= rt2800pci_get_firmware_name
,
1098 .check_firmware
= rt2800_check_firmware
,
1099 .load_firmware
= rt2800_load_firmware
,
1100 .initialize
= rt2x00pci_initialize
,
1101 .uninitialize
= rt2x00pci_uninitialize
,
1102 .get_entry_state
= rt2800pci_get_entry_state
,
1103 .clear_entry
= rt2800pci_clear_entry
,
1104 .set_device_state
= rt2800pci_set_device_state
,
1105 .rfkill_poll
= rt2800_rfkill_poll
,
1106 .link_stats
= rt2800_link_stats
,
1107 .reset_tuner
= rt2800_reset_tuner
,
1108 .link_tuner
= rt2800_link_tuner
,
1109 .gain_calibration
= rt2800_gain_calibration
,
1110 .vco_calibration
= rt2800_vco_calibration
,
1111 .start_queue
= rt2800pci_start_queue
,
1112 .kick_queue
= rt2800pci_kick_queue
,
1113 .stop_queue
= rt2800pci_stop_queue
,
1114 .flush_queue
= rt2x00pci_flush_queue
,
1115 .write_tx_desc
= rt2800pci_write_tx_desc
,
1116 .write_tx_data
= rt2800_write_tx_data
,
1117 .write_beacon
= rt2800_write_beacon
,
1118 .clear_beacon
= rt2800_clear_beacon
,
1119 .fill_rxdone
= rt2800pci_fill_rxdone
,
1120 .config_shared_key
= rt2800_config_shared_key
,
1121 .config_pairwise_key
= rt2800_config_pairwise_key
,
1122 .config_filter
= rt2800_config_filter
,
1123 .config_intf
= rt2800_config_intf
,
1124 .config_erp
= rt2800_config_erp
,
1125 .config_ant
= rt2800_config_ant
,
1126 .config
= rt2800_config
,
1127 .sta_add
= rt2800_sta_add
,
1128 .sta_remove
= rt2800_sta_remove
,
1131 static const struct data_queue_desc rt2800pci_queue_rx
= {
1133 .data_size
= AGGREGATION_SIZE
,
1134 .desc_size
= RXD_DESC_SIZE
,
1135 .priv_size
= sizeof(struct queue_entry_priv_pci
),
1138 static const struct data_queue_desc rt2800pci_queue_tx
= {
1140 .data_size
= AGGREGATION_SIZE
,
1141 .desc_size
= TXD_DESC_SIZE
,
1142 .priv_size
= sizeof(struct queue_entry_priv_pci
),
1145 static const struct data_queue_desc rt2800pci_queue_bcn
= {
1147 .data_size
= 0, /* No DMA required for beacons */
1148 .desc_size
= TXWI_DESC_SIZE
,
1149 .priv_size
= sizeof(struct queue_entry_priv_pci
),
1152 static const struct rt2x00_ops rt2800pci_ops
= {
1153 .name
= KBUILD_MODNAME
,
1154 .drv_data_size
= sizeof(struct rt2800_drv_data
),
1157 .eeprom_size
= EEPROM_SIZE
,
1159 .tx_queues
= NUM_TX_QUEUES
,
1160 .extra_tx_headroom
= TXWI_DESC_SIZE
,
1161 .rx
= &rt2800pci_queue_rx
,
1162 .tx
= &rt2800pci_queue_tx
,
1163 .bcn
= &rt2800pci_queue_bcn
,
1164 .lib
= &rt2800pci_rt2x00_ops
,
1165 .drv
= &rt2800pci_rt2800_ops
,
1166 .hw
= &rt2800pci_mac80211_ops
,
1167 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1168 .debugfs
= &rt2800_rt2x00debug
,
1169 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1173 * RT2800pci module information.
1176 static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table
) = {
1177 { PCI_DEVICE(0x1814, 0x0601) },
1178 { PCI_DEVICE(0x1814, 0x0681) },
1179 { PCI_DEVICE(0x1814, 0x0701) },
1180 { PCI_DEVICE(0x1814, 0x0781) },
1181 { PCI_DEVICE(0x1814, 0x3090) },
1182 { PCI_DEVICE(0x1814, 0x3091) },
1183 { PCI_DEVICE(0x1814, 0x3092) },
1184 { PCI_DEVICE(0x1432, 0x7708) },
1185 { PCI_DEVICE(0x1432, 0x7727) },
1186 { PCI_DEVICE(0x1432, 0x7728) },
1187 { PCI_DEVICE(0x1432, 0x7738) },
1188 { PCI_DEVICE(0x1432, 0x7748) },
1189 { PCI_DEVICE(0x1432, 0x7758) },
1190 { PCI_DEVICE(0x1432, 0x7768) },
1191 { PCI_DEVICE(0x1462, 0x891a) },
1192 { PCI_DEVICE(0x1a3b, 0x1059) },
1193 #ifdef CONFIG_RT2800PCI_RT3290
1194 { PCI_DEVICE(0x1814, 0x3290) },
1196 #ifdef CONFIG_RT2800PCI_RT33XX
1197 { PCI_DEVICE(0x1814, 0x3390) },
1199 #ifdef CONFIG_RT2800PCI_RT35XX
1200 { PCI_DEVICE(0x1432, 0x7711) },
1201 { PCI_DEVICE(0x1432, 0x7722) },
1202 { PCI_DEVICE(0x1814, 0x3060) },
1203 { PCI_DEVICE(0x1814, 0x3062) },
1204 { PCI_DEVICE(0x1814, 0x3562) },
1205 { PCI_DEVICE(0x1814, 0x3592) },
1206 { PCI_DEVICE(0x1814, 0x3593) },
1208 #ifdef CONFIG_RT2800PCI_RT53XX
1209 { PCI_DEVICE(0x1814, 0x5360) },
1210 { PCI_DEVICE(0x1814, 0x5362) },
1211 { PCI_DEVICE(0x1814, 0x5390) },
1212 { PCI_DEVICE(0x1814, 0x5392) },
1213 { PCI_DEVICE(0x1814, 0x539a) },
1214 { PCI_DEVICE(0x1814, 0x539b) },
1215 { PCI_DEVICE(0x1814, 0x539f) },
1219 #endif /* CONFIG_PCI */
1221 MODULE_AUTHOR(DRV_PROJECT
);
1222 MODULE_VERSION(DRV_VERSION
);
1223 MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
1224 MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
1226 MODULE_FIRMWARE(FIRMWARE_RT2860
);
1227 MODULE_DEVICE_TABLE(pci
, rt2800pci_device_table
);
1228 #endif /* CONFIG_PCI */
1229 MODULE_LICENSE("GPL");
1231 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
1232 static int rt2800soc_probe(struct platform_device
*pdev
)
1234 return rt2x00soc_probe(pdev
, &rt2800pci_ops
);
1237 static struct platform_driver rt2800soc_driver
= {
1239 .name
= "rt2800_wmac",
1240 .owner
= THIS_MODULE
,
1241 .mod_name
= KBUILD_MODNAME
,
1243 .probe
= rt2800soc_probe
,
1244 .remove
= __devexit_p(rt2x00soc_remove
),
1245 .suspend
= rt2x00soc_suspend
,
1246 .resume
= rt2x00soc_resume
,
1248 #endif /* CONFIG_RALINK_RT288X || CONFIG_RALINK_RT305X */
1251 static int rt2800pci_probe(struct pci_dev
*pci_dev
,
1252 const struct pci_device_id
*id
)
1254 return rt2x00pci_probe(pci_dev
, &rt2800pci_ops
);
1257 static struct pci_driver rt2800pci_driver
= {
1258 .name
= KBUILD_MODNAME
,
1259 .id_table
= rt2800pci_device_table
,
1260 .probe
= rt2800pci_probe
,
1261 .remove
= __devexit_p(rt2x00pci_remove
),
1262 .suspend
= rt2x00pci_suspend
,
1263 .resume
= rt2x00pci_resume
,
1265 #endif /* CONFIG_PCI */
1267 static int __init
rt2800pci_init(void)
1271 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
1272 ret
= platform_driver_register(&rt2800soc_driver
);
1277 ret
= pci_register_driver(&rt2800pci_driver
);
1279 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
1280 platform_driver_unregister(&rt2800soc_driver
);
1289 static void __exit
rt2800pci_exit(void)
1292 pci_unregister_driver(&rt2800pci_driver
);
1294 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
1295 platform_driver_unregister(&rt2800soc_driver
);
1299 module_init(rt2800pci_init
);
1300 module_exit(rt2800pci_exit
);