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rt2x00: Add module parameter to disable HW crypto
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt61pci.c
1 /*
2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21 /*
22 Module: rt61pci
23 Abstract: rt61pci device specific routines.
24 Supported chipsets: RT2561, RT2561s, RT2661.
25 */
26
27 #include <linux/crc-itu-t.h>
28 #include <linux/delay.h>
29 #include <linux/etherdevice.h>
30 #include <linux/init.h>
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/pci.h>
34 #include <linux/eeprom_93cx6.h>
35
36 #include "rt2x00.h"
37 #include "rt2x00pci.h"
38 #include "rt61pci.h"
39
40 /*
41 * Allow hardware encryption to be disabled.
42 */
43 static int modparam_nohwcrypt = 0;
44 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
45 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
46
47 /*
48 * Register access.
49 * BBP and RF register require indirect register access,
50 * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
51 * These indirect registers work with busy bits,
52 * and we will try maximal REGISTER_BUSY_COUNT times to access
53 * the register while taking a REGISTER_BUSY_DELAY us delay
54 * between each attampt. When the busy bit is still set at that time,
55 * the access attempt is considered to have failed,
56 * and we will print an error.
57 */
58 static u32 rt61pci_bbp_check(struct rt2x00_dev *rt2x00dev)
59 {
60 u32 reg;
61 unsigned int i;
62
63 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
64 rt2x00pci_register_read(rt2x00dev, PHY_CSR3, &reg);
65 if (!rt2x00_get_field32(reg, PHY_CSR3_BUSY))
66 break;
67 udelay(REGISTER_BUSY_DELAY);
68 }
69
70 return reg;
71 }
72
73 static void rt61pci_bbp_write(struct rt2x00_dev *rt2x00dev,
74 const unsigned int word, const u8 value)
75 {
76 u32 reg;
77
78 /*
79 * Wait until the BBP becomes ready.
80 */
81 reg = rt61pci_bbp_check(rt2x00dev);
82 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
83 ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n");
84 return;
85 }
86
87 /*
88 * Write the data into the BBP.
89 */
90 reg = 0;
91 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
92 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
93 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
94 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
95
96 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
97 }
98
99 static void rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev,
100 const unsigned int word, u8 *value)
101 {
102 u32 reg;
103
104 /*
105 * Wait until the BBP becomes ready.
106 */
107 reg = rt61pci_bbp_check(rt2x00dev);
108 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
109 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
110 return;
111 }
112
113 /*
114 * Write the request into the BBP.
115 */
116 reg = 0;
117 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
118 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
119 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
120
121 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
122
123 /*
124 * Wait until the BBP becomes ready.
125 */
126 reg = rt61pci_bbp_check(rt2x00dev);
127 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
128 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
129 *value = 0xff;
130 return;
131 }
132
133 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
134 }
135
136 static void rt61pci_rf_write(struct rt2x00_dev *rt2x00dev,
137 const unsigned int word, const u32 value)
138 {
139 u32 reg;
140 unsigned int i;
141
142 if (!word)
143 return;
144
145 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
146 rt2x00pci_register_read(rt2x00dev, PHY_CSR4, &reg);
147 if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY))
148 goto rf_write;
149 udelay(REGISTER_BUSY_DELAY);
150 }
151
152 ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n");
153 return;
154
155 rf_write:
156 reg = 0;
157 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
158 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS, 21);
159 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
160 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
161
162 rt2x00pci_register_write(rt2x00dev, PHY_CSR4, reg);
163 rt2x00_rf_write(rt2x00dev, word, value);
164 }
165
166 #ifdef CONFIG_RT61PCI_LEDS
167 /*
168 * This function is only called from rt61pci_led_brightness()
169 * make gcc happy by placing this function inside the
170 * same ifdef statement as the caller.
171 */
172 static void rt61pci_mcu_request(struct rt2x00_dev *rt2x00dev,
173 const u8 command, const u8 token,
174 const u8 arg0, const u8 arg1)
175 {
176 u32 reg;
177
178 rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CSR, &reg);
179
180 if (rt2x00_get_field32(reg, H2M_MAILBOX_CSR_OWNER)) {
181 ERROR(rt2x00dev, "mcu request error. "
182 "Request 0x%02x failed for token 0x%02x.\n",
183 command, token);
184 return;
185 }
186
187 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
188 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
189 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
190 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
191 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
192
193 rt2x00pci_register_read(rt2x00dev, HOST_CMD_CSR, &reg);
194 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
195 rt2x00_set_field32(&reg, HOST_CMD_CSR_INTERRUPT_MCU, 1);
196 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
197 }
198 #endif /* CONFIG_RT61PCI_LEDS */
199
200 static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
201 {
202 struct rt2x00_dev *rt2x00dev = eeprom->data;
203 u32 reg;
204
205 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
206
207 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
208 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
209 eeprom->reg_data_clock =
210 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
211 eeprom->reg_chip_select =
212 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
213 }
214
215 static void rt61pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
216 {
217 struct rt2x00_dev *rt2x00dev = eeprom->data;
218 u32 reg = 0;
219
220 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
221 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
222 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
223 !!eeprom->reg_data_clock);
224 rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
225 !!eeprom->reg_chip_select);
226
227 rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
228 }
229
230 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
231 #define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
232
233 static void rt61pci_read_csr(struct rt2x00_dev *rt2x00dev,
234 const unsigned int word, u32 *data)
235 {
236 rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
237 }
238
239 static void rt61pci_write_csr(struct rt2x00_dev *rt2x00dev,
240 const unsigned int word, u32 data)
241 {
242 rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
243 }
244
245 static const struct rt2x00debug rt61pci_rt2x00debug = {
246 .owner = THIS_MODULE,
247 .csr = {
248 .read = rt61pci_read_csr,
249 .write = rt61pci_write_csr,
250 .word_size = sizeof(u32),
251 .word_count = CSR_REG_SIZE / sizeof(u32),
252 },
253 .eeprom = {
254 .read = rt2x00_eeprom_read,
255 .write = rt2x00_eeprom_write,
256 .word_size = sizeof(u16),
257 .word_count = EEPROM_SIZE / sizeof(u16),
258 },
259 .bbp = {
260 .read = rt61pci_bbp_read,
261 .write = rt61pci_bbp_write,
262 .word_size = sizeof(u8),
263 .word_count = BBP_SIZE / sizeof(u8),
264 },
265 .rf = {
266 .read = rt2x00_rf_read,
267 .write = rt61pci_rf_write,
268 .word_size = sizeof(u32),
269 .word_count = RF_SIZE / sizeof(u32),
270 },
271 };
272 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
273
274 #ifdef CONFIG_RT61PCI_RFKILL
275 static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
276 {
277 u32 reg;
278
279 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
280 return rt2x00_get_field32(reg, MAC_CSR13_BIT5);
281 }
282 #else
283 #define rt61pci_rfkill_poll NULL
284 #endif /* CONFIG_RT61PCI_RFKILL */
285
286 #ifdef CONFIG_RT61PCI_LEDS
287 static void rt61pci_brightness_set(struct led_classdev *led_cdev,
288 enum led_brightness brightness)
289 {
290 struct rt2x00_led *led =
291 container_of(led_cdev, struct rt2x00_led, led_dev);
292 unsigned int enabled = brightness != LED_OFF;
293 unsigned int a_mode =
294 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
295 unsigned int bg_mode =
296 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
297
298 if (led->type == LED_TYPE_RADIO) {
299 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
300 MCU_LEDCS_RADIO_STATUS, enabled);
301
302 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
303 (led->rt2x00dev->led_mcu_reg & 0xff),
304 ((led->rt2x00dev->led_mcu_reg >> 8)));
305 } else if (led->type == LED_TYPE_ASSOC) {
306 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
307 MCU_LEDCS_LINK_BG_STATUS, bg_mode);
308 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
309 MCU_LEDCS_LINK_A_STATUS, a_mode);
310
311 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
312 (led->rt2x00dev->led_mcu_reg & 0xff),
313 ((led->rt2x00dev->led_mcu_reg >> 8)));
314 } else if (led->type == LED_TYPE_QUALITY) {
315 /*
316 * The brightness is divided into 6 levels (0 - 5),
317 * this means we need to convert the brightness
318 * argument into the matching level within that range.
319 */
320 rt61pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
321 brightness / (LED_FULL / 6), 0);
322 }
323 }
324
325 static int rt61pci_blink_set(struct led_classdev *led_cdev,
326 unsigned long *delay_on,
327 unsigned long *delay_off)
328 {
329 struct rt2x00_led *led =
330 container_of(led_cdev, struct rt2x00_led, led_dev);
331 u32 reg;
332
333 rt2x00pci_register_read(led->rt2x00dev, MAC_CSR14, &reg);
334 rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, *delay_on);
335 rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, *delay_off);
336 rt2x00pci_register_write(led->rt2x00dev, MAC_CSR14, reg);
337
338 return 0;
339 }
340
341 static void rt61pci_init_led(struct rt2x00_dev *rt2x00dev,
342 struct rt2x00_led *led,
343 enum led_type type)
344 {
345 led->rt2x00dev = rt2x00dev;
346 led->type = type;
347 led->led_dev.brightness_set = rt61pci_brightness_set;
348 led->led_dev.blink_set = rt61pci_blink_set;
349 led->flags = LED_INITIALIZED;
350 }
351 #endif /* CONFIG_RT61PCI_LEDS */
352
353 /*
354 * Configuration handlers.
355 */
356 static int rt61pci_config_shared_key(struct rt2x00_dev *rt2x00dev,
357 struct rt2x00lib_crypto *crypto,
358 struct ieee80211_key_conf *key)
359 {
360 struct hw_key_entry key_entry;
361 struct rt2x00_field32 field;
362 u32 mask;
363 u32 reg;
364
365 if (crypto->cmd == SET_KEY) {
366 /*
367 * rt2x00lib can't determine the correct free
368 * key_idx for shared keys. We have 1 register
369 * with key valid bits. The goal is simple, read
370 * the register, if that is full we have no slots
371 * left.
372 * Note that each BSS is allowed to have up to 4
373 * shared keys, so put a mask over the allowed
374 * entries.
375 */
376 mask = (0xf << crypto->bssidx);
377
378 rt2x00pci_register_read(rt2x00dev, SEC_CSR0, &reg);
379 reg &= mask;
380
381 if (reg && reg == mask)
382 return -ENOSPC;
383
384 key->hw_key_idx += reg ? (ffz(reg) - 1) : 0;
385
386 /*
387 * Upload key to hardware
388 */
389 memcpy(key_entry.key, crypto->key,
390 sizeof(key_entry.key));
391 memcpy(key_entry.tx_mic, crypto->tx_mic,
392 sizeof(key_entry.tx_mic));
393 memcpy(key_entry.rx_mic, crypto->rx_mic,
394 sizeof(key_entry.rx_mic));
395
396 reg = SHARED_KEY_ENTRY(key->hw_key_idx);
397 rt2x00pci_register_multiwrite(rt2x00dev, reg,
398 &key_entry, sizeof(key_entry));
399
400 /*
401 * The cipher types are stored over 2 registers.
402 * bssidx 0 and 1 keys are stored in SEC_CSR1 and
403 * bssidx 1 and 2 keys are stored in SEC_CSR5.
404 * Using the correct defines correctly will cause overhead,
405 * so just calculate the correct offset.
406 */
407 if (key->hw_key_idx < 8) {
408 field.bit_offset = (3 * key->hw_key_idx);
409 field.bit_mask = 0x7 << field.bit_offset;
410
411 rt2x00pci_register_read(rt2x00dev, SEC_CSR1, &reg);
412 rt2x00_set_field32(&reg, field, crypto->cipher);
413 rt2x00pci_register_write(rt2x00dev, SEC_CSR1, reg);
414 } else {
415 field.bit_offset = (3 * (key->hw_key_idx - 8));
416 field.bit_mask = 0x7 << field.bit_offset;
417
418 rt2x00pci_register_read(rt2x00dev, SEC_CSR5, &reg);
419 rt2x00_set_field32(&reg, field, crypto->cipher);
420 rt2x00pci_register_write(rt2x00dev, SEC_CSR5, reg);
421 }
422
423 /*
424 * The driver does not support the IV/EIV generation
425 * in hardware. However it doesn't support the IV/EIV
426 * inside the ieee80211 frame either, but requires it
427 * to be provided seperately for the descriptor.
428 * rt2x00lib will cut the IV/EIV data out of all frames
429 * given to us by mac80211, but we must tell mac80211
430 * to generate the IV/EIV data.
431 */
432 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
433 }
434
435 /*
436 * SEC_CSR0 contains only single-bit fields to indicate
437 * a particular key is valid. Because using the FIELD32()
438 * defines directly will cause a lot of overhead we use
439 * a calculation to determine the correct bit directly.
440 */
441 mask = 1 << key->hw_key_idx;
442
443 rt2x00pci_register_read(rt2x00dev, SEC_CSR0, &reg);
444 if (crypto->cmd == SET_KEY)
445 reg |= mask;
446 else if (crypto->cmd == DISABLE_KEY)
447 reg &= ~mask;
448 rt2x00pci_register_write(rt2x00dev, SEC_CSR0, reg);
449
450 return 0;
451 }
452
453 static int rt61pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
454 struct rt2x00lib_crypto *crypto,
455 struct ieee80211_key_conf *key)
456 {
457 struct hw_pairwise_ta_entry addr_entry;
458 struct hw_key_entry key_entry;
459 u32 mask;
460 u32 reg;
461
462 if (crypto->cmd == SET_KEY) {
463 /*
464 * rt2x00lib can't determine the correct free
465 * key_idx for pairwise keys. We have 2 registers
466 * with key valid bits. The goal is simple, read
467 * the first register, if that is full move to
468 * the next register.
469 * When both registers are full, we drop the key,
470 * otherwise we use the first invalid entry.
471 */
472 rt2x00pci_register_read(rt2x00dev, SEC_CSR2, &reg);
473 if (reg && reg == ~0) {
474 key->hw_key_idx = 32;
475 rt2x00pci_register_read(rt2x00dev, SEC_CSR3, &reg);
476 if (reg && reg == ~0)
477 return -ENOSPC;
478 }
479
480 key->hw_key_idx += reg ? (ffz(reg) - 1) : 0;
481
482 /*
483 * Upload key to hardware
484 */
485 memcpy(key_entry.key, crypto->key,
486 sizeof(key_entry.key));
487 memcpy(key_entry.tx_mic, crypto->tx_mic,
488 sizeof(key_entry.tx_mic));
489 memcpy(key_entry.rx_mic, crypto->rx_mic,
490 sizeof(key_entry.rx_mic));
491
492 memset(&addr_entry, 0, sizeof(addr_entry));
493 memcpy(&addr_entry, crypto->address, ETH_ALEN);
494 addr_entry.cipher = crypto->cipher;
495
496 reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
497 rt2x00pci_register_multiwrite(rt2x00dev, reg,
498 &key_entry, sizeof(key_entry));
499
500 reg = PAIRWISE_TA_ENTRY(key->hw_key_idx);
501 rt2x00pci_register_multiwrite(rt2x00dev, reg,
502 &addr_entry, sizeof(addr_entry));
503
504 /*
505 * Enable pairwise lookup table for given BSS idx,
506 * without this received frames will not be decrypted
507 * by the hardware.
508 */
509 rt2x00pci_register_read(rt2x00dev, SEC_CSR4, &reg);
510 reg |= (1 << crypto->bssidx);
511 rt2x00pci_register_write(rt2x00dev, SEC_CSR4, reg);
512
513 /*
514 * The driver does not support the IV/EIV generation
515 * in hardware. However it doesn't support the IV/EIV
516 * inside the ieee80211 frame either, but requires it
517 * to be provided seperately for the descriptor.
518 * rt2x00lib will cut the IV/EIV data out of all frames
519 * given to us by mac80211, but we must tell mac80211
520 * to generate the IV/EIV data.
521 */
522 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
523 }
524
525 /*
526 * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate
527 * a particular key is valid. Because using the FIELD32()
528 * defines directly will cause a lot of overhead we use
529 * a calculation to determine the correct bit directly.
530 */
531 if (key->hw_key_idx < 32) {
532 mask = 1 << key->hw_key_idx;
533
534 rt2x00pci_register_read(rt2x00dev, SEC_CSR2, &reg);
535 if (crypto->cmd == SET_KEY)
536 reg |= mask;
537 else if (crypto->cmd == DISABLE_KEY)
538 reg &= ~mask;
539 rt2x00pci_register_write(rt2x00dev, SEC_CSR2, reg);
540 } else {
541 mask = 1 << (key->hw_key_idx - 32);
542
543 rt2x00pci_register_read(rt2x00dev, SEC_CSR3, &reg);
544 if (crypto->cmd == SET_KEY)
545 reg |= mask;
546 else if (crypto->cmd == DISABLE_KEY)
547 reg &= ~mask;
548 rt2x00pci_register_write(rt2x00dev, SEC_CSR3, reg);
549 }
550
551 return 0;
552 }
553
554 static void rt61pci_config_filter(struct rt2x00_dev *rt2x00dev,
555 const unsigned int filter_flags)
556 {
557 u32 reg;
558
559 /*
560 * Start configuration steps.
561 * Note that the version error will always be dropped
562 * and broadcast frames will always be accepted since
563 * there is no filter for it at this time.
564 */
565 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
566 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
567 !(filter_flags & FIF_FCSFAIL));
568 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
569 !(filter_flags & FIF_PLCPFAIL));
570 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
571 !(filter_flags & FIF_CONTROL));
572 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
573 !(filter_flags & FIF_PROMISC_IN_BSS));
574 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
575 !(filter_flags & FIF_PROMISC_IN_BSS) &&
576 !rt2x00dev->intf_ap_count);
577 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
578 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
579 !(filter_flags & FIF_ALLMULTI));
580 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
581 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
582 !(filter_flags & FIF_CONTROL));
583 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
584 }
585
586 static void rt61pci_config_intf(struct rt2x00_dev *rt2x00dev,
587 struct rt2x00_intf *intf,
588 struct rt2x00intf_conf *conf,
589 const unsigned int flags)
590 {
591 unsigned int beacon_base;
592 u32 reg;
593
594 if (flags & CONFIG_UPDATE_TYPE) {
595 /*
596 * Clear current synchronisation setup.
597 * For the Beacon base registers we only need to clear
598 * the first byte since that byte contains the VALID and OWNER
599 * bits which (when set to 0) will invalidate the entire beacon.
600 */
601 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
602 rt2x00pci_register_write(rt2x00dev, beacon_base, 0);
603
604 /*
605 * Enable synchronisation.
606 */
607 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
608 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
609 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
610 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
611 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
612 }
613
614 if (flags & CONFIG_UPDATE_MAC) {
615 reg = le32_to_cpu(conf->mac[1]);
616 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
617 conf->mac[1] = cpu_to_le32(reg);
618
619 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR2,
620 conf->mac, sizeof(conf->mac));
621 }
622
623 if (flags & CONFIG_UPDATE_BSSID) {
624 reg = le32_to_cpu(conf->bssid[1]);
625 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
626 conf->bssid[1] = cpu_to_le32(reg);
627
628 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR4,
629 conf->bssid, sizeof(conf->bssid));
630 }
631 }
632
633 static void rt61pci_config_erp(struct rt2x00_dev *rt2x00dev,
634 struct rt2x00lib_erp *erp)
635 {
636 u32 reg;
637
638 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
639 rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, erp->ack_timeout);
640 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
641
642 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
643 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
644 !!erp->short_preamble);
645 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
646 }
647
648
649 static void rt61pci_config_lna_gain(struct rt2x00_dev *rt2x00dev,
650 struct rt2x00lib_conf *libconf)
651 {
652 u16 eeprom;
653 short lna_gain = 0;
654
655 if (libconf->band == IEEE80211_BAND_2GHZ) {
656 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
657 lna_gain += 14;
658
659 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
660 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
661 } else {
662 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
663 lna_gain += 14;
664
665 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
666 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
667 }
668
669 rt2x00dev->lna_gain = lna_gain;
670 }
671
672 static void rt61pci_config_phymode(struct rt2x00_dev *rt2x00dev,
673 const int basic_rate_mask)
674 {
675 rt2x00pci_register_write(rt2x00dev, TXRX_CSR5, basic_rate_mask);
676 }
677
678 static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev,
679 struct rf_channel *rf, const int txpower)
680 {
681 u8 r3;
682 u8 r94;
683 u8 smart;
684
685 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
686 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
687
688 smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
689 rt2x00_rf(&rt2x00dev->chip, RF2527));
690
691 rt61pci_bbp_read(rt2x00dev, 3, &r3);
692 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
693 rt61pci_bbp_write(rt2x00dev, 3, r3);
694
695 r94 = 6;
696 if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
697 r94 += txpower - MAX_TXPOWER;
698 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
699 r94 += txpower;
700 rt61pci_bbp_write(rt2x00dev, 94, r94);
701
702 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
703 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
704 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
705 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
706
707 udelay(200);
708
709 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
710 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
711 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
712 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
713
714 udelay(200);
715
716 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
717 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
718 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
719 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
720
721 msleep(1);
722 }
723
724 static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev,
725 const int txpower)
726 {
727 struct rf_channel rf;
728
729 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
730 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
731 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
732 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
733
734 rt61pci_config_channel(rt2x00dev, &rf, txpower);
735 }
736
737 static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
738 struct antenna_setup *ant)
739 {
740 u8 r3;
741 u8 r4;
742 u8 r77;
743
744 rt61pci_bbp_read(rt2x00dev, 3, &r3);
745 rt61pci_bbp_read(rt2x00dev, 4, &r4);
746 rt61pci_bbp_read(rt2x00dev, 77, &r77);
747
748 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
749 rt2x00_rf(&rt2x00dev->chip, RF5325));
750
751 /*
752 * Configure the RX antenna.
753 */
754 switch (ant->rx) {
755 case ANTENNA_HW_DIVERSITY:
756 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
757 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
758 (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ));
759 break;
760 case ANTENNA_A:
761 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
762 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
763 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
764 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
765 else
766 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
767 break;
768 case ANTENNA_B:
769 default:
770 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
771 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
772 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
773 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
774 else
775 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
776 break;
777 }
778
779 rt61pci_bbp_write(rt2x00dev, 77, r77);
780 rt61pci_bbp_write(rt2x00dev, 3, r3);
781 rt61pci_bbp_write(rt2x00dev, 4, r4);
782 }
783
784 static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
785 struct antenna_setup *ant)
786 {
787 u8 r3;
788 u8 r4;
789 u8 r77;
790
791 rt61pci_bbp_read(rt2x00dev, 3, &r3);
792 rt61pci_bbp_read(rt2x00dev, 4, &r4);
793 rt61pci_bbp_read(rt2x00dev, 77, &r77);
794
795 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
796 rt2x00_rf(&rt2x00dev->chip, RF2529));
797 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
798 !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
799
800 /*
801 * Configure the RX antenna.
802 */
803 switch (ant->rx) {
804 case ANTENNA_HW_DIVERSITY:
805 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
806 break;
807 case ANTENNA_A:
808 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
809 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
810 break;
811 case ANTENNA_B:
812 default:
813 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
814 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
815 break;
816 }
817
818 rt61pci_bbp_write(rt2x00dev, 77, r77);
819 rt61pci_bbp_write(rt2x00dev, 3, r3);
820 rt61pci_bbp_write(rt2x00dev, 4, r4);
821 }
822
823 static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev,
824 const int p1, const int p2)
825 {
826 u32 reg;
827
828 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
829
830 rt2x00_set_field32(&reg, MAC_CSR13_BIT4, p1);
831 rt2x00_set_field32(&reg, MAC_CSR13_BIT12, 0);
832
833 rt2x00_set_field32(&reg, MAC_CSR13_BIT3, !p2);
834 rt2x00_set_field32(&reg, MAC_CSR13_BIT11, 0);
835
836 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg);
837 }
838
839 static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev,
840 struct antenna_setup *ant)
841 {
842 u8 r3;
843 u8 r4;
844 u8 r77;
845
846 rt61pci_bbp_read(rt2x00dev, 3, &r3);
847 rt61pci_bbp_read(rt2x00dev, 4, &r4);
848 rt61pci_bbp_read(rt2x00dev, 77, &r77);
849
850 /*
851 * Configure the RX antenna.
852 */
853 switch (ant->rx) {
854 case ANTENNA_A:
855 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
856 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
857 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0);
858 break;
859 case ANTENNA_HW_DIVERSITY:
860 /*
861 * FIXME: Antenna selection for the rf 2529 is very confusing
862 * in the legacy driver. Just default to antenna B until the
863 * legacy code can be properly translated into rt2x00 code.
864 */
865 case ANTENNA_B:
866 default:
867 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
868 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
869 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
870 break;
871 }
872
873 rt61pci_bbp_write(rt2x00dev, 77, r77);
874 rt61pci_bbp_write(rt2x00dev, 3, r3);
875 rt61pci_bbp_write(rt2x00dev, 4, r4);
876 }
877
878 struct antenna_sel {
879 u8 word;
880 /*
881 * value[0] -> non-LNA
882 * value[1] -> LNA
883 */
884 u8 value[2];
885 };
886
887 static const struct antenna_sel antenna_sel_a[] = {
888 { 96, { 0x58, 0x78 } },
889 { 104, { 0x38, 0x48 } },
890 { 75, { 0xfe, 0x80 } },
891 { 86, { 0xfe, 0x80 } },
892 { 88, { 0xfe, 0x80 } },
893 { 35, { 0x60, 0x60 } },
894 { 97, { 0x58, 0x58 } },
895 { 98, { 0x58, 0x58 } },
896 };
897
898 static const struct antenna_sel antenna_sel_bg[] = {
899 { 96, { 0x48, 0x68 } },
900 { 104, { 0x2c, 0x3c } },
901 { 75, { 0xfe, 0x80 } },
902 { 86, { 0xfe, 0x80 } },
903 { 88, { 0xfe, 0x80 } },
904 { 35, { 0x50, 0x50 } },
905 { 97, { 0x48, 0x48 } },
906 { 98, { 0x48, 0x48 } },
907 };
908
909 static void rt61pci_config_antenna(struct rt2x00_dev *rt2x00dev,
910 struct antenna_setup *ant)
911 {
912 const struct antenna_sel *sel;
913 unsigned int lna;
914 unsigned int i;
915 u32 reg;
916
917 /*
918 * We should never come here because rt2x00lib is supposed
919 * to catch this and send us the correct antenna explicitely.
920 */
921 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
922 ant->tx == ANTENNA_SW_DIVERSITY);
923
924 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
925 sel = antenna_sel_a;
926 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
927 } else {
928 sel = antenna_sel_bg;
929 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
930 }
931
932 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
933 rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
934
935 rt2x00pci_register_read(rt2x00dev, PHY_CSR0, &reg);
936
937 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
938 rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
939 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
940 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
941
942 rt2x00pci_register_write(rt2x00dev, PHY_CSR0, reg);
943
944 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
945 rt2x00_rf(&rt2x00dev->chip, RF5325))
946 rt61pci_config_antenna_5x(rt2x00dev, ant);
947 else if (rt2x00_rf(&rt2x00dev->chip, RF2527))
948 rt61pci_config_antenna_2x(rt2x00dev, ant);
949 else if (rt2x00_rf(&rt2x00dev->chip, RF2529)) {
950 if (test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags))
951 rt61pci_config_antenna_2x(rt2x00dev, ant);
952 else
953 rt61pci_config_antenna_2529(rt2x00dev, ant);
954 }
955 }
956
957 static void rt61pci_config_duration(struct rt2x00_dev *rt2x00dev,
958 struct rt2x00lib_conf *libconf)
959 {
960 u32 reg;
961
962 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
963 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, libconf->slot_time);
964 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
965
966 rt2x00pci_register_read(rt2x00dev, MAC_CSR8, &reg);
967 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, libconf->sifs);
968 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
969 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, libconf->eifs);
970 rt2x00pci_register_write(rt2x00dev, MAC_CSR8, reg);
971
972 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
973 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
974 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
975
976 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
977 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
978 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
979
980 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
981 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
982 libconf->conf->beacon_int * 16);
983 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
984 }
985
986 static void rt61pci_config(struct rt2x00_dev *rt2x00dev,
987 struct rt2x00lib_conf *libconf,
988 const unsigned int flags)
989 {
990 /* Always recalculate LNA gain before changing configuration */
991 rt61pci_config_lna_gain(rt2x00dev, libconf);
992
993 if (flags & CONFIG_UPDATE_PHYMODE)
994 rt61pci_config_phymode(rt2x00dev, libconf->basic_rates);
995 if (flags & CONFIG_UPDATE_CHANNEL)
996 rt61pci_config_channel(rt2x00dev, &libconf->rf,
997 libconf->conf->power_level);
998 if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
999 rt61pci_config_txpower(rt2x00dev, libconf->conf->power_level);
1000 if (flags & CONFIG_UPDATE_ANTENNA)
1001 rt61pci_config_antenna(rt2x00dev, &libconf->ant);
1002 if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
1003 rt61pci_config_duration(rt2x00dev, libconf);
1004 }
1005
1006 /*
1007 * Link tuning
1008 */
1009 static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev,
1010 struct link_qual *qual)
1011 {
1012 u32 reg;
1013
1014 /*
1015 * Update FCS error count from register.
1016 */
1017 rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
1018 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
1019
1020 /*
1021 * Update False CCA count from register.
1022 */
1023 rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
1024 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
1025 }
1026
1027 static void rt61pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
1028 {
1029 rt61pci_bbp_write(rt2x00dev, 17, 0x20);
1030 rt2x00dev->link.vgc_level = 0x20;
1031 }
1032
1033 static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev)
1034 {
1035 int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
1036 u8 r17;
1037 u8 up_bound;
1038 u8 low_bound;
1039
1040 rt61pci_bbp_read(rt2x00dev, 17, &r17);
1041
1042 /*
1043 * Determine r17 bounds.
1044 */
1045 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
1046 low_bound = 0x28;
1047 up_bound = 0x48;
1048 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
1049 low_bound += 0x10;
1050 up_bound += 0x10;
1051 }
1052 } else {
1053 low_bound = 0x20;
1054 up_bound = 0x40;
1055 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
1056 low_bound += 0x10;
1057 up_bound += 0x10;
1058 }
1059 }
1060
1061 /*
1062 * If we are not associated, we should go straight to the
1063 * dynamic CCA tuning.
1064 */
1065 if (!rt2x00dev->intf_associated)
1066 goto dynamic_cca_tune;
1067
1068 /*
1069 * Special big-R17 for very short distance
1070 */
1071 if (rssi >= -35) {
1072 if (r17 != 0x60)
1073 rt61pci_bbp_write(rt2x00dev, 17, 0x60);
1074 return;
1075 }
1076
1077 /*
1078 * Special big-R17 for short distance
1079 */
1080 if (rssi >= -58) {
1081 if (r17 != up_bound)
1082 rt61pci_bbp_write(rt2x00dev, 17, up_bound);
1083 return;
1084 }
1085
1086 /*
1087 * Special big-R17 for middle-short distance
1088 */
1089 if (rssi >= -66) {
1090 low_bound += 0x10;
1091 if (r17 != low_bound)
1092 rt61pci_bbp_write(rt2x00dev, 17, low_bound);
1093 return;
1094 }
1095
1096 /*
1097 * Special mid-R17 for middle distance
1098 */
1099 if (rssi >= -74) {
1100 low_bound += 0x08;
1101 if (r17 != low_bound)
1102 rt61pci_bbp_write(rt2x00dev, 17, low_bound);
1103 return;
1104 }
1105
1106 /*
1107 * Special case: Change up_bound based on the rssi.
1108 * Lower up_bound when rssi is weaker then -74 dBm.
1109 */
1110 up_bound -= 2 * (-74 - rssi);
1111 if (low_bound > up_bound)
1112 up_bound = low_bound;
1113
1114 if (r17 > up_bound) {
1115 rt61pci_bbp_write(rt2x00dev, 17, up_bound);
1116 return;
1117 }
1118
1119 dynamic_cca_tune:
1120
1121 /*
1122 * r17 does not yet exceed upper limit, continue and base
1123 * the r17 tuning on the false CCA count.
1124 */
1125 if (rt2x00dev->link.qual.false_cca > 512 && r17 < up_bound) {
1126 if (++r17 > up_bound)
1127 r17 = up_bound;
1128 rt61pci_bbp_write(rt2x00dev, 17, r17);
1129 } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > low_bound) {
1130 if (--r17 < low_bound)
1131 r17 = low_bound;
1132 rt61pci_bbp_write(rt2x00dev, 17, r17);
1133 }
1134 }
1135
1136 /*
1137 * Firmware functions
1138 */
1139 static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1140 {
1141 char *fw_name;
1142
1143 switch (rt2x00dev->chip.rt) {
1144 case RT2561:
1145 fw_name = FIRMWARE_RT2561;
1146 break;
1147 case RT2561s:
1148 fw_name = FIRMWARE_RT2561s;
1149 break;
1150 case RT2661:
1151 fw_name = FIRMWARE_RT2661;
1152 break;
1153 default:
1154 fw_name = NULL;
1155 break;
1156 }
1157
1158 return fw_name;
1159 }
1160
1161 static u16 rt61pci_get_firmware_crc(const void *data, const size_t len)
1162 {
1163 u16 crc;
1164
1165 /*
1166 * Use the crc itu-t algorithm.
1167 * The last 2 bytes in the firmware array are the crc checksum itself,
1168 * this means that we should never pass those 2 bytes to the crc
1169 * algorithm.
1170 */
1171 crc = crc_itu_t(0, data, len - 2);
1172 crc = crc_itu_t_byte(crc, 0);
1173 crc = crc_itu_t_byte(crc, 0);
1174
1175 return crc;
1176 }
1177
1178 static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev, const void *data,
1179 const size_t len)
1180 {
1181 int i;
1182 u32 reg;
1183
1184 /*
1185 * Wait for stable hardware.
1186 */
1187 for (i = 0; i < 100; i++) {
1188 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
1189 if (reg)
1190 break;
1191 msleep(1);
1192 }
1193
1194 if (!reg) {
1195 ERROR(rt2x00dev, "Unstable hardware.\n");
1196 return -EBUSY;
1197 }
1198
1199 /*
1200 * Prepare MCU and mailbox for firmware loading.
1201 */
1202 reg = 0;
1203 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
1204 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1205 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1206 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1207 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, 0);
1208
1209 /*
1210 * Write firmware to device.
1211 */
1212 reg = 0;
1213 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
1214 rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 1);
1215 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1216
1217 rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
1218 data, len);
1219
1220 rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 0);
1221 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1222
1223 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 0);
1224 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1225
1226 for (i = 0; i < 100; i++) {
1227 rt2x00pci_register_read(rt2x00dev, MCU_CNTL_CSR, &reg);
1228 if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY))
1229 break;
1230 msleep(1);
1231 }
1232
1233 if (i == 100) {
1234 ERROR(rt2x00dev, "MCU Control register not ready.\n");
1235 return -EBUSY;
1236 }
1237
1238 /*
1239 * Hardware needs another millisecond before it is ready.
1240 */
1241 msleep(1);
1242
1243 /*
1244 * Reset MAC and BBP registers.
1245 */
1246 reg = 0;
1247 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1248 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1249 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1250
1251 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1252 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1253 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1254 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1255
1256 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1257 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1258 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1259
1260 return 0;
1261 }
1262
1263 /*
1264 * Initialization functions.
1265 */
1266 static void rt61pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
1267 struct queue_entry *entry)
1268 {
1269 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1270 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1271 u32 word;
1272
1273 rt2x00_desc_read(entry_priv->desc, 5, &word);
1274 rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS,
1275 skbdesc->skb_dma);
1276 rt2x00_desc_write(entry_priv->desc, 5, word);
1277
1278 rt2x00_desc_read(entry_priv->desc, 0, &word);
1279 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
1280 rt2x00_desc_write(entry_priv->desc, 0, word);
1281 }
1282
1283 static void rt61pci_init_txentry(struct rt2x00_dev *rt2x00dev,
1284 struct queue_entry *entry)
1285 {
1286 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1287 u32 word;
1288
1289 rt2x00_desc_read(entry_priv->desc, 0, &word);
1290 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1291 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
1292 rt2x00_desc_write(entry_priv->desc, 0, word);
1293 }
1294
1295 static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev)
1296 {
1297 struct queue_entry_priv_pci *entry_priv;
1298 u32 reg;
1299
1300 /*
1301 * Initialize registers.
1302 */
1303 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR0, &reg);
1304 rt2x00_set_field32(&reg, TX_RING_CSR0_AC0_RING_SIZE,
1305 rt2x00dev->tx[0].limit);
1306 rt2x00_set_field32(&reg, TX_RING_CSR0_AC1_RING_SIZE,
1307 rt2x00dev->tx[1].limit);
1308 rt2x00_set_field32(&reg, TX_RING_CSR0_AC2_RING_SIZE,
1309 rt2x00dev->tx[2].limit);
1310 rt2x00_set_field32(&reg, TX_RING_CSR0_AC3_RING_SIZE,
1311 rt2x00dev->tx[3].limit);
1312 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR0, reg);
1313
1314 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR1, &reg);
1315 rt2x00_set_field32(&reg, TX_RING_CSR1_TXD_SIZE,
1316 rt2x00dev->tx[0].desc_size / 4);
1317 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg);
1318
1319 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
1320 rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, &reg);
1321 rt2x00_set_field32(&reg, AC0_BASE_CSR_RING_REGISTER,
1322 entry_priv->desc_dma);
1323 rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg);
1324
1325 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
1326 rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, &reg);
1327 rt2x00_set_field32(&reg, AC1_BASE_CSR_RING_REGISTER,
1328 entry_priv->desc_dma);
1329 rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg);
1330
1331 entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
1332 rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, &reg);
1333 rt2x00_set_field32(&reg, AC2_BASE_CSR_RING_REGISTER,
1334 entry_priv->desc_dma);
1335 rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg);
1336
1337 entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
1338 rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, &reg);
1339 rt2x00_set_field32(&reg, AC3_BASE_CSR_RING_REGISTER,
1340 entry_priv->desc_dma);
1341 rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg);
1342
1343 rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, &reg);
1344 rt2x00_set_field32(&reg, RX_RING_CSR_RING_SIZE, rt2x00dev->rx->limit);
1345 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_SIZE,
1346 rt2x00dev->rx->desc_size / 4);
1347 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4);
1348 rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg);
1349
1350 entry_priv = rt2x00dev->rx->entries[0].priv_data;
1351 rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, &reg);
1352 rt2x00_set_field32(&reg, RX_BASE_CSR_RING_REGISTER,
1353 entry_priv->desc_dma);
1354 rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg);
1355
1356 rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, &reg);
1357 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC0, 2);
1358 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC1, 2);
1359 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC2, 2);
1360 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC3, 2);
1361 rt2x00pci_register_write(rt2x00dev, TX_DMA_DST_CSR, reg);
1362
1363 rt2x00pci_register_read(rt2x00dev, LOAD_TX_RING_CSR, &reg);
1364 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1);
1365 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1);
1366 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1);
1367 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1);
1368 rt2x00pci_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg);
1369
1370 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1371 rt2x00_set_field32(&reg, RX_CNTL_CSR_LOAD_RXD, 1);
1372 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1373
1374 return 0;
1375 }
1376
1377 static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)
1378 {
1379 u32 reg;
1380
1381 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1382 rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1383 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1384 rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1385 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1386
1387 rt2x00pci_register_read(rt2x00dev, TXRX_CSR1, &reg);
1388 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1389 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
1390 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1391 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
1392 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1393 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
1394 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1395 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
1396 rt2x00pci_register_write(rt2x00dev, TXRX_CSR1, reg);
1397
1398 /*
1399 * CCK TXD BBP registers
1400 */
1401 rt2x00pci_register_read(rt2x00dev, TXRX_CSR2, &reg);
1402 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
1403 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
1404 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
1405 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
1406 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
1407 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
1408 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
1409 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
1410 rt2x00pci_register_write(rt2x00dev, TXRX_CSR2, reg);
1411
1412 /*
1413 * OFDM TXD BBP registers
1414 */
1415 rt2x00pci_register_read(rt2x00dev, TXRX_CSR3, &reg);
1416 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
1417 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
1418 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1419 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1420 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1421 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
1422 rt2x00pci_register_write(rt2x00dev, TXRX_CSR3, reg);
1423
1424 rt2x00pci_register_read(rt2x00dev, TXRX_CSR7, &reg);
1425 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1426 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1427 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1428 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
1429 rt2x00pci_register_write(rt2x00dev, TXRX_CSR7, reg);
1430
1431 rt2x00pci_register_read(rt2x00dev, TXRX_CSR8, &reg);
1432 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1433 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1434 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1435 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
1436 rt2x00pci_register_write(rt2x00dev, TXRX_CSR8, reg);
1437
1438 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1439 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, 0);
1440 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1441 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 0);
1442 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1443 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1444 rt2x00_set_field32(&reg, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0);
1445 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1446
1447 rt2x00pci_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1448
1449 rt2x00pci_register_write(rt2x00dev, MAC_CSR6, 0x00000fff);
1450
1451 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
1452 rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1453 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
1454
1455 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x0000071c);
1456
1457 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1458 return -EBUSY;
1459
1460 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, 0x0000e000);
1461
1462 /*
1463 * Invalidate all Shared Keys (SEC_CSR0),
1464 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1465 */
1466 rt2x00pci_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1467 rt2x00pci_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1468 rt2x00pci_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1469
1470 rt2x00pci_register_write(rt2x00dev, PHY_CSR1, 0x000023b0);
1471 rt2x00pci_register_write(rt2x00dev, PHY_CSR5, 0x060a100c);
1472 rt2x00pci_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1473 rt2x00pci_register_write(rt2x00dev, PHY_CSR7, 0x00000a08);
1474
1475 rt2x00pci_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404);
1476
1477 rt2x00pci_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200);
1478
1479 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1480
1481 rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR0, &reg);
1482 rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC0_TX_OP, 0);
1483 rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC1_TX_OP, 0);
1484 rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
1485
1486 rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR1, &reg);
1487 rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC2_TX_OP, 192);
1488 rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC3_TX_OP, 48);
1489 rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
1490
1491 /*
1492 * Clear all beacons
1493 * For the Beacon base registers we only need to clear
1494 * the first byte since that byte contains the VALID and OWNER
1495 * bits which (when set to 0) will invalidate the entire beacon.
1496 */
1497 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1498 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1499 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1500 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1501
1502 /*
1503 * We must clear the error counters.
1504 * These registers are cleared on read,
1505 * so we may pass a useless variable to store the value.
1506 */
1507 rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
1508 rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
1509 rt2x00pci_register_read(rt2x00dev, STA_CSR2, &reg);
1510
1511 /*
1512 * Reset MAC and BBP registers.
1513 */
1514 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1515 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1516 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1517 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1518
1519 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1520 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1521 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1522 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1523
1524 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1525 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1526 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1527
1528 return 0;
1529 }
1530
1531 static int rt61pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1532 {
1533 unsigned int i;
1534 u8 value;
1535
1536 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1537 rt61pci_bbp_read(rt2x00dev, 0, &value);
1538 if ((value != 0xff) && (value != 0x00))
1539 return 0;
1540 udelay(REGISTER_BUSY_DELAY);
1541 }
1542
1543 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1544 return -EACCES;
1545 }
1546
1547 static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1548 {
1549 unsigned int i;
1550 u16 eeprom;
1551 u8 reg_id;
1552 u8 value;
1553
1554 if (unlikely(rt61pci_wait_bbp_ready(rt2x00dev)))
1555 return -EACCES;
1556
1557 rt61pci_bbp_write(rt2x00dev, 3, 0x00);
1558 rt61pci_bbp_write(rt2x00dev, 15, 0x30);
1559 rt61pci_bbp_write(rt2x00dev, 21, 0xc8);
1560 rt61pci_bbp_write(rt2x00dev, 22, 0x38);
1561 rt61pci_bbp_write(rt2x00dev, 23, 0x06);
1562 rt61pci_bbp_write(rt2x00dev, 24, 0xfe);
1563 rt61pci_bbp_write(rt2x00dev, 25, 0x0a);
1564 rt61pci_bbp_write(rt2x00dev, 26, 0x0d);
1565 rt61pci_bbp_write(rt2x00dev, 34, 0x12);
1566 rt61pci_bbp_write(rt2x00dev, 37, 0x07);
1567 rt61pci_bbp_write(rt2x00dev, 39, 0xf8);
1568 rt61pci_bbp_write(rt2x00dev, 41, 0x60);
1569 rt61pci_bbp_write(rt2x00dev, 53, 0x10);
1570 rt61pci_bbp_write(rt2x00dev, 54, 0x18);
1571 rt61pci_bbp_write(rt2x00dev, 60, 0x10);
1572 rt61pci_bbp_write(rt2x00dev, 61, 0x04);
1573 rt61pci_bbp_write(rt2x00dev, 62, 0x04);
1574 rt61pci_bbp_write(rt2x00dev, 75, 0xfe);
1575 rt61pci_bbp_write(rt2x00dev, 86, 0xfe);
1576 rt61pci_bbp_write(rt2x00dev, 88, 0xfe);
1577 rt61pci_bbp_write(rt2x00dev, 90, 0x0f);
1578 rt61pci_bbp_write(rt2x00dev, 99, 0x00);
1579 rt61pci_bbp_write(rt2x00dev, 102, 0x16);
1580 rt61pci_bbp_write(rt2x00dev, 107, 0x04);
1581
1582 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1583 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1584
1585 if (eeprom != 0xffff && eeprom != 0x0000) {
1586 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1587 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1588 rt61pci_bbp_write(rt2x00dev, reg_id, value);
1589 }
1590 }
1591
1592 return 0;
1593 }
1594
1595 /*
1596 * Device state switch handlers.
1597 */
1598 static void rt61pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1599 enum dev_state state)
1600 {
1601 u32 reg;
1602
1603 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1604 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
1605 (state == STATE_RADIO_RX_OFF) ||
1606 (state == STATE_RADIO_RX_OFF_LINK));
1607 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1608 }
1609
1610 static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1611 enum dev_state state)
1612 {
1613 int mask = (state == STATE_RADIO_IRQ_OFF);
1614 u32 reg;
1615
1616 /*
1617 * When interrupts are being enabled, the interrupt registers
1618 * should clear the register to assure a clean state.
1619 */
1620 if (state == STATE_RADIO_IRQ_ON) {
1621 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1622 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1623
1624 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg);
1625 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg);
1626 }
1627
1628 /*
1629 * Only toggle the interrupts bits we are going to use.
1630 * Non-checked interrupt bits are disabled by default.
1631 */
1632 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
1633 rt2x00_set_field32(&reg, INT_MASK_CSR_TXDONE, mask);
1634 rt2x00_set_field32(&reg, INT_MASK_CSR_RXDONE, mask);
1635 rt2x00_set_field32(&reg, INT_MASK_CSR_ENABLE_MITIGATION, mask);
1636 rt2x00_set_field32(&reg, INT_MASK_CSR_MITIGATION_PERIOD, 0xff);
1637 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
1638
1639 rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
1640 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_0, mask);
1641 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_1, mask);
1642 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_2, mask);
1643 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_3, mask);
1644 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_4, mask);
1645 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_5, mask);
1646 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_6, mask);
1647 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_7, mask);
1648 rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
1649 }
1650
1651 static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1652 {
1653 u32 reg;
1654
1655 /*
1656 * Initialize all registers.
1657 */
1658 if (unlikely(rt61pci_init_queues(rt2x00dev) ||
1659 rt61pci_init_registers(rt2x00dev) ||
1660 rt61pci_init_bbp(rt2x00dev)))
1661 return -EIO;
1662
1663 /*
1664 * Enable RX.
1665 */
1666 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1667 rt2x00_set_field32(&reg, RX_CNTL_CSR_ENABLE_RX_DMA, 1);
1668 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1669
1670 return 0;
1671 }
1672
1673 static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1674 {
1675 u32 reg;
1676
1677 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1678
1679 /*
1680 * Disable synchronisation.
1681 */
1682 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
1683
1684 /*
1685 * Cancel RX and TX.
1686 */
1687 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1688 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC0, 1);
1689 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC1, 1);
1690 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC2, 1);
1691 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC3, 1);
1692 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1693 }
1694
1695 static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1696 {
1697 u32 reg;
1698 unsigned int i;
1699 char put_to_sleep;
1700
1701 put_to_sleep = (state != STATE_AWAKE);
1702
1703 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1704 rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1705 rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1706 rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg);
1707
1708 /*
1709 * Device is not guaranteed to be in the requested state yet.
1710 * We must wait until the register indicates that the
1711 * device has entered the correct state.
1712 */
1713 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1714 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1715 state = rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1716 if (state == !put_to_sleep)
1717 return 0;
1718 msleep(10);
1719 }
1720
1721 return -EBUSY;
1722 }
1723
1724 static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1725 enum dev_state state)
1726 {
1727 int retval = 0;
1728
1729 switch (state) {
1730 case STATE_RADIO_ON:
1731 retval = rt61pci_enable_radio(rt2x00dev);
1732 break;
1733 case STATE_RADIO_OFF:
1734 rt61pci_disable_radio(rt2x00dev);
1735 break;
1736 case STATE_RADIO_RX_ON:
1737 case STATE_RADIO_RX_ON_LINK:
1738 case STATE_RADIO_RX_OFF:
1739 case STATE_RADIO_RX_OFF_LINK:
1740 rt61pci_toggle_rx(rt2x00dev, state);
1741 break;
1742 case STATE_RADIO_IRQ_ON:
1743 case STATE_RADIO_IRQ_OFF:
1744 rt61pci_toggle_irq(rt2x00dev, state);
1745 break;
1746 case STATE_DEEP_SLEEP:
1747 case STATE_SLEEP:
1748 case STATE_STANDBY:
1749 case STATE_AWAKE:
1750 retval = rt61pci_set_state(rt2x00dev, state);
1751 break;
1752 default:
1753 retval = -ENOTSUPP;
1754 break;
1755 }
1756
1757 if (unlikely(retval))
1758 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1759 state, retval);
1760
1761 return retval;
1762 }
1763
1764 /*
1765 * TX descriptor initialization
1766 */
1767 static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1768 struct sk_buff *skb,
1769 struct txentry_desc *txdesc)
1770 {
1771 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1772 __le32 *txd = skbdesc->desc;
1773 u32 word;
1774
1775 /*
1776 * Start writing the descriptor words.
1777 */
1778 rt2x00_desc_read(txd, 1, &word);
1779 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue);
1780 rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
1781 rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
1782 rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
1783 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
1784 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE,
1785 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
1786 rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1);
1787 rt2x00_desc_write(txd, 1, word);
1788
1789 rt2x00_desc_read(txd, 2, &word);
1790 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1791 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1792 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1793 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
1794 rt2x00_desc_write(txd, 2, word);
1795
1796 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
1797 _rt2x00_desc_write(txd, 3, skbdesc->iv);
1798 _rt2x00_desc_write(txd, 4, skbdesc->eiv);
1799 }
1800
1801 rt2x00_desc_read(txd, 5, &word);
1802 rt2x00_set_field32(&word, TXD_W5_PID_TYPE, skbdesc->entry->queue->qid);
1803 rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE,
1804 skbdesc->entry->entry_idx);
1805 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1806 TXPOWER_TO_DEV(rt2x00dev->tx_power));
1807 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1808 rt2x00_desc_write(txd, 5, word);
1809
1810 rt2x00_desc_read(txd, 6, &word);
1811 rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
1812 skbdesc->skb_dma);
1813 rt2x00_desc_write(txd, 6, word);
1814
1815 if (skbdesc->desc_len > TXINFO_SIZE) {
1816 rt2x00_desc_read(txd, 11, &word);
1817 rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0, skb->len);
1818 rt2x00_desc_write(txd, 11, word);
1819 }
1820
1821 rt2x00_desc_read(txd, 0, &word);
1822 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1823 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1824 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1825 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1826 rt2x00_set_field32(&word, TXD_W0_ACK,
1827 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1828 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1829 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1830 rt2x00_set_field32(&word, TXD_W0_OFDM,
1831 test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
1832 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1833 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1834 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1835 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC,
1836 test_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags));
1837 rt2x00_set_field32(&word, TXD_W0_KEY_TABLE,
1838 test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags));
1839 rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx);
1840 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skb->len);
1841 rt2x00_set_field32(&word, TXD_W0_BURST,
1842 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1843 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher);
1844 rt2x00_desc_write(txd, 0, word);
1845 }
1846
1847 /*
1848 * TX data initialization
1849 */
1850 static void rt61pci_write_beacon(struct queue_entry *entry)
1851 {
1852 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1853 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1854 unsigned int beacon_base;
1855 u32 reg;
1856
1857 /*
1858 * Disable beaconing while we are reloading the beacon data,
1859 * otherwise we might be sending out invalid data.
1860 */
1861 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1862 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1863 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1864 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1865 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1866
1867 /*
1868 * Write entire beacon with descriptor to register.
1869 */
1870 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
1871 rt2x00pci_register_multiwrite(rt2x00dev,
1872 beacon_base,
1873 skbdesc->desc, skbdesc->desc_len);
1874 rt2x00pci_register_multiwrite(rt2x00dev,
1875 beacon_base + skbdesc->desc_len,
1876 entry->skb->data, entry->skb->len);
1877
1878 /*
1879 * Clean up beacon skb.
1880 */
1881 dev_kfree_skb_any(entry->skb);
1882 entry->skb = NULL;
1883 }
1884
1885 static void rt61pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1886 const enum data_queue_qid queue)
1887 {
1888 u32 reg;
1889
1890 if (queue == QID_BEACON) {
1891 /*
1892 * For Wi-Fi faily generated beacons between participating
1893 * stations. Set TBTT phase adaptive adjustment step to 8us.
1894 */
1895 rt2x00pci_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1896
1897 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1898 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
1899 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1900 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
1901 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1902 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1903 }
1904 return;
1905 }
1906
1907 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1908 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC0, (queue == QID_AC_BE));
1909 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC1, (queue == QID_AC_BK));
1910 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC2, (queue == QID_AC_VI));
1911 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC3, (queue == QID_AC_VO));
1912 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1913 }
1914
1915 /*
1916 * RX control handlers
1917 */
1918 static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1919 {
1920 u8 offset = rt2x00dev->lna_gain;
1921 u8 lna;
1922
1923 lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1924 switch (lna) {
1925 case 3:
1926 offset += 90;
1927 break;
1928 case 2:
1929 offset += 74;
1930 break;
1931 case 1:
1932 offset += 64;
1933 break;
1934 default:
1935 return 0;
1936 }
1937
1938 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
1939 if (lna == 3 || lna == 2)
1940 offset += 10;
1941 }
1942
1943 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1944 }
1945
1946 static void rt61pci_fill_rxdone(struct queue_entry *entry,
1947 struct rxdone_entry_desc *rxdesc)
1948 {
1949 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1950 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1951 u32 word0;
1952 u32 word1;
1953
1954 rt2x00_desc_read(entry_priv->desc, 0, &word0);
1955 rt2x00_desc_read(entry_priv->desc, 1, &word1);
1956
1957 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1958 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1959
1960 if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
1961 rxdesc->cipher =
1962 rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG);
1963 rxdesc->cipher_status =
1964 rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR);
1965 }
1966
1967 if (rxdesc->cipher != CIPHER_NONE) {
1968 _rt2x00_desc_read(entry_priv->desc, 2, &rxdesc->iv);
1969 _rt2x00_desc_read(entry_priv->desc, 3, &rxdesc->eiv);
1970 _rt2x00_desc_read(entry_priv->desc, 4, &rxdesc->icv);
1971
1972 /*
1973 * Hardware has stripped IV/EIV data from 802.11 frame during
1974 * decryption. It has provided the data seperately but rt2x00lib
1975 * should decide if it should be reinserted.
1976 */
1977 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
1978
1979 /*
1980 * FIXME: Legacy driver indicates that the frame does
1981 * contain the Michael Mic. Unfortunately, in rt2x00
1982 * the MIC seems to be missing completely...
1983 */
1984 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
1985
1986 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
1987 rxdesc->flags |= RX_FLAG_DECRYPTED;
1988 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
1989 rxdesc->flags |= RX_FLAG_MMIC_ERROR;
1990 }
1991
1992 /*
1993 * Obtain the status about this packet.
1994 * When frame was received with an OFDM bitrate,
1995 * the signal is the PLCP value. If it was received with
1996 * a CCK bitrate the signal is the rate in 100kbit/s.
1997 */
1998 rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
1999 rxdesc->rssi = rt61pci_agc_to_rssi(rt2x00dev, word1);
2000 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
2001
2002 if (rt2x00_get_field32(word0, RXD_W0_OFDM))
2003 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
2004 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
2005 rxdesc->dev_flags |= RXDONE_MY_BSS;
2006 }
2007
2008 /*
2009 * Interrupt functions.
2010 */
2011 static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
2012 {
2013 struct data_queue *queue;
2014 struct queue_entry *entry;
2015 struct queue_entry *entry_done;
2016 struct queue_entry_priv_pci *entry_priv;
2017 struct txdone_entry_desc txdesc;
2018 u32 word;
2019 u32 reg;
2020 u32 old_reg;
2021 int type;
2022 int index;
2023
2024 /*
2025 * During each loop we will compare the freshly read
2026 * STA_CSR4 register value with the value read from
2027 * the previous loop. If the 2 values are equal then
2028 * we should stop processing because the chance it
2029 * quite big that the device has been unplugged and
2030 * we risk going into an endless loop.
2031 */
2032 old_reg = 0;
2033
2034 while (1) {
2035 rt2x00pci_register_read(rt2x00dev, STA_CSR4, &reg);
2036 if (!rt2x00_get_field32(reg, STA_CSR4_VALID))
2037 break;
2038
2039 if (old_reg == reg)
2040 break;
2041 old_reg = reg;
2042
2043 /*
2044 * Skip this entry when it contains an invalid
2045 * queue identication number.
2046 */
2047 type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE);
2048 queue = rt2x00queue_get_queue(rt2x00dev, type);
2049 if (unlikely(!queue))
2050 continue;
2051
2052 /*
2053 * Skip this entry when it contains an invalid
2054 * index number.
2055 */
2056 index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE);
2057 if (unlikely(index >= queue->limit))
2058 continue;
2059
2060 entry = &queue->entries[index];
2061 entry_priv = entry->priv_data;
2062 rt2x00_desc_read(entry_priv->desc, 0, &word);
2063
2064 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
2065 !rt2x00_get_field32(word, TXD_W0_VALID))
2066 return;
2067
2068 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
2069 while (entry != entry_done) {
2070 /* Catch up.
2071 * Just report any entries we missed as failed.
2072 */
2073 WARNING(rt2x00dev,
2074 "TX status report missed for entry %d\n",
2075 entry_done->entry_idx);
2076
2077 txdesc.flags = 0;
2078 __set_bit(TXDONE_UNKNOWN, &txdesc.flags);
2079 txdesc.retry = 0;
2080
2081 rt2x00lib_txdone(entry_done, &txdesc);
2082 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
2083 }
2084
2085 /*
2086 * Obtain the status about this packet.
2087 */
2088 txdesc.flags = 0;
2089 switch (rt2x00_get_field32(reg, STA_CSR4_TX_RESULT)) {
2090 case 0: /* Success, maybe with retry */
2091 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
2092 break;
2093 case 6: /* Failure, excessive retries */
2094 __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
2095 /* Don't break, this is a failed frame! */
2096 default: /* Failure */
2097 __set_bit(TXDONE_FAILURE, &txdesc.flags);
2098 }
2099 txdesc.retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT);
2100
2101 rt2x00lib_txdone(entry, &txdesc);
2102 }
2103 }
2104
2105 static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
2106 {
2107 struct rt2x00_dev *rt2x00dev = dev_instance;
2108 u32 reg_mcu;
2109 u32 reg;
2110
2111 /*
2112 * Get the interrupt sources & saved to local variable.
2113 * Write register value back to clear pending interrupts.
2114 */
2115 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg_mcu);
2116 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu);
2117
2118 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
2119 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
2120
2121 if (!reg && !reg_mcu)
2122 return IRQ_NONE;
2123
2124 if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
2125 return IRQ_HANDLED;
2126
2127 /*
2128 * Handle interrupts, walk through all bits
2129 * and run the tasks, the bits are checked in order of
2130 * priority.
2131 */
2132
2133 /*
2134 * 1 - Rx ring done interrupt.
2135 */
2136 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE))
2137 rt2x00pci_rxdone(rt2x00dev);
2138
2139 /*
2140 * 2 - Tx ring done interrupt.
2141 */
2142 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE))
2143 rt61pci_txdone(rt2x00dev);
2144
2145 /*
2146 * 3 - Handle MCU command done.
2147 */
2148 if (reg_mcu)
2149 rt2x00pci_register_write(rt2x00dev,
2150 M2H_CMD_DONE_CSR, 0xffffffff);
2151
2152 return IRQ_HANDLED;
2153 }
2154
2155 /*
2156 * Device probe functions.
2157 */
2158 static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2159 {
2160 struct eeprom_93cx6 eeprom;
2161 u32 reg;
2162 u16 word;
2163 u8 *mac;
2164 s8 value;
2165
2166 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
2167
2168 eeprom.data = rt2x00dev;
2169 eeprom.register_read = rt61pci_eepromregister_read;
2170 eeprom.register_write = rt61pci_eepromregister_write;
2171 eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ?
2172 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
2173 eeprom.reg_data_in = 0;
2174 eeprom.reg_data_out = 0;
2175 eeprom.reg_data_clock = 0;
2176 eeprom.reg_chip_select = 0;
2177
2178 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
2179 EEPROM_SIZE / sizeof(u16));
2180
2181 /*
2182 * Start validation of the data that has been read.
2183 */
2184 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2185 if (!is_valid_ether_addr(mac)) {
2186 DECLARE_MAC_BUF(macbuf);
2187
2188 random_ether_addr(mac);
2189 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
2190 }
2191
2192 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2193 if (word == 0xffff) {
2194 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
2195 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
2196 ANTENNA_B);
2197 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
2198 ANTENNA_B);
2199 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
2200 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
2201 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
2202 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5225);
2203 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2204 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2205 }
2206
2207 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2208 if (word == 0xffff) {
2209 rt2x00_set_field16(&word, EEPROM_NIC_ENABLE_DIVERSITY, 0);
2210 rt2x00_set_field16(&word, EEPROM_NIC_TX_DIVERSITY, 0);
2211 rt2x00_set_field16(&word, EEPROM_NIC_TX_RX_FIXED, 0);
2212 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2213 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2214 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2215 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2216 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2217 }
2218
2219 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
2220 if (word == 0xffff) {
2221 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
2222 LED_MODE_DEFAULT);
2223 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
2224 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
2225 }
2226
2227 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2228 if (word == 0xffff) {
2229 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2230 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
2231 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2232 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2233 }
2234
2235 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
2236 if (word == 0xffff) {
2237 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
2238 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
2239 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
2240 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
2241 } else {
2242 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
2243 if (value < -10 || value > 10)
2244 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
2245 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
2246 if (value < -10 || value > 10)
2247 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
2248 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
2249 }
2250
2251 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
2252 if (word == 0xffff) {
2253 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
2254 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
2255 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
2256 EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
2257 } else {
2258 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
2259 if (value < -10 || value > 10)
2260 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
2261 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
2262 if (value < -10 || value > 10)
2263 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
2264 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
2265 }
2266
2267 return 0;
2268 }
2269
2270 static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2271 {
2272 u32 reg;
2273 u16 value;
2274 u16 eeprom;
2275 u16 device;
2276
2277 /*
2278 * Read EEPROM word for configuration.
2279 */
2280 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2281
2282 /*
2283 * Identify RF chipset.
2284 * To determine the RT chip we have to read the
2285 * PCI header of the device.
2286 */
2287 pci_read_config_word(to_pci_dev(rt2x00dev->dev),
2288 PCI_CONFIG_HEADER_DEVICE, &device);
2289 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2290 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
2291 rt2x00_set_chip(rt2x00dev, device, value, reg);
2292
2293 if (!rt2x00_rf(&rt2x00dev->chip, RF5225) &&
2294 !rt2x00_rf(&rt2x00dev->chip, RF5325) &&
2295 !rt2x00_rf(&rt2x00dev->chip, RF2527) &&
2296 !rt2x00_rf(&rt2x00dev->chip, RF2529)) {
2297 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2298 return -ENODEV;
2299 }
2300
2301 /*
2302 * Determine number of antenna's.
2303 */
2304 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2)
2305 __set_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags);
2306
2307 /*
2308 * Identify default antenna configuration.
2309 */
2310 rt2x00dev->default_ant.tx =
2311 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
2312 rt2x00dev->default_ant.rx =
2313 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
2314
2315 /*
2316 * Read the Frame type.
2317 */
2318 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
2319 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
2320
2321 /*
2322 * Detect if this device has an hardware controlled radio.
2323 */
2324 #ifdef CONFIG_RT61PCI_RFKILL
2325 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
2326 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2327 #endif /* CONFIG_RT61PCI_RFKILL */
2328
2329 /*
2330 * Read frequency offset and RF programming sequence.
2331 */
2332 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2333 if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ))
2334 __set_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags);
2335
2336 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2337
2338 /*
2339 * Read external LNA informations.
2340 */
2341 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2342
2343 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2344 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2345 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2346 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2347
2348 /*
2349 * When working with a RF2529 chip without double antenna
2350 * the antenna settings should be gathered from the NIC
2351 * eeprom word.
2352 */
2353 if (rt2x00_rf(&rt2x00dev->chip, RF2529) &&
2354 !test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags)) {
2355 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_RX_FIXED)) {
2356 case 0:
2357 rt2x00dev->default_ant.tx = ANTENNA_B;
2358 rt2x00dev->default_ant.rx = ANTENNA_A;
2359 break;
2360 case 1:
2361 rt2x00dev->default_ant.tx = ANTENNA_B;
2362 rt2x00dev->default_ant.rx = ANTENNA_B;
2363 break;
2364 case 2:
2365 rt2x00dev->default_ant.tx = ANTENNA_A;
2366 rt2x00dev->default_ant.rx = ANTENNA_A;
2367 break;
2368 case 3:
2369 rt2x00dev->default_ant.tx = ANTENNA_A;
2370 rt2x00dev->default_ant.rx = ANTENNA_B;
2371 break;
2372 }
2373
2374 if (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY))
2375 rt2x00dev->default_ant.tx = ANTENNA_SW_DIVERSITY;
2376 if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY))
2377 rt2x00dev->default_ant.rx = ANTENNA_SW_DIVERSITY;
2378 }
2379
2380 /*
2381 * Store led settings, for correct led behaviour.
2382 * If the eeprom value is invalid,
2383 * switch to default led mode.
2384 */
2385 #ifdef CONFIG_RT61PCI_LEDS
2386 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
2387 value = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE);
2388
2389 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2390 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2391 if (value == LED_MODE_SIGNAL_STRENGTH)
2392 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
2393 LED_TYPE_QUALITY);
2394
2395 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
2396 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
2397 rt2x00_get_field16(eeprom,
2398 EEPROM_LED_POLARITY_GPIO_0));
2399 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
2400 rt2x00_get_field16(eeprom,
2401 EEPROM_LED_POLARITY_GPIO_1));
2402 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
2403 rt2x00_get_field16(eeprom,
2404 EEPROM_LED_POLARITY_GPIO_2));
2405 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
2406 rt2x00_get_field16(eeprom,
2407 EEPROM_LED_POLARITY_GPIO_3));
2408 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
2409 rt2x00_get_field16(eeprom,
2410 EEPROM_LED_POLARITY_GPIO_4));
2411 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
2412 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
2413 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
2414 rt2x00_get_field16(eeprom,
2415 EEPROM_LED_POLARITY_RDY_G));
2416 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
2417 rt2x00_get_field16(eeprom,
2418 EEPROM_LED_POLARITY_RDY_A));
2419 #endif /* CONFIG_RT61PCI_LEDS */
2420
2421 return 0;
2422 }
2423
2424 /*
2425 * RF value list for RF5225 & RF5325
2426 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled
2427 */
2428 static const struct rf_channel rf_vals_noseq[] = {
2429 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2430 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2431 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2432 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2433 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2434 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2435 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2436 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2437 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2438 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2439 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2440 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2441 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2442 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2443
2444 /* 802.11 UNI / HyperLan 2 */
2445 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2446 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2447 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2448 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2449 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2450 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2451 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2452 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2453
2454 /* 802.11 HyperLan 2 */
2455 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2456 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2457 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2458 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2459 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2460 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2461 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2462 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2463 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2464 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2465
2466 /* 802.11 UNII */
2467 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2468 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2469 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2470 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2471 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2472 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2473
2474 /* MMAC(Japan)J52 ch 34,38,42,46 */
2475 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2476 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2477 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2478 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2479 };
2480
2481 /*
2482 * RF value list for RF5225 & RF5325
2483 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled
2484 */
2485 static const struct rf_channel rf_vals_seq[] = {
2486 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2487 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2488 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2489 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2490 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2491 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2492 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2493 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2494 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2495 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2496 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2497 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2498 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2499 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2500
2501 /* 802.11 UNI / HyperLan 2 */
2502 { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 },
2503 { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 },
2504 { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b },
2505 { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b },
2506 { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 },
2507 { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 },
2508 { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 },
2509 { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b },
2510
2511 /* 802.11 HyperLan 2 */
2512 { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 },
2513 { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 },
2514 { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 },
2515 { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 },
2516 { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 },
2517 { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 },
2518 { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b },
2519 { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b },
2520 { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 },
2521 { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 },
2522
2523 /* 802.11 UNII */
2524 { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 },
2525 { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b },
2526 { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b },
2527 { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 },
2528 { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 },
2529 { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 },
2530
2531 /* MMAC(Japan)J52 ch 34,38,42,46 */
2532 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b },
2533 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 },
2534 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b },
2535 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 },
2536 };
2537
2538 static int rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2539 {
2540 struct hw_mode_spec *spec = &rt2x00dev->spec;
2541 struct channel_info *info;
2542 char *tx_power;
2543 unsigned int i;
2544
2545 /*
2546 * Initialize all hw fields.
2547 */
2548 rt2x00dev->hw->flags =
2549 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2550 IEEE80211_HW_SIGNAL_DBM;
2551 rt2x00dev->hw->extra_tx_headroom = 0;
2552
2553 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2554 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2555 rt2x00_eeprom_addr(rt2x00dev,
2556 EEPROM_MAC_ADDR_0));
2557
2558 /*
2559 * Initialize hw_mode information.
2560 */
2561 spec->supported_bands = SUPPORT_BAND_2GHZ;
2562 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2563
2564 if (!test_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags)) {
2565 spec->num_channels = 14;
2566 spec->channels = rf_vals_noseq;
2567 } else {
2568 spec->num_channels = 14;
2569 spec->channels = rf_vals_seq;
2570 }
2571
2572 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
2573 rt2x00_rf(&rt2x00dev->chip, RF5325)) {
2574 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2575 spec->num_channels = ARRAY_SIZE(rf_vals_seq);
2576 }
2577
2578 /*
2579 * Create channel information array
2580 */
2581 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2582 if (!info)
2583 return -ENOMEM;
2584
2585 spec->channels_info = info;
2586
2587 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2588 for (i = 0; i < 14; i++)
2589 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2590
2591 if (spec->num_channels > 14) {
2592 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2593 for (i = 14; i < spec->num_channels; i++)
2594 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2595 }
2596
2597 return 0;
2598 }
2599
2600 static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2601 {
2602 int retval;
2603
2604 /*
2605 * Allocate eeprom data.
2606 */
2607 retval = rt61pci_validate_eeprom(rt2x00dev);
2608 if (retval)
2609 return retval;
2610
2611 retval = rt61pci_init_eeprom(rt2x00dev);
2612 if (retval)
2613 return retval;
2614
2615 /*
2616 * Initialize hw specifications.
2617 */
2618 retval = rt61pci_probe_hw_mode(rt2x00dev);
2619 if (retval)
2620 return retval;
2621
2622 /*
2623 * This device requires firmware and DMA mapped skbs.
2624 */
2625 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2626 __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
2627 if (!modparam_nohwcrypt)
2628 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
2629
2630 /*
2631 * Set the rssi offset.
2632 */
2633 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2634
2635 return 0;
2636 }
2637
2638 /*
2639 * IEEE80211 stack callback functions.
2640 */
2641 static int rt61pci_set_retry_limit(struct ieee80211_hw *hw,
2642 u32 short_retry, u32 long_retry)
2643 {
2644 struct rt2x00_dev *rt2x00dev = hw->priv;
2645 u32 reg;
2646
2647 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
2648 rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT, long_retry);
2649 rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT, short_retry);
2650 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
2651
2652 return 0;
2653 }
2654
2655 static u64 rt61pci_get_tsf(struct ieee80211_hw *hw)
2656 {
2657 struct rt2x00_dev *rt2x00dev = hw->priv;
2658 u64 tsf;
2659 u32 reg;
2660
2661 rt2x00pci_register_read(rt2x00dev, TXRX_CSR13, &reg);
2662 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2663 rt2x00pci_register_read(rt2x00dev, TXRX_CSR12, &reg);
2664 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2665
2666 return tsf;
2667 }
2668
2669 static const struct ieee80211_ops rt61pci_mac80211_ops = {
2670 .tx = rt2x00mac_tx,
2671 .start = rt2x00mac_start,
2672 .stop = rt2x00mac_stop,
2673 .add_interface = rt2x00mac_add_interface,
2674 .remove_interface = rt2x00mac_remove_interface,
2675 .config = rt2x00mac_config,
2676 .config_interface = rt2x00mac_config_interface,
2677 .configure_filter = rt2x00mac_configure_filter,
2678 .set_key = rt2x00mac_set_key,
2679 .get_stats = rt2x00mac_get_stats,
2680 .set_retry_limit = rt61pci_set_retry_limit,
2681 .bss_info_changed = rt2x00mac_bss_info_changed,
2682 .conf_tx = rt2x00mac_conf_tx,
2683 .get_tx_stats = rt2x00mac_get_tx_stats,
2684 .get_tsf = rt61pci_get_tsf,
2685 };
2686
2687 static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
2688 .irq_handler = rt61pci_interrupt,
2689 .probe_hw = rt61pci_probe_hw,
2690 .get_firmware_name = rt61pci_get_firmware_name,
2691 .get_firmware_crc = rt61pci_get_firmware_crc,
2692 .load_firmware = rt61pci_load_firmware,
2693 .initialize = rt2x00pci_initialize,
2694 .uninitialize = rt2x00pci_uninitialize,
2695 .init_rxentry = rt61pci_init_rxentry,
2696 .init_txentry = rt61pci_init_txentry,
2697 .set_device_state = rt61pci_set_device_state,
2698 .rfkill_poll = rt61pci_rfkill_poll,
2699 .link_stats = rt61pci_link_stats,
2700 .reset_tuner = rt61pci_reset_tuner,
2701 .link_tuner = rt61pci_link_tuner,
2702 .write_tx_desc = rt61pci_write_tx_desc,
2703 .write_tx_data = rt2x00pci_write_tx_data,
2704 .write_beacon = rt61pci_write_beacon,
2705 .kick_tx_queue = rt61pci_kick_tx_queue,
2706 .fill_rxdone = rt61pci_fill_rxdone,
2707 .config_shared_key = rt61pci_config_shared_key,
2708 .config_pairwise_key = rt61pci_config_pairwise_key,
2709 .config_filter = rt61pci_config_filter,
2710 .config_intf = rt61pci_config_intf,
2711 .config_erp = rt61pci_config_erp,
2712 .config = rt61pci_config,
2713 };
2714
2715 static const struct data_queue_desc rt61pci_queue_rx = {
2716 .entry_num = RX_ENTRIES,
2717 .data_size = DATA_FRAME_SIZE,
2718 .desc_size = RXD_DESC_SIZE,
2719 .priv_size = sizeof(struct queue_entry_priv_pci),
2720 };
2721
2722 static const struct data_queue_desc rt61pci_queue_tx = {
2723 .entry_num = TX_ENTRIES,
2724 .data_size = DATA_FRAME_SIZE,
2725 .desc_size = TXD_DESC_SIZE,
2726 .priv_size = sizeof(struct queue_entry_priv_pci),
2727 };
2728
2729 static const struct data_queue_desc rt61pci_queue_bcn = {
2730 .entry_num = 4 * BEACON_ENTRIES,
2731 .data_size = 0, /* No DMA required for beacons */
2732 .desc_size = TXINFO_SIZE,
2733 .priv_size = sizeof(struct queue_entry_priv_pci),
2734 };
2735
2736 static const struct rt2x00_ops rt61pci_ops = {
2737 .name = KBUILD_MODNAME,
2738 .max_sta_intf = 1,
2739 .max_ap_intf = 4,
2740 .eeprom_size = EEPROM_SIZE,
2741 .rf_size = RF_SIZE,
2742 .tx_queues = NUM_TX_QUEUES,
2743 .rx = &rt61pci_queue_rx,
2744 .tx = &rt61pci_queue_tx,
2745 .bcn = &rt61pci_queue_bcn,
2746 .lib = &rt61pci_rt2x00_ops,
2747 .hw = &rt61pci_mac80211_ops,
2748 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2749 .debugfs = &rt61pci_rt2x00debug,
2750 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2751 };
2752
2753 /*
2754 * RT61pci module information.
2755 */
2756 static struct pci_device_id rt61pci_device_table[] = {
2757 /* RT2561s */
2758 { PCI_DEVICE(0x1814, 0x0301), PCI_DEVICE_DATA(&rt61pci_ops) },
2759 /* RT2561 v2 */
2760 { PCI_DEVICE(0x1814, 0x0302), PCI_DEVICE_DATA(&rt61pci_ops) },
2761 /* RT2661 */
2762 { PCI_DEVICE(0x1814, 0x0401), PCI_DEVICE_DATA(&rt61pci_ops) },
2763 { 0, }
2764 };
2765
2766 MODULE_AUTHOR(DRV_PROJECT);
2767 MODULE_VERSION(DRV_VERSION);
2768 MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver.");
2769 MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 "
2770 "PCI & PCMCIA chipset based cards");
2771 MODULE_DEVICE_TABLE(pci, rt61pci_device_table);
2772 MODULE_FIRMWARE(FIRMWARE_RT2561);
2773 MODULE_FIRMWARE(FIRMWARE_RT2561s);
2774 MODULE_FIRMWARE(FIRMWARE_RT2661);
2775 MODULE_LICENSE("GPL");
2776
2777 static struct pci_driver rt61pci_driver = {
2778 .name = KBUILD_MODNAME,
2779 .id_table = rt61pci_device_table,
2780 .probe = rt2x00pci_probe,
2781 .remove = __devexit_p(rt2x00pci_remove),
2782 .suspend = rt2x00pci_suspend,
2783 .resume = rt2x00pci_resume,
2784 };
2785
2786 static int __init rt61pci_init(void)
2787 {
2788 return pci_register_driver(&rt61pci_driver);
2789 }
2790
2791 static void __exit rt61pci_exit(void)
2792 {
2793 pci_unregister_driver(&rt61pci_driver);
2794 }
2795
2796 module_init(rt61pci_init);
2797 module_exit(rt61pci_exit);
Linux kernel - Deliverables
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