2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
3 <http://rt2x00.serialmonkey.com>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 Abstract: rt61pci device specific routines.
24 Supported chipsets: RT2561, RT2561s, RT2661.
27 #include <linux/crc-itu-t.h>
28 #include <linux/delay.h>
29 #include <linux/etherdevice.h>
30 #include <linux/init.h>
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/slab.h>
34 #include <linux/pci.h>
35 #include <linux/eeprom_93cx6.h>
38 #include "rt2x00pci.h"
42 * Allow hardware encryption to be disabled.
44 static int modparam_nohwcrypt
= 0;
45 module_param_named(nohwcrypt
, modparam_nohwcrypt
, bool, S_IRUGO
);
46 MODULE_PARM_DESC(nohwcrypt
, "Disable hardware encryption.");
50 * BBP and RF register require indirect register access,
51 * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
55 * between each attempt. When the busy bit is still set at that time,
56 * the access attempt is considered to have failed,
57 * and we will print an error.
59 #define WAIT_FOR_BBP(__dev, __reg) \
60 rt2x00pci_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg))
61 #define WAIT_FOR_RF(__dev, __reg) \
62 rt2x00pci_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg))
63 #define WAIT_FOR_MCU(__dev, __reg) \
64 rt2x00pci_regbusy_read((__dev), H2M_MAILBOX_CSR, \
65 H2M_MAILBOX_CSR_OWNER, (__reg))
67 static void rt61pci_bbp_write(struct rt2x00_dev
*rt2x00dev
,
68 const unsigned int word
, const u8 value
)
72 mutex_lock(&rt2x00dev
->csr_mutex
);
75 * Wait until the BBP becomes available, afterwards we
76 * can safely write the new data into the register.
78 if (WAIT_FOR_BBP(rt2x00dev
, ®
)) {
80 rt2x00_set_field32(®
, PHY_CSR3_VALUE
, value
);
81 rt2x00_set_field32(®
, PHY_CSR3_REGNUM
, word
);
82 rt2x00_set_field32(®
, PHY_CSR3_BUSY
, 1);
83 rt2x00_set_field32(®
, PHY_CSR3_READ_CONTROL
, 0);
85 rt2x00pci_register_write(rt2x00dev
, PHY_CSR3
, reg
);
88 mutex_unlock(&rt2x00dev
->csr_mutex
);
91 static void rt61pci_bbp_read(struct rt2x00_dev
*rt2x00dev
,
92 const unsigned int word
, u8
*value
)
96 mutex_lock(&rt2x00dev
->csr_mutex
);
99 * Wait until the BBP becomes available, afterwards we
100 * can safely write the read request into the register.
101 * After the data has been written, we wait until hardware
102 * returns the correct value, if at any time the register
103 * doesn't become available in time, reg will be 0xffffffff
104 * which means we return 0xff to the caller.
106 if (WAIT_FOR_BBP(rt2x00dev
, ®
)) {
108 rt2x00_set_field32(®
, PHY_CSR3_REGNUM
, word
);
109 rt2x00_set_field32(®
, PHY_CSR3_BUSY
, 1);
110 rt2x00_set_field32(®
, PHY_CSR3_READ_CONTROL
, 1);
112 rt2x00pci_register_write(rt2x00dev
, PHY_CSR3
, reg
);
114 WAIT_FOR_BBP(rt2x00dev
, ®
);
117 *value
= rt2x00_get_field32(reg
, PHY_CSR3_VALUE
);
119 mutex_unlock(&rt2x00dev
->csr_mutex
);
122 static void rt61pci_rf_write(struct rt2x00_dev
*rt2x00dev
,
123 const unsigned int word
, const u32 value
)
127 mutex_lock(&rt2x00dev
->csr_mutex
);
130 * Wait until the RF becomes available, afterwards we
131 * can safely write the new data into the register.
133 if (WAIT_FOR_RF(rt2x00dev
, ®
)) {
135 rt2x00_set_field32(®
, PHY_CSR4_VALUE
, value
);
136 rt2x00_set_field32(®
, PHY_CSR4_NUMBER_OF_BITS
, 21);
137 rt2x00_set_field32(®
, PHY_CSR4_IF_SELECT
, 0);
138 rt2x00_set_field32(®
, PHY_CSR4_BUSY
, 1);
140 rt2x00pci_register_write(rt2x00dev
, PHY_CSR4
, reg
);
141 rt2x00_rf_write(rt2x00dev
, word
, value
);
144 mutex_unlock(&rt2x00dev
->csr_mutex
);
147 static void rt61pci_mcu_request(struct rt2x00_dev
*rt2x00dev
,
148 const u8 command
, const u8 token
,
149 const u8 arg0
, const u8 arg1
)
153 mutex_lock(&rt2x00dev
->csr_mutex
);
156 * Wait until the MCU becomes available, afterwards we
157 * can safely write the new data into the register.
159 if (WAIT_FOR_MCU(rt2x00dev
, ®
)) {
160 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_OWNER
, 1);
161 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_CMD_TOKEN
, token
);
162 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_ARG0
, arg0
);
163 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_ARG1
, arg1
);
164 rt2x00pci_register_write(rt2x00dev
, H2M_MAILBOX_CSR
, reg
);
166 rt2x00pci_register_read(rt2x00dev
, HOST_CMD_CSR
, ®
);
167 rt2x00_set_field32(®
, HOST_CMD_CSR_HOST_COMMAND
, command
);
168 rt2x00_set_field32(®
, HOST_CMD_CSR_INTERRUPT_MCU
, 1);
169 rt2x00pci_register_write(rt2x00dev
, HOST_CMD_CSR
, reg
);
172 mutex_unlock(&rt2x00dev
->csr_mutex
);
176 static void rt61pci_eepromregister_read(struct eeprom_93cx6
*eeprom
)
178 struct rt2x00_dev
*rt2x00dev
= eeprom
->data
;
181 rt2x00pci_register_read(rt2x00dev
, E2PROM_CSR
, ®
);
183 eeprom
->reg_data_in
= !!rt2x00_get_field32(reg
, E2PROM_CSR_DATA_IN
);
184 eeprom
->reg_data_out
= !!rt2x00_get_field32(reg
, E2PROM_CSR_DATA_OUT
);
185 eeprom
->reg_data_clock
=
186 !!rt2x00_get_field32(reg
, E2PROM_CSR_DATA_CLOCK
);
187 eeprom
->reg_chip_select
=
188 !!rt2x00_get_field32(reg
, E2PROM_CSR_CHIP_SELECT
);
191 static void rt61pci_eepromregister_write(struct eeprom_93cx6
*eeprom
)
193 struct rt2x00_dev
*rt2x00dev
= eeprom
->data
;
196 rt2x00_set_field32(®
, E2PROM_CSR_DATA_IN
, !!eeprom
->reg_data_in
);
197 rt2x00_set_field32(®
, E2PROM_CSR_DATA_OUT
, !!eeprom
->reg_data_out
);
198 rt2x00_set_field32(®
, E2PROM_CSR_DATA_CLOCK
,
199 !!eeprom
->reg_data_clock
);
200 rt2x00_set_field32(®
, E2PROM_CSR_CHIP_SELECT
,
201 !!eeprom
->reg_chip_select
);
203 rt2x00pci_register_write(rt2x00dev
, E2PROM_CSR
, reg
);
206 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
207 static const struct rt2x00debug rt61pci_rt2x00debug
= {
208 .owner
= THIS_MODULE
,
210 .read
= rt2x00pci_register_read
,
211 .write
= rt2x00pci_register_write
,
212 .flags
= RT2X00DEBUGFS_OFFSET
,
213 .word_base
= CSR_REG_BASE
,
214 .word_size
= sizeof(u32
),
215 .word_count
= CSR_REG_SIZE
/ sizeof(u32
),
218 .read
= rt2x00_eeprom_read
,
219 .write
= rt2x00_eeprom_write
,
220 .word_base
= EEPROM_BASE
,
221 .word_size
= sizeof(u16
),
222 .word_count
= EEPROM_SIZE
/ sizeof(u16
),
225 .read
= rt61pci_bbp_read
,
226 .write
= rt61pci_bbp_write
,
227 .word_base
= BBP_BASE
,
228 .word_size
= sizeof(u8
),
229 .word_count
= BBP_SIZE
/ sizeof(u8
),
232 .read
= rt2x00_rf_read
,
233 .write
= rt61pci_rf_write
,
234 .word_base
= RF_BASE
,
235 .word_size
= sizeof(u32
),
236 .word_count
= RF_SIZE
/ sizeof(u32
),
239 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
241 static int rt61pci_rfkill_poll(struct rt2x00_dev
*rt2x00dev
)
245 rt2x00pci_register_read(rt2x00dev
, MAC_CSR13
, ®
);
246 return rt2x00_get_field32(reg
, MAC_CSR13_BIT5
);
249 #ifdef CONFIG_RT2X00_LIB_LEDS
250 static void rt61pci_brightness_set(struct led_classdev
*led_cdev
,
251 enum led_brightness brightness
)
253 struct rt2x00_led
*led
=
254 container_of(led_cdev
, struct rt2x00_led
, led_dev
);
255 unsigned int enabled
= brightness
!= LED_OFF
;
256 unsigned int a_mode
=
257 (enabled
&& led
->rt2x00dev
->curr_band
== IEEE80211_BAND_5GHZ
);
258 unsigned int bg_mode
=
259 (enabled
&& led
->rt2x00dev
->curr_band
== IEEE80211_BAND_2GHZ
);
261 if (led
->type
== LED_TYPE_RADIO
) {
262 rt2x00_set_field16(&led
->rt2x00dev
->led_mcu_reg
,
263 MCU_LEDCS_RADIO_STATUS
, enabled
);
265 rt61pci_mcu_request(led
->rt2x00dev
, MCU_LED
, 0xff,
266 (led
->rt2x00dev
->led_mcu_reg
& 0xff),
267 ((led
->rt2x00dev
->led_mcu_reg
>> 8)));
268 } else if (led
->type
== LED_TYPE_ASSOC
) {
269 rt2x00_set_field16(&led
->rt2x00dev
->led_mcu_reg
,
270 MCU_LEDCS_LINK_BG_STATUS
, bg_mode
);
271 rt2x00_set_field16(&led
->rt2x00dev
->led_mcu_reg
,
272 MCU_LEDCS_LINK_A_STATUS
, a_mode
);
274 rt61pci_mcu_request(led
->rt2x00dev
, MCU_LED
, 0xff,
275 (led
->rt2x00dev
->led_mcu_reg
& 0xff),
276 ((led
->rt2x00dev
->led_mcu_reg
>> 8)));
277 } else if (led
->type
== LED_TYPE_QUALITY
) {
279 * The brightness is divided into 6 levels (0 - 5),
280 * this means we need to convert the brightness
281 * argument into the matching level within that range.
283 rt61pci_mcu_request(led
->rt2x00dev
, MCU_LED_STRENGTH
, 0xff,
284 brightness
/ (LED_FULL
/ 6), 0);
288 static int rt61pci_blink_set(struct led_classdev
*led_cdev
,
289 unsigned long *delay_on
,
290 unsigned long *delay_off
)
292 struct rt2x00_led
*led
=
293 container_of(led_cdev
, struct rt2x00_led
, led_dev
);
296 rt2x00pci_register_read(led
->rt2x00dev
, MAC_CSR14
, ®
);
297 rt2x00_set_field32(®
, MAC_CSR14_ON_PERIOD
, *delay_on
);
298 rt2x00_set_field32(®
, MAC_CSR14_OFF_PERIOD
, *delay_off
);
299 rt2x00pci_register_write(led
->rt2x00dev
, MAC_CSR14
, reg
);
304 static void rt61pci_init_led(struct rt2x00_dev
*rt2x00dev
,
305 struct rt2x00_led
*led
,
308 led
->rt2x00dev
= rt2x00dev
;
310 led
->led_dev
.brightness_set
= rt61pci_brightness_set
;
311 led
->led_dev
.blink_set
= rt61pci_blink_set
;
312 led
->flags
= LED_INITIALIZED
;
314 #endif /* CONFIG_RT2X00_LIB_LEDS */
317 * Configuration handlers.
319 static int rt61pci_config_shared_key(struct rt2x00_dev
*rt2x00dev
,
320 struct rt2x00lib_crypto
*crypto
,
321 struct ieee80211_key_conf
*key
)
323 struct hw_key_entry key_entry
;
324 struct rt2x00_field32 field
;
328 if (crypto
->cmd
== SET_KEY
) {
330 * rt2x00lib can't determine the correct free
331 * key_idx for shared keys. We have 1 register
332 * with key valid bits. The goal is simple, read
333 * the register, if that is full we have no slots
335 * Note that each BSS is allowed to have up to 4
336 * shared keys, so put a mask over the allowed
339 mask
= (0xf << crypto
->bssidx
);
341 rt2x00pci_register_read(rt2x00dev
, SEC_CSR0
, ®
);
344 if (reg
&& reg
== mask
)
347 key
->hw_key_idx
+= reg
? ffz(reg
) : 0;
350 * Upload key to hardware
352 memcpy(key_entry
.key
, crypto
->key
,
353 sizeof(key_entry
.key
));
354 memcpy(key_entry
.tx_mic
, crypto
->tx_mic
,
355 sizeof(key_entry
.tx_mic
));
356 memcpy(key_entry
.rx_mic
, crypto
->rx_mic
,
357 sizeof(key_entry
.rx_mic
));
359 reg
= SHARED_KEY_ENTRY(key
->hw_key_idx
);
360 rt2x00pci_register_multiwrite(rt2x00dev
, reg
,
361 &key_entry
, sizeof(key_entry
));
364 * The cipher types are stored over 2 registers.
365 * bssidx 0 and 1 keys are stored in SEC_CSR1 and
366 * bssidx 1 and 2 keys are stored in SEC_CSR5.
367 * Using the correct defines correctly will cause overhead,
368 * so just calculate the correct offset.
370 if (key
->hw_key_idx
< 8) {
371 field
.bit_offset
= (3 * key
->hw_key_idx
);
372 field
.bit_mask
= 0x7 << field
.bit_offset
;
374 rt2x00pci_register_read(rt2x00dev
, SEC_CSR1
, ®
);
375 rt2x00_set_field32(®
, field
, crypto
->cipher
);
376 rt2x00pci_register_write(rt2x00dev
, SEC_CSR1
, reg
);
378 field
.bit_offset
= (3 * (key
->hw_key_idx
- 8));
379 field
.bit_mask
= 0x7 << field
.bit_offset
;
381 rt2x00pci_register_read(rt2x00dev
, SEC_CSR5
, ®
);
382 rt2x00_set_field32(®
, field
, crypto
->cipher
);
383 rt2x00pci_register_write(rt2x00dev
, SEC_CSR5
, reg
);
387 * The driver does not support the IV/EIV generation
388 * in hardware. However it doesn't support the IV/EIV
389 * inside the ieee80211 frame either, but requires it
390 * to be provided separately for the descriptor.
391 * rt2x00lib will cut the IV/EIV data out of all frames
392 * given to us by mac80211, but we must tell mac80211
393 * to generate the IV/EIV data.
395 key
->flags
|= IEEE80211_KEY_FLAG_GENERATE_IV
;
399 * SEC_CSR0 contains only single-bit fields to indicate
400 * a particular key is valid. Because using the FIELD32()
401 * defines directly will cause a lot of overhead, we use
402 * a calculation to determine the correct bit directly.
404 mask
= 1 << key
->hw_key_idx
;
406 rt2x00pci_register_read(rt2x00dev
, SEC_CSR0
, ®
);
407 if (crypto
->cmd
== SET_KEY
)
409 else if (crypto
->cmd
== DISABLE_KEY
)
411 rt2x00pci_register_write(rt2x00dev
, SEC_CSR0
, reg
);
416 static int rt61pci_config_pairwise_key(struct rt2x00_dev
*rt2x00dev
,
417 struct rt2x00lib_crypto
*crypto
,
418 struct ieee80211_key_conf
*key
)
420 struct hw_pairwise_ta_entry addr_entry
;
421 struct hw_key_entry key_entry
;
425 if (crypto
->cmd
== SET_KEY
) {
427 * rt2x00lib can't determine the correct free
428 * key_idx for pairwise keys. We have 2 registers
429 * with key valid bits. The goal is simple: read
430 * the first register. If that is full, move to
432 * When both registers are full, we drop the key.
433 * Otherwise, we use the first invalid entry.
435 rt2x00pci_register_read(rt2x00dev
, SEC_CSR2
, ®
);
436 if (reg
&& reg
== ~0) {
437 key
->hw_key_idx
= 32;
438 rt2x00pci_register_read(rt2x00dev
, SEC_CSR3
, ®
);
439 if (reg
&& reg
== ~0)
443 key
->hw_key_idx
+= reg
? ffz(reg
) : 0;
446 * Upload key to hardware
448 memcpy(key_entry
.key
, crypto
->key
,
449 sizeof(key_entry
.key
));
450 memcpy(key_entry
.tx_mic
, crypto
->tx_mic
,
451 sizeof(key_entry
.tx_mic
));
452 memcpy(key_entry
.rx_mic
, crypto
->rx_mic
,
453 sizeof(key_entry
.rx_mic
));
455 memset(&addr_entry
, 0, sizeof(addr_entry
));
456 memcpy(&addr_entry
, crypto
->address
, ETH_ALEN
);
457 addr_entry
.cipher
= crypto
->cipher
;
459 reg
= PAIRWISE_KEY_ENTRY(key
->hw_key_idx
);
460 rt2x00pci_register_multiwrite(rt2x00dev
, reg
,
461 &key_entry
, sizeof(key_entry
));
463 reg
= PAIRWISE_TA_ENTRY(key
->hw_key_idx
);
464 rt2x00pci_register_multiwrite(rt2x00dev
, reg
,
465 &addr_entry
, sizeof(addr_entry
));
468 * Enable pairwise lookup table for given BSS idx.
469 * Without this, received frames will not be decrypted
472 rt2x00pci_register_read(rt2x00dev
, SEC_CSR4
, ®
);
473 reg
|= (1 << crypto
->bssidx
);
474 rt2x00pci_register_write(rt2x00dev
, SEC_CSR4
, reg
);
477 * The driver does not support the IV/EIV generation
478 * in hardware. However it doesn't support the IV/EIV
479 * inside the ieee80211 frame either, but requires it
480 * to be provided separately for the descriptor.
481 * rt2x00lib will cut the IV/EIV data out of all frames
482 * given to us by mac80211, but we must tell mac80211
483 * to generate the IV/EIV data.
485 key
->flags
|= IEEE80211_KEY_FLAG_GENERATE_IV
;
489 * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate
490 * a particular key is valid. Because using the FIELD32()
491 * defines directly will cause a lot of overhead, we use
492 * a calculation to determine the correct bit directly.
494 if (key
->hw_key_idx
< 32) {
495 mask
= 1 << key
->hw_key_idx
;
497 rt2x00pci_register_read(rt2x00dev
, SEC_CSR2
, ®
);
498 if (crypto
->cmd
== SET_KEY
)
500 else if (crypto
->cmd
== DISABLE_KEY
)
502 rt2x00pci_register_write(rt2x00dev
, SEC_CSR2
, reg
);
504 mask
= 1 << (key
->hw_key_idx
- 32);
506 rt2x00pci_register_read(rt2x00dev
, SEC_CSR3
, ®
);
507 if (crypto
->cmd
== SET_KEY
)
509 else if (crypto
->cmd
== DISABLE_KEY
)
511 rt2x00pci_register_write(rt2x00dev
, SEC_CSR3
, reg
);
517 static void rt61pci_config_filter(struct rt2x00_dev
*rt2x00dev
,
518 const unsigned int filter_flags
)
523 * Start configuration steps.
524 * Note that the version error will always be dropped
525 * and broadcast frames will always be accepted since
526 * there is no filter for it at this time.
528 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR0
, ®
);
529 rt2x00_set_field32(®
, TXRX_CSR0_DROP_CRC
,
530 !(filter_flags
& FIF_FCSFAIL
));
531 rt2x00_set_field32(®
, TXRX_CSR0_DROP_PHYSICAL
,
532 !(filter_flags
& FIF_PLCPFAIL
));
533 rt2x00_set_field32(®
, TXRX_CSR0_DROP_CONTROL
,
534 !(filter_flags
& (FIF_CONTROL
| FIF_PSPOLL
)));
535 rt2x00_set_field32(®
, TXRX_CSR0_DROP_NOT_TO_ME
,
536 !(filter_flags
& FIF_PROMISC_IN_BSS
));
537 rt2x00_set_field32(®
, TXRX_CSR0_DROP_TO_DS
,
538 !(filter_flags
& FIF_PROMISC_IN_BSS
) &&
539 !rt2x00dev
->intf_ap_count
);
540 rt2x00_set_field32(®
, TXRX_CSR0_DROP_VERSION_ERROR
, 1);
541 rt2x00_set_field32(®
, TXRX_CSR0_DROP_MULTICAST
,
542 !(filter_flags
& FIF_ALLMULTI
));
543 rt2x00_set_field32(®
, TXRX_CSR0_DROP_BROADCAST
, 0);
544 rt2x00_set_field32(®
, TXRX_CSR0_DROP_ACK_CTS
,
545 !(filter_flags
& FIF_CONTROL
));
546 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR0
, reg
);
549 static void rt61pci_config_intf(struct rt2x00_dev
*rt2x00dev
,
550 struct rt2x00_intf
*intf
,
551 struct rt2x00intf_conf
*conf
,
552 const unsigned int flags
)
556 if (flags
& CONFIG_UPDATE_TYPE
) {
558 * Enable synchronisation.
560 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR9
, ®
);
561 rt2x00_set_field32(®
, TXRX_CSR9_TSF_SYNC
, conf
->sync
);
562 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR9
, reg
);
565 if (flags
& CONFIG_UPDATE_MAC
) {
566 reg
= le32_to_cpu(conf
->mac
[1]);
567 rt2x00_set_field32(®
, MAC_CSR3_UNICAST_TO_ME_MASK
, 0xff);
568 conf
->mac
[1] = cpu_to_le32(reg
);
570 rt2x00pci_register_multiwrite(rt2x00dev
, MAC_CSR2
,
571 conf
->mac
, sizeof(conf
->mac
));
574 if (flags
& CONFIG_UPDATE_BSSID
) {
575 reg
= le32_to_cpu(conf
->bssid
[1]);
576 rt2x00_set_field32(®
, MAC_CSR5_BSS_ID_MASK
, 3);
577 conf
->bssid
[1] = cpu_to_le32(reg
);
579 rt2x00pci_register_multiwrite(rt2x00dev
, MAC_CSR4
,
580 conf
->bssid
, sizeof(conf
->bssid
));
584 static void rt61pci_config_erp(struct rt2x00_dev
*rt2x00dev
,
585 struct rt2x00lib_erp
*erp
,
590 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR0
, ®
);
591 rt2x00_set_field32(®
, TXRX_CSR0_RX_ACK_TIMEOUT
, 0x32);
592 rt2x00_set_field32(®
, TXRX_CSR0_TSF_OFFSET
, IEEE80211_HEADER
);
593 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR0
, reg
);
595 if (changed
& BSS_CHANGED_ERP_PREAMBLE
) {
596 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR4
, ®
);
597 rt2x00_set_field32(®
, TXRX_CSR4_AUTORESPOND_ENABLE
, 1);
598 rt2x00_set_field32(®
, TXRX_CSR4_AUTORESPOND_PREAMBLE
,
599 !!erp
->short_preamble
);
600 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR4
, reg
);
603 if (changed
& BSS_CHANGED_BASIC_RATES
)
604 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR5
,
607 if (changed
& BSS_CHANGED_BEACON_INT
) {
608 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR9
, ®
);
609 rt2x00_set_field32(®
, TXRX_CSR9_BEACON_INTERVAL
,
610 erp
->beacon_int
* 16);
611 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR9
, reg
);
614 if (changed
& BSS_CHANGED_ERP_SLOT
) {
615 rt2x00pci_register_read(rt2x00dev
, MAC_CSR9
, ®
);
616 rt2x00_set_field32(®
, MAC_CSR9_SLOT_TIME
, erp
->slot_time
);
617 rt2x00pci_register_write(rt2x00dev
, MAC_CSR9
, reg
);
619 rt2x00pci_register_read(rt2x00dev
, MAC_CSR8
, ®
);
620 rt2x00_set_field32(®
, MAC_CSR8_SIFS
, erp
->sifs
);
621 rt2x00_set_field32(®
, MAC_CSR8_SIFS_AFTER_RX_OFDM
, 3);
622 rt2x00_set_field32(®
, MAC_CSR8_EIFS
, erp
->eifs
);
623 rt2x00pci_register_write(rt2x00dev
, MAC_CSR8
, reg
);
627 static void rt61pci_config_antenna_5x(struct rt2x00_dev
*rt2x00dev
,
628 struct antenna_setup
*ant
)
634 rt61pci_bbp_read(rt2x00dev
, 3, &r3
);
635 rt61pci_bbp_read(rt2x00dev
, 4, &r4
);
636 rt61pci_bbp_read(rt2x00dev
, 77, &r77
);
638 rt2x00_set_field8(&r3
, BBP_R3_SMART_MODE
, rt2x00_rf(rt2x00dev
, RF5325
));
641 * Configure the RX antenna.
644 case ANTENNA_HW_DIVERSITY
:
645 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 2);
646 rt2x00_set_field8(&r4
, BBP_R4_RX_FRAME_END
,
647 (rt2x00dev
->curr_band
!= IEEE80211_BAND_5GHZ
));
650 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 1);
651 rt2x00_set_field8(&r4
, BBP_R4_RX_FRAME_END
, 0);
652 if (rt2x00dev
->curr_band
== IEEE80211_BAND_5GHZ
)
653 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 0);
655 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 3);
659 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 1);
660 rt2x00_set_field8(&r4
, BBP_R4_RX_FRAME_END
, 0);
661 if (rt2x00dev
->curr_band
== IEEE80211_BAND_5GHZ
)
662 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 3);
664 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 0);
668 rt61pci_bbp_write(rt2x00dev
, 77, r77
);
669 rt61pci_bbp_write(rt2x00dev
, 3, r3
);
670 rt61pci_bbp_write(rt2x00dev
, 4, r4
);
673 static void rt61pci_config_antenna_2x(struct rt2x00_dev
*rt2x00dev
,
674 struct antenna_setup
*ant
)
680 rt61pci_bbp_read(rt2x00dev
, 3, &r3
);
681 rt61pci_bbp_read(rt2x00dev
, 4, &r4
);
682 rt61pci_bbp_read(rt2x00dev
, 77, &r77
);
684 rt2x00_set_field8(&r3
, BBP_R3_SMART_MODE
, rt2x00_rf(rt2x00dev
, RF2529
));
685 rt2x00_set_field8(&r4
, BBP_R4_RX_FRAME_END
,
686 !test_bit(CONFIG_FRAME_TYPE
, &rt2x00dev
->flags
));
689 * Configure the RX antenna.
692 case ANTENNA_HW_DIVERSITY
:
693 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 2);
696 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 1);
697 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 3);
701 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 1);
702 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 0);
706 rt61pci_bbp_write(rt2x00dev
, 77, r77
);
707 rt61pci_bbp_write(rt2x00dev
, 3, r3
);
708 rt61pci_bbp_write(rt2x00dev
, 4, r4
);
711 static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev
*rt2x00dev
,
712 const int p1
, const int p2
)
716 rt2x00pci_register_read(rt2x00dev
, MAC_CSR13
, ®
);
718 rt2x00_set_field32(®
, MAC_CSR13_BIT4
, p1
);
719 rt2x00_set_field32(®
, MAC_CSR13_BIT12
, 0);
721 rt2x00_set_field32(®
, MAC_CSR13_BIT3
, !p2
);
722 rt2x00_set_field32(®
, MAC_CSR13_BIT11
, 0);
724 rt2x00pci_register_write(rt2x00dev
, MAC_CSR13
, reg
);
727 static void rt61pci_config_antenna_2529(struct rt2x00_dev
*rt2x00dev
,
728 struct antenna_setup
*ant
)
734 rt61pci_bbp_read(rt2x00dev
, 3, &r3
);
735 rt61pci_bbp_read(rt2x00dev
, 4, &r4
);
736 rt61pci_bbp_read(rt2x00dev
, 77, &r77
);
739 * Configure the RX antenna.
743 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 1);
744 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 0);
745 rt61pci_config_antenna_2529_rx(rt2x00dev
, 0, 0);
747 case ANTENNA_HW_DIVERSITY
:
749 * FIXME: Antenna selection for the rf 2529 is very confusing
750 * in the legacy driver. Just default to antenna B until the
751 * legacy code can be properly translated into rt2x00 code.
755 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 1);
756 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 3);
757 rt61pci_config_antenna_2529_rx(rt2x00dev
, 1, 1);
761 rt61pci_bbp_write(rt2x00dev
, 77, r77
);
762 rt61pci_bbp_write(rt2x00dev
, 3, r3
);
763 rt61pci_bbp_write(rt2x00dev
, 4, r4
);
769 * value[0] -> non-LNA
775 static const struct antenna_sel antenna_sel_a
[] = {
776 { 96, { 0x58, 0x78 } },
777 { 104, { 0x38, 0x48 } },
778 { 75, { 0xfe, 0x80 } },
779 { 86, { 0xfe, 0x80 } },
780 { 88, { 0xfe, 0x80 } },
781 { 35, { 0x60, 0x60 } },
782 { 97, { 0x58, 0x58 } },
783 { 98, { 0x58, 0x58 } },
786 static const struct antenna_sel antenna_sel_bg
[] = {
787 { 96, { 0x48, 0x68 } },
788 { 104, { 0x2c, 0x3c } },
789 { 75, { 0xfe, 0x80 } },
790 { 86, { 0xfe, 0x80 } },
791 { 88, { 0xfe, 0x80 } },
792 { 35, { 0x50, 0x50 } },
793 { 97, { 0x48, 0x48 } },
794 { 98, { 0x48, 0x48 } },
797 static void rt61pci_config_ant(struct rt2x00_dev
*rt2x00dev
,
798 struct antenna_setup
*ant
)
800 const struct antenna_sel
*sel
;
806 * We should never come here because rt2x00lib is supposed
807 * to catch this and send us the correct antenna explicitely.
809 BUG_ON(ant
->rx
== ANTENNA_SW_DIVERSITY
||
810 ant
->tx
== ANTENNA_SW_DIVERSITY
);
812 if (rt2x00dev
->curr_band
== IEEE80211_BAND_5GHZ
) {
814 lna
= test_bit(CONFIG_EXTERNAL_LNA_A
, &rt2x00dev
->flags
);
816 sel
= antenna_sel_bg
;
817 lna
= test_bit(CONFIG_EXTERNAL_LNA_BG
, &rt2x00dev
->flags
);
820 for (i
= 0; i
< ARRAY_SIZE(antenna_sel_a
); i
++)
821 rt61pci_bbp_write(rt2x00dev
, sel
[i
].word
, sel
[i
].value
[lna
]);
823 rt2x00pci_register_read(rt2x00dev
, PHY_CSR0
, ®
);
825 rt2x00_set_field32(®
, PHY_CSR0_PA_PE_BG
,
826 rt2x00dev
->curr_band
== IEEE80211_BAND_2GHZ
);
827 rt2x00_set_field32(®
, PHY_CSR0_PA_PE_A
,
828 rt2x00dev
->curr_band
== IEEE80211_BAND_5GHZ
);
830 rt2x00pci_register_write(rt2x00dev
, PHY_CSR0
, reg
);
832 if (rt2x00_rf(rt2x00dev
, RF5225
) || rt2x00_rf(rt2x00dev
, RF5325
))
833 rt61pci_config_antenna_5x(rt2x00dev
, ant
);
834 else if (rt2x00_rf(rt2x00dev
, RF2527
))
835 rt61pci_config_antenna_2x(rt2x00dev
, ant
);
836 else if (rt2x00_rf(rt2x00dev
, RF2529
)) {
837 if (test_bit(CONFIG_DOUBLE_ANTENNA
, &rt2x00dev
->flags
))
838 rt61pci_config_antenna_2x(rt2x00dev
, ant
);
840 rt61pci_config_antenna_2529(rt2x00dev
, ant
);
844 static void rt61pci_config_lna_gain(struct rt2x00_dev
*rt2x00dev
,
845 struct rt2x00lib_conf
*libconf
)
850 if (libconf
->conf
->channel
->band
== IEEE80211_BAND_2GHZ
) {
851 if (test_bit(CONFIG_EXTERNAL_LNA_BG
, &rt2x00dev
->flags
))
854 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_OFFSET_BG
, &eeprom
);
855 lna_gain
-= rt2x00_get_field16(eeprom
, EEPROM_RSSI_OFFSET_BG_1
);
857 if (test_bit(CONFIG_EXTERNAL_LNA_A
, &rt2x00dev
->flags
))
860 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_OFFSET_A
, &eeprom
);
861 lna_gain
-= rt2x00_get_field16(eeprom
, EEPROM_RSSI_OFFSET_A_1
);
864 rt2x00dev
->lna_gain
= lna_gain
;
867 static void rt61pci_config_channel(struct rt2x00_dev
*rt2x00dev
,
868 struct rf_channel
*rf
, const int txpower
)
874 rt2x00_set_field32(&rf
->rf3
, RF3_TXPOWER
, TXPOWER_TO_DEV(txpower
));
875 rt2x00_set_field32(&rf
->rf4
, RF4_FREQ_OFFSET
, rt2x00dev
->freq_offset
);
877 smart
= !(rt2x00_rf(rt2x00dev
, RF5225
) || rt2x00_rf(rt2x00dev
, RF2527
));
879 rt61pci_bbp_read(rt2x00dev
, 3, &r3
);
880 rt2x00_set_field8(&r3
, BBP_R3_SMART_MODE
, smart
);
881 rt61pci_bbp_write(rt2x00dev
, 3, r3
);
884 if (txpower
> MAX_TXPOWER
&& txpower
<= (MAX_TXPOWER
+ r94
))
885 r94
+= txpower
- MAX_TXPOWER
;
886 else if (txpower
< MIN_TXPOWER
&& txpower
>= (MIN_TXPOWER
- r94
))
888 rt61pci_bbp_write(rt2x00dev
, 94, r94
);
890 rt61pci_rf_write(rt2x00dev
, 1, rf
->rf1
);
891 rt61pci_rf_write(rt2x00dev
, 2, rf
->rf2
);
892 rt61pci_rf_write(rt2x00dev
, 3, rf
->rf3
& ~0x00000004);
893 rt61pci_rf_write(rt2x00dev
, 4, rf
->rf4
);
897 rt61pci_rf_write(rt2x00dev
, 1, rf
->rf1
);
898 rt61pci_rf_write(rt2x00dev
, 2, rf
->rf2
);
899 rt61pci_rf_write(rt2x00dev
, 3, rf
->rf3
| 0x00000004);
900 rt61pci_rf_write(rt2x00dev
, 4, rf
->rf4
);
904 rt61pci_rf_write(rt2x00dev
, 1, rf
->rf1
);
905 rt61pci_rf_write(rt2x00dev
, 2, rf
->rf2
);
906 rt61pci_rf_write(rt2x00dev
, 3, rf
->rf3
& ~0x00000004);
907 rt61pci_rf_write(rt2x00dev
, 4, rf
->rf4
);
912 static void rt61pci_config_txpower(struct rt2x00_dev
*rt2x00dev
,
915 struct rf_channel rf
;
917 rt2x00_rf_read(rt2x00dev
, 1, &rf
.rf1
);
918 rt2x00_rf_read(rt2x00dev
, 2, &rf
.rf2
);
919 rt2x00_rf_read(rt2x00dev
, 3, &rf
.rf3
);
920 rt2x00_rf_read(rt2x00dev
, 4, &rf
.rf4
);
922 rt61pci_config_channel(rt2x00dev
, &rf
, txpower
);
925 static void rt61pci_config_retry_limit(struct rt2x00_dev
*rt2x00dev
,
926 struct rt2x00lib_conf
*libconf
)
930 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR4
, ®
);
931 rt2x00_set_field32(®
, TXRX_CSR4_OFDM_TX_RATE_DOWN
, 1);
932 rt2x00_set_field32(®
, TXRX_CSR4_OFDM_TX_RATE_STEP
, 0);
933 rt2x00_set_field32(®
, TXRX_CSR4_OFDM_TX_FALLBACK_CCK
, 0);
934 rt2x00_set_field32(®
, TXRX_CSR4_LONG_RETRY_LIMIT
,
935 libconf
->conf
->long_frame_max_tx_count
);
936 rt2x00_set_field32(®
, TXRX_CSR4_SHORT_RETRY_LIMIT
,
937 libconf
->conf
->short_frame_max_tx_count
);
938 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR4
, reg
);
941 static void rt61pci_config_ps(struct rt2x00_dev
*rt2x00dev
,
942 struct rt2x00lib_conf
*libconf
)
944 enum dev_state state
=
945 (libconf
->conf
->flags
& IEEE80211_CONF_PS
) ?
946 STATE_SLEEP
: STATE_AWAKE
;
949 if (state
== STATE_SLEEP
) {
950 rt2x00pci_register_read(rt2x00dev
, MAC_CSR11
, ®
);
951 rt2x00_set_field32(®
, MAC_CSR11_DELAY_AFTER_TBCN
,
952 rt2x00dev
->beacon_int
- 10);
953 rt2x00_set_field32(®
, MAC_CSR11_TBCN_BEFORE_WAKEUP
,
954 libconf
->conf
->listen_interval
- 1);
955 rt2x00_set_field32(®
, MAC_CSR11_WAKEUP_LATENCY
, 5);
957 /* We must first disable autowake before it can be enabled */
958 rt2x00_set_field32(®
, MAC_CSR11_AUTOWAKE
, 0);
959 rt2x00pci_register_write(rt2x00dev
, MAC_CSR11
, reg
);
961 rt2x00_set_field32(®
, MAC_CSR11_AUTOWAKE
, 1);
962 rt2x00pci_register_write(rt2x00dev
, MAC_CSR11
, reg
);
964 rt2x00pci_register_write(rt2x00dev
, SOFT_RESET_CSR
, 0x00000005);
965 rt2x00pci_register_write(rt2x00dev
, IO_CNTL_CSR
, 0x0000001c);
966 rt2x00pci_register_write(rt2x00dev
, PCI_USEC_CSR
, 0x00000060);
968 rt61pci_mcu_request(rt2x00dev
, MCU_SLEEP
, 0xff, 0, 0);
970 rt2x00pci_register_read(rt2x00dev
, MAC_CSR11
, ®
);
971 rt2x00_set_field32(®
, MAC_CSR11_DELAY_AFTER_TBCN
, 0);
972 rt2x00_set_field32(®
, MAC_CSR11_TBCN_BEFORE_WAKEUP
, 0);
973 rt2x00_set_field32(®
, MAC_CSR11_AUTOWAKE
, 0);
974 rt2x00_set_field32(®
, MAC_CSR11_WAKEUP_LATENCY
, 0);
975 rt2x00pci_register_write(rt2x00dev
, MAC_CSR11
, reg
);
977 rt2x00pci_register_write(rt2x00dev
, SOFT_RESET_CSR
, 0x00000007);
978 rt2x00pci_register_write(rt2x00dev
, IO_CNTL_CSR
, 0x00000018);
979 rt2x00pci_register_write(rt2x00dev
, PCI_USEC_CSR
, 0x00000020);
981 rt61pci_mcu_request(rt2x00dev
, MCU_WAKEUP
, 0xff, 0, 0);
985 static void rt61pci_config(struct rt2x00_dev
*rt2x00dev
,
986 struct rt2x00lib_conf
*libconf
,
987 const unsigned int flags
)
989 /* Always recalculate LNA gain before changing configuration */
990 rt61pci_config_lna_gain(rt2x00dev
, libconf
);
992 if (flags
& IEEE80211_CONF_CHANGE_CHANNEL
)
993 rt61pci_config_channel(rt2x00dev
, &libconf
->rf
,
994 libconf
->conf
->power_level
);
995 if ((flags
& IEEE80211_CONF_CHANGE_POWER
) &&
996 !(flags
& IEEE80211_CONF_CHANGE_CHANNEL
))
997 rt61pci_config_txpower(rt2x00dev
, libconf
->conf
->power_level
);
998 if (flags
& IEEE80211_CONF_CHANGE_RETRY_LIMITS
)
999 rt61pci_config_retry_limit(rt2x00dev
, libconf
);
1000 if (flags
& IEEE80211_CONF_CHANGE_PS
)
1001 rt61pci_config_ps(rt2x00dev
, libconf
);
1007 static void rt61pci_link_stats(struct rt2x00_dev
*rt2x00dev
,
1008 struct link_qual
*qual
)
1013 * Update FCS error count from register.
1015 rt2x00pci_register_read(rt2x00dev
, STA_CSR0
, ®
);
1016 qual
->rx_failed
= rt2x00_get_field32(reg
, STA_CSR0_FCS_ERROR
);
1019 * Update False CCA count from register.
1021 rt2x00pci_register_read(rt2x00dev
, STA_CSR1
, ®
);
1022 qual
->false_cca
= rt2x00_get_field32(reg
, STA_CSR1_FALSE_CCA_ERROR
);
1025 static inline void rt61pci_set_vgc(struct rt2x00_dev
*rt2x00dev
,
1026 struct link_qual
*qual
, u8 vgc_level
)
1028 if (qual
->vgc_level
!= vgc_level
) {
1029 rt61pci_bbp_write(rt2x00dev
, 17, vgc_level
);
1030 qual
->vgc_level
= vgc_level
;
1031 qual
->vgc_level_reg
= vgc_level
;
1035 static void rt61pci_reset_tuner(struct rt2x00_dev
*rt2x00dev
,
1036 struct link_qual
*qual
)
1038 rt61pci_set_vgc(rt2x00dev
, qual
, 0x20);
1041 static void rt61pci_link_tuner(struct rt2x00_dev
*rt2x00dev
,
1042 struct link_qual
*qual
, const u32 count
)
1048 * Determine r17 bounds.
1050 if (rt2x00dev
->curr_band
== IEEE80211_BAND_5GHZ
) {
1053 if (test_bit(CONFIG_EXTERNAL_LNA_A
, &rt2x00dev
->flags
)) {
1060 if (test_bit(CONFIG_EXTERNAL_LNA_BG
, &rt2x00dev
->flags
)) {
1067 * If we are not associated, we should go straight to the
1068 * dynamic CCA tuning.
1070 if (!rt2x00dev
->intf_associated
)
1071 goto dynamic_cca_tune
;
1074 * Special big-R17 for very short distance
1076 if (qual
->rssi
>= -35) {
1077 rt61pci_set_vgc(rt2x00dev
, qual
, 0x60);
1082 * Special big-R17 for short distance
1084 if (qual
->rssi
>= -58) {
1085 rt61pci_set_vgc(rt2x00dev
, qual
, up_bound
);
1090 * Special big-R17 for middle-short distance
1092 if (qual
->rssi
>= -66) {
1093 rt61pci_set_vgc(rt2x00dev
, qual
, low_bound
+ 0x10);
1098 * Special mid-R17 for middle distance
1100 if (qual
->rssi
>= -74) {
1101 rt61pci_set_vgc(rt2x00dev
, qual
, low_bound
+ 0x08);
1106 * Special case: Change up_bound based on the rssi.
1107 * Lower up_bound when rssi is weaker then -74 dBm.
1109 up_bound
-= 2 * (-74 - qual
->rssi
);
1110 if (low_bound
> up_bound
)
1111 up_bound
= low_bound
;
1113 if (qual
->vgc_level
> up_bound
) {
1114 rt61pci_set_vgc(rt2x00dev
, qual
, up_bound
);
1121 * r17 does not yet exceed upper limit, continue and base
1122 * the r17 tuning on the false CCA count.
1124 if ((qual
->false_cca
> 512) && (qual
->vgc_level
< up_bound
))
1125 rt61pci_set_vgc(rt2x00dev
, qual
, ++qual
->vgc_level
);
1126 else if ((qual
->false_cca
< 100) && (qual
->vgc_level
> low_bound
))
1127 rt61pci_set_vgc(rt2x00dev
, qual
, --qual
->vgc_level
);
1133 static void rt61pci_start_queue(struct data_queue
*queue
)
1135 struct rt2x00_dev
*rt2x00dev
= queue
->rt2x00dev
;
1138 switch (queue
->qid
) {
1140 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR0
, ®
);
1141 rt2x00_set_field32(®
, TXRX_CSR0_DISABLE_RX
, 0);
1142 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR0
, reg
);
1145 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR9
, ®
);
1146 rt2x00_set_field32(®
, TXRX_CSR9_TSF_TICKING
, 1);
1147 rt2x00_set_field32(®
, TXRX_CSR9_TBTT_ENABLE
, 1);
1148 rt2x00_set_field32(®
, TXRX_CSR9_BEACON_GEN
, 1);
1149 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR9
, reg
);
1156 static void rt61pci_kick_queue(struct data_queue
*queue
)
1158 struct rt2x00_dev
*rt2x00dev
= queue
->rt2x00dev
;
1161 switch (queue
->qid
) {
1163 rt2x00pci_register_read(rt2x00dev
, TX_CNTL_CSR
, ®
);
1164 rt2x00_set_field32(®
, TX_CNTL_CSR_KICK_TX_AC0
, 1);
1165 rt2x00pci_register_write(rt2x00dev
, TX_CNTL_CSR
, reg
);
1168 rt2x00pci_register_read(rt2x00dev
, TX_CNTL_CSR
, ®
);
1169 rt2x00_set_field32(®
, TX_CNTL_CSR_KICK_TX_AC1
, 1);
1170 rt2x00pci_register_write(rt2x00dev
, TX_CNTL_CSR
, reg
);
1173 rt2x00pci_register_read(rt2x00dev
, TX_CNTL_CSR
, ®
);
1174 rt2x00_set_field32(®
, TX_CNTL_CSR_KICK_TX_AC2
, 1);
1175 rt2x00pci_register_write(rt2x00dev
, TX_CNTL_CSR
, reg
);
1178 rt2x00pci_register_read(rt2x00dev
, TX_CNTL_CSR
, ®
);
1179 rt2x00_set_field32(®
, TX_CNTL_CSR_KICK_TX_AC3
, 1);
1180 rt2x00pci_register_write(rt2x00dev
, TX_CNTL_CSR
, reg
);
1187 static void rt61pci_stop_queue(struct data_queue
*queue
)
1189 struct rt2x00_dev
*rt2x00dev
= queue
->rt2x00dev
;
1192 switch (queue
->qid
) {
1194 rt2x00pci_register_read(rt2x00dev
, TX_CNTL_CSR
, ®
);
1195 rt2x00_set_field32(®
, TX_CNTL_CSR_ABORT_TX_AC0
, 1);
1196 rt2x00pci_register_write(rt2x00dev
, TX_CNTL_CSR
, reg
);
1199 rt2x00pci_register_read(rt2x00dev
, TX_CNTL_CSR
, ®
);
1200 rt2x00_set_field32(®
, TX_CNTL_CSR_ABORT_TX_AC1
, 1);
1201 rt2x00pci_register_write(rt2x00dev
, TX_CNTL_CSR
, reg
);
1204 rt2x00pci_register_read(rt2x00dev
, TX_CNTL_CSR
, ®
);
1205 rt2x00_set_field32(®
, TX_CNTL_CSR_ABORT_TX_AC2
, 1);
1206 rt2x00pci_register_write(rt2x00dev
, TX_CNTL_CSR
, reg
);
1209 rt2x00pci_register_read(rt2x00dev
, TX_CNTL_CSR
, ®
);
1210 rt2x00_set_field32(®
, TX_CNTL_CSR_ABORT_TX_AC3
, 1);
1211 rt2x00pci_register_write(rt2x00dev
, TX_CNTL_CSR
, reg
);
1214 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR0
, ®
);
1215 rt2x00_set_field32(®
, TXRX_CSR0_DISABLE_RX
, 1);
1216 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR0
, reg
);
1219 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR9
, ®
);
1220 rt2x00_set_field32(®
, TXRX_CSR9_TSF_TICKING
, 0);
1221 rt2x00_set_field32(®
, TXRX_CSR9_TBTT_ENABLE
, 0);
1222 rt2x00_set_field32(®
, TXRX_CSR9_BEACON_GEN
, 0);
1223 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR9
, reg
);
1231 * Firmware functions
1233 static char *rt61pci_get_firmware_name(struct rt2x00_dev
*rt2x00dev
)
1238 pci_read_config_word(to_pci_dev(rt2x00dev
->dev
), PCI_DEVICE_ID
, &chip
);
1241 fw_name
= FIRMWARE_RT2561
;
1243 case RT2561s_PCI_ID
:
1244 fw_name
= FIRMWARE_RT2561s
;
1247 fw_name
= FIRMWARE_RT2661
;
1257 static int rt61pci_check_firmware(struct rt2x00_dev
*rt2x00dev
,
1258 const u8
*data
, const size_t len
)
1264 * Only support 8kb firmware files.
1267 return FW_BAD_LENGTH
;
1270 * The last 2 bytes in the firmware array are the crc checksum itself.
1271 * This means that we should never pass those 2 bytes to the crc
1274 fw_crc
= (data
[len
- 2] << 8 | data
[len
- 1]);
1277 * Use the crc itu-t algorithm.
1279 crc
= crc_itu_t(0, data
, len
- 2);
1280 crc
= crc_itu_t_byte(crc
, 0);
1281 crc
= crc_itu_t_byte(crc
, 0);
1283 return (fw_crc
== crc
) ? FW_OK
: FW_BAD_CRC
;
1286 static int rt61pci_load_firmware(struct rt2x00_dev
*rt2x00dev
,
1287 const u8
*data
, const size_t len
)
1293 * Wait for stable hardware.
1295 for (i
= 0; i
< 100; i
++) {
1296 rt2x00pci_register_read(rt2x00dev
, MAC_CSR0
, ®
);
1303 ERROR(rt2x00dev
, "Unstable hardware.\n");
1308 * Prepare MCU and mailbox for firmware loading.
1311 rt2x00_set_field32(®
, MCU_CNTL_CSR_RESET
, 1);
1312 rt2x00pci_register_write(rt2x00dev
, MCU_CNTL_CSR
, reg
);
1313 rt2x00pci_register_write(rt2x00dev
, M2H_CMD_DONE_CSR
, 0xffffffff);
1314 rt2x00pci_register_write(rt2x00dev
, H2M_MAILBOX_CSR
, 0);
1315 rt2x00pci_register_write(rt2x00dev
, HOST_CMD_CSR
, 0);
1318 * Write firmware to device.
1321 rt2x00_set_field32(®
, MCU_CNTL_CSR_RESET
, 1);
1322 rt2x00_set_field32(®
, MCU_CNTL_CSR_SELECT_BANK
, 1);
1323 rt2x00pci_register_write(rt2x00dev
, MCU_CNTL_CSR
, reg
);
1325 rt2x00pci_register_multiwrite(rt2x00dev
, FIRMWARE_IMAGE_BASE
,
1328 rt2x00_set_field32(®
, MCU_CNTL_CSR_SELECT_BANK
, 0);
1329 rt2x00pci_register_write(rt2x00dev
, MCU_CNTL_CSR
, reg
);
1331 rt2x00_set_field32(®
, MCU_CNTL_CSR_RESET
, 0);
1332 rt2x00pci_register_write(rt2x00dev
, MCU_CNTL_CSR
, reg
);
1334 for (i
= 0; i
< 100; i
++) {
1335 rt2x00pci_register_read(rt2x00dev
, MCU_CNTL_CSR
, ®
);
1336 if (rt2x00_get_field32(reg
, MCU_CNTL_CSR_READY
))
1342 ERROR(rt2x00dev
, "MCU Control register not ready.\n");
1347 * Hardware needs another millisecond before it is ready.
1352 * Reset MAC and BBP registers.
1355 rt2x00_set_field32(®
, MAC_CSR1_SOFT_RESET
, 1);
1356 rt2x00_set_field32(®
, MAC_CSR1_BBP_RESET
, 1);
1357 rt2x00pci_register_write(rt2x00dev
, MAC_CSR1
, reg
);
1359 rt2x00pci_register_read(rt2x00dev
, MAC_CSR1
, ®
);
1360 rt2x00_set_field32(®
, MAC_CSR1_SOFT_RESET
, 0);
1361 rt2x00_set_field32(®
, MAC_CSR1_BBP_RESET
, 0);
1362 rt2x00pci_register_write(rt2x00dev
, MAC_CSR1
, reg
);
1364 rt2x00pci_register_read(rt2x00dev
, MAC_CSR1
, ®
);
1365 rt2x00_set_field32(®
, MAC_CSR1_HOST_READY
, 1);
1366 rt2x00pci_register_write(rt2x00dev
, MAC_CSR1
, reg
);
1372 * Initialization functions.
1374 static bool rt61pci_get_entry_state(struct queue_entry
*entry
)
1376 struct queue_entry_priv_pci
*entry_priv
= entry
->priv_data
;
1379 if (entry
->queue
->qid
== QID_RX
) {
1380 rt2x00_desc_read(entry_priv
->desc
, 0, &word
);
1382 return rt2x00_get_field32(word
, RXD_W0_OWNER_NIC
);
1384 rt2x00_desc_read(entry_priv
->desc
, 0, &word
);
1386 return (rt2x00_get_field32(word
, TXD_W0_OWNER_NIC
) ||
1387 rt2x00_get_field32(word
, TXD_W0_VALID
));
1391 static void rt61pci_clear_entry(struct queue_entry
*entry
)
1393 struct queue_entry_priv_pci
*entry_priv
= entry
->priv_data
;
1394 struct skb_frame_desc
*skbdesc
= get_skb_frame_desc(entry
->skb
);
1397 if (entry
->queue
->qid
== QID_RX
) {
1398 rt2x00_desc_read(entry_priv
->desc
, 5, &word
);
1399 rt2x00_set_field32(&word
, RXD_W5_BUFFER_PHYSICAL_ADDRESS
,
1401 rt2x00_desc_write(entry_priv
->desc
, 5, word
);
1403 rt2x00_desc_read(entry_priv
->desc
, 0, &word
);
1404 rt2x00_set_field32(&word
, RXD_W0_OWNER_NIC
, 1);
1405 rt2x00_desc_write(entry_priv
->desc
, 0, word
);
1407 rt2x00_desc_read(entry_priv
->desc
, 0, &word
);
1408 rt2x00_set_field32(&word
, TXD_W0_VALID
, 0);
1409 rt2x00_set_field32(&word
, TXD_W0_OWNER_NIC
, 0);
1410 rt2x00_desc_write(entry_priv
->desc
, 0, word
);
1414 static int rt61pci_init_queues(struct rt2x00_dev
*rt2x00dev
)
1416 struct queue_entry_priv_pci
*entry_priv
;
1420 * Initialize registers.
1422 rt2x00pci_register_read(rt2x00dev
, TX_RING_CSR0
, ®
);
1423 rt2x00_set_field32(®
, TX_RING_CSR0_AC0_RING_SIZE
,
1424 rt2x00dev
->tx
[0].limit
);
1425 rt2x00_set_field32(®
, TX_RING_CSR0_AC1_RING_SIZE
,
1426 rt2x00dev
->tx
[1].limit
);
1427 rt2x00_set_field32(®
, TX_RING_CSR0_AC2_RING_SIZE
,
1428 rt2x00dev
->tx
[2].limit
);
1429 rt2x00_set_field32(®
, TX_RING_CSR0_AC3_RING_SIZE
,
1430 rt2x00dev
->tx
[3].limit
);
1431 rt2x00pci_register_write(rt2x00dev
, TX_RING_CSR0
, reg
);
1433 rt2x00pci_register_read(rt2x00dev
, TX_RING_CSR1
, ®
);
1434 rt2x00_set_field32(®
, TX_RING_CSR1_TXD_SIZE
,
1435 rt2x00dev
->tx
[0].desc_size
/ 4);
1436 rt2x00pci_register_write(rt2x00dev
, TX_RING_CSR1
, reg
);
1438 entry_priv
= rt2x00dev
->tx
[0].entries
[0].priv_data
;
1439 rt2x00pci_register_read(rt2x00dev
, AC0_BASE_CSR
, ®
);
1440 rt2x00_set_field32(®
, AC0_BASE_CSR_RING_REGISTER
,
1441 entry_priv
->desc_dma
);
1442 rt2x00pci_register_write(rt2x00dev
, AC0_BASE_CSR
, reg
);
1444 entry_priv
= rt2x00dev
->tx
[1].entries
[0].priv_data
;
1445 rt2x00pci_register_read(rt2x00dev
, AC1_BASE_CSR
, ®
);
1446 rt2x00_set_field32(®
, AC1_BASE_CSR_RING_REGISTER
,
1447 entry_priv
->desc_dma
);
1448 rt2x00pci_register_write(rt2x00dev
, AC1_BASE_CSR
, reg
);
1450 entry_priv
= rt2x00dev
->tx
[2].entries
[0].priv_data
;
1451 rt2x00pci_register_read(rt2x00dev
, AC2_BASE_CSR
, ®
);
1452 rt2x00_set_field32(®
, AC2_BASE_CSR_RING_REGISTER
,
1453 entry_priv
->desc_dma
);
1454 rt2x00pci_register_write(rt2x00dev
, AC2_BASE_CSR
, reg
);
1456 entry_priv
= rt2x00dev
->tx
[3].entries
[0].priv_data
;
1457 rt2x00pci_register_read(rt2x00dev
, AC3_BASE_CSR
, ®
);
1458 rt2x00_set_field32(®
, AC3_BASE_CSR_RING_REGISTER
,
1459 entry_priv
->desc_dma
);
1460 rt2x00pci_register_write(rt2x00dev
, AC3_BASE_CSR
, reg
);
1462 rt2x00pci_register_read(rt2x00dev
, RX_RING_CSR
, ®
);
1463 rt2x00_set_field32(®
, RX_RING_CSR_RING_SIZE
, rt2x00dev
->rx
->limit
);
1464 rt2x00_set_field32(®
, RX_RING_CSR_RXD_SIZE
,
1465 rt2x00dev
->rx
->desc_size
/ 4);
1466 rt2x00_set_field32(®
, RX_RING_CSR_RXD_WRITEBACK_SIZE
, 4);
1467 rt2x00pci_register_write(rt2x00dev
, RX_RING_CSR
, reg
);
1469 entry_priv
= rt2x00dev
->rx
->entries
[0].priv_data
;
1470 rt2x00pci_register_read(rt2x00dev
, RX_BASE_CSR
, ®
);
1471 rt2x00_set_field32(®
, RX_BASE_CSR_RING_REGISTER
,
1472 entry_priv
->desc_dma
);
1473 rt2x00pci_register_write(rt2x00dev
, RX_BASE_CSR
, reg
);
1475 rt2x00pci_register_read(rt2x00dev
, TX_DMA_DST_CSR
, ®
);
1476 rt2x00_set_field32(®
, TX_DMA_DST_CSR_DEST_AC0
, 2);
1477 rt2x00_set_field32(®
, TX_DMA_DST_CSR_DEST_AC1
, 2);
1478 rt2x00_set_field32(®
, TX_DMA_DST_CSR_DEST_AC2
, 2);
1479 rt2x00_set_field32(®
, TX_DMA_DST_CSR_DEST_AC3
, 2);
1480 rt2x00pci_register_write(rt2x00dev
, TX_DMA_DST_CSR
, reg
);
1482 rt2x00pci_register_read(rt2x00dev
, LOAD_TX_RING_CSR
, ®
);
1483 rt2x00_set_field32(®
, LOAD_TX_RING_CSR_LOAD_TXD_AC0
, 1);
1484 rt2x00_set_field32(®
, LOAD_TX_RING_CSR_LOAD_TXD_AC1
, 1);
1485 rt2x00_set_field32(®
, LOAD_TX_RING_CSR_LOAD_TXD_AC2
, 1);
1486 rt2x00_set_field32(®
, LOAD_TX_RING_CSR_LOAD_TXD_AC3
, 1);
1487 rt2x00pci_register_write(rt2x00dev
, LOAD_TX_RING_CSR
, reg
);
1489 rt2x00pci_register_read(rt2x00dev
, RX_CNTL_CSR
, ®
);
1490 rt2x00_set_field32(®
, RX_CNTL_CSR_LOAD_RXD
, 1);
1491 rt2x00pci_register_write(rt2x00dev
, RX_CNTL_CSR
, reg
);
1496 static int rt61pci_init_registers(struct rt2x00_dev
*rt2x00dev
)
1500 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR0
, ®
);
1501 rt2x00_set_field32(®
, TXRX_CSR0_AUTO_TX_SEQ
, 1);
1502 rt2x00_set_field32(®
, TXRX_CSR0_DISABLE_RX
, 0);
1503 rt2x00_set_field32(®
, TXRX_CSR0_TX_WITHOUT_WAITING
, 0);
1504 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR0
, reg
);
1506 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR1
, ®
);
1507 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID0
, 47); /* CCK Signal */
1508 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID0_VALID
, 1);
1509 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID1
, 30); /* Rssi */
1510 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID1_VALID
, 1);
1511 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID2
, 42); /* OFDM Rate */
1512 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID2_VALID
, 1);
1513 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID3
, 30); /* Rssi */
1514 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID3_VALID
, 1);
1515 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR1
, reg
);
1518 * CCK TXD BBP registers
1520 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR2
, ®
);
1521 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID0
, 13);
1522 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID0_VALID
, 1);
1523 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID1
, 12);
1524 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID1_VALID
, 1);
1525 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID2
, 11);
1526 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID2_VALID
, 1);
1527 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID3
, 10);
1528 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID3_VALID
, 1);
1529 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR2
, reg
);
1532 * OFDM TXD BBP registers
1534 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR3
, ®
);
1535 rt2x00_set_field32(®
, TXRX_CSR3_BBP_ID0
, 7);
1536 rt2x00_set_field32(®
, TXRX_CSR3_BBP_ID0_VALID
, 1);
1537 rt2x00_set_field32(®
, TXRX_CSR3_BBP_ID1
, 6);
1538 rt2x00_set_field32(®
, TXRX_CSR3_BBP_ID1_VALID
, 1);
1539 rt2x00_set_field32(®
, TXRX_CSR3_BBP_ID2
, 5);
1540 rt2x00_set_field32(®
, TXRX_CSR3_BBP_ID2_VALID
, 1);
1541 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR3
, reg
);
1543 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR7
, ®
);
1544 rt2x00_set_field32(®
, TXRX_CSR7_ACK_CTS_6MBS
, 59);
1545 rt2x00_set_field32(®
, TXRX_CSR7_ACK_CTS_9MBS
, 53);
1546 rt2x00_set_field32(®
, TXRX_CSR7_ACK_CTS_12MBS
, 49);
1547 rt2x00_set_field32(®
, TXRX_CSR7_ACK_CTS_18MBS
, 46);
1548 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR7
, reg
);
1550 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR8
, ®
);
1551 rt2x00_set_field32(®
, TXRX_CSR8_ACK_CTS_24MBS
, 44);
1552 rt2x00_set_field32(®
, TXRX_CSR8_ACK_CTS_36MBS
, 42);
1553 rt2x00_set_field32(®
, TXRX_CSR8_ACK_CTS_48MBS
, 42);
1554 rt2x00_set_field32(®
, TXRX_CSR8_ACK_CTS_54MBS
, 42);
1555 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR8
, reg
);
1557 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR9
, ®
);
1558 rt2x00_set_field32(®
, TXRX_CSR9_BEACON_INTERVAL
, 0);
1559 rt2x00_set_field32(®
, TXRX_CSR9_TSF_TICKING
, 0);
1560 rt2x00_set_field32(®
, TXRX_CSR9_TSF_SYNC
, 0);
1561 rt2x00_set_field32(®
, TXRX_CSR9_TBTT_ENABLE
, 0);
1562 rt2x00_set_field32(®
, TXRX_CSR9_BEACON_GEN
, 0);
1563 rt2x00_set_field32(®
, TXRX_CSR9_TIMESTAMP_COMPENSATE
, 0);
1564 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR9
, reg
);
1566 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR15
, 0x0000000f);
1568 rt2x00pci_register_write(rt2x00dev
, MAC_CSR6
, 0x00000fff);
1570 rt2x00pci_register_read(rt2x00dev
, MAC_CSR9
, ®
);
1571 rt2x00_set_field32(®
, MAC_CSR9_CW_SELECT
, 0);
1572 rt2x00pci_register_write(rt2x00dev
, MAC_CSR9
, reg
);
1574 rt2x00pci_register_write(rt2x00dev
, MAC_CSR10
, 0x0000071c);
1576 if (rt2x00dev
->ops
->lib
->set_device_state(rt2x00dev
, STATE_AWAKE
))
1579 rt2x00pci_register_write(rt2x00dev
, MAC_CSR13
, 0x0000e000);
1582 * Invalidate all Shared Keys (SEC_CSR0),
1583 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1585 rt2x00pci_register_write(rt2x00dev
, SEC_CSR0
, 0x00000000);
1586 rt2x00pci_register_write(rt2x00dev
, SEC_CSR1
, 0x00000000);
1587 rt2x00pci_register_write(rt2x00dev
, SEC_CSR5
, 0x00000000);
1589 rt2x00pci_register_write(rt2x00dev
, PHY_CSR1
, 0x000023b0);
1590 rt2x00pci_register_write(rt2x00dev
, PHY_CSR5
, 0x060a100c);
1591 rt2x00pci_register_write(rt2x00dev
, PHY_CSR6
, 0x00080606);
1592 rt2x00pci_register_write(rt2x00dev
, PHY_CSR7
, 0x00000a08);
1594 rt2x00pci_register_write(rt2x00dev
, PCI_CFG_CSR
, 0x28ca4404);
1596 rt2x00pci_register_write(rt2x00dev
, TEST_MODE_CSR
, 0x00000200);
1598 rt2x00pci_register_write(rt2x00dev
, M2H_CMD_DONE_CSR
, 0xffffffff);
1602 * For the Beacon base registers we only need to clear
1603 * the first byte since that byte contains the VALID and OWNER
1604 * bits which (when set to 0) will invalidate the entire beacon.
1606 rt2x00pci_register_write(rt2x00dev
, HW_BEACON_BASE0
, 0);
1607 rt2x00pci_register_write(rt2x00dev
, HW_BEACON_BASE1
, 0);
1608 rt2x00pci_register_write(rt2x00dev
, HW_BEACON_BASE2
, 0);
1609 rt2x00pci_register_write(rt2x00dev
, HW_BEACON_BASE3
, 0);
1612 * We must clear the error counters.
1613 * These registers are cleared on read,
1614 * so we may pass a useless variable to store the value.
1616 rt2x00pci_register_read(rt2x00dev
, STA_CSR0
, ®
);
1617 rt2x00pci_register_read(rt2x00dev
, STA_CSR1
, ®
);
1618 rt2x00pci_register_read(rt2x00dev
, STA_CSR2
, ®
);
1621 * Reset MAC and BBP registers.
1623 rt2x00pci_register_read(rt2x00dev
, MAC_CSR1
, ®
);
1624 rt2x00_set_field32(®
, MAC_CSR1_SOFT_RESET
, 1);
1625 rt2x00_set_field32(®
, MAC_CSR1_BBP_RESET
, 1);
1626 rt2x00pci_register_write(rt2x00dev
, MAC_CSR1
, reg
);
1628 rt2x00pci_register_read(rt2x00dev
, MAC_CSR1
, ®
);
1629 rt2x00_set_field32(®
, MAC_CSR1_SOFT_RESET
, 0);
1630 rt2x00_set_field32(®
, MAC_CSR1_BBP_RESET
, 0);
1631 rt2x00pci_register_write(rt2x00dev
, MAC_CSR1
, reg
);
1633 rt2x00pci_register_read(rt2x00dev
, MAC_CSR1
, ®
);
1634 rt2x00_set_field32(®
, MAC_CSR1_HOST_READY
, 1);
1635 rt2x00pci_register_write(rt2x00dev
, MAC_CSR1
, reg
);
1640 static int rt61pci_wait_bbp_ready(struct rt2x00_dev
*rt2x00dev
)
1645 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
1646 rt61pci_bbp_read(rt2x00dev
, 0, &value
);
1647 if ((value
!= 0xff) && (value
!= 0x00))
1649 udelay(REGISTER_BUSY_DELAY
);
1652 ERROR(rt2x00dev
, "BBP register access failed, aborting.\n");
1656 static int rt61pci_init_bbp(struct rt2x00_dev
*rt2x00dev
)
1663 if (unlikely(rt61pci_wait_bbp_ready(rt2x00dev
)))
1666 rt61pci_bbp_write(rt2x00dev
, 3, 0x00);
1667 rt61pci_bbp_write(rt2x00dev
, 15, 0x30);
1668 rt61pci_bbp_write(rt2x00dev
, 21, 0xc8);
1669 rt61pci_bbp_write(rt2x00dev
, 22, 0x38);
1670 rt61pci_bbp_write(rt2x00dev
, 23, 0x06);
1671 rt61pci_bbp_write(rt2x00dev
, 24, 0xfe);
1672 rt61pci_bbp_write(rt2x00dev
, 25, 0x0a);
1673 rt61pci_bbp_write(rt2x00dev
, 26, 0x0d);
1674 rt61pci_bbp_write(rt2x00dev
, 34, 0x12);
1675 rt61pci_bbp_write(rt2x00dev
, 37, 0x07);
1676 rt61pci_bbp_write(rt2x00dev
, 39, 0xf8);
1677 rt61pci_bbp_write(rt2x00dev
, 41, 0x60);
1678 rt61pci_bbp_write(rt2x00dev
, 53, 0x10);
1679 rt61pci_bbp_write(rt2x00dev
, 54, 0x18);
1680 rt61pci_bbp_write(rt2x00dev
, 60, 0x10);
1681 rt61pci_bbp_write(rt2x00dev
, 61, 0x04);
1682 rt61pci_bbp_write(rt2x00dev
, 62, 0x04);
1683 rt61pci_bbp_write(rt2x00dev
, 75, 0xfe);
1684 rt61pci_bbp_write(rt2x00dev
, 86, 0xfe);
1685 rt61pci_bbp_write(rt2x00dev
, 88, 0xfe);
1686 rt61pci_bbp_write(rt2x00dev
, 90, 0x0f);
1687 rt61pci_bbp_write(rt2x00dev
, 99, 0x00);
1688 rt61pci_bbp_write(rt2x00dev
, 102, 0x16);
1689 rt61pci_bbp_write(rt2x00dev
, 107, 0x04);
1691 for (i
= 0; i
< EEPROM_BBP_SIZE
; i
++) {
1692 rt2x00_eeprom_read(rt2x00dev
, EEPROM_BBP_START
+ i
, &eeprom
);
1694 if (eeprom
!= 0xffff && eeprom
!= 0x0000) {
1695 reg_id
= rt2x00_get_field16(eeprom
, EEPROM_BBP_REG_ID
);
1696 value
= rt2x00_get_field16(eeprom
, EEPROM_BBP_VALUE
);
1697 rt61pci_bbp_write(rt2x00dev
, reg_id
, value
);
1705 * Device state switch handlers.
1707 static void rt61pci_toggle_irq(struct rt2x00_dev
*rt2x00dev
,
1708 enum dev_state state
)
1710 int mask
= (state
== STATE_RADIO_IRQ_OFF
) ||
1711 (state
== STATE_RADIO_IRQ_OFF_ISR
);
1715 * When interrupts are being enabled, the interrupt registers
1716 * should clear the register to assure a clean state.
1718 if (state
== STATE_RADIO_IRQ_ON
) {
1719 rt2x00pci_register_read(rt2x00dev
, INT_SOURCE_CSR
, ®
);
1720 rt2x00pci_register_write(rt2x00dev
, INT_SOURCE_CSR
, reg
);
1722 rt2x00pci_register_read(rt2x00dev
, MCU_INT_SOURCE_CSR
, ®
);
1723 rt2x00pci_register_write(rt2x00dev
, MCU_INT_SOURCE_CSR
, reg
);
1727 * Only toggle the interrupts bits we are going to use.
1728 * Non-checked interrupt bits are disabled by default.
1730 rt2x00pci_register_read(rt2x00dev
, INT_MASK_CSR
, ®
);
1731 rt2x00_set_field32(®
, INT_MASK_CSR_TXDONE
, mask
);
1732 rt2x00_set_field32(®
, INT_MASK_CSR_RXDONE
, mask
);
1733 rt2x00_set_field32(®
, INT_MASK_CSR_BEACON_DONE
, mask
);
1734 rt2x00_set_field32(®
, INT_MASK_CSR_ENABLE_MITIGATION
, mask
);
1735 rt2x00_set_field32(®
, INT_MASK_CSR_MITIGATION_PERIOD
, 0xff);
1736 rt2x00pci_register_write(rt2x00dev
, INT_MASK_CSR
, reg
);
1738 rt2x00pci_register_read(rt2x00dev
, MCU_INT_MASK_CSR
, ®
);
1739 rt2x00_set_field32(®
, MCU_INT_MASK_CSR_0
, mask
);
1740 rt2x00_set_field32(®
, MCU_INT_MASK_CSR_1
, mask
);
1741 rt2x00_set_field32(®
, MCU_INT_MASK_CSR_2
, mask
);
1742 rt2x00_set_field32(®
, MCU_INT_MASK_CSR_3
, mask
);
1743 rt2x00_set_field32(®
, MCU_INT_MASK_CSR_4
, mask
);
1744 rt2x00_set_field32(®
, MCU_INT_MASK_CSR_5
, mask
);
1745 rt2x00_set_field32(®
, MCU_INT_MASK_CSR_6
, mask
);
1746 rt2x00_set_field32(®
, MCU_INT_MASK_CSR_7
, mask
);
1747 rt2x00_set_field32(®
, MCU_INT_MASK_CSR_TWAKEUP
, mask
);
1748 rt2x00pci_register_write(rt2x00dev
, MCU_INT_MASK_CSR
, reg
);
1751 static int rt61pci_enable_radio(struct rt2x00_dev
*rt2x00dev
)
1756 * Initialize all registers.
1758 if (unlikely(rt61pci_init_queues(rt2x00dev
) ||
1759 rt61pci_init_registers(rt2x00dev
) ||
1760 rt61pci_init_bbp(rt2x00dev
)))
1766 rt2x00pci_register_read(rt2x00dev
, RX_CNTL_CSR
, ®
);
1767 rt2x00_set_field32(®
, RX_CNTL_CSR_ENABLE_RX_DMA
, 1);
1768 rt2x00pci_register_write(rt2x00dev
, RX_CNTL_CSR
, reg
);
1773 static void rt61pci_disable_radio(struct rt2x00_dev
*rt2x00dev
)
1778 rt2x00pci_register_write(rt2x00dev
, MAC_CSR10
, 0x00001818);
1781 static int rt61pci_set_state(struct rt2x00_dev
*rt2x00dev
, enum dev_state state
)
1787 put_to_sleep
= (state
!= STATE_AWAKE
);
1789 rt2x00pci_register_read(rt2x00dev
, MAC_CSR12
, ®
);
1790 rt2x00_set_field32(®
, MAC_CSR12_FORCE_WAKEUP
, !put_to_sleep
);
1791 rt2x00_set_field32(®
, MAC_CSR12_PUT_TO_SLEEP
, put_to_sleep
);
1792 rt2x00pci_register_write(rt2x00dev
, MAC_CSR12
, reg
);
1795 * Device is not guaranteed to be in the requested state yet.
1796 * We must wait until the register indicates that the
1797 * device has entered the correct state.
1799 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
1800 rt2x00pci_register_read(rt2x00dev
, MAC_CSR12
, ®2
);
1801 state
= rt2x00_get_field32(reg2
, MAC_CSR12_BBP_CURRENT_STATE
);
1802 if (state
== !put_to_sleep
)
1804 rt2x00pci_register_write(rt2x00dev
, MAC_CSR12
, reg
);
1811 static int rt61pci_set_device_state(struct rt2x00_dev
*rt2x00dev
,
1812 enum dev_state state
)
1817 case STATE_RADIO_ON
:
1818 retval
= rt61pci_enable_radio(rt2x00dev
);
1820 case STATE_RADIO_OFF
:
1821 rt61pci_disable_radio(rt2x00dev
);
1823 case STATE_RADIO_IRQ_ON
:
1824 case STATE_RADIO_IRQ_ON_ISR
:
1825 case STATE_RADIO_IRQ_OFF
:
1826 case STATE_RADIO_IRQ_OFF_ISR
:
1827 rt61pci_toggle_irq(rt2x00dev
, state
);
1829 case STATE_DEEP_SLEEP
:
1833 retval
= rt61pci_set_state(rt2x00dev
, state
);
1840 if (unlikely(retval
))
1841 ERROR(rt2x00dev
, "Device failed to enter state %d (%d).\n",
1848 * TX descriptor initialization
1850 static void rt61pci_write_tx_desc(struct queue_entry
*entry
,
1851 struct txentry_desc
*txdesc
)
1853 struct skb_frame_desc
*skbdesc
= get_skb_frame_desc(entry
->skb
);
1854 struct queue_entry_priv_pci
*entry_priv
= entry
->priv_data
;
1855 __le32
*txd
= entry_priv
->desc
;
1859 * Start writing the descriptor words.
1861 rt2x00_desc_read(txd
, 1, &word
);
1862 rt2x00_set_field32(&word
, TXD_W1_HOST_Q_ID
, entry
->queue
->qid
);
1863 rt2x00_set_field32(&word
, TXD_W1_AIFSN
, entry
->queue
->aifs
);
1864 rt2x00_set_field32(&word
, TXD_W1_CWMIN
, entry
->queue
->cw_min
);
1865 rt2x00_set_field32(&word
, TXD_W1_CWMAX
, entry
->queue
->cw_max
);
1866 rt2x00_set_field32(&word
, TXD_W1_IV_OFFSET
, txdesc
->iv_offset
);
1867 rt2x00_set_field32(&word
, TXD_W1_HW_SEQUENCE
,
1868 test_bit(ENTRY_TXD_GENERATE_SEQ
, &txdesc
->flags
));
1869 rt2x00_set_field32(&word
, TXD_W1_BUFFER_COUNT
, 1);
1870 rt2x00_desc_write(txd
, 1, word
);
1872 rt2x00_desc_read(txd
, 2, &word
);
1873 rt2x00_set_field32(&word
, TXD_W2_PLCP_SIGNAL
, txdesc
->signal
);
1874 rt2x00_set_field32(&word
, TXD_W2_PLCP_SERVICE
, txdesc
->service
);
1875 rt2x00_set_field32(&word
, TXD_W2_PLCP_LENGTH_LOW
, txdesc
->length_low
);
1876 rt2x00_set_field32(&word
, TXD_W2_PLCP_LENGTH_HIGH
, txdesc
->length_high
);
1877 rt2x00_desc_write(txd
, 2, word
);
1879 if (test_bit(ENTRY_TXD_ENCRYPT
, &txdesc
->flags
)) {
1880 _rt2x00_desc_write(txd
, 3, skbdesc
->iv
[0]);
1881 _rt2x00_desc_write(txd
, 4, skbdesc
->iv
[1]);
1884 rt2x00_desc_read(txd
, 5, &word
);
1885 rt2x00_set_field32(&word
, TXD_W5_PID_TYPE
, entry
->queue
->qid
);
1886 rt2x00_set_field32(&word
, TXD_W5_PID_SUBTYPE
,
1887 skbdesc
->entry
->entry_idx
);
1888 rt2x00_set_field32(&word
, TXD_W5_TX_POWER
,
1889 TXPOWER_TO_DEV(entry
->queue
->rt2x00dev
->tx_power
));
1890 rt2x00_set_field32(&word
, TXD_W5_WAITING_DMA_DONE_INT
, 1);
1891 rt2x00_desc_write(txd
, 5, word
);
1893 if (entry
->queue
->qid
!= QID_BEACON
) {
1894 rt2x00_desc_read(txd
, 6, &word
);
1895 rt2x00_set_field32(&word
, TXD_W6_BUFFER_PHYSICAL_ADDRESS
,
1897 rt2x00_desc_write(txd
, 6, word
);
1899 rt2x00_desc_read(txd
, 11, &word
);
1900 rt2x00_set_field32(&word
, TXD_W11_BUFFER_LENGTH0
,
1902 rt2x00_desc_write(txd
, 11, word
);
1906 * Writing TXD word 0 must the last to prevent a race condition with
1907 * the device, whereby the device may take hold of the TXD before we
1908 * finished updating it.
1910 rt2x00_desc_read(txd
, 0, &word
);
1911 rt2x00_set_field32(&word
, TXD_W0_OWNER_NIC
, 1);
1912 rt2x00_set_field32(&word
, TXD_W0_VALID
, 1);
1913 rt2x00_set_field32(&word
, TXD_W0_MORE_FRAG
,
1914 test_bit(ENTRY_TXD_MORE_FRAG
, &txdesc
->flags
));
1915 rt2x00_set_field32(&word
, TXD_W0_ACK
,
1916 test_bit(ENTRY_TXD_ACK
, &txdesc
->flags
));
1917 rt2x00_set_field32(&word
, TXD_W0_TIMESTAMP
,
1918 test_bit(ENTRY_TXD_REQ_TIMESTAMP
, &txdesc
->flags
));
1919 rt2x00_set_field32(&word
, TXD_W0_OFDM
,
1920 (txdesc
->rate_mode
== RATE_MODE_OFDM
));
1921 rt2x00_set_field32(&word
, TXD_W0_IFS
, txdesc
->ifs
);
1922 rt2x00_set_field32(&word
, TXD_W0_RETRY_MODE
,
1923 test_bit(ENTRY_TXD_RETRY_MODE
, &txdesc
->flags
));
1924 rt2x00_set_field32(&word
, TXD_W0_TKIP_MIC
,
1925 test_bit(ENTRY_TXD_ENCRYPT_MMIC
, &txdesc
->flags
));
1926 rt2x00_set_field32(&word
, TXD_W0_KEY_TABLE
,
1927 test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE
, &txdesc
->flags
));
1928 rt2x00_set_field32(&word
, TXD_W0_KEY_INDEX
, txdesc
->key_idx
);
1929 rt2x00_set_field32(&word
, TXD_W0_DATABYTE_COUNT
, txdesc
->length
);
1930 rt2x00_set_field32(&word
, TXD_W0_BURST
,
1931 test_bit(ENTRY_TXD_BURST
, &txdesc
->flags
));
1932 rt2x00_set_field32(&word
, TXD_W0_CIPHER_ALG
, txdesc
->cipher
);
1933 rt2x00_desc_write(txd
, 0, word
);
1936 * Register descriptor details in skb frame descriptor.
1938 skbdesc
->desc
= txd
;
1939 skbdesc
->desc_len
= (entry
->queue
->qid
== QID_BEACON
) ? TXINFO_SIZE
:
1944 * TX data initialization
1946 static void rt61pci_write_beacon(struct queue_entry
*entry
,
1947 struct txentry_desc
*txdesc
)
1949 struct rt2x00_dev
*rt2x00dev
= entry
->queue
->rt2x00dev
;
1950 struct queue_entry_priv_pci
*entry_priv
= entry
->priv_data
;
1951 unsigned int beacon_base
;
1952 unsigned int padding_len
;
1956 * Disable beaconing while we are reloading the beacon data,
1957 * otherwise we might be sending out invalid data.
1959 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR9
, ®
);
1960 rt2x00_set_field32(®
, TXRX_CSR9_BEACON_GEN
, 0);
1961 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR9
, reg
);
1964 * Write the TX descriptor for the beacon.
1966 rt61pci_write_tx_desc(entry
, txdesc
);
1969 * Dump beacon to userspace through debugfs.
1971 rt2x00debug_dump_frame(rt2x00dev
, DUMP_FRAME_BEACON
, entry
->skb
);
1974 * Write entire beacon with descriptor and padding to register.
1976 padding_len
= roundup(entry
->skb
->len
, 4) - entry
->skb
->len
;
1977 skb_pad(entry
->skb
, padding_len
);
1978 beacon_base
= HW_BEACON_OFFSET(entry
->entry_idx
);
1979 rt2x00pci_register_multiwrite(rt2x00dev
, beacon_base
,
1980 entry_priv
->desc
, TXINFO_SIZE
);
1981 rt2x00pci_register_multiwrite(rt2x00dev
, beacon_base
+ TXINFO_SIZE
,
1983 entry
->skb
->len
+ padding_len
);
1986 * Enable beaconing again.
1988 * For Wi-Fi faily generated beacons between participating
1989 * stations. Set TBTT phase adaptive adjustment step to 8us.
1991 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR10
, 0x00001008);
1993 rt2x00_set_field32(®
, TXRX_CSR9_BEACON_GEN
, 1);
1994 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR9
, reg
);
1997 * Clean up beacon skb.
1999 dev_kfree_skb_any(entry
->skb
);
2003 static void rt61pci_clear_beacon(struct queue_entry
*entry
)
2005 struct rt2x00_dev
*rt2x00dev
= entry
->queue
->rt2x00dev
;
2009 * Disable beaconing while we are reloading the beacon data,
2010 * otherwise we might be sending out invalid data.
2012 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR9
, ®
);
2013 rt2x00_set_field32(®
, TXRX_CSR9_BEACON_GEN
, 0);
2014 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR9
, reg
);
2019 rt2x00pci_register_write(rt2x00dev
,
2020 HW_BEACON_OFFSET(entry
->entry_idx
), 0);
2023 * Enable beaconing again.
2025 rt2x00_set_field32(®
, TXRX_CSR9_BEACON_GEN
, 1);
2026 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR9
, reg
);
2030 * RX control handlers
2032 static int rt61pci_agc_to_rssi(struct rt2x00_dev
*rt2x00dev
, int rxd_w1
)
2034 u8 offset
= rt2x00dev
->lna_gain
;
2037 lna
= rt2x00_get_field32(rxd_w1
, RXD_W1_RSSI_LNA
);
2052 if (rt2x00dev
->curr_band
== IEEE80211_BAND_5GHZ
) {
2053 if (lna
== 3 || lna
== 2)
2057 return rt2x00_get_field32(rxd_w1
, RXD_W1_RSSI_AGC
) * 2 - offset
;
2060 static void rt61pci_fill_rxdone(struct queue_entry
*entry
,
2061 struct rxdone_entry_desc
*rxdesc
)
2063 struct rt2x00_dev
*rt2x00dev
= entry
->queue
->rt2x00dev
;
2064 struct queue_entry_priv_pci
*entry_priv
= entry
->priv_data
;
2068 rt2x00_desc_read(entry_priv
->desc
, 0, &word0
);
2069 rt2x00_desc_read(entry_priv
->desc
, 1, &word1
);
2071 if (rt2x00_get_field32(word0
, RXD_W0_CRC_ERROR
))
2072 rxdesc
->flags
|= RX_FLAG_FAILED_FCS_CRC
;
2074 rxdesc
->cipher
= rt2x00_get_field32(word0
, RXD_W0_CIPHER_ALG
);
2075 rxdesc
->cipher_status
= rt2x00_get_field32(word0
, RXD_W0_CIPHER_ERROR
);
2077 if (rxdesc
->cipher
!= CIPHER_NONE
) {
2078 _rt2x00_desc_read(entry_priv
->desc
, 2, &rxdesc
->iv
[0]);
2079 _rt2x00_desc_read(entry_priv
->desc
, 3, &rxdesc
->iv
[1]);
2080 rxdesc
->dev_flags
|= RXDONE_CRYPTO_IV
;
2082 _rt2x00_desc_read(entry_priv
->desc
, 4, &rxdesc
->icv
);
2083 rxdesc
->dev_flags
|= RXDONE_CRYPTO_ICV
;
2086 * Hardware has stripped IV/EIV data from 802.11 frame during
2087 * decryption. It has provided the data separately but rt2x00lib
2088 * should decide if it should be reinserted.
2090 rxdesc
->flags
|= RX_FLAG_IV_STRIPPED
;
2093 * FIXME: Legacy driver indicates that the frame does
2094 * contain the Michael Mic. Unfortunately, in rt2x00
2095 * the MIC seems to be missing completely...
2097 rxdesc
->flags
|= RX_FLAG_MMIC_STRIPPED
;
2099 if (rxdesc
->cipher_status
== RX_CRYPTO_SUCCESS
)
2100 rxdesc
->flags
|= RX_FLAG_DECRYPTED
;
2101 else if (rxdesc
->cipher_status
== RX_CRYPTO_FAIL_MIC
)
2102 rxdesc
->flags
|= RX_FLAG_MMIC_ERROR
;
2106 * Obtain the status about this packet.
2107 * When frame was received with an OFDM bitrate,
2108 * the signal is the PLCP value. If it was received with
2109 * a CCK bitrate the signal is the rate in 100kbit/s.
2111 rxdesc
->signal
= rt2x00_get_field32(word1
, RXD_W1_SIGNAL
);
2112 rxdesc
->rssi
= rt61pci_agc_to_rssi(rt2x00dev
, word1
);
2113 rxdesc
->size
= rt2x00_get_field32(word0
, RXD_W0_DATABYTE_COUNT
);
2115 if (rt2x00_get_field32(word0
, RXD_W0_OFDM
))
2116 rxdesc
->dev_flags
|= RXDONE_SIGNAL_PLCP
;
2118 rxdesc
->dev_flags
|= RXDONE_SIGNAL_BITRATE
;
2119 if (rt2x00_get_field32(word0
, RXD_W0_MY_BSS
))
2120 rxdesc
->dev_flags
|= RXDONE_MY_BSS
;
2124 * Interrupt functions.
2126 static void rt61pci_txdone(struct rt2x00_dev
*rt2x00dev
)
2128 struct data_queue
*queue
;
2129 struct queue_entry
*entry
;
2130 struct queue_entry
*entry_done
;
2131 struct queue_entry_priv_pci
*entry_priv
;
2132 struct txdone_entry_desc txdesc
;
2140 * TX_STA_FIFO is a stack of X entries, hence read TX_STA_FIFO
2141 * at most X times and also stop processing once the TX_STA_FIFO_VALID
2142 * flag is not set anymore.
2144 * The legacy drivers use X=TX_RING_SIZE but state in a comment
2145 * that the TX_STA_FIFO stack has a size of 16. We stick to our
2146 * tx ring size for now.
2148 for (i
= 0; i
< rt2x00dev
->ops
->tx
->entry_num
; i
++) {
2149 rt2x00pci_register_read(rt2x00dev
, STA_CSR4
, ®
);
2150 if (!rt2x00_get_field32(reg
, STA_CSR4_VALID
))
2154 * Skip this entry when it contains an invalid
2155 * queue identication number.
2157 type
= rt2x00_get_field32(reg
, STA_CSR4_PID_TYPE
);
2158 queue
= rt2x00queue_get_queue(rt2x00dev
, type
);
2159 if (unlikely(!queue
))
2163 * Skip this entry when it contains an invalid
2166 index
= rt2x00_get_field32(reg
, STA_CSR4_PID_SUBTYPE
);
2167 if (unlikely(index
>= queue
->limit
))
2170 entry
= &queue
->entries
[index
];
2171 entry_priv
= entry
->priv_data
;
2172 rt2x00_desc_read(entry_priv
->desc
, 0, &word
);
2174 if (rt2x00_get_field32(word
, TXD_W0_OWNER_NIC
) ||
2175 !rt2x00_get_field32(word
, TXD_W0_VALID
))
2178 entry_done
= rt2x00queue_get_entry(queue
, Q_INDEX_DONE
);
2179 while (entry
!= entry_done
) {
2181 * Just report any entries we missed as failed.
2184 "TX status report missed for entry %d\n",
2185 entry_done
->entry_idx
);
2187 rt2x00lib_txdone_noinfo(entry_done
, TXDONE_UNKNOWN
);
2188 entry_done
= rt2x00queue_get_entry(queue
, Q_INDEX_DONE
);
2192 * Obtain the status about this packet.
2195 switch (rt2x00_get_field32(reg
, STA_CSR4_TX_RESULT
)) {
2196 case 0: /* Success, maybe with retry */
2197 __set_bit(TXDONE_SUCCESS
, &txdesc
.flags
);
2199 case 6: /* Failure, excessive retries */
2200 __set_bit(TXDONE_EXCESSIVE_RETRY
, &txdesc
.flags
);
2201 /* Don't break, this is a failed frame! */
2202 default: /* Failure */
2203 __set_bit(TXDONE_FAILURE
, &txdesc
.flags
);
2205 txdesc
.retry
= rt2x00_get_field32(reg
, STA_CSR4_RETRY_COUNT
);
2208 * the frame was retried at least once
2209 * -> hw used fallback rates
2212 __set_bit(TXDONE_FALLBACK
, &txdesc
.flags
);
2214 rt2x00lib_txdone(entry
, &txdesc
);
2218 static void rt61pci_wakeup(struct rt2x00_dev
*rt2x00dev
)
2220 struct ieee80211_conf conf
= { .flags
= 0 };
2221 struct rt2x00lib_conf libconf
= { .conf
= &conf
};
2223 rt61pci_config(rt2x00dev
, &libconf
, IEEE80211_CONF_CHANGE_PS
);
2226 static irqreturn_t
rt61pci_interrupt_thread(int irq
, void *dev_instance
)
2228 struct rt2x00_dev
*rt2x00dev
= dev_instance
;
2229 u32 reg
= rt2x00dev
->irqvalue
[0];
2230 u32 reg_mcu
= rt2x00dev
->irqvalue
[1];
2233 * Handle interrupts, walk through all bits
2234 * and run the tasks, the bits are checked in order of
2239 * 1 - Rx ring done interrupt.
2241 if (rt2x00_get_field32(reg
, INT_SOURCE_CSR_RXDONE
))
2242 rt2x00pci_rxdone(rt2x00dev
);
2245 * 2 - Tx ring done interrupt.
2247 if (rt2x00_get_field32(reg
, INT_SOURCE_CSR_TXDONE
))
2248 rt61pci_txdone(rt2x00dev
);
2251 * 3 - Handle MCU command done.
2254 rt2x00pci_register_write(rt2x00dev
,
2255 M2H_CMD_DONE_CSR
, 0xffffffff);
2258 * 4 - MCU Autowakeup interrupt.
2260 if (rt2x00_get_field32(reg_mcu
, MCU_INT_SOURCE_CSR_TWAKEUP
))
2261 rt61pci_wakeup(rt2x00dev
);
2264 * 5 - Beacon done interrupt.
2266 if (rt2x00_get_field32(reg
, INT_SOURCE_CSR_BEACON_DONE
))
2267 rt2x00lib_beacondone(rt2x00dev
);
2269 /* Enable interrupts again. */
2270 rt2x00dev
->ops
->lib
->set_device_state(rt2x00dev
,
2271 STATE_RADIO_IRQ_ON_ISR
);
2276 static irqreturn_t
rt61pci_interrupt(int irq
, void *dev_instance
)
2278 struct rt2x00_dev
*rt2x00dev
= dev_instance
;
2283 * Get the interrupt sources & saved to local variable.
2284 * Write register value back to clear pending interrupts.
2286 rt2x00pci_register_read(rt2x00dev
, MCU_INT_SOURCE_CSR
, ®_mcu
);
2287 rt2x00pci_register_write(rt2x00dev
, MCU_INT_SOURCE_CSR
, reg_mcu
);
2289 rt2x00pci_register_read(rt2x00dev
, INT_SOURCE_CSR
, ®
);
2290 rt2x00pci_register_write(rt2x00dev
, INT_SOURCE_CSR
, reg
);
2292 if (!reg
&& !reg_mcu
)
2295 if (!test_bit(DEVICE_STATE_ENABLED_RADIO
, &rt2x00dev
->flags
))
2298 /* Store irqvalues for use in the interrupt thread. */
2299 rt2x00dev
->irqvalue
[0] = reg
;
2300 rt2x00dev
->irqvalue
[1] = reg_mcu
;
2302 /* Disable interrupts, will be enabled again in the interrupt thread. */
2303 rt2x00dev
->ops
->lib
->set_device_state(rt2x00dev
,
2304 STATE_RADIO_IRQ_OFF_ISR
);
2305 return IRQ_WAKE_THREAD
;
2309 * Device probe functions.
2311 static int rt61pci_validate_eeprom(struct rt2x00_dev
*rt2x00dev
)
2313 struct eeprom_93cx6 eeprom
;
2319 rt2x00pci_register_read(rt2x00dev
, E2PROM_CSR
, ®
);
2321 eeprom
.data
= rt2x00dev
;
2322 eeprom
.register_read
= rt61pci_eepromregister_read
;
2323 eeprom
.register_write
= rt61pci_eepromregister_write
;
2324 eeprom
.width
= rt2x00_get_field32(reg
, E2PROM_CSR_TYPE_93C46
) ?
2325 PCI_EEPROM_WIDTH_93C46
: PCI_EEPROM_WIDTH_93C66
;
2326 eeprom
.reg_data_in
= 0;
2327 eeprom
.reg_data_out
= 0;
2328 eeprom
.reg_data_clock
= 0;
2329 eeprom
.reg_chip_select
= 0;
2331 eeprom_93cx6_multiread(&eeprom
, EEPROM_BASE
, rt2x00dev
->eeprom
,
2332 EEPROM_SIZE
/ sizeof(u16
));
2335 * Start validation of the data that has been read.
2337 mac
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_MAC_ADDR_0
);
2338 if (!is_valid_ether_addr(mac
)) {
2339 random_ether_addr(mac
);
2340 EEPROM(rt2x00dev
, "MAC: %pM\n", mac
);
2343 rt2x00_eeprom_read(rt2x00dev
, EEPROM_ANTENNA
, &word
);
2344 if (word
== 0xffff) {
2345 rt2x00_set_field16(&word
, EEPROM_ANTENNA_NUM
, 2);
2346 rt2x00_set_field16(&word
, EEPROM_ANTENNA_TX_DEFAULT
,
2348 rt2x00_set_field16(&word
, EEPROM_ANTENNA_RX_DEFAULT
,
2350 rt2x00_set_field16(&word
, EEPROM_ANTENNA_FRAME_TYPE
, 0);
2351 rt2x00_set_field16(&word
, EEPROM_ANTENNA_DYN_TXAGC
, 0);
2352 rt2x00_set_field16(&word
, EEPROM_ANTENNA_HARDWARE_RADIO
, 0);
2353 rt2x00_set_field16(&word
, EEPROM_ANTENNA_RF_TYPE
, RF5225
);
2354 rt2x00_eeprom_write(rt2x00dev
, EEPROM_ANTENNA
, word
);
2355 EEPROM(rt2x00dev
, "Antenna: 0x%04x\n", word
);
2358 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC
, &word
);
2359 if (word
== 0xffff) {
2360 rt2x00_set_field16(&word
, EEPROM_NIC_ENABLE_DIVERSITY
, 0);
2361 rt2x00_set_field16(&word
, EEPROM_NIC_TX_DIVERSITY
, 0);
2362 rt2x00_set_field16(&word
, EEPROM_NIC_RX_FIXED
, 0);
2363 rt2x00_set_field16(&word
, EEPROM_NIC_TX_FIXED
, 0);
2364 rt2x00_set_field16(&word
, EEPROM_NIC_EXTERNAL_LNA_BG
, 0);
2365 rt2x00_set_field16(&word
, EEPROM_NIC_CARDBUS_ACCEL
, 0);
2366 rt2x00_set_field16(&word
, EEPROM_NIC_EXTERNAL_LNA_A
, 0);
2367 rt2x00_eeprom_write(rt2x00dev
, EEPROM_NIC
, word
);
2368 EEPROM(rt2x00dev
, "NIC: 0x%04x\n", word
);
2371 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LED
, &word
);
2372 if (word
== 0xffff) {
2373 rt2x00_set_field16(&word
, EEPROM_LED_LED_MODE
,
2375 rt2x00_eeprom_write(rt2x00dev
, EEPROM_LED
, word
);
2376 EEPROM(rt2x00dev
, "Led: 0x%04x\n", word
);
2379 rt2x00_eeprom_read(rt2x00dev
, EEPROM_FREQ
, &word
);
2380 if (word
== 0xffff) {
2381 rt2x00_set_field16(&word
, EEPROM_FREQ_OFFSET
, 0);
2382 rt2x00_set_field16(&word
, EEPROM_FREQ_SEQ
, 0);
2383 rt2x00_eeprom_write(rt2x00dev
, EEPROM_FREQ
, word
);
2384 EEPROM(rt2x00dev
, "Freq: 0x%04x\n", word
);
2387 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_OFFSET_BG
, &word
);
2388 if (word
== 0xffff) {
2389 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_BG_1
, 0);
2390 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_BG_2
, 0);
2391 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_OFFSET_BG
, word
);
2392 EEPROM(rt2x00dev
, "RSSI OFFSET BG: 0x%04x\n", word
);
2394 value
= rt2x00_get_field16(word
, EEPROM_RSSI_OFFSET_BG_1
);
2395 if (value
< -10 || value
> 10)
2396 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_BG_1
, 0);
2397 value
= rt2x00_get_field16(word
, EEPROM_RSSI_OFFSET_BG_2
);
2398 if (value
< -10 || value
> 10)
2399 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_BG_2
, 0);
2400 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_OFFSET_BG
, word
);
2403 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_OFFSET_A
, &word
);
2404 if (word
== 0xffff) {
2405 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_A_1
, 0);
2406 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_A_2
, 0);
2407 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_OFFSET_A
, word
);
2408 EEPROM(rt2x00dev
, "RSSI OFFSET A: 0x%04x\n", word
);
2410 value
= rt2x00_get_field16(word
, EEPROM_RSSI_OFFSET_A_1
);
2411 if (value
< -10 || value
> 10)
2412 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_A_1
, 0);
2413 value
= rt2x00_get_field16(word
, EEPROM_RSSI_OFFSET_A_2
);
2414 if (value
< -10 || value
> 10)
2415 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_A_2
, 0);
2416 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_OFFSET_A
, word
);
2422 static int rt61pci_init_eeprom(struct rt2x00_dev
*rt2x00dev
)
2429 * Read EEPROM word for configuration.
2431 rt2x00_eeprom_read(rt2x00dev
, EEPROM_ANTENNA
, &eeprom
);
2434 * Identify RF chipset.
2436 value
= rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_RF_TYPE
);
2437 rt2x00pci_register_read(rt2x00dev
, MAC_CSR0
, ®
);
2438 rt2x00_set_chip(rt2x00dev
, rt2x00_get_field32(reg
, MAC_CSR0_CHIPSET
),
2439 value
, rt2x00_get_field32(reg
, MAC_CSR0_REVISION
));
2441 if (!rt2x00_rf(rt2x00dev
, RF5225
) &&
2442 !rt2x00_rf(rt2x00dev
, RF5325
) &&
2443 !rt2x00_rf(rt2x00dev
, RF2527
) &&
2444 !rt2x00_rf(rt2x00dev
, RF2529
)) {
2445 ERROR(rt2x00dev
, "Invalid RF chipset detected.\n");
2450 * Determine number of antennas.
2452 if (rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_NUM
) == 2)
2453 __set_bit(CONFIG_DOUBLE_ANTENNA
, &rt2x00dev
->flags
);
2456 * Identify default antenna configuration.
2458 rt2x00dev
->default_ant
.tx
=
2459 rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_TX_DEFAULT
);
2460 rt2x00dev
->default_ant
.rx
=
2461 rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_RX_DEFAULT
);
2464 * Read the Frame type.
2466 if (rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_FRAME_TYPE
))
2467 __set_bit(CONFIG_FRAME_TYPE
, &rt2x00dev
->flags
);
2470 * Detect if this device has a hardware controlled radio.
2472 if (rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_HARDWARE_RADIO
))
2473 __set_bit(CONFIG_SUPPORT_HW_BUTTON
, &rt2x00dev
->flags
);
2476 * Read frequency offset and RF programming sequence.
2478 rt2x00_eeprom_read(rt2x00dev
, EEPROM_FREQ
, &eeprom
);
2479 if (rt2x00_get_field16(eeprom
, EEPROM_FREQ_SEQ
))
2480 __set_bit(CONFIG_RF_SEQUENCE
, &rt2x00dev
->flags
);
2482 rt2x00dev
->freq_offset
= rt2x00_get_field16(eeprom
, EEPROM_FREQ_OFFSET
);
2485 * Read external LNA informations.
2487 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC
, &eeprom
);
2489 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_EXTERNAL_LNA_A
))
2490 __set_bit(CONFIG_EXTERNAL_LNA_A
, &rt2x00dev
->flags
);
2491 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_EXTERNAL_LNA_BG
))
2492 __set_bit(CONFIG_EXTERNAL_LNA_BG
, &rt2x00dev
->flags
);
2495 * When working with a RF2529 chip without double antenna,
2496 * the antenna settings should be gathered from the NIC
2499 if (rt2x00_rf(rt2x00dev
, RF2529
) &&
2500 !test_bit(CONFIG_DOUBLE_ANTENNA
, &rt2x00dev
->flags
)) {
2501 rt2x00dev
->default_ant
.rx
=
2502 ANTENNA_A
+ rt2x00_get_field16(eeprom
, EEPROM_NIC_RX_FIXED
);
2503 rt2x00dev
->default_ant
.tx
=
2504 ANTENNA_B
- rt2x00_get_field16(eeprom
, EEPROM_NIC_TX_FIXED
);
2506 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_TX_DIVERSITY
))
2507 rt2x00dev
->default_ant
.tx
= ANTENNA_SW_DIVERSITY
;
2508 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_ENABLE_DIVERSITY
))
2509 rt2x00dev
->default_ant
.rx
= ANTENNA_SW_DIVERSITY
;
2513 * Store led settings, for correct led behaviour.
2514 * If the eeprom value is invalid,
2515 * switch to default led mode.
2517 #ifdef CONFIG_RT2X00_LIB_LEDS
2518 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LED
, &eeprom
);
2519 value
= rt2x00_get_field16(eeprom
, EEPROM_LED_LED_MODE
);
2521 rt61pci_init_led(rt2x00dev
, &rt2x00dev
->led_radio
, LED_TYPE_RADIO
);
2522 rt61pci_init_led(rt2x00dev
, &rt2x00dev
->led_assoc
, LED_TYPE_ASSOC
);
2523 if (value
== LED_MODE_SIGNAL_STRENGTH
)
2524 rt61pci_init_led(rt2x00dev
, &rt2x00dev
->led_qual
,
2527 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_LED_MODE
, value
);
2528 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_GPIO_0
,
2529 rt2x00_get_field16(eeprom
,
2530 EEPROM_LED_POLARITY_GPIO_0
));
2531 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_GPIO_1
,
2532 rt2x00_get_field16(eeprom
,
2533 EEPROM_LED_POLARITY_GPIO_1
));
2534 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_GPIO_2
,
2535 rt2x00_get_field16(eeprom
,
2536 EEPROM_LED_POLARITY_GPIO_2
));
2537 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_GPIO_3
,
2538 rt2x00_get_field16(eeprom
,
2539 EEPROM_LED_POLARITY_GPIO_3
));
2540 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_GPIO_4
,
2541 rt2x00_get_field16(eeprom
,
2542 EEPROM_LED_POLARITY_GPIO_4
));
2543 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_ACT
,
2544 rt2x00_get_field16(eeprom
, EEPROM_LED_POLARITY_ACT
));
2545 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_READY_BG
,
2546 rt2x00_get_field16(eeprom
,
2547 EEPROM_LED_POLARITY_RDY_G
));
2548 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_READY_A
,
2549 rt2x00_get_field16(eeprom
,
2550 EEPROM_LED_POLARITY_RDY_A
));
2551 #endif /* CONFIG_RT2X00_LIB_LEDS */
2557 * RF value list for RF5225 & RF5325
2558 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled
2560 static const struct rf_channel rf_vals_noseq
[] = {
2561 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2562 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2563 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2564 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2565 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2566 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2567 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2568 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2569 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2570 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2571 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2572 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2573 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2574 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2576 /* 802.11 UNI / HyperLan 2 */
2577 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2578 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2579 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2580 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2581 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2582 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2583 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2584 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2586 /* 802.11 HyperLan 2 */
2587 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2588 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2589 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2590 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2591 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2592 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2593 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2594 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2595 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2596 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2599 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2600 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2601 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2602 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2603 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2604 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2606 /* MMAC(Japan)J52 ch 34,38,42,46 */
2607 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2608 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2609 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2610 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2614 * RF value list for RF5225 & RF5325
2615 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled
2617 static const struct rf_channel rf_vals_seq
[] = {
2618 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2619 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2620 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2621 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2622 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2623 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2624 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2625 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2626 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2627 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2628 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2629 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2630 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2631 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2633 /* 802.11 UNI / HyperLan 2 */
2634 { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 },
2635 { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 },
2636 { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b },
2637 { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b },
2638 { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 },
2639 { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 },
2640 { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 },
2641 { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b },
2643 /* 802.11 HyperLan 2 */
2644 { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 },
2645 { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 },
2646 { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 },
2647 { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 },
2648 { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 },
2649 { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 },
2650 { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b },
2651 { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b },
2652 { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 },
2653 { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 },
2656 { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 },
2657 { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b },
2658 { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b },
2659 { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 },
2660 { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 },
2661 { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 },
2663 /* MMAC(Japan)J52 ch 34,38,42,46 */
2664 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b },
2665 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 },
2666 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b },
2667 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 },
2670 static int rt61pci_probe_hw_mode(struct rt2x00_dev
*rt2x00dev
)
2672 struct hw_mode_spec
*spec
= &rt2x00dev
->spec
;
2673 struct channel_info
*info
;
2678 * Disable powersaving as default.
2680 rt2x00dev
->hw
->wiphy
->flags
&= ~WIPHY_FLAG_PS_ON_BY_DEFAULT
;
2683 * Initialize all hw fields.
2685 rt2x00dev
->hw
->flags
=
2686 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING
|
2687 IEEE80211_HW_SIGNAL_DBM
|
2688 IEEE80211_HW_SUPPORTS_PS
|
2689 IEEE80211_HW_PS_NULLFUNC_STACK
;
2691 SET_IEEE80211_DEV(rt2x00dev
->hw
, rt2x00dev
->dev
);
2692 SET_IEEE80211_PERM_ADDR(rt2x00dev
->hw
,
2693 rt2x00_eeprom_addr(rt2x00dev
,
2694 EEPROM_MAC_ADDR_0
));
2697 * As rt61 has a global fallback table we cannot specify
2698 * more then one tx rate per frame but since the hw will
2699 * try several rates (based on the fallback table) we should
2700 * initialize max_report_rates to the maximum number of rates
2701 * we are going to try. Otherwise mac80211 will truncate our
2702 * reported tx rates and the rc algortihm will end up with
2705 rt2x00dev
->hw
->max_rates
= 1;
2706 rt2x00dev
->hw
->max_report_rates
= 7;
2707 rt2x00dev
->hw
->max_rate_tries
= 1;
2710 * Initialize hw_mode information.
2712 spec
->supported_bands
= SUPPORT_BAND_2GHZ
;
2713 spec
->supported_rates
= SUPPORT_RATE_CCK
| SUPPORT_RATE_OFDM
;
2715 if (!test_bit(CONFIG_RF_SEQUENCE
, &rt2x00dev
->flags
)) {
2716 spec
->num_channels
= 14;
2717 spec
->channels
= rf_vals_noseq
;
2719 spec
->num_channels
= 14;
2720 spec
->channels
= rf_vals_seq
;
2723 if (rt2x00_rf(rt2x00dev
, RF5225
) || rt2x00_rf(rt2x00dev
, RF5325
)) {
2724 spec
->supported_bands
|= SUPPORT_BAND_5GHZ
;
2725 spec
->num_channels
= ARRAY_SIZE(rf_vals_seq
);
2729 * Create channel information array
2731 info
= kcalloc(spec
->num_channels
, sizeof(*info
), GFP_KERNEL
);
2735 spec
->channels_info
= info
;
2737 tx_power
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_G_START
);
2738 for (i
= 0; i
< 14; i
++) {
2739 info
[i
].max_power
= MAX_TXPOWER
;
2740 info
[i
].default_power1
= TXPOWER_FROM_DEV(tx_power
[i
]);
2743 if (spec
->num_channels
> 14) {
2744 tx_power
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_A_START
);
2745 for (i
= 14; i
< spec
->num_channels
; i
++) {
2746 info
[i
].max_power
= MAX_TXPOWER
;
2747 info
[i
].default_power1
= TXPOWER_FROM_DEV(tx_power
[i
]);
2754 static int rt61pci_probe_hw(struct rt2x00_dev
*rt2x00dev
)
2759 * Disable power saving.
2761 rt2x00pci_register_write(rt2x00dev
, SOFT_RESET_CSR
, 0x00000007);
2764 * Allocate eeprom data.
2766 retval
= rt61pci_validate_eeprom(rt2x00dev
);
2770 retval
= rt61pci_init_eeprom(rt2x00dev
);
2775 * Initialize hw specifications.
2777 retval
= rt61pci_probe_hw_mode(rt2x00dev
);
2782 * This device has multiple filters for control frames,
2783 * but has no a separate filter for PS Poll frames.
2785 __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS
, &rt2x00dev
->flags
);
2788 * This device requires firmware and DMA mapped skbs.
2790 __set_bit(DRIVER_REQUIRE_FIRMWARE
, &rt2x00dev
->flags
);
2791 __set_bit(DRIVER_REQUIRE_DMA
, &rt2x00dev
->flags
);
2792 if (!modparam_nohwcrypt
)
2793 __set_bit(CONFIG_SUPPORT_HW_CRYPTO
, &rt2x00dev
->flags
);
2794 __set_bit(DRIVER_SUPPORT_LINK_TUNING
, &rt2x00dev
->flags
);
2797 * Set the rssi offset.
2799 rt2x00dev
->rssi_offset
= DEFAULT_RSSI_OFFSET
;
2805 * IEEE80211 stack callback functions.
2807 static int rt61pci_conf_tx(struct ieee80211_hw
*hw
, u16 queue_idx
,
2808 const struct ieee80211_tx_queue_params
*params
)
2810 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
2811 struct data_queue
*queue
;
2812 struct rt2x00_field32 field
;
2818 * First pass the configuration through rt2x00lib, that will
2819 * update the queue settings and validate the input. After that
2820 * we are free to update the registers based on the value
2821 * in the queue parameter.
2823 retval
= rt2x00mac_conf_tx(hw
, queue_idx
, params
);
2828 * We only need to perform additional register initialization
2834 queue
= rt2x00queue_get_queue(rt2x00dev
, queue_idx
);
2836 /* Update WMM TXOP register */
2837 offset
= AC_TXOP_CSR0
+ (sizeof(u32
) * (!!(queue_idx
& 2)));
2838 field
.bit_offset
= (queue_idx
& 1) * 16;
2839 field
.bit_mask
= 0xffff << field
.bit_offset
;
2841 rt2x00pci_register_read(rt2x00dev
, offset
, ®
);
2842 rt2x00_set_field32(®
, field
, queue
->txop
);
2843 rt2x00pci_register_write(rt2x00dev
, offset
, reg
);
2845 /* Update WMM registers */
2846 field
.bit_offset
= queue_idx
* 4;
2847 field
.bit_mask
= 0xf << field
.bit_offset
;
2849 rt2x00pci_register_read(rt2x00dev
, AIFSN_CSR
, ®
);
2850 rt2x00_set_field32(®
, field
, queue
->aifs
);
2851 rt2x00pci_register_write(rt2x00dev
, AIFSN_CSR
, reg
);
2853 rt2x00pci_register_read(rt2x00dev
, CWMIN_CSR
, ®
);
2854 rt2x00_set_field32(®
, field
, queue
->cw_min
);
2855 rt2x00pci_register_write(rt2x00dev
, CWMIN_CSR
, reg
);
2857 rt2x00pci_register_read(rt2x00dev
, CWMAX_CSR
, ®
);
2858 rt2x00_set_field32(®
, field
, queue
->cw_max
);
2859 rt2x00pci_register_write(rt2x00dev
, CWMAX_CSR
, reg
);
2864 static u64
rt61pci_get_tsf(struct ieee80211_hw
*hw
)
2866 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
2870 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR13
, ®
);
2871 tsf
= (u64
) rt2x00_get_field32(reg
, TXRX_CSR13_HIGH_TSFTIMER
) << 32;
2872 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR12
, ®
);
2873 tsf
|= rt2x00_get_field32(reg
, TXRX_CSR12_LOW_TSFTIMER
);
2878 static const struct ieee80211_ops rt61pci_mac80211_ops
= {
2880 .start
= rt2x00mac_start
,
2881 .stop
= rt2x00mac_stop
,
2882 .add_interface
= rt2x00mac_add_interface
,
2883 .remove_interface
= rt2x00mac_remove_interface
,
2884 .config
= rt2x00mac_config
,
2885 .configure_filter
= rt2x00mac_configure_filter
,
2886 .set_key
= rt2x00mac_set_key
,
2887 .sw_scan_start
= rt2x00mac_sw_scan_start
,
2888 .sw_scan_complete
= rt2x00mac_sw_scan_complete
,
2889 .get_stats
= rt2x00mac_get_stats
,
2890 .bss_info_changed
= rt2x00mac_bss_info_changed
,
2891 .conf_tx
= rt61pci_conf_tx
,
2892 .get_tsf
= rt61pci_get_tsf
,
2893 .rfkill_poll
= rt2x00mac_rfkill_poll
,
2894 .flush
= rt2x00mac_flush
,
2897 static const struct rt2x00lib_ops rt61pci_rt2x00_ops
= {
2898 .irq_handler
= rt61pci_interrupt
,
2899 .irq_handler_thread
= rt61pci_interrupt_thread
,
2900 .probe_hw
= rt61pci_probe_hw
,
2901 .get_firmware_name
= rt61pci_get_firmware_name
,
2902 .check_firmware
= rt61pci_check_firmware
,
2903 .load_firmware
= rt61pci_load_firmware
,
2904 .initialize
= rt2x00pci_initialize
,
2905 .uninitialize
= rt2x00pci_uninitialize
,
2906 .get_entry_state
= rt61pci_get_entry_state
,
2907 .clear_entry
= rt61pci_clear_entry
,
2908 .set_device_state
= rt61pci_set_device_state
,
2909 .rfkill_poll
= rt61pci_rfkill_poll
,
2910 .link_stats
= rt61pci_link_stats
,
2911 .reset_tuner
= rt61pci_reset_tuner
,
2912 .link_tuner
= rt61pci_link_tuner
,
2913 .start_queue
= rt61pci_start_queue
,
2914 .kick_queue
= rt61pci_kick_queue
,
2915 .stop_queue
= rt61pci_stop_queue
,
2916 .write_tx_desc
= rt61pci_write_tx_desc
,
2917 .write_beacon
= rt61pci_write_beacon
,
2918 .clear_beacon
= rt61pci_clear_beacon
,
2919 .fill_rxdone
= rt61pci_fill_rxdone
,
2920 .config_shared_key
= rt61pci_config_shared_key
,
2921 .config_pairwise_key
= rt61pci_config_pairwise_key
,
2922 .config_filter
= rt61pci_config_filter
,
2923 .config_intf
= rt61pci_config_intf
,
2924 .config_erp
= rt61pci_config_erp
,
2925 .config_ant
= rt61pci_config_ant
,
2926 .config
= rt61pci_config
,
2929 static const struct data_queue_desc rt61pci_queue_rx
= {
2931 .data_size
= DATA_FRAME_SIZE
,
2932 .desc_size
= RXD_DESC_SIZE
,
2933 .priv_size
= sizeof(struct queue_entry_priv_pci
),
2936 static const struct data_queue_desc rt61pci_queue_tx
= {
2938 .data_size
= DATA_FRAME_SIZE
,
2939 .desc_size
= TXD_DESC_SIZE
,
2940 .priv_size
= sizeof(struct queue_entry_priv_pci
),
2943 static const struct data_queue_desc rt61pci_queue_bcn
= {
2945 .data_size
= 0, /* No DMA required for beacons */
2946 .desc_size
= TXINFO_SIZE
,
2947 .priv_size
= sizeof(struct queue_entry_priv_pci
),
2950 static const struct rt2x00_ops rt61pci_ops
= {
2951 .name
= KBUILD_MODNAME
,
2954 .eeprom_size
= EEPROM_SIZE
,
2956 .tx_queues
= NUM_TX_QUEUES
,
2957 .extra_tx_headroom
= 0,
2958 .rx
= &rt61pci_queue_rx
,
2959 .tx
= &rt61pci_queue_tx
,
2960 .bcn
= &rt61pci_queue_bcn
,
2961 .lib
= &rt61pci_rt2x00_ops
,
2962 .hw
= &rt61pci_mac80211_ops
,
2963 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2964 .debugfs
= &rt61pci_rt2x00debug
,
2965 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2969 * RT61pci module information.
2971 static DEFINE_PCI_DEVICE_TABLE(rt61pci_device_table
) = {
2973 { PCI_DEVICE(0x1814, 0x0301), PCI_DEVICE_DATA(&rt61pci_ops
) },
2975 { PCI_DEVICE(0x1814, 0x0302), PCI_DEVICE_DATA(&rt61pci_ops
) },
2977 { PCI_DEVICE(0x1814, 0x0401), PCI_DEVICE_DATA(&rt61pci_ops
) },
2981 MODULE_AUTHOR(DRV_PROJECT
);
2982 MODULE_VERSION(DRV_VERSION
);
2983 MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver.");
2984 MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 "
2985 "PCI & PCMCIA chipset based cards");
2986 MODULE_DEVICE_TABLE(pci
, rt61pci_device_table
);
2987 MODULE_FIRMWARE(FIRMWARE_RT2561
);
2988 MODULE_FIRMWARE(FIRMWARE_RT2561s
);
2989 MODULE_FIRMWARE(FIRMWARE_RT2661
);
2990 MODULE_LICENSE("GPL");
2992 static struct pci_driver rt61pci_driver
= {
2993 .name
= KBUILD_MODNAME
,
2994 .id_table
= rt61pci_device_table
,
2995 .probe
= rt2x00pci_probe
,
2996 .remove
= __devexit_p(rt2x00pci_remove
),
2997 .suspend
= rt2x00pci_suspend
,
2998 .resume
= rt2x00pci_resume
,
3001 static int __init
rt61pci_init(void)
3003 return pci_register_driver(&rt61pci_driver
);
3006 static void __exit
rt61pci_exit(void)
3008 pci_unregister_driver(&rt61pci_driver
);
3011 module_init(rt61pci_init
);
3012 module_exit(rt61pci_exit
);