drivers/net/wireless/rt2x00/rt61pci.h

   1 /*
   2         Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt61pci
  23         Abstract: Data structures and registers for the rt61pci module.
  24         Supported chipsets: RT2561, RT2561s, RT2661.
  25  */
  26
  27 #ifndef RT61PCI_H
  28 #define RT61PCI_H
  29
  30 /*
  31  * RF chip defines.
  32  */
  33 #define RF5225                          0x0001
  34 #define RF5325                          0x0002
  35 #define RF2527                          0x0003
  36 #define RF2529                          0x0004
  37
  38 /*
  39  * Signal information.
  40  * Defaul offset is required for RSSI <-> dBm conversion.
  41  */
  42 #define DEFAULT_RSSI_OFFSET             120
  43
  44 /*
  45  * Register layout information.
  46  */
  47 #define CSR_REG_BASE                    0x3000
  48 #define CSR_REG_SIZE                    0x04b0
  49 #define EEPROM_BASE                     0x0000
  50 #define EEPROM_SIZE                     0x0100
  51 #define BBP_BASE                        0x0000
  52 #define BBP_SIZE                        0x0080
  53 #define RF_BASE                         0x0004
  54 #define RF_SIZE                         0x0010
  55
  56 /*
  57  * Number of TX queues.
  58  */
  59 #define NUM_TX_QUEUES                   4
  60
  61 /*
  62  * PCI registers.
  63  */
  64
  65 /*
  66  * PCI Configuration Header
  67  */
  68 #define PCI_CONFIG_HEADER_VENDOR        0x0000
  69 #define PCI_CONFIG_HEADER_DEVICE        0x0002
  70
  71 /*
  72  * HOST_CMD_CSR: For HOST to interrupt embedded processor
  73  */
  74 #define HOST_CMD_CSR                    0x0008
  75 #define HOST_CMD_CSR_HOST_COMMAND       FIELD32(0x0000007f)
  76 #define HOST_CMD_CSR_INTERRUPT_MCU      FIELD32(0x00000080)
  77
  78 /*
  79  * MCU_CNTL_CSR
  80  * SELECT_BANK: Select 8051 program bank.
  81  * RESET: Enable 8051 reset state.
  82  * READY: Ready state for 8051.
  83  */
  84 #define MCU_CNTL_CSR                    0x000c
  85 #define MCU_CNTL_CSR_SELECT_BANK        FIELD32(0x00000001)
  86 #define MCU_CNTL_CSR_RESET              FIELD32(0x00000002)
  87 #define MCU_CNTL_CSR_READY              FIELD32(0x00000004)
  88
  89 /*
  90  * SOFT_RESET_CSR
  91  * FORCE_CLOCK_ON: Host force MAC clock ON
  92  */
  93 #define SOFT_RESET_CSR                  0x0010
  94 #define SOFT_RESET_CSR_FORCE_CLOCK_ON   FIELD32(0x00000002)
  95
  96 /*
  97  * MCU_INT_SOURCE_CSR: MCU interrupt source/mask register.
  98  */
  99 #define MCU_INT_SOURCE_CSR              0x0014
 100 #define MCU_INT_SOURCE_CSR_0            FIELD32(0x00000001)
 101 #define MCU_INT_SOURCE_CSR_1            FIELD32(0x00000002)
 102 #define MCU_INT_SOURCE_CSR_2            FIELD32(0x00000004)
 103 #define MCU_INT_SOURCE_CSR_3            FIELD32(0x00000008)
 104 #define MCU_INT_SOURCE_CSR_4            FIELD32(0x00000010)
 105 #define MCU_INT_SOURCE_CSR_5            FIELD32(0x00000020)
 106 #define MCU_INT_SOURCE_CSR_6            FIELD32(0x00000040)
 107 #define MCU_INT_SOURCE_CSR_7            FIELD32(0x00000080)
 108 #define MCU_INT_SOURCE_CSR_TWAKEUP      FIELD32(0x00000100)
 109 #define MCU_INT_SOURCE_CSR_TBTT_EXPIRE  FIELD32(0x00000200)
 110
 111 /*
 112  * MCU_INT_MASK_CSR: MCU interrupt source/mask register.
 113  */
 114 #define MCU_INT_MASK_CSR                0x0018
 115 #define MCU_INT_MASK_CSR_0              FIELD32(0x00000001)
 116 #define MCU_INT_MASK_CSR_1              FIELD32(0x00000002)
 117 #define MCU_INT_MASK_CSR_2              FIELD32(0x00000004)
 118 #define MCU_INT_MASK_CSR_3              FIELD32(0x00000008)
 119 #define MCU_INT_MASK_CSR_4              FIELD32(0x00000010)
 120 #define MCU_INT_MASK_CSR_5              FIELD32(0x00000020)
 121 #define MCU_INT_MASK_CSR_6              FIELD32(0x00000040)
 122 #define MCU_INT_MASK_CSR_7              FIELD32(0x00000080)
 123 #define MCU_INT_MASK_CSR_TWAKEUP        FIELD32(0x00000100)
 124 #define MCU_INT_MASK_CSR_TBTT_EXPIRE    FIELD32(0x00000200)
 125
 126 /*
 127  * PCI_USEC_CSR
 128  */
 129 #define PCI_USEC_CSR                    0x001c
 130
 131 /*
 132  * Security key table memory.
 133  * 16 entries 32-byte for shared key table
 134  * 64 entries 32-byte for pairwise key table
 135  * 64 entries 8-byte for pairwise ta key table
 136  */
 137 #define SHARED_KEY_TABLE_BASE           0x1000
 138 #define PAIRWISE_KEY_TABLE_BASE         0x1200
 139 #define PAIRWISE_TA_TABLE_BASE          0x1a00
 140
 141 #define SHARED_KEY_ENTRY(__idx) \
 142         ( SHARED_KEY_TABLE_BASE + \
 143                 ((__idx) * sizeof(struct hw_key_entry)) )
 144 #define PAIRWISE_KEY_ENTRY(__idx) \
 145         ( PAIRWISE_KEY_TABLE_BASE + \
 146                 ((__idx) * sizeof(struct hw_key_entry)) )
 147 #define PAIRWISE_TA_ENTRY(__idx) \
 148         ( PAIRWISE_TA_TABLE_BASE + \
 149                 ((__idx) * sizeof(struct hw_pairwise_ta_entry)) )
 150
 151 struct hw_key_entry {
 152         u8 key[16];
 153         u8 tx_mic[8];
 154         u8 rx_mic[8];
 155 } __attribute__ ((packed));
 156
 157 struct hw_pairwise_ta_entry {
 158         u8 address[6];
 159         u8 cipher;
 160         u8 reserved;
 161 } __attribute__ ((packed));
 162
 163 /*
 164  * Other on-chip shared memory space.
 165  */
 166 #define HW_CIS_BASE                     0x2000
 167 #define HW_NULL_BASE                    0x2b00
 168
 169 /*
 170  * Since NULL frame won't be that long (256 byte),
 171  * We steal 16 tail bytes to save debugging settings.
 172  */
 173 #define HW_DEBUG_SETTING_BASE           0x2bf0
 174
 175 /*
 176  * On-chip BEACON frame space.
 177  */
 178 #define HW_BEACON_BASE0                 0x2c00
 179 #define HW_BEACON_BASE1                 0x2d00
 180 #define HW_BEACON_BASE2                 0x2e00
 181 #define HW_BEACON_BASE3                 0x2f00
 182
 183 #define HW_BEACON_OFFSET(__index) \
 184         ( HW_BEACON_BASE0 + (__index * 0x0100) )
 185
 186 /*
 187  * HOST-MCU shared memory.
 188  */
 189
 190 /*
 191  * H2M_MAILBOX_CSR: Host-to-MCU Mailbox.
 192  */
 193 #define H2M_MAILBOX_CSR                 0x2100
 194 #define H2M_MAILBOX_CSR_ARG0            FIELD32(0x000000ff)
 195 #define H2M_MAILBOX_CSR_ARG1            FIELD32(0x0000ff00)
 196 #define H2M_MAILBOX_CSR_CMD_TOKEN       FIELD32(0x00ff0000)
 197 #define H2M_MAILBOX_CSR_OWNER           FIELD32(0xff000000)
 198
 199 /*
 200  * MCU_LEDCS: LED control for MCU Mailbox.
 201  */
 202 #define MCU_LEDCS_LED_MODE              FIELD16(0x001f)
 203 #define MCU_LEDCS_RADIO_STATUS          FIELD16(0x0020)
 204 #define MCU_LEDCS_LINK_BG_STATUS        FIELD16(0x0040)
 205 #define MCU_LEDCS_LINK_A_STATUS         FIELD16(0x0080)
 206 #define MCU_LEDCS_POLARITY_GPIO_0       FIELD16(0x0100)
 207 #define MCU_LEDCS_POLARITY_GPIO_1       FIELD16(0x0200)
 208 #define MCU_LEDCS_POLARITY_GPIO_2       FIELD16(0x0400)
 209 #define MCU_LEDCS_POLARITY_GPIO_3       FIELD16(0x0800)
 210 #define MCU_LEDCS_POLARITY_GPIO_4       FIELD16(0x1000)
 211 #define MCU_LEDCS_POLARITY_ACT          FIELD16(0x2000)
 212 #define MCU_LEDCS_POLARITY_READY_BG     FIELD16(0x4000)
 213 #define MCU_LEDCS_POLARITY_READY_A      FIELD16(0x8000)
 214
 215 /*
 216  * M2H_CMD_DONE_CSR.
 217  */
 218 #define M2H_CMD_DONE_CSR                0x2104
 219
 220 /*
 221  * MCU_TXOP_ARRAY_BASE.
 222  */
 223 #define MCU_TXOP_ARRAY_BASE             0x2110
 224
 225 /*
 226  * MAC Control/Status Registers(CSR).
 227  * Some values are set in TU, whereas 1 TU == 1024 us.
 228  */
 229
 230 /*
 231  * MAC_CSR0: ASIC revision number.
 232  */
 233 #define MAC_CSR0                        0x3000
 234
 235 /*
 236  * MAC_CSR1: System control register.
 237  * SOFT_RESET: Software reset bit, 1: reset, 0: normal.
 238  * BBP_RESET: Hardware reset BBP.
 239  * HOST_READY: Host is ready after initialization, 1: ready.
 240  */
 241 #define MAC_CSR1                        0x3004
 242 #define MAC_CSR1_SOFT_RESET             FIELD32(0x00000001)
 243 #define MAC_CSR1_BBP_RESET              FIELD32(0x00000002)
 244 #define MAC_CSR1_HOST_READY             FIELD32(0x00000004)
 245
 246 /*
 247  * MAC_CSR2: STA MAC register 0.
 248  */
 249 #define MAC_CSR2                        0x3008
 250 #define MAC_CSR2_BYTE0                  FIELD32(0x000000ff)
 251 #define MAC_CSR2_BYTE1                  FIELD32(0x0000ff00)
 252 #define MAC_CSR2_BYTE2                  FIELD32(0x00ff0000)
 253 #define MAC_CSR2_BYTE3                  FIELD32(0xff000000)
 254
 255 /*
 256  * MAC_CSR3: STA MAC register 1.
 257  * UNICAST_TO_ME_MASK:
 258  *      Used to mask off bits from byte 5 of the MAC address
 259  *      to determine the UNICAST_TO_ME bit for RX frames.
 260  *      The full mask is complemented by BSS_ID_MASK:
 261  *              MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
 262  */
 263 #define MAC_CSR3                        0x300c
 264 #define MAC_CSR3_BYTE4                  FIELD32(0x000000ff)
 265 #define MAC_CSR3_BYTE5                  FIELD32(0x0000ff00)
 266 #define MAC_CSR3_UNICAST_TO_ME_MASK     FIELD32(0x00ff0000)
 267
 268 /*
 269  * MAC_CSR4: BSSID register 0.
 270  */
 271 #define MAC_CSR4                        0x3010
 272 #define MAC_CSR4_BYTE0                  FIELD32(0x000000ff)
 273 #define MAC_CSR4_BYTE1                  FIELD32(0x0000ff00)
 274 #define MAC_CSR4_BYTE2                  FIELD32(0x00ff0000)
 275 #define MAC_CSR4_BYTE3                  FIELD32(0xff000000)
 276
 277 /*
 278  * MAC_CSR5: BSSID register 1.
 279  * BSS_ID_MASK:
 280  *      This mask is used to mask off bits 0 and 1 of byte 5 of the
 281  *      BSSID. This will make sure that those bits will be ignored
 282  *      when determining the MY_BSS of RX frames.
 283  *              0: 1-BSSID mode (BSS index = 0)
 284  *              1: 2-BSSID mode (BSS index: Byte5, bit 0)
 285  *              2: 2-BSSID mode (BSS index: byte5, bit 1)
 286  *              3: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
 287  */
 288 #define MAC_CSR5                        0x3014
 289 #define MAC_CSR5_BYTE4                  FIELD32(0x000000ff)
 290 #define MAC_CSR5_BYTE5                  FIELD32(0x0000ff00)
 291 #define MAC_CSR5_BSS_ID_MASK            FIELD32(0x00ff0000)
 292
 293 /*
 294  * MAC_CSR6: Maximum frame length register.
 295  */
 296 #define MAC_CSR6                        0x3018
 297 #define MAC_CSR6_MAX_FRAME_UNIT         FIELD32(0x00000fff)
 298
 299 /*
 300  * MAC_CSR7: Reserved
 301  */
 302 #define MAC_CSR7                        0x301c
 303
 304 /*
 305  * MAC_CSR8: SIFS/EIFS register.
 306  * All units are in US.
 307  */
 308 #define MAC_CSR8                        0x3020
 309 #define MAC_CSR8_SIFS                   FIELD32(0x000000ff)
 310 #define MAC_CSR8_SIFS_AFTER_RX_OFDM     FIELD32(0x0000ff00)
 311 #define MAC_CSR8_EIFS                   FIELD32(0xffff0000)
 312
 313 /*
 314  * MAC_CSR9: Back-Off control register.
 315  * SLOT_TIME: Slot time, default is 20us for 802.11BG.
 316  * CWMIN: Bit for Cwmin. default Cwmin is 31 (2^5 - 1).
 317  * CWMAX: Bit for Cwmax, default Cwmax is 1023 (2^10 - 1).
 318  * CW_SELECT: 1: CWmin/Cwmax select from register, 0:select from TxD.
 319  */
 320 #define MAC_CSR9                        0x3024
 321 #define MAC_CSR9_SLOT_TIME              FIELD32(0x000000ff)
 322 #define MAC_CSR9_CWMIN                  FIELD32(0x00000f00)
 323 #define MAC_CSR9_CWMAX                  FIELD32(0x0000f000)
 324 #define MAC_CSR9_CW_SELECT              FIELD32(0x00010000)
 325
 326 /*
 327  * MAC_CSR10: Power state configuration.
 328  */
 329 #define MAC_CSR10                       0x3028
 330
 331 /*
 332  * MAC_CSR11: Power saving transition time register.
 333  * DELAY_AFTER_TBCN: Delay after Tbcn expired in units of TU.
 334  * TBCN_BEFORE_WAKEUP: Number of beacon before wakeup.
 335  * WAKEUP_LATENCY: In unit of TU.
 336  */
 337 #define MAC_CSR11                       0x302c
 338 #define MAC_CSR11_DELAY_AFTER_TBCN      FIELD32(0x000000ff)
 339 #define MAC_CSR11_TBCN_BEFORE_WAKEUP    FIELD32(0x00007f00)
 340 #define MAC_CSR11_AUTOWAKE              FIELD32(0x00008000)
 341 #define MAC_CSR11_WAKEUP_LATENCY        FIELD32(0x000f0000)
 342
 343 /*
 344  * MAC_CSR12: Manual power control / status register (merge CSR20 & PWRCSR1).
 345  * CURRENT_STATE: 0:sleep, 1:awake.
 346  * FORCE_WAKEUP: This has higher priority than PUT_TO_SLEEP.
 347  * BBP_CURRENT_STATE: 0: BBP sleep, 1: BBP awake.
 348  */
 349 #define MAC_CSR12                       0x3030
 350 #define MAC_CSR12_CURRENT_STATE         FIELD32(0x00000001)
 351 #define MAC_CSR12_PUT_TO_SLEEP          FIELD32(0x00000002)
 352 #define MAC_CSR12_FORCE_WAKEUP          FIELD32(0x00000004)
 353 #define MAC_CSR12_BBP_CURRENT_STATE     FIELD32(0x00000008)
 354
 355 /*
 356  * MAC_CSR13: GPIO.
 357  */
 358 #define MAC_CSR13                       0x3034
 359 #define MAC_CSR13_BIT0                  FIELD32(0x00000001)
 360 #define MAC_CSR13_BIT1                  FIELD32(0x00000002)
 361 #define MAC_CSR13_BIT2                  FIELD32(0x00000004)
 362 #define MAC_CSR13_BIT3                  FIELD32(0x00000008)
 363 #define MAC_CSR13_BIT4                  FIELD32(0x00000010)
 364 #define MAC_CSR13_BIT5                  FIELD32(0x00000020)
 365 #define MAC_CSR13_BIT6                  FIELD32(0x00000040)
 366 #define MAC_CSR13_BIT7                  FIELD32(0x00000080)
 367 #define MAC_CSR13_BIT8                  FIELD32(0x00000100)
 368 #define MAC_CSR13_BIT9                  FIELD32(0x00000200)
 369 #define MAC_CSR13_BIT10                 FIELD32(0x00000400)
 370 #define MAC_CSR13_BIT11                 FIELD32(0x00000800)
 371 #define MAC_CSR13_BIT12                 FIELD32(0x00001000)
 372
 373 /*
 374  * MAC_CSR14: LED control register.
 375  * ON_PERIOD: On period, default 70ms.
 376  * OFF_PERIOD: Off period, default 30ms.
 377  * HW_LED: HW TX activity, 1: normal OFF, 0: normal ON.
 378  * SW_LED: s/w LED, 1: ON, 0: OFF.
 379  * HW_LED_POLARITY: 0: active low, 1: active high.
 380  */
 381 #define MAC_CSR14                       0x3038
 382 #define MAC_CSR14_ON_PERIOD             FIELD32(0x000000ff)
 383 #define MAC_CSR14_OFF_PERIOD            FIELD32(0x0000ff00)
 384 #define MAC_CSR14_HW_LED                FIELD32(0x00010000)
 385 #define MAC_CSR14_SW_LED                FIELD32(0x00020000)
 386 #define MAC_CSR14_HW_LED_POLARITY       FIELD32(0x00040000)
 387 #define MAC_CSR14_SW_LED2               FIELD32(0x00080000)
 388
 389 /*
 390  * MAC_CSR15: NAV control.
 391  */
 392 #define MAC_CSR15                       0x303c
 393
 394 /*
 395  * TXRX control registers.
 396  * Some values are set in TU, whereas 1 TU == 1024 us.
 397  */
 398
 399 /*
 400  * TXRX_CSR0: TX/RX configuration register.
 401  * TSF_OFFSET: Default is 24.
 402  * AUTO_TX_SEQ: 1: ASIC auto replace sequence nr in outgoing frame.
 403  * DISABLE_RX: Disable Rx engine.
 404  * DROP_CRC: Drop CRC error.
 405  * DROP_PHYSICAL: Drop physical error.
 406  * DROP_CONTROL: Drop control frame.
 407  * DROP_NOT_TO_ME: Drop not to me unicast frame.
 408  * DROP_TO_DS: Drop fram ToDs bit is true.
 409  * DROP_VERSION_ERROR: Drop version error frame.
 410  * DROP_MULTICAST: Drop multicast frames.
 411  * DROP_BORADCAST: Drop broadcast frames.
 412  * ROP_ACK_CTS: Drop received ACK and CTS.
 413  */
 414 #define TXRX_CSR0                       0x3040
 415 #define TXRX_CSR0_RX_ACK_TIMEOUT        FIELD32(0x000001ff)
 416 #define TXRX_CSR0_TSF_OFFSET            FIELD32(0x00007e00)
 417 #define TXRX_CSR0_AUTO_TX_SEQ           FIELD32(0x00008000)
 418 #define TXRX_CSR0_DISABLE_RX            FIELD32(0x00010000)
 419 #define TXRX_CSR0_DROP_CRC              FIELD32(0x00020000)
 420 #define TXRX_CSR0_DROP_PHYSICAL         FIELD32(0x00040000)
 421 #define TXRX_CSR0_DROP_CONTROL          FIELD32(0x00080000)
 422 #define TXRX_CSR0_DROP_NOT_TO_ME        FIELD32(0x00100000)
 423 #define TXRX_CSR0_DROP_TO_DS            FIELD32(0x00200000)
 424 #define TXRX_CSR0_DROP_VERSION_ERROR    FIELD32(0x00400000)
 425 #define TXRX_CSR0_DROP_MULTICAST        FIELD32(0x00800000)
 426 #define TXRX_CSR0_DROP_BROADCAST        FIELD32(0x01000000)
 427 #define TXRX_CSR0_DROP_ACK_CTS          FIELD32(0x02000000)
 428 #define TXRX_CSR0_TX_WITHOUT_WAITING    FIELD32(0x04000000)
 429
 430 /*
 431  * TXRX_CSR1
 432  */
 433 #define TXRX_CSR1                       0x3044
 434 #define TXRX_CSR1_BBP_ID0               FIELD32(0x0000007f)
 435 #define TXRX_CSR1_BBP_ID0_VALID         FIELD32(0x00000080)
 436 #define TXRX_CSR1_BBP_ID1               FIELD32(0x00007f00)
 437 #define TXRX_CSR1_BBP_ID1_VALID         FIELD32(0x00008000)
 438 #define TXRX_CSR1_BBP_ID2               FIELD32(0x007f0000)
 439 #define TXRX_CSR1_BBP_ID2_VALID         FIELD32(0x00800000)
 440 #define TXRX_CSR1_BBP_ID3               FIELD32(0x7f000000)
 441 #define TXRX_CSR1_BBP_ID3_VALID         FIELD32(0x80000000)
 442
 443 /*
 444  * TXRX_CSR2
 445  */
 446 #define TXRX_CSR2                       0x3048
 447 #define TXRX_CSR2_BBP_ID0               FIELD32(0x0000007f)
 448 #define TXRX_CSR2_BBP_ID0_VALID         FIELD32(0x00000080)
 449 #define TXRX_CSR2_BBP_ID1               FIELD32(0x00007f00)
 450 #define TXRX_CSR2_BBP_ID1_VALID         FIELD32(0x00008000)
 451 #define TXRX_CSR2_BBP_ID2               FIELD32(0x007f0000)
 452 #define TXRX_CSR2_BBP_ID2_VALID         FIELD32(0x00800000)
 453 #define TXRX_CSR2_BBP_ID3               FIELD32(0x7f000000)
 454 #define TXRX_CSR2_BBP_ID3_VALID         FIELD32(0x80000000)
 455
 456 /*
 457  * TXRX_CSR3
 458  */
 459 #define TXRX_CSR3                       0x304c
 460 #define TXRX_CSR3_BBP_ID0               FIELD32(0x0000007f)
 461 #define TXRX_CSR3_BBP_ID0_VALID         FIELD32(0x00000080)
 462 #define TXRX_CSR3_BBP_ID1               FIELD32(0x00007f00)
 463 #define TXRX_CSR3_BBP_ID1_VALID         FIELD32(0x00008000)
 464 #define TXRX_CSR3_BBP_ID2               FIELD32(0x007f0000)
 465 #define TXRX_CSR3_BBP_ID2_VALID         FIELD32(0x00800000)
 466 #define TXRX_CSR3_BBP_ID3               FIELD32(0x7f000000)
 467 #define TXRX_CSR3_BBP_ID3_VALID         FIELD32(0x80000000)
 468
 469 /*
 470  * TXRX_CSR4: Auto-Responder/Tx-retry register.
 471  * AUTORESPOND_PREAMBLE: 0:long, 1:short preamble.
 472  * OFDM_TX_RATE_DOWN: 1:enable.
 473  * OFDM_TX_RATE_STEP: 0:1-step, 1: 2-step, 2:3-step, 3:4-step.
 474  * OFDM_TX_FALLBACK_CCK: 0: Fallback to OFDM 6M only, 1: Fallback to CCK 1M,2M.
 475  */
 476 #define TXRX_CSR4                       0x3050
 477 #define TXRX_CSR4_TX_ACK_TIMEOUT        FIELD32(0x000000ff)
 478 #define TXRX_CSR4_CNTL_ACK_POLICY       FIELD32(0x00000700)
 479 #define TXRX_CSR4_ACK_CTS_PSM           FIELD32(0x00010000)
 480 #define TXRX_CSR4_AUTORESPOND_ENABLE    FIELD32(0x00020000)
 481 #define TXRX_CSR4_AUTORESPOND_PREAMBLE  FIELD32(0x00040000)
 482 #define TXRX_CSR4_OFDM_TX_RATE_DOWN     FIELD32(0x00080000)
 483 #define TXRX_CSR4_OFDM_TX_RATE_STEP     FIELD32(0x00300000)
 484 #define TXRX_CSR4_OFDM_TX_FALLBACK_CCK  FIELD32(0x00400000)
 485 #define TXRX_CSR4_LONG_RETRY_LIMIT      FIELD32(0x0f000000)
 486 #define TXRX_CSR4_SHORT_RETRY_LIMIT     FIELD32(0xf0000000)
 487
 488 /*
 489  * TXRX_CSR5
 490  */
 491 #define TXRX_CSR5                       0x3054
 492
 493 /*
 494  * TXRX_CSR6: ACK/CTS payload consumed time
 495  */
 496 #define TXRX_CSR6                       0x3058
 497
 498 /*
 499  * TXRX_CSR7: OFDM ACK/CTS payload consumed time for 6/9/12/18 mbps.
 500  */
 501 #define TXRX_CSR7                       0x305c
 502 #define TXRX_CSR7_ACK_CTS_6MBS          FIELD32(0x000000ff)
 503 #define TXRX_CSR7_ACK_CTS_9MBS          FIELD32(0x0000ff00)
 504 #define TXRX_CSR7_ACK_CTS_12MBS         FIELD32(0x00ff0000)
 505 #define TXRX_CSR7_ACK_CTS_18MBS         FIELD32(0xff000000)
 506
 507 /*
 508  * TXRX_CSR8: OFDM ACK/CTS payload consumed time for 24/36/48/54 mbps.
 509  */
 510 #define TXRX_CSR8                       0x3060
 511 #define TXRX_CSR8_ACK_CTS_24MBS         FIELD32(0x000000ff)
 512 #define TXRX_CSR8_ACK_CTS_36MBS         FIELD32(0x0000ff00)
 513 #define TXRX_CSR8_ACK_CTS_48MBS         FIELD32(0x00ff0000)
 514 #define TXRX_CSR8_ACK_CTS_54MBS         FIELD32(0xff000000)
 515
 516 /*
 517  * TXRX_CSR9: Synchronization control register.
 518  * BEACON_INTERVAL: In unit of 1/16 TU.
 519  * TSF_TICKING: Enable TSF auto counting.
 520  * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode.
 521  * BEACON_GEN: Enable beacon generator.
 522  */
 523 #define TXRX_CSR9                       0x3064
 524 #define TXRX_CSR9_BEACON_INTERVAL       FIELD32(0x0000ffff)
 525 #define TXRX_CSR9_TSF_TICKING           FIELD32(0x00010000)
 526 #define TXRX_CSR9_TSF_SYNC              FIELD32(0x00060000)
 527 #define TXRX_CSR9_TBTT_ENABLE           FIELD32(0x00080000)
 528 #define TXRX_CSR9_BEACON_GEN            FIELD32(0x00100000)
 529 #define TXRX_CSR9_TIMESTAMP_COMPENSATE  FIELD32(0xff000000)
 530
 531 /*
 532  * TXRX_CSR10: BEACON alignment.
 533  */
 534 #define TXRX_CSR10                      0x3068
 535
 536 /*
 537  * TXRX_CSR11: AES mask.
 538  */
 539 #define TXRX_CSR11                      0x306c
 540
 541 /*
 542  * TXRX_CSR12: TSF low 32.
 543  */
 544 #define TXRX_CSR12                      0x3070
 545 #define TXRX_CSR12_LOW_TSFTIMER         FIELD32(0xffffffff)
 546
 547 /*
 548  * TXRX_CSR13: TSF high 32.
 549  */
 550 #define TXRX_CSR13                      0x3074
 551 #define TXRX_CSR13_HIGH_TSFTIMER        FIELD32(0xffffffff)
 552
 553 /*
 554  * TXRX_CSR14: TBTT timer.
 555  */
 556 #define TXRX_CSR14                      0x3078
 557
 558 /*
 559  * TXRX_CSR15: TKIP MIC priority byte "AND" mask.
 560  */
 561 #define TXRX_CSR15                      0x307c
 562
 563 /*
 564  * PHY control registers.
 565  * Some values are set in TU, whereas 1 TU == 1024 us.
 566  */
 567
 568 /*
 569  * PHY_CSR0: RF/PS control.
 570  */
 571 #define PHY_CSR0                        0x3080
 572 #define PHY_CSR0_PA_PE_BG               FIELD32(0x00010000)
 573 #define PHY_CSR0_PA_PE_A                FIELD32(0x00020000)
 574
 575 /*
 576  * PHY_CSR1
 577  */
 578 #define PHY_CSR1                        0x3084
 579
 580 /*
 581  * PHY_CSR2: Pre-TX BBP control.
 582  */
 583 #define PHY_CSR2                        0x3088
 584
 585 /*
 586  * PHY_CSR3: BBP serial control register.
 587  * VALUE: Register value to program into BBP.
 588  * REG_NUM: Selected BBP register.
 589  * READ_CONTROL: 0: Write BBP, 1: Read BBP.
 590  * BUSY: 1: ASIC is busy execute BBP programming.
 591  */
 592 #define PHY_CSR3                        0x308c
 593 #define PHY_CSR3_VALUE                  FIELD32(0x000000ff)
 594 #define PHY_CSR3_REGNUM                 FIELD32(0x00007f00)
 595 #define PHY_CSR3_READ_CONTROL           FIELD32(0x00008000)
 596 #define PHY_CSR3_BUSY                   FIELD32(0x00010000)
 597
 598 /*
 599  * PHY_CSR4: RF serial control register
 600  * VALUE: Register value (include register id) serial out to RF/IF chip.
 601  * NUMBER_OF_BITS: Number of bits used in RFRegValue (I:20, RFMD:22).
 602  * IF_SELECT: 1: select IF to program, 0: select RF to program.
 603  * PLL_LD: RF PLL_LD status.
 604  * BUSY: 1: ASIC is busy execute RF programming.
 605  */
 606 #define PHY_CSR4                        0x3090
 607 #define PHY_CSR4_VALUE                  FIELD32(0x00ffffff)
 608 #define PHY_CSR4_NUMBER_OF_BITS         FIELD32(0x1f000000)
 609 #define PHY_CSR4_IF_SELECT              FIELD32(0x20000000)
 610 #define PHY_CSR4_PLL_LD                 FIELD32(0x40000000)
 611 #define PHY_CSR4_BUSY                   FIELD32(0x80000000)
 612
 613 /*
 614  * PHY_CSR5: RX to TX signal switch timing control.
 615  */
 616 #define PHY_CSR5                        0x3094
 617 #define PHY_CSR5_IQ_FLIP                FIELD32(0x00000004)
 618
 619 /*
 620  * PHY_CSR6: TX to RX signal timing control.
 621  */
 622 #define PHY_CSR6                        0x3098
 623 #define PHY_CSR6_IQ_FLIP                FIELD32(0x00000004)
 624
 625 /*
 626  * PHY_CSR7: TX DAC switching timing control.
 627  */
 628 #define PHY_CSR7                        0x309c
 629
 630 /*
 631  * Security control register.
 632  */
 633
 634 /*
 635  * SEC_CSR0: Shared key table control.
 636  */
 637 #define SEC_CSR0                        0x30a0
 638 #define SEC_CSR0_BSS0_KEY0_VALID        FIELD32(0x00000001)
 639 #define SEC_CSR0_BSS0_KEY1_VALID        FIELD32(0x00000002)
 640 #define SEC_CSR0_BSS0_KEY2_VALID        FIELD32(0x00000004)
 641 #define SEC_CSR0_BSS0_KEY3_VALID        FIELD32(0x00000008)
 642 #define SEC_CSR0_BSS1_KEY0_VALID        FIELD32(0x00000010)
 643 #define SEC_CSR0_BSS1_KEY1_VALID        FIELD32(0x00000020)
 644 #define SEC_CSR0_BSS1_KEY2_VALID        FIELD32(0x00000040)
 645 #define SEC_CSR0_BSS1_KEY3_VALID        FIELD32(0x00000080)
 646 #define SEC_CSR0_BSS2_KEY0_VALID        FIELD32(0x00000100)
 647 #define SEC_CSR0_BSS2_KEY1_VALID        FIELD32(0x00000200)
 648 #define SEC_CSR0_BSS2_KEY2_VALID        FIELD32(0x00000400)
 649 #define SEC_CSR0_BSS2_KEY3_VALID        FIELD32(0x00000800)
 650 #define SEC_CSR0_BSS3_KEY0_VALID        FIELD32(0x00001000)
 651 #define SEC_CSR0_BSS3_KEY1_VALID        FIELD32(0x00002000)
 652 #define SEC_CSR0_BSS3_KEY2_VALID        FIELD32(0x00004000)
 653 #define SEC_CSR0_BSS3_KEY3_VALID        FIELD32(0x00008000)
 654
 655 /*
 656  * SEC_CSR1: Shared key table security mode register.
 657  */
 658 #define SEC_CSR1                        0x30a4
 659 #define SEC_CSR1_BSS0_KEY0_CIPHER_ALG   FIELD32(0x00000007)
 660 #define SEC_CSR1_BSS0_KEY1_CIPHER_ALG   FIELD32(0x00000070)
 661 #define SEC_CSR1_BSS0_KEY2_CIPHER_ALG   FIELD32(0x00000700)
 662 #define SEC_CSR1_BSS0_KEY3_CIPHER_ALG   FIELD32(0x00007000)
 663 #define SEC_CSR1_BSS1_KEY0_CIPHER_ALG   FIELD32(0x00070000)
 664 #define SEC_CSR1_BSS1_KEY1_CIPHER_ALG   FIELD32(0x00700000)
 665 #define SEC_CSR1_BSS1_KEY2_CIPHER_ALG   FIELD32(0x07000000)
 666 #define SEC_CSR1_BSS1_KEY3_CIPHER_ALG   FIELD32(0x70000000)
 667
 668 /*
 669  * Pairwise key table valid bitmap registers.
 670  * SEC_CSR2: pairwise key table valid bitmap 0.
 671  * SEC_CSR3: pairwise key table valid bitmap 1.
 672  */
 673 #define SEC_CSR2                        0x30a8
 674 #define SEC_CSR3                        0x30ac
 675
 676 /*
 677  * SEC_CSR4: Pairwise key table lookup control.
 678  */
 679 #define SEC_CSR4                        0x30b0
 680 #define SEC_CSR4_ENABLE_BSS0            FIELD32(0x00000001)
 681 #define SEC_CSR4_ENABLE_BSS1            FIELD32(0x00000002)
 682 #define SEC_CSR4_ENABLE_BSS2            FIELD32(0x00000004)
 683 #define SEC_CSR4_ENABLE_BSS3            FIELD32(0x00000008)
 684
 685 /*
 686  * SEC_CSR5: shared key table security mode register.
 687  */
 688 #define SEC_CSR5                        0x30b4
 689 #define SEC_CSR5_BSS2_KEY0_CIPHER_ALG   FIELD32(0x00000007)
 690 #define SEC_CSR5_BSS2_KEY1_CIPHER_ALG   FIELD32(0x00000070)
 691 #define SEC_CSR5_BSS2_KEY2_CIPHER_ALG   FIELD32(0x00000700)
 692 #define SEC_CSR5_BSS2_KEY3_CIPHER_ALG   FIELD32(0x00007000)
 693 #define SEC_CSR5_BSS3_KEY0_CIPHER_ALG   FIELD32(0x00070000)
 694 #define SEC_CSR5_BSS3_KEY1_CIPHER_ALG   FIELD32(0x00700000)
 695 #define SEC_CSR5_BSS3_KEY2_CIPHER_ALG   FIELD32(0x07000000)
 696 #define SEC_CSR5_BSS3_KEY3_CIPHER_ALG   FIELD32(0x70000000)
 697
 698 /*
 699  * STA control registers.
 700  */
 701
 702 /*
 703  * STA_CSR0: RX PLCP error count & RX FCS error count.
 704  */
 705 #define STA_CSR0                        0x30c0
 706 #define STA_CSR0_FCS_ERROR              FIELD32(0x0000ffff)
 707 #define STA_CSR0_PLCP_ERROR             FIELD32(0xffff0000)
 708
 709 /*
 710  * STA_CSR1: RX False CCA count & RX LONG frame count.
 711  */
 712 #define STA_CSR1                        0x30c4
 713 #define STA_CSR1_PHYSICAL_ERROR         FIELD32(0x0000ffff)
 714 #define STA_CSR1_FALSE_CCA_ERROR        FIELD32(0xffff0000)
 715
 716 /*
 717  * STA_CSR2: TX Beacon count and RX FIFO overflow count.
 718  */
 719 #define STA_CSR2                        0x30c8
 720 #define STA_CSR2_RX_FIFO_OVERFLOW_COUNT FIELD32(0x0000ffff)
 721 #define STA_CSR2_RX_OVERFLOW_COUNT      FIELD32(0xffff0000)
 722
 723 /*
 724  * STA_CSR3: TX Beacon count.
 725  */
 726 #define STA_CSR3                        0x30cc
 727 #define STA_CSR3_TX_BEACON_COUNT        FIELD32(0x0000ffff)
 728
 729 /*
 730  * STA_CSR4: TX Result status register.
 731  * VALID: 1:This register contains a valid TX result.
 732  */
 733 #define STA_CSR4                        0x30d0
 734 #define STA_CSR4_VALID                  FIELD32(0x00000001)
 735 #define STA_CSR4_TX_RESULT              FIELD32(0x0000000e)
 736 #define STA_CSR4_RETRY_COUNT            FIELD32(0x000000f0)
 737 #define STA_CSR4_PID_SUBTYPE            FIELD32(0x00001f00)
 738 #define STA_CSR4_PID_TYPE               FIELD32(0x0000e000)
 739 #define STA_CSR4_TXRATE                 FIELD32(0x000f0000)
 740
 741 /*
 742  * QOS control registers.
 743  */
 744
 745 /*
 746  * QOS_CSR0: TXOP holder MAC address register.
 747  */
 748 #define QOS_CSR0                        0x30e0
 749 #define QOS_CSR0_BYTE0                  FIELD32(0x000000ff)
 750 #define QOS_CSR0_BYTE1                  FIELD32(0x0000ff00)
 751 #define QOS_CSR0_BYTE2                  FIELD32(0x00ff0000)
 752 #define QOS_CSR0_BYTE3                  FIELD32(0xff000000)
 753
 754 /*
 755  * QOS_CSR1: TXOP holder MAC address register.
 756  */
 757 #define QOS_CSR1                        0x30e4
 758 #define QOS_CSR1_BYTE4                  FIELD32(0x000000ff)
 759 #define QOS_CSR1_BYTE5                  FIELD32(0x0000ff00)
 760
 761 /*
 762  * QOS_CSR2: TXOP holder timeout register.
 763  */
 764 #define QOS_CSR2                        0x30e8
 765
 766 /*
 767  * RX QOS-CFPOLL MAC address register.
 768  * QOS_CSR3: RX QOS-CFPOLL MAC address 0.
 769  * QOS_CSR4: RX QOS-CFPOLL MAC address 1.
 770  */
 771 #define QOS_CSR3                        0x30ec
 772 #define QOS_CSR4                        0x30f0
 773
 774 /*
 775  * QOS_CSR5: "QosControl" field of the RX QOS-CFPOLL.
 776  */
 777 #define QOS_CSR5                        0x30f4
 778
 779 /*
 780  * Host DMA registers.
 781  */
 782
 783 /*
 784  * AC0_BASE_CSR: AC_BK base address.
 785  */
 786 #define AC0_BASE_CSR                    0x3400
 787 #define AC0_BASE_CSR_RING_REGISTER      FIELD32(0xffffffff)
 788
 789 /*
 790  * AC1_BASE_CSR: AC_BE base address.
 791  */
 792 #define AC1_BASE_CSR                    0x3404
 793 #define AC1_BASE_CSR_RING_REGISTER      FIELD32(0xffffffff)
 794
 795 /*
 796  * AC2_BASE_CSR: AC_VI base address.
 797  */
 798 #define AC2_BASE_CSR                    0x3408
 799 #define AC2_BASE_CSR_RING_REGISTER      FIELD32(0xffffffff)
 800
 801 /*
 802  * AC3_BASE_CSR: AC_VO base address.
 803  */
 804 #define AC3_BASE_CSR                    0x340c
 805 #define AC3_BASE_CSR_RING_REGISTER      FIELD32(0xffffffff)
 806
 807 /*
 808  * MGMT_BASE_CSR: MGMT ring base address.
 809  */
 810 #define MGMT_BASE_CSR                   0x3410
 811 #define MGMT_BASE_CSR_RING_REGISTER     FIELD32(0xffffffff)
 812
 813 /*
 814  * TX_RING_CSR0: TX Ring size for AC_BK, AC_BE, AC_VI, AC_VO.
 815  */
 816 #define TX_RING_CSR0                    0x3418
 817 #define TX_RING_CSR0_AC0_RING_SIZE      FIELD32(0x000000ff)
 818 #define TX_RING_CSR0_AC1_RING_SIZE      FIELD32(0x0000ff00)
 819 #define TX_RING_CSR0_AC2_RING_SIZE      FIELD32(0x00ff0000)
 820 #define TX_RING_CSR0_AC3_RING_SIZE      FIELD32(0xff000000)
 821
 822 /*
 823  * TX_RING_CSR1: TX Ring size for MGMT Ring, HCCA Ring
 824  * TXD_SIZE: In unit of 32-bit.
 825  */
 826 #define TX_RING_CSR1                    0x341c
 827 #define TX_RING_CSR1_MGMT_RING_SIZE     FIELD32(0x000000ff)
 828 #define TX_RING_CSR1_HCCA_RING_SIZE     FIELD32(0x0000ff00)
 829 #define TX_RING_CSR1_TXD_SIZE           FIELD32(0x003f0000)
 830
 831 /*
 832  * AIFSN_CSR: AIFSN for each EDCA AC.
 833  * AIFSN0: For AC_BK.
 834  * AIFSN1: For AC_BE.
 835  * AIFSN2: For AC_VI.
 836  * AIFSN3: For AC_VO.
 837  */
 838 #define AIFSN_CSR                       0x3420
 839 #define AIFSN_CSR_AIFSN0                FIELD32(0x0000000f)
 840 #define AIFSN_CSR_AIFSN1                FIELD32(0x000000f0)
 841 #define AIFSN_CSR_AIFSN2                FIELD32(0x00000f00)
 842 #define AIFSN_CSR_AIFSN3                FIELD32(0x0000f000)
 843
 844 /*
 845  * CWMIN_CSR: CWmin for each EDCA AC.
 846  * CWMIN0: For AC_BK.
 847  * CWMIN1: For AC_BE.
 848  * CWMIN2: For AC_VI.
 849  * CWMIN3: For AC_VO.
 850  */
 851 #define CWMIN_CSR                       0x3424
 852 #define CWMIN_CSR_CWMIN0                FIELD32(0x0000000f)
 853 #define CWMIN_CSR_CWMIN1                FIELD32(0x000000f0)
 854 #define CWMIN_CSR_CWMIN2                FIELD32(0x00000f00)
 855 #define CWMIN_CSR_CWMIN3                FIELD32(0x0000f000)
 856
 857 /*
 858  * CWMAX_CSR: CWmax for each EDCA AC.
 859  * CWMAX0: For AC_BK.
 860  * CWMAX1: For AC_BE.
 861  * CWMAX2: For AC_VI.
 862  * CWMAX3: For AC_VO.
 863  */
 864 #define CWMAX_CSR                       0x3428
 865 #define CWMAX_CSR_CWMAX0                FIELD32(0x0000000f)
 866 #define CWMAX_CSR_CWMAX1                FIELD32(0x000000f0)
 867 #define CWMAX_CSR_CWMAX2                FIELD32(0x00000f00)
 868 #define CWMAX_CSR_CWMAX3                FIELD32(0x0000f000)
 869
 870 /*
 871  * TX_DMA_DST_CSR: TX DMA destination
 872  * 0: TX ring0, 1: TX ring1, 2: TX ring2 3: invalid
 873  */
 874 #define TX_DMA_DST_CSR                  0x342c
 875 #define TX_DMA_DST_CSR_DEST_AC0         FIELD32(0x00000003)
 876 #define TX_DMA_DST_CSR_DEST_AC1         FIELD32(0x0000000c)
 877 #define TX_DMA_DST_CSR_DEST_AC2         FIELD32(0x00000030)
 878 #define TX_DMA_DST_CSR_DEST_AC3         FIELD32(0x000000c0)
 879 #define TX_DMA_DST_CSR_DEST_MGMT        FIELD32(0x00000300)
 880
 881 /*
 882  * TX_CNTL_CSR: KICK/Abort TX.
 883  * KICK_TX_AC0: For AC_BK.
 884  * KICK_TX_AC1: For AC_BE.
 885  * KICK_TX_AC2: For AC_VI.
 886  * KICK_TX_AC3: For AC_VO.
 887  * ABORT_TX_AC0: For AC_BK.
 888  * ABORT_TX_AC1: For AC_BE.
 889  * ABORT_TX_AC2: For AC_VI.
 890  * ABORT_TX_AC3: For AC_VO.
 891  */
 892 #define TX_CNTL_CSR                     0x3430
 893 #define TX_CNTL_CSR_KICK_TX_AC0         FIELD32(0x00000001)
 894 #define TX_CNTL_CSR_KICK_TX_AC1         FIELD32(0x00000002)
 895 #define TX_CNTL_CSR_KICK_TX_AC2         FIELD32(0x00000004)
 896 #define TX_CNTL_CSR_KICK_TX_AC3         FIELD32(0x00000008)
 897 #define TX_CNTL_CSR_KICK_TX_MGMT        FIELD32(0x00000010)
 898 #define TX_CNTL_CSR_ABORT_TX_AC0        FIELD32(0x00010000)
 899 #define TX_CNTL_CSR_ABORT_TX_AC1        FIELD32(0x00020000)
 900 #define TX_CNTL_CSR_ABORT_TX_AC2        FIELD32(0x00040000)
 901 #define TX_CNTL_CSR_ABORT_TX_AC3        FIELD32(0x00080000)
 902 #define TX_CNTL_CSR_ABORT_TX_MGMT       FIELD32(0x00100000)
 903
 904 /*
 905  * LOAD_TX_RING_CSR: Load RX desriptor
 906  */
 907 #define LOAD_TX_RING_CSR                0x3434
 908 #define LOAD_TX_RING_CSR_LOAD_TXD_AC0   FIELD32(0x00000001)
 909 #define LOAD_TX_RING_CSR_LOAD_TXD_AC1   FIELD32(0x00000002)
 910 #define LOAD_TX_RING_CSR_LOAD_TXD_AC2   FIELD32(0x00000004)
 911 #define LOAD_TX_RING_CSR_LOAD_TXD_AC3   FIELD32(0x00000008)
 912 #define LOAD_TX_RING_CSR_LOAD_TXD_MGMT  FIELD32(0x00000010)
 913
 914 /*
 915  * Several read-only registers, for debugging.
 916  */
 917 #define AC0_TXPTR_CSR                   0x3438
 918 #define AC1_TXPTR_CSR                   0x343c
 919 #define AC2_TXPTR_CSR                   0x3440
 920 #define AC3_TXPTR_CSR                   0x3444
 921 #define MGMT_TXPTR_CSR                  0x3448
 922
 923 /*
 924  * RX_BASE_CSR
 925  */
 926 #define RX_BASE_CSR                     0x3450
 927 #define RX_BASE_CSR_RING_REGISTER       FIELD32(0xffffffff)
 928
 929 /*
 930  * RX_RING_CSR.
 931  * RXD_SIZE: In unit of 32-bit.
 932  */
 933 #define RX_RING_CSR                     0x3454
 934 #define RX_RING_CSR_RING_SIZE           FIELD32(0x000000ff)
 935 #define RX_RING_CSR_RXD_SIZE            FIELD32(0x00003f00)
 936 #define RX_RING_CSR_RXD_WRITEBACK_SIZE  FIELD32(0x00070000)
 937
 938 /*
 939  * RX_CNTL_CSR
 940  */
 941 #define RX_CNTL_CSR                     0x3458
 942 #define RX_CNTL_CSR_ENABLE_RX_DMA       FIELD32(0x00000001)
 943 #define RX_CNTL_CSR_LOAD_RXD            FIELD32(0x00000002)
 944
 945 /*
 946  * RXPTR_CSR: Read-only, for debugging.
 947  */
 948 #define RXPTR_CSR                       0x345c
 949
 950 /*
 951  * PCI_CFG_CSR
 952  */
 953 #define PCI_CFG_CSR                     0x3460
 954
 955 /*
 956  * BUF_FORMAT_CSR
 957  */
 958 #define BUF_FORMAT_CSR                  0x3464
 959
 960 /*
 961  * INT_SOURCE_CSR: Interrupt source register.
 962  * Write one to clear corresponding bit.
 963  */
 964 #define INT_SOURCE_CSR                  0x3468
 965 #define INT_SOURCE_CSR_TXDONE           FIELD32(0x00000001)
 966 #define INT_SOURCE_CSR_RXDONE           FIELD32(0x00000002)
 967 #define INT_SOURCE_CSR_BEACON_DONE      FIELD32(0x00000004)
 968 #define INT_SOURCE_CSR_TX_ABORT_DONE    FIELD32(0x00000010)
 969 #define INT_SOURCE_CSR_AC0_DMA_DONE     FIELD32(0x00010000)
 970 #define INT_SOURCE_CSR_AC1_DMA_DONE     FIELD32(0x00020000)
 971 #define INT_SOURCE_CSR_AC2_DMA_DONE     FIELD32(0x00040000)
 972 #define INT_SOURCE_CSR_AC3_DMA_DONE     FIELD32(0x00080000)
 973 #define INT_SOURCE_CSR_MGMT_DMA_DONE    FIELD32(0x00100000)
 974 #define INT_SOURCE_CSR_HCCA_DMA_DONE    FIELD32(0x00200000)
 975
 976 /*
 977  * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
 978  * MITIGATION_PERIOD: Interrupt mitigation in unit of 32 PCI clock.
 979  */
 980 #define INT_MASK_CSR                    0x346c
 981 #define INT_MASK_CSR_TXDONE             FIELD32(0x00000001)
 982 #define INT_MASK_CSR_RXDONE             FIELD32(0x00000002)
 983 #define INT_MASK_CSR_BEACON_DONE        FIELD32(0x00000004)
 984 #define INT_MASK_CSR_TX_ABORT_DONE      FIELD32(0x00000010)
 985 #define INT_MASK_CSR_ENABLE_MITIGATION  FIELD32(0x00000080)
 986 #define INT_MASK_CSR_MITIGATION_PERIOD  FIELD32(0x0000ff00)
 987 #define INT_MASK_CSR_AC0_DMA_DONE       FIELD32(0x00010000)
 988 #define INT_MASK_CSR_AC1_DMA_DONE       FIELD32(0x00020000)
 989 #define INT_MASK_CSR_AC2_DMA_DONE       FIELD32(0x00040000)
 990 #define INT_MASK_CSR_AC3_DMA_DONE       FIELD32(0x00080000)
 991 #define INT_MASK_CSR_MGMT_DMA_DONE      FIELD32(0x00100000)
 992 #define INT_MASK_CSR_HCCA_DMA_DONE      FIELD32(0x00200000)
 993
 994 /*
 995  * E2PROM_CSR: EEPROM control register.
 996  * RELOAD: Write 1 to reload eeprom content.
 997  * TYPE_93C46: 1: 93c46, 0:93c66.
 998  * LOAD_STATUS: 1:loading, 0:done.
 999  */
1000 #define E2PROM_CSR                      0x3470
1001 #define E2PROM_CSR_RELOAD               FIELD32(0x00000001)
1002 #define E2PROM_CSR_DATA_CLOCK           FIELD32(0x00000002)
1003 #define E2PROM_CSR_CHIP_SELECT          FIELD32(0x00000004)
1004 #define E2PROM_CSR_DATA_IN              FIELD32(0x00000008)
1005 #define E2PROM_CSR_DATA_OUT             FIELD32(0x00000010)
1006 #define E2PROM_CSR_TYPE_93C46           FIELD32(0x00000020)
1007 #define E2PROM_CSR_LOAD_STATUS          FIELD32(0x00000040)
1008
1009 /*
1010  * AC_TXOP_CSR0: AC_BK/AC_BE TXOP register.
1011  * AC0_TX_OP: For AC_BK, in unit of 32us.
1012  * AC1_TX_OP: For AC_BE, in unit of 32us.
1013  */
1014 #define AC_TXOP_CSR0                    0x3474
1015 #define AC_TXOP_CSR0_AC0_TX_OP          FIELD32(0x0000ffff)
1016 #define AC_TXOP_CSR0_AC1_TX_OP          FIELD32(0xffff0000)
1017
1018 /*
1019  * AC_TXOP_CSR1: AC_VO/AC_VI TXOP register.
1020  * AC2_TX_OP: For AC_VI, in unit of 32us.
1021  * AC3_TX_OP: For AC_VO, in unit of 32us.
1022  */
1023 #define AC_TXOP_CSR1                    0x3478
1024 #define AC_TXOP_CSR1_AC2_TX_OP          FIELD32(0x0000ffff)
1025 #define AC_TXOP_CSR1_AC3_TX_OP          FIELD32(0xffff0000)
1026
1027 /*
1028  * DMA_STATUS_CSR
1029  */
1030 #define DMA_STATUS_CSR                  0x3480
1031
1032 /*
1033  * TEST_MODE_CSR
1034  */
1035 #define TEST_MODE_CSR                   0x3484
1036
1037 /*
1038  * UART0_TX_CSR
1039  */
1040 #define UART0_TX_CSR                    0x3488
1041
1042 /*
1043  * UART0_RX_CSR
1044  */
1045 #define UART0_RX_CSR                    0x348c
1046
1047 /*
1048  * UART0_FRAME_CSR
1049  */
1050 #define UART0_FRAME_CSR                 0x3490
1051
1052 /*
1053  * UART0_BUFFER_CSR
1054  */
1055 #define UART0_BUFFER_CSR                0x3494
1056
1057 /*
1058  * IO_CNTL_CSR
1059  * RF_PS: Set RF interface value to power save
1060  */
1061 #define IO_CNTL_CSR                     0x3498
1062 #define IO_CNTL_CSR_RF_PS               FIELD32(0x00000004)
1063
1064 /*
1065  * UART_INT_SOURCE_CSR
1066  */
1067 #define UART_INT_SOURCE_CSR             0x34a8
1068
1069 /*
1070  * UART_INT_MASK_CSR
1071  */
1072 #define UART_INT_MASK_CSR               0x34ac
1073
1074 /*
1075  * PBF_QUEUE_CSR
1076  */
1077 #define PBF_QUEUE_CSR                   0x34b0
1078
1079 /*
1080  * Firmware DMA registers.
1081  * Firmware DMA registers are dedicated for MCU usage
1082  * and should not be touched by host driver.
1083  * Therefore we skip the definition of these registers.
1084  */
1085 #define FW_TX_BASE_CSR                  0x34c0
1086 #define FW_TX_START_CSR                 0x34c4
1087 #define FW_TX_LAST_CSR                  0x34c8
1088 #define FW_MODE_CNTL_CSR                0x34cc
1089 #define FW_TXPTR_CSR                    0x34d0
1090
1091 /*
1092  * 8051 firmware image.
1093  */
1094 #define FIRMWARE_RT2561                 "rt2561.bin"
1095 #define FIRMWARE_RT2561s                "rt2561s.bin"
1096 #define FIRMWARE_RT2661                 "rt2661.bin"
1097 #define FIRMWARE_IMAGE_BASE             0x4000
1098
1099 /*
1100  * BBP registers.
1101  * The wordsize of the BBP is 8 bits.
1102  */
1103
1104 /*
1105  * R2
1106  */
1107 #define BBP_R2_BG_MODE                  FIELD8(0x20)
1108
1109 /*
1110  * R3
1111  */
1112 #define BBP_R3_SMART_MODE               FIELD8(0x01)
1113
1114 /*
1115  * R4: RX antenna control
1116  * FRAME_END: 1 - DPDT, 0 - SPDT (Only valid for 802.11G, RF2527 & RF2529)
1117  */
1118
1119 /*
1120  * ANTENNA_CONTROL semantics (guessed):
1121  * 0x1: Software controlled antenna switching (fixed or SW diversity)
1122  * 0x2: Hardware diversity.
1123  */
1124 #define BBP_R4_RX_ANTENNA_CONTROL       FIELD8(0x03)
1125 #define BBP_R4_RX_FRAME_END             FIELD8(0x20)
1126
1127 /*
1128  * R77
1129  */
1130 #define BBP_R77_RX_ANTENNA              FIELD8(0x03)
1131
1132 /*
1133  * RF registers
1134  */
1135
1136 /*
1137  * RF 3
1138  */
1139 #define RF3_TXPOWER                     FIELD32(0x00003e00)
1140
1141 /*
1142  * RF 4
1143  */
1144 #define RF4_FREQ_OFFSET                 FIELD32(0x0003f000)
1145
1146 /*
1147  * EEPROM content.
1148  * The wordsize of the EEPROM is 16 bits.
1149  */
1150
1151 /*
1152  * HW MAC address.
1153  */
1154 #define EEPROM_MAC_ADDR_0               0x0002
1155 #define EEPROM_MAC_ADDR_BYTE0           FIELD16(0x00ff)
1156 #define EEPROM_MAC_ADDR_BYTE1           FIELD16(0xff00)
1157 #define EEPROM_MAC_ADDR1                0x0003
1158 #define EEPROM_MAC_ADDR_BYTE2           FIELD16(0x00ff)
1159 #define EEPROM_MAC_ADDR_BYTE3           FIELD16(0xff00)
1160 #define EEPROM_MAC_ADDR_2               0x0004
1161 #define EEPROM_MAC_ADDR_BYTE4           FIELD16(0x00ff)
1162 #define EEPROM_MAC_ADDR_BYTE5           FIELD16(0xff00)
1163
1164 /*
1165  * EEPROM antenna.
1166  * ANTENNA_NUM: Number of antenna's.
1167  * TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
1168  * RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
1169  * FRAME_TYPE: 0: DPDT , 1: SPDT , noted this bit is valid for g only.
1170  * DYN_TXAGC: Dynamic TX AGC control.
1171  * HARDWARE_RADIO: 1: Hardware controlled radio. Read GPIO0.
1172  * RF_TYPE: Rf_type of this adapter.
1173  */
1174 #define EEPROM_ANTENNA                  0x0010
1175 #define EEPROM_ANTENNA_NUM              FIELD16(0x0003)
1176 #define EEPROM_ANTENNA_TX_DEFAULT       FIELD16(0x000c)
1177 #define EEPROM_ANTENNA_RX_DEFAULT       FIELD16(0x0030)
1178 #define EEPROM_ANTENNA_FRAME_TYPE       FIELD16(0x0040)
1179 #define EEPROM_ANTENNA_DYN_TXAGC        FIELD16(0x0200)
1180 #define EEPROM_ANTENNA_HARDWARE_RADIO   FIELD16(0x0400)
1181 #define EEPROM_ANTENNA_RF_TYPE          FIELD16(0xf800)
1182
1183 /*
1184  * EEPROM NIC config.
1185  * ENABLE_DIVERSITY: 1:enable, 0:disable.
1186  * EXTERNAL_LNA_BG: External LNA enable for 2.4G.
1187  * CARDBUS_ACCEL: 0:enable, 1:disable.
1188  * EXTERNAL_LNA_A: External LNA enable for 5G.
1189  */
1190 #define EEPROM_NIC                      0x0011
1191 #define EEPROM_NIC_ENABLE_DIVERSITY     FIELD16(0x0001)
1192 #define EEPROM_NIC_TX_DIVERSITY         FIELD16(0x0002)
1193 #define EEPROM_NIC_RX_FIXED             FIELD16(0x0004)
1194 #define EEPROM_NIC_TX_FIXED             FIELD16(0x0008)
1195 #define EEPROM_NIC_EXTERNAL_LNA_BG      FIELD16(0x0010)
1196 #define EEPROM_NIC_CARDBUS_ACCEL        FIELD16(0x0020)
1197 #define EEPROM_NIC_EXTERNAL_LNA_A       FIELD16(0x0040)
1198
1199 /*
1200  * EEPROM geography.
1201  * GEO_A: Default geographical setting for 5GHz band
1202  * GEO: Default geographical setting.
1203  */
1204 #define EEPROM_GEOGRAPHY                0x0012
1205 #define EEPROM_GEOGRAPHY_GEO_A          FIELD16(0x00ff)
1206 #define EEPROM_GEOGRAPHY_GEO            FIELD16(0xff00)
1207
1208 /*
1209  * EEPROM BBP.
1210  */
1211 #define EEPROM_BBP_START                0x0013
1212 #define EEPROM_BBP_SIZE                 16
1213 #define EEPROM_BBP_VALUE                FIELD16(0x00ff)
1214 #define EEPROM_BBP_REG_ID               FIELD16(0xff00)
1215
1216 /*
1217  * EEPROM TXPOWER 802.11G
1218  */
1219 #define EEPROM_TXPOWER_G_START          0x0023
1220 #define EEPROM_TXPOWER_G_SIZE           7
1221 #define EEPROM_TXPOWER_G_1              FIELD16(0x00ff)
1222 #define EEPROM_TXPOWER_G_2              FIELD16(0xff00)
1223
1224 /*
1225  * EEPROM Frequency
1226  */
1227 #define EEPROM_FREQ                     0x002f
1228 #define EEPROM_FREQ_OFFSET              FIELD16(0x00ff)
1229 #define EEPROM_FREQ_SEQ_MASK            FIELD16(0xff00)
1230 #define EEPROM_FREQ_SEQ                 FIELD16(0x0300)
1231
1232 /*
1233  * EEPROM LED.
1234  * POLARITY_RDY_G: Polarity RDY_G setting.
1235  * POLARITY_RDY_A: Polarity RDY_A setting.
1236  * POLARITY_ACT: Polarity ACT setting.
1237  * POLARITY_GPIO_0: Polarity GPIO0 setting.
1238  * POLARITY_GPIO_1: Polarity GPIO1 setting.
1239  * POLARITY_GPIO_2: Polarity GPIO2 setting.
1240  * POLARITY_GPIO_3: Polarity GPIO3 setting.
1241  * POLARITY_GPIO_4: Polarity GPIO4 setting.
1242  * LED_MODE: Led mode.
1243  */
1244 #define EEPROM_LED                      0x0030
1245 #define EEPROM_LED_POLARITY_RDY_G       FIELD16(0x0001)
1246 #define EEPROM_LED_POLARITY_RDY_A       FIELD16(0x0002)
1247 #define EEPROM_LED_POLARITY_ACT         FIELD16(0x0004)
1248 #define EEPROM_LED_POLARITY_GPIO_0      FIELD16(0x0008)
1249 #define EEPROM_LED_POLARITY_GPIO_1      FIELD16(0x0010)
1250 #define EEPROM_LED_POLARITY_GPIO_2      FIELD16(0x0020)
1251 #define EEPROM_LED_POLARITY_GPIO_3      FIELD16(0x0040)
1252 #define EEPROM_LED_POLARITY_GPIO_4      FIELD16(0x0080)
1253 #define EEPROM_LED_LED_MODE             FIELD16(0x1f00)
1254
1255 /*
1256  * EEPROM TXPOWER 802.11A
1257  */
1258 #define EEPROM_TXPOWER_A_START          0x0031
1259 #define EEPROM_TXPOWER_A_SIZE           12
1260 #define EEPROM_TXPOWER_A_1              FIELD16(0x00ff)
1261 #define EEPROM_TXPOWER_A_2              FIELD16(0xff00)
1262
1263 /*
1264  * EEPROM RSSI offset 802.11BG
1265  */
1266 #define EEPROM_RSSI_OFFSET_BG           0x004d
1267 #define EEPROM_RSSI_OFFSET_BG_1         FIELD16(0x00ff)
1268 #define EEPROM_RSSI_OFFSET_BG_2         FIELD16(0xff00)
1269
1270 /*
1271  * EEPROM RSSI offset 802.11A
1272  */
1273 #define EEPROM_RSSI_OFFSET_A            0x004e
1274 #define EEPROM_RSSI_OFFSET_A_1          FIELD16(0x00ff)
1275 #define EEPROM_RSSI_OFFSET_A_2          FIELD16(0xff00)
1276
1277 /*
1278  * MCU mailbox commands.
1279  */
1280 #define MCU_SLEEP                       0x30
1281 #define MCU_WAKEUP                      0x31
1282 #define MCU_LED                         0x50
1283 #define MCU_LED_STRENGTH                0x52
1284
1285 /*
1286  * DMA descriptor defines.
1287  */
1288 #define TXD_DESC_SIZE                   ( 16 * sizeof(__le32) )
1289 #define TXINFO_SIZE                     ( 6 * sizeof(__le32) )
1290 #define RXD_DESC_SIZE                   ( 16 * sizeof(__le32) )
1291
1292 /*
1293  * TX descriptor format for TX, PRIO and Beacon Ring.
1294  */
1295
1296 /*
1297  * Word0
1298  * TKIP_MIC: ASIC appends TKIP MIC if TKIP is used.
1299  * KEY_TABLE: Use per-client pairwise KEY table.
1300  * KEY_INDEX:
1301  * Key index (0~31) to the pairwise KEY table.
1302  * 0~3 to shared KEY table 0 (BSS0).
1303  * 4~7 to shared KEY table 1 (BSS1).
1304  * 8~11 to shared KEY table 2 (BSS2).
1305  * 12~15 to shared KEY table 3 (BSS3).
1306  * BURST: Next frame belongs to same "burst" event.
1307  */
1308 #define TXD_W0_OWNER_NIC                FIELD32(0x00000001)
1309 #define TXD_W0_VALID                    FIELD32(0x00000002)
1310 #define TXD_W0_MORE_FRAG                FIELD32(0x00000004)
1311 #define TXD_W0_ACK                      FIELD32(0x00000008)
1312 #define TXD_W0_TIMESTAMP                FIELD32(0x00000010)
1313 #define TXD_W0_OFDM                     FIELD32(0x00000020)
1314 #define TXD_W0_IFS                      FIELD32(0x00000040)
1315 #define TXD_W0_RETRY_MODE               FIELD32(0x00000080)
1316 #define TXD_W0_TKIP_MIC                 FIELD32(0x00000100)
1317 #define TXD_W0_KEY_TABLE                FIELD32(0x00000200)
1318 #define TXD_W0_KEY_INDEX                FIELD32(0x0000fc00)
1319 #define TXD_W0_DATABYTE_COUNT           FIELD32(0x0fff0000)
1320 #define TXD_W0_BURST                    FIELD32(0x10000000)
1321 #define TXD_W0_CIPHER_ALG               FIELD32(0xe0000000)
1322
1323 /*
1324  * Word1
1325  * HOST_Q_ID: EDCA/HCCA queue ID.
1326  * HW_SEQUENCE: MAC overwrites the frame sequence number.
1327  * BUFFER_COUNT: Number of buffers in this TXD.
1328  */
1329 #define TXD_W1_HOST_Q_ID                FIELD32(0x0000000f)
1330 #define TXD_W1_AIFSN                    FIELD32(0x000000f0)
1331 #define TXD_W1_CWMIN                    FIELD32(0x00000f00)
1332 #define TXD_W1_CWMAX                    FIELD32(0x0000f000)
1333 #define TXD_W1_IV_OFFSET                FIELD32(0x003f0000)
1334 #define TXD_W1_PIGGY_BACK               FIELD32(0x01000000)
1335 #define TXD_W1_HW_SEQUENCE              FIELD32(0x10000000)
1336 #define TXD_W1_BUFFER_COUNT             FIELD32(0xe0000000)
1337
1338 /*
1339  * Word2: PLCP information
1340  */
1341 #define TXD_W2_PLCP_SIGNAL              FIELD32(0x000000ff)
1342 #define TXD_W2_PLCP_SERVICE             FIELD32(0x0000ff00)
1343 #define TXD_W2_PLCP_LENGTH_LOW          FIELD32(0x00ff0000)
1344 #define TXD_W2_PLCP_LENGTH_HIGH         FIELD32(0xff000000)
1345
1346 /*
1347  * Word3
1348  */
1349 #define TXD_W3_IV                       FIELD32(0xffffffff)
1350
1351 /*
1352  * Word4
1353  */
1354 #define TXD_W4_EIV                      FIELD32(0xffffffff)
1355
1356 /*
1357  * Word5
1358  * FRAME_OFFSET: Frame start offset inside ASIC TXFIFO (after TXINFO field).
1359  * TXD_W5_PID_SUBTYPE: Driver assigned packet ID index for txdone handler.
1360  * TXD_W5_PID_TYPE: Driver assigned packet ID type for txdone handler.
1361  * WAITING_DMA_DONE_INT: TXD been filled with data
1362  * and waiting for TxDoneISR housekeeping.
1363  */
1364 #define TXD_W5_FRAME_OFFSET             FIELD32(0x000000ff)
1365 #define TXD_W5_PID_SUBTYPE              FIELD32(0x00001f00)
1366 #define TXD_W5_PID_TYPE                 FIELD32(0x0000e000)
1367 #define TXD_W5_TX_POWER                 FIELD32(0x00ff0000)
1368 #define TXD_W5_WAITING_DMA_DONE_INT     FIELD32(0x01000000)
1369
1370 /*
1371  * the above 24-byte is called TXINFO and will be DMAed to MAC block
1372  * through TXFIFO. MAC block use this TXINFO to control the transmission
1373  * behavior of this frame.
1374  * The following fields are not used by MAC block.
1375  * They are used by DMA block and HOST driver only.
1376  * Once a frame has been DMA to ASIC, all the following fields are useless
1377  * to ASIC.
1378  */
1379
1380 /*
1381  * Word6-10: Buffer physical address
1382  */
1383 #define TXD_W6_BUFFER_PHYSICAL_ADDRESS  FIELD32(0xffffffff)
1384 #define TXD_W7_BUFFER_PHYSICAL_ADDRESS  FIELD32(0xffffffff)
1385 #define TXD_W8_BUFFER_PHYSICAL_ADDRESS  FIELD32(0xffffffff)
1386 #define TXD_W9_BUFFER_PHYSICAL_ADDRESS  FIELD32(0xffffffff)
1387 #define TXD_W10_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff)
1388
1389 /*
1390  * Word11-13: Buffer length
1391  */
1392 #define TXD_W11_BUFFER_LENGTH0          FIELD32(0x00000fff)
1393 #define TXD_W11_BUFFER_LENGTH1          FIELD32(0x0fff0000)
1394 #define TXD_W12_BUFFER_LENGTH2          FIELD32(0x00000fff)
1395 #define TXD_W12_BUFFER_LENGTH3          FIELD32(0x0fff0000)
1396 #define TXD_W13_BUFFER_LENGTH4          FIELD32(0x00000fff)
1397
1398 /*
1399  * Word14
1400  */
1401 #define TXD_W14_SK_BUFFER               FIELD32(0xffffffff)
1402
1403 /*
1404  * Word15
1405  */
1406 #define TXD_W15_NEXT_SK_BUFFER          FIELD32(0xffffffff)
1407
1408 /*
1409  * RX descriptor format for RX Ring.
1410  */
1411
1412 /*
1413  * Word0
1414  * CIPHER_ERROR: 1:ICV error, 2:MIC error, 3:invalid key.
1415  * KEY_INDEX: Decryption key actually used.
1416  */
1417 #define RXD_W0_OWNER_NIC                FIELD32(0x00000001)
1418 #define RXD_W0_DROP                     FIELD32(0x00000002)
1419 #define RXD_W0_UNICAST_TO_ME            FIELD32(0x00000004)
1420 #define RXD_W0_MULTICAST                FIELD32(0x00000008)
1421 #define RXD_W0_BROADCAST                FIELD32(0x00000010)
1422 #define RXD_W0_MY_BSS                   FIELD32(0x00000020)
1423 #define RXD_W0_CRC_ERROR                FIELD32(0x00000040)
1424 #define RXD_W0_OFDM                     FIELD32(0x00000080)
1425 #define RXD_W0_CIPHER_ERROR             FIELD32(0x00000300)
1426 #define RXD_W0_KEY_INDEX                FIELD32(0x0000fc00)
1427 #define RXD_W0_DATABYTE_COUNT           FIELD32(0x0fff0000)
1428 #define RXD_W0_CIPHER_ALG               FIELD32(0xe0000000)
1429
1430 /*
1431  * Word1
1432  * SIGNAL: RX raw data rate reported by BBP.
1433  */
1434 #define RXD_W1_SIGNAL                   FIELD32(0x000000ff)
1435 #define RXD_W1_RSSI_AGC                 FIELD32(0x00001f00)
1436 #define RXD_W1_RSSI_LNA                 FIELD32(0x00006000)
1437 #define RXD_W1_FRAME_OFFSET             FIELD32(0x7f000000)
1438
1439 /*
1440  * Word2
1441  * IV: Received IV of originally encrypted.
1442  */
1443 #define RXD_W2_IV                       FIELD32(0xffffffff)
1444
1445 /*
1446  * Word3
1447  * EIV: Received EIV of originally encrypted.
1448  */
1449 #define RXD_W3_EIV                      FIELD32(0xffffffff)
1450
1451 /*
1452  * Word4
1453  * ICV: Received ICV of originally encrypted.
1454  * NOTE: This is a guess, the official definition is "reserved"
1455  */
1456 #define RXD_W4_ICV                      FIELD32(0xffffffff)
1457
1458 /*
1459  * the above 20-byte is called RXINFO and will be DMAed to MAC RX block
1460  * and passed to the HOST driver.
1461  * The following fields are for DMA block and HOST usage only.
1462  * Can't be touched by ASIC MAC block.
1463  */
1464
1465 /*
1466  * Word5
1467  */
1468 #define RXD_W5_BUFFER_PHYSICAL_ADDRESS  FIELD32(0xffffffff)
1469
1470 /*
1471  * Word6-15: Reserved
1472  */
1473 #define RXD_W6_RESERVED                 FIELD32(0xffffffff)
1474 #define RXD_W7_RESERVED                 FIELD32(0xffffffff)
1475 #define RXD_W8_RESERVED                 FIELD32(0xffffffff)
1476 #define RXD_W9_RESERVED                 FIELD32(0xffffffff)
1477 #define RXD_W10_RESERVED                FIELD32(0xffffffff)
1478 #define RXD_W11_RESERVED                FIELD32(0xffffffff)
1479 #define RXD_W12_RESERVED                FIELD32(0xffffffff)
1480 #define RXD_W13_RESERVED                FIELD32(0xffffffff)
1481 #define RXD_W14_RESERVED                FIELD32(0xffffffff)
1482 #define RXD_W15_RESERVED                FIELD32(0xffffffff)
1483
1484 /*
1485  * Macro's for converting txpower from EEPROM to mac80211 value
1486  * and from mac80211 value to register value.
1487  */
1488 #define MIN_TXPOWER     0
1489 #define MAX_TXPOWER     31
1490 #define DEFAULT_TXPOWER 24
1491
1492 #define TXPOWER_FROM_DEV(__txpower) \
1493         (((u8)(__txpower)) > MAX_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
1494
1495 #define TXPOWER_TO_DEV(__txpower) \
1496         clamp_t(char, __txpower, MIN_TXPOWER, MAX_TXPOWER)
1497
1498 #endif /* RT61PCI_H */