2 Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 Abstract: rt73usb device specific routines.
24 Supported chipsets: rt2571W & rt2671.
27 #include <linux/crc-itu-t.h>
28 #include <linux/delay.h>
29 #include <linux/etherdevice.h>
30 #include <linux/init.h>
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/usb.h>
36 #include "rt2x00usb.h"
40 * Allow hardware encryption to be disabled.
42 static int modparam_nohwcrypt
= 0;
43 module_param_named(nohwcrypt
, modparam_nohwcrypt
, bool, S_IRUGO
);
44 MODULE_PARM_DESC(nohwcrypt
, "Disable hardware encryption.");
48 * All access to the CSR registers will go through the methods
49 * rt2x00usb_register_read and rt2x00usb_register_write.
50 * BBP and RF register require indirect register access,
51 * and use the CSR registers BBPCSR and RFCSR to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
55 * between each attampt. When the busy bit is still set at that time,
56 * the access attempt is considered to have failed,
57 * and we will print an error.
58 * The _lock versions must be used if you already hold the csr_mutex
60 #define WAIT_FOR_BBP(__dev, __reg) \
61 rt2x00usb_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg))
62 #define WAIT_FOR_RF(__dev, __reg) \
63 rt2x00usb_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg))
65 static void rt73usb_bbp_write(struct rt2x00_dev
*rt2x00dev
,
66 const unsigned int word
, const u8 value
)
70 mutex_lock(&rt2x00dev
->csr_mutex
);
73 * Wait until the BBP becomes available, afterwards we
74 * can safely write the new data into the register.
76 if (WAIT_FOR_BBP(rt2x00dev
, ®
)) {
78 rt2x00_set_field32(®
, PHY_CSR3_VALUE
, value
);
79 rt2x00_set_field32(®
, PHY_CSR3_REGNUM
, word
);
80 rt2x00_set_field32(®
, PHY_CSR3_BUSY
, 1);
81 rt2x00_set_field32(®
, PHY_CSR3_READ_CONTROL
, 0);
83 rt2x00usb_register_write_lock(rt2x00dev
, PHY_CSR3
, reg
);
86 mutex_unlock(&rt2x00dev
->csr_mutex
);
89 static void rt73usb_bbp_read(struct rt2x00_dev
*rt2x00dev
,
90 const unsigned int word
, u8
*value
)
94 mutex_lock(&rt2x00dev
->csr_mutex
);
97 * Wait until the BBP becomes available, afterwards we
98 * can safely write the read request into the register.
99 * After the data has been written, we wait until hardware
100 * returns the correct value, if at any time the register
101 * doesn't become available in time, reg will be 0xffffffff
102 * which means we return 0xff to the caller.
104 if (WAIT_FOR_BBP(rt2x00dev
, ®
)) {
106 rt2x00_set_field32(®
, PHY_CSR3_REGNUM
, word
);
107 rt2x00_set_field32(®
, PHY_CSR3_BUSY
, 1);
108 rt2x00_set_field32(®
, PHY_CSR3_READ_CONTROL
, 1);
110 rt2x00usb_register_write_lock(rt2x00dev
, PHY_CSR3
, reg
);
112 WAIT_FOR_BBP(rt2x00dev
, ®
);
115 *value
= rt2x00_get_field32(reg
, PHY_CSR3_VALUE
);
117 mutex_unlock(&rt2x00dev
->csr_mutex
);
120 static void rt73usb_rf_write(struct rt2x00_dev
*rt2x00dev
,
121 const unsigned int word
, const u32 value
)
125 mutex_lock(&rt2x00dev
->csr_mutex
);
128 * Wait until the RF becomes available, afterwards we
129 * can safely write the new data into the register.
131 if (WAIT_FOR_RF(rt2x00dev
, ®
)) {
133 rt2x00_set_field32(®
, PHY_CSR4_VALUE
, value
);
135 * RF5225 and RF2527 contain 21 bits per RF register value,
136 * all others contain 20 bits.
138 rt2x00_set_field32(®
, PHY_CSR4_NUMBER_OF_BITS
,
139 20 + (rt2x00_rf(&rt2x00dev
->chip
, RF5225
) ||
140 rt2x00_rf(&rt2x00dev
->chip
, RF2527
)));
141 rt2x00_set_field32(®
, PHY_CSR4_IF_SELECT
, 0);
142 rt2x00_set_field32(®
, PHY_CSR4_BUSY
, 1);
144 rt2x00usb_register_write_lock(rt2x00dev
, PHY_CSR4
, reg
);
145 rt2x00_rf_write(rt2x00dev
, word
, value
);
148 mutex_unlock(&rt2x00dev
->csr_mutex
);
151 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
152 static const struct rt2x00debug rt73usb_rt2x00debug
= {
153 .owner
= THIS_MODULE
,
155 .read
= rt2x00usb_register_read
,
156 .write
= rt2x00usb_register_write
,
157 .flags
= RT2X00DEBUGFS_OFFSET
,
158 .word_base
= CSR_REG_BASE
,
159 .word_size
= sizeof(u32
),
160 .word_count
= CSR_REG_SIZE
/ sizeof(u32
),
163 .read
= rt2x00_eeprom_read
,
164 .write
= rt2x00_eeprom_write
,
165 .word_base
= EEPROM_BASE
,
166 .word_size
= sizeof(u16
),
167 .word_count
= EEPROM_SIZE
/ sizeof(u16
),
170 .read
= rt73usb_bbp_read
,
171 .write
= rt73usb_bbp_write
,
172 .word_base
= BBP_BASE
,
173 .word_size
= sizeof(u8
),
174 .word_count
= BBP_SIZE
/ sizeof(u8
),
177 .read
= rt2x00_rf_read
,
178 .write
= rt73usb_rf_write
,
179 .word_base
= RF_BASE
,
180 .word_size
= sizeof(u32
),
181 .word_count
= RF_SIZE
/ sizeof(u32
),
184 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
186 #ifdef CONFIG_RT2X00_LIB_RFKILL
187 static int rt73usb_rfkill_poll(struct rt2x00_dev
*rt2x00dev
)
191 rt2x00usb_register_read(rt2x00dev
, MAC_CSR13
, ®
);
192 return rt2x00_get_field32(reg
, MAC_CSR13_BIT7
);
195 #define rt73usb_rfkill_poll NULL
196 #endif /* CONFIG_RT2X00_LIB_RFKILL */
198 #ifdef CONFIG_RT2X00_LIB_LEDS
199 static void rt73usb_brightness_set(struct led_classdev
*led_cdev
,
200 enum led_brightness brightness
)
202 struct rt2x00_led
*led
=
203 container_of(led_cdev
, struct rt2x00_led
, led_dev
);
204 unsigned int enabled
= brightness
!= LED_OFF
;
205 unsigned int a_mode
=
206 (enabled
&& led
->rt2x00dev
->curr_band
== IEEE80211_BAND_5GHZ
);
207 unsigned int bg_mode
=
208 (enabled
&& led
->rt2x00dev
->curr_band
== IEEE80211_BAND_2GHZ
);
210 if (led
->type
== LED_TYPE_RADIO
) {
211 rt2x00_set_field16(&led
->rt2x00dev
->led_mcu_reg
,
212 MCU_LEDCS_RADIO_STATUS
, enabled
);
214 rt2x00usb_vendor_request_sw(led
->rt2x00dev
, USB_LED_CONTROL
,
215 0, led
->rt2x00dev
->led_mcu_reg
,
217 } else if (led
->type
== LED_TYPE_ASSOC
) {
218 rt2x00_set_field16(&led
->rt2x00dev
->led_mcu_reg
,
219 MCU_LEDCS_LINK_BG_STATUS
, bg_mode
);
220 rt2x00_set_field16(&led
->rt2x00dev
->led_mcu_reg
,
221 MCU_LEDCS_LINK_A_STATUS
, a_mode
);
223 rt2x00usb_vendor_request_sw(led
->rt2x00dev
, USB_LED_CONTROL
,
224 0, led
->rt2x00dev
->led_mcu_reg
,
226 } else if (led
->type
== LED_TYPE_QUALITY
) {
228 * The brightness is divided into 6 levels (0 - 5),
229 * this means we need to convert the brightness
230 * argument into the matching level within that range.
232 rt2x00usb_vendor_request_sw(led
->rt2x00dev
, USB_LED_CONTROL
,
233 brightness
/ (LED_FULL
/ 6),
234 led
->rt2x00dev
->led_mcu_reg
,
239 static int rt73usb_blink_set(struct led_classdev
*led_cdev
,
240 unsigned long *delay_on
,
241 unsigned long *delay_off
)
243 struct rt2x00_led
*led
=
244 container_of(led_cdev
, struct rt2x00_led
, led_dev
);
247 rt2x00usb_register_read(led
->rt2x00dev
, MAC_CSR14
, ®
);
248 rt2x00_set_field32(®
, MAC_CSR14_ON_PERIOD
, *delay_on
);
249 rt2x00_set_field32(®
, MAC_CSR14_OFF_PERIOD
, *delay_off
);
250 rt2x00usb_register_write(led
->rt2x00dev
, MAC_CSR14
, reg
);
255 static void rt73usb_init_led(struct rt2x00_dev
*rt2x00dev
,
256 struct rt2x00_led
*led
,
259 led
->rt2x00dev
= rt2x00dev
;
261 led
->led_dev
.brightness_set
= rt73usb_brightness_set
;
262 led
->led_dev
.blink_set
= rt73usb_blink_set
;
263 led
->flags
= LED_INITIALIZED
;
265 #endif /* CONFIG_RT2X00_LIB_LEDS */
268 * Configuration handlers.
270 static int rt73usb_config_shared_key(struct rt2x00_dev
*rt2x00dev
,
271 struct rt2x00lib_crypto
*crypto
,
272 struct ieee80211_key_conf
*key
)
274 struct hw_key_entry key_entry
;
275 struct rt2x00_field32 field
;
280 if (crypto
->cmd
== SET_KEY
) {
282 * rt2x00lib can't determine the correct free
283 * key_idx for shared keys. We have 1 register
284 * with key valid bits. The goal is simple, read
285 * the register, if that is full we have no slots
287 * Note that each BSS is allowed to have up to 4
288 * shared keys, so put a mask over the allowed
291 mask
= (0xf << crypto
->bssidx
);
293 rt2x00usb_register_read(rt2x00dev
, SEC_CSR0
, ®
);
296 if (reg
&& reg
== mask
)
299 key
->hw_key_idx
+= reg
? ffz(reg
) : 0;
302 * Upload key to hardware
304 memcpy(key_entry
.key
, crypto
->key
,
305 sizeof(key_entry
.key
));
306 memcpy(key_entry
.tx_mic
, crypto
->tx_mic
,
307 sizeof(key_entry
.tx_mic
));
308 memcpy(key_entry
.rx_mic
, crypto
->rx_mic
,
309 sizeof(key_entry
.rx_mic
));
311 reg
= SHARED_KEY_ENTRY(key
->hw_key_idx
);
312 timeout
= REGISTER_TIMEOUT32(sizeof(key_entry
));
313 rt2x00usb_vendor_request_large_buff(rt2x00dev
, USB_MULTI_WRITE
,
314 USB_VENDOR_REQUEST_OUT
, reg
,
320 * The cipher types are stored over 2 registers.
321 * bssidx 0 and 1 keys are stored in SEC_CSR1 and
322 * bssidx 1 and 2 keys are stored in SEC_CSR5.
323 * Using the correct defines correctly will cause overhead,
324 * so just calculate the correct offset.
326 if (key
->hw_key_idx
< 8) {
327 field
.bit_offset
= (3 * key
->hw_key_idx
);
328 field
.bit_mask
= 0x7 << field
.bit_offset
;
330 rt2x00usb_register_read(rt2x00dev
, SEC_CSR1
, ®
);
331 rt2x00_set_field32(®
, field
, crypto
->cipher
);
332 rt2x00usb_register_write(rt2x00dev
, SEC_CSR1
, reg
);
334 field
.bit_offset
= (3 * (key
->hw_key_idx
- 8));
335 field
.bit_mask
= 0x7 << field
.bit_offset
;
337 rt2x00usb_register_read(rt2x00dev
, SEC_CSR5
, ®
);
338 rt2x00_set_field32(®
, field
, crypto
->cipher
);
339 rt2x00usb_register_write(rt2x00dev
, SEC_CSR5
, reg
);
343 * The driver does not support the IV/EIV generation
344 * in hardware. However it doesn't support the IV/EIV
345 * inside the ieee80211 frame either, but requires it
346 * to be provided seperately for the descriptor.
347 * rt2x00lib will cut the IV/EIV data out of all frames
348 * given to us by mac80211, but we must tell mac80211
349 * to generate the IV/EIV data.
351 key
->flags
|= IEEE80211_KEY_FLAG_GENERATE_IV
;
355 * SEC_CSR0 contains only single-bit fields to indicate
356 * a particular key is valid. Because using the FIELD32()
357 * defines directly will cause a lot of overhead we use
358 * a calculation to determine the correct bit directly.
360 mask
= 1 << key
->hw_key_idx
;
362 rt2x00usb_register_read(rt2x00dev
, SEC_CSR0
, ®
);
363 if (crypto
->cmd
== SET_KEY
)
365 else if (crypto
->cmd
== DISABLE_KEY
)
367 rt2x00usb_register_write(rt2x00dev
, SEC_CSR0
, reg
);
372 static int rt73usb_config_pairwise_key(struct rt2x00_dev
*rt2x00dev
,
373 struct rt2x00lib_crypto
*crypto
,
374 struct ieee80211_key_conf
*key
)
376 struct hw_pairwise_ta_entry addr_entry
;
377 struct hw_key_entry key_entry
;
382 if (crypto
->cmd
== SET_KEY
) {
384 * rt2x00lib can't determine the correct free
385 * key_idx for pairwise keys. We have 2 registers
386 * with key valid bits. The goal is simple, read
387 * the first register, if that is full move to
389 * When both registers are full, we drop the key,
390 * otherwise we use the first invalid entry.
392 rt2x00usb_register_read(rt2x00dev
, SEC_CSR2
, ®
);
393 if (reg
&& reg
== ~0) {
394 key
->hw_key_idx
= 32;
395 rt2x00usb_register_read(rt2x00dev
, SEC_CSR3
, ®
);
396 if (reg
&& reg
== ~0)
400 key
->hw_key_idx
+= reg
? ffz(reg
) : 0;
403 * Upload key to hardware
405 memcpy(key_entry
.key
, crypto
->key
,
406 sizeof(key_entry
.key
));
407 memcpy(key_entry
.tx_mic
, crypto
->tx_mic
,
408 sizeof(key_entry
.tx_mic
));
409 memcpy(key_entry
.rx_mic
, crypto
->rx_mic
,
410 sizeof(key_entry
.rx_mic
));
412 reg
= PAIRWISE_KEY_ENTRY(key
->hw_key_idx
);
413 timeout
= REGISTER_TIMEOUT32(sizeof(key_entry
));
414 rt2x00usb_vendor_request_large_buff(rt2x00dev
, USB_MULTI_WRITE
,
415 USB_VENDOR_REQUEST_OUT
, reg
,
421 * Send the address and cipher type to the hardware register.
422 * This data fits within the CSR cache size, so we can use
423 * rt2x00usb_register_multiwrite() directly.
425 memset(&addr_entry
, 0, sizeof(addr_entry
));
426 memcpy(&addr_entry
, crypto
->address
, ETH_ALEN
);
427 addr_entry
.cipher
= crypto
->cipher
;
429 reg
= PAIRWISE_TA_ENTRY(key
->hw_key_idx
);
430 rt2x00usb_register_multiwrite(rt2x00dev
, reg
,
431 &addr_entry
, sizeof(addr_entry
));
434 * Enable pairwise lookup table for given BSS idx,
435 * without this received frames will not be decrypted
438 rt2x00usb_register_read(rt2x00dev
, SEC_CSR4
, ®
);
439 reg
|= (1 << crypto
->bssidx
);
440 rt2x00usb_register_write(rt2x00dev
, SEC_CSR4
, reg
);
443 * The driver does not support the IV/EIV generation
444 * in hardware. However it doesn't support the IV/EIV
445 * inside the ieee80211 frame either, but requires it
446 * to be provided seperately for the descriptor.
447 * rt2x00lib will cut the IV/EIV data out of all frames
448 * given to us by mac80211, but we must tell mac80211
449 * to generate the IV/EIV data.
451 key
->flags
|= IEEE80211_KEY_FLAG_GENERATE_IV
;
455 * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate
456 * a particular key is valid. Because using the FIELD32()
457 * defines directly will cause a lot of overhead we use
458 * a calculation to determine the correct bit directly.
460 if (key
->hw_key_idx
< 32) {
461 mask
= 1 << key
->hw_key_idx
;
463 rt2x00usb_register_read(rt2x00dev
, SEC_CSR2
, ®
);
464 if (crypto
->cmd
== SET_KEY
)
466 else if (crypto
->cmd
== DISABLE_KEY
)
468 rt2x00usb_register_write(rt2x00dev
, SEC_CSR2
, reg
);
470 mask
= 1 << (key
->hw_key_idx
- 32);
472 rt2x00usb_register_read(rt2x00dev
, SEC_CSR3
, ®
);
473 if (crypto
->cmd
== SET_KEY
)
475 else if (crypto
->cmd
== DISABLE_KEY
)
477 rt2x00usb_register_write(rt2x00dev
, SEC_CSR3
, reg
);
483 static void rt73usb_config_filter(struct rt2x00_dev
*rt2x00dev
,
484 const unsigned int filter_flags
)
489 * Start configuration steps.
490 * Note that the version error will always be dropped
491 * and broadcast frames will always be accepted since
492 * there is no filter for it at this time.
494 rt2x00usb_register_read(rt2x00dev
, TXRX_CSR0
, ®
);
495 rt2x00_set_field32(®
, TXRX_CSR0_DROP_CRC
,
496 !(filter_flags
& FIF_FCSFAIL
));
497 rt2x00_set_field32(®
, TXRX_CSR0_DROP_PHYSICAL
,
498 !(filter_flags
& FIF_PLCPFAIL
));
499 rt2x00_set_field32(®
, TXRX_CSR0_DROP_CONTROL
,
500 !(filter_flags
& FIF_CONTROL
));
501 rt2x00_set_field32(®
, TXRX_CSR0_DROP_NOT_TO_ME
,
502 !(filter_flags
& FIF_PROMISC_IN_BSS
));
503 rt2x00_set_field32(®
, TXRX_CSR0_DROP_TO_DS
,
504 !(filter_flags
& FIF_PROMISC_IN_BSS
) &&
505 !rt2x00dev
->intf_ap_count
);
506 rt2x00_set_field32(®
, TXRX_CSR0_DROP_VERSION_ERROR
, 1);
507 rt2x00_set_field32(®
, TXRX_CSR0_DROP_MULTICAST
,
508 !(filter_flags
& FIF_ALLMULTI
));
509 rt2x00_set_field32(®
, TXRX_CSR0_DROP_BROADCAST
, 0);
510 rt2x00_set_field32(®
, TXRX_CSR0_DROP_ACK_CTS
,
511 !(filter_flags
& FIF_CONTROL
));
512 rt2x00usb_register_write(rt2x00dev
, TXRX_CSR0
, reg
);
515 static void rt73usb_config_intf(struct rt2x00_dev
*rt2x00dev
,
516 struct rt2x00_intf
*intf
,
517 struct rt2x00intf_conf
*conf
,
518 const unsigned int flags
)
520 unsigned int beacon_base
;
523 if (flags
& CONFIG_UPDATE_TYPE
) {
525 * Clear current synchronisation setup.
526 * For the Beacon base registers we only need to clear
527 * the first byte since that byte contains the VALID and OWNER
528 * bits which (when set to 0) will invalidate the entire beacon.
530 beacon_base
= HW_BEACON_OFFSET(intf
->beacon
->entry_idx
);
531 rt2x00usb_register_write(rt2x00dev
, beacon_base
, 0);
534 * Enable synchronisation.
536 rt2x00usb_register_read(rt2x00dev
, TXRX_CSR9
, ®
);
537 rt2x00_set_field32(®
, TXRX_CSR9_TSF_TICKING
, 1);
538 rt2x00_set_field32(®
, TXRX_CSR9_TSF_SYNC
, conf
->sync
);
539 rt2x00_set_field32(®
, TXRX_CSR9_TBTT_ENABLE
, 1);
540 rt2x00usb_register_write(rt2x00dev
, TXRX_CSR9
, reg
);
543 if (flags
& CONFIG_UPDATE_MAC
) {
544 reg
= le32_to_cpu(conf
->mac
[1]);
545 rt2x00_set_field32(®
, MAC_CSR3_UNICAST_TO_ME_MASK
, 0xff);
546 conf
->mac
[1] = cpu_to_le32(reg
);
548 rt2x00usb_register_multiwrite(rt2x00dev
, MAC_CSR2
,
549 conf
->mac
, sizeof(conf
->mac
));
552 if (flags
& CONFIG_UPDATE_BSSID
) {
553 reg
= le32_to_cpu(conf
->bssid
[1]);
554 rt2x00_set_field32(®
, MAC_CSR5_BSS_ID_MASK
, 3);
555 conf
->bssid
[1] = cpu_to_le32(reg
);
557 rt2x00usb_register_multiwrite(rt2x00dev
, MAC_CSR4
,
558 conf
->bssid
, sizeof(conf
->bssid
));
562 static void rt73usb_config_erp(struct rt2x00_dev
*rt2x00dev
,
563 struct rt2x00lib_erp
*erp
)
567 rt2x00usb_register_read(rt2x00dev
, TXRX_CSR0
, ®
);
568 rt2x00_set_field32(®
, TXRX_CSR0_RX_ACK_TIMEOUT
, erp
->ack_timeout
);
569 rt2x00usb_register_write(rt2x00dev
, TXRX_CSR0
, reg
);
571 rt2x00usb_register_read(rt2x00dev
, TXRX_CSR4
, ®
);
572 rt2x00_set_field32(®
, TXRX_CSR4_AUTORESPOND_PREAMBLE
,
573 !!erp
->short_preamble
);
574 rt2x00usb_register_write(rt2x00dev
, TXRX_CSR4
, reg
);
576 rt2x00usb_register_write(rt2x00dev
, TXRX_CSR5
, erp
->basic_rates
);
578 rt2x00usb_register_read(rt2x00dev
, MAC_CSR9
, ®
);
579 rt2x00_set_field32(®
, MAC_CSR9_SLOT_TIME
, erp
->slot_time
);
580 rt2x00usb_register_write(rt2x00dev
, MAC_CSR9
, reg
);
582 rt2x00usb_register_read(rt2x00dev
, MAC_CSR8
, ®
);
583 rt2x00_set_field32(®
, MAC_CSR8_SIFS
, erp
->sifs
);
584 rt2x00_set_field32(®
, MAC_CSR8_SIFS_AFTER_RX_OFDM
, 3);
585 rt2x00_set_field32(®
, MAC_CSR8_EIFS
, erp
->eifs
);
586 rt2x00usb_register_write(rt2x00dev
, MAC_CSR8
, reg
);
589 static void rt73usb_config_antenna_5x(struct rt2x00_dev
*rt2x00dev
,
590 struct antenna_setup
*ant
)
597 rt73usb_bbp_read(rt2x00dev
, 3, &r3
);
598 rt73usb_bbp_read(rt2x00dev
, 4, &r4
);
599 rt73usb_bbp_read(rt2x00dev
, 77, &r77
);
601 rt2x00_set_field8(&r3
, BBP_R3_SMART_MODE
, 0);
604 * Configure the RX antenna.
607 case ANTENNA_HW_DIVERSITY
:
608 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 2);
609 temp
= !test_bit(CONFIG_FRAME_TYPE
, &rt2x00dev
->flags
)
610 && (rt2x00dev
->curr_band
!= IEEE80211_BAND_5GHZ
);
611 rt2x00_set_field8(&r4
, BBP_R4_RX_FRAME_END
, temp
);
614 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 1);
615 rt2x00_set_field8(&r4
, BBP_R4_RX_FRAME_END
, 0);
616 if (rt2x00dev
->curr_band
== IEEE80211_BAND_5GHZ
)
617 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 0);
619 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 3);
623 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 1);
624 rt2x00_set_field8(&r4
, BBP_R4_RX_FRAME_END
, 0);
625 if (rt2x00dev
->curr_band
== IEEE80211_BAND_5GHZ
)
626 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 3);
628 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 0);
632 rt73usb_bbp_write(rt2x00dev
, 77, r77
);
633 rt73usb_bbp_write(rt2x00dev
, 3, r3
);
634 rt73usb_bbp_write(rt2x00dev
, 4, r4
);
637 static void rt73usb_config_antenna_2x(struct rt2x00_dev
*rt2x00dev
,
638 struct antenna_setup
*ant
)
644 rt73usb_bbp_read(rt2x00dev
, 3, &r3
);
645 rt73usb_bbp_read(rt2x00dev
, 4, &r4
);
646 rt73usb_bbp_read(rt2x00dev
, 77, &r77
);
648 rt2x00_set_field8(&r3
, BBP_R3_SMART_MODE
, 0);
649 rt2x00_set_field8(&r4
, BBP_R4_RX_FRAME_END
,
650 !test_bit(CONFIG_FRAME_TYPE
, &rt2x00dev
->flags
));
653 * Configure the RX antenna.
656 case ANTENNA_HW_DIVERSITY
:
657 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 2);
660 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 3);
661 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 1);
665 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 0);
666 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 1);
670 rt73usb_bbp_write(rt2x00dev
, 77, r77
);
671 rt73usb_bbp_write(rt2x00dev
, 3, r3
);
672 rt73usb_bbp_write(rt2x00dev
, 4, r4
);
678 * value[0] -> non-LNA
684 static const struct antenna_sel antenna_sel_a
[] = {
685 { 96, { 0x58, 0x78 } },
686 { 104, { 0x38, 0x48 } },
687 { 75, { 0xfe, 0x80 } },
688 { 86, { 0xfe, 0x80 } },
689 { 88, { 0xfe, 0x80 } },
690 { 35, { 0x60, 0x60 } },
691 { 97, { 0x58, 0x58 } },
692 { 98, { 0x58, 0x58 } },
695 static const struct antenna_sel antenna_sel_bg
[] = {
696 { 96, { 0x48, 0x68 } },
697 { 104, { 0x2c, 0x3c } },
698 { 75, { 0xfe, 0x80 } },
699 { 86, { 0xfe, 0x80 } },
700 { 88, { 0xfe, 0x80 } },
701 { 35, { 0x50, 0x50 } },
702 { 97, { 0x48, 0x48 } },
703 { 98, { 0x48, 0x48 } },
706 static void rt73usb_config_ant(struct rt2x00_dev
*rt2x00dev
,
707 struct antenna_setup
*ant
)
709 const struct antenna_sel
*sel
;
715 * We should never come here because rt2x00lib is supposed
716 * to catch this and send us the correct antenna explicitely.
718 BUG_ON(ant
->rx
== ANTENNA_SW_DIVERSITY
||
719 ant
->tx
== ANTENNA_SW_DIVERSITY
);
721 if (rt2x00dev
->curr_band
== IEEE80211_BAND_5GHZ
) {
723 lna
= test_bit(CONFIG_EXTERNAL_LNA_A
, &rt2x00dev
->flags
);
725 sel
= antenna_sel_bg
;
726 lna
= test_bit(CONFIG_EXTERNAL_LNA_BG
, &rt2x00dev
->flags
);
729 for (i
= 0; i
< ARRAY_SIZE(antenna_sel_a
); i
++)
730 rt73usb_bbp_write(rt2x00dev
, sel
[i
].word
, sel
[i
].value
[lna
]);
732 rt2x00usb_register_read(rt2x00dev
, PHY_CSR0
, ®
);
734 rt2x00_set_field32(®
, PHY_CSR0_PA_PE_BG
,
735 (rt2x00dev
->curr_band
== IEEE80211_BAND_2GHZ
));
736 rt2x00_set_field32(®
, PHY_CSR0_PA_PE_A
,
737 (rt2x00dev
->curr_band
== IEEE80211_BAND_5GHZ
));
739 rt2x00usb_register_write(rt2x00dev
, PHY_CSR0
, reg
);
741 if (rt2x00_rf(&rt2x00dev
->chip
, RF5226
) ||
742 rt2x00_rf(&rt2x00dev
->chip
, RF5225
))
743 rt73usb_config_antenna_5x(rt2x00dev
, ant
);
744 else if (rt2x00_rf(&rt2x00dev
->chip
, RF2528
) ||
745 rt2x00_rf(&rt2x00dev
->chip
, RF2527
))
746 rt73usb_config_antenna_2x(rt2x00dev
, ant
);
749 static void rt73usb_config_lna_gain(struct rt2x00_dev
*rt2x00dev
,
750 struct rt2x00lib_conf
*libconf
)
755 if (libconf
->conf
->channel
->band
== IEEE80211_BAND_2GHZ
) {
756 if (test_bit(CONFIG_EXTERNAL_LNA_BG
, &rt2x00dev
->flags
))
759 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_OFFSET_BG
, &eeprom
);
760 lna_gain
-= rt2x00_get_field16(eeprom
, EEPROM_RSSI_OFFSET_BG_1
);
762 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_OFFSET_A
, &eeprom
);
763 lna_gain
-= rt2x00_get_field16(eeprom
, EEPROM_RSSI_OFFSET_A_1
);
766 rt2x00dev
->lna_gain
= lna_gain
;
769 static void rt73usb_config_channel(struct rt2x00_dev
*rt2x00dev
,
770 struct rf_channel
*rf
, const int txpower
)
776 rt2x00_set_field32(&rf
->rf3
, RF3_TXPOWER
, TXPOWER_TO_DEV(txpower
));
777 rt2x00_set_field32(&rf
->rf4
, RF4_FREQ_OFFSET
, rt2x00dev
->freq_offset
);
779 smart
= !(rt2x00_rf(&rt2x00dev
->chip
, RF5225
) ||
780 rt2x00_rf(&rt2x00dev
->chip
, RF2527
));
782 rt73usb_bbp_read(rt2x00dev
, 3, &r3
);
783 rt2x00_set_field8(&r3
, BBP_R3_SMART_MODE
, smart
);
784 rt73usb_bbp_write(rt2x00dev
, 3, r3
);
787 if (txpower
> MAX_TXPOWER
&& txpower
<= (MAX_TXPOWER
+ r94
))
788 r94
+= txpower
- MAX_TXPOWER
;
789 else if (txpower
< MIN_TXPOWER
&& txpower
>= (MIN_TXPOWER
- r94
))
791 rt73usb_bbp_write(rt2x00dev
, 94, r94
);
793 rt73usb_rf_write(rt2x00dev
, 1, rf
->rf1
);
794 rt73usb_rf_write(rt2x00dev
, 2, rf
->rf2
);
795 rt73usb_rf_write(rt2x00dev
, 3, rf
->rf3
& ~0x00000004);
796 rt73usb_rf_write(rt2x00dev
, 4, rf
->rf4
);
798 rt73usb_rf_write(rt2x00dev
, 1, rf
->rf1
);
799 rt73usb_rf_write(rt2x00dev
, 2, rf
->rf2
);
800 rt73usb_rf_write(rt2x00dev
, 3, rf
->rf3
| 0x00000004);
801 rt73usb_rf_write(rt2x00dev
, 4, rf
->rf4
);
803 rt73usb_rf_write(rt2x00dev
, 1, rf
->rf1
);
804 rt73usb_rf_write(rt2x00dev
, 2, rf
->rf2
);
805 rt73usb_rf_write(rt2x00dev
, 3, rf
->rf3
& ~0x00000004);
806 rt73usb_rf_write(rt2x00dev
, 4, rf
->rf4
);
811 static void rt73usb_config_txpower(struct rt2x00_dev
*rt2x00dev
,
814 struct rf_channel rf
;
816 rt2x00_rf_read(rt2x00dev
, 1, &rf
.rf1
);
817 rt2x00_rf_read(rt2x00dev
, 2, &rf
.rf2
);
818 rt2x00_rf_read(rt2x00dev
, 3, &rf
.rf3
);
819 rt2x00_rf_read(rt2x00dev
, 4, &rf
.rf4
);
821 rt73usb_config_channel(rt2x00dev
, &rf
, txpower
);
824 static void rt73usb_config_retry_limit(struct rt2x00_dev
*rt2x00dev
,
825 struct rt2x00lib_conf
*libconf
)
829 rt2x00usb_register_read(rt2x00dev
, TXRX_CSR4
, ®
);
830 rt2x00_set_field32(®
, TXRX_CSR4_LONG_RETRY_LIMIT
,
831 libconf
->conf
->long_frame_max_tx_count
);
832 rt2x00_set_field32(®
, TXRX_CSR4_SHORT_RETRY_LIMIT
,
833 libconf
->conf
->short_frame_max_tx_count
);
834 rt2x00usb_register_write(rt2x00dev
, TXRX_CSR4
, reg
);
837 static void rt73usb_config_duration(struct rt2x00_dev
*rt2x00dev
,
838 struct rt2x00lib_conf
*libconf
)
842 rt2x00usb_register_read(rt2x00dev
, TXRX_CSR0
, ®
);
843 rt2x00_set_field32(®
, TXRX_CSR0_TSF_OFFSET
, IEEE80211_HEADER
);
844 rt2x00usb_register_write(rt2x00dev
, TXRX_CSR0
, reg
);
846 rt2x00usb_register_read(rt2x00dev
, TXRX_CSR4
, ®
);
847 rt2x00_set_field32(®
, TXRX_CSR4_AUTORESPOND_ENABLE
, 1);
848 rt2x00usb_register_write(rt2x00dev
, TXRX_CSR4
, reg
);
850 rt2x00usb_register_read(rt2x00dev
, TXRX_CSR9
, ®
);
851 rt2x00_set_field32(®
, TXRX_CSR9_BEACON_INTERVAL
,
852 libconf
->conf
->beacon_int
* 16);
853 rt2x00usb_register_write(rt2x00dev
, TXRX_CSR9
, reg
);
856 static void rt73usb_config_ps(struct rt2x00_dev
*rt2x00dev
,
857 struct rt2x00lib_conf
*libconf
)
859 enum dev_state state
=
860 (libconf
->conf
->flags
& IEEE80211_CONF_PS
) ?
861 STATE_SLEEP
: STATE_AWAKE
;
864 if (state
== STATE_SLEEP
) {
865 rt2x00usb_register_read(rt2x00dev
, MAC_CSR11
, ®
);
866 rt2x00_set_field32(®
, MAC_CSR11_DELAY_AFTER_TBCN
,
867 libconf
->conf
->beacon_int
- 10);
868 rt2x00_set_field32(®
, MAC_CSR11_TBCN_BEFORE_WAKEUP
,
869 libconf
->conf
->listen_interval
- 1);
870 rt2x00_set_field32(®
, MAC_CSR11_WAKEUP_LATENCY
, 5);
872 /* We must first disable autowake before it can be enabled */
873 rt2x00_set_field32(®
, MAC_CSR11_AUTOWAKE
, 0);
874 rt2x00usb_register_write(rt2x00dev
, MAC_CSR11
, reg
);
876 rt2x00_set_field32(®
, MAC_CSR11_AUTOWAKE
, 1);
877 rt2x00usb_register_write(rt2x00dev
, MAC_CSR11
, reg
);
879 rt2x00usb_vendor_request_sw(rt2x00dev
, USB_DEVICE_MODE
, 0,
880 USB_MODE_SLEEP
, REGISTER_TIMEOUT
);
882 rt2x00usb_vendor_request_sw(rt2x00dev
, USB_DEVICE_MODE
, 0,
883 USB_MODE_WAKEUP
, REGISTER_TIMEOUT
);
885 rt2x00usb_register_read(rt2x00dev
, MAC_CSR11
, ®
);
886 rt2x00_set_field32(®
, MAC_CSR11_DELAY_AFTER_TBCN
, 0);
887 rt2x00_set_field32(®
, MAC_CSR11_TBCN_BEFORE_WAKEUP
, 0);
888 rt2x00_set_field32(®
, MAC_CSR11_AUTOWAKE
, 0);
889 rt2x00_set_field32(®
, MAC_CSR11_WAKEUP_LATENCY
, 0);
890 rt2x00usb_register_write(rt2x00dev
, MAC_CSR11
, reg
);
894 static void rt73usb_config(struct rt2x00_dev
*rt2x00dev
,
895 struct rt2x00lib_conf
*libconf
,
896 const unsigned int flags
)
898 /* Always recalculate LNA gain before changing configuration */
899 rt73usb_config_lna_gain(rt2x00dev
, libconf
);
901 if (flags
& IEEE80211_CONF_CHANGE_CHANNEL
)
902 rt73usb_config_channel(rt2x00dev
, &libconf
->rf
,
903 libconf
->conf
->power_level
);
904 if ((flags
& IEEE80211_CONF_CHANGE_POWER
) &&
905 !(flags
& IEEE80211_CONF_CHANGE_CHANNEL
))
906 rt73usb_config_txpower(rt2x00dev
, libconf
->conf
->power_level
);
907 if (flags
& IEEE80211_CONF_CHANGE_RETRY_LIMITS
)
908 rt73usb_config_retry_limit(rt2x00dev
, libconf
);
909 if (flags
& IEEE80211_CONF_CHANGE_BEACON_INTERVAL
)
910 rt73usb_config_duration(rt2x00dev
, libconf
);
911 if (flags
& IEEE80211_CONF_CHANGE_PS
)
912 rt73usb_config_ps(rt2x00dev
, libconf
);
918 static void rt73usb_link_stats(struct rt2x00_dev
*rt2x00dev
,
919 struct link_qual
*qual
)
924 * Update FCS error count from register.
926 rt2x00usb_register_read(rt2x00dev
, STA_CSR0
, ®
);
927 qual
->rx_failed
= rt2x00_get_field32(reg
, STA_CSR0_FCS_ERROR
);
930 * Update False CCA count from register.
932 rt2x00usb_register_read(rt2x00dev
, STA_CSR1
, ®
);
933 qual
->false_cca
= rt2x00_get_field32(reg
, STA_CSR1_FALSE_CCA_ERROR
);
936 static inline void rt73usb_set_vgc(struct rt2x00_dev
*rt2x00dev
,
937 struct link_qual
*qual
, u8 vgc_level
)
939 if (qual
->vgc_level
!= vgc_level
) {
940 rt73usb_bbp_write(rt2x00dev
, 17, vgc_level
);
941 qual
->vgc_level
= vgc_level
;
942 qual
->vgc_level_reg
= vgc_level
;
946 static void rt73usb_reset_tuner(struct rt2x00_dev
*rt2x00dev
,
947 struct link_qual
*qual
)
949 rt73usb_set_vgc(rt2x00dev
, qual
, 0x20);
952 static void rt73usb_link_tuner(struct rt2x00_dev
*rt2x00dev
,
953 struct link_qual
*qual
, const u32 count
)
959 * Determine r17 bounds.
961 if (rt2x00dev
->rx_status
.band
== IEEE80211_BAND_5GHZ
) {
965 if (test_bit(CONFIG_EXTERNAL_LNA_A
, &rt2x00dev
->flags
)) {
970 if (qual
->rssi
> -82) {
973 } else if (qual
->rssi
> -84) {
981 if (test_bit(CONFIG_EXTERNAL_LNA_BG
, &rt2x00dev
->flags
)) {
988 * If we are not associated, we should go straight to the
989 * dynamic CCA tuning.
991 if (!rt2x00dev
->intf_associated
)
992 goto dynamic_cca_tune
;
995 * Special big-R17 for very short distance
997 if (qual
->rssi
> -35) {
998 rt73usb_set_vgc(rt2x00dev
, qual
, 0x60);
1003 * Special big-R17 for short distance
1005 if (qual
->rssi
>= -58) {
1006 rt73usb_set_vgc(rt2x00dev
, qual
, up_bound
);
1011 * Special big-R17 for middle-short distance
1013 if (qual
->rssi
>= -66) {
1014 rt73usb_set_vgc(rt2x00dev
, qual
, low_bound
+ 0x10);
1019 * Special mid-R17 for middle distance
1021 if (qual
->rssi
>= -74) {
1022 rt73usb_set_vgc(rt2x00dev
, qual
, low_bound
+ 0x08);
1027 * Special case: Change up_bound based on the rssi.
1028 * Lower up_bound when rssi is weaker then -74 dBm.
1030 up_bound
-= 2 * (-74 - qual
->rssi
);
1031 if (low_bound
> up_bound
)
1032 up_bound
= low_bound
;
1034 if (qual
->vgc_level
> up_bound
) {
1035 rt73usb_set_vgc(rt2x00dev
, qual
, up_bound
);
1042 * r17 does not yet exceed upper limit, continue and base
1043 * the r17 tuning on the false CCA count.
1045 if ((qual
->false_cca
> 512) && (qual
->vgc_level
< up_bound
))
1046 rt73usb_set_vgc(rt2x00dev
, qual
,
1047 min_t(u8
, qual
->vgc_level
+ 4, up_bound
));
1048 else if ((qual
->false_cca
< 100) && (qual
->vgc_level
> low_bound
))
1049 rt73usb_set_vgc(rt2x00dev
, qual
,
1050 max_t(u8
, qual
->vgc_level
- 4, low_bound
));
1054 * Firmware functions
1056 static char *rt73usb_get_firmware_name(struct rt2x00_dev
*rt2x00dev
)
1058 return FIRMWARE_RT2571
;
1061 static int rt73usb_check_firmware(struct rt2x00_dev
*rt2x00dev
,
1062 const u8
*data
, const size_t len
)
1068 * Only support 2kb firmware files.
1071 return FW_BAD_LENGTH
;
1074 * The last 2 bytes in the firmware array are the crc checksum itself,
1075 * this means that we should never pass those 2 bytes to the crc
1078 fw_crc
= (data
[len
- 2] << 8 | data
[len
- 1]);
1081 * Use the crc itu-t algorithm.
1083 crc
= crc_itu_t(0, data
, len
- 2);
1084 crc
= crc_itu_t_byte(crc
, 0);
1085 crc
= crc_itu_t_byte(crc
, 0);
1087 return (fw_crc
== crc
) ? FW_OK
: FW_BAD_CRC
;
1090 static int rt73usb_load_firmware(struct rt2x00_dev
*rt2x00dev
,
1091 const u8
*data
, const size_t len
)
1098 * Wait for stable hardware.
1100 for (i
= 0; i
< 100; i
++) {
1101 rt2x00usb_register_read(rt2x00dev
, MAC_CSR0
, ®
);
1108 ERROR(rt2x00dev
, "Unstable hardware.\n");
1113 * Write firmware to device.
1115 rt2x00usb_vendor_request_large_buff(rt2x00dev
, USB_MULTI_WRITE
,
1116 USB_VENDOR_REQUEST_OUT
,
1117 FIRMWARE_IMAGE_BASE
,
1119 REGISTER_TIMEOUT32(len
));
1122 * Send firmware request to device to load firmware,
1123 * we need to specify a long timeout time.
1125 status
= rt2x00usb_vendor_request_sw(rt2x00dev
, USB_DEVICE_MODE
,
1126 0, USB_MODE_FIRMWARE
,
1127 REGISTER_TIMEOUT_FIRMWARE
);
1129 ERROR(rt2x00dev
, "Failed to write Firmware to device.\n");
1137 * Initialization functions.
1139 static int rt73usb_init_registers(struct rt2x00_dev
*rt2x00dev
)
1143 rt2x00usb_register_read(rt2x00dev
, TXRX_CSR0
, ®
);
1144 rt2x00_set_field32(®
, TXRX_CSR0_AUTO_TX_SEQ
, 1);
1145 rt2x00_set_field32(®
, TXRX_CSR0_DISABLE_RX
, 0);
1146 rt2x00_set_field32(®
, TXRX_CSR0_TX_WITHOUT_WAITING
, 0);
1147 rt2x00usb_register_write(rt2x00dev
, TXRX_CSR0
, reg
);
1149 rt2x00usb_register_read(rt2x00dev
, TXRX_CSR1
, ®
);
1150 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID0
, 47); /* CCK Signal */
1151 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID0_VALID
, 1);
1152 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID1
, 30); /* Rssi */
1153 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID1_VALID
, 1);
1154 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID2
, 42); /* OFDM Rate */
1155 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID2_VALID
, 1);
1156 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID3
, 30); /* Rssi */
1157 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID3_VALID
, 1);
1158 rt2x00usb_register_write(rt2x00dev
, TXRX_CSR1
, reg
);
1161 * CCK TXD BBP registers
1163 rt2x00usb_register_read(rt2x00dev
, TXRX_CSR2
, ®
);
1164 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID0
, 13);
1165 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID0_VALID
, 1);
1166 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID1
, 12);
1167 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID1_VALID
, 1);
1168 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID2
, 11);
1169 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID2_VALID
, 1);
1170 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID3
, 10);
1171 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID3_VALID
, 1);
1172 rt2x00usb_register_write(rt2x00dev
, TXRX_CSR2
, reg
);
1175 * OFDM TXD BBP registers
1177 rt2x00usb_register_read(rt2x00dev
, TXRX_CSR3
, ®
);
1178 rt2x00_set_field32(®
, TXRX_CSR3_BBP_ID0
, 7);
1179 rt2x00_set_field32(®
, TXRX_CSR3_BBP_ID0_VALID
, 1);
1180 rt2x00_set_field32(®
, TXRX_CSR3_BBP_ID1
, 6);
1181 rt2x00_set_field32(®
, TXRX_CSR3_BBP_ID1_VALID
, 1);
1182 rt2x00_set_field32(®
, TXRX_CSR3_BBP_ID2
, 5);
1183 rt2x00_set_field32(®
, TXRX_CSR3_BBP_ID2_VALID
, 1);
1184 rt2x00usb_register_write(rt2x00dev
, TXRX_CSR3
, reg
);
1186 rt2x00usb_register_read(rt2x00dev
, TXRX_CSR7
, ®
);
1187 rt2x00_set_field32(®
, TXRX_CSR7_ACK_CTS_6MBS
, 59);
1188 rt2x00_set_field32(®
, TXRX_CSR7_ACK_CTS_9MBS
, 53);
1189 rt2x00_set_field32(®
, TXRX_CSR7_ACK_CTS_12MBS
, 49);
1190 rt2x00_set_field32(®
, TXRX_CSR7_ACK_CTS_18MBS
, 46);
1191 rt2x00usb_register_write(rt2x00dev
, TXRX_CSR7
, reg
);
1193 rt2x00usb_register_read(rt2x00dev
, TXRX_CSR8
, ®
);
1194 rt2x00_set_field32(®
, TXRX_CSR8_ACK_CTS_24MBS
, 44);
1195 rt2x00_set_field32(®
, TXRX_CSR8_ACK_CTS_36MBS
, 42);
1196 rt2x00_set_field32(®
, TXRX_CSR8_ACK_CTS_48MBS
, 42);
1197 rt2x00_set_field32(®
, TXRX_CSR8_ACK_CTS_54MBS
, 42);
1198 rt2x00usb_register_write(rt2x00dev
, TXRX_CSR8
, reg
);
1200 rt2x00usb_register_read(rt2x00dev
, TXRX_CSR9
, ®
);
1201 rt2x00_set_field32(®
, TXRX_CSR9_BEACON_INTERVAL
, 0);
1202 rt2x00_set_field32(®
, TXRX_CSR9_TSF_TICKING
, 0);
1203 rt2x00_set_field32(®
, TXRX_CSR9_TSF_SYNC
, 0);
1204 rt2x00_set_field32(®
, TXRX_CSR9_TBTT_ENABLE
, 0);
1205 rt2x00_set_field32(®
, TXRX_CSR9_BEACON_GEN
, 0);
1206 rt2x00_set_field32(®
, TXRX_CSR9_TIMESTAMP_COMPENSATE
, 0);
1207 rt2x00usb_register_write(rt2x00dev
, TXRX_CSR9
, reg
);
1209 rt2x00usb_register_write(rt2x00dev
, TXRX_CSR15
, 0x0000000f);
1211 rt2x00usb_register_read(rt2x00dev
, MAC_CSR6
, ®
);
1212 rt2x00_set_field32(®
, MAC_CSR6_MAX_FRAME_UNIT
, 0xfff);
1213 rt2x00usb_register_write(rt2x00dev
, MAC_CSR6
, reg
);
1215 rt2x00usb_register_write(rt2x00dev
, MAC_CSR10
, 0x00000718);
1217 if (rt2x00dev
->ops
->lib
->set_device_state(rt2x00dev
, STATE_AWAKE
))
1220 rt2x00usb_register_write(rt2x00dev
, MAC_CSR13
, 0x00007f00);
1223 * Invalidate all Shared Keys (SEC_CSR0),
1224 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1226 rt2x00usb_register_write(rt2x00dev
, SEC_CSR0
, 0x00000000);
1227 rt2x00usb_register_write(rt2x00dev
, SEC_CSR1
, 0x00000000);
1228 rt2x00usb_register_write(rt2x00dev
, SEC_CSR5
, 0x00000000);
1231 if (rt2x00_rf(&rt2x00dev
->chip
, RF5225
) ||
1232 rt2x00_rf(&rt2x00dev
->chip
, RF2527
))
1233 rt2x00_set_field32(®
, PHY_CSR1_RF_RPI
, 1);
1234 rt2x00usb_register_write(rt2x00dev
, PHY_CSR1
, reg
);
1236 rt2x00usb_register_write(rt2x00dev
, PHY_CSR5
, 0x00040a06);
1237 rt2x00usb_register_write(rt2x00dev
, PHY_CSR6
, 0x00080606);
1238 rt2x00usb_register_write(rt2x00dev
, PHY_CSR7
, 0x00000408);
1240 rt2x00usb_register_read(rt2x00dev
, MAC_CSR9
, ®
);
1241 rt2x00_set_field32(®
, MAC_CSR9_CW_SELECT
, 0);
1242 rt2x00usb_register_write(rt2x00dev
, MAC_CSR9
, reg
);
1246 * For the Beacon base registers we only need to clear
1247 * the first byte since that byte contains the VALID and OWNER
1248 * bits which (when set to 0) will invalidate the entire beacon.
1250 rt2x00usb_register_write(rt2x00dev
, HW_BEACON_BASE0
, 0);
1251 rt2x00usb_register_write(rt2x00dev
, HW_BEACON_BASE1
, 0);
1252 rt2x00usb_register_write(rt2x00dev
, HW_BEACON_BASE2
, 0);
1253 rt2x00usb_register_write(rt2x00dev
, HW_BEACON_BASE3
, 0);
1256 * We must clear the error counters.
1257 * These registers are cleared on read,
1258 * so we may pass a useless variable to store the value.
1260 rt2x00usb_register_read(rt2x00dev
, STA_CSR0
, ®
);
1261 rt2x00usb_register_read(rt2x00dev
, STA_CSR1
, ®
);
1262 rt2x00usb_register_read(rt2x00dev
, STA_CSR2
, ®
);
1265 * Reset MAC and BBP registers.
1267 rt2x00usb_register_read(rt2x00dev
, MAC_CSR1
, ®
);
1268 rt2x00_set_field32(®
, MAC_CSR1_SOFT_RESET
, 1);
1269 rt2x00_set_field32(®
, MAC_CSR1_BBP_RESET
, 1);
1270 rt2x00usb_register_write(rt2x00dev
, MAC_CSR1
, reg
);
1272 rt2x00usb_register_read(rt2x00dev
, MAC_CSR1
, ®
);
1273 rt2x00_set_field32(®
, MAC_CSR1_SOFT_RESET
, 0);
1274 rt2x00_set_field32(®
, MAC_CSR1_BBP_RESET
, 0);
1275 rt2x00usb_register_write(rt2x00dev
, MAC_CSR1
, reg
);
1277 rt2x00usb_register_read(rt2x00dev
, MAC_CSR1
, ®
);
1278 rt2x00_set_field32(®
, MAC_CSR1_HOST_READY
, 1);
1279 rt2x00usb_register_write(rt2x00dev
, MAC_CSR1
, reg
);
1284 static int rt73usb_wait_bbp_ready(struct rt2x00_dev
*rt2x00dev
)
1289 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
1290 rt73usb_bbp_read(rt2x00dev
, 0, &value
);
1291 if ((value
!= 0xff) && (value
!= 0x00))
1293 udelay(REGISTER_BUSY_DELAY
);
1296 ERROR(rt2x00dev
, "BBP register access failed, aborting.\n");
1300 static int rt73usb_init_bbp(struct rt2x00_dev
*rt2x00dev
)
1307 if (unlikely(rt73usb_wait_bbp_ready(rt2x00dev
)))
1310 rt73usb_bbp_write(rt2x00dev
, 3, 0x80);
1311 rt73usb_bbp_write(rt2x00dev
, 15, 0x30);
1312 rt73usb_bbp_write(rt2x00dev
, 21, 0xc8);
1313 rt73usb_bbp_write(rt2x00dev
, 22, 0x38);
1314 rt73usb_bbp_write(rt2x00dev
, 23, 0x06);
1315 rt73usb_bbp_write(rt2x00dev
, 24, 0xfe);
1316 rt73usb_bbp_write(rt2x00dev
, 25, 0x0a);
1317 rt73usb_bbp_write(rt2x00dev
, 26, 0x0d);
1318 rt73usb_bbp_write(rt2x00dev
, 32, 0x0b);
1319 rt73usb_bbp_write(rt2x00dev
, 34, 0x12);
1320 rt73usb_bbp_write(rt2x00dev
, 37, 0x07);
1321 rt73usb_bbp_write(rt2x00dev
, 39, 0xf8);
1322 rt73usb_bbp_write(rt2x00dev
, 41, 0x60);
1323 rt73usb_bbp_write(rt2x00dev
, 53, 0x10);
1324 rt73usb_bbp_write(rt2x00dev
, 54, 0x18);
1325 rt73usb_bbp_write(rt2x00dev
, 60, 0x10);
1326 rt73usb_bbp_write(rt2x00dev
, 61, 0x04);
1327 rt73usb_bbp_write(rt2x00dev
, 62, 0x04);
1328 rt73usb_bbp_write(rt2x00dev
, 75, 0xfe);
1329 rt73usb_bbp_write(rt2x00dev
, 86, 0xfe);
1330 rt73usb_bbp_write(rt2x00dev
, 88, 0xfe);
1331 rt73usb_bbp_write(rt2x00dev
, 90, 0x0f);
1332 rt73usb_bbp_write(rt2x00dev
, 99, 0x00);
1333 rt73usb_bbp_write(rt2x00dev
, 102, 0x16);
1334 rt73usb_bbp_write(rt2x00dev
, 107, 0x04);
1336 for (i
= 0; i
< EEPROM_BBP_SIZE
; i
++) {
1337 rt2x00_eeprom_read(rt2x00dev
, EEPROM_BBP_START
+ i
, &eeprom
);
1339 if (eeprom
!= 0xffff && eeprom
!= 0x0000) {
1340 reg_id
= rt2x00_get_field16(eeprom
, EEPROM_BBP_REG_ID
);
1341 value
= rt2x00_get_field16(eeprom
, EEPROM_BBP_VALUE
);
1342 rt73usb_bbp_write(rt2x00dev
, reg_id
, value
);
1350 * Device state switch handlers.
1352 static void rt73usb_toggle_rx(struct rt2x00_dev
*rt2x00dev
,
1353 enum dev_state state
)
1357 rt2x00usb_register_read(rt2x00dev
, TXRX_CSR0
, ®
);
1358 rt2x00_set_field32(®
, TXRX_CSR0_DISABLE_RX
,
1359 (state
== STATE_RADIO_RX_OFF
) ||
1360 (state
== STATE_RADIO_RX_OFF_LINK
));
1361 rt2x00usb_register_write(rt2x00dev
, TXRX_CSR0
, reg
);
1364 static int rt73usb_enable_radio(struct rt2x00_dev
*rt2x00dev
)
1367 * Initialize all registers.
1369 if (unlikely(rt73usb_init_registers(rt2x00dev
) ||
1370 rt73usb_init_bbp(rt2x00dev
)))
1376 static void rt73usb_disable_radio(struct rt2x00_dev
*rt2x00dev
)
1378 rt2x00usb_register_write(rt2x00dev
, MAC_CSR10
, 0x00001818);
1381 * Disable synchronisation.
1383 rt2x00usb_register_write(rt2x00dev
, TXRX_CSR9
, 0);
1385 rt2x00usb_disable_radio(rt2x00dev
);
1388 static int rt73usb_set_state(struct rt2x00_dev
*rt2x00dev
, enum dev_state state
)
1394 put_to_sleep
= (state
!= STATE_AWAKE
);
1396 rt2x00usb_register_read(rt2x00dev
, MAC_CSR12
, ®
);
1397 rt2x00_set_field32(®
, MAC_CSR12_FORCE_WAKEUP
, !put_to_sleep
);
1398 rt2x00_set_field32(®
, MAC_CSR12_PUT_TO_SLEEP
, put_to_sleep
);
1399 rt2x00usb_register_write(rt2x00dev
, MAC_CSR12
, reg
);
1402 * Device is not guaranteed to be in the requested state yet.
1403 * We must wait until the register indicates that the
1404 * device has entered the correct state.
1406 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
1407 rt2x00usb_register_read(rt2x00dev
, MAC_CSR12
, ®
);
1408 state
= rt2x00_get_field32(reg
, MAC_CSR12_BBP_CURRENT_STATE
);
1409 if (state
== !put_to_sleep
)
1417 static int rt73usb_set_device_state(struct rt2x00_dev
*rt2x00dev
,
1418 enum dev_state state
)
1423 case STATE_RADIO_ON
:
1424 retval
= rt73usb_enable_radio(rt2x00dev
);
1426 case STATE_RADIO_OFF
:
1427 rt73usb_disable_radio(rt2x00dev
);
1429 case STATE_RADIO_RX_ON
:
1430 case STATE_RADIO_RX_ON_LINK
:
1431 case STATE_RADIO_RX_OFF
:
1432 case STATE_RADIO_RX_OFF_LINK
:
1433 rt73usb_toggle_rx(rt2x00dev
, state
);
1435 case STATE_RADIO_IRQ_ON
:
1436 case STATE_RADIO_IRQ_OFF
:
1437 /* No support, but no error either */
1439 case STATE_DEEP_SLEEP
:
1443 retval
= rt73usb_set_state(rt2x00dev
, state
);
1450 if (unlikely(retval
))
1451 ERROR(rt2x00dev
, "Device failed to enter state %d (%d).\n",
1458 * TX descriptor initialization
1460 static void rt73usb_write_tx_desc(struct rt2x00_dev
*rt2x00dev
,
1461 struct sk_buff
*skb
,
1462 struct txentry_desc
*txdesc
)
1464 struct skb_frame_desc
*skbdesc
= get_skb_frame_desc(skb
);
1465 __le32
*txd
= skbdesc
->desc
;
1469 * Start writing the descriptor words.
1471 rt2x00_desc_read(txd
, 1, &word
);
1472 rt2x00_set_field32(&word
, TXD_W1_HOST_Q_ID
, txdesc
->queue
);
1473 rt2x00_set_field32(&word
, TXD_W1_AIFSN
, txdesc
->aifs
);
1474 rt2x00_set_field32(&word
, TXD_W1_CWMIN
, txdesc
->cw_min
);
1475 rt2x00_set_field32(&word
, TXD_W1_CWMAX
, txdesc
->cw_max
);
1476 rt2x00_set_field32(&word
, TXD_W1_IV_OFFSET
, txdesc
->iv_offset
);
1477 rt2x00_set_field32(&word
, TXD_W1_HW_SEQUENCE
,
1478 test_bit(ENTRY_TXD_GENERATE_SEQ
, &txdesc
->flags
));
1479 rt2x00_desc_write(txd
, 1, word
);
1481 rt2x00_desc_read(txd
, 2, &word
);
1482 rt2x00_set_field32(&word
, TXD_W2_PLCP_SIGNAL
, txdesc
->signal
);
1483 rt2x00_set_field32(&word
, TXD_W2_PLCP_SERVICE
, txdesc
->service
);
1484 rt2x00_set_field32(&word
, TXD_W2_PLCP_LENGTH_LOW
, txdesc
->length_low
);
1485 rt2x00_set_field32(&word
, TXD_W2_PLCP_LENGTH_HIGH
, txdesc
->length_high
);
1486 rt2x00_desc_write(txd
, 2, word
);
1488 if (test_bit(ENTRY_TXD_ENCRYPT
, &txdesc
->flags
)) {
1489 _rt2x00_desc_write(txd
, 3, skbdesc
->iv
[0]);
1490 _rt2x00_desc_write(txd
, 4, skbdesc
->iv
[1]);
1493 rt2x00_desc_read(txd
, 5, &word
);
1494 rt2x00_set_field32(&word
, TXD_W5_TX_POWER
,
1495 TXPOWER_TO_DEV(rt2x00dev
->tx_power
));
1496 rt2x00_set_field32(&word
, TXD_W5_WAITING_DMA_DONE_INT
, 1);
1497 rt2x00_desc_write(txd
, 5, word
);
1499 rt2x00_desc_read(txd
, 0, &word
);
1500 rt2x00_set_field32(&word
, TXD_W0_BURST
,
1501 test_bit(ENTRY_TXD_BURST
, &txdesc
->flags
));
1502 rt2x00_set_field32(&word
, TXD_W0_VALID
, 1);
1503 rt2x00_set_field32(&word
, TXD_W0_MORE_FRAG
,
1504 test_bit(ENTRY_TXD_MORE_FRAG
, &txdesc
->flags
));
1505 rt2x00_set_field32(&word
, TXD_W0_ACK
,
1506 test_bit(ENTRY_TXD_ACK
, &txdesc
->flags
));
1507 rt2x00_set_field32(&word
, TXD_W0_TIMESTAMP
,
1508 test_bit(ENTRY_TXD_REQ_TIMESTAMP
, &txdesc
->flags
));
1509 rt2x00_set_field32(&word
, TXD_W0_OFDM
,
1510 (txdesc
->rate_mode
== RATE_MODE_OFDM
));
1511 rt2x00_set_field32(&word
, TXD_W0_IFS
, txdesc
->ifs
);
1512 rt2x00_set_field32(&word
, TXD_W0_RETRY_MODE
,
1513 test_bit(ENTRY_TXD_RETRY_MODE
, &txdesc
->flags
));
1514 rt2x00_set_field32(&word
, TXD_W0_TKIP_MIC
,
1515 test_bit(ENTRY_TXD_ENCRYPT_MMIC
, &txdesc
->flags
));
1516 rt2x00_set_field32(&word
, TXD_W0_KEY_TABLE
,
1517 test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE
, &txdesc
->flags
));
1518 rt2x00_set_field32(&word
, TXD_W0_KEY_INDEX
, txdesc
->key_idx
);
1519 rt2x00_set_field32(&word
, TXD_W0_DATABYTE_COUNT
, skb
->len
);
1520 rt2x00_set_field32(&word
, TXD_W0_BURST2
,
1521 test_bit(ENTRY_TXD_BURST
, &txdesc
->flags
));
1522 rt2x00_set_field32(&word
, TXD_W0_CIPHER_ALG
, txdesc
->cipher
);
1523 rt2x00_desc_write(txd
, 0, word
);
1527 * TX data initialization
1529 static void rt73usb_write_beacon(struct queue_entry
*entry
)
1531 struct rt2x00_dev
*rt2x00dev
= entry
->queue
->rt2x00dev
;
1532 struct skb_frame_desc
*skbdesc
= get_skb_frame_desc(entry
->skb
);
1533 unsigned int beacon_base
;
1537 * Add the descriptor in front of the skb.
1539 skb_push(entry
->skb
, entry
->queue
->desc_size
);
1540 memcpy(entry
->skb
->data
, skbdesc
->desc
, skbdesc
->desc_len
);
1541 skbdesc
->desc
= entry
->skb
->data
;
1544 * Disable beaconing while we are reloading the beacon data,
1545 * otherwise we might be sending out invalid data.
1547 rt2x00usb_register_read(rt2x00dev
, TXRX_CSR9
, ®
);
1548 rt2x00_set_field32(®
, TXRX_CSR9_TSF_TICKING
, 0);
1549 rt2x00_set_field32(®
, TXRX_CSR9_TBTT_ENABLE
, 0);
1550 rt2x00_set_field32(®
, TXRX_CSR9_BEACON_GEN
, 0);
1551 rt2x00usb_register_write(rt2x00dev
, TXRX_CSR9
, reg
);
1554 * Write entire beacon with descriptor to register.
1556 beacon_base
= HW_BEACON_OFFSET(entry
->entry_idx
);
1557 rt2x00usb_vendor_request_large_buff(rt2x00dev
, USB_MULTI_WRITE
,
1558 USB_VENDOR_REQUEST_OUT
, beacon_base
,
1559 entry
->skb
->data
, entry
->skb
->len
,
1560 REGISTER_TIMEOUT32(entry
->skb
->len
));
1563 * Clean up the beacon skb.
1565 dev_kfree_skb(entry
->skb
);
1569 static int rt73usb_get_tx_data_len(struct queue_entry
*entry
)
1574 * The length _must_ be a multiple of 4,
1575 * but it must _not_ be a multiple of the USB packet size.
1577 length
= roundup(entry
->skb
->len
, 4);
1578 length
+= (4 * !(length
% entry
->queue
->usb_maxpacket
));
1583 static void rt73usb_kick_tx_queue(struct rt2x00_dev
*rt2x00dev
,
1584 const enum data_queue_qid queue
)
1588 if (queue
!= QID_BEACON
) {
1589 rt2x00usb_kick_tx_queue(rt2x00dev
, queue
);
1594 * For Wi-Fi faily generated beacons between participating stations.
1595 * Set TBTT phase adaptive adjustment step to 8us (default 16us)
1597 rt2x00usb_register_write(rt2x00dev
, TXRX_CSR10
, 0x00001008);
1599 rt2x00usb_register_read(rt2x00dev
, TXRX_CSR9
, ®
);
1600 if (!rt2x00_get_field32(reg
, TXRX_CSR9_BEACON_GEN
)) {
1601 rt2x00_set_field32(®
, TXRX_CSR9_TSF_TICKING
, 1);
1602 rt2x00_set_field32(®
, TXRX_CSR9_TBTT_ENABLE
, 1);
1603 rt2x00_set_field32(®
, TXRX_CSR9_BEACON_GEN
, 1);
1604 rt2x00usb_register_write(rt2x00dev
, TXRX_CSR9
, reg
);
1609 * RX control handlers
1611 static int rt73usb_agc_to_rssi(struct rt2x00_dev
*rt2x00dev
, int rxd_w1
)
1613 u8 offset
= rt2x00dev
->lna_gain
;
1616 lna
= rt2x00_get_field32(rxd_w1
, RXD_W1_RSSI_LNA
);
1631 if (rt2x00dev
->rx_status
.band
== IEEE80211_BAND_5GHZ
) {
1632 if (test_bit(CONFIG_EXTERNAL_LNA_A
, &rt2x00dev
->flags
)) {
1633 if (lna
== 3 || lna
== 2)
1643 return rt2x00_get_field32(rxd_w1
, RXD_W1_RSSI_AGC
) * 2 - offset
;
1646 static void rt73usb_fill_rxdone(struct queue_entry
*entry
,
1647 struct rxdone_entry_desc
*rxdesc
)
1649 struct rt2x00_dev
*rt2x00dev
= entry
->queue
->rt2x00dev
;
1650 struct skb_frame_desc
*skbdesc
= get_skb_frame_desc(entry
->skb
);
1651 __le32
*rxd
= (__le32
*)entry
->skb
->data
;
1656 * Copy descriptor to the skbdesc->desc buffer, making it safe from moving of
1657 * frame data in rt2x00usb.
1659 memcpy(skbdesc
->desc
, rxd
, skbdesc
->desc_len
);
1660 rxd
= (__le32
*)skbdesc
->desc
;
1663 * It is now safe to read the descriptor on all architectures.
1665 rt2x00_desc_read(rxd
, 0, &word0
);
1666 rt2x00_desc_read(rxd
, 1, &word1
);
1668 if (rt2x00_get_field32(word0
, RXD_W0_CRC_ERROR
))
1669 rxdesc
->flags
|= RX_FLAG_FAILED_FCS_CRC
;
1671 if (test_bit(CONFIG_SUPPORT_HW_CRYPTO
, &rt2x00dev
->flags
)) {
1673 rt2x00_get_field32(word0
, RXD_W0_CIPHER_ALG
);
1674 rxdesc
->cipher_status
=
1675 rt2x00_get_field32(word0
, RXD_W0_CIPHER_ERROR
);
1678 if (rxdesc
->cipher
!= CIPHER_NONE
) {
1679 _rt2x00_desc_read(rxd
, 2, &rxdesc
->iv
[0]);
1680 _rt2x00_desc_read(rxd
, 3, &rxdesc
->iv
[1]);
1681 rxdesc
->dev_flags
|= RXDONE_CRYPTO_IV
;
1683 _rt2x00_desc_read(rxd
, 4, &rxdesc
->icv
);
1684 rxdesc
->dev_flags
|= RXDONE_CRYPTO_ICV
;
1687 * Hardware has stripped IV/EIV data from 802.11 frame during
1688 * decryption. It has provided the data seperately but rt2x00lib
1689 * should decide if it should be reinserted.
1691 rxdesc
->flags
|= RX_FLAG_IV_STRIPPED
;
1694 * FIXME: Legacy driver indicates that the frame does
1695 * contain the Michael Mic. Unfortunately, in rt2x00
1696 * the MIC seems to be missing completely...
1698 rxdesc
->flags
|= RX_FLAG_MMIC_STRIPPED
;
1700 if (rxdesc
->cipher_status
== RX_CRYPTO_SUCCESS
)
1701 rxdesc
->flags
|= RX_FLAG_DECRYPTED
;
1702 else if (rxdesc
->cipher_status
== RX_CRYPTO_FAIL_MIC
)
1703 rxdesc
->flags
|= RX_FLAG_MMIC_ERROR
;
1707 * Obtain the status about this packet.
1708 * When frame was received with an OFDM bitrate,
1709 * the signal is the PLCP value. If it was received with
1710 * a CCK bitrate the signal is the rate in 100kbit/s.
1712 rxdesc
->signal
= rt2x00_get_field32(word1
, RXD_W1_SIGNAL
);
1713 rxdesc
->rssi
= rt73usb_agc_to_rssi(rt2x00dev
, word1
);
1714 rxdesc
->size
= rt2x00_get_field32(word0
, RXD_W0_DATABYTE_COUNT
);
1716 if (rt2x00_get_field32(word0
, RXD_W0_OFDM
))
1717 rxdesc
->dev_flags
|= RXDONE_SIGNAL_PLCP
;
1719 rxdesc
->dev_flags
|= RXDONE_SIGNAL_BITRATE
;
1720 if (rt2x00_get_field32(word0
, RXD_W0_MY_BSS
))
1721 rxdesc
->dev_flags
|= RXDONE_MY_BSS
;
1724 * Set skb pointers, and update frame information.
1726 skb_pull(entry
->skb
, entry
->queue
->desc_size
);
1727 skb_trim(entry
->skb
, rxdesc
->size
);
1731 * Device probe functions.
1733 static int rt73usb_validate_eeprom(struct rt2x00_dev
*rt2x00dev
)
1739 rt2x00usb_eeprom_read(rt2x00dev
, rt2x00dev
->eeprom
, EEPROM_SIZE
);
1742 * Start validation of the data that has been read.
1744 mac
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_MAC_ADDR_0
);
1745 if (!is_valid_ether_addr(mac
)) {
1746 random_ether_addr(mac
);
1747 EEPROM(rt2x00dev
, "MAC: %pM\n", mac
);
1750 rt2x00_eeprom_read(rt2x00dev
, EEPROM_ANTENNA
, &word
);
1751 if (word
== 0xffff) {
1752 rt2x00_set_field16(&word
, EEPROM_ANTENNA_NUM
, 2);
1753 rt2x00_set_field16(&word
, EEPROM_ANTENNA_TX_DEFAULT
,
1755 rt2x00_set_field16(&word
, EEPROM_ANTENNA_RX_DEFAULT
,
1757 rt2x00_set_field16(&word
, EEPROM_ANTENNA_FRAME_TYPE
, 0);
1758 rt2x00_set_field16(&word
, EEPROM_ANTENNA_DYN_TXAGC
, 0);
1759 rt2x00_set_field16(&word
, EEPROM_ANTENNA_HARDWARE_RADIO
, 0);
1760 rt2x00_set_field16(&word
, EEPROM_ANTENNA_RF_TYPE
, RF5226
);
1761 rt2x00_eeprom_write(rt2x00dev
, EEPROM_ANTENNA
, word
);
1762 EEPROM(rt2x00dev
, "Antenna: 0x%04x\n", word
);
1765 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC
, &word
);
1766 if (word
== 0xffff) {
1767 rt2x00_set_field16(&word
, EEPROM_NIC_EXTERNAL_LNA
, 0);
1768 rt2x00_eeprom_write(rt2x00dev
, EEPROM_NIC
, word
);
1769 EEPROM(rt2x00dev
, "NIC: 0x%04x\n", word
);
1772 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LED
, &word
);
1773 if (word
== 0xffff) {
1774 rt2x00_set_field16(&word
, EEPROM_LED_POLARITY_RDY_G
, 0);
1775 rt2x00_set_field16(&word
, EEPROM_LED_POLARITY_RDY_A
, 0);
1776 rt2x00_set_field16(&word
, EEPROM_LED_POLARITY_ACT
, 0);
1777 rt2x00_set_field16(&word
, EEPROM_LED_POLARITY_GPIO_0
, 0);
1778 rt2x00_set_field16(&word
, EEPROM_LED_POLARITY_GPIO_1
, 0);
1779 rt2x00_set_field16(&word
, EEPROM_LED_POLARITY_GPIO_2
, 0);
1780 rt2x00_set_field16(&word
, EEPROM_LED_POLARITY_GPIO_3
, 0);
1781 rt2x00_set_field16(&word
, EEPROM_LED_POLARITY_GPIO_4
, 0);
1782 rt2x00_set_field16(&word
, EEPROM_LED_LED_MODE
,
1784 rt2x00_eeprom_write(rt2x00dev
, EEPROM_LED
, word
);
1785 EEPROM(rt2x00dev
, "Led: 0x%04x\n", word
);
1788 rt2x00_eeprom_read(rt2x00dev
, EEPROM_FREQ
, &word
);
1789 if (word
== 0xffff) {
1790 rt2x00_set_field16(&word
, EEPROM_FREQ_OFFSET
, 0);
1791 rt2x00_set_field16(&word
, EEPROM_FREQ_SEQ
, 0);
1792 rt2x00_eeprom_write(rt2x00dev
, EEPROM_FREQ
, word
);
1793 EEPROM(rt2x00dev
, "Freq: 0x%04x\n", word
);
1796 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_OFFSET_BG
, &word
);
1797 if (word
== 0xffff) {
1798 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_BG_1
, 0);
1799 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_BG_2
, 0);
1800 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_OFFSET_BG
, word
);
1801 EEPROM(rt2x00dev
, "RSSI OFFSET BG: 0x%04x\n", word
);
1803 value
= rt2x00_get_field16(word
, EEPROM_RSSI_OFFSET_BG_1
);
1804 if (value
< -10 || value
> 10)
1805 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_BG_1
, 0);
1806 value
= rt2x00_get_field16(word
, EEPROM_RSSI_OFFSET_BG_2
);
1807 if (value
< -10 || value
> 10)
1808 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_BG_2
, 0);
1809 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_OFFSET_BG
, word
);
1812 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_OFFSET_A
, &word
);
1813 if (word
== 0xffff) {
1814 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_A_1
, 0);
1815 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_A_2
, 0);
1816 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_OFFSET_A
, word
);
1817 EEPROM(rt2x00dev
, "RSSI OFFSET A: 0x%04x\n", word
);
1819 value
= rt2x00_get_field16(word
, EEPROM_RSSI_OFFSET_A_1
);
1820 if (value
< -10 || value
> 10)
1821 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_A_1
, 0);
1822 value
= rt2x00_get_field16(word
, EEPROM_RSSI_OFFSET_A_2
);
1823 if (value
< -10 || value
> 10)
1824 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_A_2
, 0);
1825 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_OFFSET_A
, word
);
1831 static int rt73usb_init_eeprom(struct rt2x00_dev
*rt2x00dev
)
1838 * Read EEPROM word for configuration.
1840 rt2x00_eeprom_read(rt2x00dev
, EEPROM_ANTENNA
, &eeprom
);
1843 * Identify RF chipset.
1845 value
= rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_RF_TYPE
);
1846 rt2x00usb_register_read(rt2x00dev
, MAC_CSR0
, ®
);
1847 rt2x00_set_chip(rt2x00dev
, RT2571
, value
, reg
);
1849 if (!rt2x00_check_rev(&rt2x00dev
->chip
, 0x25730)) {
1850 ERROR(rt2x00dev
, "Invalid RT chipset detected.\n");
1854 if (!rt2x00_rf(&rt2x00dev
->chip
, RF5226
) &&
1855 !rt2x00_rf(&rt2x00dev
->chip
, RF2528
) &&
1856 !rt2x00_rf(&rt2x00dev
->chip
, RF5225
) &&
1857 !rt2x00_rf(&rt2x00dev
->chip
, RF2527
)) {
1858 ERROR(rt2x00dev
, "Invalid RF chipset detected.\n");
1863 * Identify default antenna configuration.
1865 rt2x00dev
->default_ant
.tx
=
1866 rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_TX_DEFAULT
);
1867 rt2x00dev
->default_ant
.rx
=
1868 rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_RX_DEFAULT
);
1871 * Read the Frame type.
1873 if (rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_FRAME_TYPE
))
1874 __set_bit(CONFIG_FRAME_TYPE
, &rt2x00dev
->flags
);
1877 * Detect if this device has an hardware controlled radio.
1879 #ifdef CONFIG_RT2X00_LIB_RFKILL
1880 if (rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_HARDWARE_RADIO
))
1881 __set_bit(CONFIG_SUPPORT_HW_BUTTON
, &rt2x00dev
->flags
);
1882 #endif /* CONFIG_RT2X00_LIB_RFKILL */
1885 * Read frequency offset.
1887 rt2x00_eeprom_read(rt2x00dev
, EEPROM_FREQ
, &eeprom
);
1888 rt2x00dev
->freq_offset
= rt2x00_get_field16(eeprom
, EEPROM_FREQ_OFFSET
);
1891 * Read external LNA informations.
1893 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC
, &eeprom
);
1895 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_EXTERNAL_LNA
)) {
1896 __set_bit(CONFIG_EXTERNAL_LNA_A
, &rt2x00dev
->flags
);
1897 __set_bit(CONFIG_EXTERNAL_LNA_BG
, &rt2x00dev
->flags
);
1901 * Store led settings, for correct led behaviour.
1903 #ifdef CONFIG_RT2X00_LIB_LEDS
1904 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LED
, &eeprom
);
1906 rt73usb_init_led(rt2x00dev
, &rt2x00dev
->led_radio
, LED_TYPE_RADIO
);
1907 rt73usb_init_led(rt2x00dev
, &rt2x00dev
->led_assoc
, LED_TYPE_ASSOC
);
1908 if (value
== LED_MODE_SIGNAL_STRENGTH
)
1909 rt73usb_init_led(rt2x00dev
, &rt2x00dev
->led_qual
,
1912 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_LED_MODE
, value
);
1913 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_GPIO_0
,
1914 rt2x00_get_field16(eeprom
,
1915 EEPROM_LED_POLARITY_GPIO_0
));
1916 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_GPIO_1
,
1917 rt2x00_get_field16(eeprom
,
1918 EEPROM_LED_POLARITY_GPIO_1
));
1919 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_GPIO_2
,
1920 rt2x00_get_field16(eeprom
,
1921 EEPROM_LED_POLARITY_GPIO_2
));
1922 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_GPIO_3
,
1923 rt2x00_get_field16(eeprom
,
1924 EEPROM_LED_POLARITY_GPIO_3
));
1925 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_GPIO_4
,
1926 rt2x00_get_field16(eeprom
,
1927 EEPROM_LED_POLARITY_GPIO_4
));
1928 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_ACT
,
1929 rt2x00_get_field16(eeprom
, EEPROM_LED_POLARITY_ACT
));
1930 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_READY_BG
,
1931 rt2x00_get_field16(eeprom
,
1932 EEPROM_LED_POLARITY_RDY_G
));
1933 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_READY_A
,
1934 rt2x00_get_field16(eeprom
,
1935 EEPROM_LED_POLARITY_RDY_A
));
1936 #endif /* CONFIG_RT2X00_LIB_LEDS */
1942 * RF value list for RF2528
1945 static const struct rf_channel rf_vals_bg_2528
[] = {
1946 { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1947 { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1948 { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1949 { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1950 { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1951 { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1952 { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1953 { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1954 { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1955 { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1956 { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1957 { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1958 { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1959 { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1963 * RF value list for RF5226
1964 * Supports: 2.4 GHz & 5.2 GHz
1966 static const struct rf_channel rf_vals_5226
[] = {
1967 { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1968 { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1969 { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1970 { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1971 { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1972 { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1973 { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1974 { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1975 { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1976 { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1977 { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1978 { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1979 { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1980 { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1982 /* 802.11 UNI / HyperLan 2 */
1983 { 36, 0x00002c0c, 0x0000099a, 0x00098255, 0x000fea23 },
1984 { 40, 0x00002c0c, 0x000009a2, 0x00098255, 0x000fea03 },
1985 { 44, 0x00002c0c, 0x000009a6, 0x00098255, 0x000fea0b },
1986 { 48, 0x00002c0c, 0x000009aa, 0x00098255, 0x000fea13 },
1987 { 52, 0x00002c0c, 0x000009ae, 0x00098255, 0x000fea1b },
1988 { 56, 0x00002c0c, 0x000009b2, 0x00098255, 0x000fea23 },
1989 { 60, 0x00002c0c, 0x000009ba, 0x00098255, 0x000fea03 },
1990 { 64, 0x00002c0c, 0x000009be, 0x00098255, 0x000fea0b },
1992 /* 802.11 HyperLan 2 */
1993 { 100, 0x00002c0c, 0x00000a2a, 0x000b8255, 0x000fea03 },
1994 { 104, 0x00002c0c, 0x00000a2e, 0x000b8255, 0x000fea0b },
1995 { 108, 0x00002c0c, 0x00000a32, 0x000b8255, 0x000fea13 },
1996 { 112, 0x00002c0c, 0x00000a36, 0x000b8255, 0x000fea1b },
1997 { 116, 0x00002c0c, 0x00000a3a, 0x000b8255, 0x000fea23 },
1998 { 120, 0x00002c0c, 0x00000a82, 0x000b8255, 0x000fea03 },
1999 { 124, 0x00002c0c, 0x00000a86, 0x000b8255, 0x000fea0b },
2000 { 128, 0x00002c0c, 0x00000a8a, 0x000b8255, 0x000fea13 },
2001 { 132, 0x00002c0c, 0x00000a8e, 0x000b8255, 0x000fea1b },
2002 { 136, 0x00002c0c, 0x00000a92, 0x000b8255, 0x000fea23 },
2005 { 140, 0x00002c0c, 0x00000a9a, 0x000b8255, 0x000fea03 },
2006 { 149, 0x00002c0c, 0x00000aa2, 0x000b8255, 0x000fea1f },
2007 { 153, 0x00002c0c, 0x00000aa6, 0x000b8255, 0x000fea27 },
2008 { 157, 0x00002c0c, 0x00000aae, 0x000b8255, 0x000fea07 },
2009 { 161, 0x00002c0c, 0x00000ab2, 0x000b8255, 0x000fea0f },
2010 { 165, 0x00002c0c, 0x00000ab6, 0x000b8255, 0x000fea17 },
2012 /* MMAC(Japan)J52 ch 34,38,42,46 */
2013 { 34, 0x00002c0c, 0x0008099a, 0x000da255, 0x000d3a0b },
2014 { 38, 0x00002c0c, 0x0008099e, 0x000da255, 0x000d3a13 },
2015 { 42, 0x00002c0c, 0x000809a2, 0x000da255, 0x000d3a1b },
2016 { 46, 0x00002c0c, 0x000809a6, 0x000da255, 0x000d3a23 },
2020 * RF value list for RF5225 & RF2527
2021 * Supports: 2.4 GHz & 5.2 GHz
2023 static const struct rf_channel rf_vals_5225_2527
[] = {
2024 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2025 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2026 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2027 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2028 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2029 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2030 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2031 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2032 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2033 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2034 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2035 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2036 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2037 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2039 /* 802.11 UNI / HyperLan 2 */
2040 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2041 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2042 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2043 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2044 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2045 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2046 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2047 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2049 /* 802.11 HyperLan 2 */
2050 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2051 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2052 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2053 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2054 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2055 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2056 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2057 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2058 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2059 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2062 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2063 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2064 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2065 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2066 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2067 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2069 /* MMAC(Japan)J52 ch 34,38,42,46 */
2070 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2071 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2072 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2073 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2077 static int rt73usb_probe_hw_mode(struct rt2x00_dev
*rt2x00dev
)
2079 struct hw_mode_spec
*spec
= &rt2x00dev
->spec
;
2080 struct channel_info
*info
;
2085 * Initialize all hw fields.
2087 rt2x00dev
->hw
->flags
=
2088 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING
|
2089 IEEE80211_HW_SIGNAL_DBM
|
2090 IEEE80211_HW_SUPPORTS_PS
|
2091 IEEE80211_HW_PS_NULLFUNC_STACK
;
2092 rt2x00dev
->hw
->extra_tx_headroom
= TXD_DESC_SIZE
;
2094 SET_IEEE80211_DEV(rt2x00dev
->hw
, rt2x00dev
->dev
);
2095 SET_IEEE80211_PERM_ADDR(rt2x00dev
->hw
,
2096 rt2x00_eeprom_addr(rt2x00dev
,
2097 EEPROM_MAC_ADDR_0
));
2100 * Initialize hw_mode information.
2102 spec
->supported_bands
= SUPPORT_BAND_2GHZ
;
2103 spec
->supported_rates
= SUPPORT_RATE_CCK
| SUPPORT_RATE_OFDM
;
2105 if (rt2x00_rf(&rt2x00dev
->chip
, RF2528
)) {
2106 spec
->num_channels
= ARRAY_SIZE(rf_vals_bg_2528
);
2107 spec
->channels
= rf_vals_bg_2528
;
2108 } else if (rt2x00_rf(&rt2x00dev
->chip
, RF5226
)) {
2109 spec
->supported_bands
|= SUPPORT_BAND_5GHZ
;
2110 spec
->num_channels
= ARRAY_SIZE(rf_vals_5226
);
2111 spec
->channels
= rf_vals_5226
;
2112 } else if (rt2x00_rf(&rt2x00dev
->chip
, RF2527
)) {
2113 spec
->num_channels
= 14;
2114 spec
->channels
= rf_vals_5225_2527
;
2115 } else if (rt2x00_rf(&rt2x00dev
->chip
, RF5225
)) {
2116 spec
->supported_bands
|= SUPPORT_BAND_5GHZ
;
2117 spec
->num_channels
= ARRAY_SIZE(rf_vals_5225_2527
);
2118 spec
->channels
= rf_vals_5225_2527
;
2122 * Create channel information array
2124 info
= kzalloc(spec
->num_channels
* sizeof(*info
), GFP_KERNEL
);
2128 spec
->channels_info
= info
;
2130 tx_power
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_G_START
);
2131 for (i
= 0; i
< 14; i
++)
2132 info
[i
].tx_power1
= TXPOWER_FROM_DEV(tx_power
[i
]);
2134 if (spec
->num_channels
> 14) {
2135 tx_power
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_A_START
);
2136 for (i
= 14; i
< spec
->num_channels
; i
++)
2137 info
[i
].tx_power1
= TXPOWER_FROM_DEV(tx_power
[i
]);
2143 static int rt73usb_probe_hw(struct rt2x00_dev
*rt2x00dev
)
2148 * Allocate eeprom data.
2150 retval
= rt73usb_validate_eeprom(rt2x00dev
);
2154 retval
= rt73usb_init_eeprom(rt2x00dev
);
2159 * Initialize hw specifications.
2161 retval
= rt73usb_probe_hw_mode(rt2x00dev
);
2166 * This device requires firmware.
2168 __set_bit(DRIVER_REQUIRE_FIRMWARE
, &rt2x00dev
->flags
);
2169 __set_bit(DRIVER_REQUIRE_SCHEDULED
, &rt2x00dev
->flags
);
2170 if (!modparam_nohwcrypt
)
2171 __set_bit(CONFIG_SUPPORT_HW_CRYPTO
, &rt2x00dev
->flags
);
2174 * Set the rssi offset.
2176 rt2x00dev
->rssi_offset
= DEFAULT_RSSI_OFFSET
;
2182 * IEEE80211 stack callback functions.
2184 static int rt73usb_conf_tx(struct ieee80211_hw
*hw
, u16 queue_idx
,
2185 const struct ieee80211_tx_queue_params
*params
)
2187 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
2188 struct data_queue
*queue
;
2189 struct rt2x00_field32 field
;
2195 * First pass the configuration through rt2x00lib, that will
2196 * update the queue settings and validate the input. After that
2197 * we are free to update the registers based on the value
2198 * in the queue parameter.
2200 retval
= rt2x00mac_conf_tx(hw
, queue_idx
, params
);
2205 * We only need to perform additional register initialization
2211 queue
= rt2x00queue_get_queue(rt2x00dev
, queue_idx
);
2213 /* Update WMM TXOP register */
2214 offset
= AC_TXOP_CSR0
+ (sizeof(u32
) * (!!(queue_idx
& 2)));
2215 field
.bit_offset
= (queue_idx
& 1) * 16;
2216 field
.bit_mask
= 0xffff << field
.bit_offset
;
2218 rt2x00usb_register_read(rt2x00dev
, offset
, ®
);
2219 rt2x00_set_field32(®
, field
, queue
->txop
);
2220 rt2x00usb_register_write(rt2x00dev
, offset
, reg
);
2222 /* Update WMM registers */
2223 field
.bit_offset
= queue_idx
* 4;
2224 field
.bit_mask
= 0xf << field
.bit_offset
;
2226 rt2x00usb_register_read(rt2x00dev
, AIFSN_CSR
, ®
);
2227 rt2x00_set_field32(®
, field
, queue
->aifs
);
2228 rt2x00usb_register_write(rt2x00dev
, AIFSN_CSR
, reg
);
2230 rt2x00usb_register_read(rt2x00dev
, CWMIN_CSR
, ®
);
2231 rt2x00_set_field32(®
, field
, queue
->cw_min
);
2232 rt2x00usb_register_write(rt2x00dev
, CWMIN_CSR
, reg
);
2234 rt2x00usb_register_read(rt2x00dev
, CWMAX_CSR
, ®
);
2235 rt2x00_set_field32(®
, field
, queue
->cw_max
);
2236 rt2x00usb_register_write(rt2x00dev
, CWMAX_CSR
, reg
);
2241 static u64
rt73usb_get_tsf(struct ieee80211_hw
*hw
)
2243 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
2247 rt2x00usb_register_read(rt2x00dev
, TXRX_CSR13
, ®
);
2248 tsf
= (u64
) rt2x00_get_field32(reg
, TXRX_CSR13_HIGH_TSFTIMER
) << 32;
2249 rt2x00usb_register_read(rt2x00dev
, TXRX_CSR12
, ®
);
2250 tsf
|= rt2x00_get_field32(reg
, TXRX_CSR12_LOW_TSFTIMER
);
2255 static const struct ieee80211_ops rt73usb_mac80211_ops
= {
2257 .start
= rt2x00mac_start
,
2258 .stop
= rt2x00mac_stop
,
2259 .add_interface
= rt2x00mac_add_interface
,
2260 .remove_interface
= rt2x00mac_remove_interface
,
2261 .config
= rt2x00mac_config
,
2262 .config_interface
= rt2x00mac_config_interface
,
2263 .configure_filter
= rt2x00mac_configure_filter
,
2264 .set_key
= rt2x00mac_set_key
,
2265 .get_stats
= rt2x00mac_get_stats
,
2266 .bss_info_changed
= rt2x00mac_bss_info_changed
,
2267 .conf_tx
= rt73usb_conf_tx
,
2268 .get_tx_stats
= rt2x00mac_get_tx_stats
,
2269 .get_tsf
= rt73usb_get_tsf
,
2272 static const struct rt2x00lib_ops rt73usb_rt2x00_ops
= {
2273 .probe_hw
= rt73usb_probe_hw
,
2274 .get_firmware_name
= rt73usb_get_firmware_name
,
2275 .check_firmware
= rt73usb_check_firmware
,
2276 .load_firmware
= rt73usb_load_firmware
,
2277 .initialize
= rt2x00usb_initialize
,
2278 .uninitialize
= rt2x00usb_uninitialize
,
2279 .clear_entry
= rt2x00usb_clear_entry
,
2280 .set_device_state
= rt73usb_set_device_state
,
2281 .rfkill_poll
= rt73usb_rfkill_poll
,
2282 .link_stats
= rt73usb_link_stats
,
2283 .reset_tuner
= rt73usb_reset_tuner
,
2284 .link_tuner
= rt73usb_link_tuner
,
2285 .write_tx_desc
= rt73usb_write_tx_desc
,
2286 .write_tx_data
= rt2x00usb_write_tx_data
,
2287 .write_beacon
= rt73usb_write_beacon
,
2288 .get_tx_data_len
= rt73usb_get_tx_data_len
,
2289 .kick_tx_queue
= rt73usb_kick_tx_queue
,
2290 .kill_tx_queue
= rt2x00usb_kill_tx_queue
,
2291 .fill_rxdone
= rt73usb_fill_rxdone
,
2292 .config_shared_key
= rt73usb_config_shared_key
,
2293 .config_pairwise_key
= rt73usb_config_pairwise_key
,
2294 .config_filter
= rt73usb_config_filter
,
2295 .config_intf
= rt73usb_config_intf
,
2296 .config_erp
= rt73usb_config_erp
,
2297 .config_ant
= rt73usb_config_ant
,
2298 .config
= rt73usb_config
,
2301 static const struct data_queue_desc rt73usb_queue_rx
= {
2302 .entry_num
= RX_ENTRIES
,
2303 .data_size
= DATA_FRAME_SIZE
,
2304 .desc_size
= RXD_DESC_SIZE
,
2305 .priv_size
= sizeof(struct queue_entry_priv_usb
),
2308 static const struct data_queue_desc rt73usb_queue_tx
= {
2309 .entry_num
= TX_ENTRIES
,
2310 .data_size
= DATA_FRAME_SIZE
,
2311 .desc_size
= TXD_DESC_SIZE
,
2312 .priv_size
= sizeof(struct queue_entry_priv_usb
),
2315 static const struct data_queue_desc rt73usb_queue_bcn
= {
2316 .entry_num
= 4 * BEACON_ENTRIES
,
2317 .data_size
= MGMT_FRAME_SIZE
,
2318 .desc_size
= TXINFO_SIZE
,
2319 .priv_size
= sizeof(struct queue_entry_priv_usb
),
2322 static const struct rt2x00_ops rt73usb_ops
= {
2323 .name
= KBUILD_MODNAME
,
2326 .eeprom_size
= EEPROM_SIZE
,
2328 .tx_queues
= NUM_TX_QUEUES
,
2329 .rx
= &rt73usb_queue_rx
,
2330 .tx
= &rt73usb_queue_tx
,
2331 .bcn
= &rt73usb_queue_bcn
,
2332 .lib
= &rt73usb_rt2x00_ops
,
2333 .hw
= &rt73usb_mac80211_ops
,
2334 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2335 .debugfs
= &rt73usb_rt2x00debug
,
2336 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2340 * rt73usb module information.
2342 static struct usb_device_id rt73usb_device_table
[] = {
2344 { USB_DEVICE(0x07b8, 0xb21b), USB_DEVICE_DATA(&rt73usb_ops
) },
2345 { USB_DEVICE(0x07b8, 0xb21c), USB_DEVICE_DATA(&rt73usb_ops
) },
2346 { USB_DEVICE(0x07b8, 0xb21d), USB_DEVICE_DATA(&rt73usb_ops
) },
2347 { USB_DEVICE(0x07b8, 0xb21e), USB_DEVICE_DATA(&rt73usb_ops
) },
2348 { USB_DEVICE(0x07b8, 0xb21f), USB_DEVICE_DATA(&rt73usb_ops
) },
2350 { USB_DEVICE(0x14b2, 0x3c10), USB_DEVICE_DATA(&rt73usb_ops
) },
2352 { USB_DEVICE(0x148f, 0x9021), USB_DEVICE_DATA(&rt73usb_ops
) },
2353 { USB_DEVICE(0x0eb0, 0x9021), USB_DEVICE_DATA(&rt73usb_ops
) },
2355 { USB_DEVICE(0x18c5, 0x0002), USB_DEVICE_DATA(&rt73usb_ops
) },
2357 { USB_DEVICE(0x1690, 0x0722), USB_DEVICE_DATA(&rt73usb_ops
) },
2359 { USB_DEVICE(0x0b05, 0x1723), USB_DEVICE_DATA(&rt73usb_ops
) },
2360 { USB_DEVICE(0x0b05, 0x1724), USB_DEVICE_DATA(&rt73usb_ops
) },
2362 { USB_DEVICE(0x050d, 0x7050), USB_DEVICE_DATA(&rt73usb_ops
) },
2363 { USB_DEVICE(0x050d, 0x705a), USB_DEVICE_DATA(&rt73usb_ops
) },
2364 { USB_DEVICE(0x050d, 0x905b), USB_DEVICE_DATA(&rt73usb_ops
) },
2365 { USB_DEVICE(0x050d, 0x905c), USB_DEVICE_DATA(&rt73usb_ops
) },
2367 { USB_DEVICE(0x1631, 0xc019), USB_DEVICE_DATA(&rt73usb_ops
) },
2368 { USB_DEVICE(0x08dd, 0x0120), USB_DEVICE_DATA(&rt73usb_ops
) },
2370 { USB_DEVICE(0x0411, 0x00d8), USB_DEVICE_DATA(&rt73usb_ops
) },
2371 { USB_DEVICE(0x0411, 0x00f4), USB_DEVICE_DATA(&rt73usb_ops
) },
2372 { USB_DEVICE(0x0411, 0x0116), USB_DEVICE_DATA(&rt73usb_ops
) },
2373 { USB_DEVICE(0x0411, 0x0119), USB_DEVICE_DATA(&rt73usb_ops
) },
2375 { USB_DEVICE(0x1371, 0x9022), USB_DEVICE_DATA(&rt73usb_ops
) },
2376 { USB_DEVICE(0x1371, 0x9032), USB_DEVICE_DATA(&rt73usb_ops
) },
2378 { USB_DEVICE(0x14b2, 0x3c22), USB_DEVICE_DATA(&rt73usb_ops
) },
2380 { USB_DEVICE(0x07aa, 0x002e), USB_DEVICE_DATA(&rt73usb_ops
) },
2382 { USB_DEVICE(0x07d1, 0x3c03), USB_DEVICE_DATA(&rt73usb_ops
) },
2383 { USB_DEVICE(0x07d1, 0x3c04), USB_DEVICE_DATA(&rt73usb_ops
) },
2384 { USB_DEVICE(0x07d1, 0x3c06), USB_DEVICE_DATA(&rt73usb_ops
) },
2385 { USB_DEVICE(0x07d1, 0x3c07), USB_DEVICE_DATA(&rt73usb_ops
) },
2387 { USB_DEVICE(0x7392, 0x7318), USB_DEVICE_DATA(&rt73usb_ops
) },
2388 { USB_DEVICE(0x7392, 0x7618), USB_DEVICE_DATA(&rt73usb_ops
) },
2390 { USB_DEVICE(0x1740, 0x3701), USB_DEVICE_DATA(&rt73usb_ops
) },
2392 { USB_DEVICE(0x15a9, 0x0004), USB_DEVICE_DATA(&rt73usb_ops
) },
2394 { USB_DEVICE(0x1044, 0x8008), USB_DEVICE_DATA(&rt73usb_ops
) },
2395 { USB_DEVICE(0x1044, 0x800a), USB_DEVICE_DATA(&rt73usb_ops
) },
2397 { USB_DEVICE(0x1472, 0x0009), USB_DEVICE_DATA(&rt73usb_ops
) },
2399 { USB_DEVICE(0x06f8, 0xe010), USB_DEVICE_DATA(&rt73usb_ops
) },
2400 { USB_DEVICE(0x06f8, 0xe020), USB_DEVICE_DATA(&rt73usb_ops
) },
2402 { USB_DEVICE(0x13b1, 0x0020), USB_DEVICE_DATA(&rt73usb_ops
) },
2403 { USB_DEVICE(0x13b1, 0x0023), USB_DEVICE_DATA(&rt73usb_ops
) },
2404 { USB_DEVICE(0x13b1, 0x0028), USB_DEVICE_DATA(&rt73usb_ops
) },
2406 { USB_DEVICE(0x0db0, 0x6877), USB_DEVICE_DATA(&rt73usb_ops
) },
2407 { USB_DEVICE(0x0db0, 0x6874), USB_DEVICE_DATA(&rt73usb_ops
) },
2408 { USB_DEVICE(0x0db0, 0xa861), USB_DEVICE_DATA(&rt73usb_ops
) },
2409 { USB_DEVICE(0x0db0, 0xa874), USB_DEVICE_DATA(&rt73usb_ops
) },
2411 { USB_DEVICE(0x04bb, 0x093d), USB_DEVICE_DATA(&rt73usb_ops
) },
2412 { USB_DEVICE(0x148f, 0x2573), USB_DEVICE_DATA(&rt73usb_ops
) },
2413 { USB_DEVICE(0x148f, 0x2671), USB_DEVICE_DATA(&rt73usb_ops
) },
2415 { USB_DEVICE(0x18e8, 0x6196), USB_DEVICE_DATA(&rt73usb_ops
) },
2416 { USB_DEVICE(0x18e8, 0x6229), USB_DEVICE_DATA(&rt73usb_ops
) },
2417 { USB_DEVICE(0x18e8, 0x6238), USB_DEVICE_DATA(&rt73usb_ops
) },
2419 { USB_DEVICE(0x04e8, 0x4471), USB_DEVICE_DATA(&rt73usb_ops
) },
2421 { USB_DEVICE(0x1740, 0x7100), USB_DEVICE_DATA(&rt73usb_ops
) },
2423 { USB_DEVICE(0x0df6, 0x0024), USB_DEVICE_DATA(&rt73usb_ops
) },
2424 { USB_DEVICE(0x0df6, 0x0027), USB_DEVICE_DATA(&rt73usb_ops
) },
2425 { USB_DEVICE(0x0df6, 0x002f), USB_DEVICE_DATA(&rt73usb_ops
) },
2426 { USB_DEVICE(0x0df6, 0x90ac), USB_DEVICE_DATA(&rt73usb_ops
) },
2427 { USB_DEVICE(0x0df6, 0x9712), USB_DEVICE_DATA(&rt73usb_ops
) },
2429 { USB_DEVICE(0x0769, 0x31f3), USB_DEVICE_DATA(&rt73usb_ops
) },
2431 { USB_DEVICE(0x6933, 0x5001), USB_DEVICE_DATA(&rt73usb_ops
) },
2433 { USB_DEVICE(0x0471, 0x200a), USB_DEVICE_DATA(&rt73usb_ops
) },
2435 { USB_DEVICE(0x2019, 0xab01), USB_DEVICE_DATA(&rt73usb_ops
) },
2436 { USB_DEVICE(0x2019, 0xab50), USB_DEVICE_DATA(&rt73usb_ops
) },
2438 { USB_DEVICE(0x0cde, 0x001c), USB_DEVICE_DATA(&rt73usb_ops
) },
2440 { USB_DEVICE(0x0586, 0x3415), USB_DEVICE_DATA(&rt73usb_ops
) },
2444 MODULE_AUTHOR(DRV_PROJECT
);
2445 MODULE_VERSION(DRV_VERSION
);
2446 MODULE_DESCRIPTION("Ralink RT73 USB Wireless LAN driver.");
2447 MODULE_SUPPORTED_DEVICE("Ralink RT2571W & RT2671 USB chipset based cards");
2448 MODULE_DEVICE_TABLE(usb
, rt73usb_device_table
);
2449 MODULE_FIRMWARE(FIRMWARE_RT2571
);
2450 MODULE_LICENSE("GPL");
2452 static struct usb_driver rt73usb_driver
= {
2453 .name
= KBUILD_MODNAME
,
2454 .id_table
= rt73usb_device_table
,
2455 .probe
= rt2x00usb_probe
,
2456 .disconnect
= rt2x00usb_disconnect
,
2457 .suspend
= rt2x00usb_suspend
,
2458 .resume
= rt2x00usb_resume
,
2461 static int __init
rt73usb_init(void)
2463 return usb_register(&rt73usb_driver
);
2466 static void __exit
rt73usb_exit(void)
2468 usb_deregister(&rt73usb_driver
);
2471 module_init(rt73usb_init
);
2472 module_exit(rt73usb_exit
);