projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
rt2x00: Enable LED class support for rt2500usb/rt73usb
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt73usb.c
1 /*
2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21 /*
22 Module: rt73usb
23 Abstract: rt73usb device specific routines.
24 Supported chipsets: rt2571W & rt2671.
25 */
26
27 #include <linux/delay.h>
28 #include <linux/etherdevice.h>
29 #include <linux/init.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/usb.h>
33
34 #include "rt2x00.h"
35 #include "rt2x00usb.h"
36 #include "rt73usb.h"
37
38 /*
39 * Register access.
40 * All access to the CSR registers will go through the methods
41 * rt73usb_register_read and rt73usb_register_write.
42 * BBP and RF register require indirect register access,
43 * and use the CSR registers BBPCSR and RFCSR to achieve this.
44 * These indirect registers work with busy bits,
45 * and we will try maximal REGISTER_BUSY_COUNT times to access
46 * the register while taking a REGISTER_BUSY_DELAY us delay
47 * between each attampt. When the busy bit is still set at that time,
48 * the access attempt is considered to have failed,
49 * and we will print an error.
50 * The _lock versions must be used if you already hold the usb_cache_mutex
51 */
52 static inline void rt73usb_register_read(struct rt2x00_dev *rt2x00dev,
53 const unsigned int offset, u32 *value)
54 {
55 __le32 reg;
56 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
57 USB_VENDOR_REQUEST_IN, offset,
58 &reg, sizeof(u32), REGISTER_TIMEOUT);
59 *value = le32_to_cpu(reg);
60 }
61
62 static inline void rt73usb_register_read_lock(struct rt2x00_dev *rt2x00dev,
63 const unsigned int offset, u32 *value)
64 {
65 __le32 reg;
66 rt2x00usb_vendor_req_buff_lock(rt2x00dev, USB_MULTI_READ,
67 USB_VENDOR_REQUEST_IN, offset,
68 &reg, sizeof(u32), REGISTER_TIMEOUT);
69 *value = le32_to_cpu(reg);
70 }
71
72 static inline void rt73usb_register_multiread(struct rt2x00_dev *rt2x00dev,
73 const unsigned int offset,
74 void *value, const u32 length)
75 {
76 int timeout = REGISTER_TIMEOUT * (length / sizeof(u32));
77 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
78 USB_VENDOR_REQUEST_IN, offset,
79 value, length, timeout);
80 }
81
82 static inline void rt73usb_register_write(struct rt2x00_dev *rt2x00dev,
83 const unsigned int offset, u32 value)
84 {
85 __le32 reg = cpu_to_le32(value);
86 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
87 USB_VENDOR_REQUEST_OUT, offset,
88 &reg, sizeof(u32), REGISTER_TIMEOUT);
89 }
90
91 static inline void rt73usb_register_write_lock(struct rt2x00_dev *rt2x00dev,
92 const unsigned int offset, u32 value)
93 {
94 __le32 reg = cpu_to_le32(value);
95 rt2x00usb_vendor_req_buff_lock(rt2x00dev, USB_MULTI_WRITE,
96 USB_VENDOR_REQUEST_OUT, offset,
97 &reg, sizeof(u32), REGISTER_TIMEOUT);
98 }
99
100 static inline void rt73usb_register_multiwrite(struct rt2x00_dev *rt2x00dev,
101 const unsigned int offset,
102 void *value, const u32 length)
103 {
104 int timeout = REGISTER_TIMEOUT * (length / sizeof(u32));
105 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
106 USB_VENDOR_REQUEST_OUT, offset,
107 value, length, timeout);
108 }
109
110 static u32 rt73usb_bbp_check(struct rt2x00_dev *rt2x00dev)
111 {
112 u32 reg;
113 unsigned int i;
114
115 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
116 rt73usb_register_read_lock(rt2x00dev, PHY_CSR3, &reg);
117 if (!rt2x00_get_field32(reg, PHY_CSR3_BUSY))
118 break;
119 udelay(REGISTER_BUSY_DELAY);
120 }
121
122 return reg;
123 }
124
125 static void rt73usb_bbp_write(struct rt2x00_dev *rt2x00dev,
126 const unsigned int word, const u8 value)
127 {
128 u32 reg;
129
130 mutex_lock(&rt2x00dev->usb_cache_mutex);
131
132 /*
133 * Wait until the BBP becomes ready.
134 */
135 reg = rt73usb_bbp_check(rt2x00dev);
136 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
137 ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n");
138 mutex_unlock(&rt2x00dev->usb_cache_mutex);
139 return;
140 }
141
142 /*
143 * Write the data into the BBP.
144 */
145 reg = 0;
146 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
147 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
148 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
149 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
150
151 rt73usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
152 mutex_unlock(&rt2x00dev->usb_cache_mutex);
153 }
154
155 static void rt73usb_bbp_read(struct rt2x00_dev *rt2x00dev,
156 const unsigned int word, u8 *value)
157 {
158 u32 reg;
159
160 mutex_lock(&rt2x00dev->usb_cache_mutex);
161
162 /*
163 * Wait until the BBP becomes ready.
164 */
165 reg = rt73usb_bbp_check(rt2x00dev);
166 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
167 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
168 mutex_unlock(&rt2x00dev->usb_cache_mutex);
169 return;
170 }
171
172 /*
173 * Write the request into the BBP.
174 */
175 reg = 0;
176 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
177 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
178 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
179
180 rt73usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
181
182 /*
183 * Wait until the BBP becomes ready.
184 */
185 reg = rt73usb_bbp_check(rt2x00dev);
186 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
187 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
188 *value = 0xff;
189 return;
190 }
191
192 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
193 mutex_unlock(&rt2x00dev->usb_cache_mutex);
194 }
195
196 static void rt73usb_rf_write(struct rt2x00_dev *rt2x00dev,
197 const unsigned int word, const u32 value)
198 {
199 u32 reg;
200 unsigned int i;
201
202 if (!word)
203 return;
204
205 mutex_lock(&rt2x00dev->usb_cache_mutex);
206
207 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
208 rt73usb_register_read_lock(rt2x00dev, PHY_CSR4, &reg);
209 if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY))
210 goto rf_write;
211 udelay(REGISTER_BUSY_DELAY);
212 }
213
214 mutex_unlock(&rt2x00dev->usb_cache_mutex);
215 ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n");
216 return;
217
218 rf_write:
219 reg = 0;
220 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
221
222 /*
223 * RF5225 and RF2527 contain 21 bits per RF register value,
224 * all others contain 20 bits.
225 */
226 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS,
227 20 + (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
228 rt2x00_rf(&rt2x00dev->chip, RF2527)));
229 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
230 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
231
232 rt73usb_register_write_lock(rt2x00dev, PHY_CSR4, reg);
233 rt2x00_rf_write(rt2x00dev, word, value);
234 mutex_unlock(&rt2x00dev->usb_cache_mutex);
235 }
236
237 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
238 #define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
239
240 static void rt73usb_read_csr(struct rt2x00_dev *rt2x00dev,
241 const unsigned int word, u32 *data)
242 {
243 rt73usb_register_read(rt2x00dev, CSR_OFFSET(word), data);
244 }
245
246 static void rt73usb_write_csr(struct rt2x00_dev *rt2x00dev,
247 const unsigned int word, u32 data)
248 {
249 rt73usb_register_write(rt2x00dev, CSR_OFFSET(word), data);
250 }
251
252 static const struct rt2x00debug rt73usb_rt2x00debug = {
253 .owner = THIS_MODULE,
254 .csr = {
255 .read = rt73usb_read_csr,
256 .write = rt73usb_write_csr,
257 .word_size = sizeof(u32),
258 .word_count = CSR_REG_SIZE / sizeof(u32),
259 },
260 .eeprom = {
261 .read = rt2x00_eeprom_read,
262 .write = rt2x00_eeprom_write,
263 .word_size = sizeof(u16),
264 .word_count = EEPROM_SIZE / sizeof(u16),
265 },
266 .bbp = {
267 .read = rt73usb_bbp_read,
268 .write = rt73usb_bbp_write,
269 .word_size = sizeof(u8),
270 .word_count = BBP_SIZE / sizeof(u8),
271 },
272 .rf = {
273 .read = rt2x00_rf_read,
274 .write = rt73usb_rf_write,
275 .word_size = sizeof(u32),
276 .word_count = RF_SIZE / sizeof(u32),
277 },
278 };
279 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
280
281 #ifdef CONFIG_RT73USB_LEDS
282 static void rt73usb_led_brightness(struct led_classdev *led_cdev,
283 enum led_brightness brightness)
284 {
285 struct rt2x00_led *led =
286 container_of(led_cdev, struct rt2x00_led, led_dev);
287 unsigned int enabled = brightness != LED_OFF;
288 unsigned int a_mode =
289 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
290 unsigned int bg_mode =
291 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
292
293 if (led->type == LED_TYPE_RADIO) {
294 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
295 MCU_LEDCS_RADIO_STATUS, enabled);
296
297 rt2x00usb_vendor_request_async(led->rt2x00dev, USB_LED_CONTROL,
298 0, led->rt2x00dev->led_mcu_reg);
299 } else if (led->type == LED_TYPE_ASSOC) {
300 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
301 MCU_LEDCS_LINK_BG_STATUS, bg_mode);
302 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
303 MCU_LEDCS_LINK_A_STATUS, a_mode);
304
305 rt2x00usb_vendor_request_async(led->rt2x00dev, USB_LED_CONTROL,
306 0, led->rt2x00dev->led_mcu_reg);
307 } else if (led->type == LED_TYPE_QUALITY) {
308 /*
309 * The brightness is divided into 6 levels (0 - 5),
310 * this means we need to convert the brightness
311 * argument into the matching level within that range.
312 */
313 rt2x00usb_vendor_request_async(led->rt2x00dev, USB_LED_CONTROL,
314 brightness / (LED_FULL / 6),
315 led->rt2x00dev->led_mcu_reg);
316 }
317 }
318 #else
319 #define rt73usb_led_brightness NULL
320 #endif /* CONFIG_RT73USB_LEDS */
321
322 /*
323 * Configuration handlers.
324 */
325 static void rt73usb_config_intf(struct rt2x00_dev *rt2x00dev,
326 struct rt2x00_intf *intf,
327 struct rt2x00intf_conf *conf,
328 const unsigned int flags)
329 {
330 unsigned int beacon_base;
331 u32 reg;
332
333 if (flags & CONFIG_UPDATE_TYPE) {
334 /*
335 * Clear current synchronisation setup.
336 * For the Beacon base registers we only need to clear
337 * the first byte since that byte contains the VALID and OWNER
338 * bits which (when set to 0) will invalidate the entire beacon.
339 */
340 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
341 rt73usb_register_write(rt2x00dev, TXRX_CSR9, 0);
342 rt73usb_register_write(rt2x00dev, beacon_base, 0);
343
344 /*
345 * Enable synchronisation.
346 */
347 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
348 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
349 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE,
350 (conf->sync == TSF_SYNC_BEACON));
351 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
352 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
353 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
354 }
355
356 if (flags & CONFIG_UPDATE_MAC) {
357 reg = le32_to_cpu(conf->mac[1]);
358 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
359 conf->mac[1] = cpu_to_le32(reg);
360
361 rt73usb_register_multiwrite(rt2x00dev, MAC_CSR2,
362 conf->mac, sizeof(conf->mac));
363 }
364
365 if (flags & CONFIG_UPDATE_BSSID) {
366 reg = le32_to_cpu(conf->bssid[1]);
367 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
368 conf->bssid[1] = cpu_to_le32(reg);
369
370 rt73usb_register_multiwrite(rt2x00dev, MAC_CSR4,
371 conf->bssid, sizeof(conf->bssid));
372 }
373 }
374
375 static int rt73usb_config_preamble(struct rt2x00_dev *rt2x00dev,
376 const int short_preamble,
377 const int ack_timeout,
378 const int ack_consume_time)
379 {
380 u32 reg;
381
382 /*
383 * When in atomic context, we should let rt2x00lib
384 * try this configuration again later.
385 */
386 if (in_atomic())
387 return -EAGAIN;
388
389 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
390 rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, ack_timeout);
391 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
392
393 rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
394 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
395 !!short_preamble);
396 rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
397
398 return 0;
399 }
400
401 static void rt73usb_config_phymode(struct rt2x00_dev *rt2x00dev,
402 const int basic_rate_mask)
403 {
404 rt73usb_register_write(rt2x00dev, TXRX_CSR5, basic_rate_mask);
405 }
406
407 static void rt73usb_config_channel(struct rt2x00_dev *rt2x00dev,
408 struct rf_channel *rf, const int txpower)
409 {
410 u8 r3;
411 u8 r94;
412 u8 smart;
413
414 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
415 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
416
417 smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
418 rt2x00_rf(&rt2x00dev->chip, RF2527));
419
420 rt73usb_bbp_read(rt2x00dev, 3, &r3);
421 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
422 rt73usb_bbp_write(rt2x00dev, 3, r3);
423
424 r94 = 6;
425 if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
426 r94 += txpower - MAX_TXPOWER;
427 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
428 r94 += txpower;
429 rt73usb_bbp_write(rt2x00dev, 94, r94);
430
431 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
432 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
433 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
434 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
435
436 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
437 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
438 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
439 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
440
441 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
442 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
443 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
444 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
445
446 udelay(10);
447 }
448
449 static void rt73usb_config_txpower(struct rt2x00_dev *rt2x00dev,
450 const int txpower)
451 {
452 struct rf_channel rf;
453
454 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
455 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
456 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
457 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
458
459 rt73usb_config_channel(rt2x00dev, &rf, txpower);
460 }
461
462 static void rt73usb_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
463 struct antenna_setup *ant)
464 {
465 u8 r3;
466 u8 r4;
467 u8 r77;
468 u8 temp;
469
470 rt73usb_bbp_read(rt2x00dev, 3, &r3);
471 rt73usb_bbp_read(rt2x00dev, 4, &r4);
472 rt73usb_bbp_read(rt2x00dev, 77, &r77);
473
474 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
475
476 /*
477 * Configure the RX antenna.
478 */
479 switch (ant->rx) {
480 case ANTENNA_HW_DIVERSITY:
481 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
482 temp = !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags)
483 && (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ);
484 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, temp);
485 break;
486 case ANTENNA_A:
487 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
488 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
489 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
490 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
491 else
492 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
493 break;
494 case ANTENNA_SW_DIVERSITY:
495 /*
496 * NOTE: We should never come here because rt2x00lib is
497 * supposed to catch this and send us the correct antenna
498 * explicitely. However we are nog going to bug about this.
499 * Instead, just default to antenna B.
500 */
501 case ANTENNA_B:
502 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
503 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
504 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
505 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
506 else
507 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
508 break;
509 }
510
511 rt73usb_bbp_write(rt2x00dev, 77, r77);
512 rt73usb_bbp_write(rt2x00dev, 3, r3);
513 rt73usb_bbp_write(rt2x00dev, 4, r4);
514 }
515
516 static void rt73usb_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
517 struct antenna_setup *ant)
518 {
519 u8 r3;
520 u8 r4;
521 u8 r77;
522
523 rt73usb_bbp_read(rt2x00dev, 3, &r3);
524 rt73usb_bbp_read(rt2x00dev, 4, &r4);
525 rt73usb_bbp_read(rt2x00dev, 77, &r77);
526
527 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
528 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
529 !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
530
531 /*
532 * Configure the RX antenna.
533 */
534 switch (ant->rx) {
535 case ANTENNA_HW_DIVERSITY:
536 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
537 break;
538 case ANTENNA_A:
539 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
540 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
541 break;
542 case ANTENNA_SW_DIVERSITY:
543 /*
544 * NOTE: We should never come here because rt2x00lib is
545 * supposed to catch this and send us the correct antenna
546 * explicitely. However we are nog going to bug about this.
547 * Instead, just default to antenna B.
548 */
549 case ANTENNA_B:
550 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
551 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
552 break;
553 }
554
555 rt73usb_bbp_write(rt2x00dev, 77, r77);
556 rt73usb_bbp_write(rt2x00dev, 3, r3);
557 rt73usb_bbp_write(rt2x00dev, 4, r4);
558 }
559
560 struct antenna_sel {
561 u8 word;
562 /*
563 * value[0] -> non-LNA
564 * value[1] -> LNA
565 */
566 u8 value[2];
567 };
568
569 static const struct antenna_sel antenna_sel_a[] = {
570 { 96, { 0x58, 0x78 } },
571 { 104, { 0x38, 0x48 } },
572 { 75, { 0xfe, 0x80 } },
573 { 86, { 0xfe, 0x80 } },
574 { 88, { 0xfe, 0x80 } },
575 { 35, { 0x60, 0x60 } },
576 { 97, { 0x58, 0x58 } },
577 { 98, { 0x58, 0x58 } },
578 };
579
580 static const struct antenna_sel antenna_sel_bg[] = {
581 { 96, { 0x48, 0x68 } },
582 { 104, { 0x2c, 0x3c } },
583 { 75, { 0xfe, 0x80 } },
584 { 86, { 0xfe, 0x80 } },
585 { 88, { 0xfe, 0x80 } },
586 { 35, { 0x50, 0x50 } },
587 { 97, { 0x48, 0x48 } },
588 { 98, { 0x48, 0x48 } },
589 };
590
591 static void rt73usb_config_antenna(struct rt2x00_dev *rt2x00dev,
592 struct antenna_setup *ant)
593 {
594 const struct antenna_sel *sel;
595 unsigned int lna;
596 unsigned int i;
597 u32 reg;
598
599 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
600 sel = antenna_sel_a;
601 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
602 } else {
603 sel = antenna_sel_bg;
604 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
605 }
606
607 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
608 rt73usb_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
609
610 rt73usb_register_read(rt2x00dev, PHY_CSR0, &reg);
611
612 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
613 (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ));
614 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
615 (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ));
616
617 rt73usb_register_write(rt2x00dev, PHY_CSR0, reg);
618
619 if (rt2x00_rf(&rt2x00dev->chip, RF5226) ||
620 rt2x00_rf(&rt2x00dev->chip, RF5225))
621 rt73usb_config_antenna_5x(rt2x00dev, ant);
622 else if (rt2x00_rf(&rt2x00dev->chip, RF2528) ||
623 rt2x00_rf(&rt2x00dev->chip, RF2527))
624 rt73usb_config_antenna_2x(rt2x00dev, ant);
625 }
626
627 static void rt73usb_config_duration(struct rt2x00_dev *rt2x00dev,
628 struct rt2x00lib_conf *libconf)
629 {
630 u32 reg;
631
632 rt73usb_register_read(rt2x00dev, MAC_CSR9, &reg);
633 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, libconf->slot_time);
634 rt73usb_register_write(rt2x00dev, MAC_CSR9, reg);
635
636 rt73usb_register_read(rt2x00dev, MAC_CSR8, &reg);
637 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, libconf->sifs);
638 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
639 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, libconf->eifs);
640 rt73usb_register_write(rt2x00dev, MAC_CSR8, reg);
641
642 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
643 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
644 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
645
646 rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
647 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
648 rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
649
650 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
651 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
652 libconf->conf->beacon_int * 16);
653 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
654 }
655
656 static void rt73usb_config(struct rt2x00_dev *rt2x00dev,
657 struct rt2x00lib_conf *libconf,
658 const unsigned int flags)
659 {
660 if (flags & CONFIG_UPDATE_PHYMODE)
661 rt73usb_config_phymode(rt2x00dev, libconf->basic_rates);
662 if (flags & CONFIG_UPDATE_CHANNEL)
663 rt73usb_config_channel(rt2x00dev, &libconf->rf,
664 libconf->conf->power_level);
665 if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
666 rt73usb_config_txpower(rt2x00dev, libconf->conf->power_level);
667 if (flags & CONFIG_UPDATE_ANTENNA)
668 rt73usb_config_antenna(rt2x00dev, &libconf->ant);
669 if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
670 rt73usb_config_duration(rt2x00dev, libconf);
671 }
672
673 /*
674 * Link tuning
675 */
676 static void rt73usb_link_stats(struct rt2x00_dev *rt2x00dev,
677 struct link_qual *qual)
678 {
679 u32 reg;
680
681 /*
682 * Update FCS error count from register.
683 */
684 rt73usb_register_read(rt2x00dev, STA_CSR0, &reg);
685 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
686
687 /*
688 * Update False CCA count from register.
689 */
690 rt73usb_register_read(rt2x00dev, STA_CSR1, &reg);
691 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
692 }
693
694 static void rt73usb_reset_tuner(struct rt2x00_dev *rt2x00dev)
695 {
696 rt73usb_bbp_write(rt2x00dev, 17, 0x20);
697 rt2x00dev->link.vgc_level = 0x20;
698 }
699
700 static void rt73usb_link_tuner(struct rt2x00_dev *rt2x00dev)
701 {
702 int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
703 u8 r17;
704 u8 up_bound;
705 u8 low_bound;
706
707 rt73usb_bbp_read(rt2x00dev, 17, &r17);
708
709 /*
710 * Determine r17 bounds.
711 */
712 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
713 low_bound = 0x28;
714 up_bound = 0x48;
715
716 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
717 low_bound += 0x10;
718 up_bound += 0x10;
719 }
720 } else {
721 if (rssi > -82) {
722 low_bound = 0x1c;
723 up_bound = 0x40;
724 } else if (rssi > -84) {
725 low_bound = 0x1c;
726 up_bound = 0x20;
727 } else {
728 low_bound = 0x1c;
729 up_bound = 0x1c;
730 }
731
732 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
733 low_bound += 0x14;
734 up_bound += 0x10;
735 }
736 }
737
738 /*
739 * If we are not associated, we should go straight to the
740 * dynamic CCA tuning.
741 */
742 if (!rt2x00dev->intf_associated)
743 goto dynamic_cca_tune;
744
745 /*
746 * Special big-R17 for very short distance
747 */
748 if (rssi > -35) {
749 if (r17 != 0x60)
750 rt73usb_bbp_write(rt2x00dev, 17, 0x60);
751 return;
752 }
753
754 /*
755 * Special big-R17 for short distance
756 */
757 if (rssi >= -58) {
758 if (r17 != up_bound)
759 rt73usb_bbp_write(rt2x00dev, 17, up_bound);
760 return;
761 }
762
763 /*
764 * Special big-R17 for middle-short distance
765 */
766 if (rssi >= -66) {
767 low_bound += 0x10;
768 if (r17 != low_bound)
769 rt73usb_bbp_write(rt2x00dev, 17, low_bound);
770 return;
771 }
772
773 /*
774 * Special mid-R17 for middle distance
775 */
776 if (rssi >= -74) {
777 if (r17 != (low_bound + 0x10))
778 rt73usb_bbp_write(rt2x00dev, 17, low_bound + 0x08);
779 return;
780 }
781
782 /*
783 * Special case: Change up_bound based on the rssi.
784 * Lower up_bound when rssi is weaker then -74 dBm.
785 */
786 up_bound -= 2 * (-74 - rssi);
787 if (low_bound > up_bound)
788 up_bound = low_bound;
789
790 if (r17 > up_bound) {
791 rt73usb_bbp_write(rt2x00dev, 17, up_bound);
792 return;
793 }
794
795 dynamic_cca_tune:
796
797 /*
798 * r17 does not yet exceed upper limit, continue and base
799 * the r17 tuning on the false CCA count.
800 */
801 if (rt2x00dev->link.qual.false_cca > 512 && r17 < up_bound) {
802 r17 += 4;
803 if (r17 > up_bound)
804 r17 = up_bound;
805 rt73usb_bbp_write(rt2x00dev, 17, r17);
806 } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > low_bound) {
807 r17 -= 4;
808 if (r17 < low_bound)
809 r17 = low_bound;
810 rt73usb_bbp_write(rt2x00dev, 17, r17);
811 }
812 }
813
814 /*
815 * Firmware name function.
816 */
817 static char *rt73usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
818 {
819 return FIRMWARE_RT2571;
820 }
821
822 /*
823 * Initialization functions.
824 */
825 static int rt73usb_load_firmware(struct rt2x00_dev *rt2x00dev, void *data,
826 const size_t len)
827 {
828 unsigned int i;
829 int status;
830 u32 reg;
831 char *ptr = data;
832 char *cache;
833 int buflen;
834 int timeout;
835
836 /*
837 * Wait for stable hardware.
838 */
839 for (i = 0; i < 100; i++) {
840 rt73usb_register_read(rt2x00dev, MAC_CSR0, &reg);
841 if (reg)
842 break;
843 msleep(1);
844 }
845
846 if (!reg) {
847 ERROR(rt2x00dev, "Unstable hardware.\n");
848 return -EBUSY;
849 }
850
851 /*
852 * Write firmware to device.
853 * We setup a seperate cache for this action,
854 * since we are going to write larger chunks of data
855 * then normally used cache size.
856 */
857 cache = kmalloc(CSR_CACHE_SIZE_FIRMWARE, GFP_KERNEL);
858 if (!cache) {
859 ERROR(rt2x00dev, "Failed to allocate firmware cache.\n");
860 return -ENOMEM;
861 }
862
863 for (i = 0; i < len; i += CSR_CACHE_SIZE_FIRMWARE) {
864 buflen = min_t(int, len - i, CSR_CACHE_SIZE_FIRMWARE);
865 timeout = REGISTER_TIMEOUT * (buflen / sizeof(u32));
866
867 memcpy(cache, ptr, buflen);
868
869 rt2x00usb_vendor_request(rt2x00dev, USB_MULTI_WRITE,
870 USB_VENDOR_REQUEST_OUT,
871 FIRMWARE_IMAGE_BASE + i, 0,
872 cache, buflen, timeout);
873
874 ptr += buflen;
875 }
876
877 kfree(cache);
878
879 /*
880 * Send firmware request to device to load firmware,
881 * we need to specify a long timeout time.
882 */
883 status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE,
884 0, USB_MODE_FIRMWARE,
885 REGISTER_TIMEOUT_FIRMWARE);
886 if (status < 0) {
887 ERROR(rt2x00dev, "Failed to write Firmware to device.\n");
888 return status;
889 }
890
891 return 0;
892 }
893
894 static int rt73usb_init_registers(struct rt2x00_dev *rt2x00dev)
895 {
896 u32 reg;
897
898 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
899 rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
900 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
901 rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
902 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
903
904 rt73usb_register_read(rt2x00dev, TXRX_CSR1, &reg);
905 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
906 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
907 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
908 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
909 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
910 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
911 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
912 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
913 rt73usb_register_write(rt2x00dev, TXRX_CSR1, reg);
914
915 /*
916 * CCK TXD BBP registers
917 */
918 rt73usb_register_read(rt2x00dev, TXRX_CSR2, &reg);
919 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
920 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
921 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
922 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
923 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
924 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
925 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
926 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
927 rt73usb_register_write(rt2x00dev, TXRX_CSR2, reg);
928
929 /*
930 * OFDM TXD BBP registers
931 */
932 rt73usb_register_read(rt2x00dev, TXRX_CSR3, &reg);
933 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
934 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
935 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
936 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
937 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
938 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
939 rt73usb_register_write(rt2x00dev, TXRX_CSR3, reg);
940
941 rt73usb_register_read(rt2x00dev, TXRX_CSR7, &reg);
942 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
943 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
944 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
945 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
946 rt73usb_register_write(rt2x00dev, TXRX_CSR7, reg);
947
948 rt73usb_register_read(rt2x00dev, TXRX_CSR8, &reg);
949 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
950 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
951 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
952 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
953 rt73usb_register_write(rt2x00dev, TXRX_CSR8, reg);
954
955 rt73usb_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
956
957 rt73usb_register_read(rt2x00dev, MAC_CSR6, &reg);
958 rt2x00_set_field32(&reg, MAC_CSR6_MAX_FRAME_UNIT, 0xfff);
959 rt73usb_register_write(rt2x00dev, MAC_CSR6, reg);
960
961 rt73usb_register_write(rt2x00dev, MAC_CSR10, 0x00000718);
962
963 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
964 return -EBUSY;
965
966 rt73usb_register_write(rt2x00dev, MAC_CSR13, 0x00007f00);
967
968 rt73usb_register_read(rt2x00dev, MAC_CSR14, &reg);
969 rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, 70);
970 rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, 30);
971 rt73usb_register_write(rt2x00dev, MAC_CSR14, reg);
972
973 /*
974 * Invalidate all Shared Keys (SEC_CSR0),
975 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
976 */
977 rt73usb_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
978 rt73usb_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
979 rt73usb_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
980
981 reg = 0x000023b0;
982 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
983 rt2x00_rf(&rt2x00dev->chip, RF2527))
984 rt2x00_set_field32(&reg, PHY_CSR1_RF_RPI, 1);
985 rt73usb_register_write(rt2x00dev, PHY_CSR1, reg);
986
987 rt73usb_register_write(rt2x00dev, PHY_CSR5, 0x00040a06);
988 rt73usb_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
989 rt73usb_register_write(rt2x00dev, PHY_CSR7, 0x00000408);
990
991 rt73usb_register_read(rt2x00dev, AC_TXOP_CSR0, &reg);
992 rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC0_TX_OP, 0);
993 rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC1_TX_OP, 0);
994 rt73usb_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
995
996 rt73usb_register_read(rt2x00dev, AC_TXOP_CSR1, &reg);
997 rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC2_TX_OP, 192);
998 rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC3_TX_OP, 48);
999 rt73usb_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
1000
1001 rt73usb_register_read(rt2x00dev, MAC_CSR9, &reg);
1002 rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1003 rt73usb_register_write(rt2x00dev, MAC_CSR9, reg);
1004
1005 /*
1006 * Clear all beacons
1007 * For the Beacon base registers we only need to clear
1008 * the first byte since that byte contains the VALID and OWNER
1009 * bits which (when set to 0) will invalidate the entire beacon.
1010 */
1011 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1012 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1013 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1014 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1015
1016 /*
1017 * We must clear the error counters.
1018 * These registers are cleared on read,
1019 * so we may pass a useless variable to store the value.
1020 */
1021 rt73usb_register_read(rt2x00dev, STA_CSR0, &reg);
1022 rt73usb_register_read(rt2x00dev, STA_CSR1, &reg);
1023 rt73usb_register_read(rt2x00dev, STA_CSR2, &reg);
1024
1025 /*
1026 * Reset MAC and BBP registers.
1027 */
1028 rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1029 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1030 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1031 rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1032
1033 rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1034 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1035 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1036 rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1037
1038 rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1039 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1040 rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1041
1042 return 0;
1043 }
1044
1045 static int rt73usb_init_bbp(struct rt2x00_dev *rt2x00dev)
1046 {
1047 unsigned int i;
1048 u16 eeprom;
1049 u8 reg_id;
1050 u8 value;
1051
1052 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1053 rt73usb_bbp_read(rt2x00dev, 0, &value);
1054 if ((value != 0xff) && (value != 0x00))
1055 goto continue_csr_init;
1056 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
1057 udelay(REGISTER_BUSY_DELAY);
1058 }
1059
1060 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1061 return -EACCES;
1062
1063 continue_csr_init:
1064 rt73usb_bbp_write(rt2x00dev, 3, 0x80);
1065 rt73usb_bbp_write(rt2x00dev, 15, 0x30);
1066 rt73usb_bbp_write(rt2x00dev, 21, 0xc8);
1067 rt73usb_bbp_write(rt2x00dev, 22, 0x38);
1068 rt73usb_bbp_write(rt2x00dev, 23, 0x06);
1069 rt73usb_bbp_write(rt2x00dev, 24, 0xfe);
1070 rt73usb_bbp_write(rt2x00dev, 25, 0x0a);
1071 rt73usb_bbp_write(rt2x00dev, 26, 0x0d);
1072 rt73usb_bbp_write(rt2x00dev, 32, 0x0b);
1073 rt73usb_bbp_write(rt2x00dev, 34, 0x12);
1074 rt73usb_bbp_write(rt2x00dev, 37, 0x07);
1075 rt73usb_bbp_write(rt2x00dev, 39, 0xf8);
1076 rt73usb_bbp_write(rt2x00dev, 41, 0x60);
1077 rt73usb_bbp_write(rt2x00dev, 53, 0x10);
1078 rt73usb_bbp_write(rt2x00dev, 54, 0x18);
1079 rt73usb_bbp_write(rt2x00dev, 60, 0x10);
1080 rt73usb_bbp_write(rt2x00dev, 61, 0x04);
1081 rt73usb_bbp_write(rt2x00dev, 62, 0x04);
1082 rt73usb_bbp_write(rt2x00dev, 75, 0xfe);
1083 rt73usb_bbp_write(rt2x00dev, 86, 0xfe);
1084 rt73usb_bbp_write(rt2x00dev, 88, 0xfe);
1085 rt73usb_bbp_write(rt2x00dev, 90, 0x0f);
1086 rt73usb_bbp_write(rt2x00dev, 99, 0x00);
1087 rt73usb_bbp_write(rt2x00dev, 102, 0x16);
1088 rt73usb_bbp_write(rt2x00dev, 107, 0x04);
1089
1090 DEBUG(rt2x00dev, "Start initialization from EEPROM...\n");
1091 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1092 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1093
1094 if (eeprom != 0xffff && eeprom != 0x0000) {
1095 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1096 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1097 DEBUG(rt2x00dev, "BBP: 0x%02x, value: 0x%02x.\n",
1098 reg_id, value);
1099 rt73usb_bbp_write(rt2x00dev, reg_id, value);
1100 }
1101 }
1102 DEBUG(rt2x00dev, "...End initialization from EEPROM.\n");
1103
1104 return 0;
1105 }
1106
1107 /*
1108 * Device state switch handlers.
1109 */
1110 static void rt73usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
1111 enum dev_state state)
1112 {
1113 u32 reg;
1114
1115 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1116 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
1117 state == STATE_RADIO_RX_OFF);
1118 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1119 }
1120
1121 static int rt73usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1122 {
1123 /*
1124 * Initialize all registers.
1125 */
1126 if (rt73usb_init_registers(rt2x00dev) ||
1127 rt73usb_init_bbp(rt2x00dev)) {
1128 ERROR(rt2x00dev, "Register initialization failed.\n");
1129 return -EIO;
1130 }
1131
1132 return 0;
1133 }
1134
1135 static void rt73usb_disable_radio(struct rt2x00_dev *rt2x00dev)
1136 {
1137 rt73usb_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1138
1139 /*
1140 * Disable synchronisation.
1141 */
1142 rt73usb_register_write(rt2x00dev, TXRX_CSR9, 0);
1143
1144 rt2x00usb_disable_radio(rt2x00dev);
1145 }
1146
1147 static int rt73usb_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1148 {
1149 u32 reg;
1150 unsigned int i;
1151 char put_to_sleep;
1152 char current_state;
1153
1154 put_to_sleep = (state != STATE_AWAKE);
1155
1156 rt73usb_register_read(rt2x00dev, MAC_CSR12, &reg);
1157 rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1158 rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1159 rt73usb_register_write(rt2x00dev, MAC_CSR12, reg);
1160
1161 /*
1162 * Device is not guaranteed to be in the requested state yet.
1163 * We must wait until the register indicates that the
1164 * device has entered the correct state.
1165 */
1166 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1167 rt73usb_register_read(rt2x00dev, MAC_CSR12, &reg);
1168 current_state =
1169 rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1170 if (current_state == !put_to_sleep)
1171 return 0;
1172 msleep(10);
1173 }
1174
1175 NOTICE(rt2x00dev, "Device failed to enter state %d, "
1176 "current device state %d.\n", !put_to_sleep, current_state);
1177
1178 return -EBUSY;
1179 }
1180
1181 static int rt73usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1182 enum dev_state state)
1183 {
1184 int retval = 0;
1185
1186 switch (state) {
1187 case STATE_RADIO_ON:
1188 retval = rt73usb_enable_radio(rt2x00dev);
1189 break;
1190 case STATE_RADIO_OFF:
1191 rt73usb_disable_radio(rt2x00dev);
1192 break;
1193 case STATE_RADIO_RX_ON:
1194 case STATE_RADIO_RX_ON_LINK:
1195 rt73usb_toggle_rx(rt2x00dev, STATE_RADIO_RX_ON);
1196 break;
1197 case STATE_RADIO_RX_OFF:
1198 case STATE_RADIO_RX_OFF_LINK:
1199 rt73usb_toggle_rx(rt2x00dev, STATE_RADIO_RX_OFF);
1200 break;
1201 case STATE_DEEP_SLEEP:
1202 case STATE_SLEEP:
1203 case STATE_STANDBY:
1204 case STATE_AWAKE:
1205 retval = rt73usb_set_state(rt2x00dev, state);
1206 break;
1207 default:
1208 retval = -ENOTSUPP;
1209 break;
1210 }
1211
1212 return retval;
1213 }
1214
1215 /*
1216 * TX descriptor initialization
1217 */
1218 static void rt73usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1219 struct sk_buff *skb,
1220 struct txentry_desc *txdesc,
1221 struct ieee80211_tx_control *control)
1222 {
1223 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1224 __le32 *txd = skbdesc->desc;
1225 u32 word;
1226
1227 /*
1228 * Start writing the descriptor words.
1229 */
1230 rt2x00_desc_read(txd, 1, &word);
1231 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue);
1232 rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
1233 rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
1234 rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
1235 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, IEEE80211_HEADER);
1236 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, 1);
1237 rt2x00_desc_write(txd, 1, word);
1238
1239 rt2x00_desc_read(txd, 2, &word);
1240 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1241 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1242 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1243 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
1244 rt2x00_desc_write(txd, 2, word);
1245
1246 rt2x00_desc_read(txd, 5, &word);
1247 /* XXX: removed for now
1248 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1249 TXPOWER_TO_DEV(control->power_level));
1250 */
1251 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1252 rt2x00_desc_write(txd, 5, word);
1253
1254 rt2x00_desc_read(txd, 0, &word);
1255 rt2x00_set_field32(&word, TXD_W0_BURST,
1256 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1257 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1258 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1259 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1260 rt2x00_set_field32(&word, TXD_W0_ACK,
1261 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1262 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1263 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1264 rt2x00_set_field32(&word, TXD_W0_OFDM,
1265 test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
1266 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1267 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1268 !!(control->flags &
1269 IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1270 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 0);
1271 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skbdesc->data_len);
1272 rt2x00_set_field32(&word, TXD_W0_BURST2,
1273 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1274 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1275 rt2x00_desc_write(txd, 0, word);
1276 }
1277
1278 static int rt73usb_get_tx_data_len(struct rt2x00_dev *rt2x00dev,
1279 struct sk_buff *skb)
1280 {
1281 int length;
1282
1283 /*
1284 * The length _must_ be a multiple of 4,
1285 * but it must _not_ be a multiple of the USB packet size.
1286 */
1287 length = roundup(skb->len, 4);
1288 length += (4 * !(length % rt2x00dev->usb_maxpacket));
1289
1290 return length;
1291 }
1292
1293 /*
1294 * TX data initialization
1295 */
1296 static void rt73usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1297 const unsigned int queue)
1298 {
1299 u32 reg;
1300
1301 if (queue != RT2X00_BCN_QUEUE_BEACON)
1302 return;
1303
1304 /*
1305 * For Wi-Fi faily generated beacons between participating stations.
1306 * Set TBTT phase adaptive adjustment step to 8us (default 16us)
1307 */
1308 rt73usb_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1309
1310 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1311 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
1312 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1313 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1314 }
1315 }
1316
1317 /*
1318 * RX control handlers
1319 */
1320 static int rt73usb_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1321 {
1322 u16 eeprom;
1323 u8 offset;
1324 u8 lna;
1325
1326 lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1327 switch (lna) {
1328 case 3:
1329 offset = 90;
1330 break;
1331 case 2:
1332 offset = 74;
1333 break;
1334 case 1:
1335 offset = 64;
1336 break;
1337 default:
1338 return 0;
1339 }
1340
1341 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
1342 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
1343 if (lna == 3 || lna == 2)
1344 offset += 10;
1345 } else {
1346 if (lna == 3)
1347 offset += 6;
1348 else if (lna == 2)
1349 offset += 8;
1350 }
1351
1352 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
1353 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
1354 } else {
1355 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
1356 offset += 14;
1357
1358 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
1359 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
1360 }
1361
1362 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1363 }
1364
1365 static void rt73usb_fill_rxdone(struct queue_entry *entry,
1366 struct rxdone_entry_desc *rxdesc)
1367 {
1368 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1369 __le32 *rxd = (__le32 *)entry->skb->data;
1370 struct ieee80211_hdr *hdr =
1371 (struct ieee80211_hdr *)entry->skb->data + entry->queue->desc_size;
1372 int header_size = ieee80211_get_hdrlen(le16_to_cpu(hdr->frame_control));
1373 u32 word0;
1374 u32 word1;
1375
1376 rt2x00_desc_read(rxd, 0, &word0);
1377 rt2x00_desc_read(rxd, 1, &word1);
1378
1379 rxdesc->flags = 0;
1380 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1381 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1382
1383 /*
1384 * Obtain the status about this packet.
1385 */
1386 rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
1387 rxdesc->rssi = rt73usb_agc_to_rssi(entry->queue->rt2x00dev, word1);
1388 rxdesc->ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM);
1389 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1390 rxdesc->my_bss = !!rt2x00_get_field32(word0, RXD_W0_MY_BSS);
1391
1392 /*
1393 * The data behind the ieee80211 header must be
1394 * aligned on a 4 byte boundary.
1395 */
1396 if (header_size % 4 == 0) {
1397 skb_push(entry->skb, 2);
1398 memmove(entry->skb->data, entry->skb->data + 2,
1399 entry->skb->len - 2);
1400 }
1401
1402 /*
1403 * Set descriptor and data pointer.
1404 */
1405 skbdesc->data = entry->skb->data + entry->queue->desc_size;
1406 skbdesc->data_len = entry->queue->data_size;
1407 skbdesc->desc = entry->skb->data;
1408 skbdesc->desc_len = entry->queue->desc_size;
1409
1410 /*
1411 * Remove descriptor from skb buffer and trim the whole thing
1412 * down to only contain data.
1413 */
1414 skb_pull(entry->skb, skbdesc->desc_len);
1415 skb_trim(entry->skb, rxdesc->size);
1416 }
1417
1418 /*
1419 * Device probe functions.
1420 */
1421 static int rt73usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1422 {
1423 u16 word;
1424 u8 *mac;
1425 s8 value;
1426
1427 rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
1428
1429 /*
1430 * Start validation of the data that has been read.
1431 */
1432 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1433 if (!is_valid_ether_addr(mac)) {
1434 DECLARE_MAC_BUF(macbuf);
1435
1436 random_ether_addr(mac);
1437 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
1438 }
1439
1440 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1441 if (word == 0xffff) {
1442 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1443 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1444 ANTENNA_B);
1445 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1446 ANTENNA_B);
1447 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1448 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1449 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1450 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5226);
1451 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1452 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1453 }
1454
1455 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1456 if (word == 0xffff) {
1457 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA, 0);
1458 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1459 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1460 }
1461
1462 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
1463 if (word == 0xffff) {
1464 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_G, 0);
1465 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_A, 0);
1466 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_ACT, 0);
1467 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_0, 0);
1468 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_1, 0);
1469 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_2, 0);
1470 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_3, 0);
1471 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_4, 0);
1472 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1473 LED_MODE_DEFAULT);
1474 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
1475 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
1476 }
1477
1478 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1479 if (word == 0xffff) {
1480 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1481 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
1482 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1483 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1484 }
1485
1486 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
1487 if (word == 0xffff) {
1488 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1489 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1490 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1491 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1492 } else {
1493 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
1494 if (value < -10 || value > 10)
1495 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1496 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
1497 if (value < -10 || value > 10)
1498 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1499 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1500 }
1501
1502 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
1503 if (word == 0xffff) {
1504 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1505 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1506 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1507 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1508 } else {
1509 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
1510 if (value < -10 || value > 10)
1511 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1512 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
1513 if (value < -10 || value > 10)
1514 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1515 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1516 }
1517
1518 return 0;
1519 }
1520
1521 static int rt73usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
1522 {
1523 u32 reg;
1524 u16 value;
1525 u16 eeprom;
1526
1527 /*
1528 * Read EEPROM word for configuration.
1529 */
1530 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1531
1532 /*
1533 * Identify RF chipset.
1534 */
1535 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1536 rt73usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1537 rt2x00_set_chip(rt2x00dev, RT2571, value, reg);
1538
1539 if (!rt2x00_check_rev(&rt2x00dev->chip, 0x25730)) {
1540 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
1541 return -ENODEV;
1542 }
1543
1544 if (!rt2x00_rf(&rt2x00dev->chip, RF5226) &&
1545 !rt2x00_rf(&rt2x00dev->chip, RF2528) &&
1546 !rt2x00_rf(&rt2x00dev->chip, RF5225) &&
1547 !rt2x00_rf(&rt2x00dev->chip, RF2527)) {
1548 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1549 return -ENODEV;
1550 }
1551
1552 /*
1553 * Identify default antenna configuration.
1554 */
1555 rt2x00dev->default_ant.tx =
1556 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1557 rt2x00dev->default_ant.rx =
1558 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1559
1560 /*
1561 * Read the Frame type.
1562 */
1563 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
1564 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
1565
1566 /*
1567 * Read frequency offset.
1568 */
1569 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1570 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
1571
1572 /*
1573 * Read external LNA informations.
1574 */
1575 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1576
1577 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA)) {
1578 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
1579 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
1580 }
1581
1582 /*
1583 * Store led settings, for correct led behaviour.
1584 */
1585 #ifdef CONFIG_RT73USB_LEDS
1586 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
1587
1588 switch (value) {
1589 case LED_MODE_TXRX_ACTIVITY:
1590 case LED_MODE_ASUS:
1591 case LED_MODE_ALPHA:
1592 case LED_MODE_DEFAULT:
1593 rt2x00dev->led_flags =
1594 LED_SUPPORT_RADIO | LED_SUPPORT_ASSOC;
1595 break;
1596 case LED_MODE_SIGNAL_STRENGTH:
1597 rt2x00dev->led_flags =
1598 LED_SUPPORT_RADIO | LED_SUPPORT_ASSOC |
1599 LED_SUPPORT_QUALITY;
1600 break;
1601 }
1602
1603 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
1604 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
1605 rt2x00_get_field16(eeprom,
1606 EEPROM_LED_POLARITY_GPIO_0));
1607 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
1608 rt2x00_get_field16(eeprom,
1609 EEPROM_LED_POLARITY_GPIO_1));
1610 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
1611 rt2x00_get_field16(eeprom,
1612 EEPROM_LED_POLARITY_GPIO_2));
1613 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
1614 rt2x00_get_field16(eeprom,
1615 EEPROM_LED_POLARITY_GPIO_3));
1616 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
1617 rt2x00_get_field16(eeprom,
1618 EEPROM_LED_POLARITY_GPIO_4));
1619 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
1620 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
1621 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
1622 rt2x00_get_field16(eeprom,
1623 EEPROM_LED_POLARITY_RDY_G));
1624 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
1625 rt2x00_get_field16(eeprom,
1626 EEPROM_LED_POLARITY_RDY_A));
1627 #endif /* CONFIG_RT73USB_LEDS */
1628
1629 return 0;
1630 }
1631
1632 /*
1633 * RF value list for RF2528
1634 * Supports: 2.4 GHz
1635 */
1636 static const struct rf_channel rf_vals_bg_2528[] = {
1637 { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1638 { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1639 { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1640 { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1641 { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1642 { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1643 { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1644 { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1645 { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1646 { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1647 { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1648 { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1649 { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1650 { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1651 };
1652
1653 /*
1654 * RF value list for RF5226
1655 * Supports: 2.4 GHz & 5.2 GHz
1656 */
1657 static const struct rf_channel rf_vals_5226[] = {
1658 { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1659 { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1660 { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1661 { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1662 { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1663 { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1664 { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1665 { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1666 { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1667 { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1668 { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1669 { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1670 { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1671 { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1672
1673 /* 802.11 UNI / HyperLan 2 */
1674 { 36, 0x00002c0c, 0x0000099a, 0x00098255, 0x000fea23 },
1675 { 40, 0x00002c0c, 0x000009a2, 0x00098255, 0x000fea03 },
1676 { 44, 0x00002c0c, 0x000009a6, 0x00098255, 0x000fea0b },
1677 { 48, 0x00002c0c, 0x000009aa, 0x00098255, 0x000fea13 },
1678 { 52, 0x00002c0c, 0x000009ae, 0x00098255, 0x000fea1b },
1679 { 56, 0x00002c0c, 0x000009b2, 0x00098255, 0x000fea23 },
1680 { 60, 0x00002c0c, 0x000009ba, 0x00098255, 0x000fea03 },
1681 { 64, 0x00002c0c, 0x000009be, 0x00098255, 0x000fea0b },
1682
1683 /* 802.11 HyperLan 2 */
1684 { 100, 0x00002c0c, 0x00000a2a, 0x000b8255, 0x000fea03 },
1685 { 104, 0x00002c0c, 0x00000a2e, 0x000b8255, 0x000fea0b },
1686 { 108, 0x00002c0c, 0x00000a32, 0x000b8255, 0x000fea13 },
1687 { 112, 0x00002c0c, 0x00000a36, 0x000b8255, 0x000fea1b },
1688 { 116, 0x00002c0c, 0x00000a3a, 0x000b8255, 0x000fea23 },
1689 { 120, 0x00002c0c, 0x00000a82, 0x000b8255, 0x000fea03 },
1690 { 124, 0x00002c0c, 0x00000a86, 0x000b8255, 0x000fea0b },
1691 { 128, 0x00002c0c, 0x00000a8a, 0x000b8255, 0x000fea13 },
1692 { 132, 0x00002c0c, 0x00000a8e, 0x000b8255, 0x000fea1b },
1693 { 136, 0x00002c0c, 0x00000a92, 0x000b8255, 0x000fea23 },
1694
1695 /* 802.11 UNII */
1696 { 140, 0x00002c0c, 0x00000a9a, 0x000b8255, 0x000fea03 },
1697 { 149, 0x00002c0c, 0x00000aa2, 0x000b8255, 0x000fea1f },
1698 { 153, 0x00002c0c, 0x00000aa6, 0x000b8255, 0x000fea27 },
1699 { 157, 0x00002c0c, 0x00000aae, 0x000b8255, 0x000fea07 },
1700 { 161, 0x00002c0c, 0x00000ab2, 0x000b8255, 0x000fea0f },
1701 { 165, 0x00002c0c, 0x00000ab6, 0x000b8255, 0x000fea17 },
1702
1703 /* MMAC(Japan)J52 ch 34,38,42,46 */
1704 { 34, 0x00002c0c, 0x0008099a, 0x000da255, 0x000d3a0b },
1705 { 38, 0x00002c0c, 0x0008099e, 0x000da255, 0x000d3a13 },
1706 { 42, 0x00002c0c, 0x000809a2, 0x000da255, 0x000d3a1b },
1707 { 46, 0x00002c0c, 0x000809a6, 0x000da255, 0x000d3a23 },
1708 };
1709
1710 /*
1711 * RF value list for RF5225 & RF2527
1712 * Supports: 2.4 GHz & 5.2 GHz
1713 */
1714 static const struct rf_channel rf_vals_5225_2527[] = {
1715 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
1716 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
1717 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
1718 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
1719 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
1720 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
1721 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
1722 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
1723 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
1724 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
1725 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
1726 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
1727 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
1728 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
1729
1730 /* 802.11 UNI / HyperLan 2 */
1731 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
1732 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
1733 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
1734 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
1735 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
1736 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
1737 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
1738 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
1739
1740 /* 802.11 HyperLan 2 */
1741 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
1742 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
1743 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
1744 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
1745 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
1746 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
1747 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
1748 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
1749 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
1750 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
1751
1752 /* 802.11 UNII */
1753 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
1754 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
1755 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
1756 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
1757 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
1758 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
1759
1760 /* MMAC(Japan)J52 ch 34,38,42,46 */
1761 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
1762 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
1763 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
1764 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
1765 };
1766
1767
1768 static void rt73usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1769 {
1770 struct hw_mode_spec *spec = &rt2x00dev->spec;
1771 u8 *txpower;
1772 unsigned int i;
1773
1774 /*
1775 * Initialize all hw fields.
1776 */
1777 rt2x00dev->hw->flags =
1778 IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
1779 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
1780 rt2x00dev->hw->extra_tx_headroom = TXD_DESC_SIZE;
1781 rt2x00dev->hw->max_signal = MAX_SIGNAL;
1782 rt2x00dev->hw->max_rssi = MAX_RX_SSI;
1783 rt2x00dev->hw->queues = 4;
1784
1785 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_usb(rt2x00dev)->dev);
1786 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1787 rt2x00_eeprom_addr(rt2x00dev,
1788 EEPROM_MAC_ADDR_0));
1789
1790 /*
1791 * Convert tx_power array in eeprom.
1792 */
1793 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
1794 for (i = 0; i < 14; i++)
1795 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1796
1797 /*
1798 * Initialize hw_mode information.
1799 */
1800 spec->num_modes = 2;
1801 spec->num_rates = 12;
1802 spec->tx_power_a = NULL;
1803 spec->tx_power_bg = txpower;
1804 spec->tx_power_default = DEFAULT_TXPOWER;
1805
1806 if (rt2x00_rf(&rt2x00dev->chip, RF2528)) {
1807 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2528);
1808 spec->channels = rf_vals_bg_2528;
1809 } else if (rt2x00_rf(&rt2x00dev->chip, RF5226)) {
1810 spec->num_channels = ARRAY_SIZE(rf_vals_5226);
1811 spec->channels = rf_vals_5226;
1812 } else if (rt2x00_rf(&rt2x00dev->chip, RF2527)) {
1813 spec->num_channels = 14;
1814 spec->channels = rf_vals_5225_2527;
1815 } else if (rt2x00_rf(&rt2x00dev->chip, RF5225)) {
1816 spec->num_channels = ARRAY_SIZE(rf_vals_5225_2527);
1817 spec->channels = rf_vals_5225_2527;
1818 }
1819
1820 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
1821 rt2x00_rf(&rt2x00dev->chip, RF5226)) {
1822 spec->num_modes = 3;
1823
1824 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
1825 for (i = 0; i < 14; i++)
1826 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1827
1828 spec->tx_power_a = txpower;
1829 }
1830 }
1831
1832 static int rt73usb_probe_hw(struct rt2x00_dev *rt2x00dev)
1833 {
1834 int retval;
1835
1836 /*
1837 * Allocate eeprom data.
1838 */
1839 retval = rt73usb_validate_eeprom(rt2x00dev);
1840 if (retval)
1841 return retval;
1842
1843 retval = rt73usb_init_eeprom(rt2x00dev);
1844 if (retval)
1845 return retval;
1846
1847 /*
1848 * Initialize hw specifications.
1849 */
1850 rt73usb_probe_hw_mode(rt2x00dev);
1851
1852 /*
1853 * This device requires firmware.
1854 */
1855 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
1856 __set_bit(DRIVER_REQUIRE_FIRMWARE_CRC_ITU_T, &rt2x00dev->flags);
1857
1858 /*
1859 * Set the rssi offset.
1860 */
1861 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1862
1863 return 0;
1864 }
1865
1866 /*
1867 * IEEE80211 stack callback functions.
1868 */
1869 static void rt73usb_configure_filter(struct ieee80211_hw *hw,
1870 unsigned int changed_flags,
1871 unsigned int *total_flags,
1872 int mc_count,
1873 struct dev_addr_list *mc_list)
1874 {
1875 struct rt2x00_dev *rt2x00dev = hw->priv;
1876 u32 reg;
1877
1878 /*
1879 * Mask off any flags we are going to ignore from
1880 * the total_flags field.
1881 */
1882 *total_flags &=
1883 FIF_ALLMULTI |
1884 FIF_FCSFAIL |
1885 FIF_PLCPFAIL |
1886 FIF_CONTROL |
1887 FIF_OTHER_BSS |
1888 FIF_PROMISC_IN_BSS;
1889
1890 /*
1891 * Apply some rules to the filters:
1892 * - Some filters imply different filters to be set.
1893 * - Some things we can't filter out at all.
1894 */
1895 if (mc_count)
1896 *total_flags |= FIF_ALLMULTI;
1897 if (*total_flags & FIF_OTHER_BSS ||
1898 *total_flags & FIF_PROMISC_IN_BSS)
1899 *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
1900
1901 /*
1902 * Check if there is any work left for us.
1903 */
1904 if (rt2x00dev->packet_filter == *total_flags)
1905 return;
1906 rt2x00dev->packet_filter = *total_flags;
1907
1908 /*
1909 * When in atomic context, reschedule and let rt2x00lib
1910 * call this function again.
1911 */
1912 if (in_atomic()) {
1913 queue_work(rt2x00dev->hw->workqueue, &rt2x00dev->filter_work);
1914 return;
1915 }
1916
1917 /*
1918 * Start configuration steps.
1919 * Note that the version error will always be dropped
1920 * and broadcast frames will always be accepted since
1921 * there is no filter for it at this time.
1922 */
1923 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1924 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
1925 !(*total_flags & FIF_FCSFAIL));
1926 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
1927 !(*total_flags & FIF_PLCPFAIL));
1928 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
1929 !(*total_flags & FIF_CONTROL));
1930 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
1931 !(*total_flags & FIF_PROMISC_IN_BSS));
1932 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
1933 !(*total_flags & FIF_PROMISC_IN_BSS));
1934 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
1935 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
1936 !(*total_flags & FIF_ALLMULTI));
1937 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
1938 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS, 1);
1939 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1940 }
1941
1942 static int rt73usb_set_retry_limit(struct ieee80211_hw *hw,
1943 u32 short_retry, u32 long_retry)
1944 {
1945 struct rt2x00_dev *rt2x00dev = hw->priv;
1946 u32 reg;
1947
1948 rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
1949 rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT, long_retry);
1950 rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT, short_retry);
1951 rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
1952
1953 return 0;
1954 }
1955
1956 #if 0
1957 /*
1958 * Mac80211 demands get_tsf must be atomic.
1959 * This is not possible for rt73usb since all register access
1960 * functions require sleeping. Untill mac80211 no longer needs
1961 * get_tsf to be atomic, this function should be disabled.
1962 */
1963 static u64 rt73usb_get_tsf(struct ieee80211_hw *hw)
1964 {
1965 struct rt2x00_dev *rt2x00dev = hw->priv;
1966 u64 tsf;
1967 u32 reg;
1968
1969 rt73usb_register_read(rt2x00dev, TXRX_CSR13, &reg);
1970 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
1971 rt73usb_register_read(rt2x00dev, TXRX_CSR12, &reg);
1972 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
1973
1974 return tsf;
1975 }
1976 #else
1977 #define rt73usb_get_tsf NULL
1978 #endif
1979
1980 static void rt73usb_reset_tsf(struct ieee80211_hw *hw)
1981 {
1982 struct rt2x00_dev *rt2x00dev = hw->priv;
1983
1984 rt73usb_register_write(rt2x00dev, TXRX_CSR12, 0);
1985 rt73usb_register_write(rt2x00dev, TXRX_CSR13, 0);
1986 }
1987
1988 static int rt73usb_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
1989 struct ieee80211_tx_control *control)
1990 {
1991 struct rt2x00_dev *rt2x00dev = hw->priv;
1992 struct rt2x00_intf *intf = vif_to_intf(control->vif);
1993 struct skb_frame_desc *skbdesc;
1994 unsigned int beacon_base;
1995 unsigned int timeout;
1996
1997 if (unlikely(!intf->beacon))
1998 return -ENOBUFS;
1999
2000 /*
2001 * Add the descriptor in front of the skb.
2002 */
2003 skb_push(skb, intf->beacon->queue->desc_size);
2004 memset(skb->data, 0, intf->beacon->queue->desc_size);
2005
2006 /*
2007 * Fill in skb descriptor
2008 */
2009 skbdesc = get_skb_frame_desc(skb);
2010 memset(skbdesc, 0, sizeof(*skbdesc));
2011 skbdesc->data = skb->data + intf->beacon->queue->desc_size;
2012 skbdesc->data_len = skb->len - intf->beacon->queue->desc_size;
2013 skbdesc->desc = skb->data;
2014 skbdesc->desc_len = intf->beacon->queue->desc_size;
2015 skbdesc->entry = intf->beacon;
2016
2017 /*
2018 * mac80211 doesn't provide the control->queue variable
2019 * for beacons. Set our own queue identification so
2020 * it can be used during descriptor initialization.
2021 */
2022 control->queue = RT2X00_BCN_QUEUE_BEACON;
2023 rt2x00lib_write_tx_desc(rt2x00dev, skb, control);
2024
2025 /*
2026 * Write entire beacon with descriptor to register,
2027 * and kick the beacon generator.
2028 */
2029 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
2030 timeout = REGISTER_TIMEOUT * (skb->len / sizeof(u32));
2031 rt2x00usb_vendor_request(rt2x00dev, USB_MULTI_WRITE,
2032 USB_VENDOR_REQUEST_OUT, beacon_base, 0,
2033 skb->data, skb->len, timeout);
2034 rt73usb_kick_tx_queue(rt2x00dev, control->queue);
2035
2036 return 0;
2037 }
2038
2039 static const struct ieee80211_ops rt73usb_mac80211_ops = {
2040 .tx = rt2x00mac_tx,
2041 .start = rt2x00mac_start,
2042 .stop = rt2x00mac_stop,
2043 .add_interface = rt2x00mac_add_interface,
2044 .remove_interface = rt2x00mac_remove_interface,
2045 .config = rt2x00mac_config,
2046 .config_interface = rt2x00mac_config_interface,
2047 .configure_filter = rt73usb_configure_filter,
2048 .get_stats = rt2x00mac_get_stats,
2049 .set_retry_limit = rt73usb_set_retry_limit,
2050 .bss_info_changed = rt2x00mac_bss_info_changed,
2051 .conf_tx = rt2x00mac_conf_tx,
2052 .get_tx_stats = rt2x00mac_get_tx_stats,
2053 .get_tsf = rt73usb_get_tsf,
2054 .reset_tsf = rt73usb_reset_tsf,
2055 .beacon_update = rt73usb_beacon_update,
2056 };
2057
2058 static const struct rt2x00lib_ops rt73usb_rt2x00_ops = {
2059 .probe_hw = rt73usb_probe_hw,
2060 .get_firmware_name = rt73usb_get_firmware_name,
2061 .load_firmware = rt73usb_load_firmware,
2062 .initialize = rt2x00usb_initialize,
2063 .uninitialize = rt2x00usb_uninitialize,
2064 .init_rxentry = rt2x00usb_init_rxentry,
2065 .init_txentry = rt2x00usb_init_txentry,
2066 .set_device_state = rt73usb_set_device_state,
2067 .link_stats = rt73usb_link_stats,
2068 .reset_tuner = rt73usb_reset_tuner,
2069 .link_tuner = rt73usb_link_tuner,
2070 .led_brightness = rt73usb_led_brightness,
2071 .write_tx_desc = rt73usb_write_tx_desc,
2072 .write_tx_data = rt2x00usb_write_tx_data,
2073 .get_tx_data_len = rt73usb_get_tx_data_len,
2074 .kick_tx_queue = rt73usb_kick_tx_queue,
2075 .fill_rxdone = rt73usb_fill_rxdone,
2076 .config_intf = rt73usb_config_intf,
2077 .config_preamble = rt73usb_config_preamble,
2078 .config = rt73usb_config,
2079 };
2080
2081 static const struct data_queue_desc rt73usb_queue_rx = {
2082 .entry_num = RX_ENTRIES,
2083 .data_size = DATA_FRAME_SIZE,
2084 .desc_size = RXD_DESC_SIZE,
2085 .priv_size = sizeof(struct queue_entry_priv_usb_rx),
2086 };
2087
2088 static const struct data_queue_desc rt73usb_queue_tx = {
2089 .entry_num = TX_ENTRIES,
2090 .data_size = DATA_FRAME_SIZE,
2091 .desc_size = TXD_DESC_SIZE,
2092 .priv_size = sizeof(struct queue_entry_priv_usb_tx),
2093 };
2094
2095 static const struct data_queue_desc rt73usb_queue_bcn = {
2096 .entry_num = 4 * BEACON_ENTRIES,
2097 .data_size = MGMT_FRAME_SIZE,
2098 .desc_size = TXINFO_SIZE,
2099 .priv_size = sizeof(struct queue_entry_priv_usb_tx),
2100 };
2101
2102 static const struct rt2x00_ops rt73usb_ops = {
2103 .name = KBUILD_MODNAME,
2104 .max_sta_intf = 1,
2105 .max_ap_intf = 4,
2106 .eeprom_size = EEPROM_SIZE,
2107 .rf_size = RF_SIZE,
2108 .rx = &rt73usb_queue_rx,
2109 .tx = &rt73usb_queue_tx,
2110 .bcn = &rt73usb_queue_bcn,
2111 .lib = &rt73usb_rt2x00_ops,
2112 .hw = &rt73usb_mac80211_ops,
2113 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2114 .debugfs = &rt73usb_rt2x00debug,
2115 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2116 };
2117
2118 /*
2119 * rt73usb module information.
2120 */
2121 static struct usb_device_id rt73usb_device_table[] = {
2122 /* AboCom */
2123 { USB_DEVICE(0x07b8, 0xb21d), USB_DEVICE_DATA(&rt73usb_ops) },
2124 /* Askey */
2125 { USB_DEVICE(0x1690, 0x0722), USB_DEVICE_DATA(&rt73usb_ops) },
2126 /* ASUS */
2127 { USB_DEVICE(0x0b05, 0x1723), USB_DEVICE_DATA(&rt73usb_ops) },
2128 { USB_DEVICE(0x0b05, 0x1724), USB_DEVICE_DATA(&rt73usb_ops) },
2129 /* Belkin */
2130 { USB_DEVICE(0x050d, 0x7050), USB_DEVICE_DATA(&rt73usb_ops) },
2131 { USB_DEVICE(0x050d, 0x705a), USB_DEVICE_DATA(&rt73usb_ops) },
2132 { USB_DEVICE(0x050d, 0x905b), USB_DEVICE_DATA(&rt73usb_ops) },
2133 { USB_DEVICE(0x050d, 0x905c), USB_DEVICE_DATA(&rt73usb_ops) },
2134 /* Billionton */
2135 { USB_DEVICE(0x1631, 0xc019), USB_DEVICE_DATA(&rt73usb_ops) },
2136 /* Buffalo */
2137 { USB_DEVICE(0x0411, 0x00f4), USB_DEVICE_DATA(&rt73usb_ops) },
2138 /* CNet */
2139 { USB_DEVICE(0x1371, 0x9022), USB_DEVICE_DATA(&rt73usb_ops) },
2140 { USB_DEVICE(0x1371, 0x9032), USB_DEVICE_DATA(&rt73usb_ops) },
2141 /* Conceptronic */
2142 { USB_DEVICE(0x14b2, 0x3c22), USB_DEVICE_DATA(&rt73usb_ops) },
2143 /* D-Link */
2144 { USB_DEVICE(0x07d1, 0x3c03), USB_DEVICE_DATA(&rt73usb_ops) },
2145 { USB_DEVICE(0x07d1, 0x3c04), USB_DEVICE_DATA(&rt73usb_ops) },
2146 /* Gemtek */
2147 { USB_DEVICE(0x15a9, 0x0004), USB_DEVICE_DATA(&rt73usb_ops) },
2148 /* Gigabyte */
2149 { USB_DEVICE(0x1044, 0x8008), USB_DEVICE_DATA(&rt73usb_ops) },
2150 { USB_DEVICE(0x1044, 0x800a), USB_DEVICE_DATA(&rt73usb_ops) },
2151 /* Huawei-3Com */
2152 { USB_DEVICE(0x1472, 0x0009), USB_DEVICE_DATA(&rt73usb_ops) },
2153 /* Hercules */
2154 { USB_DEVICE(0x06f8, 0xe010), USB_DEVICE_DATA(&rt73usb_ops) },
2155 { USB_DEVICE(0x06f8, 0xe020), USB_DEVICE_DATA(&rt73usb_ops) },
2156 /* Linksys */
2157 { USB_DEVICE(0x13b1, 0x0020), USB_DEVICE_DATA(&rt73usb_ops) },
2158 { USB_DEVICE(0x13b1, 0x0023), USB_DEVICE_DATA(&rt73usb_ops) },
2159 /* MSI */
2160 { USB_DEVICE(0x0db0, 0x6877), USB_DEVICE_DATA(&rt73usb_ops) },
2161 { USB_DEVICE(0x0db0, 0x6874), USB_DEVICE_DATA(&rt73usb_ops) },
2162 { USB_DEVICE(0x0db0, 0xa861), USB_DEVICE_DATA(&rt73usb_ops) },
2163 { USB_DEVICE(0x0db0, 0xa874), USB_DEVICE_DATA(&rt73usb_ops) },
2164 /* Ralink */
2165 { USB_DEVICE(0x148f, 0x2573), USB_DEVICE_DATA(&rt73usb_ops) },
2166 { USB_DEVICE(0x148f, 0x2671), USB_DEVICE_DATA(&rt73usb_ops) },
2167 /* Qcom */
2168 { USB_DEVICE(0x18e8, 0x6196), USB_DEVICE_DATA(&rt73usb_ops) },
2169 { USB_DEVICE(0x18e8, 0x6229), USB_DEVICE_DATA(&rt73usb_ops) },
2170 { USB_DEVICE(0x18e8, 0x6238), USB_DEVICE_DATA(&rt73usb_ops) },
2171 /* Senao */
2172 { USB_DEVICE(0x1740, 0x7100), USB_DEVICE_DATA(&rt73usb_ops) },
2173 /* Sitecom */
2174 { USB_DEVICE(0x0df6, 0x9712), USB_DEVICE_DATA(&rt73usb_ops) },
2175 { USB_DEVICE(0x0df6, 0x90ac), USB_DEVICE_DATA(&rt73usb_ops) },
2176 /* Surecom */
2177 { USB_DEVICE(0x0769, 0x31f3), USB_DEVICE_DATA(&rt73usb_ops) },
2178 /* Planex */
2179 { USB_DEVICE(0x2019, 0xab01), USB_DEVICE_DATA(&rt73usb_ops) },
2180 { USB_DEVICE(0x2019, 0xab50), USB_DEVICE_DATA(&rt73usb_ops) },
2181 { 0, }
2182 };
2183
2184 MODULE_AUTHOR(DRV_PROJECT);
2185 MODULE_VERSION(DRV_VERSION);
2186 MODULE_DESCRIPTION("Ralink RT73 USB Wireless LAN driver.");
2187 MODULE_SUPPORTED_DEVICE("Ralink RT2571W & RT2671 USB chipset based cards");
2188 MODULE_DEVICE_TABLE(usb, rt73usb_device_table);
2189 MODULE_FIRMWARE(FIRMWARE_RT2571);
2190 MODULE_LICENSE("GPL");
2191
2192 static struct usb_driver rt73usb_driver = {
2193 .name = KBUILD_MODNAME,
2194 .id_table = rt73usb_device_table,
2195 .probe = rt2x00usb_probe,
2196 .disconnect = rt2x00usb_disconnect,
2197 .suspend = rt2x00usb_suspend,
2198 .resume = rt2x00usb_resume,
2199 };
2200
2201 static int __init rt73usb_init(void)
2202 {
2203 return usb_register(&rt73usb_driver);
2204 }
2205
2206 static void __exit rt73usb_exit(void)
2207 {
2208 usb_deregister(&rt73usb_driver);
2209 }
2210
2211 module_init(rt73usb_init);
2212 module_exit(rt73usb_exit);
Linux kernel - Deliverables
This page took 0.121918 seconds and 5 git commands to generate.