3 * Linux device driver for RTL8180 / RTL8185
5 * Copyright 2007 Michael Wu <flamingice@sourmilk.net>
6 * Copyright 2007 Andrea Merello <andreamrl@tiscali.it>
8 * Based on the r8180 driver, which is:
9 * Copyright 2004-2005 Andrea Merello <andreamrl@tiscali.it>, et al.
11 * Thanks to Realtek for their support!
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
18 #include <linux/init.h>
19 #include <linux/pci.h>
20 #include <linux/delay.h>
21 #include <linux/etherdevice.h>
22 #include <linux/eeprom_93cx6.h>
23 #include <net/mac80211.h>
26 #include "rtl8180_rtl8225.h"
27 #include "rtl8180_sa2400.h"
28 #include "rtl8180_max2820.h"
29 #include "rtl8180_grf5101.h"
31 MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
32 MODULE_AUTHOR("Andrea Merello <andreamrl@tiscali.it>");
33 MODULE_DESCRIPTION("RTL8180 / RTL8185 PCI wireless driver");
34 MODULE_LICENSE("GPL");
36 static struct pci_device_id rtl8180_table
[] __devinitdata
= {
38 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8185) },
39 { PCI_DEVICE(PCI_VENDOR_ID_BELKIN
, 0x701f) },
42 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8180) },
43 { PCI_DEVICE(0x1799, 0x6001) },
44 { PCI_DEVICE(0x1799, 0x6020) },
45 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x3300) },
49 MODULE_DEVICE_TABLE(pci
, rtl8180_table
);
51 void rtl8180_write_phy(struct ieee80211_hw
*dev
, u8 addr
, u32 data
)
53 struct rtl8180_priv
*priv
= dev
->priv
;
57 buf
= (data
<< 8) | addr
;
59 rtl818x_iowrite32(priv
, (__le32 __iomem
*)&priv
->map
->PHY
[0], buf
| 0x80);
61 rtl818x_iowrite32(priv
, (__le32 __iomem
*)&priv
->map
->PHY
[0], buf
);
62 if (rtl818x_ioread8(priv
, &priv
->map
->PHY
[2]) == (data
& 0xFF))
67 static void rtl8180_handle_rx(struct ieee80211_hw
*dev
)
69 struct rtl8180_priv
*priv
= dev
->priv
;
70 unsigned int count
= 32;
73 struct rtl8180_rx_desc
*entry
= &priv
->rx_ring
[priv
->rx_idx
];
74 struct sk_buff
*skb
= priv
->rx_buf
[priv
->rx_idx
];
75 u32 flags
= le32_to_cpu(entry
->flags
);
77 if (flags
& RTL8180_RX_DESC_FLAG_OWN
)
80 if (unlikely(flags
& (RTL8180_RX_DESC_FLAG_DMA_FAIL
|
81 RTL8180_RX_DESC_FLAG_FOF
|
82 RTL8180_RX_DESC_FLAG_RX_ERR
)))
85 u32 flags2
= le32_to_cpu(entry
->flags2
);
86 struct ieee80211_rx_status rx_status
= {0};
87 struct sk_buff
*new_skb
= dev_alloc_skb(MAX_RX_SIZE
);
89 if (unlikely(!new_skb
))
92 pci_unmap_single(priv
->pdev
,
93 *((dma_addr_t
*)skb
->cb
),
94 MAX_RX_SIZE
, PCI_DMA_FROMDEVICE
);
95 skb_put(skb
, flags
& 0xFFF);
97 rx_status
.antenna
= (flags2
>> 15) & 1;
98 /* TODO: improve signal/rssi reporting */
99 rx_status
.signal
= flags2
& 0xFF;
100 rx_status
.ssi
= (flags2
>> 8) & 0x7F;
101 rx_status
.rate
= (flags
>> 20) & 0xF;
102 rx_status
.freq
= dev
->conf
.freq
;
103 rx_status
.channel
= dev
->conf
.channel
;
104 rx_status
.phymode
= dev
->conf
.phymode
;
105 rx_status
.mactime
= le64_to_cpu(entry
->tsft
);
106 rx_status
.flag
|= RX_FLAG_TSFT
;
107 if (flags
& RTL8180_RX_DESC_FLAG_CRC32_ERR
)
108 rx_status
.flag
|= RX_FLAG_FAILED_FCS_CRC
;
110 ieee80211_rx_irqsafe(dev
, skb
, &rx_status
);
113 priv
->rx_buf
[priv
->rx_idx
] = skb
;
114 *((dma_addr_t
*) skb
->cb
) =
115 pci_map_single(priv
->pdev
, skb_tail_pointer(skb
),
116 MAX_RX_SIZE
, PCI_DMA_FROMDEVICE
);
120 entry
->rx_buf
= cpu_to_le32(*((dma_addr_t
*)skb
->cb
));
121 entry
->flags
= cpu_to_le32(RTL8180_RX_DESC_FLAG_OWN
|
123 if (priv
->rx_idx
== 31)
124 entry
->flags
|= cpu_to_le32(RTL8180_RX_DESC_FLAG_EOR
);
125 priv
->rx_idx
= (priv
->rx_idx
+ 1) % 32;
129 static void rtl8180_handle_tx(struct ieee80211_hw
*dev
, unsigned int prio
)
131 struct rtl8180_priv
*priv
= dev
->priv
;
132 struct rtl8180_tx_ring
*ring
= &priv
->tx_ring
[prio
];
134 while (skb_queue_len(&ring
->queue
)) {
135 struct rtl8180_tx_desc
*entry
= &ring
->desc
[ring
->idx
];
137 struct ieee80211_tx_status status
= { {0} };
138 struct ieee80211_tx_control
*control
;
139 u32 flags
= le32_to_cpu(entry
->flags
);
141 if (flags
& RTL8180_TX_DESC_FLAG_OWN
)
144 ring
->idx
= (ring
->idx
+ 1) % ring
->entries
;
145 skb
= __skb_dequeue(&ring
->queue
);
146 pci_unmap_single(priv
->pdev
, le32_to_cpu(entry
->tx_buf
),
147 skb
->len
, PCI_DMA_TODEVICE
);
149 control
= *((struct ieee80211_tx_control
**)skb
->cb
);
151 memcpy(&status
.control
, control
, sizeof(*control
));
154 if (!(status
.control
.flags
& IEEE80211_TXCTL_NO_ACK
)) {
155 if (flags
& RTL8180_TX_DESC_FLAG_TX_OK
)
156 status
.flags
= IEEE80211_TX_STATUS_ACK
;
158 status
.excessive_retries
= 1;
160 status
.retry_count
= flags
& 0xFF;
162 ieee80211_tx_status_irqsafe(dev
, skb
, &status
);
163 if (ring
->entries
- skb_queue_len(&ring
->queue
) == 2)
164 ieee80211_wake_queue(dev
, prio
);
168 static irqreturn_t
rtl8180_interrupt(int irq
, void *dev_id
)
170 struct ieee80211_hw
*dev
= dev_id
;
171 struct rtl8180_priv
*priv
= dev
->priv
;
174 spin_lock(&priv
->lock
);
175 reg
= rtl818x_ioread16(priv
, &priv
->map
->INT_STATUS
);
176 if (unlikely(reg
== 0xFFFF)) {
177 spin_unlock(&priv
->lock
);
181 rtl818x_iowrite16(priv
, &priv
->map
->INT_STATUS
, reg
);
183 if (reg
& (RTL818X_INT_TXB_OK
| RTL818X_INT_TXB_ERR
))
184 rtl8180_handle_tx(dev
, 3);
186 if (reg
& (RTL818X_INT_TXH_OK
| RTL818X_INT_TXH_ERR
))
187 rtl8180_handle_tx(dev
, 2);
189 if (reg
& (RTL818X_INT_TXN_OK
| RTL818X_INT_TXN_ERR
))
190 rtl8180_handle_tx(dev
, 1);
192 if (reg
& (RTL818X_INT_TXL_OK
| RTL818X_INT_TXL_ERR
))
193 rtl8180_handle_tx(dev
, 0);
195 if (reg
& (RTL818X_INT_RX_OK
| RTL818X_INT_RX_ERR
))
196 rtl8180_handle_rx(dev
);
198 spin_unlock(&priv
->lock
);
203 static int rtl8180_tx(struct ieee80211_hw
*dev
, struct sk_buff
*skb
,
204 struct ieee80211_tx_control
*control
)
206 struct rtl8180_priv
*priv
= dev
->priv
;
207 struct rtl8180_tx_ring
*ring
;
208 struct rtl8180_tx_desc
*entry
;
210 unsigned int idx
, prio
;
214 __le16 rts_duration
= 0;
216 prio
= control
->queue
;
217 ring
= &priv
->tx_ring
[prio
];
219 mapping
= pci_map_single(priv
->pdev
, skb
->data
,
220 skb
->len
, PCI_DMA_TODEVICE
);
222 tx_flags
= RTL8180_TX_DESC_FLAG_OWN
| RTL8180_TX_DESC_FLAG_FS
|
223 RTL8180_TX_DESC_FLAG_LS
| (control
->tx_rate
<< 24) |
224 (control
->rts_cts_rate
<< 19) | skb
->len
;
227 tx_flags
|= RTL8180_TX_DESC_FLAG_DMA
|
228 RTL8180_TX_DESC_FLAG_NO_ENC
;
230 if (control
->flags
& IEEE80211_TXCTL_USE_RTS_CTS
)
231 tx_flags
|= RTL8180_TX_DESC_FLAG_RTS
;
232 else if (control
->flags
& IEEE80211_TXCTL_USE_CTS_PROTECT
)
233 tx_flags
|= RTL8180_TX_DESC_FLAG_CTS
;
235 *((struct ieee80211_tx_control
**) skb
->cb
) =
236 kmemdup(control
, sizeof(*control
), GFP_ATOMIC
);
238 if (control
->flags
& IEEE80211_TXCTL_USE_RTS_CTS
)
239 rts_duration
= ieee80211_rts_duration(dev
, priv
->vif
, skb
->len
,
243 unsigned int remainder
;
245 plcp_len
= DIV_ROUND_UP(16 * (skb
->len
+ 4),
246 (control
->rate
->rate
* 2) / 10);
247 remainder
= (16 * (skb
->len
+ 4)) %
248 ((control
->rate
->rate
* 2) / 10);
249 if (remainder
> 0 && remainder
<= 6)
253 spin_lock_irqsave(&priv
->lock
, flags
);
254 idx
= (ring
->idx
+ skb_queue_len(&ring
->queue
)) % ring
->entries
;
255 entry
= &ring
->desc
[idx
];
257 entry
->rts_duration
= rts_duration
;
258 entry
->plcp_len
= cpu_to_le16(plcp_len
);
259 entry
->tx_buf
= cpu_to_le32(mapping
);
260 entry
->frame_len
= cpu_to_le32(skb
->len
);
261 entry
->flags2
= control
->alt_retry_rate
!= -1 ?
262 control
->alt_retry_rate
<< 4 : 0;
263 entry
->retry_limit
= control
->retry_limit
;
264 entry
->flags
= cpu_to_le32(tx_flags
);
265 __skb_queue_tail(&ring
->queue
, skb
);
266 if (ring
->entries
- skb_queue_len(&ring
->queue
) < 2)
267 ieee80211_stop_queue(dev
, control
->queue
);
268 spin_unlock_irqrestore(&priv
->lock
, flags
);
270 rtl818x_iowrite8(priv
, &priv
->map
->TX_DMA_POLLING
, (1 << (prio
+ 4)));
275 void rtl8180_set_anaparam(struct rtl8180_priv
*priv
, u32 anaparam
)
279 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
, RTL818X_EEPROM_CMD_CONFIG
);
280 reg
= rtl818x_ioread8(priv
, &priv
->map
->CONFIG3
);
281 rtl818x_iowrite8(priv
, &priv
->map
->CONFIG3
,
282 reg
| RTL818X_CONFIG3_ANAPARAM_WRITE
);
283 rtl818x_iowrite32(priv
, &priv
->map
->ANAPARAM
, anaparam
);
284 rtl818x_iowrite8(priv
, &priv
->map
->CONFIG3
,
285 reg
& ~RTL818X_CONFIG3_ANAPARAM_WRITE
);
286 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
, RTL818X_EEPROM_CMD_NORMAL
);
289 static int rtl8180_init_hw(struct ieee80211_hw
*dev
)
291 struct rtl8180_priv
*priv
= dev
->priv
;
294 rtl818x_iowrite8(priv
, &priv
->map
->CMD
, 0);
295 rtl818x_ioread8(priv
, &priv
->map
->CMD
);
299 rtl818x_iowrite16(priv
, &priv
->map
->INT_MASK
, 0);
300 rtl818x_ioread8(priv
, &priv
->map
->CMD
);
302 reg
= rtl818x_ioread8(priv
, &priv
->map
->CMD
);
304 reg
|= RTL818X_CMD_RESET
;
305 rtl818x_iowrite8(priv
, &priv
->map
->CMD
, RTL818X_CMD_RESET
);
306 rtl818x_ioread8(priv
, &priv
->map
->CMD
);
309 /* check success of reset */
310 if (rtl818x_ioread8(priv
, &priv
->map
->CMD
) & RTL818X_CMD_RESET
) {
311 printk(KERN_ERR
"%s: reset timeout!\n", wiphy_name(dev
->wiphy
));
315 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
, RTL818X_EEPROM_CMD_LOAD
);
316 rtl818x_ioread8(priv
, &priv
->map
->CMD
);
319 if (rtl818x_ioread8(priv
, &priv
->map
->CONFIG3
) & (1 << 3)) {
321 reg
= rtl818x_ioread8(priv
, &priv
->map
->CONFIG3
);
323 rtl818x_iowrite8(priv
, &priv
->map
->CONFIG3
, reg
);
324 reg
= rtl818x_ioread16(priv
, &priv
->map
->FEMR
);
325 reg
|= (1 << 15) | (1 << 14) | (1 << 4);
326 rtl818x_iowrite16(priv
, &priv
->map
->FEMR
, reg
);
329 rtl818x_iowrite8(priv
, &priv
->map
->MSR
, 0);
332 rtl8180_set_anaparam(priv
, priv
->anaparam
);
334 rtl818x_iowrite32(priv
, &priv
->map
->RDSAR
, priv
->rx_ring_dma
);
335 rtl818x_iowrite32(priv
, &priv
->map
->TBDA
, priv
->tx_ring
[3].dma
);
336 rtl818x_iowrite32(priv
, &priv
->map
->THPDA
, priv
->tx_ring
[2].dma
);
337 rtl818x_iowrite32(priv
, &priv
->map
->TNPDA
, priv
->tx_ring
[1].dma
);
338 rtl818x_iowrite32(priv
, &priv
->map
->TLPDA
, priv
->tx_ring
[0].dma
);
340 /* TODO: necessary? specs indicate not */
341 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
, RTL818X_EEPROM_CMD_CONFIG
);
342 reg
= rtl818x_ioread8(priv
, &priv
->map
->CONFIG2
);
343 rtl818x_iowrite8(priv
, &priv
->map
->CONFIG2
, reg
& ~(1 << 3));
345 reg
= rtl818x_ioread8(priv
, &priv
->map
->CONFIG2
);
346 rtl818x_iowrite8(priv
, &priv
->map
->CONFIG2
, reg
| (1 << 4));
348 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
, RTL818X_EEPROM_CMD_NORMAL
);
350 /* TODO: set CONFIG5 for calibrating AGC on rtl8180 + philips radio? */
352 /* TODO: turn off hw wep on rtl8180 */
354 rtl818x_iowrite32(priv
, &priv
->map
->INT_TIMEOUT
, 0);
357 rtl818x_iowrite8(priv
, &priv
->map
->WPA_CONF
, 0);
358 rtl818x_iowrite8(priv
, &priv
->map
->RATE_FALLBACK
, 0x81);
359 rtl818x_iowrite8(priv
, &priv
->map
->RESP_RATE
, (8 << 4) | 0);
361 rtl818x_iowrite16(priv
, &priv
->map
->BRSR
, 0x01F3);
363 /* TODO: set ClkRun enable? necessary? */
364 reg
= rtl818x_ioread8(priv
, &priv
->map
->GP_ENABLE
);
365 rtl818x_iowrite8(priv
, &priv
->map
->GP_ENABLE
, reg
& ~(1 << 6));
366 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
, RTL818X_EEPROM_CMD_CONFIG
);
367 reg
= rtl818x_ioread8(priv
, &priv
->map
->CONFIG3
);
368 rtl818x_iowrite8(priv
, &priv
->map
->CONFIG3
, reg
| (1 << 2));
369 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
, RTL818X_EEPROM_CMD_NORMAL
);
371 rtl818x_iowrite16(priv
, &priv
->map
->BRSR
, 0x1);
372 rtl818x_iowrite8(priv
, &priv
->map
->SECURITY
, 0);
374 rtl818x_iowrite8(priv
, &priv
->map
->PHY_DELAY
, 0x6);
375 rtl818x_iowrite8(priv
, &priv
->map
->CARRIER_SENSE_COUNTER
, 0x4C);
380 rtl818x_iowrite16(priv
, &priv
->map
->BRSR
, 0x01F3);
384 static int rtl8180_init_rx_ring(struct ieee80211_hw
*dev
)
386 struct rtl8180_priv
*priv
= dev
->priv
;
387 struct rtl8180_rx_desc
*entry
;
390 priv
->rx_ring
= pci_alloc_consistent(priv
->pdev
,
391 sizeof(*priv
->rx_ring
) * 32,
394 if (!priv
->rx_ring
|| (unsigned long)priv
->rx_ring
& 0xFF) {
395 printk(KERN_ERR
"%s: Cannot allocate RX ring\n",
396 wiphy_name(dev
->wiphy
));
400 memset(priv
->rx_ring
, 0, sizeof(*priv
->rx_ring
) * 32);
403 for (i
= 0; i
< 32; i
++) {
404 struct sk_buff
*skb
= dev_alloc_skb(MAX_RX_SIZE
);
406 entry
= &priv
->rx_ring
[i
];
410 priv
->rx_buf
[i
] = skb
;
411 mapping
= (dma_addr_t
*)skb
->cb
;
412 *mapping
= pci_map_single(priv
->pdev
, skb_tail_pointer(skb
),
413 MAX_RX_SIZE
, PCI_DMA_FROMDEVICE
);
414 entry
->rx_buf
= cpu_to_le32(*mapping
);
415 entry
->flags
= cpu_to_le32(RTL8180_RX_DESC_FLAG_OWN
|
418 entry
->flags
|= cpu_to_le32(RTL8180_RX_DESC_FLAG_EOR
);
422 static void rtl8180_free_rx_ring(struct ieee80211_hw
*dev
)
424 struct rtl8180_priv
*priv
= dev
->priv
;
427 for (i
= 0; i
< 32; i
++) {
428 struct sk_buff
*skb
= priv
->rx_buf
[i
];
432 pci_unmap_single(priv
->pdev
,
433 *((dma_addr_t
*)skb
->cb
),
434 MAX_RX_SIZE
, PCI_DMA_FROMDEVICE
);
438 pci_free_consistent(priv
->pdev
, sizeof(*priv
->rx_ring
) * 32,
439 priv
->rx_ring
, priv
->rx_ring_dma
);
440 priv
->rx_ring
= NULL
;
443 static int rtl8180_init_tx_ring(struct ieee80211_hw
*dev
,
444 unsigned int prio
, unsigned int entries
)
446 struct rtl8180_priv
*priv
= dev
->priv
;
447 struct rtl8180_tx_desc
*ring
;
451 ring
= pci_alloc_consistent(priv
->pdev
, sizeof(*ring
) * entries
, &dma
);
452 if (!ring
|| (unsigned long)ring
& 0xFF) {
453 printk(KERN_ERR
"%s: Cannot allocate TX ring (prio = %d)\n",
454 wiphy_name(dev
->wiphy
), prio
);
458 memset(ring
, 0, sizeof(*ring
)*entries
);
459 priv
->tx_ring
[prio
].desc
= ring
;
460 priv
->tx_ring
[prio
].dma
= dma
;
461 priv
->tx_ring
[prio
].idx
= 0;
462 priv
->tx_ring
[prio
].entries
= entries
;
463 skb_queue_head_init(&priv
->tx_ring
[prio
].queue
);
465 for (i
= 0; i
< entries
; i
++)
466 ring
[i
].next_tx_desc
=
467 cpu_to_le32((u32
)dma
+ ((i
+ 1) % entries
) * sizeof(*ring
));
472 static void rtl8180_free_tx_ring(struct ieee80211_hw
*dev
, unsigned int prio
)
474 struct rtl8180_priv
*priv
= dev
->priv
;
475 struct rtl8180_tx_ring
*ring
= &priv
->tx_ring
[prio
];
477 while (skb_queue_len(&ring
->queue
)) {
478 struct rtl8180_tx_desc
*entry
= &ring
->desc
[ring
->idx
];
479 struct sk_buff
*skb
= __skb_dequeue(&ring
->queue
);
481 pci_unmap_single(priv
->pdev
, le32_to_cpu(entry
->tx_buf
),
482 skb
->len
, PCI_DMA_TODEVICE
);
483 kfree(*((struct ieee80211_tx_control
**) skb
->cb
));
485 ring
->idx
= (ring
->idx
+ 1) % ring
->entries
;
488 pci_free_consistent(priv
->pdev
, sizeof(*ring
->desc
)*ring
->entries
,
489 ring
->desc
, ring
->dma
);
493 static int rtl8180_start(struct ieee80211_hw
*dev
)
495 struct rtl8180_priv
*priv
= dev
->priv
;
499 ret
= rtl8180_init_rx_ring(dev
);
503 for (i
= 0; i
< 4; i
++)
504 if ((ret
= rtl8180_init_tx_ring(dev
, i
, 16)))
507 ret
= rtl8180_init_hw(dev
);
511 rtl818x_iowrite32(priv
, &priv
->map
->RDSAR
, priv
->rx_ring_dma
);
512 rtl818x_iowrite32(priv
, &priv
->map
->TBDA
, priv
->tx_ring
[3].dma
);
513 rtl818x_iowrite32(priv
, &priv
->map
->THPDA
, priv
->tx_ring
[2].dma
);
514 rtl818x_iowrite32(priv
, &priv
->map
->TNPDA
, priv
->tx_ring
[1].dma
);
515 rtl818x_iowrite32(priv
, &priv
->map
->TLPDA
, priv
->tx_ring
[0].dma
);
517 ret
= request_irq(priv
->pdev
->irq
, &rtl8180_interrupt
,
518 IRQF_SHARED
, KBUILD_MODNAME
, dev
);
520 printk(KERN_ERR
"%s: failed to register IRQ handler\n",
521 wiphy_name(dev
->wiphy
));
525 rtl818x_iowrite16(priv
, &priv
->map
->INT_MASK
, 0xFFFF);
527 rtl818x_iowrite32(priv
, &priv
->map
->MAR
[0], ~0);
528 rtl818x_iowrite32(priv
, &priv
->map
->MAR
[1], ~0);
530 reg
= RTL818X_RX_CONF_ONLYERLPKT
|
531 RTL818X_RX_CONF_RX_AUTORESETPHY
|
532 RTL818X_RX_CONF_MGMT
|
533 RTL818X_RX_CONF_DATA
|
534 (7 << 8 /* MAX RX DMA */) |
535 RTL818X_RX_CONF_BROADCAST
|
536 RTL818X_RX_CONF_NICMAC
;
539 reg
|= RTL818X_RX_CONF_CSDM1
| RTL818X_RX_CONF_CSDM2
;
541 reg
|= (priv
->rfparam
& RF_PARAM_CARRIERSENSE1
)
542 ? RTL818X_RX_CONF_CSDM1
: 0;
543 reg
|= (priv
->rfparam
& RF_PARAM_CARRIERSENSE2
)
544 ? RTL818X_RX_CONF_CSDM2
: 0;
548 rtl818x_iowrite32(priv
, &priv
->map
->RX_CONF
, reg
);
551 reg
= rtl818x_ioread8(priv
, &priv
->map
->CW_CONF
);
552 reg
&= ~RTL818X_CW_CONF_PERPACKET_CW_SHIFT
;
553 reg
|= RTL818X_CW_CONF_PERPACKET_RETRY_SHIFT
;
554 rtl818x_iowrite8(priv
, &priv
->map
->CW_CONF
, reg
);
556 reg
= rtl818x_ioread8(priv
, &priv
->map
->TX_AGC_CTL
);
557 reg
&= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN_SHIFT
;
558 reg
&= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT
;
559 reg
|= RTL818X_TX_AGC_CTL_FEEDBACK_ANT
;
560 rtl818x_iowrite8(priv
, &priv
->map
->TX_AGC_CTL
, reg
);
562 /* disable early TX */
563 rtl818x_iowrite8(priv
, (u8 __iomem
*)priv
->map
+ 0xec, 0x3f);
566 reg
= rtl818x_ioread32(priv
, &priv
->map
->TX_CONF
);
567 reg
|= (6 << 21 /* MAX TX DMA */) |
568 RTL818X_TX_CONF_NO_ICV
;
571 reg
&= ~RTL818X_TX_CONF_PROBE_DTS
;
573 reg
&= ~RTL818X_TX_CONF_HW_SEQNUM
;
575 /* different meaning, same value on both rtl8185 and rtl8180 */
576 reg
&= ~RTL818X_TX_CONF_SAT_HWPLCP
;
578 rtl818x_iowrite32(priv
, &priv
->map
->TX_CONF
, reg
);
580 reg
= rtl818x_ioread8(priv
, &priv
->map
->CMD
);
581 reg
|= RTL818X_CMD_RX_ENABLE
;
582 reg
|= RTL818X_CMD_TX_ENABLE
;
583 rtl818x_iowrite8(priv
, &priv
->map
->CMD
, reg
);
585 priv
->mode
= IEEE80211_IF_TYPE_MNTR
;
589 rtl8180_free_rx_ring(dev
);
590 for (i
= 0; i
< 4; i
++)
591 if (priv
->tx_ring
[i
].desc
)
592 rtl8180_free_tx_ring(dev
, i
);
597 static void rtl8180_stop(struct ieee80211_hw
*dev
)
599 struct rtl8180_priv
*priv
= dev
->priv
;
603 priv
->mode
= IEEE80211_IF_TYPE_INVALID
;
605 rtl818x_iowrite16(priv
, &priv
->map
->INT_MASK
, 0);
607 reg
= rtl818x_ioread8(priv
, &priv
->map
->CMD
);
608 reg
&= ~RTL818X_CMD_TX_ENABLE
;
609 reg
&= ~RTL818X_CMD_RX_ENABLE
;
610 rtl818x_iowrite8(priv
, &priv
->map
->CMD
, reg
);
614 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
, RTL818X_EEPROM_CMD_CONFIG
);
615 reg
= rtl818x_ioread8(priv
, &priv
->map
->CONFIG4
);
616 rtl818x_iowrite8(priv
, &priv
->map
->CONFIG4
, reg
| RTL818X_CONFIG4_VCOOFF
);
617 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
, RTL818X_EEPROM_CMD_NORMAL
);
619 free_irq(priv
->pdev
->irq
, dev
);
621 rtl8180_free_rx_ring(dev
);
622 for (i
= 0; i
< 4; i
++)
623 rtl8180_free_tx_ring(dev
, i
);
626 static int rtl8180_add_interface(struct ieee80211_hw
*dev
,
627 struct ieee80211_if_init_conf
*conf
)
629 struct rtl8180_priv
*priv
= dev
->priv
;
631 if (priv
->mode
!= IEEE80211_IF_TYPE_MNTR
)
634 switch (conf
->type
) {
635 case IEEE80211_IF_TYPE_STA
:
636 priv
->mode
= conf
->type
;
642 priv
->vif
= conf
->vif
;
644 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
, RTL818X_EEPROM_CMD_CONFIG
);
645 rtl818x_iowrite32(priv
, (__le32 __iomem
*)&priv
->map
->MAC
[0],
646 cpu_to_le32(*(u32
*)conf
->mac_addr
));
647 rtl818x_iowrite16(priv
, (__le16 __iomem
*)&priv
->map
->MAC
[4],
648 cpu_to_le16(*(u16
*)(conf
->mac_addr
+ 4)));
649 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
, RTL818X_EEPROM_CMD_NORMAL
);
654 static void rtl8180_remove_interface(struct ieee80211_hw
*dev
,
655 struct ieee80211_if_init_conf
*conf
)
657 struct rtl8180_priv
*priv
= dev
->priv
;
658 priv
->mode
= IEEE80211_IF_TYPE_MNTR
;
662 static int rtl8180_config(struct ieee80211_hw
*dev
, struct ieee80211_conf
*conf
)
664 struct rtl8180_priv
*priv
= dev
->priv
;
666 priv
->rf
->set_chan(dev
, conf
);
671 static int rtl8180_config_interface(struct ieee80211_hw
*dev
,
672 struct ieee80211_vif
*vif
,
673 struct ieee80211_if_conf
*conf
)
675 struct rtl8180_priv
*priv
= dev
->priv
;
678 for (i
= 0; i
< ETH_ALEN
; i
++)
679 rtl818x_iowrite8(priv
, &priv
->map
->BSSID
[i
], conf
->bssid
[i
]);
681 if (is_valid_ether_addr(conf
->bssid
))
682 rtl818x_iowrite8(priv
, &priv
->map
->MSR
, RTL818X_MSR_INFRA
);
684 rtl818x_iowrite8(priv
, &priv
->map
->MSR
, RTL818X_MSR_NO_LINK
);
689 static void rtl8180_configure_filter(struct ieee80211_hw
*dev
,
690 unsigned int changed_flags
,
691 unsigned int *total_flags
,
692 int mc_count
, struct dev_addr_list
*mclist
)
694 struct rtl8180_priv
*priv
= dev
->priv
;
696 if (changed_flags
& FIF_FCSFAIL
)
697 priv
->rx_conf
^= RTL818X_RX_CONF_FCS
;
698 if (changed_flags
& FIF_CONTROL
)
699 priv
->rx_conf
^= RTL818X_RX_CONF_CTRL
;
700 if (changed_flags
& FIF_OTHER_BSS
)
701 priv
->rx_conf
^= RTL818X_RX_CONF_MONITOR
;
702 if (*total_flags
& FIF_ALLMULTI
|| mc_count
> 0)
703 priv
->rx_conf
|= RTL818X_RX_CONF_MULTICAST
;
705 priv
->rx_conf
&= ~RTL818X_RX_CONF_MULTICAST
;
709 if (priv
->rx_conf
& RTL818X_RX_CONF_FCS
)
710 *total_flags
|= FIF_FCSFAIL
;
711 if (priv
->rx_conf
& RTL818X_RX_CONF_CTRL
)
712 *total_flags
|= FIF_CONTROL
;
713 if (priv
->rx_conf
& RTL818X_RX_CONF_MONITOR
)
714 *total_flags
|= FIF_OTHER_BSS
;
715 if (priv
->rx_conf
& RTL818X_RX_CONF_MULTICAST
)
716 *total_flags
|= FIF_ALLMULTI
;
718 rtl818x_iowrite32(priv
, &priv
->map
->RX_CONF
, priv
->rx_conf
);
721 static const struct ieee80211_ops rtl8180_ops
= {
723 .start
= rtl8180_start
,
724 .stop
= rtl8180_stop
,
725 .add_interface
= rtl8180_add_interface
,
726 .remove_interface
= rtl8180_remove_interface
,
727 .config
= rtl8180_config
,
728 .config_interface
= rtl8180_config_interface
,
729 .configure_filter
= rtl8180_configure_filter
,
732 static void rtl8180_eeprom_register_read(struct eeprom_93cx6
*eeprom
)
734 struct ieee80211_hw
*dev
= eeprom
->data
;
735 struct rtl8180_priv
*priv
= dev
->priv
;
736 u8 reg
= rtl818x_ioread8(priv
, &priv
->map
->EEPROM_CMD
);
738 eeprom
->reg_data_in
= reg
& RTL818X_EEPROM_CMD_WRITE
;
739 eeprom
->reg_data_out
= reg
& RTL818X_EEPROM_CMD_READ
;
740 eeprom
->reg_data_clock
= reg
& RTL818X_EEPROM_CMD_CK
;
741 eeprom
->reg_chip_select
= reg
& RTL818X_EEPROM_CMD_CS
;
744 static void rtl8180_eeprom_register_write(struct eeprom_93cx6
*eeprom
)
746 struct ieee80211_hw
*dev
= eeprom
->data
;
747 struct rtl8180_priv
*priv
= dev
->priv
;
750 if (eeprom
->reg_data_in
)
751 reg
|= RTL818X_EEPROM_CMD_WRITE
;
752 if (eeprom
->reg_data_out
)
753 reg
|= RTL818X_EEPROM_CMD_READ
;
754 if (eeprom
->reg_data_clock
)
755 reg
|= RTL818X_EEPROM_CMD_CK
;
756 if (eeprom
->reg_chip_select
)
757 reg
|= RTL818X_EEPROM_CMD_CS
;
759 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
, reg
);
760 rtl818x_ioread8(priv
, &priv
->map
->EEPROM_CMD
);
764 static int __devinit
rtl8180_probe(struct pci_dev
*pdev
,
765 const struct pci_device_id
*id
)
767 struct ieee80211_hw
*dev
;
768 struct rtl8180_priv
*priv
;
769 unsigned long mem_addr
, mem_len
;
770 unsigned int io_addr
, io_len
;
772 struct eeprom_93cx6 eeprom
;
773 const char *chip_name
, *rf_name
= NULL
;
776 DECLARE_MAC_BUF(mac
);
778 err
= pci_enable_device(pdev
);
780 printk(KERN_ERR
"%s (rtl8180): Cannot enable new PCI device\n",
785 err
= pci_request_regions(pdev
, KBUILD_MODNAME
);
787 printk(KERN_ERR
"%s (rtl8180): Cannot obtain PCI resources\n",
792 io_addr
= pci_resource_start(pdev
, 0);
793 io_len
= pci_resource_len(pdev
, 0);
794 mem_addr
= pci_resource_start(pdev
, 1);
795 mem_len
= pci_resource_len(pdev
, 1);
797 if (mem_len
< sizeof(struct rtl818x_csr
) ||
798 io_len
< sizeof(struct rtl818x_csr
)) {
799 printk(KERN_ERR
"%s (rtl8180): Too short PCI resources\n",
805 if ((err
= pci_set_dma_mask(pdev
, 0xFFFFFF00ULL
)) ||
806 (err
= pci_set_consistent_dma_mask(pdev
, 0xFFFFFF00ULL
))) {
807 printk(KERN_ERR
"%s (rtl8180): No suitable DMA available\n",
812 pci_set_master(pdev
);
814 dev
= ieee80211_alloc_hw(sizeof(*priv
), &rtl8180_ops
);
816 printk(KERN_ERR
"%s (rtl8180): ieee80211 alloc failed\n",
825 SET_IEEE80211_DEV(dev
, &pdev
->dev
);
826 pci_set_drvdata(pdev
, dev
);
828 priv
->map
= pci_iomap(pdev
, 1, mem_len
);
830 priv
->map
= pci_iomap(pdev
, 0, io_len
);
833 printk(KERN_ERR
"%s (rtl8180): Cannot map device memory\n",
838 memcpy(priv
->channels
, rtl818x_channels
, sizeof(rtl818x_channels
));
839 memcpy(priv
->rates
, rtl818x_rates
, sizeof(rtl818x_rates
));
840 priv
->modes
[0].mode
= MODE_IEEE80211G
;
841 priv
->modes
[0].num_rates
= ARRAY_SIZE(rtl818x_rates
);
842 priv
->modes
[0].rates
= priv
->rates
;
843 priv
->modes
[0].num_channels
= ARRAY_SIZE(rtl818x_channels
);
844 priv
->modes
[0].channels
= priv
->channels
;
845 priv
->modes
[1].mode
= MODE_IEEE80211B
;
846 priv
->modes
[1].num_rates
= 4;
847 priv
->modes
[1].rates
= priv
->rates
;
848 priv
->modes
[1].num_channels
= ARRAY_SIZE(rtl818x_channels
);
849 priv
->modes
[1].channels
= priv
->channels
;
850 priv
->mode
= IEEE80211_IF_TYPE_INVALID
;
851 dev
->flags
= IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING
|
852 IEEE80211_HW_RX_INCLUDES_FCS
;
856 reg
= rtl818x_ioread32(priv
, &priv
->map
->TX_CONF
);
857 reg
&= RTL818X_TX_CONF_HWVER_MASK
;
859 case RTL818X_TX_CONF_R8180_ABCD
:
860 chip_name
= "RTL8180";
862 case RTL818X_TX_CONF_R8180_F
:
863 chip_name
= "RTL8180vF";
865 case RTL818X_TX_CONF_R8185_ABC
:
866 chip_name
= "RTL8185";
868 case RTL818X_TX_CONF_R8185_D
:
869 chip_name
= "RTL8185vD";
872 printk(KERN_ERR
"%s (rtl8180): Unknown chip! (0x%x)\n",
873 pci_name(pdev
), reg
>> 25);
877 priv
->r8185
= reg
& RTL818X_TX_CONF_R8185_ABC
;
879 if ((err
= ieee80211_register_hwmode(dev
, &priv
->modes
[0])))
882 pci_try_set_mwi(pdev
);
885 if ((err
= ieee80211_register_hwmode(dev
, &priv
->modes
[1])))
889 eeprom
.register_read
= rtl8180_eeprom_register_read
;
890 eeprom
.register_write
= rtl8180_eeprom_register_write
;
891 if (rtl818x_ioread32(priv
, &priv
->map
->RX_CONF
) & (1 << 6))
892 eeprom
.width
= PCI_EEPROM_WIDTH_93C66
;
894 eeprom
.width
= PCI_EEPROM_WIDTH_93C46
;
896 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
, RTL818X_EEPROM_CMD_PROGRAM
);
897 rtl818x_ioread8(priv
, &priv
->map
->EEPROM_CMD
);
900 eeprom_93cx6_read(&eeprom
, 0x06, &eeprom_val
);
902 switch (eeprom_val
) {
903 case 1: rf_name
= "Intersil";
905 case 2: rf_name
= "RFMD";
907 case 3: priv
->rf
= &sa2400_rf_ops
;
909 case 4: priv
->rf
= &max2820_rf_ops
;
911 case 5: priv
->rf
= &grf5101_rf_ops
;
913 case 9: priv
->rf
= rtl8180_detect_rf(dev
);
919 printk(KERN_ERR
"%s (rtl8180): Unknown RF! (0x%x)\n",
920 pci_name(pdev
), eeprom_val
);
925 printk(KERN_ERR
"%s (rtl8180): %s RF frontend not supported!\n",
926 pci_name(pdev
), rf_name
);
930 eeprom_93cx6_read(&eeprom
, 0x17, &eeprom_val
);
931 priv
->csthreshold
= eeprom_val
>> 8;
934 eeprom_93cx6_multiread(&eeprom
, 0xD, (__le16
*)&anaparam
, 2);
935 priv
->anaparam
= le32_to_cpu(anaparam
);
936 eeprom_93cx6_read(&eeprom
, 0x19, &priv
->rfparam
);
939 eeprom_93cx6_multiread(&eeprom
, 0x7, (__le16
*)dev
->wiphy
->perm_addr
, 3);
940 if (!is_valid_ether_addr(dev
->wiphy
->perm_addr
)) {
941 printk(KERN_WARNING
"%s (rtl8180): Invalid hwaddr! Using"
942 " randomly generated MAC addr\n", pci_name(pdev
));
943 random_ether_addr(dev
->wiphy
->perm_addr
);
947 for (i
= 0; i
< 14; i
+= 2) {
949 eeprom_93cx6_read(&eeprom
, 0x10 + (i
>> 1), &txpwr
);
950 priv
->channels
[i
].val
= txpwr
& 0xFF;
951 priv
->channels
[i
+ 1].val
= txpwr
>> 8;
956 for (i
= 0; i
< 14; i
+= 2) {
958 eeprom_93cx6_read(&eeprom
, 0x20 + (i
>> 1), &txpwr
);
959 priv
->channels
[i
].val
|= (txpwr
& 0xFF) << 8;
960 priv
->channels
[i
+ 1].val
|= txpwr
& 0xFF00;
964 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
, RTL818X_EEPROM_CMD_NORMAL
);
966 spin_lock_init(&priv
->lock
);
968 err
= ieee80211_register_hw(dev
);
970 printk(KERN_ERR
"%s (rtl8180): Cannot register device\n",
975 printk(KERN_INFO
"%s: hwaddr %s, %s + %s\n",
976 wiphy_name(dev
->wiphy
), print_mac(mac
, dev
->wiphy
->perm_addr
),
977 chip_name
, priv
->rf
->name
);
985 pci_set_drvdata(pdev
, NULL
);
986 ieee80211_free_hw(dev
);
989 pci_release_regions(pdev
);
990 pci_disable_device(pdev
);
994 static void __devexit
rtl8180_remove(struct pci_dev
*pdev
)
996 struct ieee80211_hw
*dev
= pci_get_drvdata(pdev
);
997 struct rtl8180_priv
*priv
;
1002 ieee80211_unregister_hw(dev
);
1006 pci_iounmap(pdev
, priv
->map
);
1007 pci_release_regions(pdev
);
1008 pci_disable_device(pdev
);
1009 ieee80211_free_hw(dev
);
1013 static int rtl8180_suspend(struct pci_dev
*pdev
, pm_message_t state
)
1015 pci_save_state(pdev
);
1016 pci_set_power_state(pdev
, pci_choose_state(pdev
, state
));
1020 static int rtl8180_resume(struct pci_dev
*pdev
)
1022 pci_set_power_state(pdev
, PCI_D0
);
1023 pci_restore_state(pdev
);
1027 #endif /* CONFIG_PM */
1029 static struct pci_driver rtl8180_driver
= {
1030 .name
= KBUILD_MODNAME
,
1031 .id_table
= rtl8180_table
,
1032 .probe
= rtl8180_probe
,
1033 .remove
= __devexit_p(rtl8180_remove
),
1035 .suspend
= rtl8180_suspend
,
1036 .resume
= rtl8180_resume
,
1037 #endif /* CONFIG_PM */
1040 static int __init
rtl8180_init(void)
1042 return pci_register_driver(&rtl8180_driver
);
1045 static void __exit
rtl8180_exit(void)
1047 pci_unregister_driver(&rtl8180_driver
);
1050 module_init(rtl8180_init
);
1051 module_exit(rtl8180_exit
);