2 /* Linux device driver for RTL8180 / RTL8185 / RTL8187SE
4 * Copyright 2007 Michael Wu <flamingice@sourmilk.net>
5 * Copyright 2007,2014 Andrea Merello <andrea.merello@gmail.com>
7 * Based on the r8180 driver, which is:
8 * Copyright 2004-2005 Andrea Merello <andrea.merello@gmail.com>, et al.
10 * Thanks to Realtek for their support!
12 ************************************************************************
14 * The driver was extended to the RTL8187SE in 2014 by
15 * Andrea Merello <andrea.merello@gmail.com>
18 * - portions of rtl8187se Linux staging driver, Copyright Realtek corp.
19 * - other GPL, unpublished (until now), Linux driver code,
20 * Copyright Larry Finger <Larry.Finger@lwfinger.net>
22 * A huge thanks goes to Sara V. Nari who forgives me when I'm
23 * sitting in front of my laptop at evening, week-end, night...
25 * A special thanks goes to Antonio Cuni, who helped me with
26 * some python userspace stuff I used to debug RTL8187SE code, and who
27 * bought a laptop with an unsupported Wi-Fi card some years ago...
29 * Thanks to Larry Finger for writing some code for rtl8187se and for
32 * Thanks to Dan Carpenter for reviewing my initial patch and for his
35 * Thanks to Bernhard Schiffner for his help in testing and for his
38 ************************************************************************
40 * This program is free software; you can redistribute it and/or modify
41 * it under the terms of the GNU General Public License version 2 as
42 * published by the Free Software Foundation.
45 #include <linux/interrupt.h>
46 #include <linux/pci.h>
47 #include <linux/slab.h>
48 #include <linux/delay.h>
49 #include <linux/etherdevice.h>
50 #include <linux/eeprom_93cx6.h>
51 #include <linux/module.h>
52 #include <net/mac80211.h>
59 #include "rtl8225se.h"
61 MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
62 MODULE_AUTHOR("Andrea Merello <andrea.merello@gmail.com>");
63 MODULE_DESCRIPTION("RTL8180 / RTL8185 / RTL8187SE PCI wireless driver");
64 MODULE_LICENSE("GPL");
66 static DEFINE_PCI_DEVICE_TABLE(rtl8180_table
) = {
69 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8199) },
72 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8185) },
73 { PCI_DEVICE(PCI_VENDOR_ID_BELKIN
, 0x700f) },
74 { PCI_DEVICE(PCI_VENDOR_ID_BELKIN
, 0x701f) },
77 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8180) },
78 { PCI_DEVICE(0x1799, 0x6001) },
79 { PCI_DEVICE(0x1799, 0x6020) },
80 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x3300) },
81 { PCI_DEVICE(0x1186, 0x3301) },
82 { PCI_DEVICE(0x1432, 0x7106) },
86 MODULE_DEVICE_TABLE(pci
, rtl8180_table
);
88 static const struct ieee80211_rate rtl818x_rates
[] = {
89 { .bitrate
= 10, .hw_value
= 0, },
90 { .bitrate
= 20, .hw_value
= 1, },
91 { .bitrate
= 55, .hw_value
= 2, },
92 { .bitrate
= 110, .hw_value
= 3, },
93 { .bitrate
= 60, .hw_value
= 4, },
94 { .bitrate
= 90, .hw_value
= 5, },
95 { .bitrate
= 120, .hw_value
= 6, },
96 { .bitrate
= 180, .hw_value
= 7, },
97 { .bitrate
= 240, .hw_value
= 8, },
98 { .bitrate
= 360, .hw_value
= 9, },
99 { .bitrate
= 480, .hw_value
= 10, },
100 { .bitrate
= 540, .hw_value
= 11, },
103 static const struct ieee80211_channel rtl818x_channels
[] = {
104 { .center_freq
= 2412 },
105 { .center_freq
= 2417 },
106 { .center_freq
= 2422 },
107 { .center_freq
= 2427 },
108 { .center_freq
= 2432 },
109 { .center_freq
= 2437 },
110 { .center_freq
= 2442 },
111 { .center_freq
= 2447 },
112 { .center_freq
= 2452 },
113 { .center_freq
= 2457 },
114 { .center_freq
= 2462 },
115 { .center_freq
= 2467 },
116 { .center_freq
= 2472 },
117 { .center_freq
= 2484 },
120 /* Queues for rtl8187se card
131 * The complete map for DMA kick reg using use all queue is:
132 * static const int rtl8187se_queues_map[RTL8187SE_NR_TX_QUEUES] =
133 * {1, 6, 5, 4, 3, 2, 7};
135 * .. but.. Because for mac80211 4 queues are enough for QoS we use this
138 * BC | 7 | 4 <- currently not used yet
139 * MG | 1 | x <- Not used
140 * HI | 6 | x <- Not used
146 * Beacon queue could be used, but this is not finished yet.
148 * I thougth about using the other two queues but I decided not to do this:
150 * - I'm unsure whether the mac80211 will ever try to use more than 4 queues
153 * - I could route MGMT frames (currently sent over VO queue) to the MGMT
154 * queue but since mac80211 will do not know about it, I will probably gain
155 * some HW priority whenever the VO queue is not empty, but this gain is
156 * limited by the fact that I had to stop the mac80211 queue whenever one of
157 * the VO or MGMT queues is full, stopping also submitting of MGMT frame
160 * - I don't know how to set in the HW the contention window params for MGMT
161 * and HI-prio queues.
164 static const int rtl8187se_queues_map
[RTL8187SE_NR_TX_QUEUES
] = {5, 4, 3, 2, 7};
166 /* Queues for rtl8180/rtl8185 cards
174 * The complete map for DMA kick reg using all queue is:
175 * static const int rtl8180_queues_map[RTL8180_NR_TX_QUEUES] = {6, 5, 4, 7};
177 * .. but .. Because the mac80211 needs at least 4 queues for QoS or
178 * otherwise QoS can't be done, we use just one.
179 * Beacon queue could be used, but this is not finished yet.
183 * BC | 7 | 1 <- currently not used yet.
184 * HI | 6 | x <- not used
185 * NO | 5 | x <- not used
189 static const int rtl8180_queues_map
[RTL8180_NR_TX_QUEUES
] = {4, 7};
191 void rtl8180_write_phy(struct ieee80211_hw
*dev
, u8 addr
, u32 data
)
193 struct rtl8180_priv
*priv
= dev
->priv
;
197 buf
= (data
<< 8) | addr
;
199 rtl818x_iowrite32(priv
, (__le32 __iomem
*)&priv
->map
->PHY
[0], buf
| 0x80);
201 rtl818x_iowrite32(priv
, (__le32 __iomem
*)&priv
->map
->PHY
[0], buf
);
202 if (rtl818x_ioread8(priv
, &priv
->map
->PHY
[2]) == (data
& 0xFF))
207 static void rtl8180_handle_rx(struct ieee80211_hw
*dev
)
209 struct rtl8180_priv
*priv
= dev
->priv
;
210 struct rtl818x_rx_cmd_desc
*cmd_desc
;
211 unsigned int count
= 32;
216 void *entry
= priv
->rx_ring
+ priv
->rx_idx
* priv
->rx_ring_sz
;
217 struct sk_buff
*skb
= priv
->rx_buf
[priv
->rx_idx
];
221 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8187SE
) {
222 struct rtl8187se_rx_desc
*desc
= entry
;
224 flags
= le32_to_cpu(desc
->flags
);
225 flags2
= le32_to_cpu(desc
->flags2
);
226 tsft
= le64_to_cpu(desc
->tsft
);
228 struct rtl8180_rx_desc
*desc
= entry
;
230 flags
= le32_to_cpu(desc
->flags
);
231 flags2
= le32_to_cpu(desc
->flags2
);
232 tsft
= le64_to_cpu(desc
->tsft
);
235 if (flags
& RTL818X_RX_DESC_FLAG_OWN
)
238 if (unlikely(flags
& (RTL818X_RX_DESC_FLAG_DMA_FAIL
|
239 RTL818X_RX_DESC_FLAG_FOF
|
240 RTL818X_RX_DESC_FLAG_RX_ERR
)))
243 struct ieee80211_rx_status rx_status
= {0};
244 struct sk_buff
*new_skb
= dev_alloc_skb(MAX_RX_SIZE
);
246 if (unlikely(!new_skb
))
249 mapping
= pci_map_single(priv
->pdev
,
250 skb_tail_pointer(new_skb
),
251 MAX_RX_SIZE
, PCI_DMA_FROMDEVICE
);
253 if (pci_dma_mapping_error(priv
->pdev
, mapping
)) {
255 dev_err(&priv
->pdev
->dev
, "RX DMA map error\n");
260 pci_unmap_single(priv
->pdev
,
261 *((dma_addr_t
*)skb
->cb
),
262 MAX_RX_SIZE
, PCI_DMA_FROMDEVICE
);
263 skb_put(skb
, flags
& 0xFFF);
265 rx_status
.antenna
= (flags2
>> 15) & 1;
266 rx_status
.rate_idx
= (flags
>> 20) & 0xF;
267 agc
= (flags2
>> 17) & 0x7F;
269 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8185
) {
270 if (rx_status
.rate_idx
> 3)
271 signal
= 90 - clamp_t(u8
, agc
, 25, 90);
273 signal
= 95 - clamp_t(u8
, agc
, 30, 95);
274 } else if (priv
->chip_family
==
275 RTL818X_CHIP_FAMILY_RTL8180
) {
277 signal
= priv
->rf
->calc_rssi(agc
, sq
);
279 /* TODO: rtl8187se rssi */
282 rx_status
.signal
= signal
;
283 rx_status
.freq
= dev
->conf
.chandef
.chan
->center_freq
;
284 rx_status
.band
= dev
->conf
.chandef
.chan
->band
;
285 rx_status
.mactime
= tsft
;
286 rx_status
.flag
|= RX_FLAG_MACTIME_START
;
287 if (flags
& RTL818X_RX_DESC_FLAG_CRC32_ERR
)
288 rx_status
.flag
|= RX_FLAG_FAILED_FCS_CRC
;
290 memcpy(IEEE80211_SKB_RXCB(skb
), &rx_status
, sizeof(rx_status
));
291 ieee80211_rx_irqsafe(dev
, skb
);
294 priv
->rx_buf
[priv
->rx_idx
] = skb
;
295 *((dma_addr_t
*) skb
->cb
) = mapping
;
300 cmd_desc
->rx_buf
= cpu_to_le32(*((dma_addr_t
*)skb
->cb
));
301 cmd_desc
->flags
= cpu_to_le32(RTL818X_RX_DESC_FLAG_OWN
|
303 if (priv
->rx_idx
== 31)
305 cpu_to_le32(RTL818X_RX_DESC_FLAG_EOR
);
306 priv
->rx_idx
= (priv
->rx_idx
+ 1) % 32;
310 static void rtl8180_handle_tx(struct ieee80211_hw
*dev
, unsigned int prio
)
312 struct rtl8180_priv
*priv
= dev
->priv
;
313 struct rtl8180_tx_ring
*ring
= &priv
->tx_ring
[prio
];
315 while (skb_queue_len(&ring
->queue
)) {
316 struct rtl8180_tx_desc
*entry
= &ring
->desc
[ring
->idx
];
318 struct ieee80211_tx_info
*info
;
319 u32 flags
= le32_to_cpu(entry
->flags
);
321 if (flags
& RTL818X_TX_DESC_FLAG_OWN
)
324 ring
->idx
= (ring
->idx
+ 1) % ring
->entries
;
325 skb
= __skb_dequeue(&ring
->queue
);
326 pci_unmap_single(priv
->pdev
, le32_to_cpu(entry
->tx_buf
),
327 skb
->len
, PCI_DMA_TODEVICE
);
329 info
= IEEE80211_SKB_CB(skb
);
330 ieee80211_tx_info_clear_status(info
);
332 if (!(info
->flags
& IEEE80211_TX_CTL_NO_ACK
) &&
333 (flags
& RTL818X_TX_DESC_FLAG_TX_OK
))
334 info
->flags
|= IEEE80211_TX_STAT_ACK
;
336 info
->status
.rates
[0].count
= (flags
& 0xFF) + 1;
337 info
->status
.rates
[1].idx
= -1;
339 ieee80211_tx_status_irqsafe(dev
, skb
);
340 if (ring
->entries
- skb_queue_len(&ring
->queue
) == 2)
341 ieee80211_wake_queue(dev
, prio
);
345 static irqreturn_t
rtl8187se_interrupt(int irq
, void *dev_id
)
347 struct ieee80211_hw
*dev
= dev_id
;
348 struct rtl8180_priv
*priv
= dev
->priv
;
353 spin_lock_irqsave(&priv
->lock
, flags
);
354 /* Note: 32-bit interrupt status */
355 reg
= rtl818x_ioread32(priv
, &priv
->map
->INT_STATUS_SE
);
356 if (unlikely(reg
== 0xFFFFFFFF)) {
357 spin_unlock_irqrestore(&priv
->lock
, flags
);
361 rtl818x_iowrite32(priv
, &priv
->map
->INT_STATUS_SE
, reg
);
363 if (reg
& IMR_TIMEOUT1
)
364 rtl818x_iowrite32(priv
, &priv
->map
->INT_TIMEOUT
, 0);
366 if (reg
& (IMR_TBDOK
| IMR_TBDER
))
367 rtl8180_handle_tx(dev
, 4);
369 if (reg
& (IMR_TVODOK
| IMR_TVODER
))
370 rtl8180_handle_tx(dev
, 0);
372 if (reg
& (IMR_TVIDOK
| IMR_TVIDER
))
373 rtl8180_handle_tx(dev
, 1);
375 if (reg
& (IMR_TBEDOK
| IMR_TBEDER
))
376 rtl8180_handle_tx(dev
, 2);
378 if (reg
& (IMR_TBKDOK
| IMR_TBKDER
))
379 rtl8180_handle_tx(dev
, 3);
381 if (reg
& (IMR_ROK
| IMR_RER
| RTL818X_INT_SE_RX_DU
| IMR_RQOSOK
))
382 rtl8180_handle_rx(dev
);
383 /* The interface sometimes generates several RX DMA descriptor errors
384 * at startup. Do not report these.
386 if ((reg
& RTL818X_INT_SE_RX_DU
) && desc_err
++ > 2)
388 wiphy_err(dev
->wiphy
, "No RX DMA Descriptor avail\n");
390 spin_unlock_irqrestore(&priv
->lock
, flags
);
394 static irqreturn_t
rtl8180_interrupt(int irq
, void *dev_id
)
396 struct ieee80211_hw
*dev
= dev_id
;
397 struct rtl8180_priv
*priv
= dev
->priv
;
400 spin_lock(&priv
->lock
);
401 reg
= rtl818x_ioread16(priv
, &priv
->map
->INT_STATUS
);
402 if (unlikely(reg
== 0xFFFF)) {
403 spin_unlock(&priv
->lock
);
407 rtl818x_iowrite16(priv
, &priv
->map
->INT_STATUS
, reg
);
409 if (reg
& (RTL818X_INT_TXB_OK
| RTL818X_INT_TXB_ERR
))
410 rtl8180_handle_tx(dev
, 1);
412 if (reg
& (RTL818X_INT_TXL_OK
| RTL818X_INT_TXL_ERR
))
413 rtl8180_handle_tx(dev
, 0);
415 if (reg
& (RTL818X_INT_RX_OK
| RTL818X_INT_RX_ERR
))
416 rtl8180_handle_rx(dev
);
418 spin_unlock(&priv
->lock
);
423 static void rtl8180_tx(struct ieee80211_hw
*dev
,
424 struct ieee80211_tx_control
*control
,
427 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
428 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
429 struct rtl8180_priv
*priv
= dev
->priv
;
430 struct rtl8180_tx_ring
*ring
;
431 struct rtl8180_tx_desc
*entry
;
433 unsigned int idx
, prio
, hw_prio
;
438 __le16 rts_duration
= 0;
439 /* do arithmetic and then convert to le16 */
440 u16 frame_duration
= 0;
442 prio
= skb_get_queue_mapping(skb
);
443 ring
= &priv
->tx_ring
[prio
];
445 mapping
= pci_map_single(priv
->pdev
, skb
->data
,
446 skb
->len
, PCI_DMA_TODEVICE
);
448 if (pci_dma_mapping_error(priv
->pdev
, mapping
)) {
450 dev_err(&priv
->pdev
->dev
, "TX DMA mapping error\n");
454 tx_flags
= RTL818X_TX_DESC_FLAG_OWN
| RTL818X_TX_DESC_FLAG_FS
|
455 RTL818X_TX_DESC_FLAG_LS
|
456 (ieee80211_get_tx_rate(dev
, info
)->hw_value
<< 24) |
459 if (priv
->chip_family
!= RTL818X_CHIP_FAMILY_RTL8180
)
460 tx_flags
|= RTL818X_TX_DESC_FLAG_DMA
|
461 RTL818X_TX_DESC_FLAG_NO_ENC
;
463 rc_flags
= info
->control
.rates
[0].flags
;
464 if (rc_flags
& IEEE80211_TX_RC_USE_RTS_CTS
) {
465 tx_flags
|= RTL818X_TX_DESC_FLAG_RTS
;
466 tx_flags
|= ieee80211_get_rts_cts_rate(dev
, info
)->hw_value
<< 19;
467 } else if (rc_flags
& IEEE80211_TX_RC_USE_CTS_PROTECT
) {
468 tx_flags
|= RTL818X_TX_DESC_FLAG_CTS
;
469 tx_flags
|= ieee80211_get_rts_cts_rate(dev
, info
)->hw_value
<< 19;
472 if (rc_flags
& IEEE80211_TX_RC_USE_RTS_CTS
)
473 rts_duration
= ieee80211_rts_duration(dev
, priv
->vif
, skb
->len
,
476 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8180
) {
477 unsigned int remainder
;
479 plcp_len
= DIV_ROUND_UP(16 * (skb
->len
+ 4),
480 (ieee80211_get_tx_rate(dev
, info
)->bitrate
* 2) / 10);
481 remainder
= (16 * (skb
->len
+ 4)) %
482 ((ieee80211_get_tx_rate(dev
, info
)->bitrate
* 2) / 10);
487 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8187SE
) {
489 /* SIFS time (required by HW) is already included by
490 * ieee80211_generic_frame_duration
492 duration
= ieee80211_generic_frame_duration(dev
, priv
->vif
,
493 IEEE80211_BAND_2GHZ
, skb
->len
,
494 ieee80211_get_tx_rate(dev
, info
));
496 frame_duration
= priv
->ack_time
+ le16_to_cpu(duration
);
499 spin_lock_irqsave(&priv
->lock
, flags
);
501 if (info
->flags
& IEEE80211_TX_CTL_ASSIGN_SEQ
) {
502 if (info
->flags
& IEEE80211_TX_CTL_FIRST_FRAGMENT
)
504 hdr
->seq_ctrl
&= cpu_to_le16(IEEE80211_SCTL_FRAG
);
505 hdr
->seq_ctrl
|= cpu_to_le16(priv
->seqno
);
508 idx
= (ring
->idx
+ skb_queue_len(&ring
->queue
)) % ring
->entries
;
509 entry
= &ring
->desc
[idx
];
511 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8187SE
) {
512 entry
->frame_duration
= cpu_to_le16(frame_duration
);
513 entry
->frame_len_se
= cpu_to_le16(skb
->len
);
516 entry
->flags3
= cpu_to_le16(1<<4);
518 entry
->frame_len
= cpu_to_le32(skb
->len
);
520 entry
->rts_duration
= rts_duration
;
521 entry
->plcp_len
= cpu_to_le16(plcp_len
);
522 entry
->tx_buf
= cpu_to_le32(mapping
);
524 entry
->flags2
= info
->control
.rates
[1].idx
>= 0 ?
525 ieee80211_get_alt_retry_rate(dev
, info
, 0)->bitrate
<< 4 : 0;
526 entry
->retry_limit
= info
->control
.rates
[0].count
;
528 /* We must be sure that tx_flags is written last because the HW
529 * looks at it to check if the rest of data is valid or not
532 entry
->flags
= cpu_to_le32(tx_flags
);
533 /* We must be sure this has been written before followings HW
534 * register write, because this write will made the HW attempts
535 * to DMA the just-written data
539 __skb_queue_tail(&ring
->queue
, skb
);
540 if (ring
->entries
- skb_queue_len(&ring
->queue
) < 2)
541 ieee80211_stop_queue(dev
, prio
);
543 spin_unlock_irqrestore(&priv
->lock
, flags
);
545 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8187SE
) {
546 /* just poll: rings are stopped with TPPollStop reg */
547 hw_prio
= rtl8187se_queues_map
[prio
];
548 rtl818x_iowrite8(priv
, &priv
->map
->TX_DMA_POLLING
,
551 hw_prio
= rtl8180_queues_map
[prio
];
552 rtl818x_iowrite8(priv
, &priv
->map
->TX_DMA_POLLING
,
553 (1 << hw_prio
) | /* ring to poll */
554 (1<<1) | (1<<2));/* stopped rings */
558 static void rtl8180_set_anaparam3(struct rtl8180_priv
*priv
, u16 anaparam3
)
562 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
,
563 RTL818X_EEPROM_CMD_CONFIG
);
565 reg
= rtl818x_ioread8(priv
, &priv
->map
->CONFIG3
);
566 rtl818x_iowrite8(priv
, &priv
->map
->CONFIG3
,
567 reg
| RTL818X_CONFIG3_ANAPARAM_WRITE
);
569 rtl818x_iowrite16(priv
, &priv
->map
->ANAPARAM3
, anaparam3
);
571 rtl818x_iowrite8(priv
, &priv
->map
->CONFIG3
,
572 reg
& ~RTL818X_CONFIG3_ANAPARAM_WRITE
);
574 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
,
575 RTL818X_EEPROM_CMD_NORMAL
);
578 void rtl8180_set_anaparam2(struct rtl8180_priv
*priv
, u32 anaparam2
)
582 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
,
583 RTL818X_EEPROM_CMD_CONFIG
);
585 reg
= rtl818x_ioread8(priv
, &priv
->map
->CONFIG3
);
586 rtl818x_iowrite8(priv
, &priv
->map
->CONFIG3
,
587 reg
| RTL818X_CONFIG3_ANAPARAM_WRITE
);
589 rtl818x_iowrite32(priv
, &priv
->map
->ANAPARAM2
, anaparam2
);
591 rtl818x_iowrite8(priv
, &priv
->map
->CONFIG3
,
592 reg
& ~RTL818X_CONFIG3_ANAPARAM_WRITE
);
594 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
,
595 RTL818X_EEPROM_CMD_NORMAL
);
598 void rtl8180_set_anaparam(struct rtl8180_priv
*priv
, u32 anaparam
)
602 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
, RTL818X_EEPROM_CMD_CONFIG
);
603 reg
= rtl818x_ioread8(priv
, &priv
->map
->CONFIG3
);
604 rtl818x_iowrite8(priv
, &priv
->map
->CONFIG3
,
605 reg
| RTL818X_CONFIG3_ANAPARAM_WRITE
);
606 rtl818x_iowrite32(priv
, &priv
->map
->ANAPARAM
, anaparam
);
607 rtl818x_iowrite8(priv
, &priv
->map
->CONFIG3
,
608 reg
& ~RTL818X_CONFIG3_ANAPARAM_WRITE
);
609 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
, RTL818X_EEPROM_CMD_NORMAL
);
612 static void rtl8187se_mac_config(struct ieee80211_hw
*dev
)
614 struct rtl8180_priv
*priv
= dev
->priv
;
617 rtl818x_iowrite32(priv
, REG_ADDR4(0x1F0), 0);
618 rtl818x_ioread32(priv
, REG_ADDR4(0x1F0));
619 rtl818x_iowrite32(priv
, REG_ADDR4(0x1F4), 0);
620 rtl818x_ioread32(priv
, REG_ADDR4(0x1F4));
621 rtl818x_iowrite8(priv
, REG_ADDR1(0x1F8), 0);
622 rtl818x_ioread8(priv
, REG_ADDR1(0x1F8));
623 /* Enable DA10 TX power saving */
624 reg
= rtl818x_ioread8(priv
, &priv
->map
->PHY_PR
);
625 rtl818x_iowrite8(priv
, &priv
->map
->PHY_PR
, reg
| 0x04);
627 rtl818x_iowrite16(priv
, PI_DATA_REG
, 0x1000);
628 rtl818x_iowrite16(priv
, SI_DATA_REG
, 0x1000);
629 /* AFE - default to power ON */
630 rtl818x_iowrite16(priv
, REG_ADDR2(0x370), 0x0560);
631 rtl818x_iowrite16(priv
, REG_ADDR2(0x372), 0x0560);
632 rtl818x_iowrite16(priv
, REG_ADDR2(0x374), 0x0DA4);
633 rtl818x_iowrite16(priv
, REG_ADDR2(0x376), 0x0DA4);
634 rtl818x_iowrite16(priv
, REG_ADDR2(0x378), 0x0560);
635 rtl818x_iowrite16(priv
, REG_ADDR2(0x37A), 0x0560);
636 rtl818x_iowrite16(priv
, REG_ADDR2(0x37C), 0x00EC);
637 rtl818x_iowrite16(priv
, REG_ADDR2(0x37E), 0x00EC);
638 rtl818x_iowrite8(priv
, REG_ADDR1(0x24E), 0x01);
639 /* unknown, needed for suspend to RAM resume */
640 rtl818x_iowrite8(priv
, REG_ADDR1(0x0A), 0x72);
643 static void rtl8187se_set_antenna_config(struct ieee80211_hw
*dev
, u8 def_ant
,
646 struct rtl8180_priv
*priv
= dev
->priv
;
648 rtl8225_write_phy_cck(dev
, 0x0C, 0x09);
651 rtl818x_iowrite8(priv
, &priv
->map
->TX_ANTENNA
, 0x00);
652 rtl8225_write_phy_cck(dev
, 0x11, 0xBB);
653 rtl8225_write_phy_cck(dev
, 0x01, 0xC7);
654 rtl8225_write_phy_ofdm(dev
, 0x0D, 0x54);
655 rtl8225_write_phy_ofdm(dev
, 0x18, 0xB2);
656 } else { /* main antenna */
657 rtl818x_iowrite8(priv
, &priv
->map
->TX_ANTENNA
, 0x03);
658 rtl8225_write_phy_cck(dev
, 0x11, 0x9B);
659 rtl8225_write_phy_cck(dev
, 0x01, 0xC7);
660 rtl8225_write_phy_ofdm(dev
, 0x0D, 0x5C);
661 rtl8225_write_phy_ofdm(dev
, 0x18, 0xB2);
663 } else { /* disable antenna diversity */
665 rtl818x_iowrite8(priv
, &priv
->map
->TX_ANTENNA
, 0x00);
666 rtl8225_write_phy_cck(dev
, 0x11, 0xBB);
667 rtl8225_write_phy_cck(dev
, 0x01, 0x47);
668 rtl8225_write_phy_ofdm(dev
, 0x0D, 0x54);
669 rtl8225_write_phy_ofdm(dev
, 0x18, 0x32);
670 } else { /* main antenna */
671 rtl818x_iowrite8(priv
, &priv
->map
->TX_ANTENNA
, 0x03);
672 rtl8225_write_phy_cck(dev
, 0x11, 0x9B);
673 rtl8225_write_phy_cck(dev
, 0x01, 0x47);
674 rtl8225_write_phy_ofdm(dev
, 0x0D, 0x5C);
675 rtl8225_write_phy_ofdm(dev
, 0x18, 0x32);
678 /* priv->curr_ant = def_ant; */
681 static void rtl8180_int_enable(struct ieee80211_hw
*dev
)
683 struct rtl8180_priv
*priv
= dev
->priv
;
685 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8187SE
) {
686 rtl818x_iowrite32(priv
, &priv
->map
->IMR
, IMR_TMGDOK
|
687 IMR_TBDER
| IMR_THPDER
|
688 IMR_THPDER
| IMR_THPDOK
|
689 IMR_TVODER
| IMR_TVODOK
|
690 IMR_TVIDER
| IMR_TVIDOK
|
691 IMR_TBEDER
| IMR_TBEDOK
|
692 IMR_TBKDER
| IMR_TBKDOK
|
694 IMR_ROK
| IMR_RQOSOK
);
696 rtl818x_iowrite16(priv
, &priv
->map
->INT_MASK
, 0xFFFF);
700 static void rtl8180_int_disable(struct ieee80211_hw
*dev
)
702 struct rtl8180_priv
*priv
= dev
->priv
;
704 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8187SE
) {
705 rtl818x_iowrite32(priv
, &priv
->map
->IMR
, 0);
707 rtl818x_iowrite16(priv
, &priv
->map
->INT_MASK
, 0);
711 static void rtl8180_conf_basic_rates(struct ieee80211_hw
*dev
,
714 struct rtl8180_priv
*priv
= dev
->priv
;
719 max
= fls(rates_mask
) - 1;
720 min
= ffs(rates_mask
) - 1;
722 switch (priv
->chip_family
) {
724 case RTL818X_CHIP_FAMILY_RTL8180
:
725 /* in 8180 this is NOT a BITMAP */
726 reg
= rtl818x_ioread16(priv
, &priv
->map
->BRSR
);
729 rtl818x_iowrite16(priv
, &priv
->map
->BRSR
, reg
);
732 case RTL818X_CHIP_FAMILY_RTL8185
:
733 /* in 8185 this is a BITMAP */
734 rtl818x_iowrite16(priv
, &priv
->map
->BRSR
, rates_mask
);
735 rtl818x_iowrite8(priv
, &priv
->map
->RESP_RATE
, (max
<< 4) | min
);
738 case RTL818X_CHIP_FAMILY_RTL8187SE
:
739 /* in 8187se this is a BITMAP */
740 rtl818x_iowrite16(priv
, &priv
->map
->BRSR_8187SE
, rates_mask
);
745 static void rtl8180_config_cardbus(struct ieee80211_hw
*dev
)
747 struct rtl8180_priv
*priv
= dev
->priv
;
751 reg8
= rtl818x_ioread8(priv
, &priv
->map
->CONFIG3
);
753 rtl818x_iowrite8(priv
, &priv
->map
->CONFIG3
, reg8
);
755 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8187SE
) {
756 rtl818x_iowrite16(priv
, FEMR_SE
, 0xffff);
758 reg16
= rtl818x_ioread16(priv
, &priv
->map
->FEMR
);
759 reg16
|= (1 << 15) | (1 << 14) | (1 << 4);
760 rtl818x_iowrite16(priv
, &priv
->map
->FEMR
, reg16
);
765 static int rtl8180_init_hw(struct ieee80211_hw
*dev
)
767 struct rtl8180_priv
*priv
= dev
->priv
;
771 rtl818x_iowrite8(priv
, &priv
->map
->CMD
, 0);
772 rtl818x_ioread8(priv
, &priv
->map
->CMD
);
776 rtl8180_int_disable(dev
);
777 rtl818x_ioread8(priv
, &priv
->map
->CMD
);
779 reg
= rtl818x_ioread8(priv
, &priv
->map
->CMD
);
781 reg
|= RTL818X_CMD_RESET
;
782 rtl818x_iowrite8(priv
, &priv
->map
->CMD
, RTL818X_CMD_RESET
);
783 rtl818x_ioread8(priv
, &priv
->map
->CMD
);
786 /* check success of reset */
787 if (rtl818x_ioread8(priv
, &priv
->map
->CMD
) & RTL818X_CMD_RESET
) {
788 wiphy_err(dev
->wiphy
, "reset timeout!\n");
792 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
, RTL818X_EEPROM_CMD_LOAD
);
793 rtl818x_ioread8(priv
, &priv
->map
->CMD
);
796 if (rtl818x_ioread8(priv
, &priv
->map
->CONFIG3
) & (1 << 3)) {
797 rtl8180_config_cardbus(dev
);
800 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8187SE
)
801 rtl818x_iowrite8(priv
, &priv
->map
->MSR
, RTL818X_MSR_ENEDCA
);
803 rtl818x_iowrite8(priv
, &priv
->map
->MSR
, 0);
805 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8180
)
806 rtl8180_set_anaparam(priv
, priv
->anaparam
);
808 rtl818x_iowrite32(priv
, &priv
->map
->RDSAR
, priv
->rx_ring_dma
);
809 /* mac80211 queue have higher prio for lower index. The last queue
810 * (that mac80211 is not aware of) is reserved for beacons (and have
811 * the highest priority on the NIC)
813 if (priv
->chip_family
!= RTL818X_CHIP_FAMILY_RTL8187SE
) {
814 rtl818x_iowrite32(priv
, &priv
->map
->TBDA
,
815 priv
->tx_ring
[1].dma
);
816 rtl818x_iowrite32(priv
, &priv
->map
->TLPDA
,
817 priv
->tx_ring
[0].dma
);
819 rtl818x_iowrite32(priv
, &priv
->map
->TBDA
,
820 priv
->tx_ring
[4].dma
);
821 rtl818x_iowrite32(priv
, &priv
->map
->TVODA
,
822 priv
->tx_ring
[0].dma
);
823 rtl818x_iowrite32(priv
, &priv
->map
->TVIDA
,
824 priv
->tx_ring
[1].dma
);
825 rtl818x_iowrite32(priv
, &priv
->map
->TBEDA
,
826 priv
->tx_ring
[2].dma
);
827 rtl818x_iowrite32(priv
, &priv
->map
->TBKDA
,
828 priv
->tx_ring
[3].dma
);
831 /* TODO: necessary? specs indicate not */
832 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
, RTL818X_EEPROM_CMD_CONFIG
);
833 reg
= rtl818x_ioread8(priv
, &priv
->map
->CONFIG2
);
834 rtl818x_iowrite8(priv
, &priv
->map
->CONFIG2
, reg
& ~(1 << 3));
835 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8185
) {
836 reg
= rtl818x_ioread8(priv
, &priv
->map
->CONFIG2
);
837 rtl818x_iowrite8(priv
, &priv
->map
->CONFIG2
, reg
| (1 << 4));
839 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
, RTL818X_EEPROM_CMD_NORMAL
);
841 /* TODO: set CONFIG5 for calibrating AGC on rtl8180 + philips radio? */
843 /* TODO: turn off hw wep on rtl8180 */
845 rtl818x_iowrite32(priv
, &priv
->map
->INT_TIMEOUT
, 0);
847 if (priv
->chip_family
!= RTL818X_CHIP_FAMILY_RTL8180
) {
848 rtl818x_iowrite8(priv
, &priv
->map
->WPA_CONF
, 0);
849 rtl818x_iowrite8(priv
, &priv
->map
->RATE_FALLBACK
, 0x81);
851 rtl818x_iowrite8(priv
, &priv
->map
->SECURITY
, 0);
853 rtl818x_iowrite8(priv
, &priv
->map
->PHY_DELAY
, 0x6);
854 rtl818x_iowrite8(priv
, &priv
->map
->CARRIER_SENSE_COUNTER
, 0x4C);
857 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8185
) {
858 /* TODO: set ClkRun enable? necessary? */
859 reg
= rtl818x_ioread8(priv
, &priv
->map
->GP_ENABLE
);
860 rtl818x_iowrite8(priv
, &priv
->map
->GP_ENABLE
, reg
& ~(1 << 6));
861 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
, RTL818X_EEPROM_CMD_CONFIG
);
862 reg
= rtl818x_ioread8(priv
, &priv
->map
->CONFIG3
);
863 rtl818x_iowrite8(priv
, &priv
->map
->CONFIG3
, reg
| (1 << 2));
864 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
, RTL818X_EEPROM_CMD_NORMAL
);
867 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8187SE
) {
869 /* the set auto rate fallback bitmask from 1M to 54 Mb/s */
870 rtl818x_iowrite16(priv
, ARFR
, 0xFFF);
871 rtl818x_ioread16(priv
, ARFR
);
873 /* stop unused queus (no dma alloc) */
874 rtl818x_iowrite8(priv
, &priv
->map
->TPPOLL_STOP
,
875 RTL818x_TPPOLL_STOP_MG
| RTL818x_TPPOLL_STOP_HI
);
877 rtl818x_iowrite8(priv
, &priv
->map
->ACM_CONTROL
, 0x00);
878 rtl818x_iowrite16(priv
, &priv
->map
->TID_AC_MAP
, 0xFA50);
880 rtl818x_iowrite16(priv
, &priv
->map
->INT_MIG
, 0);
882 /* some black magic here.. */
883 rtl8187se_mac_config(dev
);
885 rtl818x_iowrite16(priv
, RFSW_CTRL
, 0x569A);
886 rtl818x_ioread16(priv
, RFSW_CTRL
);
888 rtl8180_set_anaparam(priv
, RTL8225SE_ANAPARAM_ON
);
889 rtl8180_set_anaparam2(priv
, RTL8225SE_ANAPARAM2_ON
);
890 rtl8180_set_anaparam3(priv
, RTL8225SE_ANAPARAM3
);
893 rtl818x_iowrite8(priv
, &priv
->map
->CONFIG5
,
894 rtl818x_ioread8(priv
, &priv
->map
->CONFIG5
) & 0x7F);
896 /*probably this switch led on */
897 rtl818x_iowrite8(priv
, &priv
->map
->PGSELECT
,
898 rtl818x_ioread8(priv
, &priv
->map
->PGSELECT
) | 0x08);
900 rtl818x_iowrite16(priv
, &priv
->map
->RFPinsOutput
, 0x0480);
901 rtl818x_iowrite16(priv
, &priv
->map
->RFPinsEnable
, 0x1BFF);
902 rtl818x_iowrite16(priv
, &priv
->map
->RFPinsSelect
, 0x2488);
904 rtl818x_iowrite32(priv
, &priv
->map
->RF_TIMING
, 0x4003);
906 /* the reference code mac hardcode table write
907 * this reg by doing byte-wide accesses.
908 * It does it just for lowest and highest byte..
910 reg32
= rtl818x_ioread32(priv
, &priv
->map
->RF_PARA
);
913 rtl818x_iowrite32(priv
, &priv
->map
->RF_PARA
, reg32
);
918 /* default basic rates are 1,2 Mbps for rtl8180. 1,2,6,9,12,18,24 Mbps
919 * otherwise. bitmask 0x3 and 0x01f3 respectively.
920 * NOTE: currenty rtl8225 RF code changes basic rates, so we need to do
921 * this after rf init.
922 * TODO: try to find out whether RF code really needs to do this..
924 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8180
)
925 rtl8180_conf_basic_rates(dev
, 0x3);
927 rtl8180_conf_basic_rates(dev
, 0x1f3);
929 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8187SE
)
930 rtl8187se_set_antenna_config(dev
,
931 priv
->antenna_diversity_default
,
932 priv
->antenna_diversity_en
);
936 static int rtl8180_init_rx_ring(struct ieee80211_hw
*dev
)
938 struct rtl8180_priv
*priv
= dev
->priv
;
939 struct rtl818x_rx_cmd_desc
*entry
;
942 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8187SE
)
943 priv
->rx_ring_sz
= sizeof(struct rtl8187se_rx_desc
);
945 priv
->rx_ring_sz
= sizeof(struct rtl8180_rx_desc
);
947 priv
->rx_ring
= pci_alloc_consistent(priv
->pdev
,
948 priv
->rx_ring_sz
* 32,
951 if (!priv
->rx_ring
|| (unsigned long)priv
->rx_ring
& 0xFF) {
952 wiphy_err(dev
->wiphy
, "Cannot allocate RX ring\n");
956 memset(priv
->rx_ring
, 0, priv
->rx_ring_sz
* 32);
959 for (i
= 0; i
< 32; i
++) {
960 struct sk_buff
*skb
= dev_alloc_skb(MAX_RX_SIZE
);
962 entry
= priv
->rx_ring
+ priv
->rx_ring_sz
*i
;
964 wiphy_err(dev
->wiphy
, "Cannot allocate RX skb\n");
967 priv
->rx_buf
[i
] = skb
;
968 mapping
= (dma_addr_t
*)skb
->cb
;
969 *mapping
= pci_map_single(priv
->pdev
, skb_tail_pointer(skb
),
970 MAX_RX_SIZE
, PCI_DMA_FROMDEVICE
);
972 if (pci_dma_mapping_error(priv
->pdev
, *mapping
)) {
974 wiphy_err(dev
->wiphy
, "Cannot map DMA for RX skb\n");
978 entry
->rx_buf
= cpu_to_le32(*mapping
);
979 entry
->flags
= cpu_to_le32(RTL818X_RX_DESC_FLAG_OWN
|
982 entry
->flags
|= cpu_to_le32(RTL818X_RX_DESC_FLAG_EOR
);
986 static void rtl8180_free_rx_ring(struct ieee80211_hw
*dev
)
988 struct rtl8180_priv
*priv
= dev
->priv
;
991 for (i
= 0; i
< 32; i
++) {
992 struct sk_buff
*skb
= priv
->rx_buf
[i
];
996 pci_unmap_single(priv
->pdev
,
997 *((dma_addr_t
*)skb
->cb
),
998 MAX_RX_SIZE
, PCI_DMA_FROMDEVICE
);
1002 pci_free_consistent(priv
->pdev
, priv
->rx_ring_sz
* 32,
1003 priv
->rx_ring
, priv
->rx_ring_dma
);
1004 priv
->rx_ring
= NULL
;
1007 static int rtl8180_init_tx_ring(struct ieee80211_hw
*dev
,
1008 unsigned int prio
, unsigned int entries
)
1010 struct rtl8180_priv
*priv
= dev
->priv
;
1011 struct rtl8180_tx_desc
*ring
;
1015 ring
= pci_alloc_consistent(priv
->pdev
, sizeof(*ring
) * entries
, &dma
);
1016 if (!ring
|| (unsigned long)ring
& 0xFF) {
1017 wiphy_err(dev
->wiphy
, "Cannot allocate TX ring (prio = %d)\n",
1022 memset(ring
, 0, sizeof(*ring
)*entries
);
1023 priv
->tx_ring
[prio
].desc
= ring
;
1024 priv
->tx_ring
[prio
].dma
= dma
;
1025 priv
->tx_ring
[prio
].idx
= 0;
1026 priv
->tx_ring
[prio
].entries
= entries
;
1027 skb_queue_head_init(&priv
->tx_ring
[prio
].queue
);
1029 for (i
= 0; i
< entries
; i
++)
1030 ring
[i
].next_tx_desc
=
1031 cpu_to_le32((u32
)dma
+ ((i
+ 1) % entries
) * sizeof(*ring
));
1036 static void rtl8180_free_tx_ring(struct ieee80211_hw
*dev
, unsigned int prio
)
1038 struct rtl8180_priv
*priv
= dev
->priv
;
1039 struct rtl8180_tx_ring
*ring
= &priv
->tx_ring
[prio
];
1041 while (skb_queue_len(&ring
->queue
)) {
1042 struct rtl8180_tx_desc
*entry
= &ring
->desc
[ring
->idx
];
1043 struct sk_buff
*skb
= __skb_dequeue(&ring
->queue
);
1045 pci_unmap_single(priv
->pdev
, le32_to_cpu(entry
->tx_buf
),
1046 skb
->len
, PCI_DMA_TODEVICE
);
1048 ring
->idx
= (ring
->idx
+ 1) % ring
->entries
;
1051 pci_free_consistent(priv
->pdev
, sizeof(*ring
->desc
)*ring
->entries
,
1052 ring
->desc
, ring
->dma
);
1056 static int rtl8180_start(struct ieee80211_hw
*dev
)
1058 struct rtl8180_priv
*priv
= dev
->priv
;
1062 ret
= rtl8180_init_rx_ring(dev
);
1066 for (i
= 0; i
< (dev
->queues
+ 1); i
++)
1067 if ((ret
= rtl8180_init_tx_ring(dev
, i
, 16)))
1068 goto err_free_rings
;
1070 ret
= rtl8180_init_hw(dev
);
1072 goto err_free_rings
;
1074 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8187SE
) {
1075 ret
= request_irq(priv
->pdev
->irq
, rtl8187se_interrupt
,
1076 IRQF_SHARED
, KBUILD_MODNAME
, dev
);
1078 ret
= request_irq(priv
->pdev
->irq
, rtl8180_interrupt
,
1079 IRQF_SHARED
, KBUILD_MODNAME
, dev
);
1083 wiphy_err(dev
->wiphy
, "failed to register IRQ handler\n");
1084 goto err_free_rings
;
1087 rtl8180_int_enable(dev
);
1089 /* in rtl8187se at MAR regs offset there is the management
1090 * TX descriptor DMA addres..
1092 if (priv
->chip_family
!= RTL818X_CHIP_FAMILY_RTL8187SE
) {
1093 rtl818x_iowrite32(priv
, &priv
->map
->MAR
[0], ~0);
1094 rtl818x_iowrite32(priv
, &priv
->map
->MAR
[1], ~0);
1097 reg
= RTL818X_RX_CONF_ONLYERLPKT
|
1098 RTL818X_RX_CONF_RX_AUTORESETPHY
|
1099 RTL818X_RX_CONF_MGMT
|
1100 RTL818X_RX_CONF_DATA
|
1101 (7 << 8 /* MAX RX DMA */) |
1102 RTL818X_RX_CONF_BROADCAST
|
1103 RTL818X_RX_CONF_NICMAC
;
1105 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8185
)
1106 reg
|= RTL818X_RX_CONF_CSDM1
| RTL818X_RX_CONF_CSDM2
;
1107 else if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8180
) {
1108 reg
|= (priv
->rfparam
& RF_PARAM_CARRIERSENSE1
)
1109 ? RTL818X_RX_CONF_CSDM1
: 0;
1110 reg
|= (priv
->rfparam
& RF_PARAM_CARRIERSENSE2
)
1111 ? RTL818X_RX_CONF_CSDM2
: 0;
1113 reg
&= ~(RTL818X_RX_CONF_CSDM1
| RTL818X_RX_CONF_CSDM2
);
1116 priv
->rx_conf
= reg
;
1117 rtl818x_iowrite32(priv
, &priv
->map
->RX_CONF
, reg
);
1119 if (priv
->chip_family
!= RTL818X_CHIP_FAMILY_RTL8180
) {
1120 reg
= rtl818x_ioread8(priv
, &priv
->map
->CW_CONF
);
1122 /* CW is not on per-packet basis.
1123 * in rtl8185 the CW_VALUE reg is used.
1124 * in rtl8187se the AC param regs are used.
1126 reg
&= ~RTL818X_CW_CONF_PERPACKET_CW
;
1127 /* retry limit IS on per-packet basis.
1128 * the short and long retry limit in TX_CONF
1131 reg
|= RTL818X_CW_CONF_PERPACKET_RETRY
;
1132 rtl818x_iowrite8(priv
, &priv
->map
->CW_CONF
, reg
);
1134 reg
= rtl818x_ioread8(priv
, &priv
->map
->TX_AGC_CTL
);
1135 /* TX antenna and TX gain are not on per-packet basis.
1136 * TX Antenna is selected by ANTSEL reg (RX in BB regs).
1137 * TX gain is selected with CCK_TX_AGC and OFDM_TX_AGC regs
1139 reg
&= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN
;
1140 reg
&= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL
;
1141 reg
|= RTL818X_TX_AGC_CTL_FEEDBACK_ANT
;
1142 rtl818x_iowrite8(priv
, &priv
->map
->TX_AGC_CTL
, reg
);
1144 /* disable early TX */
1145 rtl818x_iowrite8(priv
, (u8 __iomem
*)priv
->map
+ 0xec, 0x3f);
1148 reg
= rtl818x_ioread32(priv
, &priv
->map
->TX_CONF
);
1149 reg
|= (6 << 21 /* MAX TX DMA */) |
1150 RTL818X_TX_CONF_NO_ICV
;
1152 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8187SE
)
1153 reg
|= 1<<30; /* "duration procedure mode" */
1155 if (priv
->chip_family
!= RTL818X_CHIP_FAMILY_RTL8180
)
1156 reg
&= ~RTL818X_TX_CONF_PROBE_DTS
;
1158 reg
&= ~RTL818X_TX_CONF_HW_SEQNUM
;
1160 reg
&= ~RTL818X_TX_CONF_DISCW
;
1162 /* different meaning, same value on both rtl8185 and rtl8180 */
1163 reg
&= ~RTL818X_TX_CONF_SAT_HWPLCP
;
1165 rtl818x_iowrite32(priv
, &priv
->map
->TX_CONF
, reg
);
1167 reg
= rtl818x_ioread8(priv
, &priv
->map
->CMD
);
1168 reg
|= RTL818X_CMD_RX_ENABLE
;
1169 reg
|= RTL818X_CMD_TX_ENABLE
;
1170 rtl818x_iowrite8(priv
, &priv
->map
->CMD
, reg
);
1175 rtl8180_free_rx_ring(dev
);
1176 for (i
= 0; i
< (dev
->queues
+ 1); i
++)
1177 if (priv
->tx_ring
[i
].desc
)
1178 rtl8180_free_tx_ring(dev
, i
);
1183 static void rtl8180_stop(struct ieee80211_hw
*dev
)
1185 struct rtl8180_priv
*priv
= dev
->priv
;
1189 rtl8180_int_disable(dev
);
1191 reg
= rtl818x_ioread8(priv
, &priv
->map
->CMD
);
1192 reg
&= ~RTL818X_CMD_TX_ENABLE
;
1193 reg
&= ~RTL818X_CMD_RX_ENABLE
;
1194 rtl818x_iowrite8(priv
, &priv
->map
->CMD
, reg
);
1196 priv
->rf
->stop(dev
);
1198 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
, RTL818X_EEPROM_CMD_CONFIG
);
1199 reg
= rtl818x_ioread8(priv
, &priv
->map
->CONFIG4
);
1200 rtl818x_iowrite8(priv
, &priv
->map
->CONFIG4
, reg
| RTL818X_CONFIG4_VCOOFF
);
1201 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
, RTL818X_EEPROM_CMD_NORMAL
);
1203 free_irq(priv
->pdev
->irq
, dev
);
1205 rtl8180_free_rx_ring(dev
);
1206 for (i
= 0; i
< (dev
->queues
+ 1); i
++)
1207 rtl8180_free_tx_ring(dev
, i
);
1210 static u64
rtl8180_get_tsf(struct ieee80211_hw
*dev
,
1211 struct ieee80211_vif
*vif
)
1213 struct rtl8180_priv
*priv
= dev
->priv
;
1215 return rtl818x_ioread32(priv
, &priv
->map
->TSFT
[0]) |
1216 (u64
)(rtl818x_ioread32(priv
, &priv
->map
->TSFT
[1])) << 32;
1219 static void rtl8180_beacon_work(struct work_struct
*work
)
1221 struct rtl8180_vif
*vif_priv
=
1222 container_of(work
, struct rtl8180_vif
, beacon_work
.work
);
1223 struct ieee80211_vif
*vif
=
1224 container_of((void *)vif_priv
, struct ieee80211_vif
, drv_priv
);
1225 struct ieee80211_hw
*dev
= vif_priv
->dev
;
1226 struct ieee80211_mgmt
*mgmt
;
1227 struct sk_buff
*skb
;
1229 /* don't overflow the tx ring */
1230 if (ieee80211_queue_stopped(dev
, 0))
1233 /* grab a fresh beacon */
1234 skb
= ieee80211_beacon_get(dev
, vif
);
1239 * update beacon timestamp w/ TSF value
1240 * TODO: make hardware update beacon timestamp
1242 mgmt
= (struct ieee80211_mgmt
*)skb
->data
;
1243 mgmt
->u
.beacon
.timestamp
= cpu_to_le64(rtl8180_get_tsf(dev
, vif
));
1245 /* TODO: use actual beacon queue */
1246 skb_set_queue_mapping(skb
, 0);
1248 rtl8180_tx(dev
, NULL
, skb
);
1252 * schedule next beacon
1253 * TODO: use hardware support for beacon timing
1255 schedule_delayed_work(&vif_priv
->beacon_work
,
1256 usecs_to_jiffies(1024 * vif
->bss_conf
.beacon_int
));
1259 static int rtl8180_add_interface(struct ieee80211_hw
*dev
,
1260 struct ieee80211_vif
*vif
)
1262 struct rtl8180_priv
*priv
= dev
->priv
;
1263 struct rtl8180_vif
*vif_priv
;
1266 * We only support one active interface at a time.
1271 switch (vif
->type
) {
1272 case NL80211_IFTYPE_STATION
:
1273 case NL80211_IFTYPE_ADHOC
:
1281 /* Initialize driver private area */
1282 vif_priv
= (struct rtl8180_vif
*)&vif
->drv_priv
;
1283 vif_priv
->dev
= dev
;
1284 INIT_DELAYED_WORK(&vif_priv
->beacon_work
, rtl8180_beacon_work
);
1285 vif_priv
->enable_beacon
= false;
1287 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
, RTL818X_EEPROM_CMD_CONFIG
);
1288 rtl818x_iowrite32(priv
, (__le32 __iomem
*)&priv
->map
->MAC
[0],
1289 le32_to_cpu(*(__le32
*)vif
->addr
));
1290 rtl818x_iowrite16(priv
, (__le16 __iomem
*)&priv
->map
->MAC
[4],
1291 le16_to_cpu(*(__le16
*)(vif
->addr
+ 4)));
1292 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
, RTL818X_EEPROM_CMD_NORMAL
);
1297 static void rtl8180_remove_interface(struct ieee80211_hw
*dev
,
1298 struct ieee80211_vif
*vif
)
1300 struct rtl8180_priv
*priv
= dev
->priv
;
1304 static int rtl8180_config(struct ieee80211_hw
*dev
, u32 changed
)
1306 struct rtl8180_priv
*priv
= dev
->priv
;
1307 struct ieee80211_conf
*conf
= &dev
->conf
;
1309 priv
->rf
->set_chan(dev
, conf
);
1314 static void rtl8187se_conf_ac_parm(struct ieee80211_hw
*dev
, u8 queue
)
1316 const struct ieee80211_tx_queue_params
*params
;
1317 struct rtl8180_priv
*priv
= dev
->priv
;
1326 params
= &priv
->queue_param
[queue
];
1328 cw_min
= fls(params
->cw_min
);
1329 cw_max
= fls(params
->cw_max
);
1331 aifs
= 10 + params
->aifs
* priv
->slot_time
;
1333 /* TODO: check if txop HW is in us (mult by 32) */
1334 txop
= params
->txop
;
1336 ac_param
= txop
<< AC_PARAM_TXOP_LIMIT_SHIFT
|
1337 cw_max
<< AC_PARAM_ECW_MAX_SHIFT
|
1338 cw_min
<< AC_PARAM_ECW_MIN_SHIFT
|
1339 aifs
<< AC_PARAM_AIFS_SHIFT
;
1342 case IEEE80211_AC_BK
:
1343 rtl818x_iowrite32(priv
, &priv
->map
->AC_BK_PARAM
, ac_param
);
1345 case IEEE80211_AC_BE
:
1346 rtl818x_iowrite32(priv
, &priv
->map
->AC_BE_PARAM
, ac_param
);
1348 case IEEE80211_AC_VI
:
1349 rtl818x_iowrite32(priv
, &priv
->map
->AC_VI_PARAM
, ac_param
);
1351 case IEEE80211_AC_VO
:
1352 rtl818x_iowrite32(priv
, &priv
->map
->AC_VO_PARAM
, ac_param
);
1357 static int rtl8180_conf_tx(struct ieee80211_hw
*dev
,
1358 struct ieee80211_vif
*vif
, u16 queue
,
1359 const struct ieee80211_tx_queue_params
*params
)
1361 struct rtl8180_priv
*priv
= dev
->priv
;
1364 /* nothing to do ? */
1365 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8180
)
1368 cw_min
= fls(params
->cw_min
);
1369 cw_max
= fls(params
->cw_max
);
1371 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8187SE
) {
1372 priv
->queue_param
[queue
] = *params
;
1373 rtl8187se_conf_ac_parm(dev
, queue
);
1375 rtl818x_iowrite8(priv
, &priv
->map
->CW_VAL
,
1376 (cw_max
<< 4) | cw_min
);
1380 static void rtl8180_conf_erp(struct ieee80211_hw
*dev
,
1381 struct ieee80211_bss_conf
*info
)
1383 struct rtl8180_priv
*priv
= dev
->priv
;
1388 /* TODO: should we do something ? */
1389 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8180
)
1392 /* I _hope_ this means 10uS for the HW.
1393 * In reference code it is 0x22 for
1394 * both rtl8187L and rtl8187SE
1398 if (info
->use_short_slot
)
1399 priv
->slot_time
= 9;
1401 priv
->slot_time
= 20;
1403 /* 10 is SIFS time in uS */
1404 difs
= 10 + 2 * priv
->slot_time
;
1405 eifs
= 10 + difs
+ priv
->ack_time
;
1407 /* HW should use 4uS units for EIFS (I'm sure for rtl8185)*/
1408 hw_eifs
= DIV_ROUND_UP(eifs
, 4);
1411 rtl818x_iowrite8(priv
, &priv
->map
->SLOT
, priv
->slot_time
);
1412 rtl818x_iowrite8(priv
, &priv
->map
->SIFS
, sifs
);
1413 rtl818x_iowrite8(priv
, &priv
->map
->DIFS
, difs
);
1415 /* from reference code. set ack timeout reg = eifs reg */
1416 rtl818x_iowrite8(priv
, &priv
->map
->CARRIER_SENSE_COUNTER
, hw_eifs
);
1418 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8187SE
)
1419 rtl818x_iowrite8(priv
, &priv
->map
->EIFS_8187SE
, hw_eifs
);
1420 else if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8185
) {
1421 /* rtl8187/rtl8185 HW bug. After EIFS is elapsed,
1422 * the HW still wait for DIFS.
1423 * HW uses 4uS units for EIFS.
1425 hw_eifs
= DIV_ROUND_UP(eifs
- difs
, 4);
1427 rtl818x_iowrite8(priv
, &priv
->map
->EIFS
, hw_eifs
);
1431 static void rtl8180_bss_info_changed(struct ieee80211_hw
*dev
,
1432 struct ieee80211_vif
*vif
,
1433 struct ieee80211_bss_conf
*info
,
1436 struct rtl8180_priv
*priv
= dev
->priv
;
1437 struct rtl8180_vif
*vif_priv
;
1441 vif_priv
= (struct rtl8180_vif
*)&vif
->drv_priv
;
1443 if (changed
& BSS_CHANGED_BSSID
) {
1444 for (i
= 0; i
< ETH_ALEN
; i
++)
1445 rtl818x_iowrite8(priv
, &priv
->map
->BSSID
[i
],
1448 if (is_valid_ether_addr(info
->bssid
)) {
1449 if (vif
->type
== NL80211_IFTYPE_ADHOC
)
1450 reg
= RTL818X_MSR_ADHOC
;
1452 reg
= RTL818X_MSR_INFRA
;
1454 reg
= RTL818X_MSR_NO_LINK
;
1456 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8187SE
)
1457 reg
|= RTL818X_MSR_ENEDCA
;
1459 rtl818x_iowrite8(priv
, &priv
->map
->MSR
, reg
);
1462 if (changed
& BSS_CHANGED_BASIC_RATES
)
1463 rtl8180_conf_basic_rates(dev
, info
->basic_rates
);
1465 if (changed
& (BSS_CHANGED_ERP_SLOT
| BSS_CHANGED_ERP_PREAMBLE
)) {
1467 /* when preamble changes, acktime duration changes, and erp must
1468 * be recalculated. ACK time is calculated at lowest rate.
1469 * Since mac80211 include SIFS time we remove it (-10)
1472 le16_to_cpu(ieee80211_generic_frame_duration(dev
,
1474 IEEE80211_BAND_2GHZ
, 10,
1475 &priv
->rates
[0])) - 10;
1477 rtl8180_conf_erp(dev
, info
);
1479 /* mac80211 supplies aifs_n to driver and calls
1480 * conf_tx callback whether aifs_n changes, NOT
1481 * when aifs changes.
1482 * Aifs should be recalculated if slot changes.
1484 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8187SE
) {
1485 for (i
= 0; i
< 4; i
++)
1486 rtl8187se_conf_ac_parm(dev
, i
);
1490 if (changed
& BSS_CHANGED_BEACON_ENABLED
)
1491 vif_priv
->enable_beacon
= info
->enable_beacon
;
1493 if (changed
& (BSS_CHANGED_BEACON_ENABLED
| BSS_CHANGED_BEACON
)) {
1494 cancel_delayed_work_sync(&vif_priv
->beacon_work
);
1495 if (vif_priv
->enable_beacon
)
1496 schedule_work(&vif_priv
->beacon_work
.work
);
1500 static u64
rtl8180_prepare_multicast(struct ieee80211_hw
*dev
,
1501 struct netdev_hw_addr_list
*mc_list
)
1503 return netdev_hw_addr_list_count(mc_list
);
1506 static void rtl8180_configure_filter(struct ieee80211_hw
*dev
,
1507 unsigned int changed_flags
,
1508 unsigned int *total_flags
,
1511 struct rtl8180_priv
*priv
= dev
->priv
;
1513 if (changed_flags
& FIF_FCSFAIL
)
1514 priv
->rx_conf
^= RTL818X_RX_CONF_FCS
;
1515 if (changed_flags
& FIF_CONTROL
)
1516 priv
->rx_conf
^= RTL818X_RX_CONF_CTRL
;
1517 if (changed_flags
& FIF_OTHER_BSS
)
1518 priv
->rx_conf
^= RTL818X_RX_CONF_MONITOR
;
1519 if (*total_flags
& FIF_ALLMULTI
|| multicast
> 0)
1520 priv
->rx_conf
|= RTL818X_RX_CONF_MULTICAST
;
1522 priv
->rx_conf
&= ~RTL818X_RX_CONF_MULTICAST
;
1526 if (priv
->rx_conf
& RTL818X_RX_CONF_FCS
)
1527 *total_flags
|= FIF_FCSFAIL
;
1528 if (priv
->rx_conf
& RTL818X_RX_CONF_CTRL
)
1529 *total_flags
|= FIF_CONTROL
;
1530 if (priv
->rx_conf
& RTL818X_RX_CONF_MONITOR
)
1531 *total_flags
|= FIF_OTHER_BSS
;
1532 if (priv
->rx_conf
& RTL818X_RX_CONF_MULTICAST
)
1533 *total_flags
|= FIF_ALLMULTI
;
1535 rtl818x_iowrite32(priv
, &priv
->map
->RX_CONF
, priv
->rx_conf
);
1538 static const struct ieee80211_ops rtl8180_ops
= {
1540 .start
= rtl8180_start
,
1541 .stop
= rtl8180_stop
,
1542 .add_interface
= rtl8180_add_interface
,
1543 .remove_interface
= rtl8180_remove_interface
,
1544 .config
= rtl8180_config
,
1545 .bss_info_changed
= rtl8180_bss_info_changed
,
1546 .conf_tx
= rtl8180_conf_tx
,
1547 .prepare_multicast
= rtl8180_prepare_multicast
,
1548 .configure_filter
= rtl8180_configure_filter
,
1549 .get_tsf
= rtl8180_get_tsf
,
1552 static void rtl8180_eeprom_register_read(struct eeprom_93cx6
*eeprom
)
1554 struct rtl8180_priv
*priv
= eeprom
->data
;
1555 u8 reg
= rtl818x_ioread8(priv
, &priv
->map
->EEPROM_CMD
);
1557 eeprom
->reg_data_in
= reg
& RTL818X_EEPROM_CMD_WRITE
;
1558 eeprom
->reg_data_out
= reg
& RTL818X_EEPROM_CMD_READ
;
1559 eeprom
->reg_data_clock
= reg
& RTL818X_EEPROM_CMD_CK
;
1560 eeprom
->reg_chip_select
= reg
& RTL818X_EEPROM_CMD_CS
;
1563 static void rtl8180_eeprom_register_write(struct eeprom_93cx6
*eeprom
)
1565 struct rtl8180_priv
*priv
= eeprom
->data
;
1568 if (eeprom
->reg_data_in
)
1569 reg
|= RTL818X_EEPROM_CMD_WRITE
;
1570 if (eeprom
->reg_data_out
)
1571 reg
|= RTL818X_EEPROM_CMD_READ
;
1572 if (eeprom
->reg_data_clock
)
1573 reg
|= RTL818X_EEPROM_CMD_CK
;
1574 if (eeprom
->reg_chip_select
)
1575 reg
|= RTL818X_EEPROM_CMD_CS
;
1577 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
, reg
);
1578 rtl818x_ioread8(priv
, &priv
->map
->EEPROM_CMD
);
1582 static void rtl8180_eeprom_read(struct rtl8180_priv
*priv
)
1584 struct eeprom_93cx6 eeprom
;
1585 int eeprom_cck_table_adr
;
1590 eeprom
.register_read
= rtl8180_eeprom_register_read
;
1591 eeprom
.register_write
= rtl8180_eeprom_register_write
;
1592 if (rtl818x_ioread32(priv
, &priv
->map
->RX_CONF
) & (1 << 6))
1593 eeprom
.width
= PCI_EEPROM_WIDTH_93C66
;
1595 eeprom
.width
= PCI_EEPROM_WIDTH_93C46
;
1597 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
,
1598 RTL818X_EEPROM_CMD_PROGRAM
);
1599 rtl818x_ioread8(priv
, &priv
->map
->EEPROM_CMD
);
1602 eeprom_93cx6_read(&eeprom
, 0x06, &eeprom_val
);
1604 priv
->rf_type
= eeprom_val
;
1606 eeprom_93cx6_read(&eeprom
, 0x17, &eeprom_val
);
1607 priv
->csthreshold
= eeprom_val
>> 8;
1609 eeprom_93cx6_multiread(&eeprom
, 0x7, (__le16
*)priv
->mac_addr
, 3);
1611 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8187SE
)
1612 eeprom_cck_table_adr
= 0x30;
1614 eeprom_cck_table_adr
= 0x10;
1617 for (i
= 0; i
< 14; i
+= 2) {
1619 eeprom_93cx6_read(&eeprom
, eeprom_cck_table_adr
+ (i
>> 1),
1621 priv
->channels
[i
].hw_value
= txpwr
& 0xFF;
1622 priv
->channels
[i
+ 1].hw_value
= txpwr
>> 8;
1626 if (priv
->chip_family
!= RTL818X_CHIP_FAMILY_RTL8180
) {
1627 for (i
= 0; i
< 14; i
+= 2) {
1629 eeprom_93cx6_read(&eeprom
, 0x20 + (i
>> 1), &txpwr
);
1630 priv
->channels
[i
].hw_value
|= (txpwr
& 0xFF) << 8;
1631 priv
->channels
[i
+ 1].hw_value
|= txpwr
& 0xFF00;
1635 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8180
) {
1637 eeprom_93cx6_multiread(&eeprom
, 0xD, (__le16
*)&anaparam
, 2);
1638 priv
->anaparam
= le32_to_cpu(anaparam
);
1639 eeprom_93cx6_read(&eeprom
, 0x19, &priv
->rfparam
);
1642 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8187SE
) {
1643 eeprom_93cx6_read(&eeprom
, 0x3F, &eeprom_val
);
1644 priv
->antenna_diversity_en
= !!(eeprom_val
& 0x100);
1645 priv
->antenna_diversity_default
= (eeprom_val
& 0xC00) == 0x400;
1647 eeprom_93cx6_read(&eeprom
, 0x7C, &eeprom_val
);
1648 priv
->xtal_out
= eeprom_val
& 0xF;
1649 priv
->xtal_in
= (eeprom_val
& 0xF0) >> 4;
1650 priv
->xtal_cal
= !!(eeprom_val
& 0x1000);
1651 priv
->thermal_meter_val
= (eeprom_val
& 0xF00) >> 8;
1652 priv
->thermal_meter_en
= !!(eeprom_val
& 0x2000);
1655 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
,
1656 RTL818X_EEPROM_CMD_NORMAL
);
1659 static int rtl8180_probe(struct pci_dev
*pdev
,
1660 const struct pci_device_id
*id
)
1662 struct ieee80211_hw
*dev
;
1663 struct rtl8180_priv
*priv
;
1664 unsigned long mem_addr
, mem_len
;
1665 unsigned int io_addr
, io_len
;
1667 const char *chip_name
, *rf_name
= NULL
;
1670 err
= pci_enable_device(pdev
);
1672 printk(KERN_ERR
"%s (rtl8180): Cannot enable new PCI device\n",
1677 err
= pci_request_regions(pdev
, KBUILD_MODNAME
);
1679 printk(KERN_ERR
"%s (rtl8180): Cannot obtain PCI resources\n",
1684 io_addr
= pci_resource_start(pdev
, 0);
1685 io_len
= pci_resource_len(pdev
, 0);
1686 mem_addr
= pci_resource_start(pdev
, 1);
1687 mem_len
= pci_resource_len(pdev
, 1);
1689 if (mem_len
< sizeof(struct rtl818x_csr
) ||
1690 io_len
< sizeof(struct rtl818x_csr
)) {
1691 printk(KERN_ERR
"%s (rtl8180): Too short PCI resources\n",
1697 if ((err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32))) ||
1698 (err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(32)))) {
1699 printk(KERN_ERR
"%s (rtl8180): No suitable DMA available\n",
1704 pci_set_master(pdev
);
1706 dev
= ieee80211_alloc_hw(sizeof(*priv
), &rtl8180_ops
);
1708 printk(KERN_ERR
"%s (rtl8180): ieee80211 alloc failed\n",
1718 SET_IEEE80211_DEV(dev
, &pdev
->dev
);
1719 pci_set_drvdata(pdev
, dev
);
1721 priv
->map
= pci_iomap(pdev
, 1, mem_len
);
1723 priv
->map
= pci_iomap(pdev
, 0, io_len
);
1726 printk(KERN_ERR
"%s (rtl8180): Cannot map device memory\n",
1731 BUILD_BUG_ON(sizeof(priv
->channels
) != sizeof(rtl818x_channels
));
1732 BUILD_BUG_ON(sizeof(priv
->rates
) != sizeof(rtl818x_rates
));
1734 memcpy(priv
->channels
, rtl818x_channels
, sizeof(rtl818x_channels
));
1735 memcpy(priv
->rates
, rtl818x_rates
, sizeof(rtl818x_rates
));
1737 priv
->band
.band
= IEEE80211_BAND_2GHZ
;
1738 priv
->band
.channels
= priv
->channels
;
1739 priv
->band
.n_channels
= ARRAY_SIZE(rtl818x_channels
);
1740 priv
->band
.bitrates
= priv
->rates
;
1741 priv
->band
.n_bitrates
= 4;
1742 dev
->wiphy
->bands
[IEEE80211_BAND_2GHZ
] = &priv
->band
;
1744 dev
->flags
= IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING
|
1745 IEEE80211_HW_RX_INCLUDES_FCS
|
1746 IEEE80211_HW_SIGNAL_UNSPEC
;
1747 dev
->vif_data_size
= sizeof(struct rtl8180_vif
);
1748 dev
->wiphy
->interface_modes
= BIT(NL80211_IFTYPE_STATION
) |
1749 BIT(NL80211_IFTYPE_ADHOC
);
1750 dev
->max_signal
= 65;
1752 reg
= rtl818x_ioread32(priv
, &priv
->map
->TX_CONF
);
1753 reg
&= RTL818X_TX_CONF_HWVER_MASK
;
1755 case RTL818X_TX_CONF_R8180_ABCD
:
1756 chip_name
= "RTL8180";
1757 priv
->chip_family
= RTL818X_CHIP_FAMILY_RTL8180
;
1760 case RTL818X_TX_CONF_R8180_F
:
1761 chip_name
= "RTL8180vF";
1762 priv
->chip_family
= RTL818X_CHIP_FAMILY_RTL8180
;
1765 case RTL818X_TX_CONF_R8185_ABC
:
1766 chip_name
= "RTL8185";
1767 priv
->chip_family
= RTL818X_CHIP_FAMILY_RTL8185
;
1770 case RTL818X_TX_CONF_R8185_D
:
1771 chip_name
= "RTL8185vD";
1772 priv
->chip_family
= RTL818X_CHIP_FAMILY_RTL8185
;
1775 case RTL818X_TX_CONF_RTL8187SE
:
1776 chip_name
= "RTL8187SE";
1777 priv
->chip_family
= RTL818X_CHIP_FAMILY_RTL8187SE
;
1781 printk(KERN_ERR
"%s (rtl8180): Unknown chip! (0x%x)\n",
1782 pci_name(pdev
), reg
>> 25);
1786 /* we declare to MAC80211 all the queues except for beacon queue
1787 * that will be eventually handled by DRV.
1788 * TX rings are arranged in such a way that lower is the IDX,
1789 * higher is the priority, in order to achieve direct mapping
1790 * with mac80211, however the beacon queue is an exception and it
1791 * is mapped on the highst tx ring IDX.
1793 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8187SE
)
1794 dev
->queues
= RTL8187SE_NR_TX_QUEUES
- 1;
1796 dev
->queues
= RTL8180_NR_TX_QUEUES
- 1;
1798 if (priv
->chip_family
!= RTL818X_CHIP_FAMILY_RTL8180
) {
1799 priv
->band
.n_bitrates
= ARRAY_SIZE(rtl818x_rates
);
1800 pci_try_set_mwi(pdev
);
1803 rtl8180_eeprom_read(priv
);
1805 switch (priv
->rf_type
) {
1806 case 1: rf_name
= "Intersil";
1808 case 2: rf_name
= "RFMD";
1810 case 3: priv
->rf
= &sa2400_rf_ops
;
1812 case 4: priv
->rf
= &max2820_rf_ops
;
1814 case 5: priv
->rf
= &grf5101_rf_ops
;
1817 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8187SE
)
1818 priv
->rf
= rtl8187se_detect_rf(dev
);
1820 priv
->rf
= rtl8180_detect_rf(dev
);
1823 rf_name
= "RTL8255";
1826 printk(KERN_ERR
"%s (rtl8180): Unknown RF! (0x%x)\n",
1827 pci_name(pdev
), priv
->rf_type
);
1832 printk(KERN_ERR
"%s (rtl8180): %s RF frontend not supported!\n",
1833 pci_name(pdev
), rf_name
);
1837 if (!is_valid_ether_addr(priv
->mac_addr
)) {
1838 printk(KERN_WARNING
"%s (rtl8180): Invalid hwaddr! Using"
1839 " randomly generated MAC addr\n", pci_name(pdev
));
1840 eth_random_addr(priv
->mac_addr
);
1842 SET_IEEE80211_PERM_ADDR(dev
, priv
->mac_addr
);
1844 spin_lock_init(&priv
->lock
);
1846 err
= ieee80211_register_hw(dev
);
1848 printk(KERN_ERR
"%s (rtl8180): Cannot register device\n",
1853 wiphy_info(dev
->wiphy
, "hwaddr %pm, %s + %s\n",
1854 priv
->mac_addr
, chip_name
, priv
->rf
->name
);
1859 pci_iounmap(pdev
, priv
->map
);
1862 ieee80211_free_hw(dev
);
1865 pci_release_regions(pdev
);
1866 pci_disable_device(pdev
);
1870 static void rtl8180_remove(struct pci_dev
*pdev
)
1872 struct ieee80211_hw
*dev
= pci_get_drvdata(pdev
);
1873 struct rtl8180_priv
*priv
;
1878 ieee80211_unregister_hw(dev
);
1882 pci_iounmap(pdev
, priv
->map
);
1883 pci_release_regions(pdev
);
1884 pci_disable_device(pdev
);
1885 ieee80211_free_hw(dev
);
1889 static int rtl8180_suspend(struct pci_dev
*pdev
, pm_message_t state
)
1891 pci_save_state(pdev
);
1892 pci_set_power_state(pdev
, pci_choose_state(pdev
, state
));
1896 static int rtl8180_resume(struct pci_dev
*pdev
)
1898 pci_set_power_state(pdev
, PCI_D0
);
1899 pci_restore_state(pdev
);
1903 #endif /* CONFIG_PM */
1905 static struct pci_driver rtl8180_driver
= {
1906 .name
= KBUILD_MODNAME
,
1907 .id_table
= rtl8180_table
,
1908 .probe
= rtl8180_probe
,
1909 .remove
= rtl8180_remove
,
1911 .suspend
= rtl8180_suspend
,
1912 .resume
= rtl8180_resume
,
1913 #endif /* CONFIG_PM */
1916 module_pci_driver(rtl8180_driver
);