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Merge branch 'oprofile-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[deliverable/linux.git] / drivers / net / wireless / rtl818x / rtl8187_dev.c
1 /*
2 * Linux device driver for RTL8187
3 *
4 * Copyright 2007 Michael Wu <flamingice@sourmilk.net>
5 * Copyright 2007 Andrea Merello <andreamrl@tiscali.it>
6 *
7 * Based on the r8187 driver, which is:
8 * Copyright 2005 Andrea Merello <andreamrl@tiscali.it>, et al.
9 *
10 * The driver was extended to the RTL8187B in 2008 by:
11 * Herton Ronaldo Krzesinski <herton@mandriva.com.br>
12 * Hin-Tak Leung <htl10@users.sourceforge.net>
13 * Larry Finger <Larry.Finger@lwfinger.net>
14 *
15 * Magic delays and register offsets below are taken from the original
16 * r8187 driver sources. Thanks to Realtek for their support!
17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License version 2 as
20 * published by the Free Software Foundation.
21 */
22
23 #include <linux/init.h>
24 #include <linux/usb.h>
25 #include <linux/delay.h>
26 #include <linux/etherdevice.h>
27 #include <linux/eeprom_93cx6.h>
28 #include <net/mac80211.h>
29
30 #include "rtl8187.h"
31 #include "rtl8187_rtl8225.h"
32
33 MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
34 MODULE_AUTHOR("Andrea Merello <andreamrl@tiscali.it>");
35 MODULE_AUTHOR("Herton Ronaldo Krzesinski <herton@mandriva.com.br>");
36 MODULE_AUTHOR("Hin-Tak Leung <htl10@users.sourceforge.net>");
37 MODULE_AUTHOR("Larry Finger <Larry.Finger@lwfinger.net>");
38 MODULE_DESCRIPTION("RTL8187/RTL8187B USB wireless driver");
39 MODULE_LICENSE("GPL");
40
41 static struct usb_device_id rtl8187_table[] __devinitdata = {
42 /* Asus */
43 {USB_DEVICE(0x0b05, 0x171d), .driver_info = DEVICE_RTL8187},
44 /* Belkin */
45 {USB_DEVICE(0x050d, 0x705e), .driver_info = DEVICE_RTL8187B},
46 /* Realtek */
47 {USB_DEVICE(0x0bda, 0x8187), .driver_info = DEVICE_RTL8187},
48 {USB_DEVICE(0x0bda, 0x8189), .driver_info = DEVICE_RTL8187B},
49 {USB_DEVICE(0x0bda, 0x8197), .driver_info = DEVICE_RTL8187B},
50 {USB_DEVICE(0x0bda, 0x8198), .driver_info = DEVICE_RTL8187B},
51 /* Surecom */
52 {USB_DEVICE(0x0769, 0x11F2), .driver_info = DEVICE_RTL8187},
53 /* Logitech */
54 {USB_DEVICE(0x0789, 0x010C), .driver_info = DEVICE_RTL8187},
55 /* Netgear */
56 {USB_DEVICE(0x0846, 0x6100), .driver_info = DEVICE_RTL8187},
57 {USB_DEVICE(0x0846, 0x6a00), .driver_info = DEVICE_RTL8187},
58 {USB_DEVICE(0x0846, 0x4260), .driver_info = DEVICE_RTL8187B},
59 /* HP */
60 {USB_DEVICE(0x03f0, 0xca02), .driver_info = DEVICE_RTL8187},
61 /* Sitecom */
62 {USB_DEVICE(0x0df6, 0x000d), .driver_info = DEVICE_RTL8187},
63 {USB_DEVICE(0x0df6, 0x0028), .driver_info = DEVICE_RTL8187B},
64 /* Sphairon Access Systems GmbH */
65 {USB_DEVICE(0x114B, 0x0150), .driver_info = DEVICE_RTL8187},
66 /* Dick Smith Electronics */
67 {USB_DEVICE(0x1371, 0x9401), .driver_info = DEVICE_RTL8187},
68 /* Abocom */
69 {USB_DEVICE(0x13d1, 0xabe6), .driver_info = DEVICE_RTL8187},
70 /* Qcom */
71 {USB_DEVICE(0x18E8, 0x6232), .driver_info = DEVICE_RTL8187},
72 /* AirLive */
73 {USB_DEVICE(0x1b75, 0x8187), .driver_info = DEVICE_RTL8187},
74 /* Linksys */
75 {USB_DEVICE(0x1737, 0x0073), .driver_info = DEVICE_RTL8187B},
76 {}
77 };
78
79 MODULE_DEVICE_TABLE(usb, rtl8187_table);
80
81 static const struct ieee80211_rate rtl818x_rates[] = {
82 { .bitrate = 10, .hw_value = 0, },
83 { .bitrate = 20, .hw_value = 1, },
84 { .bitrate = 55, .hw_value = 2, },
85 { .bitrate = 110, .hw_value = 3, },
86 { .bitrate = 60, .hw_value = 4, },
87 { .bitrate = 90, .hw_value = 5, },
88 { .bitrate = 120, .hw_value = 6, },
89 { .bitrate = 180, .hw_value = 7, },
90 { .bitrate = 240, .hw_value = 8, },
91 { .bitrate = 360, .hw_value = 9, },
92 { .bitrate = 480, .hw_value = 10, },
93 { .bitrate = 540, .hw_value = 11, },
94 };
95
96 static const struct ieee80211_channel rtl818x_channels[] = {
97 { .center_freq = 2412 },
98 { .center_freq = 2417 },
99 { .center_freq = 2422 },
100 { .center_freq = 2427 },
101 { .center_freq = 2432 },
102 { .center_freq = 2437 },
103 { .center_freq = 2442 },
104 { .center_freq = 2447 },
105 { .center_freq = 2452 },
106 { .center_freq = 2457 },
107 { .center_freq = 2462 },
108 { .center_freq = 2467 },
109 { .center_freq = 2472 },
110 { .center_freq = 2484 },
111 };
112
113 static void rtl8187_iowrite_async_cb(struct urb *urb)
114 {
115 kfree(urb->context);
116 }
117
118 static void rtl8187_iowrite_async(struct rtl8187_priv *priv, __le16 addr,
119 void *data, u16 len)
120 {
121 struct usb_ctrlrequest *dr;
122 struct urb *urb;
123 struct rtl8187_async_write_data {
124 u8 data[4];
125 struct usb_ctrlrequest dr;
126 } *buf;
127 int rc;
128
129 buf = kmalloc(sizeof(*buf), GFP_ATOMIC);
130 if (!buf)
131 return;
132
133 urb = usb_alloc_urb(0, GFP_ATOMIC);
134 if (!urb) {
135 kfree(buf);
136 return;
137 }
138
139 dr = &buf->dr;
140
141 dr->bRequestType = RTL8187_REQT_WRITE;
142 dr->bRequest = RTL8187_REQ_SET_REG;
143 dr->wValue = addr;
144 dr->wIndex = 0;
145 dr->wLength = cpu_to_le16(len);
146
147 memcpy(buf, data, len);
148
149 usb_fill_control_urb(urb, priv->udev, usb_sndctrlpipe(priv->udev, 0),
150 (unsigned char *)dr, buf, len,
151 rtl8187_iowrite_async_cb, buf);
152 usb_anchor_urb(urb, &priv->anchored);
153 rc = usb_submit_urb(urb, GFP_ATOMIC);
154 if (rc < 0) {
155 kfree(buf);
156 usb_unanchor_urb(urb);
157 }
158 usb_free_urb(urb);
159 }
160
161 static inline void rtl818x_iowrite32_async(struct rtl8187_priv *priv,
162 __le32 *addr, u32 val)
163 {
164 __le32 buf = cpu_to_le32(val);
165
166 rtl8187_iowrite_async(priv, cpu_to_le16((unsigned long)addr),
167 &buf, sizeof(buf));
168 }
169
170 void rtl8187_write_phy(struct ieee80211_hw *dev, u8 addr, u32 data)
171 {
172 struct rtl8187_priv *priv = dev->priv;
173
174 data <<= 8;
175 data |= addr | 0x80;
176
177 rtl818x_iowrite8(priv, &priv->map->PHY[3], (data >> 24) & 0xFF);
178 rtl818x_iowrite8(priv, &priv->map->PHY[2], (data >> 16) & 0xFF);
179 rtl818x_iowrite8(priv, &priv->map->PHY[1], (data >> 8) & 0xFF);
180 rtl818x_iowrite8(priv, &priv->map->PHY[0], data & 0xFF);
181 }
182
183 static void rtl8187_tx_cb(struct urb *urb)
184 {
185 struct sk_buff *skb = (struct sk_buff *)urb->context;
186 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
187 struct ieee80211_hw *hw = info->rate_driver_data[0];
188 struct rtl8187_priv *priv = hw->priv;
189
190 skb_pull(skb, priv->is_rtl8187b ? sizeof(struct rtl8187b_tx_hdr) :
191 sizeof(struct rtl8187_tx_hdr));
192 ieee80211_tx_info_clear_status(info);
193
194 if (!(urb->status) && !(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
195 if (priv->is_rtl8187b) {
196 skb_queue_tail(&priv->b_tx_status.queue, skb);
197
198 /* queue is "full", discard last items */
199 while (skb_queue_len(&priv->b_tx_status.queue) > 5) {
200 struct sk_buff *old_skb;
201
202 dev_dbg(&priv->udev->dev,
203 "transmit status queue full\n");
204
205 old_skb = skb_dequeue(&priv->b_tx_status.queue);
206 ieee80211_tx_status_irqsafe(hw, old_skb);
207 }
208 return;
209 } else {
210 info->flags |= IEEE80211_TX_STAT_ACK;
211 }
212 }
213 if (priv->is_rtl8187b)
214 ieee80211_tx_status_irqsafe(hw, skb);
215 else {
216 /* Retry information for the RTI8187 is only available by
217 * reading a register in the device. We are in interrupt mode
218 * here, thus queue the skb and finish on a work queue. */
219 skb_queue_tail(&priv->b_tx_status.queue, skb);
220 queue_delayed_work(hw->workqueue, &priv->work, 0);
221 }
222 }
223
224 static int rtl8187_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
225 {
226 struct rtl8187_priv *priv = dev->priv;
227 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
228 unsigned int ep;
229 void *buf;
230 struct urb *urb;
231 __le16 rts_dur = 0;
232 u32 flags;
233 int rc;
234
235 urb = usb_alloc_urb(0, GFP_ATOMIC);
236 if (!urb) {
237 kfree_skb(skb);
238 return NETDEV_TX_OK;
239 }
240
241 flags = skb->len;
242 flags |= RTL818X_TX_DESC_FLAG_NO_ENC;
243
244 flags |= ieee80211_get_tx_rate(dev, info)->hw_value << 24;
245 if (ieee80211_has_morefrags(((struct ieee80211_hdr *)skb->data)->frame_control))
246 flags |= RTL818X_TX_DESC_FLAG_MOREFRAG;
247 if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
248 flags |= RTL818X_TX_DESC_FLAG_RTS;
249 flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
250 rts_dur = ieee80211_rts_duration(dev, priv->vif,
251 skb->len, info);
252 } else if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
253 flags |= RTL818X_TX_DESC_FLAG_CTS;
254 flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
255 }
256
257 if (!priv->is_rtl8187b) {
258 struct rtl8187_tx_hdr *hdr =
259 (struct rtl8187_tx_hdr *)skb_push(skb, sizeof(*hdr));
260 hdr->flags = cpu_to_le32(flags);
261 hdr->len = 0;
262 hdr->rts_duration = rts_dur;
263 hdr->retry = cpu_to_le32((info->control.rates[0].count - 1) << 8);
264 buf = hdr;
265
266 ep = 2;
267 } else {
268 /* fc needs to be calculated before skb_push() */
269 unsigned int epmap[4] = { 6, 7, 5, 4 };
270 struct ieee80211_hdr *tx_hdr =
271 (struct ieee80211_hdr *)(skb->data);
272 u16 fc = le16_to_cpu(tx_hdr->frame_control);
273
274 struct rtl8187b_tx_hdr *hdr =
275 (struct rtl8187b_tx_hdr *)skb_push(skb, sizeof(*hdr));
276 struct ieee80211_rate *txrate =
277 ieee80211_get_tx_rate(dev, info);
278 memset(hdr, 0, sizeof(*hdr));
279 hdr->flags = cpu_to_le32(flags);
280 hdr->rts_duration = rts_dur;
281 hdr->retry = cpu_to_le32((info->control.rates[0].count - 1) << 8);
282 hdr->tx_duration =
283 ieee80211_generic_frame_duration(dev, priv->vif,
284 skb->len, txrate);
285 buf = hdr;
286
287 if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT)
288 ep = 12;
289 else
290 ep = epmap[skb_get_queue_mapping(skb)];
291 }
292
293 info->rate_driver_data[0] = dev;
294 info->rate_driver_data[1] = urb;
295
296 usb_fill_bulk_urb(urb, priv->udev, usb_sndbulkpipe(priv->udev, ep),
297 buf, skb->len, rtl8187_tx_cb, skb);
298 urb->transfer_flags |= URB_ZERO_PACKET;
299 usb_anchor_urb(urb, &priv->anchored);
300 rc = usb_submit_urb(urb, GFP_ATOMIC);
301 if (rc < 0) {
302 usb_unanchor_urb(urb);
303 kfree_skb(skb);
304 }
305 usb_free_urb(urb);
306
307 return NETDEV_TX_OK;
308 }
309
310 static void rtl8187_rx_cb(struct urb *urb)
311 {
312 struct sk_buff *skb = (struct sk_buff *)urb->context;
313 struct rtl8187_rx_info *info = (struct rtl8187_rx_info *)skb->cb;
314 struct ieee80211_hw *dev = info->dev;
315 struct rtl8187_priv *priv = dev->priv;
316 struct ieee80211_rx_status rx_status = { 0 };
317 int rate, signal;
318 u32 flags;
319 u32 quality;
320 unsigned long f;
321
322 spin_lock_irqsave(&priv->rx_queue.lock, f);
323 if (skb->next)
324 __skb_unlink(skb, &priv->rx_queue);
325 else {
326 spin_unlock_irqrestore(&priv->rx_queue.lock, f);
327 return;
328 }
329 spin_unlock_irqrestore(&priv->rx_queue.lock, f);
330 skb_put(skb, urb->actual_length);
331
332 if (unlikely(urb->status)) {
333 dev_kfree_skb_irq(skb);
334 return;
335 }
336
337 if (!priv->is_rtl8187b) {
338 struct rtl8187_rx_hdr *hdr =
339 (typeof(hdr))(skb_tail_pointer(skb) - sizeof(*hdr));
340 flags = le32_to_cpu(hdr->flags);
341 /* As with the RTL8187B below, the AGC is used to calculate
342 * signal strength and quality. In this case, the scaling
343 * constants are derived from the output of p54usb.
344 */
345 quality = 130 - ((41 * hdr->agc) >> 6);
346 signal = -4 - ((27 * hdr->agc) >> 6);
347 rx_status.antenna = (hdr->signal >> 7) & 1;
348 rx_status.mactime = le64_to_cpu(hdr->mac_time);
349 } else {
350 struct rtl8187b_rx_hdr *hdr =
351 (typeof(hdr))(skb_tail_pointer(skb) - sizeof(*hdr));
352 /* The Realtek datasheet for the RTL8187B shows that the RX
353 * header contains the following quantities: signal quality,
354 * RSSI, AGC, the received power in dB, and the measured SNR.
355 * In testing, none of these quantities show qualitative
356 * agreement with AP signal strength, except for the AGC,
357 * which is inversely proportional to the strength of the
358 * signal. In the following, the quality and signal strength
359 * are derived from the AGC. The arbitrary scaling constants
360 * are chosen to make the results close to the values obtained
361 * for a BCM4312 using b43 as the driver. The noise is ignored
362 * for now.
363 */
364 flags = le32_to_cpu(hdr->flags);
365 quality = 170 - hdr->agc;
366 signal = 14 - hdr->agc / 2;
367 rx_status.antenna = (hdr->rssi >> 7) & 1;
368 rx_status.mactime = le64_to_cpu(hdr->mac_time);
369 }
370
371 if (quality > 100)
372 quality = 100;
373 rx_status.qual = quality;
374 priv->quality = quality;
375 rx_status.signal = signal;
376 priv->signal = signal;
377 rate = (flags >> 20) & 0xF;
378 skb_trim(skb, flags & 0x0FFF);
379 rx_status.rate_idx = rate;
380 rx_status.freq = dev->conf.channel->center_freq;
381 rx_status.band = dev->conf.channel->band;
382 rx_status.flag |= RX_FLAG_TSFT;
383 if (flags & RTL818X_RX_DESC_FLAG_CRC32_ERR)
384 rx_status.flag |= RX_FLAG_FAILED_FCS_CRC;
385 ieee80211_rx_irqsafe(dev, skb, &rx_status);
386
387 skb = dev_alloc_skb(RTL8187_MAX_RX);
388 if (unlikely(!skb)) {
389 /* TODO check rx queue length and refill *somewhere* */
390 return;
391 }
392
393 info = (struct rtl8187_rx_info *)skb->cb;
394 info->urb = urb;
395 info->dev = dev;
396 urb->transfer_buffer = skb_tail_pointer(skb);
397 urb->context = skb;
398 skb_queue_tail(&priv->rx_queue, skb);
399
400 usb_anchor_urb(urb, &priv->anchored);
401 if (usb_submit_urb(urb, GFP_ATOMIC)) {
402 usb_unanchor_urb(urb);
403 skb_unlink(skb, &priv->rx_queue);
404 dev_kfree_skb_irq(skb);
405 }
406 }
407
408 static int rtl8187_init_urbs(struct ieee80211_hw *dev)
409 {
410 struct rtl8187_priv *priv = dev->priv;
411 struct urb *entry = NULL;
412 struct sk_buff *skb;
413 struct rtl8187_rx_info *info;
414 int ret = 0;
415
416 while (skb_queue_len(&priv->rx_queue) < 16) {
417 skb = __dev_alloc_skb(RTL8187_MAX_RX, GFP_KERNEL);
418 if (!skb) {
419 ret = -ENOMEM;
420 goto err;
421 }
422 entry = usb_alloc_urb(0, GFP_KERNEL);
423 if (!entry) {
424 ret = -ENOMEM;
425 goto err;
426 }
427 usb_fill_bulk_urb(entry, priv->udev,
428 usb_rcvbulkpipe(priv->udev,
429 priv->is_rtl8187b ? 3 : 1),
430 skb_tail_pointer(skb),
431 RTL8187_MAX_RX, rtl8187_rx_cb, skb);
432 info = (struct rtl8187_rx_info *)skb->cb;
433 info->urb = entry;
434 info->dev = dev;
435 skb_queue_tail(&priv->rx_queue, skb);
436 usb_anchor_urb(entry, &priv->anchored);
437 ret = usb_submit_urb(entry, GFP_KERNEL);
438 if (ret) {
439 skb_unlink(skb, &priv->rx_queue);
440 usb_unanchor_urb(entry);
441 goto err;
442 }
443 usb_free_urb(entry);
444 }
445 return ret;
446
447 err:
448 usb_free_urb(entry);
449 kfree_skb(skb);
450 usb_kill_anchored_urbs(&priv->anchored);
451 return ret;
452 }
453
454 static void rtl8187b_status_cb(struct urb *urb)
455 {
456 struct ieee80211_hw *hw = (struct ieee80211_hw *)urb->context;
457 struct rtl8187_priv *priv = hw->priv;
458 u64 val;
459 unsigned int cmd_type;
460
461 if (unlikely(urb->status))
462 return;
463
464 /*
465 * Read from status buffer:
466 *
467 * bits [30:31] = cmd type:
468 * - 0 indicates tx beacon interrupt
469 * - 1 indicates tx close descriptor
470 *
471 * In the case of tx beacon interrupt:
472 * [0:9] = Last Beacon CW
473 * [10:29] = reserved
474 * [30:31] = 00b
475 * [32:63] = Last Beacon TSF
476 *
477 * If it's tx close descriptor:
478 * [0:7] = Packet Retry Count
479 * [8:14] = RTS Retry Count
480 * [15] = TOK
481 * [16:27] = Sequence No
482 * [28] = LS
483 * [29] = FS
484 * [30:31] = 01b
485 * [32:47] = unused (reserved?)
486 * [48:63] = MAC Used Time
487 */
488 val = le64_to_cpu(priv->b_tx_status.buf);
489
490 cmd_type = (val >> 30) & 0x3;
491 if (cmd_type == 1) {
492 unsigned int pkt_rc, seq_no;
493 bool tok;
494 struct sk_buff *skb;
495 struct ieee80211_hdr *ieee80211hdr;
496 unsigned long flags;
497
498 pkt_rc = val & 0xFF;
499 tok = val & (1 << 15);
500 seq_no = (val >> 16) & 0xFFF;
501
502 spin_lock_irqsave(&priv->b_tx_status.queue.lock, flags);
503 skb_queue_reverse_walk(&priv->b_tx_status.queue, skb) {
504 ieee80211hdr = (struct ieee80211_hdr *)skb->data;
505
506 /*
507 * While testing, it was discovered that the seq_no
508 * doesn't actually contains the sequence number.
509 * Instead of returning just the 12 bits of sequence
510 * number, hardware is returning entire sequence control
511 * (fragment number plus sequence number) in a 12 bit
512 * only field overflowing after some time. As a
513 * workaround, just consider the lower bits, and expect
514 * it's unlikely we wrongly ack some sent data
515 */
516 if ((le16_to_cpu(ieee80211hdr->seq_ctrl)
517 & 0xFFF) == seq_no)
518 break;
519 }
520 if (skb != (struct sk_buff *) &priv->b_tx_status.queue) {
521 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
522
523 __skb_unlink(skb, &priv->b_tx_status.queue);
524 if (tok)
525 info->flags |= IEEE80211_TX_STAT_ACK;
526 info->status.rates[0].count = pkt_rc + 1;
527
528 ieee80211_tx_status_irqsafe(hw, skb);
529 }
530 spin_unlock_irqrestore(&priv->b_tx_status.queue.lock, flags);
531 }
532
533 usb_anchor_urb(urb, &priv->anchored);
534 if (usb_submit_urb(urb, GFP_ATOMIC))
535 usb_unanchor_urb(urb);
536 }
537
538 static int rtl8187b_init_status_urb(struct ieee80211_hw *dev)
539 {
540 struct rtl8187_priv *priv = dev->priv;
541 struct urb *entry;
542 int ret = 0;
543
544 entry = usb_alloc_urb(0, GFP_KERNEL);
545 if (!entry)
546 return -ENOMEM;
547
548 usb_fill_bulk_urb(entry, priv->udev, usb_rcvbulkpipe(priv->udev, 9),
549 &priv->b_tx_status.buf, sizeof(priv->b_tx_status.buf),
550 rtl8187b_status_cb, dev);
551
552 usb_anchor_urb(entry, &priv->anchored);
553 ret = usb_submit_urb(entry, GFP_KERNEL);
554 if (ret)
555 usb_unanchor_urb(entry);
556 usb_free_urb(entry);
557
558 return ret;
559 }
560
561 static int rtl8187_cmd_reset(struct ieee80211_hw *dev)
562 {
563 struct rtl8187_priv *priv = dev->priv;
564 u8 reg;
565 int i;
566
567 reg = rtl818x_ioread8(priv, &priv->map->CMD);
568 reg &= (1 << 1);
569 reg |= RTL818X_CMD_RESET;
570 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
571
572 i = 10;
573 do {
574 msleep(2);
575 if (!(rtl818x_ioread8(priv, &priv->map->CMD) &
576 RTL818X_CMD_RESET))
577 break;
578 } while (--i);
579
580 if (!i) {
581 printk(KERN_ERR "%s: Reset timeout!\n", wiphy_name(dev->wiphy));
582 return -ETIMEDOUT;
583 }
584
585 /* reload registers from eeprom */
586 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_LOAD);
587
588 i = 10;
589 do {
590 msleep(4);
591 if (!(rtl818x_ioread8(priv, &priv->map->EEPROM_CMD) &
592 RTL818X_EEPROM_CMD_CONFIG))
593 break;
594 } while (--i);
595
596 if (!i) {
597 printk(KERN_ERR "%s: eeprom reset timeout!\n",
598 wiphy_name(dev->wiphy));
599 return -ETIMEDOUT;
600 }
601
602 return 0;
603 }
604
605 static int rtl8187_init_hw(struct ieee80211_hw *dev)
606 {
607 struct rtl8187_priv *priv = dev->priv;
608 u8 reg;
609 int res;
610
611 /* reset */
612 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
613 RTL818X_EEPROM_CMD_CONFIG);
614 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
615 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg |
616 RTL818X_CONFIG3_ANAPARAM_WRITE);
617 rtl818x_iowrite32(priv, &priv->map->ANAPARAM,
618 RTL8187_RTL8225_ANAPARAM_ON);
619 rtl818x_iowrite32(priv, &priv->map->ANAPARAM2,
620 RTL8187_RTL8225_ANAPARAM2_ON);
621 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg &
622 ~RTL818X_CONFIG3_ANAPARAM_WRITE);
623 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
624 RTL818X_EEPROM_CMD_NORMAL);
625
626 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
627
628 msleep(200);
629 rtl818x_iowrite8(priv, (u8 *)0xFE18, 0x10);
630 rtl818x_iowrite8(priv, (u8 *)0xFE18, 0x11);
631 rtl818x_iowrite8(priv, (u8 *)0xFE18, 0x00);
632 msleep(200);
633
634 res = rtl8187_cmd_reset(dev);
635 if (res)
636 return res;
637
638 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
639 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
640 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
641 reg | RTL818X_CONFIG3_ANAPARAM_WRITE);
642 rtl818x_iowrite32(priv, &priv->map->ANAPARAM,
643 RTL8187_RTL8225_ANAPARAM_ON);
644 rtl818x_iowrite32(priv, &priv->map->ANAPARAM2,
645 RTL8187_RTL8225_ANAPARAM2_ON);
646 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
647 reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE);
648 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
649
650 /* setup card */
651 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0);
652 rtl818x_iowrite8(priv, &priv->map->GPIO, 0);
653
654 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, (4 << 8));
655 rtl818x_iowrite8(priv, &priv->map->GPIO, 1);
656 rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, 0);
657
658 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
659
660 rtl818x_iowrite16(priv, (__le16 *)0xFFF4, 0xFFFF);
661 reg = rtl818x_ioread8(priv, &priv->map->CONFIG1);
662 reg &= 0x3F;
663 reg |= 0x80;
664 rtl818x_iowrite8(priv, &priv->map->CONFIG1, reg);
665
666 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
667
668 rtl818x_iowrite32(priv, &priv->map->INT_TIMEOUT, 0);
669 rtl818x_iowrite8(priv, &priv->map->WPA_CONF, 0);
670 rtl818x_iowrite8(priv, &priv->map->RATE_FALLBACK, 0);
671
672 // TODO: set RESP_RATE and BRSR properly
673 rtl818x_iowrite8(priv, &priv->map->RESP_RATE, (8 << 4) | 0);
674 rtl818x_iowrite16(priv, &priv->map->BRSR, 0x01F3);
675
676 /* host_usb_init */
677 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0);
678 rtl818x_iowrite8(priv, &priv->map->GPIO, 0);
679 reg = rtl818x_ioread8(priv, (u8 *)0xFE53);
680 rtl818x_iowrite8(priv, (u8 *)0xFE53, reg | (1 << 7));
681 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, (4 << 8));
682 rtl818x_iowrite8(priv, &priv->map->GPIO, 0x20);
683 rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, 0);
684 rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, 0x80);
685 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0x80);
686 rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x80);
687 msleep(100);
688
689 rtl818x_iowrite32(priv, &priv->map->RF_TIMING, 0x000a8008);
690 rtl818x_iowrite16(priv, &priv->map->BRSR, 0xFFFF);
691 rtl818x_iowrite32(priv, &priv->map->RF_PARA, 0x00100044);
692 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
693 RTL818X_EEPROM_CMD_CONFIG);
694 rtl818x_iowrite8(priv, &priv->map->CONFIG3, 0x44);
695 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
696 RTL818X_EEPROM_CMD_NORMAL);
697 rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x1FF7);
698 msleep(100);
699
700 priv->rf->init(dev);
701
702 rtl818x_iowrite16(priv, &priv->map->BRSR, 0x01F3);
703 reg = rtl818x_ioread8(priv, &priv->map->PGSELECT) & ~1;
704 rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg | 1);
705 rtl818x_iowrite16(priv, (__le16 *)0xFFFE, 0x10);
706 rtl818x_iowrite8(priv, &priv->map->TALLY_SEL, 0x80);
707 rtl818x_iowrite8(priv, (u8 *)0xFFFF, 0x60);
708 rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg);
709
710 return 0;
711 }
712
713 static const u8 rtl8187b_reg_table[][3] = {
714 {0xF0, 0x32, 0}, {0xF1, 0x32, 0}, {0xF2, 0x00, 0}, {0xF3, 0x00, 0},
715 {0xF4, 0x32, 0}, {0xF5, 0x43, 0}, {0xF6, 0x00, 0}, {0xF7, 0x00, 0},
716 {0xF8, 0x46, 0}, {0xF9, 0xA4, 0}, {0xFA, 0x00, 0}, {0xFB, 0x00, 0},
717 {0xFC, 0x96, 0}, {0xFD, 0xA4, 0}, {0xFE, 0x00, 0}, {0xFF, 0x00, 0},
718
719 {0x58, 0x4B, 1}, {0x59, 0x00, 1}, {0x5A, 0x4B, 1}, {0x5B, 0x00, 1},
720 {0x60, 0x4B, 1}, {0x61, 0x09, 1}, {0x62, 0x4B, 1}, {0x63, 0x09, 1},
721 {0xCE, 0x0F, 1}, {0xCF, 0x00, 1}, {0xE0, 0xFF, 1}, {0xE1, 0x0F, 1},
722 {0xE2, 0x00, 1}, {0xF0, 0x4E, 1}, {0xF1, 0x01, 1}, {0xF2, 0x02, 1},
723 {0xF3, 0x03, 1}, {0xF4, 0x04, 1}, {0xF5, 0x05, 1}, {0xF6, 0x06, 1},
724 {0xF7, 0x07, 1}, {0xF8, 0x08, 1},
725
726 {0x4E, 0x00, 2}, {0x0C, 0x04, 2}, {0x21, 0x61, 2}, {0x22, 0x68, 2},
727 {0x23, 0x6F, 2}, {0x24, 0x76, 2}, {0x25, 0x7D, 2}, {0x26, 0x84, 2},
728 {0x27, 0x8D, 2}, {0x4D, 0x08, 2}, {0x50, 0x05, 2}, {0x51, 0xF5, 2},
729 {0x52, 0x04, 2}, {0x53, 0xA0, 2}, {0x54, 0x1F, 2}, {0x55, 0x23, 2},
730 {0x56, 0x45, 2}, {0x57, 0x67, 2}, {0x58, 0x08, 2}, {0x59, 0x08, 2},
731 {0x5A, 0x08, 2}, {0x5B, 0x08, 2}, {0x60, 0x08, 2}, {0x61, 0x08, 2},
732 {0x62, 0x08, 2}, {0x63, 0x08, 2}, {0x64, 0xCF, 2}, {0x72, 0x56, 2},
733 {0x73, 0x9A, 2},
734
735 {0x34, 0xF0, 0}, {0x35, 0x0F, 0}, {0x5B, 0x40, 0}, {0x84, 0x88, 0},
736 {0x85, 0x24, 0}, {0x88, 0x54, 0}, {0x8B, 0xB8, 0}, {0x8C, 0x07, 0},
737 {0x8D, 0x00, 0}, {0x94, 0x1B, 0}, {0x95, 0x12, 0}, {0x96, 0x00, 0},
738 {0x97, 0x06, 0}, {0x9D, 0x1A, 0}, {0x9F, 0x10, 0}, {0xB4, 0x22, 0},
739 {0xBE, 0x80, 0}, {0xDB, 0x00, 0}, {0xEE, 0x00, 0}, {0x91, 0x03, 0},
740
741 {0x4C, 0x00, 2}, {0x9F, 0x00, 3}, {0x8C, 0x01, 0}, {0x8D, 0x10, 0},
742 {0x8E, 0x08, 0}, {0x8F, 0x00, 0}
743 };
744
745 static int rtl8187b_init_hw(struct ieee80211_hw *dev)
746 {
747 struct rtl8187_priv *priv = dev->priv;
748 int res, i;
749 u8 reg;
750
751 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
752 RTL818X_EEPROM_CMD_CONFIG);
753
754 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
755 reg |= RTL818X_CONFIG3_ANAPARAM_WRITE | RTL818X_CONFIG3_GNT_SELECT;
756 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg);
757 rtl818x_iowrite32(priv, &priv->map->ANAPARAM2,
758 RTL8187B_RTL8225_ANAPARAM2_ON);
759 rtl818x_iowrite32(priv, &priv->map->ANAPARAM,
760 RTL8187B_RTL8225_ANAPARAM_ON);
761 rtl818x_iowrite8(priv, &priv->map->ANAPARAM3,
762 RTL8187B_RTL8225_ANAPARAM3_ON);
763
764 rtl818x_iowrite8(priv, (u8 *)0xFF61, 0x10);
765 reg = rtl818x_ioread8(priv, (u8 *)0xFF62);
766 rtl818x_iowrite8(priv, (u8 *)0xFF62, reg & ~(1 << 5));
767 rtl818x_iowrite8(priv, (u8 *)0xFF62, reg | (1 << 5));
768
769 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
770 reg &= ~RTL818X_CONFIG3_ANAPARAM_WRITE;
771 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg);
772
773 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
774 RTL818X_EEPROM_CMD_NORMAL);
775
776 res = rtl8187_cmd_reset(dev);
777 if (res)
778 return res;
779
780 rtl818x_iowrite16(priv, (__le16 *)0xFF2D, 0x0FFF);
781 reg = rtl818x_ioread8(priv, &priv->map->CW_CONF);
782 reg |= RTL818X_CW_CONF_PERPACKET_RETRY_SHIFT;
783 rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg);
784 reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL);
785 reg |= RTL818X_TX_AGC_CTL_PERPACKET_GAIN_SHIFT |
786 RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT;
787 rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg);
788
789 rtl818x_iowrite16_idx(priv, (__le16 *)0xFFE0, 0x0FFF, 1);
790
791 rtl818x_iowrite16(priv, &priv->map->BEACON_INTERVAL, 100);
792 rtl818x_iowrite16(priv, &priv->map->ATIM_WND, 2);
793 rtl818x_iowrite16_idx(priv, (__le16 *)0xFFD4, 0xFFFF, 1);
794
795 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
796 RTL818X_EEPROM_CMD_CONFIG);
797 reg = rtl818x_ioread8(priv, &priv->map->CONFIG1);
798 rtl818x_iowrite8(priv, &priv->map->CONFIG1, (reg & 0x3F) | 0x80);
799 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
800 RTL818X_EEPROM_CMD_NORMAL);
801
802 rtl818x_iowrite8(priv, &priv->map->WPA_CONF, 0);
803 for (i = 0; i < ARRAY_SIZE(rtl8187b_reg_table); i++) {
804 rtl818x_iowrite8_idx(priv,
805 (u8 *)(uintptr_t)
806 (rtl8187b_reg_table[i][0] | 0xFF00),
807 rtl8187b_reg_table[i][1],
808 rtl8187b_reg_table[i][2]);
809 }
810
811 rtl818x_iowrite16(priv, &priv->map->TID_AC_MAP, 0xFA50);
812 rtl818x_iowrite16(priv, &priv->map->INT_MIG, 0);
813
814 rtl818x_iowrite32_idx(priv, (__le32 *)0xFFF0, 0, 1);
815 rtl818x_iowrite32_idx(priv, (__le32 *)0xFFF4, 0, 1);
816 rtl818x_iowrite8_idx(priv, (u8 *)0xFFF8, 0, 1);
817
818 rtl818x_iowrite32(priv, &priv->map->RF_TIMING, 0x00004001);
819
820 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF72, 0x569A, 2);
821
822 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
823 RTL818X_EEPROM_CMD_CONFIG);
824 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
825 reg |= RTL818X_CONFIG3_ANAPARAM_WRITE;
826 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg);
827 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
828 RTL818X_EEPROM_CMD_NORMAL);
829
830 rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, 0x0480);
831 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0x2488);
832 rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x1FFF);
833 msleep(100);
834
835 priv->rf->init(dev);
836
837 reg = RTL818X_CMD_TX_ENABLE | RTL818X_CMD_RX_ENABLE;
838 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
839 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF);
840
841 rtl818x_iowrite8(priv, (u8 *)0xFE41, 0xF4);
842 rtl818x_iowrite8(priv, (u8 *)0xFE40, 0x00);
843 rtl818x_iowrite8(priv, (u8 *)0xFE42, 0x00);
844 rtl818x_iowrite8(priv, (u8 *)0xFE42, 0x01);
845 rtl818x_iowrite8(priv, (u8 *)0xFE40, 0x0F);
846 rtl818x_iowrite8(priv, (u8 *)0xFE42, 0x00);
847 rtl818x_iowrite8(priv, (u8 *)0xFE42, 0x01);
848
849 reg = rtl818x_ioread8(priv, (u8 *)0xFFDB);
850 rtl818x_iowrite8(priv, (u8 *)0xFFDB, reg | (1 << 2));
851 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF72, 0x59FA, 3);
852 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF74, 0x59D2, 3);
853 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF76, 0x59D2, 3);
854 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF78, 0x19FA, 3);
855 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF7A, 0x19FA, 3);
856 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF7C, 0x00D0, 3);
857 rtl818x_iowrite8(priv, (u8 *)0xFF61, 0);
858 rtl818x_iowrite8_idx(priv, (u8 *)0xFF80, 0x0F, 1);
859 rtl818x_iowrite8_idx(priv, (u8 *)0xFF83, 0x03, 1);
860 rtl818x_iowrite8(priv, (u8 *)0xFFDA, 0x10);
861 rtl818x_iowrite8_idx(priv, (u8 *)0xFF4D, 0x08, 2);
862
863 rtl818x_iowrite32(priv, &priv->map->HSSI_PARA, 0x0600321B);
864
865 rtl818x_iowrite16_idx(priv, (__le16 *)0xFFEC, 0x0800, 1);
866
867 priv->slot_time = 0x9;
868 priv->aifsn[0] = 2; /* AIFSN[AC_VO] */
869 priv->aifsn[1] = 2; /* AIFSN[AC_VI] */
870 priv->aifsn[2] = 7; /* AIFSN[AC_BK] */
871 priv->aifsn[3] = 3; /* AIFSN[AC_BE] */
872 rtl818x_iowrite8(priv, &priv->map->ACM_CONTROL, 0);
873
874 return 0;
875 }
876
877 static void rtl8187_work(struct work_struct *work)
878 {
879 /* The RTL8187 returns the retry count through register 0xFFFA. In
880 * addition, it appears to be a cumulative retry count, not the
881 * value for the current TX packet. When multiple TX entries are
882 * queued, the retry count will be valid for the last one in the queue.
883 * The "error" should not matter for purposes of rate setting. */
884 struct rtl8187_priv *priv = container_of(work, struct rtl8187_priv,
885 work.work);
886 struct ieee80211_tx_info *info;
887 struct ieee80211_hw *dev = priv->dev;
888 static u16 retry;
889 u16 tmp;
890
891 mutex_lock(&priv->conf_mutex);
892 tmp = rtl818x_ioread16(priv, (__le16 *)0xFFFA);
893 while (skb_queue_len(&priv->b_tx_status.queue) > 0) {
894 struct sk_buff *old_skb;
895
896 old_skb = skb_dequeue(&priv->b_tx_status.queue);
897 info = IEEE80211_SKB_CB(old_skb);
898 info->status.rates[0].count = tmp - retry + 1;
899 ieee80211_tx_status_irqsafe(dev, old_skb);
900 }
901 retry = tmp;
902 mutex_unlock(&priv->conf_mutex);
903 }
904
905 static int rtl8187_start(struct ieee80211_hw *dev)
906 {
907 struct rtl8187_priv *priv = dev->priv;
908 u32 reg;
909 int ret;
910
911 ret = (!priv->is_rtl8187b) ? rtl8187_init_hw(dev) :
912 rtl8187b_init_hw(dev);
913 if (ret)
914 return ret;
915
916 mutex_lock(&priv->conf_mutex);
917
918 init_usb_anchor(&priv->anchored);
919 priv->dev = dev;
920
921 if (priv->is_rtl8187b) {
922 reg = RTL818X_RX_CONF_MGMT |
923 RTL818X_RX_CONF_DATA |
924 RTL818X_RX_CONF_BROADCAST |
925 RTL818X_RX_CONF_NICMAC |
926 RTL818X_RX_CONF_BSSID |
927 (7 << 13 /* RX FIFO threshold NONE */) |
928 (7 << 10 /* MAX RX DMA */) |
929 RTL818X_RX_CONF_RX_AUTORESETPHY |
930 RTL818X_RX_CONF_ONLYERLPKT |
931 RTL818X_RX_CONF_MULTICAST;
932 priv->rx_conf = reg;
933 rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg);
934
935 rtl818x_iowrite32(priv, &priv->map->TX_CONF,
936 RTL818X_TX_CONF_HW_SEQNUM |
937 RTL818X_TX_CONF_DISREQQSIZE |
938 (7 << 8 /* short retry limit */) |
939 (7 << 0 /* long retry limit */) |
940 (7 << 21 /* MAX TX DMA */));
941 rtl8187_init_urbs(dev);
942 rtl8187b_init_status_urb(dev);
943 mutex_unlock(&priv->conf_mutex);
944 return 0;
945 }
946
947 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF);
948
949 rtl818x_iowrite32(priv, &priv->map->MAR[0], ~0);
950 rtl818x_iowrite32(priv, &priv->map->MAR[1], ~0);
951
952 rtl8187_init_urbs(dev);
953
954 reg = RTL818X_RX_CONF_ONLYERLPKT |
955 RTL818X_RX_CONF_RX_AUTORESETPHY |
956 RTL818X_RX_CONF_BSSID |
957 RTL818X_RX_CONF_MGMT |
958 RTL818X_RX_CONF_DATA |
959 (7 << 13 /* RX FIFO threshold NONE */) |
960 (7 << 10 /* MAX RX DMA */) |
961 RTL818X_RX_CONF_BROADCAST |
962 RTL818X_RX_CONF_NICMAC;
963
964 priv->rx_conf = reg;
965 rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg);
966
967 reg = rtl818x_ioread8(priv, &priv->map->CW_CONF);
968 reg &= ~RTL818X_CW_CONF_PERPACKET_CW_SHIFT;
969 reg |= RTL818X_CW_CONF_PERPACKET_RETRY_SHIFT;
970 rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg);
971
972 reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL);
973 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN_SHIFT;
974 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT;
975 reg &= ~RTL818X_TX_AGC_CTL_FEEDBACK_ANT;
976 rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg);
977
978 reg = RTL818X_TX_CONF_CW_MIN |
979 (7 << 21 /* MAX TX DMA */) |
980 RTL818X_TX_CONF_NO_ICV;
981 rtl818x_iowrite32(priv, &priv->map->TX_CONF, reg);
982
983 reg = rtl818x_ioread8(priv, &priv->map->CMD);
984 reg |= RTL818X_CMD_TX_ENABLE;
985 reg |= RTL818X_CMD_RX_ENABLE;
986 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
987 INIT_DELAYED_WORK(&priv->work, rtl8187_work);
988 mutex_unlock(&priv->conf_mutex);
989
990 return 0;
991 }
992
993 static void rtl8187_stop(struct ieee80211_hw *dev)
994 {
995 struct rtl8187_priv *priv = dev->priv;
996 struct sk_buff *skb;
997 u32 reg;
998
999 mutex_lock(&priv->conf_mutex);
1000 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
1001
1002 reg = rtl818x_ioread8(priv, &priv->map->CMD);
1003 reg &= ~RTL818X_CMD_TX_ENABLE;
1004 reg &= ~RTL818X_CMD_RX_ENABLE;
1005 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
1006
1007 priv->rf->stop(dev);
1008
1009 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
1010 reg = rtl818x_ioread8(priv, &priv->map->CONFIG4);
1011 rtl818x_iowrite8(priv, &priv->map->CONFIG4, reg | RTL818X_CONFIG4_VCOOFF);
1012 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
1013
1014 while ((skb = skb_dequeue(&priv->b_tx_status.queue)))
1015 dev_kfree_skb_any(skb);
1016
1017 usb_kill_anchored_urbs(&priv->anchored);
1018 if (!priv->is_rtl8187b)
1019 cancel_delayed_work_sync(&priv->work);
1020 mutex_unlock(&priv->conf_mutex);
1021 }
1022
1023 static int rtl8187_add_interface(struct ieee80211_hw *dev,
1024 struct ieee80211_if_init_conf *conf)
1025 {
1026 struct rtl8187_priv *priv = dev->priv;
1027 int i;
1028 int ret = -EOPNOTSUPP;
1029
1030 mutex_lock(&priv->conf_mutex);
1031 if (priv->mode != NL80211_IFTYPE_MONITOR)
1032 goto exit;
1033
1034 switch (conf->type) {
1035 case NL80211_IFTYPE_STATION:
1036 priv->mode = conf->type;
1037 break;
1038 default:
1039 goto exit;
1040 }
1041
1042 ret = 0;
1043 priv->vif = conf->vif;
1044
1045 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
1046 for (i = 0; i < ETH_ALEN; i++)
1047 rtl818x_iowrite8(priv, &priv->map->MAC[i],
1048 ((u8 *)conf->mac_addr)[i]);
1049 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
1050
1051 exit:
1052 mutex_unlock(&priv->conf_mutex);
1053 return ret;
1054 }
1055
1056 static void rtl8187_remove_interface(struct ieee80211_hw *dev,
1057 struct ieee80211_if_init_conf *conf)
1058 {
1059 struct rtl8187_priv *priv = dev->priv;
1060 mutex_lock(&priv->conf_mutex);
1061 priv->mode = NL80211_IFTYPE_MONITOR;
1062 priv->vif = NULL;
1063 mutex_unlock(&priv->conf_mutex);
1064 }
1065
1066 static int rtl8187_config(struct ieee80211_hw *dev, u32 changed)
1067 {
1068 struct rtl8187_priv *priv = dev->priv;
1069 struct ieee80211_conf *conf = &dev->conf;
1070 u32 reg;
1071
1072 mutex_lock(&priv->conf_mutex);
1073 reg = rtl818x_ioread32(priv, &priv->map->TX_CONF);
1074 /* Enable TX loopback on MAC level to avoid TX during channel
1075 * changes, as this has be seen to causes problems and the
1076 * card will stop work until next reset
1077 */
1078 rtl818x_iowrite32(priv, &priv->map->TX_CONF,
1079 reg | RTL818X_TX_CONF_LOOPBACK_MAC);
1080 priv->rf->set_chan(dev, conf);
1081 msleep(10);
1082 rtl818x_iowrite32(priv, &priv->map->TX_CONF, reg);
1083
1084 rtl818x_iowrite16(priv, &priv->map->ATIM_WND, 2);
1085 rtl818x_iowrite16(priv, &priv->map->ATIMTR_INTERVAL, 100);
1086 rtl818x_iowrite16(priv, &priv->map->BEACON_INTERVAL, 100);
1087 rtl818x_iowrite16(priv, &priv->map->BEACON_INTERVAL_TIME, 100);
1088 mutex_unlock(&priv->conf_mutex);
1089 return 0;
1090 }
1091
1092 static int rtl8187_config_interface(struct ieee80211_hw *dev,
1093 struct ieee80211_vif *vif,
1094 struct ieee80211_if_conf *conf)
1095 {
1096 struct rtl8187_priv *priv = dev->priv;
1097 int i;
1098 u8 reg;
1099
1100 mutex_lock(&priv->conf_mutex);
1101 for (i = 0; i < ETH_ALEN; i++)
1102 rtl818x_iowrite8(priv, &priv->map->BSSID[i], conf->bssid[i]);
1103
1104 if (is_valid_ether_addr(conf->bssid)) {
1105 reg = RTL818X_MSR_INFRA;
1106 if (priv->is_rtl8187b)
1107 reg |= RTL818X_MSR_ENEDCA;
1108 rtl818x_iowrite8(priv, &priv->map->MSR, reg);
1109 } else {
1110 reg = RTL818X_MSR_NO_LINK;
1111 rtl818x_iowrite8(priv, &priv->map->MSR, reg);
1112 }
1113
1114 mutex_unlock(&priv->conf_mutex);
1115 return 0;
1116 }
1117
1118 /*
1119 * With 8187B, AC_*_PARAM clashes with FEMR definition in struct rtl818x_csr for
1120 * example. Thus we have to use raw values for AC_*_PARAM register addresses.
1121 */
1122 static __le32 *rtl8187b_ac_addr[4] = {
1123 (__le32 *) 0xFFF0, /* AC_VO */
1124 (__le32 *) 0xFFF4, /* AC_VI */
1125 (__le32 *) 0xFFFC, /* AC_BK */
1126 (__le32 *) 0xFFF8, /* AC_BE */
1127 };
1128
1129 #define SIFS_TIME 0xa
1130
1131 static void rtl8187_conf_erp(struct rtl8187_priv *priv, bool use_short_slot,
1132 bool use_short_preamble)
1133 {
1134 if (priv->is_rtl8187b) {
1135 u8 difs, eifs;
1136 u16 ack_timeout;
1137 int queue;
1138
1139 if (use_short_slot) {
1140 priv->slot_time = 0x9;
1141 difs = 0x1c;
1142 eifs = 0x53;
1143 } else {
1144 priv->slot_time = 0x14;
1145 difs = 0x32;
1146 eifs = 0x5b;
1147 }
1148 rtl818x_iowrite8(priv, &priv->map->SIFS, 0x22);
1149 rtl818x_iowrite8(priv, &priv->map->SLOT, priv->slot_time);
1150 rtl818x_iowrite8(priv, &priv->map->DIFS, difs);
1151
1152 /*
1153 * BRSR+1 on 8187B is in fact EIFS register
1154 * Value in units of 4 us
1155 */
1156 rtl818x_iowrite8(priv, (u8 *)&priv->map->BRSR + 1, eifs);
1157
1158 /*
1159 * For 8187B, CARRIER_SENSE_COUNTER is in fact ack timeout
1160 * register. In units of 4 us like eifs register
1161 * ack_timeout = ack duration + plcp + difs + preamble
1162 */
1163 ack_timeout = 112 + 48 + difs;
1164 if (use_short_preamble)
1165 ack_timeout += 72;
1166 else
1167 ack_timeout += 144;
1168 rtl818x_iowrite8(priv, &priv->map->CARRIER_SENSE_COUNTER,
1169 DIV_ROUND_UP(ack_timeout, 4));
1170
1171 for (queue = 0; queue < 4; queue++)
1172 rtl818x_iowrite8(priv, (u8 *) rtl8187b_ac_addr[queue],
1173 priv->aifsn[queue] * priv->slot_time +
1174 SIFS_TIME);
1175 } else {
1176 rtl818x_iowrite8(priv, &priv->map->SIFS, 0x22);
1177 if (use_short_slot) {
1178 rtl818x_iowrite8(priv, &priv->map->SLOT, 0x9);
1179 rtl818x_iowrite8(priv, &priv->map->DIFS, 0x14);
1180 rtl818x_iowrite8(priv, &priv->map->EIFS, 91 - 0x14);
1181 } else {
1182 rtl818x_iowrite8(priv, &priv->map->SLOT, 0x14);
1183 rtl818x_iowrite8(priv, &priv->map->DIFS, 0x24);
1184 rtl818x_iowrite8(priv, &priv->map->EIFS, 91 - 0x24);
1185 }
1186 }
1187 }
1188
1189 static void rtl8187_bss_info_changed(struct ieee80211_hw *dev,
1190 struct ieee80211_vif *vif,
1191 struct ieee80211_bss_conf *info,
1192 u32 changed)
1193 {
1194 struct rtl8187_priv *priv = dev->priv;
1195
1196 if (changed & (BSS_CHANGED_ERP_SLOT | BSS_CHANGED_ERP_PREAMBLE))
1197 rtl8187_conf_erp(priv, info->use_short_slot,
1198 info->use_short_preamble);
1199 }
1200
1201 static void rtl8187_configure_filter(struct ieee80211_hw *dev,
1202 unsigned int changed_flags,
1203 unsigned int *total_flags,
1204 int mc_count, struct dev_addr_list *mclist)
1205 {
1206 struct rtl8187_priv *priv = dev->priv;
1207
1208 if (changed_flags & FIF_FCSFAIL)
1209 priv->rx_conf ^= RTL818X_RX_CONF_FCS;
1210 if (changed_flags & FIF_CONTROL)
1211 priv->rx_conf ^= RTL818X_RX_CONF_CTRL;
1212 if (changed_flags & FIF_OTHER_BSS)
1213 priv->rx_conf ^= RTL818X_RX_CONF_MONITOR;
1214 if (*total_flags & FIF_ALLMULTI || mc_count > 0)
1215 priv->rx_conf |= RTL818X_RX_CONF_MULTICAST;
1216 else
1217 priv->rx_conf &= ~RTL818X_RX_CONF_MULTICAST;
1218
1219 *total_flags = 0;
1220
1221 if (priv->rx_conf & RTL818X_RX_CONF_FCS)
1222 *total_flags |= FIF_FCSFAIL;
1223 if (priv->rx_conf & RTL818X_RX_CONF_CTRL)
1224 *total_flags |= FIF_CONTROL;
1225 if (priv->rx_conf & RTL818X_RX_CONF_MONITOR)
1226 *total_flags |= FIF_OTHER_BSS;
1227 if (priv->rx_conf & RTL818X_RX_CONF_MULTICAST)
1228 *total_flags |= FIF_ALLMULTI;
1229
1230 rtl818x_iowrite32_async(priv, &priv->map->RX_CONF, priv->rx_conf);
1231 }
1232
1233 static int rtl8187_conf_tx(struct ieee80211_hw *dev, u16 queue,
1234 const struct ieee80211_tx_queue_params *params)
1235 {
1236 struct rtl8187_priv *priv = dev->priv;
1237 u8 cw_min, cw_max;
1238
1239 if (queue > 3)
1240 return -EINVAL;
1241
1242 cw_min = fls(params->cw_min);
1243 cw_max = fls(params->cw_max);
1244
1245 if (priv->is_rtl8187b) {
1246 priv->aifsn[queue] = params->aifs;
1247
1248 /*
1249 * This is the structure of AC_*_PARAM registers in 8187B:
1250 * - TXOP limit field, bit offset = 16
1251 * - ECWmax, bit offset = 12
1252 * - ECWmin, bit offset = 8
1253 * - AIFS, bit offset = 0
1254 */
1255 rtl818x_iowrite32(priv, rtl8187b_ac_addr[queue],
1256 (params->txop << 16) | (cw_max << 12) |
1257 (cw_min << 8) | (params->aifs *
1258 priv->slot_time + SIFS_TIME));
1259 } else {
1260 if (queue != 0)
1261 return -EINVAL;
1262
1263 rtl818x_iowrite8(priv, &priv->map->CW_VAL,
1264 cw_min | (cw_max << 4));
1265 }
1266 return 0;
1267 }
1268
1269 static const struct ieee80211_ops rtl8187_ops = {
1270 .tx = rtl8187_tx,
1271 .start = rtl8187_start,
1272 .stop = rtl8187_stop,
1273 .add_interface = rtl8187_add_interface,
1274 .remove_interface = rtl8187_remove_interface,
1275 .config = rtl8187_config,
1276 .config_interface = rtl8187_config_interface,
1277 .bss_info_changed = rtl8187_bss_info_changed,
1278 .configure_filter = rtl8187_configure_filter,
1279 .conf_tx = rtl8187_conf_tx
1280 };
1281
1282 static void rtl8187_eeprom_register_read(struct eeprom_93cx6 *eeprom)
1283 {
1284 struct ieee80211_hw *dev = eeprom->data;
1285 struct rtl8187_priv *priv = dev->priv;
1286 u8 reg = rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
1287
1288 eeprom->reg_data_in = reg & RTL818X_EEPROM_CMD_WRITE;
1289 eeprom->reg_data_out = reg & RTL818X_EEPROM_CMD_READ;
1290 eeprom->reg_data_clock = reg & RTL818X_EEPROM_CMD_CK;
1291 eeprom->reg_chip_select = reg & RTL818X_EEPROM_CMD_CS;
1292 }
1293
1294 static void rtl8187_eeprom_register_write(struct eeprom_93cx6 *eeprom)
1295 {
1296 struct ieee80211_hw *dev = eeprom->data;
1297 struct rtl8187_priv *priv = dev->priv;
1298 u8 reg = RTL818X_EEPROM_CMD_PROGRAM;
1299
1300 if (eeprom->reg_data_in)
1301 reg |= RTL818X_EEPROM_CMD_WRITE;
1302 if (eeprom->reg_data_out)
1303 reg |= RTL818X_EEPROM_CMD_READ;
1304 if (eeprom->reg_data_clock)
1305 reg |= RTL818X_EEPROM_CMD_CK;
1306 if (eeprom->reg_chip_select)
1307 reg |= RTL818X_EEPROM_CMD_CS;
1308
1309 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, reg);
1310 udelay(10);
1311 }
1312
1313 static int __devinit rtl8187_probe(struct usb_interface *intf,
1314 const struct usb_device_id *id)
1315 {
1316 struct usb_device *udev = interface_to_usbdev(intf);
1317 struct ieee80211_hw *dev;
1318 struct rtl8187_priv *priv;
1319 struct eeprom_93cx6 eeprom;
1320 struct ieee80211_channel *channel;
1321 const char *chip_name;
1322 u16 txpwr, reg;
1323 int err, i;
1324
1325 dev = ieee80211_alloc_hw(sizeof(*priv), &rtl8187_ops);
1326 if (!dev) {
1327 printk(KERN_ERR "rtl8187: ieee80211 alloc failed\n");
1328 return -ENOMEM;
1329 }
1330
1331 priv = dev->priv;
1332 priv->is_rtl8187b = (id->driver_info == DEVICE_RTL8187B);
1333
1334 /* allocate "DMA aware" buffer for register accesses */
1335 priv->io_dmabuf = kmalloc(sizeof(*priv->io_dmabuf), GFP_KERNEL);
1336 if (!priv->io_dmabuf) {
1337 err = -ENOMEM;
1338 goto err_free_dev;
1339 }
1340 mutex_init(&priv->io_mutex);
1341
1342 SET_IEEE80211_DEV(dev, &intf->dev);
1343 usb_set_intfdata(intf, dev);
1344 priv->udev = udev;
1345
1346 usb_get_dev(udev);
1347
1348 skb_queue_head_init(&priv->rx_queue);
1349
1350 BUILD_BUG_ON(sizeof(priv->channels) != sizeof(rtl818x_channels));
1351 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(rtl818x_rates));
1352
1353 memcpy(priv->channels, rtl818x_channels, sizeof(rtl818x_channels));
1354 memcpy(priv->rates, rtl818x_rates, sizeof(rtl818x_rates));
1355 priv->map = (struct rtl818x_csr *)0xFF00;
1356
1357 priv->band.band = IEEE80211_BAND_2GHZ;
1358 priv->band.channels = priv->channels;
1359 priv->band.n_channels = ARRAY_SIZE(rtl818x_channels);
1360 priv->band.bitrates = priv->rates;
1361 priv->band.n_bitrates = ARRAY_SIZE(rtl818x_rates);
1362 dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
1363
1364
1365 priv->mode = NL80211_IFTYPE_MONITOR;
1366 dev->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1367 IEEE80211_HW_SIGNAL_DBM |
1368 IEEE80211_HW_RX_INCLUDES_FCS;
1369
1370 eeprom.data = dev;
1371 eeprom.register_read = rtl8187_eeprom_register_read;
1372 eeprom.register_write = rtl8187_eeprom_register_write;
1373 if (rtl818x_ioread32(priv, &priv->map->RX_CONF) & (1 << 6))
1374 eeprom.width = PCI_EEPROM_WIDTH_93C66;
1375 else
1376 eeprom.width = PCI_EEPROM_WIDTH_93C46;
1377
1378 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
1379 udelay(10);
1380
1381 eeprom_93cx6_multiread(&eeprom, RTL8187_EEPROM_MAC_ADDR,
1382 (__le16 __force *)dev->wiphy->perm_addr, 3);
1383 if (!is_valid_ether_addr(dev->wiphy->perm_addr)) {
1384 printk(KERN_WARNING "rtl8187: Invalid hwaddr! Using randomly "
1385 "generated MAC address\n");
1386 random_ether_addr(dev->wiphy->perm_addr);
1387 }
1388
1389 channel = priv->channels;
1390 for (i = 0; i < 3; i++) {
1391 eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_CHAN_1 + i,
1392 &txpwr);
1393 (*channel++).hw_value = txpwr & 0xFF;
1394 (*channel++).hw_value = txpwr >> 8;
1395 }
1396 for (i = 0; i < 2; i++) {
1397 eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_CHAN_4 + i,
1398 &txpwr);
1399 (*channel++).hw_value = txpwr & 0xFF;
1400 (*channel++).hw_value = txpwr >> 8;
1401 }
1402
1403 eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_BASE,
1404 &priv->txpwr_base);
1405
1406 reg = rtl818x_ioread8(priv, &priv->map->PGSELECT) & ~1;
1407 rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg | 1);
1408 /* 0 means asic B-cut, we should use SW 3 wire
1409 * bit-by-bit banging for radio. 1 means we can use
1410 * USB specific request to write radio registers */
1411 priv->asic_rev = rtl818x_ioread8(priv, (u8 *)0xFFFE) & 0x3;
1412 rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg);
1413 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
1414
1415 if (!priv->is_rtl8187b) {
1416 u32 reg32;
1417 reg32 = rtl818x_ioread32(priv, &priv->map->TX_CONF);
1418 reg32 &= RTL818X_TX_CONF_HWVER_MASK;
1419 switch (reg32) {
1420 case RTL818X_TX_CONF_R8187vD_B:
1421 /* Some RTL8187B devices have a USB ID of 0x8187
1422 * detect them here */
1423 chip_name = "RTL8187BvB(early)";
1424 priv->is_rtl8187b = 1;
1425 priv->hw_rev = RTL8187BvB;
1426 break;
1427 case RTL818X_TX_CONF_R8187vD:
1428 chip_name = "RTL8187vD";
1429 break;
1430 default:
1431 chip_name = "RTL8187vB (default)";
1432 }
1433 } else {
1434 /*
1435 * Force USB request to write radio registers for 8187B, Realtek
1436 * only uses it in their sources
1437 */
1438 /*if (priv->asic_rev == 0) {
1439 printk(KERN_WARNING "rtl8187: Forcing use of USB "
1440 "requests to write to radio registers\n");
1441 priv->asic_rev = 1;
1442 }*/
1443 switch (rtl818x_ioread8(priv, (u8 *)0xFFE1)) {
1444 case RTL818X_R8187B_B:
1445 chip_name = "RTL8187BvB";
1446 priv->hw_rev = RTL8187BvB;
1447 break;
1448 case RTL818X_R8187B_D:
1449 chip_name = "RTL8187BvD";
1450 priv->hw_rev = RTL8187BvD;
1451 break;
1452 case RTL818X_R8187B_E:
1453 chip_name = "RTL8187BvE";
1454 priv->hw_rev = RTL8187BvE;
1455 break;
1456 default:
1457 chip_name = "RTL8187BvB (default)";
1458 priv->hw_rev = RTL8187BvB;
1459 }
1460 }
1461
1462 if (!priv->is_rtl8187b) {
1463 for (i = 0; i < 2; i++) {
1464 eeprom_93cx6_read(&eeprom,
1465 RTL8187_EEPROM_TXPWR_CHAN_6 + i,
1466 &txpwr);
1467 (*channel++).hw_value = txpwr & 0xFF;
1468 (*channel++).hw_value = txpwr >> 8;
1469 }
1470 } else {
1471 eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_CHAN_6,
1472 &txpwr);
1473 (*channel++).hw_value = txpwr & 0xFF;
1474
1475 eeprom_93cx6_read(&eeprom, 0x0A, &txpwr);
1476 (*channel++).hw_value = txpwr & 0xFF;
1477
1478 eeprom_93cx6_read(&eeprom, 0x1C, &txpwr);
1479 (*channel++).hw_value = txpwr & 0xFF;
1480 (*channel++).hw_value = txpwr >> 8;
1481 }
1482
1483 if (priv->is_rtl8187b)
1484 printk(KERN_WARNING "rtl8187: 8187B chip detected.\n");
1485
1486 /*
1487 * XXX: Once this driver supports anything that requires
1488 * beacons it must implement IEEE80211_TX_CTL_ASSIGN_SEQ.
1489 */
1490 dev->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
1491
1492 if ((id->driver_info == DEVICE_RTL8187) && priv->is_rtl8187b)
1493 printk(KERN_INFO "rtl8187: inconsistency between id with OEM"
1494 " info!\n");
1495
1496 priv->rf = rtl8187_detect_rf(dev);
1497 dev->extra_tx_headroom = (!priv->is_rtl8187b) ?
1498 sizeof(struct rtl8187_tx_hdr) :
1499 sizeof(struct rtl8187b_tx_hdr);
1500 if (!priv->is_rtl8187b)
1501 dev->queues = 1;
1502 else
1503 dev->queues = 4;
1504
1505 err = ieee80211_register_hw(dev);
1506 if (err) {
1507 printk(KERN_ERR "rtl8187: Cannot register device\n");
1508 goto err_free_dmabuf;
1509 }
1510 mutex_init(&priv->conf_mutex);
1511 skb_queue_head_init(&priv->b_tx_status.queue);
1512
1513 printk(KERN_INFO "%s: hwaddr %pM, %s V%d + %s\n",
1514 wiphy_name(dev->wiphy), dev->wiphy->perm_addr,
1515 chip_name, priv->asic_rev, priv->rf->name);
1516
1517 return 0;
1518
1519 err_free_dmabuf:
1520 kfree(priv->io_dmabuf);
1521 err_free_dev:
1522 ieee80211_free_hw(dev);
1523 usb_set_intfdata(intf, NULL);
1524 usb_put_dev(udev);
1525 return err;
1526 }
1527
1528 static void __devexit rtl8187_disconnect(struct usb_interface *intf)
1529 {
1530 struct ieee80211_hw *dev = usb_get_intfdata(intf);
1531 struct rtl8187_priv *priv;
1532
1533 if (!dev)
1534 return;
1535
1536 ieee80211_unregister_hw(dev);
1537
1538 priv = dev->priv;
1539 usb_reset_device(priv->udev);
1540 usb_put_dev(interface_to_usbdev(intf));
1541 kfree(priv->io_dmabuf);
1542 ieee80211_free_hw(dev);
1543 }
1544
1545 static struct usb_driver rtl8187_driver = {
1546 .name = KBUILD_MODNAME,
1547 .id_table = rtl8187_table,
1548 .probe = rtl8187_probe,
1549 .disconnect = __devexit_p(rtl8187_disconnect),
1550 };
1551
1552 static int __init rtl8187_init(void)
1553 {
1554 return usb_register(&rtl8187_driver);
1555 }
1556
1557 static void __exit rtl8187_exit(void)
1558 {
1559 usb_deregister(&rtl8187_driver);
1560 }
1561
1562 module_init(rtl8187_init);
1563 module_exit(rtl8187_exit);
Linux kernel - Deliverables
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