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oprofile: introduce module_param oprofile.cpu_type
[deliverable/linux.git] / drivers / net / wireless / rtl818x / rtl8187_dev.c
1 /*
2 * Linux device driver for RTL8187
3 *
4 * Copyright 2007 Michael Wu <flamingice@sourmilk.net>
5 * Copyright 2007 Andrea Merello <andreamrl@tiscali.it>
6 *
7 * Based on the r8187 driver, which is:
8 * Copyright 2005 Andrea Merello <andreamrl@tiscali.it>, et al.
9 *
10 * The driver was extended to the RTL8187B in 2008 by:
11 * Herton Ronaldo Krzesinski <herton@mandriva.com.br>
12 * Hin-Tak Leung <htl10@users.sourceforge.net>
13 * Larry Finger <Larry.Finger@lwfinger.net>
14 *
15 * Magic delays and register offsets below are taken from the original
16 * r8187 driver sources. Thanks to Realtek for their support!
17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License version 2 as
20 * published by the Free Software Foundation.
21 */
22
23 #include <linux/init.h>
24 #include <linux/usb.h>
25 #include <linux/delay.h>
26 #include <linux/etherdevice.h>
27 #include <linux/eeprom_93cx6.h>
28 #include <net/mac80211.h>
29
30 #include "rtl8187.h"
31 #include "rtl8187_rtl8225.h"
32
33 MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
34 MODULE_AUTHOR("Andrea Merello <andreamrl@tiscali.it>");
35 MODULE_AUTHOR("Herton Ronaldo Krzesinski <herton@mandriva.com.br>");
36 MODULE_AUTHOR("Hin-Tak Leung <htl10@users.sourceforge.net>");
37 MODULE_AUTHOR("Larry Finger <Larry.Finger@lwfinger.net>");
38 MODULE_DESCRIPTION("RTL8187/RTL8187B USB wireless driver");
39 MODULE_LICENSE("GPL");
40
41 static struct usb_device_id rtl8187_table[] __devinitdata = {
42 /* Asus */
43 {USB_DEVICE(0x0b05, 0x171d), .driver_info = DEVICE_RTL8187},
44 /* Belkin */
45 {USB_DEVICE(0x050d, 0x705e), .driver_info = DEVICE_RTL8187B},
46 /* Realtek */
47 {USB_DEVICE(0x0bda, 0x8187), .driver_info = DEVICE_RTL8187},
48 {USB_DEVICE(0x0bda, 0x8189), .driver_info = DEVICE_RTL8187B},
49 {USB_DEVICE(0x0bda, 0x8197), .driver_info = DEVICE_RTL8187B},
50 {USB_DEVICE(0x0bda, 0x8198), .driver_info = DEVICE_RTL8187B},
51 /* Surecom */
52 {USB_DEVICE(0x0769, 0x11F2), .driver_info = DEVICE_RTL8187},
53 /* Logitech */
54 {USB_DEVICE(0x0789, 0x010C), .driver_info = DEVICE_RTL8187},
55 /* Netgear */
56 {USB_DEVICE(0x0846, 0x6100), .driver_info = DEVICE_RTL8187},
57 {USB_DEVICE(0x0846, 0x6a00), .driver_info = DEVICE_RTL8187},
58 {USB_DEVICE(0x0846, 0x4260), .driver_info = DEVICE_RTL8187B},
59 /* HP */
60 {USB_DEVICE(0x03f0, 0xca02), .driver_info = DEVICE_RTL8187},
61 /* Sitecom */
62 {USB_DEVICE(0x0df6, 0x000d), .driver_info = DEVICE_RTL8187},
63 {USB_DEVICE(0x0df6, 0x0028), .driver_info = DEVICE_RTL8187B},
64 /* Sphairon Access Systems GmbH */
65 {USB_DEVICE(0x114B, 0x0150), .driver_info = DEVICE_RTL8187},
66 /* Dick Smith Electronics */
67 {USB_DEVICE(0x1371, 0x9401), .driver_info = DEVICE_RTL8187},
68 /* Abocom */
69 {USB_DEVICE(0x13d1, 0xabe6), .driver_info = DEVICE_RTL8187},
70 /* Qcom */
71 {USB_DEVICE(0x18E8, 0x6232), .driver_info = DEVICE_RTL8187},
72 /* AirLive */
73 {USB_DEVICE(0x1b75, 0x8187), .driver_info = DEVICE_RTL8187},
74 {}
75 };
76
77 MODULE_DEVICE_TABLE(usb, rtl8187_table);
78
79 static const struct ieee80211_rate rtl818x_rates[] = {
80 { .bitrate = 10, .hw_value = 0, },
81 { .bitrate = 20, .hw_value = 1, },
82 { .bitrate = 55, .hw_value = 2, },
83 { .bitrate = 110, .hw_value = 3, },
84 { .bitrate = 60, .hw_value = 4, },
85 { .bitrate = 90, .hw_value = 5, },
86 { .bitrate = 120, .hw_value = 6, },
87 { .bitrate = 180, .hw_value = 7, },
88 { .bitrate = 240, .hw_value = 8, },
89 { .bitrate = 360, .hw_value = 9, },
90 { .bitrate = 480, .hw_value = 10, },
91 { .bitrate = 540, .hw_value = 11, },
92 };
93
94 static const struct ieee80211_channel rtl818x_channels[] = {
95 { .center_freq = 2412 },
96 { .center_freq = 2417 },
97 { .center_freq = 2422 },
98 { .center_freq = 2427 },
99 { .center_freq = 2432 },
100 { .center_freq = 2437 },
101 { .center_freq = 2442 },
102 { .center_freq = 2447 },
103 { .center_freq = 2452 },
104 { .center_freq = 2457 },
105 { .center_freq = 2462 },
106 { .center_freq = 2467 },
107 { .center_freq = 2472 },
108 { .center_freq = 2484 },
109 };
110
111 static void rtl8187_iowrite_async_cb(struct urb *urb)
112 {
113 kfree(urb->context);
114 }
115
116 static void rtl8187_iowrite_async(struct rtl8187_priv *priv, __le16 addr,
117 void *data, u16 len)
118 {
119 struct usb_ctrlrequest *dr;
120 struct urb *urb;
121 struct rtl8187_async_write_data {
122 u8 data[4];
123 struct usb_ctrlrequest dr;
124 } *buf;
125 int rc;
126
127 buf = kmalloc(sizeof(*buf), GFP_ATOMIC);
128 if (!buf)
129 return;
130
131 urb = usb_alloc_urb(0, GFP_ATOMIC);
132 if (!urb) {
133 kfree(buf);
134 return;
135 }
136
137 dr = &buf->dr;
138
139 dr->bRequestType = RTL8187_REQT_WRITE;
140 dr->bRequest = RTL8187_REQ_SET_REG;
141 dr->wValue = addr;
142 dr->wIndex = 0;
143 dr->wLength = cpu_to_le16(len);
144
145 memcpy(buf, data, len);
146
147 usb_fill_control_urb(urb, priv->udev, usb_sndctrlpipe(priv->udev, 0),
148 (unsigned char *)dr, buf, len,
149 rtl8187_iowrite_async_cb, buf);
150 usb_anchor_urb(urb, &priv->anchored);
151 rc = usb_submit_urb(urb, GFP_ATOMIC);
152 if (rc < 0) {
153 kfree(buf);
154 usb_unanchor_urb(urb);
155 }
156 usb_free_urb(urb);
157 }
158
159 static inline void rtl818x_iowrite32_async(struct rtl8187_priv *priv,
160 __le32 *addr, u32 val)
161 {
162 __le32 buf = cpu_to_le32(val);
163
164 rtl8187_iowrite_async(priv, cpu_to_le16((unsigned long)addr),
165 &buf, sizeof(buf));
166 }
167
168 void rtl8187_write_phy(struct ieee80211_hw *dev, u8 addr, u32 data)
169 {
170 struct rtl8187_priv *priv = dev->priv;
171
172 data <<= 8;
173 data |= addr | 0x80;
174
175 rtl818x_iowrite8(priv, &priv->map->PHY[3], (data >> 24) & 0xFF);
176 rtl818x_iowrite8(priv, &priv->map->PHY[2], (data >> 16) & 0xFF);
177 rtl818x_iowrite8(priv, &priv->map->PHY[1], (data >> 8) & 0xFF);
178 rtl818x_iowrite8(priv, &priv->map->PHY[0], data & 0xFF);
179 }
180
181 static void rtl8187_tx_cb(struct urb *urb)
182 {
183 struct sk_buff *skb = (struct sk_buff *)urb->context;
184 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
185 struct ieee80211_hw *hw = info->rate_driver_data[0];
186 struct rtl8187_priv *priv = hw->priv;
187
188 skb_pull(skb, priv->is_rtl8187b ? sizeof(struct rtl8187b_tx_hdr) :
189 sizeof(struct rtl8187_tx_hdr));
190 ieee80211_tx_info_clear_status(info);
191
192 if (!(urb->status) && !(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
193 if (priv->is_rtl8187b) {
194 skb_queue_tail(&priv->b_tx_status.queue, skb);
195
196 /* queue is "full", discard last items */
197 while (skb_queue_len(&priv->b_tx_status.queue) > 5) {
198 struct sk_buff *old_skb;
199
200 dev_dbg(&priv->udev->dev,
201 "transmit status queue full\n");
202
203 old_skb = skb_dequeue(&priv->b_tx_status.queue);
204 ieee80211_tx_status_irqsafe(hw, old_skb);
205 }
206 return;
207 } else {
208 info->flags |= IEEE80211_TX_STAT_ACK;
209 }
210 }
211 if (priv->is_rtl8187b)
212 ieee80211_tx_status_irqsafe(hw, skb);
213 else {
214 /* Retry information for the RTI8187 is only available by
215 * reading a register in the device. We are in interrupt mode
216 * here, thus queue the skb and finish on a work queue. */
217 skb_queue_tail(&priv->b_tx_status.queue, skb);
218 queue_delayed_work(hw->workqueue, &priv->work, 0);
219 }
220 }
221
222 static int rtl8187_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
223 {
224 struct rtl8187_priv *priv = dev->priv;
225 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
226 unsigned int ep;
227 void *buf;
228 struct urb *urb;
229 __le16 rts_dur = 0;
230 u32 flags;
231 int rc;
232
233 urb = usb_alloc_urb(0, GFP_ATOMIC);
234 if (!urb) {
235 kfree_skb(skb);
236 return NETDEV_TX_OK;
237 }
238
239 flags = skb->len;
240 flags |= RTL818X_TX_DESC_FLAG_NO_ENC;
241
242 flags |= ieee80211_get_tx_rate(dev, info)->hw_value << 24;
243 if (ieee80211_has_morefrags(((struct ieee80211_hdr *)skb->data)->frame_control))
244 flags |= RTL818X_TX_DESC_FLAG_MOREFRAG;
245 if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
246 flags |= RTL818X_TX_DESC_FLAG_RTS;
247 flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
248 rts_dur = ieee80211_rts_duration(dev, priv->vif,
249 skb->len, info);
250 } else if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
251 flags |= RTL818X_TX_DESC_FLAG_CTS;
252 flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
253 }
254
255 if (!priv->is_rtl8187b) {
256 struct rtl8187_tx_hdr *hdr =
257 (struct rtl8187_tx_hdr *)skb_push(skb, sizeof(*hdr));
258 hdr->flags = cpu_to_le32(flags);
259 hdr->len = 0;
260 hdr->rts_duration = rts_dur;
261 hdr->retry = cpu_to_le32((info->control.rates[0].count - 1) << 8);
262 buf = hdr;
263
264 ep = 2;
265 } else {
266 /* fc needs to be calculated before skb_push() */
267 unsigned int epmap[4] = { 6, 7, 5, 4 };
268 struct ieee80211_hdr *tx_hdr =
269 (struct ieee80211_hdr *)(skb->data);
270 u16 fc = le16_to_cpu(tx_hdr->frame_control);
271
272 struct rtl8187b_tx_hdr *hdr =
273 (struct rtl8187b_tx_hdr *)skb_push(skb, sizeof(*hdr));
274 struct ieee80211_rate *txrate =
275 ieee80211_get_tx_rate(dev, info);
276 memset(hdr, 0, sizeof(*hdr));
277 hdr->flags = cpu_to_le32(flags);
278 hdr->rts_duration = rts_dur;
279 hdr->retry = cpu_to_le32((info->control.rates[0].count - 1) << 8);
280 hdr->tx_duration =
281 ieee80211_generic_frame_duration(dev, priv->vif,
282 skb->len, txrate);
283 buf = hdr;
284
285 if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT)
286 ep = 12;
287 else
288 ep = epmap[skb_get_queue_mapping(skb)];
289 }
290
291 info->rate_driver_data[0] = dev;
292 info->rate_driver_data[1] = urb;
293
294 usb_fill_bulk_urb(urb, priv->udev, usb_sndbulkpipe(priv->udev, ep),
295 buf, skb->len, rtl8187_tx_cb, skb);
296 urb->transfer_flags |= URB_ZERO_PACKET;
297 usb_anchor_urb(urb, &priv->anchored);
298 rc = usb_submit_urb(urb, GFP_ATOMIC);
299 if (rc < 0) {
300 usb_unanchor_urb(urb);
301 kfree_skb(skb);
302 }
303 usb_free_urb(urb);
304
305 return NETDEV_TX_OK;
306 }
307
308 static void rtl8187_rx_cb(struct urb *urb)
309 {
310 struct sk_buff *skb = (struct sk_buff *)urb->context;
311 struct rtl8187_rx_info *info = (struct rtl8187_rx_info *)skb->cb;
312 struct ieee80211_hw *dev = info->dev;
313 struct rtl8187_priv *priv = dev->priv;
314 struct ieee80211_rx_status rx_status = { 0 };
315 int rate, signal;
316 u32 flags;
317 u32 quality;
318 unsigned long f;
319
320 spin_lock_irqsave(&priv->rx_queue.lock, f);
321 if (skb->next)
322 __skb_unlink(skb, &priv->rx_queue);
323 else {
324 spin_unlock_irqrestore(&priv->rx_queue.lock, f);
325 return;
326 }
327 spin_unlock_irqrestore(&priv->rx_queue.lock, f);
328 skb_put(skb, urb->actual_length);
329
330 if (unlikely(urb->status)) {
331 dev_kfree_skb_irq(skb);
332 return;
333 }
334
335 if (!priv->is_rtl8187b) {
336 struct rtl8187_rx_hdr *hdr =
337 (typeof(hdr))(skb_tail_pointer(skb) - sizeof(*hdr));
338 flags = le32_to_cpu(hdr->flags);
339 /* As with the RTL8187B below, the AGC is used to calculate
340 * signal strength and quality. In this case, the scaling
341 * constants are derived from the output of p54usb.
342 */
343 quality = 130 - ((41 * hdr->agc) >> 6);
344 signal = -4 - ((27 * hdr->agc) >> 6);
345 rx_status.antenna = (hdr->signal >> 7) & 1;
346 rx_status.mactime = le64_to_cpu(hdr->mac_time);
347 } else {
348 struct rtl8187b_rx_hdr *hdr =
349 (typeof(hdr))(skb_tail_pointer(skb) - sizeof(*hdr));
350 /* The Realtek datasheet for the RTL8187B shows that the RX
351 * header contains the following quantities: signal quality,
352 * RSSI, AGC, the received power in dB, and the measured SNR.
353 * In testing, none of these quantities show qualitative
354 * agreement with AP signal strength, except for the AGC,
355 * which is inversely proportional to the strength of the
356 * signal. In the following, the quality and signal strength
357 * are derived from the AGC. The arbitrary scaling constants
358 * are chosen to make the results close to the values obtained
359 * for a BCM4312 using b43 as the driver. The noise is ignored
360 * for now.
361 */
362 flags = le32_to_cpu(hdr->flags);
363 quality = 170 - hdr->agc;
364 signal = 14 - hdr->agc / 2;
365 rx_status.antenna = (hdr->rssi >> 7) & 1;
366 rx_status.mactime = le64_to_cpu(hdr->mac_time);
367 }
368
369 if (quality > 100)
370 quality = 100;
371 rx_status.qual = quality;
372 priv->quality = quality;
373 rx_status.signal = signal;
374 priv->signal = signal;
375 rate = (flags >> 20) & 0xF;
376 skb_trim(skb, flags & 0x0FFF);
377 rx_status.rate_idx = rate;
378 rx_status.freq = dev->conf.channel->center_freq;
379 rx_status.band = dev->conf.channel->band;
380 rx_status.flag |= RX_FLAG_TSFT;
381 if (flags & RTL818X_RX_DESC_FLAG_CRC32_ERR)
382 rx_status.flag |= RX_FLAG_FAILED_FCS_CRC;
383 ieee80211_rx_irqsafe(dev, skb, &rx_status);
384
385 skb = dev_alloc_skb(RTL8187_MAX_RX);
386 if (unlikely(!skb)) {
387 /* TODO check rx queue length and refill *somewhere* */
388 return;
389 }
390
391 info = (struct rtl8187_rx_info *)skb->cb;
392 info->urb = urb;
393 info->dev = dev;
394 urb->transfer_buffer = skb_tail_pointer(skb);
395 urb->context = skb;
396 skb_queue_tail(&priv->rx_queue, skb);
397
398 usb_anchor_urb(urb, &priv->anchored);
399 if (usb_submit_urb(urb, GFP_ATOMIC)) {
400 usb_unanchor_urb(urb);
401 skb_unlink(skb, &priv->rx_queue);
402 dev_kfree_skb_irq(skb);
403 }
404 }
405
406 static int rtl8187_init_urbs(struct ieee80211_hw *dev)
407 {
408 struct rtl8187_priv *priv = dev->priv;
409 struct urb *entry = NULL;
410 struct sk_buff *skb;
411 struct rtl8187_rx_info *info;
412 int ret = 0;
413
414 while (skb_queue_len(&priv->rx_queue) < 16) {
415 skb = __dev_alloc_skb(RTL8187_MAX_RX, GFP_KERNEL);
416 if (!skb) {
417 ret = -ENOMEM;
418 goto err;
419 }
420 entry = usb_alloc_urb(0, GFP_KERNEL);
421 if (!entry) {
422 ret = -ENOMEM;
423 goto err;
424 }
425 usb_fill_bulk_urb(entry, priv->udev,
426 usb_rcvbulkpipe(priv->udev,
427 priv->is_rtl8187b ? 3 : 1),
428 skb_tail_pointer(skb),
429 RTL8187_MAX_RX, rtl8187_rx_cb, skb);
430 info = (struct rtl8187_rx_info *)skb->cb;
431 info->urb = entry;
432 info->dev = dev;
433 skb_queue_tail(&priv->rx_queue, skb);
434 usb_anchor_urb(entry, &priv->anchored);
435 ret = usb_submit_urb(entry, GFP_KERNEL);
436 if (ret) {
437 skb_unlink(skb, &priv->rx_queue);
438 usb_unanchor_urb(entry);
439 goto err;
440 }
441 usb_free_urb(entry);
442 }
443 return ret;
444
445 err:
446 usb_free_urb(entry);
447 kfree_skb(skb);
448 usb_kill_anchored_urbs(&priv->anchored);
449 return ret;
450 }
451
452 static void rtl8187b_status_cb(struct urb *urb)
453 {
454 struct ieee80211_hw *hw = (struct ieee80211_hw *)urb->context;
455 struct rtl8187_priv *priv = hw->priv;
456 u64 val;
457 unsigned int cmd_type;
458
459 if (unlikely(urb->status))
460 return;
461
462 /*
463 * Read from status buffer:
464 *
465 * bits [30:31] = cmd type:
466 * - 0 indicates tx beacon interrupt
467 * - 1 indicates tx close descriptor
468 *
469 * In the case of tx beacon interrupt:
470 * [0:9] = Last Beacon CW
471 * [10:29] = reserved
472 * [30:31] = 00b
473 * [32:63] = Last Beacon TSF
474 *
475 * If it's tx close descriptor:
476 * [0:7] = Packet Retry Count
477 * [8:14] = RTS Retry Count
478 * [15] = TOK
479 * [16:27] = Sequence No
480 * [28] = LS
481 * [29] = FS
482 * [30:31] = 01b
483 * [32:47] = unused (reserved?)
484 * [48:63] = MAC Used Time
485 */
486 val = le64_to_cpu(priv->b_tx_status.buf);
487
488 cmd_type = (val >> 30) & 0x3;
489 if (cmd_type == 1) {
490 unsigned int pkt_rc, seq_no;
491 bool tok;
492 struct sk_buff *skb;
493 struct ieee80211_hdr *ieee80211hdr;
494 unsigned long flags;
495
496 pkt_rc = val & 0xFF;
497 tok = val & (1 << 15);
498 seq_no = (val >> 16) & 0xFFF;
499
500 spin_lock_irqsave(&priv->b_tx_status.queue.lock, flags);
501 skb_queue_reverse_walk(&priv->b_tx_status.queue, skb) {
502 ieee80211hdr = (struct ieee80211_hdr *)skb->data;
503
504 /*
505 * While testing, it was discovered that the seq_no
506 * doesn't actually contains the sequence number.
507 * Instead of returning just the 12 bits of sequence
508 * number, hardware is returning entire sequence control
509 * (fragment number plus sequence number) in a 12 bit
510 * only field overflowing after some time. As a
511 * workaround, just consider the lower bits, and expect
512 * it's unlikely we wrongly ack some sent data
513 */
514 if ((le16_to_cpu(ieee80211hdr->seq_ctrl)
515 & 0xFFF) == seq_no)
516 break;
517 }
518 if (skb != (struct sk_buff *) &priv->b_tx_status.queue) {
519 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
520
521 __skb_unlink(skb, &priv->b_tx_status.queue);
522 if (tok)
523 info->flags |= IEEE80211_TX_STAT_ACK;
524 info->status.rates[0].count = pkt_rc + 1;
525
526 ieee80211_tx_status_irqsafe(hw, skb);
527 }
528 spin_unlock_irqrestore(&priv->b_tx_status.queue.lock, flags);
529 }
530
531 usb_anchor_urb(urb, &priv->anchored);
532 if (usb_submit_urb(urb, GFP_ATOMIC))
533 usb_unanchor_urb(urb);
534 }
535
536 static int rtl8187b_init_status_urb(struct ieee80211_hw *dev)
537 {
538 struct rtl8187_priv *priv = dev->priv;
539 struct urb *entry;
540 int ret = 0;
541
542 entry = usb_alloc_urb(0, GFP_KERNEL);
543 if (!entry)
544 return -ENOMEM;
545
546 usb_fill_bulk_urb(entry, priv->udev, usb_rcvbulkpipe(priv->udev, 9),
547 &priv->b_tx_status.buf, sizeof(priv->b_tx_status.buf),
548 rtl8187b_status_cb, dev);
549
550 usb_anchor_urb(entry, &priv->anchored);
551 ret = usb_submit_urb(entry, GFP_KERNEL);
552 if (ret)
553 usb_unanchor_urb(entry);
554 usb_free_urb(entry);
555
556 return ret;
557 }
558
559 static int rtl8187_cmd_reset(struct ieee80211_hw *dev)
560 {
561 struct rtl8187_priv *priv = dev->priv;
562 u8 reg;
563 int i;
564
565 reg = rtl818x_ioread8(priv, &priv->map->CMD);
566 reg &= (1 << 1);
567 reg |= RTL818X_CMD_RESET;
568 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
569
570 i = 10;
571 do {
572 msleep(2);
573 if (!(rtl818x_ioread8(priv, &priv->map->CMD) &
574 RTL818X_CMD_RESET))
575 break;
576 } while (--i);
577
578 if (!i) {
579 printk(KERN_ERR "%s: Reset timeout!\n", wiphy_name(dev->wiphy));
580 return -ETIMEDOUT;
581 }
582
583 /* reload registers from eeprom */
584 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_LOAD);
585
586 i = 10;
587 do {
588 msleep(4);
589 if (!(rtl818x_ioread8(priv, &priv->map->EEPROM_CMD) &
590 RTL818X_EEPROM_CMD_CONFIG))
591 break;
592 } while (--i);
593
594 if (!i) {
595 printk(KERN_ERR "%s: eeprom reset timeout!\n",
596 wiphy_name(dev->wiphy));
597 return -ETIMEDOUT;
598 }
599
600 return 0;
601 }
602
603 static int rtl8187_init_hw(struct ieee80211_hw *dev)
604 {
605 struct rtl8187_priv *priv = dev->priv;
606 u8 reg;
607 int res;
608
609 /* reset */
610 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
611 RTL818X_EEPROM_CMD_CONFIG);
612 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
613 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg |
614 RTL818X_CONFIG3_ANAPARAM_WRITE);
615 rtl818x_iowrite32(priv, &priv->map->ANAPARAM,
616 RTL8187_RTL8225_ANAPARAM_ON);
617 rtl818x_iowrite32(priv, &priv->map->ANAPARAM2,
618 RTL8187_RTL8225_ANAPARAM2_ON);
619 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg &
620 ~RTL818X_CONFIG3_ANAPARAM_WRITE);
621 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
622 RTL818X_EEPROM_CMD_NORMAL);
623
624 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
625
626 msleep(200);
627 rtl818x_iowrite8(priv, (u8 *)0xFE18, 0x10);
628 rtl818x_iowrite8(priv, (u8 *)0xFE18, 0x11);
629 rtl818x_iowrite8(priv, (u8 *)0xFE18, 0x00);
630 msleep(200);
631
632 res = rtl8187_cmd_reset(dev);
633 if (res)
634 return res;
635
636 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
637 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
638 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
639 reg | RTL818X_CONFIG3_ANAPARAM_WRITE);
640 rtl818x_iowrite32(priv, &priv->map->ANAPARAM,
641 RTL8187_RTL8225_ANAPARAM_ON);
642 rtl818x_iowrite32(priv, &priv->map->ANAPARAM2,
643 RTL8187_RTL8225_ANAPARAM2_ON);
644 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
645 reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE);
646 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
647
648 /* setup card */
649 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0);
650 rtl818x_iowrite8(priv, &priv->map->GPIO, 0);
651
652 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, (4 << 8));
653 rtl818x_iowrite8(priv, &priv->map->GPIO, 1);
654 rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, 0);
655
656 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
657
658 rtl818x_iowrite16(priv, (__le16 *)0xFFF4, 0xFFFF);
659 reg = rtl818x_ioread8(priv, &priv->map->CONFIG1);
660 reg &= 0x3F;
661 reg |= 0x80;
662 rtl818x_iowrite8(priv, &priv->map->CONFIG1, reg);
663
664 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
665
666 rtl818x_iowrite32(priv, &priv->map->INT_TIMEOUT, 0);
667 rtl818x_iowrite8(priv, &priv->map->WPA_CONF, 0);
668 rtl818x_iowrite8(priv, &priv->map->RATE_FALLBACK, 0);
669
670 // TODO: set RESP_RATE and BRSR properly
671 rtl818x_iowrite8(priv, &priv->map->RESP_RATE, (8 << 4) | 0);
672 rtl818x_iowrite16(priv, &priv->map->BRSR, 0x01F3);
673
674 /* host_usb_init */
675 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0);
676 rtl818x_iowrite8(priv, &priv->map->GPIO, 0);
677 reg = rtl818x_ioread8(priv, (u8 *)0xFE53);
678 rtl818x_iowrite8(priv, (u8 *)0xFE53, reg | (1 << 7));
679 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, (4 << 8));
680 rtl818x_iowrite8(priv, &priv->map->GPIO, 0x20);
681 rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, 0);
682 rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, 0x80);
683 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0x80);
684 rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x80);
685 msleep(100);
686
687 rtl818x_iowrite32(priv, &priv->map->RF_TIMING, 0x000a8008);
688 rtl818x_iowrite16(priv, &priv->map->BRSR, 0xFFFF);
689 rtl818x_iowrite32(priv, &priv->map->RF_PARA, 0x00100044);
690 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
691 RTL818X_EEPROM_CMD_CONFIG);
692 rtl818x_iowrite8(priv, &priv->map->CONFIG3, 0x44);
693 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
694 RTL818X_EEPROM_CMD_NORMAL);
695 rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x1FF7);
696 msleep(100);
697
698 priv->rf->init(dev);
699
700 rtl818x_iowrite16(priv, &priv->map->BRSR, 0x01F3);
701 reg = rtl818x_ioread8(priv, &priv->map->PGSELECT) & ~1;
702 rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg | 1);
703 rtl818x_iowrite16(priv, (__le16 *)0xFFFE, 0x10);
704 rtl818x_iowrite8(priv, &priv->map->TALLY_SEL, 0x80);
705 rtl818x_iowrite8(priv, (u8 *)0xFFFF, 0x60);
706 rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg);
707
708 return 0;
709 }
710
711 static const u8 rtl8187b_reg_table[][3] = {
712 {0xF0, 0x32, 0}, {0xF1, 0x32, 0}, {0xF2, 0x00, 0}, {0xF3, 0x00, 0},
713 {0xF4, 0x32, 0}, {0xF5, 0x43, 0}, {0xF6, 0x00, 0}, {0xF7, 0x00, 0},
714 {0xF8, 0x46, 0}, {0xF9, 0xA4, 0}, {0xFA, 0x00, 0}, {0xFB, 0x00, 0},
715 {0xFC, 0x96, 0}, {0xFD, 0xA4, 0}, {0xFE, 0x00, 0}, {0xFF, 0x00, 0},
716
717 {0x58, 0x4B, 1}, {0x59, 0x00, 1}, {0x5A, 0x4B, 1}, {0x5B, 0x00, 1},
718 {0x60, 0x4B, 1}, {0x61, 0x09, 1}, {0x62, 0x4B, 1}, {0x63, 0x09, 1},
719 {0xCE, 0x0F, 1}, {0xCF, 0x00, 1}, {0xE0, 0xFF, 1}, {0xE1, 0x0F, 1},
720 {0xE2, 0x00, 1}, {0xF0, 0x4E, 1}, {0xF1, 0x01, 1}, {0xF2, 0x02, 1},
721 {0xF3, 0x03, 1}, {0xF4, 0x04, 1}, {0xF5, 0x05, 1}, {0xF6, 0x06, 1},
722 {0xF7, 0x07, 1}, {0xF8, 0x08, 1},
723
724 {0x4E, 0x00, 2}, {0x0C, 0x04, 2}, {0x21, 0x61, 2}, {0x22, 0x68, 2},
725 {0x23, 0x6F, 2}, {0x24, 0x76, 2}, {0x25, 0x7D, 2}, {0x26, 0x84, 2},
726 {0x27, 0x8D, 2}, {0x4D, 0x08, 2}, {0x50, 0x05, 2}, {0x51, 0xF5, 2},
727 {0x52, 0x04, 2}, {0x53, 0xA0, 2}, {0x54, 0x1F, 2}, {0x55, 0x23, 2},
728 {0x56, 0x45, 2}, {0x57, 0x67, 2}, {0x58, 0x08, 2}, {0x59, 0x08, 2},
729 {0x5A, 0x08, 2}, {0x5B, 0x08, 2}, {0x60, 0x08, 2}, {0x61, 0x08, 2},
730 {0x62, 0x08, 2}, {0x63, 0x08, 2}, {0x64, 0xCF, 2}, {0x72, 0x56, 2},
731 {0x73, 0x9A, 2},
732
733 {0x34, 0xF0, 0}, {0x35, 0x0F, 0}, {0x5B, 0x40, 0}, {0x84, 0x88, 0},
734 {0x85, 0x24, 0}, {0x88, 0x54, 0}, {0x8B, 0xB8, 0}, {0x8C, 0x07, 0},
735 {0x8D, 0x00, 0}, {0x94, 0x1B, 0}, {0x95, 0x12, 0}, {0x96, 0x00, 0},
736 {0x97, 0x06, 0}, {0x9D, 0x1A, 0}, {0x9F, 0x10, 0}, {0xB4, 0x22, 0},
737 {0xBE, 0x80, 0}, {0xDB, 0x00, 0}, {0xEE, 0x00, 0}, {0x91, 0x03, 0},
738
739 {0x4C, 0x00, 2}, {0x9F, 0x00, 3}, {0x8C, 0x01, 0}, {0x8D, 0x10, 0},
740 {0x8E, 0x08, 0}, {0x8F, 0x00, 0}
741 };
742
743 static int rtl8187b_init_hw(struct ieee80211_hw *dev)
744 {
745 struct rtl8187_priv *priv = dev->priv;
746 int res, i;
747 u8 reg;
748
749 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
750 RTL818X_EEPROM_CMD_CONFIG);
751
752 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
753 reg |= RTL818X_CONFIG3_ANAPARAM_WRITE | RTL818X_CONFIG3_GNT_SELECT;
754 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg);
755 rtl818x_iowrite32(priv, &priv->map->ANAPARAM2,
756 RTL8187B_RTL8225_ANAPARAM2_ON);
757 rtl818x_iowrite32(priv, &priv->map->ANAPARAM,
758 RTL8187B_RTL8225_ANAPARAM_ON);
759 rtl818x_iowrite8(priv, &priv->map->ANAPARAM3,
760 RTL8187B_RTL8225_ANAPARAM3_ON);
761
762 rtl818x_iowrite8(priv, (u8 *)0xFF61, 0x10);
763 reg = rtl818x_ioread8(priv, (u8 *)0xFF62);
764 rtl818x_iowrite8(priv, (u8 *)0xFF62, reg & ~(1 << 5));
765 rtl818x_iowrite8(priv, (u8 *)0xFF62, reg | (1 << 5));
766
767 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
768 reg &= ~RTL818X_CONFIG3_ANAPARAM_WRITE;
769 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg);
770
771 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
772 RTL818X_EEPROM_CMD_NORMAL);
773
774 res = rtl8187_cmd_reset(dev);
775 if (res)
776 return res;
777
778 rtl818x_iowrite16(priv, (__le16 *)0xFF2D, 0x0FFF);
779 reg = rtl818x_ioread8(priv, &priv->map->CW_CONF);
780 reg |= RTL818X_CW_CONF_PERPACKET_RETRY_SHIFT;
781 rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg);
782 reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL);
783 reg |= RTL818X_TX_AGC_CTL_PERPACKET_GAIN_SHIFT |
784 RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT;
785 rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg);
786
787 rtl818x_iowrite16_idx(priv, (__le16 *)0xFFE0, 0x0FFF, 1);
788
789 rtl818x_iowrite16(priv, &priv->map->BEACON_INTERVAL, 100);
790 rtl818x_iowrite16(priv, &priv->map->ATIM_WND, 2);
791 rtl818x_iowrite16_idx(priv, (__le16 *)0xFFD4, 0xFFFF, 1);
792
793 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
794 RTL818X_EEPROM_CMD_CONFIG);
795 reg = rtl818x_ioread8(priv, &priv->map->CONFIG1);
796 rtl818x_iowrite8(priv, &priv->map->CONFIG1, (reg & 0x3F) | 0x80);
797 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
798 RTL818X_EEPROM_CMD_NORMAL);
799
800 rtl818x_iowrite8(priv, &priv->map->WPA_CONF, 0);
801 for (i = 0; i < ARRAY_SIZE(rtl8187b_reg_table); i++) {
802 rtl818x_iowrite8_idx(priv,
803 (u8 *)(uintptr_t)
804 (rtl8187b_reg_table[i][0] | 0xFF00),
805 rtl8187b_reg_table[i][1],
806 rtl8187b_reg_table[i][2]);
807 }
808
809 rtl818x_iowrite16(priv, &priv->map->TID_AC_MAP, 0xFA50);
810 rtl818x_iowrite16(priv, &priv->map->INT_MIG, 0);
811
812 rtl818x_iowrite32_idx(priv, (__le32 *)0xFFF0, 0, 1);
813 rtl818x_iowrite32_idx(priv, (__le32 *)0xFFF4, 0, 1);
814 rtl818x_iowrite8_idx(priv, (u8 *)0xFFF8, 0, 1);
815
816 rtl818x_iowrite32(priv, &priv->map->RF_TIMING, 0x00004001);
817
818 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF72, 0x569A, 2);
819
820 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
821 RTL818X_EEPROM_CMD_CONFIG);
822 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
823 reg |= RTL818X_CONFIG3_ANAPARAM_WRITE;
824 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg);
825 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
826 RTL818X_EEPROM_CMD_NORMAL);
827
828 rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, 0x0480);
829 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0x2488);
830 rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x1FFF);
831 msleep(100);
832
833 priv->rf->init(dev);
834
835 reg = RTL818X_CMD_TX_ENABLE | RTL818X_CMD_RX_ENABLE;
836 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
837 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF);
838
839 rtl818x_iowrite8(priv, (u8 *)0xFE41, 0xF4);
840 rtl818x_iowrite8(priv, (u8 *)0xFE40, 0x00);
841 rtl818x_iowrite8(priv, (u8 *)0xFE42, 0x00);
842 rtl818x_iowrite8(priv, (u8 *)0xFE42, 0x01);
843 rtl818x_iowrite8(priv, (u8 *)0xFE40, 0x0F);
844 rtl818x_iowrite8(priv, (u8 *)0xFE42, 0x00);
845 rtl818x_iowrite8(priv, (u8 *)0xFE42, 0x01);
846
847 reg = rtl818x_ioread8(priv, (u8 *)0xFFDB);
848 rtl818x_iowrite8(priv, (u8 *)0xFFDB, reg | (1 << 2));
849 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF72, 0x59FA, 3);
850 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF74, 0x59D2, 3);
851 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF76, 0x59D2, 3);
852 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF78, 0x19FA, 3);
853 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF7A, 0x19FA, 3);
854 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF7C, 0x00D0, 3);
855 rtl818x_iowrite8(priv, (u8 *)0xFF61, 0);
856 rtl818x_iowrite8_idx(priv, (u8 *)0xFF80, 0x0F, 1);
857 rtl818x_iowrite8_idx(priv, (u8 *)0xFF83, 0x03, 1);
858 rtl818x_iowrite8(priv, (u8 *)0xFFDA, 0x10);
859 rtl818x_iowrite8_idx(priv, (u8 *)0xFF4D, 0x08, 2);
860
861 rtl818x_iowrite32(priv, &priv->map->HSSI_PARA, 0x0600321B);
862
863 rtl818x_iowrite16_idx(priv, (__le16 *)0xFFEC, 0x0800, 1);
864
865 priv->slot_time = 0x9;
866 priv->aifsn[0] = 2; /* AIFSN[AC_VO] */
867 priv->aifsn[1] = 2; /* AIFSN[AC_VI] */
868 priv->aifsn[2] = 7; /* AIFSN[AC_BK] */
869 priv->aifsn[3] = 3; /* AIFSN[AC_BE] */
870 rtl818x_iowrite8(priv, &priv->map->ACM_CONTROL, 0);
871
872 return 0;
873 }
874
875 static void rtl8187_work(struct work_struct *work)
876 {
877 /* The RTL8187 returns the retry count through register 0xFFFA. In
878 * addition, it appears to be a cumulative retry count, not the
879 * value for the current TX packet. When multiple TX entries are
880 * queued, the retry count will be valid for the last one in the queue.
881 * The "error" should not matter for purposes of rate setting. */
882 struct rtl8187_priv *priv = container_of(work, struct rtl8187_priv,
883 work.work);
884 struct ieee80211_tx_info *info;
885 struct ieee80211_hw *dev = priv->dev;
886 static u16 retry;
887 u16 tmp;
888
889 mutex_lock(&priv->conf_mutex);
890 tmp = rtl818x_ioread16(priv, (__le16 *)0xFFFA);
891 while (skb_queue_len(&priv->b_tx_status.queue) > 0) {
892 struct sk_buff *old_skb;
893
894 old_skb = skb_dequeue(&priv->b_tx_status.queue);
895 info = IEEE80211_SKB_CB(old_skb);
896 info->status.rates[0].count = tmp - retry + 1;
897 ieee80211_tx_status_irqsafe(dev, old_skb);
898 }
899 retry = tmp;
900 mutex_unlock(&priv->conf_mutex);
901 }
902
903 static int rtl8187_start(struct ieee80211_hw *dev)
904 {
905 struct rtl8187_priv *priv = dev->priv;
906 u32 reg;
907 int ret;
908
909 ret = (!priv->is_rtl8187b) ? rtl8187_init_hw(dev) :
910 rtl8187b_init_hw(dev);
911 if (ret)
912 return ret;
913
914 mutex_lock(&priv->conf_mutex);
915
916 init_usb_anchor(&priv->anchored);
917 priv->dev = dev;
918
919 if (priv->is_rtl8187b) {
920 reg = RTL818X_RX_CONF_MGMT |
921 RTL818X_RX_CONF_DATA |
922 RTL818X_RX_CONF_BROADCAST |
923 RTL818X_RX_CONF_NICMAC |
924 RTL818X_RX_CONF_BSSID |
925 (7 << 13 /* RX FIFO threshold NONE */) |
926 (7 << 10 /* MAX RX DMA */) |
927 RTL818X_RX_CONF_RX_AUTORESETPHY |
928 RTL818X_RX_CONF_ONLYERLPKT |
929 RTL818X_RX_CONF_MULTICAST;
930 priv->rx_conf = reg;
931 rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg);
932
933 rtl818x_iowrite32(priv, &priv->map->TX_CONF,
934 RTL818X_TX_CONF_HW_SEQNUM |
935 RTL818X_TX_CONF_DISREQQSIZE |
936 (7 << 8 /* short retry limit */) |
937 (7 << 0 /* long retry limit */) |
938 (7 << 21 /* MAX TX DMA */));
939 rtl8187_init_urbs(dev);
940 rtl8187b_init_status_urb(dev);
941 mutex_unlock(&priv->conf_mutex);
942 return 0;
943 }
944
945 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF);
946
947 rtl818x_iowrite32(priv, &priv->map->MAR[0], ~0);
948 rtl818x_iowrite32(priv, &priv->map->MAR[1], ~0);
949
950 rtl8187_init_urbs(dev);
951
952 reg = RTL818X_RX_CONF_ONLYERLPKT |
953 RTL818X_RX_CONF_RX_AUTORESETPHY |
954 RTL818X_RX_CONF_BSSID |
955 RTL818X_RX_CONF_MGMT |
956 RTL818X_RX_CONF_DATA |
957 (7 << 13 /* RX FIFO threshold NONE */) |
958 (7 << 10 /* MAX RX DMA */) |
959 RTL818X_RX_CONF_BROADCAST |
960 RTL818X_RX_CONF_NICMAC;
961
962 priv->rx_conf = reg;
963 rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg);
964
965 reg = rtl818x_ioread8(priv, &priv->map->CW_CONF);
966 reg &= ~RTL818X_CW_CONF_PERPACKET_CW_SHIFT;
967 reg |= RTL818X_CW_CONF_PERPACKET_RETRY_SHIFT;
968 rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg);
969
970 reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL);
971 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN_SHIFT;
972 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT;
973 reg &= ~RTL818X_TX_AGC_CTL_FEEDBACK_ANT;
974 rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg);
975
976 reg = RTL818X_TX_CONF_CW_MIN |
977 (7 << 21 /* MAX TX DMA */) |
978 RTL818X_TX_CONF_NO_ICV;
979 rtl818x_iowrite32(priv, &priv->map->TX_CONF, reg);
980
981 reg = rtl818x_ioread8(priv, &priv->map->CMD);
982 reg |= RTL818X_CMD_TX_ENABLE;
983 reg |= RTL818X_CMD_RX_ENABLE;
984 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
985 INIT_DELAYED_WORK(&priv->work, rtl8187_work);
986 mutex_unlock(&priv->conf_mutex);
987
988 return 0;
989 }
990
991 static void rtl8187_stop(struct ieee80211_hw *dev)
992 {
993 struct rtl8187_priv *priv = dev->priv;
994 struct sk_buff *skb;
995 u32 reg;
996
997 mutex_lock(&priv->conf_mutex);
998 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
999
1000 reg = rtl818x_ioread8(priv, &priv->map->CMD);
1001 reg &= ~RTL818X_CMD_TX_ENABLE;
1002 reg &= ~RTL818X_CMD_RX_ENABLE;
1003 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
1004
1005 priv->rf->stop(dev);
1006
1007 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
1008 reg = rtl818x_ioread8(priv, &priv->map->CONFIG4);
1009 rtl818x_iowrite8(priv, &priv->map->CONFIG4, reg | RTL818X_CONFIG4_VCOOFF);
1010 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
1011
1012 while ((skb = skb_dequeue(&priv->b_tx_status.queue)))
1013 dev_kfree_skb_any(skb);
1014
1015 usb_kill_anchored_urbs(&priv->anchored);
1016 if (!priv->is_rtl8187b)
1017 cancel_delayed_work_sync(&priv->work);
1018 mutex_unlock(&priv->conf_mutex);
1019 }
1020
1021 static int rtl8187_add_interface(struct ieee80211_hw *dev,
1022 struct ieee80211_if_init_conf *conf)
1023 {
1024 struct rtl8187_priv *priv = dev->priv;
1025 int i;
1026 int ret = -EOPNOTSUPP;
1027
1028 mutex_lock(&priv->conf_mutex);
1029 if (priv->mode != NL80211_IFTYPE_MONITOR)
1030 goto exit;
1031
1032 switch (conf->type) {
1033 case NL80211_IFTYPE_STATION:
1034 priv->mode = conf->type;
1035 break;
1036 default:
1037 goto exit;
1038 }
1039
1040 ret = 0;
1041 priv->vif = conf->vif;
1042
1043 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
1044 for (i = 0; i < ETH_ALEN; i++)
1045 rtl818x_iowrite8(priv, &priv->map->MAC[i],
1046 ((u8 *)conf->mac_addr)[i]);
1047 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
1048
1049 exit:
1050 mutex_unlock(&priv->conf_mutex);
1051 return ret;
1052 }
1053
1054 static void rtl8187_remove_interface(struct ieee80211_hw *dev,
1055 struct ieee80211_if_init_conf *conf)
1056 {
1057 struct rtl8187_priv *priv = dev->priv;
1058 mutex_lock(&priv->conf_mutex);
1059 priv->mode = NL80211_IFTYPE_MONITOR;
1060 priv->vif = NULL;
1061 mutex_unlock(&priv->conf_mutex);
1062 }
1063
1064 static int rtl8187_config(struct ieee80211_hw *dev, u32 changed)
1065 {
1066 struct rtl8187_priv *priv = dev->priv;
1067 struct ieee80211_conf *conf = &dev->conf;
1068 u32 reg;
1069
1070 mutex_lock(&priv->conf_mutex);
1071 reg = rtl818x_ioread32(priv, &priv->map->TX_CONF);
1072 /* Enable TX loopback on MAC level to avoid TX during channel
1073 * changes, as this has be seen to causes problems and the
1074 * card will stop work until next reset
1075 */
1076 rtl818x_iowrite32(priv, &priv->map->TX_CONF,
1077 reg | RTL818X_TX_CONF_LOOPBACK_MAC);
1078 priv->rf->set_chan(dev, conf);
1079 msleep(10);
1080 rtl818x_iowrite32(priv, &priv->map->TX_CONF, reg);
1081
1082 rtl818x_iowrite16(priv, &priv->map->ATIM_WND, 2);
1083 rtl818x_iowrite16(priv, &priv->map->ATIMTR_INTERVAL, 100);
1084 rtl818x_iowrite16(priv, &priv->map->BEACON_INTERVAL, 100);
1085 rtl818x_iowrite16(priv, &priv->map->BEACON_INTERVAL_TIME, 100);
1086 mutex_unlock(&priv->conf_mutex);
1087 return 0;
1088 }
1089
1090 static int rtl8187_config_interface(struct ieee80211_hw *dev,
1091 struct ieee80211_vif *vif,
1092 struct ieee80211_if_conf *conf)
1093 {
1094 struct rtl8187_priv *priv = dev->priv;
1095 int i;
1096 u8 reg;
1097
1098 mutex_lock(&priv->conf_mutex);
1099 for (i = 0; i < ETH_ALEN; i++)
1100 rtl818x_iowrite8(priv, &priv->map->BSSID[i], conf->bssid[i]);
1101
1102 if (is_valid_ether_addr(conf->bssid)) {
1103 reg = RTL818X_MSR_INFRA;
1104 if (priv->is_rtl8187b)
1105 reg |= RTL818X_MSR_ENEDCA;
1106 rtl818x_iowrite8(priv, &priv->map->MSR, reg);
1107 } else {
1108 reg = RTL818X_MSR_NO_LINK;
1109 rtl818x_iowrite8(priv, &priv->map->MSR, reg);
1110 }
1111
1112 mutex_unlock(&priv->conf_mutex);
1113 return 0;
1114 }
1115
1116 /*
1117 * With 8187B, AC_*_PARAM clashes with FEMR definition in struct rtl818x_csr for
1118 * example. Thus we have to use raw values for AC_*_PARAM register addresses.
1119 */
1120 static __le32 *rtl8187b_ac_addr[4] = {
1121 (__le32 *) 0xFFF0, /* AC_VO */
1122 (__le32 *) 0xFFF4, /* AC_VI */
1123 (__le32 *) 0xFFFC, /* AC_BK */
1124 (__le32 *) 0xFFF8, /* AC_BE */
1125 };
1126
1127 #define SIFS_TIME 0xa
1128
1129 static void rtl8187_conf_erp(struct rtl8187_priv *priv, bool use_short_slot,
1130 bool use_short_preamble)
1131 {
1132 if (priv->is_rtl8187b) {
1133 u8 difs, eifs;
1134 u16 ack_timeout;
1135 int queue;
1136
1137 if (use_short_slot) {
1138 priv->slot_time = 0x9;
1139 difs = 0x1c;
1140 eifs = 0x53;
1141 } else {
1142 priv->slot_time = 0x14;
1143 difs = 0x32;
1144 eifs = 0x5b;
1145 }
1146 rtl818x_iowrite8(priv, &priv->map->SIFS, 0x22);
1147 rtl818x_iowrite8(priv, &priv->map->SLOT, priv->slot_time);
1148 rtl818x_iowrite8(priv, &priv->map->DIFS, difs);
1149
1150 /*
1151 * BRSR+1 on 8187B is in fact EIFS register
1152 * Value in units of 4 us
1153 */
1154 rtl818x_iowrite8(priv, (u8 *)&priv->map->BRSR + 1, eifs);
1155
1156 /*
1157 * For 8187B, CARRIER_SENSE_COUNTER is in fact ack timeout
1158 * register. In units of 4 us like eifs register
1159 * ack_timeout = ack duration + plcp + difs + preamble
1160 */
1161 ack_timeout = 112 + 48 + difs;
1162 if (use_short_preamble)
1163 ack_timeout += 72;
1164 else
1165 ack_timeout += 144;
1166 rtl818x_iowrite8(priv, &priv->map->CARRIER_SENSE_COUNTER,
1167 DIV_ROUND_UP(ack_timeout, 4));
1168
1169 for (queue = 0; queue < 4; queue++)
1170 rtl818x_iowrite8(priv, (u8 *) rtl8187b_ac_addr[queue],
1171 priv->aifsn[queue] * priv->slot_time +
1172 SIFS_TIME);
1173 } else {
1174 rtl818x_iowrite8(priv, &priv->map->SIFS, 0x22);
1175 if (use_short_slot) {
1176 rtl818x_iowrite8(priv, &priv->map->SLOT, 0x9);
1177 rtl818x_iowrite8(priv, &priv->map->DIFS, 0x14);
1178 rtl818x_iowrite8(priv, &priv->map->EIFS, 91 - 0x14);
1179 } else {
1180 rtl818x_iowrite8(priv, &priv->map->SLOT, 0x14);
1181 rtl818x_iowrite8(priv, &priv->map->DIFS, 0x24);
1182 rtl818x_iowrite8(priv, &priv->map->EIFS, 91 - 0x24);
1183 }
1184 }
1185 }
1186
1187 static void rtl8187_bss_info_changed(struct ieee80211_hw *dev,
1188 struct ieee80211_vif *vif,
1189 struct ieee80211_bss_conf *info,
1190 u32 changed)
1191 {
1192 struct rtl8187_priv *priv = dev->priv;
1193
1194 if (changed & (BSS_CHANGED_ERP_SLOT | BSS_CHANGED_ERP_PREAMBLE))
1195 rtl8187_conf_erp(priv, info->use_short_slot,
1196 info->use_short_preamble);
1197 }
1198
1199 static void rtl8187_configure_filter(struct ieee80211_hw *dev,
1200 unsigned int changed_flags,
1201 unsigned int *total_flags,
1202 int mc_count, struct dev_addr_list *mclist)
1203 {
1204 struct rtl8187_priv *priv = dev->priv;
1205
1206 if (changed_flags & FIF_FCSFAIL)
1207 priv->rx_conf ^= RTL818X_RX_CONF_FCS;
1208 if (changed_flags & FIF_CONTROL)
1209 priv->rx_conf ^= RTL818X_RX_CONF_CTRL;
1210 if (changed_flags & FIF_OTHER_BSS)
1211 priv->rx_conf ^= RTL818X_RX_CONF_MONITOR;
1212 if (*total_flags & FIF_ALLMULTI || mc_count > 0)
1213 priv->rx_conf |= RTL818X_RX_CONF_MULTICAST;
1214 else
1215 priv->rx_conf &= ~RTL818X_RX_CONF_MULTICAST;
1216
1217 *total_flags = 0;
1218
1219 if (priv->rx_conf & RTL818X_RX_CONF_FCS)
1220 *total_flags |= FIF_FCSFAIL;
1221 if (priv->rx_conf & RTL818X_RX_CONF_CTRL)
1222 *total_flags |= FIF_CONTROL;
1223 if (priv->rx_conf & RTL818X_RX_CONF_MONITOR)
1224 *total_flags |= FIF_OTHER_BSS;
1225 if (priv->rx_conf & RTL818X_RX_CONF_MULTICAST)
1226 *total_flags |= FIF_ALLMULTI;
1227
1228 rtl818x_iowrite32_async(priv, &priv->map->RX_CONF, priv->rx_conf);
1229 }
1230
1231 static int rtl8187_conf_tx(struct ieee80211_hw *dev, u16 queue,
1232 const struct ieee80211_tx_queue_params *params)
1233 {
1234 struct rtl8187_priv *priv = dev->priv;
1235 u8 cw_min, cw_max;
1236
1237 if (queue > 3)
1238 return -EINVAL;
1239
1240 cw_min = fls(params->cw_min);
1241 cw_max = fls(params->cw_max);
1242
1243 if (priv->is_rtl8187b) {
1244 priv->aifsn[queue] = params->aifs;
1245
1246 /*
1247 * This is the structure of AC_*_PARAM registers in 8187B:
1248 * - TXOP limit field, bit offset = 16
1249 * - ECWmax, bit offset = 12
1250 * - ECWmin, bit offset = 8
1251 * - AIFS, bit offset = 0
1252 */
1253 rtl818x_iowrite32(priv, rtl8187b_ac_addr[queue],
1254 (params->txop << 16) | (cw_max << 12) |
1255 (cw_min << 8) | (params->aifs *
1256 priv->slot_time + SIFS_TIME));
1257 } else {
1258 if (queue != 0)
1259 return -EINVAL;
1260
1261 rtl818x_iowrite8(priv, &priv->map->CW_VAL,
1262 cw_min | (cw_max << 4));
1263 }
1264 return 0;
1265 }
1266
1267 static const struct ieee80211_ops rtl8187_ops = {
1268 .tx = rtl8187_tx,
1269 .start = rtl8187_start,
1270 .stop = rtl8187_stop,
1271 .add_interface = rtl8187_add_interface,
1272 .remove_interface = rtl8187_remove_interface,
1273 .config = rtl8187_config,
1274 .config_interface = rtl8187_config_interface,
1275 .bss_info_changed = rtl8187_bss_info_changed,
1276 .configure_filter = rtl8187_configure_filter,
1277 .conf_tx = rtl8187_conf_tx
1278 };
1279
1280 static void rtl8187_eeprom_register_read(struct eeprom_93cx6 *eeprom)
1281 {
1282 struct ieee80211_hw *dev = eeprom->data;
1283 struct rtl8187_priv *priv = dev->priv;
1284 u8 reg = rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
1285
1286 eeprom->reg_data_in = reg & RTL818X_EEPROM_CMD_WRITE;
1287 eeprom->reg_data_out = reg & RTL818X_EEPROM_CMD_READ;
1288 eeprom->reg_data_clock = reg & RTL818X_EEPROM_CMD_CK;
1289 eeprom->reg_chip_select = reg & RTL818X_EEPROM_CMD_CS;
1290 }
1291
1292 static void rtl8187_eeprom_register_write(struct eeprom_93cx6 *eeprom)
1293 {
1294 struct ieee80211_hw *dev = eeprom->data;
1295 struct rtl8187_priv *priv = dev->priv;
1296 u8 reg = RTL818X_EEPROM_CMD_PROGRAM;
1297
1298 if (eeprom->reg_data_in)
1299 reg |= RTL818X_EEPROM_CMD_WRITE;
1300 if (eeprom->reg_data_out)
1301 reg |= RTL818X_EEPROM_CMD_READ;
1302 if (eeprom->reg_data_clock)
1303 reg |= RTL818X_EEPROM_CMD_CK;
1304 if (eeprom->reg_chip_select)
1305 reg |= RTL818X_EEPROM_CMD_CS;
1306
1307 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, reg);
1308 udelay(10);
1309 }
1310
1311 static int __devinit rtl8187_probe(struct usb_interface *intf,
1312 const struct usb_device_id *id)
1313 {
1314 struct usb_device *udev = interface_to_usbdev(intf);
1315 struct ieee80211_hw *dev;
1316 struct rtl8187_priv *priv;
1317 struct eeprom_93cx6 eeprom;
1318 struct ieee80211_channel *channel;
1319 const char *chip_name;
1320 u16 txpwr, reg;
1321 int err, i;
1322
1323 dev = ieee80211_alloc_hw(sizeof(*priv), &rtl8187_ops);
1324 if (!dev) {
1325 printk(KERN_ERR "rtl8187: ieee80211 alloc failed\n");
1326 return -ENOMEM;
1327 }
1328
1329 priv = dev->priv;
1330 priv->is_rtl8187b = (id->driver_info == DEVICE_RTL8187B);
1331
1332 SET_IEEE80211_DEV(dev, &intf->dev);
1333 usb_set_intfdata(intf, dev);
1334 priv->udev = udev;
1335
1336 usb_get_dev(udev);
1337
1338 skb_queue_head_init(&priv->rx_queue);
1339
1340 BUILD_BUG_ON(sizeof(priv->channels) != sizeof(rtl818x_channels));
1341 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(rtl818x_rates));
1342
1343 memcpy(priv->channels, rtl818x_channels, sizeof(rtl818x_channels));
1344 memcpy(priv->rates, rtl818x_rates, sizeof(rtl818x_rates));
1345 priv->map = (struct rtl818x_csr *)0xFF00;
1346
1347 priv->band.band = IEEE80211_BAND_2GHZ;
1348 priv->band.channels = priv->channels;
1349 priv->band.n_channels = ARRAY_SIZE(rtl818x_channels);
1350 priv->band.bitrates = priv->rates;
1351 priv->band.n_bitrates = ARRAY_SIZE(rtl818x_rates);
1352 dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
1353
1354
1355 priv->mode = NL80211_IFTYPE_MONITOR;
1356 dev->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1357 IEEE80211_HW_SIGNAL_DBM |
1358 IEEE80211_HW_RX_INCLUDES_FCS;
1359
1360 eeprom.data = dev;
1361 eeprom.register_read = rtl8187_eeprom_register_read;
1362 eeprom.register_write = rtl8187_eeprom_register_write;
1363 if (rtl818x_ioread32(priv, &priv->map->RX_CONF) & (1 << 6))
1364 eeprom.width = PCI_EEPROM_WIDTH_93C66;
1365 else
1366 eeprom.width = PCI_EEPROM_WIDTH_93C46;
1367
1368 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
1369 udelay(10);
1370
1371 eeprom_93cx6_multiread(&eeprom, RTL8187_EEPROM_MAC_ADDR,
1372 (__le16 __force *)dev->wiphy->perm_addr, 3);
1373 if (!is_valid_ether_addr(dev->wiphy->perm_addr)) {
1374 printk(KERN_WARNING "rtl8187: Invalid hwaddr! Using randomly "
1375 "generated MAC address\n");
1376 random_ether_addr(dev->wiphy->perm_addr);
1377 }
1378
1379 channel = priv->channels;
1380 for (i = 0; i < 3; i++) {
1381 eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_CHAN_1 + i,
1382 &txpwr);
1383 (*channel++).hw_value = txpwr & 0xFF;
1384 (*channel++).hw_value = txpwr >> 8;
1385 }
1386 for (i = 0; i < 2; i++) {
1387 eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_CHAN_4 + i,
1388 &txpwr);
1389 (*channel++).hw_value = txpwr & 0xFF;
1390 (*channel++).hw_value = txpwr >> 8;
1391 }
1392
1393 eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_BASE,
1394 &priv->txpwr_base);
1395
1396 reg = rtl818x_ioread8(priv, &priv->map->PGSELECT) & ~1;
1397 rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg | 1);
1398 /* 0 means asic B-cut, we should use SW 3 wire
1399 * bit-by-bit banging for radio. 1 means we can use
1400 * USB specific request to write radio registers */
1401 priv->asic_rev = rtl818x_ioread8(priv, (u8 *)0xFFFE) & 0x3;
1402 rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg);
1403 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
1404
1405 if (!priv->is_rtl8187b) {
1406 u32 reg32;
1407 reg32 = rtl818x_ioread32(priv, &priv->map->TX_CONF);
1408 reg32 &= RTL818X_TX_CONF_HWVER_MASK;
1409 switch (reg32) {
1410 case RTL818X_TX_CONF_R8187vD_B:
1411 /* Some RTL8187B devices have a USB ID of 0x8187
1412 * detect them here */
1413 chip_name = "RTL8187BvB(early)";
1414 priv->is_rtl8187b = 1;
1415 priv->hw_rev = RTL8187BvB;
1416 break;
1417 case RTL818X_TX_CONF_R8187vD:
1418 chip_name = "RTL8187vD";
1419 break;
1420 default:
1421 chip_name = "RTL8187vB (default)";
1422 }
1423 } else {
1424 /*
1425 * Force USB request to write radio registers for 8187B, Realtek
1426 * only uses it in their sources
1427 */
1428 /*if (priv->asic_rev == 0) {
1429 printk(KERN_WARNING "rtl8187: Forcing use of USB "
1430 "requests to write to radio registers\n");
1431 priv->asic_rev = 1;
1432 }*/
1433 switch (rtl818x_ioread8(priv, (u8 *)0xFFE1)) {
1434 case RTL818X_R8187B_B:
1435 chip_name = "RTL8187BvB";
1436 priv->hw_rev = RTL8187BvB;
1437 break;
1438 case RTL818X_R8187B_D:
1439 chip_name = "RTL8187BvD";
1440 priv->hw_rev = RTL8187BvD;
1441 break;
1442 case RTL818X_R8187B_E:
1443 chip_name = "RTL8187BvE";
1444 priv->hw_rev = RTL8187BvE;
1445 break;
1446 default:
1447 chip_name = "RTL8187BvB (default)";
1448 priv->hw_rev = RTL8187BvB;
1449 }
1450 }
1451
1452 if (!priv->is_rtl8187b) {
1453 for (i = 0; i < 2; i++) {
1454 eeprom_93cx6_read(&eeprom,
1455 RTL8187_EEPROM_TXPWR_CHAN_6 + i,
1456 &txpwr);
1457 (*channel++).hw_value = txpwr & 0xFF;
1458 (*channel++).hw_value = txpwr >> 8;
1459 }
1460 } else {
1461 eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_CHAN_6,
1462 &txpwr);
1463 (*channel++).hw_value = txpwr & 0xFF;
1464
1465 eeprom_93cx6_read(&eeprom, 0x0A, &txpwr);
1466 (*channel++).hw_value = txpwr & 0xFF;
1467
1468 eeprom_93cx6_read(&eeprom, 0x1C, &txpwr);
1469 (*channel++).hw_value = txpwr & 0xFF;
1470 (*channel++).hw_value = txpwr >> 8;
1471 }
1472
1473 if (priv->is_rtl8187b)
1474 printk(KERN_WARNING "rtl8187: 8187B chip detected.\n");
1475
1476 /*
1477 * XXX: Once this driver supports anything that requires
1478 * beacons it must implement IEEE80211_TX_CTL_ASSIGN_SEQ.
1479 */
1480 dev->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
1481
1482 if ((id->driver_info == DEVICE_RTL8187) && priv->is_rtl8187b)
1483 printk(KERN_INFO "rtl8187: inconsistency between id with OEM"
1484 " info!\n");
1485
1486 priv->rf = rtl8187_detect_rf(dev);
1487 dev->extra_tx_headroom = (!priv->is_rtl8187b) ?
1488 sizeof(struct rtl8187_tx_hdr) :
1489 sizeof(struct rtl8187b_tx_hdr);
1490 if (!priv->is_rtl8187b)
1491 dev->queues = 1;
1492 else
1493 dev->queues = 4;
1494
1495 err = ieee80211_register_hw(dev);
1496 if (err) {
1497 printk(KERN_ERR "rtl8187: Cannot register device\n");
1498 goto err_free_dev;
1499 }
1500 mutex_init(&priv->conf_mutex);
1501 skb_queue_head_init(&priv->b_tx_status.queue);
1502
1503 printk(KERN_INFO "%s: hwaddr %pM, %s V%d + %s\n",
1504 wiphy_name(dev->wiphy), dev->wiphy->perm_addr,
1505 chip_name, priv->asic_rev, priv->rf->name);
1506
1507 return 0;
1508
1509 err_free_dev:
1510 ieee80211_free_hw(dev);
1511 usb_set_intfdata(intf, NULL);
1512 usb_put_dev(udev);
1513 return err;
1514 }
1515
1516 static void __devexit rtl8187_disconnect(struct usb_interface *intf)
1517 {
1518 struct ieee80211_hw *dev = usb_get_intfdata(intf);
1519 struct rtl8187_priv *priv;
1520
1521 if (!dev)
1522 return;
1523
1524 ieee80211_unregister_hw(dev);
1525
1526 priv = dev->priv;
1527 usb_reset_device(priv->udev);
1528 usb_put_dev(interface_to_usbdev(intf));
1529 ieee80211_free_hw(dev);
1530 }
1531
1532 static struct usb_driver rtl8187_driver = {
1533 .name = KBUILD_MODNAME,
1534 .id_table = rtl8187_table,
1535 .probe = rtl8187_probe,
1536 .disconnect = __devexit_p(rtl8187_disconnect),
1537 };
1538
1539 static int __init rtl8187_init(void)
1540 {
1541 return usb_register(&rtl8187_driver);
1542 }
1543
1544 static void __exit rtl8187_exit(void)
1545 {
1546 usb_deregister(&rtl8187_driver);
1547 }
1548
1549 module_init(rtl8187_init);
1550 module_exit(rtl8187_exit);
Linux kernel - Deliverables
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