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Merge branch 'for-linus' of git://git.infradead.org/ubi-2.6
[deliverable/linux.git] / drivers / net / wireless / rtlwifi / pci.c
1 /******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30 #include "core.h"
31 #include "wifi.h"
32 #include "pci.h"
33 #include "base.h"
34 #include "ps.h"
35
36 static const u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = {
37 INTEL_VENDOR_ID,
38 ATI_VENDOR_ID,
39 AMD_VENDOR_ID,
40 SIS_VENDOR_ID
41 };
42
43 /* Update PCI dependent default settings*/
44 static void _rtl_pci_update_default_setting(struct ieee80211_hw *hw)
45 {
46 struct rtl_priv *rtlpriv = rtl_priv(hw);
47 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
48 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
49 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
50 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
51
52 ppsc->reg_rfps_level = 0;
53 ppsc->b_support_aspm = 0;
54
55 /*Update PCI ASPM setting */
56 ppsc->const_amdpci_aspm = rtlpci->const_amdpci_aspm;
57 switch (rtlpci->const_pci_aspm) {
58 case 0:
59 /*No ASPM */
60 break;
61
62 case 1:
63 /*ASPM dynamically enabled/disable. */
64 ppsc->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM;
65 break;
66
67 case 2:
68 /*ASPM with Clock Req dynamically enabled/disable. */
69 ppsc->reg_rfps_level |= (RT_RF_LPS_LEVEL_ASPM |
70 RT_RF_OFF_LEVL_CLK_REQ);
71 break;
72
73 case 3:
74 /*
75 * Always enable ASPM and Clock Req
76 * from initialization to halt.
77 * */
78 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM);
79 ppsc->reg_rfps_level |= (RT_RF_PS_LEVEL_ALWAYS_ASPM |
80 RT_RF_OFF_LEVL_CLK_REQ);
81 break;
82
83 case 4:
84 /*
85 * Always enable ASPM without Clock Req
86 * from initialization to halt.
87 * */
88 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM |
89 RT_RF_OFF_LEVL_CLK_REQ);
90 ppsc->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM;
91 break;
92 }
93
94 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
95
96 /*Update Radio OFF setting */
97 switch (rtlpci->const_hwsw_rfoff_d3) {
98 case 1:
99 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
100 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
101 break;
102
103 case 2:
104 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
105 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
106 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
107 break;
108
109 case 3:
110 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3;
111 break;
112 }
113
114 /*Set HW definition to determine if it supports ASPM. */
115 switch (rtlpci->const_support_pciaspm) {
116 case 0:{
117 /*Not support ASPM. */
118 bool b_support_aspm = false;
119 ppsc->b_support_aspm = b_support_aspm;
120 break;
121 }
122 case 1:{
123 /*Support ASPM. */
124 bool b_support_aspm = true;
125 bool b_support_backdoor = true;
126 ppsc->b_support_aspm = b_support_aspm;
127
128 /*if(priv->oem_id == RT_CID_TOSHIBA &&
129 !priv->ndis_adapter.amd_l1_patch)
130 b_support_backdoor = false; */
131
132 ppsc->b_support_backdoor = b_support_backdoor;
133
134 break;
135 }
136 case 2:
137 /*ASPM value set by chipset. */
138 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL) {
139 bool b_support_aspm = true;
140 ppsc->b_support_aspm = b_support_aspm;
141 }
142 break;
143 default:
144 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
145 ("switch case not process\n"));
146 break;
147 }
148 }
149
150 static bool _rtl_pci_platform_switch_device_pci_aspm(
151 struct ieee80211_hw *hw,
152 u8 value)
153 {
154 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
155 bool bresult = false;
156
157 value |= 0x40;
158
159 pci_write_config_byte(rtlpci->pdev, 0x80, value);
160
161 return bresult;
162 }
163
164 /*When we set 0x01 to enable clk request. Set 0x0 to disable clk req.*/
165 static bool _rtl_pci_switch_clk_req(struct ieee80211_hw *hw, u8 value)
166 {
167 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
168 u8 buffer;
169 bool bresult = false;
170
171 buffer = value;
172
173 pci_write_config_byte(rtlpci->pdev, 0x81, value);
174 bresult = true;
175
176 return bresult;
177 }
178
179 /*Disable RTL8192SE ASPM & Disable Pci Bridge ASPM*/
180 static void rtl_pci_disable_aspm(struct ieee80211_hw *hw)
181 {
182 struct rtl_priv *rtlpriv = rtl_priv(hw);
183 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
184 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
185 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
186 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
187 u32 pcicfg_addrport = pcipriv->ndis_adapter.pcicfg_addrport;
188 u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
189 /*Retrieve original configuration settings. */
190 u8 linkctrl_reg = pcipriv->ndis_adapter.linkctrl_reg;
191 u16 pcibridge_linkctrlreg = pcipriv->ndis_adapter.
192 pcibridge_linkctrlreg;
193 u16 aspmlevel = 0;
194
195 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
196 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
197 ("PCI(Bridge) UNKNOWN.\n"));
198
199 return;
200 }
201
202 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
203 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
204 _rtl_pci_switch_clk_req(hw, 0x0);
205 }
206
207 if (1) {
208 /*for promising device will in L0 state after an I/O. */
209 u8 tmp_u1b;
210 pci_read_config_byte(rtlpci->pdev, 0x80, &tmp_u1b);
211 }
212
213 /*Set corresponding value. */
214 aspmlevel |= BIT(0) | BIT(1);
215 linkctrl_reg &= ~aspmlevel;
216 pcibridge_linkctrlreg &= ~(BIT(0) | BIT(1));
217
218 _rtl_pci_platform_switch_device_pci_aspm(hw, linkctrl_reg);
219 udelay(50);
220
221 /*4 Disable Pci Bridge ASPM */
222 rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
223 pcicfg_addrport + (num4bytes << 2));
224 rtl_pci_raw_write_port_uchar(PCI_CONF_DATA, pcibridge_linkctrlreg);
225
226 udelay(50);
227
228 }
229
230 /*
231 *Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for
232 *power saving We should follow the sequence to enable
233 *RTL8192SE first then enable Pci Bridge ASPM
234 *or the system will show bluescreen.
235 */
236 static void rtl_pci_enable_aspm(struct ieee80211_hw *hw)
237 {
238 struct rtl_priv *rtlpriv = rtl_priv(hw);
239 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
240 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
241 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
242 u8 pcibridge_busnum = pcipriv->ndis_adapter.pcibridge_busnum;
243 u8 pcibridge_devnum = pcipriv->ndis_adapter.pcibridge_devnum;
244 u8 pcibridge_funcnum = pcipriv->ndis_adapter.pcibridge_funcnum;
245 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
246 u32 pcicfg_addrport = pcipriv->ndis_adapter.pcicfg_addrport;
247 u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
248 u16 aspmlevel;
249 u8 u_pcibridge_aspmsetting;
250 u8 u_device_aspmsetting;
251
252 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
253 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
254 ("PCI(Bridge) UNKNOWN.\n"));
255 return;
256 }
257
258 /*4 Enable Pci Bridge ASPM */
259 rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
260 pcicfg_addrport + (num4bytes << 2));
261
262 u_pcibridge_aspmsetting =
263 pcipriv->ndis_adapter.pcibridge_linkctrlreg |
264 rtlpci->const_hostpci_aspm_setting;
265
266 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL)
267 u_pcibridge_aspmsetting &= ~BIT(0);
268
269 rtl_pci_raw_write_port_uchar(PCI_CONF_DATA, u_pcibridge_aspmsetting);
270
271 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
272 ("PlatformEnableASPM():PciBridge busnumber[%x], "
273 "DevNumbe[%x], funcnumber[%x], Write reg[%x] = %x\n",
274 pcibridge_busnum, pcibridge_devnum, pcibridge_funcnum,
275 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10),
276 u_pcibridge_aspmsetting));
277
278 udelay(50);
279
280 /*Get ASPM level (with/without Clock Req) */
281 aspmlevel = rtlpci->const_devicepci_aspm_setting;
282 u_device_aspmsetting = pcipriv->ndis_adapter.linkctrl_reg;
283
284 /*_rtl_pci_platform_switch_device_pci_aspm(dev,*/
285 /*(priv->ndis_adapter.linkctrl_reg | ASPMLevel)); */
286
287 u_device_aspmsetting |= aspmlevel;
288
289 _rtl_pci_platform_switch_device_pci_aspm(hw, u_device_aspmsetting);
290
291 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
292 _rtl_pci_switch_clk_req(hw, (ppsc->reg_rfps_level &
293 RT_RF_OFF_LEVL_CLK_REQ) ? 1 : 0);
294 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
295 }
296 udelay(200);
297 }
298
299 static bool rtl_pci_get_amd_l1_patch(struct ieee80211_hw *hw)
300 {
301 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
302 u32 pcicfg_addrport = pcipriv->ndis_adapter.pcicfg_addrport;
303
304 bool status = false;
305 u8 offset_e0;
306 unsigned offset_e4;
307
308 rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
309 pcicfg_addrport + 0xE0);
310 rtl_pci_raw_write_port_uchar(PCI_CONF_DATA, 0xA0);
311
312 rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
313 pcicfg_addrport + 0xE0);
314 rtl_pci_raw_read_port_uchar(PCI_CONF_DATA, &offset_e0);
315
316 if (offset_e0 == 0xA0) {
317 rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
318 pcicfg_addrport + 0xE4);
319 rtl_pci_raw_read_port_ulong(PCI_CONF_DATA, &offset_e4);
320 if (offset_e4 & BIT(23))
321 status = true;
322 }
323
324 return status;
325 }
326
327 static void rtl_pci_get_linkcontrol_field(struct ieee80211_hw *hw)
328 {
329 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
330 u8 capabilityoffset = pcipriv->ndis_adapter.pcibridge_pciehdr_offset;
331 u32 pcicfg_addrport = pcipriv->ndis_adapter.pcicfg_addrport;
332 u8 linkctrl_reg;
333 u8 num4bBytes;
334
335 num4bBytes = (capabilityoffset + 0x10) / 4;
336
337 /*Read Link Control Register */
338 rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
339 pcicfg_addrport + (num4bBytes << 2));
340 rtl_pci_raw_read_port_uchar(PCI_CONF_DATA, &linkctrl_reg);
341
342 pcipriv->ndis_adapter.pcibridge_linkctrlreg = linkctrl_reg;
343 }
344
345 static void rtl_pci_parse_configuration(struct pci_dev *pdev,
346 struct ieee80211_hw *hw)
347 {
348 struct rtl_priv *rtlpriv = rtl_priv(hw);
349 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
350
351 u8 tmp;
352 int pos;
353 u8 linkctrl_reg;
354
355 /*Link Control Register */
356 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
357 pci_read_config_byte(pdev, pos + PCI_EXP_LNKCTL, &linkctrl_reg);
358 pcipriv->ndis_adapter.linkctrl_reg = linkctrl_reg;
359
360 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
361 ("Link Control Register =%x\n",
362 pcipriv->ndis_adapter.linkctrl_reg));
363
364 pci_read_config_byte(pdev, 0x98, &tmp);
365 tmp |= BIT(4);
366 pci_write_config_byte(pdev, 0x98, tmp);
367
368 tmp = 0x17;
369 pci_write_config_byte(pdev, 0x70f, tmp);
370 }
371
372 static void _rtl_pci_initialize_adapter_common(struct ieee80211_hw *hw)
373 {
374 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
375
376 _rtl_pci_update_default_setting(hw);
377
378 if (ppsc->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM) {
379 /*Always enable ASPM & Clock Req. */
380 rtl_pci_enable_aspm(hw);
381 RT_SET_PS_LEVEL(ppsc, RT_RF_PS_LEVEL_ALWAYS_ASPM);
382 }
383
384 }
385
386 static void rtl_pci_init_aspm(struct ieee80211_hw *hw)
387 {
388 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
389
390 /*close ASPM for AMD defaultly */
391 rtlpci->const_amdpci_aspm = 0;
392
393 /*
394 * ASPM PS mode.
395 * 0 - Disable ASPM,
396 * 1 - Enable ASPM without Clock Req,
397 * 2 - Enable ASPM with Clock Req,
398 * 3 - Alwyas Enable ASPM with Clock Req,
399 * 4 - Always Enable ASPM without Clock Req.
400 * set defult to RTL8192CE:3 RTL8192E:2
401 * */
402 rtlpci->const_pci_aspm = 3;
403
404 /*Setting for PCI-E device */
405 rtlpci->const_devicepci_aspm_setting = 0x03;
406
407 /*Setting for PCI-E bridge */
408 rtlpci->const_hostpci_aspm_setting = 0x02;
409
410 /*
411 * In Hw/Sw Radio Off situation.
412 * 0 - Default,
413 * 1 - From ASPM setting without low Mac Pwr,
414 * 2 - From ASPM setting with low Mac Pwr,
415 * 3 - Bus D3
416 * set default to RTL8192CE:0 RTL8192SE:2
417 */
418 rtlpci->const_hwsw_rfoff_d3 = 0;
419
420 /*
421 * This setting works for those device with
422 * backdoor ASPM setting such as EPHY setting.
423 * 0 - Not support ASPM,
424 * 1 - Support ASPM,
425 * 2 - According to chipset.
426 */
427 rtlpci->const_support_pciaspm = 1;
428
429 _rtl_pci_initialize_adapter_common(hw);
430 }
431
432 static void _rtl_pci_io_handler_init(struct device *dev,
433 struct ieee80211_hw *hw)
434 {
435 struct rtl_priv *rtlpriv = rtl_priv(hw);
436
437 rtlpriv->io.dev = dev;
438
439 rtlpriv->io.write8_async = pci_write8_async;
440 rtlpriv->io.write16_async = pci_write16_async;
441 rtlpriv->io.write32_async = pci_write32_async;
442
443 rtlpriv->io.read8_sync = pci_read8_sync;
444 rtlpriv->io.read16_sync = pci_read16_sync;
445 rtlpriv->io.read32_sync = pci_read32_sync;
446
447 }
448
449 static void _rtl_pci_io_handler_release(struct ieee80211_hw *hw)
450 {
451 }
452
453 static void _rtl_pci_tx_isr(struct ieee80211_hw *hw, int prio)
454 {
455 struct rtl_priv *rtlpriv = rtl_priv(hw);
456 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
457
458 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
459
460 while (skb_queue_len(&ring->queue)) {
461 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
462 struct sk_buff *skb;
463 struct ieee80211_tx_info *info;
464
465 u8 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) entry, true,
466 HW_DESC_OWN);
467
468 /*
469 *beacon packet will only use the first
470 *descriptor defautly,and the own may not
471 *be cleared by the hardware
472 */
473 if (own)
474 return;
475 ring->idx = (ring->idx + 1) % ring->entries;
476
477 skb = __skb_dequeue(&ring->queue);
478 pci_unmap_single(rtlpci->pdev,
479 le32_to_cpu(rtlpriv->cfg->ops->
480 get_desc((u8 *) entry, true,
481 HW_DESC_TXBUFF_ADDR)),
482 skb->len, PCI_DMA_TODEVICE);
483
484 RT_TRACE(rtlpriv, (COMP_INTR | COMP_SEND), DBG_TRACE,
485 ("new ring->idx:%d, "
486 "free: skb_queue_len:%d, free: seq:%x\n",
487 ring->idx,
488 skb_queue_len(&ring->queue),
489 *(u16 *) (skb->data + 22)));
490
491 info = IEEE80211_SKB_CB(skb);
492 ieee80211_tx_info_clear_status(info);
493
494 info->flags |= IEEE80211_TX_STAT_ACK;
495 /*info->status.rates[0].count = 1; */
496
497 ieee80211_tx_status_irqsafe(hw, skb);
498
499 if ((ring->entries - skb_queue_len(&ring->queue))
500 == 2) {
501
502 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
503 ("more desc left, wake"
504 "skb_queue@%d,ring->idx = %d,"
505 "skb_queue_len = 0x%d\n",
506 prio, ring->idx,
507 skb_queue_len(&ring->queue)));
508
509 ieee80211_wake_queue(hw,
510 skb_get_queue_mapping
511 (skb));
512 }
513
514 skb = NULL;
515 }
516
517 if (((rtlpriv->link_info.num_rx_inperiod +
518 rtlpriv->link_info.num_tx_inperiod) > 8) ||
519 (rtlpriv->link_info.num_rx_inperiod > 2)) {
520 rtl_lps_leave(hw);
521 }
522 }
523
524 static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw)
525 {
526 struct rtl_priv *rtlpriv = rtl_priv(hw);
527 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
528 int rx_queue_idx = RTL_PCI_RX_MPDU_QUEUE;
529
530 struct ieee80211_rx_status rx_status = { 0 };
531 unsigned int count = rtlpci->rxringcount;
532 u8 own;
533 u8 tmp_one;
534 u32 bufferaddress;
535 bool unicast = false;
536
537 struct rtl_stats stats = {
538 .signal = 0,
539 .noise = -98,
540 .rate = 0,
541 };
542
543 /*RX NORMAL PKT */
544 while (count--) {
545 /*rx descriptor */
546 struct rtl_rx_desc *pdesc = &rtlpci->rx_ring[rx_queue_idx].desc[
547 rtlpci->rx_ring[rx_queue_idx].idx];
548 /*rx pkt */
549 struct sk_buff *skb = rtlpci->rx_ring[rx_queue_idx].rx_buf[
550 rtlpci->rx_ring[rx_queue_idx].idx];
551
552 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) pdesc,
553 false, HW_DESC_OWN);
554
555 if (own) {
556 /*wait data to be filled by hardware */
557 return;
558 } else {
559 struct ieee80211_hdr *hdr;
560 u16 fc;
561 struct sk_buff *new_skb = NULL;
562
563 rtlpriv->cfg->ops->query_rx_desc(hw, &stats,
564 &rx_status,
565 (u8 *) pdesc, skb);
566
567 pci_unmap_single(rtlpci->pdev,
568 *((dma_addr_t *) skb->cb),
569 rtlpci->rxbuffersize,
570 PCI_DMA_FROMDEVICE);
571
572 skb_put(skb, rtlpriv->cfg->ops->get_desc((u8 *) pdesc,
573 false,
574 HW_DESC_RXPKT_LEN));
575 skb_reserve(skb,
576 stats.rx_drvinfo_size + stats.rx_bufshift);
577
578 /*
579 *NOTICE This can not be use for mac80211,
580 *this is done in mac80211 code,
581 *if you done here sec DHCP will fail
582 *skb_trim(skb, skb->len - 4);
583 */
584
585 hdr = (struct ieee80211_hdr *)(skb->data);
586 fc = le16_to_cpu(hdr->frame_control);
587
588 if (!stats.b_crc) {
589 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status,
590 sizeof(rx_status));
591
592 if (is_broadcast_ether_addr(hdr->addr1))
593 ;/*TODO*/
594 else {
595 if (is_multicast_ether_addr(hdr->addr1))
596 ;/*TODO*/
597 else {
598 unicast = true;
599 rtlpriv->stats.rxbytesunicast +=
600 skb->len;
601 }
602 }
603
604 rtl_is_special_data(hw, skb, false);
605
606 if (ieee80211_is_data(fc)) {
607 rtlpriv->cfg->ops->led_control(hw,
608 LED_CTL_RX);
609
610 if (unicast)
611 rtlpriv->link_info.
612 num_rx_inperiod++;
613 }
614
615 if (unlikely(!rtl_action_proc(hw, skb,
616 false))) {
617 dev_kfree_skb_any(skb);
618 } else {
619 struct sk_buff *uskb = NULL;
620 u8 *pdata;
621 uskb = dev_alloc_skb(skb->len + 128);
622 if (!uskb) {
623 RT_TRACE(rtlpriv,
624 (COMP_INTR | COMP_RECV),
625 DBG_EMERG,
626 ("can't alloc rx skb\n"));
627 goto done;
628 }
629 memcpy(IEEE80211_SKB_RXCB(uskb),
630 &rx_status,
631 sizeof(rx_status));
632 pdata = (u8 *)skb_put(uskb, skb->len);
633 memcpy(pdata, skb->data, skb->len);
634 dev_kfree_skb_any(skb);
635
636 ieee80211_rx_irqsafe(hw, uskb);
637 }
638 } else {
639 dev_kfree_skb_any(skb);
640 }
641
642 if (((rtlpriv->link_info.num_rx_inperiod +
643 rtlpriv->link_info.num_tx_inperiod) > 8) ||
644 (rtlpriv->link_info.num_rx_inperiod > 2)) {
645 rtl_lps_leave(hw);
646 }
647
648 new_skb = dev_alloc_skb(rtlpci->rxbuffersize);
649 if (unlikely(!new_skb)) {
650 RT_TRACE(rtlpriv, (COMP_INTR | COMP_RECV),
651 DBG_EMERG,
652 ("can't alloc skb for rx\n"));
653 goto done;
654 }
655 skb = new_skb;
656 /*skb->dev = dev; */
657
658 rtlpci->rx_ring[rx_queue_idx].rx_buf[rtlpci->
659 rx_ring
660 [rx_queue_idx].
661 idx] = skb;
662 *((dma_addr_t *) skb->cb) =
663 pci_map_single(rtlpci->pdev, skb_tail_pointer(skb),
664 rtlpci->rxbuffersize,
665 PCI_DMA_FROMDEVICE);
666
667 }
668 done:
669 bufferaddress = cpu_to_le32(*((dma_addr_t *) skb->cb));
670 tmp_one = 1;
671 rtlpriv->cfg->ops->set_desc((u8 *) pdesc, false,
672 HW_DESC_RXBUFF_ADDR,
673 (u8 *)&bufferaddress);
674 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false, HW_DESC_RXOWN,
675 (u8 *)&tmp_one);
676 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false,
677 HW_DESC_RXPKT_LEN,
678 (u8 *)&rtlpci->rxbuffersize);
679
680 if (rtlpci->rx_ring[rx_queue_idx].idx ==
681 rtlpci->rxringcount - 1)
682 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false,
683 HW_DESC_RXERO,
684 (u8 *)&tmp_one);
685
686 rtlpci->rx_ring[rx_queue_idx].idx =
687 (rtlpci->rx_ring[rx_queue_idx].idx + 1) %
688 rtlpci->rxringcount;
689 }
690
691 }
692
693 void _rtl_pci_tx_interrupt(struct ieee80211_hw *hw)
694 {
695 struct rtl_priv *rtlpriv = rtl_priv(hw);
696 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
697 int prio;
698
699 for (prio = 0; prio < RTL_PCI_MAX_TX_QUEUE_COUNT; prio++) {
700 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
701
702 while (skb_queue_len(&ring->queue)) {
703 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
704 struct sk_buff *skb;
705 struct ieee80211_tx_info *info;
706 u8 own;
707
708 /*
709 *beacon packet will only use the first
710 *descriptor defautly, and the own may not
711 *be cleared by the hardware, and
712 *beacon will free in prepare beacon
713 */
714 if (prio == BEACON_QUEUE || prio == TXCMD_QUEUE ||
715 prio == HCCA_QUEUE)
716 break;
717
718 own = (u8)rtlpriv->cfg->ops->get_desc((u8 *)entry,
719 true,
720 HW_DESC_OWN);
721
722 if (own)
723 break;
724
725 skb = __skb_dequeue(&ring->queue);
726 pci_unmap_single(rtlpci->pdev,
727 le32_to_cpu(rtlpriv->cfg->ops->
728 get_desc((u8 *) entry,
729 true,
730 HW_DESC_TXBUFF_ADDR)),
731 skb->len, PCI_DMA_TODEVICE);
732
733 ring->idx = (ring->idx + 1) % ring->entries;
734
735 info = IEEE80211_SKB_CB(skb);
736 ieee80211_tx_info_clear_status(info);
737
738 info->flags |= IEEE80211_TX_STAT_ACK;
739 /*info->status.rates[0].count = 1; */
740
741 ieee80211_tx_status_irqsafe(hw, skb);
742
743 if ((ring->entries - skb_queue_len(&ring->queue))
744 == 2 && prio != BEACON_QUEUE) {
745 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
746 ("more desc left, wake "
747 "skb_queue@%d,ring->idx = %d,"
748 "skb_queue_len = 0x%d\n",
749 prio, ring->idx,
750 skb_queue_len(&ring->queue)));
751
752 ieee80211_wake_queue(hw,
753 skb_get_queue_mapping
754 (skb));
755 }
756
757 skb = NULL;
758 }
759 }
760 }
761
762 static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id)
763 {
764 struct ieee80211_hw *hw = dev_id;
765 struct rtl_priv *rtlpriv = rtl_priv(hw);
766 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
767 unsigned long flags;
768 u32 inta = 0;
769 u32 intb = 0;
770
771 if (rtlpci->irq_enabled == 0)
772 return IRQ_HANDLED;
773
774 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
775
776 /*read ISR: 4/8bytes */
777 rtlpriv->cfg->ops->interrupt_recognized(hw, &inta, &intb);
778
779 /*Shared IRQ or HW disappared */
780 if (!inta || inta == 0xffff)
781 goto done;
782
783 /*<1> beacon related */
784 if (inta & rtlpriv->cfg->maps[RTL_IMR_TBDOK]) {
785 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
786 ("beacon ok interrupt!\n"));
787 }
788
789 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_TBDER])) {
790 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
791 ("beacon err interrupt!\n"));
792 }
793
794 if (inta & rtlpriv->cfg->maps[RTL_IMR_BDOK]) {
795 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
796 ("beacon interrupt!\n"));
797 }
798
799 if (inta & rtlpriv->cfg->maps[RTL_IMR_BcnInt]) {
800 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
801 ("prepare beacon for interrupt!\n"));
802 tasklet_schedule(&rtlpriv->works.irq_prepare_bcn_tasklet);
803 }
804
805 /*<3> Tx related */
806 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_TXFOVW]))
807 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, ("IMR_TXFOVW!\n"));
808
809 if (inta & rtlpriv->cfg->maps[RTL_IMR_MGNTDOK]) {
810 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
811 ("Manage ok interrupt!\n"));
812 _rtl_pci_tx_isr(hw, MGNT_QUEUE);
813 }
814
815 if (inta & rtlpriv->cfg->maps[RTL_IMR_HIGHDOK]) {
816 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
817 ("HIGH_QUEUE ok interrupt!\n"));
818 _rtl_pci_tx_isr(hw, HIGH_QUEUE);
819 }
820
821 if (inta & rtlpriv->cfg->maps[RTL_IMR_BKDOK]) {
822 rtlpriv->link_info.num_tx_inperiod++;
823
824 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
825 ("BK Tx OK interrupt!\n"));
826 _rtl_pci_tx_isr(hw, BK_QUEUE);
827 }
828
829 if (inta & rtlpriv->cfg->maps[RTL_IMR_BEDOK]) {
830 rtlpriv->link_info.num_tx_inperiod++;
831
832 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
833 ("BE TX OK interrupt!\n"));
834 _rtl_pci_tx_isr(hw, BE_QUEUE);
835 }
836
837 if (inta & rtlpriv->cfg->maps[RTL_IMR_VIDOK]) {
838 rtlpriv->link_info.num_tx_inperiod++;
839
840 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
841 ("VI TX OK interrupt!\n"));
842 _rtl_pci_tx_isr(hw, VI_QUEUE);
843 }
844
845 if (inta & rtlpriv->cfg->maps[RTL_IMR_VODOK]) {
846 rtlpriv->link_info.num_tx_inperiod++;
847
848 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
849 ("Vo TX OK interrupt!\n"));
850 _rtl_pci_tx_isr(hw, VO_QUEUE);
851 }
852
853 /*<2> Rx related */
854 if (inta & rtlpriv->cfg->maps[RTL_IMR_ROK]) {
855 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, ("Rx ok interrupt!\n"));
856 tasklet_schedule(&rtlpriv->works.irq_tasklet);
857 }
858
859 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_RDU])) {
860 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
861 ("rx descriptor unavailable!\n"));
862 tasklet_schedule(&rtlpriv->works.irq_tasklet);
863 }
864
865 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_RXFOVW])) {
866 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, ("rx overflow !\n"));
867 tasklet_schedule(&rtlpriv->works.irq_tasklet);
868 }
869
870 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
871 return IRQ_HANDLED;
872
873 done:
874 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
875 return IRQ_HANDLED;
876 }
877
878 static void _rtl_pci_irq_tasklet(struct ieee80211_hw *hw)
879 {
880 _rtl_pci_rx_interrupt(hw);
881 }
882
883 static void _rtl_pci_prepare_bcn_tasklet(struct ieee80211_hw *hw)
884 {
885 struct rtl_priv *rtlpriv = rtl_priv(hw);
886 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
887 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
888 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[BEACON_QUEUE];
889 struct ieee80211_hdr *hdr = NULL;
890 struct ieee80211_tx_info *info = NULL;
891 struct sk_buff *pskb = NULL;
892 struct rtl_tx_desc *pdesc = NULL;
893 unsigned int queue_index;
894 u8 temp_one = 1;
895
896 ring = &rtlpci->tx_ring[BEACON_QUEUE];
897 pskb = __skb_dequeue(&ring->queue);
898 if (pskb)
899 kfree_skb(pskb);
900
901 /*NB: the beacon data buffer must be 32-bit aligned. */
902 pskb = ieee80211_beacon_get(hw, mac->vif);
903 if (pskb == NULL)
904 return;
905 hdr = (struct ieee80211_hdr *)(pskb->data);
906 info = IEEE80211_SKB_CB(pskb);
907
908 queue_index = BEACON_QUEUE;
909
910 pdesc = &ring->desc[0];
911 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *) pdesc,
912 info, pskb, queue_index);
913
914 __skb_queue_tail(&ring->queue, pskb);
915
916 rtlpriv->cfg->ops->set_desc((u8 *) pdesc, true, HW_DESC_OWN,
917 (u8 *)&temp_one);
918
919 return;
920 }
921
922 static void _rtl_pci_init_trx_var(struct ieee80211_hw *hw)
923 {
924 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
925 u8 i;
926
927 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
928 rtlpci->txringcount[i] = RT_TXDESC_NUM;
929
930 /*
931 *we just alloc 2 desc for beacon queue,
932 *because we just need first desc in hw beacon.
933 */
934 rtlpci->txringcount[BEACON_QUEUE] = 2;
935
936 /*
937 *BE queue need more descriptor for performance
938 *consideration or, No more tx desc will happen,
939 *and may cause mac80211 mem leakage.
940 */
941 rtlpci->txringcount[BE_QUEUE] = RT_TXDESC_NUM_BE_QUEUE;
942
943 rtlpci->rxbuffersize = 9100; /*2048/1024; */
944 rtlpci->rxringcount = RTL_PCI_MAX_RX_COUNT; /*64; */
945 }
946
947 static void _rtl_pci_init_struct(struct ieee80211_hw *hw,
948 struct pci_dev *pdev)
949 {
950 struct rtl_priv *rtlpriv = rtl_priv(hw);
951 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
952 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
953 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
954 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
955
956 rtlpci->up_first_time = true;
957 rtlpci->being_init_adapter = false;
958
959 rtlhal->hw = hw;
960 rtlpci->pdev = pdev;
961
962 ppsc->b_inactiveps = false;
963 ppsc->b_leisure_ps = true;
964 ppsc->b_fwctrl_lps = true;
965 ppsc->b_reg_fwctrl_lps = 3;
966 ppsc->reg_max_lps_awakeintvl = 5;
967
968 if (ppsc->b_reg_fwctrl_lps == 1)
969 ppsc->fwctrl_psmode = FW_PS_MIN_MODE;
970 else if (ppsc->b_reg_fwctrl_lps == 2)
971 ppsc->fwctrl_psmode = FW_PS_MAX_MODE;
972 else if (ppsc->b_reg_fwctrl_lps == 3)
973 ppsc->fwctrl_psmode = FW_PS_DTIM_MODE;
974
975 /*Tx/Rx related var */
976 _rtl_pci_init_trx_var(hw);
977
978 /*IBSS*/ mac->beacon_interval = 100;
979
980 /*AMPDU*/ mac->min_space_cfg = 0;
981 mac->max_mss_density = 0;
982 /*set sane AMPDU defaults */
983 mac->current_ampdu_density = 7;
984 mac->current_ampdu_factor = 3;
985
986 /*QOS*/ rtlpci->acm_method = eAcmWay2_SW;
987
988 /*task */
989 tasklet_init(&rtlpriv->works.irq_tasklet,
990 (void (*)(unsigned long))_rtl_pci_irq_tasklet,
991 (unsigned long)hw);
992 tasklet_init(&rtlpriv->works.irq_prepare_bcn_tasklet,
993 (void (*)(unsigned long))_rtl_pci_prepare_bcn_tasklet,
994 (unsigned long)hw);
995 }
996
997 static int _rtl_pci_init_tx_ring(struct ieee80211_hw *hw,
998 unsigned int prio, unsigned int entries)
999 {
1000 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1001 struct rtl_priv *rtlpriv = rtl_priv(hw);
1002 struct rtl_tx_desc *ring;
1003 dma_addr_t dma;
1004 u32 nextdescaddress;
1005 int i;
1006
1007 ring = pci_alloc_consistent(rtlpci->pdev,
1008 sizeof(*ring) * entries, &dma);
1009
1010 if (!ring || (unsigned long)ring & 0xFF) {
1011 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1012 ("Cannot allocate TX ring (prio = %d)\n", prio));
1013 return -ENOMEM;
1014 }
1015
1016 memset(ring, 0, sizeof(*ring) * entries);
1017 rtlpci->tx_ring[prio].desc = ring;
1018 rtlpci->tx_ring[prio].dma = dma;
1019 rtlpci->tx_ring[prio].idx = 0;
1020 rtlpci->tx_ring[prio].entries = entries;
1021 skb_queue_head_init(&rtlpci->tx_ring[prio].queue);
1022
1023 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1024 ("queue:%d, ring_addr:%p\n", prio, ring));
1025
1026 for (i = 0; i < entries; i++) {
1027 nextdescaddress = cpu_to_le32((u32) dma +
1028 ((i + 1) % entries) *
1029 sizeof(*ring));
1030
1031 rtlpriv->cfg->ops->set_desc((u8 *)&(ring[i]),
1032 true, HW_DESC_TX_NEXTDESC_ADDR,
1033 (u8 *)&nextdescaddress);
1034 }
1035
1036 return 0;
1037 }
1038
1039 static int _rtl_pci_init_rx_ring(struct ieee80211_hw *hw)
1040 {
1041 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1042 struct rtl_priv *rtlpriv = rtl_priv(hw);
1043 struct rtl_rx_desc *entry = NULL;
1044 int i, rx_queue_idx;
1045 u8 tmp_one = 1;
1046
1047 /*
1048 *rx_queue_idx 0:RX_MPDU_QUEUE
1049 *rx_queue_idx 1:RX_CMD_QUEUE
1050 */
1051 for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
1052 rx_queue_idx++) {
1053 rtlpci->rx_ring[rx_queue_idx].desc =
1054 pci_alloc_consistent(rtlpci->pdev,
1055 sizeof(*rtlpci->rx_ring[rx_queue_idx].
1056 desc) * rtlpci->rxringcount,
1057 &rtlpci->rx_ring[rx_queue_idx].dma);
1058
1059 if (!rtlpci->rx_ring[rx_queue_idx].desc ||
1060 (unsigned long)rtlpci->rx_ring[rx_queue_idx].desc & 0xFF) {
1061 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1062 ("Cannot allocate RX ring\n"));
1063 return -ENOMEM;
1064 }
1065
1066 memset(rtlpci->rx_ring[rx_queue_idx].desc, 0,
1067 sizeof(*rtlpci->rx_ring[rx_queue_idx].desc) *
1068 rtlpci->rxringcount);
1069
1070 rtlpci->rx_ring[rx_queue_idx].idx = 0;
1071
1072 for (i = 0; i < rtlpci->rxringcount; i++) {
1073 struct sk_buff *skb =
1074 dev_alloc_skb(rtlpci->rxbuffersize);
1075 u32 bufferaddress;
1076 if (!skb)
1077 return 0;
1078 entry = &rtlpci->rx_ring[rx_queue_idx].desc[i];
1079
1080 /*skb->dev = dev; */
1081
1082 rtlpci->rx_ring[rx_queue_idx].rx_buf[i] = skb;
1083
1084 /*
1085 *just set skb->cb to mapping addr
1086 *for pci_unmap_single use
1087 */
1088 *((dma_addr_t *) skb->cb) =
1089 pci_map_single(rtlpci->pdev, skb_tail_pointer(skb),
1090 rtlpci->rxbuffersize,
1091 PCI_DMA_FROMDEVICE);
1092
1093 bufferaddress = cpu_to_le32(*((dma_addr_t *)skb->cb));
1094 rtlpriv->cfg->ops->set_desc((u8 *)entry, false,
1095 HW_DESC_RXBUFF_ADDR,
1096 (u8 *)&bufferaddress);
1097 rtlpriv->cfg->ops->set_desc((u8 *)entry, false,
1098 HW_DESC_RXPKT_LEN,
1099 (u8 *)&rtlpci->
1100 rxbuffersize);
1101 rtlpriv->cfg->ops->set_desc((u8 *) entry, false,
1102 HW_DESC_RXOWN,
1103 (u8 *)&tmp_one);
1104 }
1105
1106 rtlpriv->cfg->ops->set_desc((u8 *) entry, false,
1107 HW_DESC_RXERO, (u8 *)&tmp_one);
1108 }
1109 return 0;
1110 }
1111
1112 static void _rtl_pci_free_tx_ring(struct ieee80211_hw *hw,
1113 unsigned int prio)
1114 {
1115 struct rtl_priv *rtlpriv = rtl_priv(hw);
1116 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1117 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
1118
1119 while (skb_queue_len(&ring->queue)) {
1120 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
1121 struct sk_buff *skb = __skb_dequeue(&ring->queue);
1122
1123 pci_unmap_single(rtlpci->pdev,
1124 le32_to_cpu(rtlpriv->cfg->
1125 ops->get_desc((u8 *) entry, true,
1126 HW_DESC_TXBUFF_ADDR)),
1127 skb->len, PCI_DMA_TODEVICE);
1128 kfree_skb(skb);
1129 ring->idx = (ring->idx + 1) % ring->entries;
1130 }
1131
1132 pci_free_consistent(rtlpci->pdev,
1133 sizeof(*ring->desc) * ring->entries,
1134 ring->desc, ring->dma);
1135 ring->desc = NULL;
1136 }
1137
1138 static void _rtl_pci_free_rx_ring(struct rtl_pci *rtlpci)
1139 {
1140 int i, rx_queue_idx;
1141
1142 /*rx_queue_idx 0:RX_MPDU_QUEUE */
1143 /*rx_queue_idx 1:RX_CMD_QUEUE */
1144 for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
1145 rx_queue_idx++) {
1146 for (i = 0; i < rtlpci->rxringcount; i++) {
1147 struct sk_buff *skb =
1148 rtlpci->rx_ring[rx_queue_idx].rx_buf[i];
1149 if (!skb)
1150 continue;
1151
1152 pci_unmap_single(rtlpci->pdev,
1153 *((dma_addr_t *) skb->cb),
1154 rtlpci->rxbuffersize,
1155 PCI_DMA_FROMDEVICE);
1156 kfree_skb(skb);
1157 }
1158
1159 pci_free_consistent(rtlpci->pdev,
1160 sizeof(*rtlpci->rx_ring[rx_queue_idx].
1161 desc) * rtlpci->rxringcount,
1162 rtlpci->rx_ring[rx_queue_idx].desc,
1163 rtlpci->rx_ring[rx_queue_idx].dma);
1164 rtlpci->rx_ring[rx_queue_idx].desc = NULL;
1165 }
1166 }
1167
1168 static int _rtl_pci_init_trx_ring(struct ieee80211_hw *hw)
1169 {
1170 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1171 int ret;
1172 int i;
1173
1174 ret = _rtl_pci_init_rx_ring(hw);
1175 if (ret)
1176 return ret;
1177
1178 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1179 ret = _rtl_pci_init_tx_ring(hw, i,
1180 rtlpci->txringcount[i]);
1181 if (ret)
1182 goto err_free_rings;
1183 }
1184
1185 return 0;
1186
1187 err_free_rings:
1188 _rtl_pci_free_rx_ring(rtlpci);
1189
1190 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1191 if (rtlpci->tx_ring[i].desc)
1192 _rtl_pci_free_tx_ring(hw, i);
1193
1194 return 1;
1195 }
1196
1197 static int _rtl_pci_deinit_trx_ring(struct ieee80211_hw *hw)
1198 {
1199 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1200 u32 i;
1201
1202 /*free rx rings */
1203 _rtl_pci_free_rx_ring(rtlpci);
1204
1205 /*free tx rings */
1206 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1207 _rtl_pci_free_tx_ring(hw, i);
1208
1209 return 0;
1210 }
1211
1212 int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw)
1213 {
1214 struct rtl_priv *rtlpriv = rtl_priv(hw);
1215 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1216 int i, rx_queue_idx;
1217 unsigned long flags;
1218 u8 tmp_one = 1;
1219
1220 /*rx_queue_idx 0:RX_MPDU_QUEUE */
1221 /*rx_queue_idx 1:RX_CMD_QUEUE */
1222 for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
1223 rx_queue_idx++) {
1224 /*
1225 *force the rx_ring[RX_MPDU_QUEUE/
1226 *RX_CMD_QUEUE].idx to the first one
1227 */
1228 if (rtlpci->rx_ring[rx_queue_idx].desc) {
1229 struct rtl_rx_desc *entry = NULL;
1230
1231 for (i = 0; i < rtlpci->rxringcount; i++) {
1232 entry = &rtlpci->rx_ring[rx_queue_idx].desc[i];
1233 rtlpriv->cfg->ops->set_desc((u8 *) entry,
1234 false,
1235 HW_DESC_RXOWN,
1236 (u8 *)&tmp_one);
1237 }
1238 rtlpci->rx_ring[rx_queue_idx].idx = 0;
1239 }
1240 }
1241
1242 /*
1243 *after reset, release previous pending packet,
1244 *and force the tx idx to the first one
1245 */
1246 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1247 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1248 if (rtlpci->tx_ring[i].desc) {
1249 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[i];
1250
1251 while (skb_queue_len(&ring->queue)) {
1252 struct rtl_tx_desc *entry =
1253 &ring->desc[ring->idx];
1254 struct sk_buff *skb =
1255 __skb_dequeue(&ring->queue);
1256
1257 pci_unmap_single(rtlpci->pdev,
1258 le32_to_cpu(rtlpriv->cfg->ops->
1259 get_desc((u8 *)
1260 entry,
1261 true,
1262 HW_DESC_TXBUFF_ADDR)),
1263 skb->len, PCI_DMA_TODEVICE);
1264 kfree_skb(skb);
1265 ring->idx = (ring->idx + 1) % ring->entries;
1266 }
1267 ring->idx = 0;
1268 }
1269 }
1270
1271 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1272
1273 return 0;
1274 }
1275
1276 unsigned int _rtl_mac_to_hwqueue(u16 fc,
1277 unsigned int mac80211_queue_index)
1278 {
1279 unsigned int hw_queue_index;
1280
1281 if (unlikely(ieee80211_is_beacon(fc))) {
1282 hw_queue_index = BEACON_QUEUE;
1283 goto out;
1284 }
1285
1286 if (ieee80211_is_mgmt(fc)) {
1287 hw_queue_index = MGNT_QUEUE;
1288 goto out;
1289 }
1290
1291 switch (mac80211_queue_index) {
1292 case 0:
1293 hw_queue_index = VO_QUEUE;
1294 break;
1295 case 1:
1296 hw_queue_index = VI_QUEUE;
1297 break;
1298 case 2:
1299 hw_queue_index = BE_QUEUE;;
1300 break;
1301 case 3:
1302 hw_queue_index = BK_QUEUE;
1303 break;
1304 default:
1305 hw_queue_index = BE_QUEUE;
1306 RT_ASSERT(false, ("QSLT_BE queue, skb_queue:%d\n",
1307 mac80211_queue_index));
1308 break;
1309 }
1310
1311 out:
1312 return hw_queue_index;
1313 }
1314
1315 int rtl_pci_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
1316 {
1317 struct rtl_priv *rtlpriv = rtl_priv(hw);
1318 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1319 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1320 struct rtl8192_tx_ring *ring;
1321 struct rtl_tx_desc *pdesc;
1322 u8 idx;
1323 unsigned int queue_index, hw_queue;
1324 unsigned long flags;
1325 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)(skb->data);
1326 u16 fc = le16_to_cpu(hdr->frame_control);
1327 u8 *pda_addr = hdr->addr1;
1328 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1329 /*ssn */
1330 u8 *qc = NULL;
1331 u8 tid = 0;
1332 u16 seq_number = 0;
1333 u8 own;
1334 u8 temp_one = 1;
1335
1336 if (ieee80211_is_mgmt(fc))
1337 rtl_tx_mgmt_proc(hw, skb);
1338 rtl_action_proc(hw, skb, true);
1339
1340 queue_index = skb_get_queue_mapping(skb);
1341 hw_queue = _rtl_mac_to_hwqueue(fc, queue_index);
1342
1343 if (is_multicast_ether_addr(pda_addr))
1344 rtlpriv->stats.txbytesmulticast += skb->len;
1345 else if (is_broadcast_ether_addr(pda_addr))
1346 rtlpriv->stats.txbytesbroadcast += skb->len;
1347 else
1348 rtlpriv->stats.txbytesunicast += skb->len;
1349
1350 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1351
1352 ring = &rtlpci->tx_ring[hw_queue];
1353 if (hw_queue != BEACON_QUEUE)
1354 idx = (ring->idx + skb_queue_len(&ring->queue)) %
1355 ring->entries;
1356 else
1357 idx = 0;
1358
1359 pdesc = &ring->desc[idx];
1360 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) pdesc,
1361 true, HW_DESC_OWN);
1362
1363 if ((own == 1) && (hw_queue != BEACON_QUEUE)) {
1364 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1365 ("No more TX desc@%d, ring->idx = %d,"
1366 "idx = %d, skb_queue_len = 0x%d\n",
1367 hw_queue, ring->idx, idx,
1368 skb_queue_len(&ring->queue)));
1369
1370 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1371 return skb->len;
1372 }
1373
1374 /*
1375 *if(ieee80211_is_nullfunc(fc)) {
1376 * spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1377 * return 1;
1378 *}
1379 */
1380
1381 if (ieee80211_is_data_qos(fc)) {
1382 qc = ieee80211_get_qos_ctl(hdr);
1383 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
1384
1385 seq_number = mac->tids[tid].seq_number;
1386 seq_number &= IEEE80211_SCTL_SEQ;
1387 /*
1388 *hdr->seq_ctrl = hdr->seq_ctrl &
1389 *cpu_to_le16(IEEE80211_SCTL_FRAG);
1390 *hdr->seq_ctrl |= cpu_to_le16(seq_number);
1391 */
1392
1393 seq_number += 1;
1394 }
1395
1396 if (ieee80211_is_data(fc))
1397 rtlpriv->cfg->ops->led_control(hw, LED_CTL_TX);
1398
1399 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *) pdesc,
1400 info, skb, hw_queue);
1401
1402 __skb_queue_tail(&ring->queue, skb);
1403
1404 rtlpriv->cfg->ops->set_desc((u8 *) pdesc, true,
1405 HW_DESC_OWN, (u8 *)&temp_one);
1406
1407 if (!ieee80211_has_morefrags(hdr->frame_control)) {
1408 if (qc)
1409 mac->tids[tid].seq_number = seq_number;
1410 }
1411
1412 if ((ring->entries - skb_queue_len(&ring->queue)) < 2 &&
1413 hw_queue != BEACON_QUEUE) {
1414
1415 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
1416 ("less desc left, stop skb_queue@%d, "
1417 "ring->idx = %d,"
1418 "idx = %d, skb_queue_len = 0x%d\n",
1419 hw_queue, ring->idx, idx,
1420 skb_queue_len(&ring->queue)));
1421
1422 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
1423 }
1424
1425 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1426
1427 rtlpriv->cfg->ops->tx_polling(hw, hw_queue);
1428
1429 return 0;
1430 }
1431
1432 void rtl_pci_deinit(struct ieee80211_hw *hw)
1433 {
1434 struct rtl_priv *rtlpriv = rtl_priv(hw);
1435 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1436
1437 _rtl_pci_deinit_trx_ring(hw);
1438
1439 synchronize_irq(rtlpci->pdev->irq);
1440 tasklet_kill(&rtlpriv->works.irq_tasklet);
1441
1442 flush_workqueue(rtlpriv->works.rtl_wq);
1443 destroy_workqueue(rtlpriv->works.rtl_wq);
1444
1445 }
1446
1447 int rtl_pci_init(struct ieee80211_hw *hw, struct pci_dev *pdev)
1448 {
1449 struct rtl_priv *rtlpriv = rtl_priv(hw);
1450 int err;
1451
1452 _rtl_pci_init_struct(hw, pdev);
1453
1454 err = _rtl_pci_init_trx_ring(hw);
1455 if (err) {
1456 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1457 ("tx ring initialization failed"));
1458 return err;
1459 }
1460
1461 return 1;
1462 }
1463
1464 int rtl_pci_start(struct ieee80211_hw *hw)
1465 {
1466 struct rtl_priv *rtlpriv = rtl_priv(hw);
1467 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1468 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1469 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1470
1471 int err;
1472
1473 rtl_pci_reset_trx_ring(hw);
1474
1475 rtlpci->driver_is_goingto_unload = false;
1476 err = rtlpriv->cfg->ops->hw_init(hw);
1477 if (err) {
1478 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1479 ("Failed to config hardware!\n"));
1480 return err;
1481 }
1482
1483 rtlpriv->cfg->ops->enable_interrupt(hw);
1484 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("enable_interrupt OK\n"));
1485
1486 rtl_init_rx_config(hw);
1487
1488 /*should after adapter start and interrupt enable. */
1489 set_hal_start(rtlhal);
1490
1491 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1492
1493 rtlpci->up_first_time = false;
1494
1495 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("OK\n"));
1496 return 0;
1497 }
1498
1499 void rtl_pci_stop(struct ieee80211_hw *hw)
1500 {
1501 struct rtl_priv *rtlpriv = rtl_priv(hw);
1502 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1503 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1504 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1505 unsigned long flags;
1506 u8 RFInProgressTimeOut = 0;
1507
1508 /*
1509 *should before disable interrrupt&adapter
1510 *and will do it immediately.
1511 */
1512 set_hal_stop(rtlhal);
1513
1514 rtlpriv->cfg->ops->disable_interrupt(hw);
1515
1516 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1517 while (ppsc->rfchange_inprogress) {
1518 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1519 if (RFInProgressTimeOut > 100) {
1520 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1521 break;
1522 }
1523 mdelay(1);
1524 RFInProgressTimeOut++;
1525 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1526 }
1527 ppsc->rfchange_inprogress = true;
1528 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1529
1530 rtlpci->driver_is_goingto_unload = true;
1531 rtlpriv->cfg->ops->hw_disable(hw);
1532 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1533
1534 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1535 ppsc->rfchange_inprogress = false;
1536 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1537
1538 rtl_pci_enable_aspm(hw);
1539 }
1540
1541 static bool _rtl_pci_find_adapter(struct pci_dev *pdev,
1542 struct ieee80211_hw *hw)
1543 {
1544 struct rtl_priv *rtlpriv = rtl_priv(hw);
1545 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1546 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1547 struct pci_dev *bridge_pdev = pdev->bus->self;
1548 u16 venderid;
1549 u16 deviceid;
1550 u8 revisionid;
1551 u16 irqline;
1552 u8 tmp;
1553
1554 venderid = pdev->vendor;
1555 deviceid = pdev->device;
1556 pci_read_config_byte(pdev, 0x8, &revisionid);
1557 pci_read_config_word(pdev, 0x3C, &irqline);
1558
1559 if (deviceid == RTL_PCI_8192_DID ||
1560 deviceid == RTL_PCI_0044_DID ||
1561 deviceid == RTL_PCI_0047_DID ||
1562 deviceid == RTL_PCI_8192SE_DID ||
1563 deviceid == RTL_PCI_8174_DID ||
1564 deviceid == RTL_PCI_8173_DID ||
1565 deviceid == RTL_PCI_8172_DID ||
1566 deviceid == RTL_PCI_8171_DID) {
1567 switch (revisionid) {
1568 case RTL_PCI_REVISION_ID_8192PCIE:
1569 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1570 ("8192 PCI-E is found - "
1571 "vid/did=%x/%x\n", venderid, deviceid));
1572 rtlhal->hw_type = HARDWARE_TYPE_RTL8192E;
1573 break;
1574 case RTL_PCI_REVISION_ID_8192SE:
1575 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1576 ("8192SE is found - "
1577 "vid/did=%x/%x\n", venderid, deviceid));
1578 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1579 break;
1580 default:
1581 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1582 ("Err: Unknown device - "
1583 "vid/did=%x/%x\n", venderid, deviceid));
1584 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1585 break;
1586
1587 }
1588 } else if (deviceid == RTL_PCI_8192CET_DID ||
1589 deviceid == RTL_PCI_8192CE_DID ||
1590 deviceid == RTL_PCI_8191CE_DID ||
1591 deviceid == RTL_PCI_8188CE_DID) {
1592 rtlhal->hw_type = HARDWARE_TYPE_RTL8192CE;
1593 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1594 ("8192C PCI-E is found - "
1595 "vid/did=%x/%x\n", venderid, deviceid));
1596 } else {
1597 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1598 ("Err: Unknown device -"
1599 " vid/did=%x/%x\n", venderid, deviceid));
1600
1601 rtlhal->hw_type = RTL_DEFAULT_HARDWARE_TYPE;
1602 }
1603
1604 /*find bus info */
1605 pcipriv->ndis_adapter.busnumber = pdev->bus->number;
1606 pcipriv->ndis_adapter.devnumber = PCI_SLOT(pdev->devfn);
1607 pcipriv->ndis_adapter.funcnumber = PCI_FUNC(pdev->devfn);
1608
1609 /*find bridge info */
1610 pcipriv->ndis_adapter.pcibridge_vendorid = bridge_pdev->vendor;
1611 for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) {
1612 if (bridge_pdev->vendor == pcibridge_vendors[tmp]) {
1613 pcipriv->ndis_adapter.pcibridge_vendor = tmp;
1614 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1615 ("Pci Bridge Vendor is found index: %d\n",
1616 tmp));
1617 break;
1618 }
1619 }
1620
1621 if (pcipriv->ndis_adapter.pcibridge_vendor !=
1622 PCI_BRIDGE_VENDOR_UNKNOWN) {
1623 pcipriv->ndis_adapter.pcibridge_busnum =
1624 bridge_pdev->bus->number;
1625 pcipriv->ndis_adapter.pcibridge_devnum =
1626 PCI_SLOT(bridge_pdev->devfn);
1627 pcipriv->ndis_adapter.pcibridge_funcnum =
1628 PCI_FUNC(bridge_pdev->devfn);
1629 pcipriv->ndis_adapter.pcibridge_pciehdr_offset =
1630 pci_pcie_cap(bridge_pdev);
1631 pcipriv->ndis_adapter.pcicfg_addrport =
1632 (pcipriv->ndis_adapter.pcibridge_busnum << 16) |
1633 (pcipriv->ndis_adapter.pcibridge_devnum << 11) |
1634 (pcipriv->ndis_adapter.pcibridge_funcnum << 8) | (1 << 31);
1635 pcipriv->ndis_adapter.num4bytes =
1636 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10) / 4;
1637
1638 rtl_pci_get_linkcontrol_field(hw);
1639
1640 if (pcipriv->ndis_adapter.pcibridge_vendor ==
1641 PCI_BRIDGE_VENDOR_AMD) {
1642 pcipriv->ndis_adapter.amd_l1_patch =
1643 rtl_pci_get_amd_l1_patch(hw);
1644 }
1645 }
1646
1647 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1648 ("pcidev busnumber:devnumber:funcnumber:"
1649 "vendor:link_ctl %d:%d:%d:%x:%x\n",
1650 pcipriv->ndis_adapter.busnumber,
1651 pcipriv->ndis_adapter.devnumber,
1652 pcipriv->ndis_adapter.funcnumber,
1653 pdev->vendor, pcipriv->ndis_adapter.linkctrl_reg));
1654
1655 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1656 ("pci_bridge busnumber:devnumber:funcnumber:vendor:"
1657 "pcie_cap:link_ctl_reg:amd %d:%d:%d:%x:%x:%x:%x\n",
1658 pcipriv->ndis_adapter.pcibridge_busnum,
1659 pcipriv->ndis_adapter.pcibridge_devnum,
1660 pcipriv->ndis_adapter.pcibridge_funcnum,
1661 pcibridge_vendors[pcipriv->ndis_adapter.pcibridge_vendor],
1662 pcipriv->ndis_adapter.pcibridge_pciehdr_offset,
1663 pcipriv->ndis_adapter.pcibridge_linkctrlreg,
1664 pcipriv->ndis_adapter.amd_l1_patch));
1665
1666 rtl_pci_parse_configuration(pdev, hw);
1667
1668 return true;
1669 }
1670
1671 int __devinit rtl_pci_probe(struct pci_dev *pdev,
1672 const struct pci_device_id *id)
1673 {
1674 struct ieee80211_hw *hw = NULL;
1675
1676 struct rtl_priv *rtlpriv = NULL;
1677 struct rtl_pci_priv *pcipriv = NULL;
1678 struct rtl_pci *rtlpci;
1679 unsigned long pmem_start, pmem_len, pmem_flags;
1680 int err;
1681
1682 err = pci_enable_device(pdev);
1683 if (err) {
1684 RT_ASSERT(false,
1685 ("%s : Cannot enable new PCI device\n",
1686 pci_name(pdev)));
1687 return err;
1688 }
1689
1690 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
1691 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
1692 RT_ASSERT(false, ("Unable to obtain 32bit DMA "
1693 "for consistent allocations\n"));
1694 pci_disable_device(pdev);
1695 return -ENOMEM;
1696 }
1697 }
1698
1699 pci_set_master(pdev);
1700
1701 hw = ieee80211_alloc_hw(sizeof(struct rtl_pci_priv) +
1702 sizeof(struct rtl_priv), &rtl_ops);
1703 if (!hw) {
1704 RT_ASSERT(false,
1705 ("%s : ieee80211 alloc failed\n", pci_name(pdev)));
1706 err = -ENOMEM;
1707 goto fail1;
1708 }
1709
1710 SET_IEEE80211_DEV(hw, &pdev->dev);
1711 pci_set_drvdata(pdev, hw);
1712
1713 rtlpriv = hw->priv;
1714 pcipriv = (void *)rtlpriv->priv;
1715 pcipriv->dev.pdev = pdev;
1716
1717 /*
1718 *init dbgp flags before all
1719 *other functions, because we will
1720 *use it in other funtions like
1721 *RT_TRACE/RT_PRINT/RTL_PRINT_DATA
1722 *you can not use these macro
1723 *before this
1724 */
1725 rtl_dbgp_flag_init(hw);
1726
1727 /* MEM map */
1728 err = pci_request_regions(pdev, KBUILD_MODNAME);
1729 if (err) {
1730 RT_ASSERT(false, ("Can't obtain PCI resources\n"));
1731 return err;
1732 }
1733
1734 pmem_start = pci_resource_start(pdev, 2);
1735 pmem_len = pci_resource_len(pdev, 2);
1736 pmem_flags = pci_resource_flags(pdev, 2);
1737
1738 /*shared mem start */
1739 rtlpriv->io.pci_mem_start =
1740 (unsigned long)pci_iomap(pdev, 2, pmem_len);
1741 if (rtlpriv->io.pci_mem_start == 0) {
1742 RT_ASSERT(false, ("Can't map PCI mem\n"));
1743 goto fail2;
1744 }
1745
1746 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1747 ("mem mapped space: start: 0x%08lx len:%08lx "
1748 "flags:%08lx, after map:0x%08lx\n",
1749 pmem_start, pmem_len, pmem_flags,
1750 rtlpriv->io.pci_mem_start));
1751
1752 /* Disable Clk Request */
1753 pci_write_config_byte(pdev, 0x81, 0);
1754 /* leave D3 mode */
1755 pci_write_config_byte(pdev, 0x44, 0);
1756 pci_write_config_byte(pdev, 0x04, 0x06);
1757 pci_write_config_byte(pdev, 0x04, 0x07);
1758
1759 /* init cfg & intf_ops */
1760 rtlpriv->rtlhal.interface = INTF_PCI;
1761 rtlpriv->cfg = (struct rtl_hal_cfg *)(id->driver_data);
1762 rtlpriv->intf_ops = &rtl_pci_ops;
1763
1764 /* find adapter */
1765 _rtl_pci_find_adapter(pdev, hw);
1766
1767 /* Init IO handler */
1768 _rtl_pci_io_handler_init(&pdev->dev, hw);
1769
1770 /*like read eeprom and so on */
1771 rtlpriv->cfg->ops->read_eeprom_info(hw);
1772
1773 if (rtlpriv->cfg->ops->init_sw_vars(hw)) {
1774 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1775 ("Can't init_sw_vars.\n"));
1776 goto fail3;
1777 }
1778
1779 rtlpriv->cfg->ops->init_sw_leds(hw);
1780
1781 /*aspm */
1782 rtl_pci_init_aspm(hw);
1783
1784 /* Init mac80211 sw */
1785 err = rtl_init_core(hw);
1786 if (err) {
1787 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1788 ("Can't allocate sw for mac80211.\n"));
1789 goto fail3;
1790 }
1791
1792 /* Init PCI sw */
1793 err = !rtl_pci_init(hw, pdev);
1794 if (err) {
1795 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1796 ("Failed to init PCI.\n"));
1797 goto fail3;
1798 }
1799
1800 err = ieee80211_register_hw(hw);
1801 if (err) {
1802 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1803 ("Can't register mac80211 hw.\n"));
1804 goto fail3;
1805 } else {
1806 rtlpriv->mac80211.mac80211_registered = 1;
1807 }
1808
1809 err = sysfs_create_group(&pdev->dev.kobj, &rtl_attribute_group);
1810 if (err) {
1811 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1812 ("failed to create sysfs device attributes\n"));
1813 goto fail3;
1814 }
1815
1816 /*init rfkill */
1817 rtl_init_rfkill(hw);
1818
1819 rtlpci = rtl_pcidev(pcipriv);
1820 err = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt,
1821 IRQF_SHARED, KBUILD_MODNAME, hw);
1822 if (err) {
1823 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1824 ("%s: failed to register IRQ handler\n",
1825 wiphy_name(hw->wiphy)));
1826 goto fail3;
1827 } else {
1828 rtlpci->irq_alloc = 1;
1829 }
1830
1831 set_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
1832 return 0;
1833
1834 fail3:
1835 pci_set_drvdata(pdev, NULL);
1836 rtl_deinit_core(hw);
1837 _rtl_pci_io_handler_release(hw);
1838 ieee80211_free_hw(hw);
1839
1840 if (rtlpriv->io.pci_mem_start != 0)
1841 pci_iounmap(pdev, (void *)rtlpriv->io.pci_mem_start);
1842
1843 fail2:
1844 pci_release_regions(pdev);
1845
1846 fail1:
1847
1848 pci_disable_device(pdev);
1849
1850 return -ENODEV;
1851
1852 }
1853 EXPORT_SYMBOL(rtl_pci_probe);
1854
1855 void rtl_pci_disconnect(struct pci_dev *pdev)
1856 {
1857 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
1858 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1859 struct rtl_priv *rtlpriv = rtl_priv(hw);
1860 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
1861 struct rtl_mac *rtlmac = rtl_mac(rtlpriv);
1862
1863 clear_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
1864
1865 sysfs_remove_group(&pdev->dev.kobj, &rtl_attribute_group);
1866
1867 /*ieee80211_unregister_hw will call ops_stop */
1868 if (rtlmac->mac80211_registered == 1) {
1869 ieee80211_unregister_hw(hw);
1870 rtlmac->mac80211_registered = 0;
1871 } else {
1872 rtl_deinit_deferred_work(hw);
1873 rtlpriv->intf_ops->adapter_stop(hw);
1874 }
1875
1876 /*deinit rfkill */
1877 rtl_deinit_rfkill(hw);
1878
1879 rtl_pci_deinit(hw);
1880 rtl_deinit_core(hw);
1881 rtlpriv->cfg->ops->deinit_sw_leds(hw);
1882 _rtl_pci_io_handler_release(hw);
1883 rtlpriv->cfg->ops->deinit_sw_vars(hw);
1884
1885 if (rtlpci->irq_alloc) {
1886 free_irq(rtlpci->pdev->irq, hw);
1887 rtlpci->irq_alloc = 0;
1888 }
1889
1890 if (rtlpriv->io.pci_mem_start != 0) {
1891 pci_iounmap(pdev, (void *)rtlpriv->io.pci_mem_start);
1892 pci_release_regions(pdev);
1893 }
1894
1895 pci_disable_device(pdev);
1896 pci_set_drvdata(pdev, NULL);
1897
1898 ieee80211_free_hw(hw);
1899 }
1900 EXPORT_SYMBOL(rtl_pci_disconnect);
1901
1902 /***************************************
1903 kernel pci power state define:
1904 PCI_D0 ((pci_power_t __force) 0)
1905 PCI_D1 ((pci_power_t __force) 1)
1906 PCI_D2 ((pci_power_t __force) 2)
1907 PCI_D3hot ((pci_power_t __force) 3)
1908 PCI_D3cold ((pci_power_t __force) 4)
1909 PCI_UNKNOWN ((pci_power_t __force) 5)
1910
1911 This function is called when system
1912 goes into suspend state mac80211 will
1913 call rtl_mac_stop() from the mac80211
1914 suspend function first, So there is
1915 no need to call hw_disable here.
1916 ****************************************/
1917 int rtl_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1918 {
1919 pci_save_state(pdev);
1920 pci_disable_device(pdev);
1921 pci_set_power_state(pdev, PCI_D3hot);
1922
1923 return 0;
1924 }
1925 EXPORT_SYMBOL(rtl_pci_suspend);
1926
1927 int rtl_pci_resume(struct pci_dev *pdev)
1928 {
1929 int ret;
1930
1931 pci_set_power_state(pdev, PCI_D0);
1932 ret = pci_enable_device(pdev);
1933 if (ret) {
1934 RT_ASSERT(false, ("ERR: <======\n"));
1935 return ret;
1936 }
1937
1938 pci_restore_state(pdev);
1939
1940 return 0;
1941 }
1942 EXPORT_SYMBOL(rtl_pci_resume);
1943
1944 struct rtl_intf_ops rtl_pci_ops = {
1945 .adapter_start = rtl_pci_start,
1946 .adapter_stop = rtl_pci_stop,
1947 .adapter_tx = rtl_pci_tx,
1948 .reset_trx_ring = rtl_pci_reset_trx_ring,
1949
1950 .disable_aspm = rtl_pci_disable_aspm,
1951 .enable_aspm = rtl_pci_enable_aspm,
1952 };
Linux kernel - Deliverables
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