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Merge git://git.samba.org/sfrench/cifs-2.6
[deliverable/linux.git] / drivers / net / wireless / rtlwifi / pci.c
1 /******************************************************************************
2 *
3 * Copyright(c) 2009-2012 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30 #include "wifi.h"
31 #include "core.h"
32 #include "pci.h"
33 #include "base.h"
34 #include "ps.h"
35 #include "efuse.h"
36 #include <linux/export.h>
37
38 static const u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = {
39 PCI_VENDOR_ID_INTEL,
40 PCI_VENDOR_ID_ATI,
41 PCI_VENDOR_ID_AMD,
42 PCI_VENDOR_ID_SI
43 };
44
45 static const u8 ac_to_hwq[] = {
46 VO_QUEUE,
47 VI_QUEUE,
48 BE_QUEUE,
49 BK_QUEUE
50 };
51
52 static u8 _rtl_mac_to_hwqueue(struct ieee80211_hw *hw,
53 struct sk_buff *skb)
54 {
55 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
56 __le16 fc = rtl_get_fc(skb);
57 u8 queue_index = skb_get_queue_mapping(skb);
58
59 if (unlikely(ieee80211_is_beacon(fc)))
60 return BEACON_QUEUE;
61 if (ieee80211_is_mgmt(fc))
62 return MGNT_QUEUE;
63 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
64 if (ieee80211_is_nullfunc(fc))
65 return HIGH_QUEUE;
66
67 return ac_to_hwq[queue_index];
68 }
69
70 /* Update PCI dependent default settings*/
71 static void _rtl_pci_update_default_setting(struct ieee80211_hw *hw)
72 {
73 struct rtl_priv *rtlpriv = rtl_priv(hw);
74 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
75 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
76 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
77 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
78 u8 init_aspm;
79
80 ppsc->reg_rfps_level = 0;
81 ppsc->support_aspm = false;
82
83 /*Update PCI ASPM setting */
84 ppsc->const_amdpci_aspm = rtlpci->const_amdpci_aspm;
85 switch (rtlpci->const_pci_aspm) {
86 case 0:
87 /*No ASPM */
88 break;
89
90 case 1:
91 /*ASPM dynamically enabled/disable. */
92 ppsc->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM;
93 break;
94
95 case 2:
96 /*ASPM with Clock Req dynamically enabled/disable. */
97 ppsc->reg_rfps_level |= (RT_RF_LPS_LEVEL_ASPM |
98 RT_RF_OFF_LEVL_CLK_REQ);
99 break;
100
101 case 3:
102 /*
103 * Always enable ASPM and Clock Req
104 * from initialization to halt.
105 * */
106 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM);
107 ppsc->reg_rfps_level |= (RT_RF_PS_LEVEL_ALWAYS_ASPM |
108 RT_RF_OFF_LEVL_CLK_REQ);
109 break;
110
111 case 4:
112 /*
113 * Always enable ASPM without Clock Req
114 * from initialization to halt.
115 * */
116 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM |
117 RT_RF_OFF_LEVL_CLK_REQ);
118 ppsc->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM;
119 break;
120 }
121
122 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
123
124 /*Update Radio OFF setting */
125 switch (rtlpci->const_hwsw_rfoff_d3) {
126 case 1:
127 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
128 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
129 break;
130
131 case 2:
132 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
133 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
134 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
135 break;
136
137 case 3:
138 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3;
139 break;
140 }
141
142 /*Set HW definition to determine if it supports ASPM. */
143 switch (rtlpci->const_support_pciaspm) {
144 case 0:{
145 /*Not support ASPM. */
146 bool support_aspm = false;
147 ppsc->support_aspm = support_aspm;
148 break;
149 }
150 case 1:{
151 /*Support ASPM. */
152 bool support_aspm = true;
153 bool support_backdoor = true;
154 ppsc->support_aspm = support_aspm;
155
156 /*if (priv->oem_id == RT_CID_TOSHIBA &&
157 !priv->ndis_adapter.amd_l1_patch)
158 support_backdoor = false; */
159
160 ppsc->support_backdoor = support_backdoor;
161
162 break;
163 }
164 case 2:
165 /*ASPM value set by chipset. */
166 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL) {
167 bool support_aspm = true;
168 ppsc->support_aspm = support_aspm;
169 }
170 break;
171 default:
172 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
173 "switch case not processed\n");
174 break;
175 }
176
177 /* toshiba aspm issue, toshiba will set aspm selfly
178 * so we should not set aspm in driver */
179 pci_read_config_byte(rtlpci->pdev, 0x80, &init_aspm);
180 if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8192SE &&
181 init_aspm == 0x43)
182 ppsc->support_aspm = false;
183 }
184
185 static bool _rtl_pci_platform_switch_device_pci_aspm(
186 struct ieee80211_hw *hw,
187 u8 value)
188 {
189 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
190 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
191
192 if (rtlhal->hw_type != HARDWARE_TYPE_RTL8192SE)
193 value |= 0x40;
194
195 pci_write_config_byte(rtlpci->pdev, 0x80, value);
196
197 return false;
198 }
199
200 /*When we set 0x01 to enable clk request. Set 0x0 to disable clk req.*/
201 static void _rtl_pci_switch_clk_req(struct ieee80211_hw *hw, u8 value)
202 {
203 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
204 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
205
206 pci_write_config_byte(rtlpci->pdev, 0x81, value);
207
208 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
209 udelay(100);
210 }
211
212 /*Disable RTL8192SE ASPM & Disable Pci Bridge ASPM*/
213 static void rtl_pci_disable_aspm(struct ieee80211_hw *hw)
214 {
215 struct rtl_priv *rtlpriv = rtl_priv(hw);
216 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
217 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
218 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
219 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
220 u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
221 /*Retrieve original configuration settings. */
222 u8 linkctrl_reg = pcipriv->ndis_adapter.linkctrl_reg;
223 u16 pcibridge_linkctrlreg = pcipriv->ndis_adapter.
224 pcibridge_linkctrlreg;
225 u16 aspmlevel = 0;
226 u8 tmp_u1b = 0;
227
228 if (!ppsc->support_aspm)
229 return;
230
231 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
232 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
233 "PCI(Bridge) UNKNOWN\n");
234
235 return;
236 }
237
238 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
239 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
240 _rtl_pci_switch_clk_req(hw, 0x0);
241 }
242
243 /*for promising device will in L0 state after an I/O. */
244 pci_read_config_byte(rtlpci->pdev, 0x80, &tmp_u1b);
245
246 /*Set corresponding value. */
247 aspmlevel |= BIT(0) | BIT(1);
248 linkctrl_reg &= ~aspmlevel;
249 pcibridge_linkctrlreg &= ~(BIT(0) | BIT(1));
250
251 _rtl_pci_platform_switch_device_pci_aspm(hw, linkctrl_reg);
252 udelay(50);
253
254 /*4 Disable Pci Bridge ASPM */
255 pci_write_config_byte(rtlpci->pdev, (num4bytes << 2),
256 pcibridge_linkctrlreg);
257
258 udelay(50);
259 }
260
261 /*
262 *Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for
263 *power saving We should follow the sequence to enable
264 *RTL8192SE first then enable Pci Bridge ASPM
265 *or the system will show bluescreen.
266 */
267 static void rtl_pci_enable_aspm(struct ieee80211_hw *hw)
268 {
269 struct rtl_priv *rtlpriv = rtl_priv(hw);
270 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
271 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
272 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
273 u8 pcibridge_busnum = pcipriv->ndis_adapter.pcibridge_busnum;
274 u8 pcibridge_devnum = pcipriv->ndis_adapter.pcibridge_devnum;
275 u8 pcibridge_funcnum = pcipriv->ndis_adapter.pcibridge_funcnum;
276 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
277 u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
278 u16 aspmlevel;
279 u8 u_pcibridge_aspmsetting;
280 u8 u_device_aspmsetting;
281
282 if (!ppsc->support_aspm)
283 return;
284
285 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
286 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
287 "PCI(Bridge) UNKNOWN\n");
288 return;
289 }
290
291 /*4 Enable Pci Bridge ASPM */
292
293 u_pcibridge_aspmsetting =
294 pcipriv->ndis_adapter.pcibridge_linkctrlreg |
295 rtlpci->const_hostpci_aspm_setting;
296
297 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL)
298 u_pcibridge_aspmsetting &= ~BIT(0);
299
300 pci_write_config_byte(rtlpci->pdev, (num4bytes << 2),
301 u_pcibridge_aspmsetting);
302
303 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
304 "PlatformEnableASPM():PciBridge busnumber[%x], DevNumbe[%x], funcnumber[%x], Write reg[%x] = %x\n",
305 pcibridge_busnum, pcibridge_devnum, pcibridge_funcnum,
306 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10),
307 u_pcibridge_aspmsetting);
308
309 udelay(50);
310
311 /*Get ASPM level (with/without Clock Req) */
312 aspmlevel = rtlpci->const_devicepci_aspm_setting;
313 u_device_aspmsetting = pcipriv->ndis_adapter.linkctrl_reg;
314
315 /*_rtl_pci_platform_switch_device_pci_aspm(dev,*/
316 /*(priv->ndis_adapter.linkctrl_reg | ASPMLevel)); */
317
318 u_device_aspmsetting |= aspmlevel;
319
320 _rtl_pci_platform_switch_device_pci_aspm(hw, u_device_aspmsetting);
321
322 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
323 _rtl_pci_switch_clk_req(hw, (ppsc->reg_rfps_level &
324 RT_RF_OFF_LEVL_CLK_REQ) ? 1 : 0);
325 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
326 }
327 udelay(100);
328 }
329
330 static bool rtl_pci_get_amd_l1_patch(struct ieee80211_hw *hw)
331 {
332 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
333
334 bool status = false;
335 u8 offset_e0;
336 unsigned offset_e4;
337
338 pci_write_config_byte(rtlpci->pdev, 0xe0, 0xa0);
339
340 pci_read_config_byte(rtlpci->pdev, 0xe0, &offset_e0);
341
342 if (offset_e0 == 0xA0) {
343 pci_read_config_dword(rtlpci->pdev, 0xe4, &offset_e4);
344 if (offset_e4 & BIT(23))
345 status = true;
346 }
347
348 return status;
349 }
350
351 static void rtl_pci_get_linkcontrol_field(struct ieee80211_hw *hw)
352 {
353 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
354 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
355 u8 capabilityoffset = pcipriv->ndis_adapter.pcibridge_pciehdr_offset;
356 u8 linkctrl_reg;
357 u8 num4bbytes;
358
359 num4bbytes = (capabilityoffset + 0x10) / 4;
360
361 /*Read Link Control Register */
362 pci_read_config_byte(rtlpci->pdev, (num4bbytes << 2), &linkctrl_reg);
363
364 pcipriv->ndis_adapter.pcibridge_linkctrlreg = linkctrl_reg;
365 }
366
367 static void rtl_pci_parse_configuration(struct pci_dev *pdev,
368 struct ieee80211_hw *hw)
369 {
370 struct rtl_priv *rtlpriv = rtl_priv(hw);
371 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
372
373 u8 tmp;
374 int pos;
375 u8 linkctrl_reg;
376
377 /*Link Control Register */
378 pos = pci_pcie_cap(pdev);
379 pci_read_config_byte(pdev, pos + PCI_EXP_LNKCTL, &linkctrl_reg);
380 pcipriv->ndis_adapter.linkctrl_reg = linkctrl_reg;
381
382 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Link Control Register =%x\n",
383 pcipriv->ndis_adapter.linkctrl_reg);
384
385 pci_read_config_byte(pdev, 0x98, &tmp);
386 tmp |= BIT(4);
387 pci_write_config_byte(pdev, 0x98, tmp);
388
389 tmp = 0x17;
390 pci_write_config_byte(pdev, 0x70f, tmp);
391 }
392
393 static void rtl_pci_init_aspm(struct ieee80211_hw *hw)
394 {
395 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
396
397 _rtl_pci_update_default_setting(hw);
398
399 if (ppsc->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM) {
400 /*Always enable ASPM & Clock Req. */
401 rtl_pci_enable_aspm(hw);
402 RT_SET_PS_LEVEL(ppsc, RT_RF_PS_LEVEL_ALWAYS_ASPM);
403 }
404
405 }
406
407 static void _rtl_pci_io_handler_init(struct device *dev,
408 struct ieee80211_hw *hw)
409 {
410 struct rtl_priv *rtlpriv = rtl_priv(hw);
411
412 rtlpriv->io.dev = dev;
413
414 rtlpriv->io.write8_async = pci_write8_async;
415 rtlpriv->io.write16_async = pci_write16_async;
416 rtlpriv->io.write32_async = pci_write32_async;
417
418 rtlpriv->io.read8_sync = pci_read8_sync;
419 rtlpriv->io.read16_sync = pci_read16_sync;
420 rtlpriv->io.read32_sync = pci_read32_sync;
421
422 }
423
424 static void _rtl_pci_io_handler_release(struct ieee80211_hw *hw)
425 {
426 }
427
428 static bool _rtl_update_earlymode_info(struct ieee80211_hw *hw,
429 struct sk_buff *skb, struct rtl_tcb_desc *tcb_desc, u8 tid)
430 {
431 struct rtl_priv *rtlpriv = rtl_priv(hw);
432 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
433 u8 additionlen = FCS_LEN;
434 struct sk_buff *next_skb;
435
436 /* here open is 4, wep/tkip is 8, aes is 12*/
437 if (info->control.hw_key)
438 additionlen += info->control.hw_key->icv_len;
439
440 /* The most skb num is 6 */
441 tcb_desc->empkt_num = 0;
442 spin_lock_bh(&rtlpriv->locks.waitq_lock);
443 skb_queue_walk(&rtlpriv->mac80211.skb_waitq[tid], next_skb) {
444 struct ieee80211_tx_info *next_info;
445
446 next_info = IEEE80211_SKB_CB(next_skb);
447 if (next_info->flags & IEEE80211_TX_CTL_AMPDU) {
448 tcb_desc->empkt_len[tcb_desc->empkt_num] =
449 next_skb->len + additionlen;
450 tcb_desc->empkt_num++;
451 } else {
452 break;
453 }
454
455 if (skb_queue_is_last(&rtlpriv->mac80211.skb_waitq[tid],
456 next_skb))
457 break;
458
459 if (tcb_desc->empkt_num >= 5)
460 break;
461 }
462 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
463
464 return true;
465 }
466
467 /* just for early mode now */
468 static void _rtl_pci_tx_chk_waitq(struct ieee80211_hw *hw)
469 {
470 struct rtl_priv *rtlpriv = rtl_priv(hw);
471 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
472 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
473 struct sk_buff *skb = NULL;
474 struct ieee80211_tx_info *info = NULL;
475 int tid;
476
477 if (!rtlpriv->rtlhal.earlymode_enable)
478 return;
479
480 /* we juse use em for BE/BK/VI/VO */
481 for (tid = 7; tid >= 0; tid--) {
482 u8 hw_queue = ac_to_hwq[rtl_tid_to_ac(hw, tid)];
483 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];
484 while (!mac->act_scanning &&
485 rtlpriv->psc.rfpwr_state == ERFON) {
486 struct rtl_tcb_desc tcb_desc;
487 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
488
489 spin_lock_bh(&rtlpriv->locks.waitq_lock);
490 if (!skb_queue_empty(&mac->skb_waitq[tid]) &&
491 (ring->entries - skb_queue_len(&ring->queue) > 5)) {
492 skb = skb_dequeue(&mac->skb_waitq[tid]);
493 } else {
494 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
495 break;
496 }
497 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
498
499 /* Some macaddr can't do early mode. like
500 * multicast/broadcast/no_qos data */
501 info = IEEE80211_SKB_CB(skb);
502 if (info->flags & IEEE80211_TX_CTL_AMPDU)
503 _rtl_update_earlymode_info(hw, skb,
504 &tcb_desc, tid);
505
506 rtlpriv->intf_ops->adapter_tx(hw, skb, &tcb_desc);
507 }
508 }
509 }
510
511
512 static void _rtl_pci_tx_isr(struct ieee80211_hw *hw, int prio)
513 {
514 struct rtl_priv *rtlpriv = rtl_priv(hw);
515 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
516
517 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
518
519 while (skb_queue_len(&ring->queue)) {
520 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
521 struct sk_buff *skb;
522 struct ieee80211_tx_info *info;
523 __le16 fc;
524 u8 tid;
525
526 u8 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) entry, true,
527 HW_DESC_OWN);
528
529 /*
530 *beacon packet will only use the first
531 *descriptor defautly,and the own may not
532 *be cleared by the hardware
533 */
534 if (own)
535 return;
536 ring->idx = (ring->idx + 1) % ring->entries;
537
538 skb = __skb_dequeue(&ring->queue);
539 pci_unmap_single(rtlpci->pdev,
540 rtlpriv->cfg->ops->
541 get_desc((u8 *) entry, true,
542 HW_DESC_TXBUFF_ADDR),
543 skb->len, PCI_DMA_TODEVICE);
544
545 /* remove early mode header */
546 if (rtlpriv->rtlhal.earlymode_enable)
547 skb_pull(skb, EM_HDR_LEN);
548
549 RT_TRACE(rtlpriv, (COMP_INTR | COMP_SEND), DBG_TRACE,
550 "new ring->idx:%d, free: skb_queue_len:%d, free: seq:%x\n",
551 ring->idx,
552 skb_queue_len(&ring->queue),
553 *(u16 *) (skb->data + 22));
554
555 if (prio == TXCMD_QUEUE) {
556 dev_kfree_skb(skb);
557 goto tx_status_ok;
558
559 }
560
561 /* for sw LPS, just after NULL skb send out, we can
562 * sure AP kown we are sleeped, our we should not let
563 * rf to sleep*/
564 fc = rtl_get_fc(skb);
565 if (ieee80211_is_nullfunc(fc)) {
566 if (ieee80211_has_pm(fc)) {
567 rtlpriv->mac80211.offchan_delay = true;
568 rtlpriv->psc.state_inap = true;
569 } else {
570 rtlpriv->psc.state_inap = false;
571 }
572 }
573
574 /* update tid tx pkt num */
575 tid = rtl_get_tid(skb);
576 if (tid <= 7)
577 rtlpriv->link_info.tidtx_inperiod[tid]++;
578
579 info = IEEE80211_SKB_CB(skb);
580 ieee80211_tx_info_clear_status(info);
581
582 info->flags |= IEEE80211_TX_STAT_ACK;
583 /*info->status.rates[0].count = 1; */
584
585 ieee80211_tx_status_irqsafe(hw, skb);
586
587 if ((ring->entries - skb_queue_len(&ring->queue))
588 == 2) {
589
590 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
591 "more desc left, wake skb_queue@%d, ring->idx = %d, skb_queue_len = 0x%d\n",
592 prio, ring->idx,
593 skb_queue_len(&ring->queue));
594
595 ieee80211_wake_queue(hw,
596 skb_get_queue_mapping
597 (skb));
598 }
599 tx_status_ok:
600 skb = NULL;
601 }
602
603 if (((rtlpriv->link_info.num_rx_inperiod +
604 rtlpriv->link_info.num_tx_inperiod) > 8) ||
605 (rtlpriv->link_info.num_rx_inperiod > 2)) {
606 schedule_work(&rtlpriv->works.lps_leave_work);
607 }
608 }
609
610 static void _rtl_receive_one(struct ieee80211_hw *hw, struct sk_buff *skb,
611 struct ieee80211_rx_status rx_status)
612 {
613 struct rtl_priv *rtlpriv = rtl_priv(hw);
614 struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
615 __le16 fc = rtl_get_fc(skb);
616 bool unicast = false;
617 struct sk_buff *uskb = NULL;
618 u8 *pdata;
619
620
621 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, sizeof(rx_status));
622
623 if (is_broadcast_ether_addr(hdr->addr1)) {
624 ;/*TODO*/
625 } else if (is_multicast_ether_addr(hdr->addr1)) {
626 ;/*TODO*/
627 } else {
628 unicast = true;
629 rtlpriv->stats.rxbytesunicast += skb->len;
630 }
631
632 rtl_is_special_data(hw, skb, false);
633
634 if (ieee80211_is_data(fc)) {
635 rtlpriv->cfg->ops->led_control(hw, LED_CTL_RX);
636
637 if (unicast)
638 rtlpriv->link_info.num_rx_inperiod++;
639 }
640
641 /* for sw lps */
642 rtl_swlps_beacon(hw, (void *)skb->data, skb->len);
643 rtl_recognize_peer(hw, (void *)skb->data, skb->len);
644 if ((rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP) &&
645 (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G) &&
646 (ieee80211_is_beacon(fc) || ieee80211_is_probe_resp(fc)))
647 return;
648
649 if (unlikely(!rtl_action_proc(hw, skb, false)))
650 return;
651
652 uskb = dev_alloc_skb(skb->len + 128);
653 if (!uskb)
654 return; /* exit if allocation failed */
655 memcpy(IEEE80211_SKB_RXCB(uskb), &rx_status, sizeof(rx_status));
656 pdata = (u8 *)skb_put(uskb, skb->len);
657 memcpy(pdata, skb->data, skb->len);
658
659 ieee80211_rx_irqsafe(hw, uskb);
660 }
661
662 static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw)
663 {
664 struct rtl_priv *rtlpriv = rtl_priv(hw);
665 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
666 int rx_queue_idx = RTL_PCI_RX_MPDU_QUEUE;
667
668 struct ieee80211_rx_status rx_status = { 0 };
669 unsigned int count = rtlpci->rxringcount;
670 u8 own;
671 u8 tmp_one;
672 u32 bufferaddress;
673
674 struct rtl_stats stats = {
675 .signal = 0,
676 .noise = -98,
677 .rate = 0,
678 };
679 int index = rtlpci->rx_ring[rx_queue_idx].idx;
680
681 /*RX NORMAL PKT */
682 while (count--) {
683 /*rx descriptor */
684 struct rtl_rx_desc *pdesc = &rtlpci->rx_ring[rx_queue_idx].desc[
685 index];
686 /*rx pkt */
687 struct sk_buff *skb = rtlpci->rx_ring[rx_queue_idx].rx_buf[
688 index];
689 struct sk_buff *new_skb = NULL;
690
691 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) pdesc,
692 false, HW_DESC_OWN);
693
694 /*wait data to be filled by hardware */
695 if (own)
696 break;
697
698 rtlpriv->cfg->ops->query_rx_desc(hw, &stats,
699 &rx_status,
700 (u8 *) pdesc, skb);
701
702 if (stats.crc || stats.hwerror)
703 goto done;
704
705 new_skb = dev_alloc_skb(rtlpci->rxbuffersize);
706 if (unlikely(!new_skb)) {
707 RT_TRACE(rtlpriv, (COMP_INTR | COMP_RECV), DBG_DMESG,
708 "can't alloc skb for rx\n");
709 goto done;
710 }
711
712 pci_unmap_single(rtlpci->pdev,
713 *((dma_addr_t *) skb->cb),
714 rtlpci->rxbuffersize,
715 PCI_DMA_FROMDEVICE);
716
717 skb_put(skb, rtlpriv->cfg->ops->get_desc((u8 *) pdesc, false,
718 HW_DESC_RXPKT_LEN));
719 skb_reserve(skb, stats.rx_drvinfo_size + stats.rx_bufshift);
720
721 /*
722 * NOTICE This can not be use for mac80211,
723 * this is done in mac80211 code,
724 * if you done here sec DHCP will fail
725 * skb_trim(skb, skb->len - 4);
726 */
727
728 _rtl_receive_one(hw, skb, rx_status);
729
730 if (((rtlpriv->link_info.num_rx_inperiod +
731 rtlpriv->link_info.num_tx_inperiod) > 8) ||
732 (rtlpriv->link_info.num_rx_inperiod > 2)) {
733 schedule_work(&rtlpriv->works.lps_leave_work);
734 }
735
736 dev_kfree_skb_any(skb);
737 skb = new_skb;
738
739 rtlpci->rx_ring[rx_queue_idx].rx_buf[index] = skb;
740 *((dma_addr_t *) skb->cb) =
741 pci_map_single(rtlpci->pdev, skb_tail_pointer(skb),
742 rtlpci->rxbuffersize,
743 PCI_DMA_FROMDEVICE);
744
745 done:
746 bufferaddress = (*((dma_addr_t *)skb->cb));
747 tmp_one = 1;
748 rtlpriv->cfg->ops->set_desc((u8 *) pdesc, false,
749 HW_DESC_RXBUFF_ADDR,
750 (u8 *)&bufferaddress);
751 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false,
752 HW_DESC_RXPKT_LEN,
753 (u8 *)&rtlpci->rxbuffersize);
754
755 if (index == rtlpci->rxringcount - 1)
756 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false,
757 HW_DESC_RXERO,
758 (u8 *)&tmp_one);
759
760 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false, HW_DESC_RXOWN,
761 (u8 *)&tmp_one);
762
763 index = (index + 1) % rtlpci->rxringcount;
764 }
765
766 rtlpci->rx_ring[rx_queue_idx].idx = index;
767 }
768
769 static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id)
770 {
771 struct ieee80211_hw *hw = dev_id;
772 struct rtl_priv *rtlpriv = rtl_priv(hw);
773 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
774 unsigned long flags;
775 u32 inta = 0;
776 u32 intb = 0;
777 irqreturn_t ret = IRQ_HANDLED;
778
779 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
780
781 /*read ISR: 4/8bytes */
782 rtlpriv->cfg->ops->interrupt_recognized(hw, &inta, &intb);
783
784 /*Shared IRQ or HW disappared */
785 if (!inta || inta == 0xffff) {
786 ret = IRQ_NONE;
787 goto done;
788 }
789
790 /*<1> beacon related */
791 if (inta & rtlpriv->cfg->maps[RTL_IMR_TBDOK]) {
792 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
793 "beacon ok interrupt!\n");
794 }
795
796 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_TBDER])) {
797 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
798 "beacon err interrupt!\n");
799 }
800
801 if (inta & rtlpriv->cfg->maps[RTL_IMR_BDOK]) {
802 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, "beacon interrupt!\n");
803 }
804
805 if (inta & rtlpriv->cfg->maps[RTL_IMR_BcnInt]) {
806 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
807 "prepare beacon for interrupt!\n");
808 tasklet_schedule(&rtlpriv->works.irq_prepare_bcn_tasklet);
809 }
810
811 /*<3> Tx related */
812 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_TXFOVW]))
813 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, "IMR_TXFOVW!\n");
814
815 if (inta & rtlpriv->cfg->maps[RTL_IMR_MGNTDOK]) {
816 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
817 "Manage ok interrupt!\n");
818 _rtl_pci_tx_isr(hw, MGNT_QUEUE);
819 }
820
821 if (inta & rtlpriv->cfg->maps[RTL_IMR_HIGHDOK]) {
822 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
823 "HIGH_QUEUE ok interrupt!\n");
824 _rtl_pci_tx_isr(hw, HIGH_QUEUE);
825 }
826
827 if (inta & rtlpriv->cfg->maps[RTL_IMR_BKDOK]) {
828 rtlpriv->link_info.num_tx_inperiod++;
829
830 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
831 "BK Tx OK interrupt!\n");
832 _rtl_pci_tx_isr(hw, BK_QUEUE);
833 }
834
835 if (inta & rtlpriv->cfg->maps[RTL_IMR_BEDOK]) {
836 rtlpriv->link_info.num_tx_inperiod++;
837
838 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
839 "BE TX OK interrupt!\n");
840 _rtl_pci_tx_isr(hw, BE_QUEUE);
841 }
842
843 if (inta & rtlpriv->cfg->maps[RTL_IMR_VIDOK]) {
844 rtlpriv->link_info.num_tx_inperiod++;
845
846 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
847 "VI TX OK interrupt!\n");
848 _rtl_pci_tx_isr(hw, VI_QUEUE);
849 }
850
851 if (inta & rtlpriv->cfg->maps[RTL_IMR_VODOK]) {
852 rtlpriv->link_info.num_tx_inperiod++;
853
854 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
855 "Vo TX OK interrupt!\n");
856 _rtl_pci_tx_isr(hw, VO_QUEUE);
857 }
858
859 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) {
860 if (inta & rtlpriv->cfg->maps[RTL_IMR_COMDOK]) {
861 rtlpriv->link_info.num_tx_inperiod++;
862
863 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
864 "CMD TX OK interrupt!\n");
865 _rtl_pci_tx_isr(hw, TXCMD_QUEUE);
866 }
867 }
868
869 /*<2> Rx related */
870 if (inta & rtlpriv->cfg->maps[RTL_IMR_ROK]) {
871 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, "Rx ok interrupt!\n");
872 _rtl_pci_rx_interrupt(hw);
873 }
874
875 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_RDU])) {
876 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
877 "rx descriptor unavailable!\n");
878 _rtl_pci_rx_interrupt(hw);
879 }
880
881 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_RXFOVW])) {
882 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, "rx overflow !\n");
883 _rtl_pci_rx_interrupt(hw);
884 }
885
886 if (rtlpriv->rtlhal.earlymode_enable)
887 tasklet_schedule(&rtlpriv->works.irq_tasklet);
888
889 done:
890 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
891 return ret;
892 }
893
894 static void _rtl_pci_irq_tasklet(struct ieee80211_hw *hw)
895 {
896 _rtl_pci_tx_chk_waitq(hw);
897 }
898
899 static void _rtl_pci_prepare_bcn_tasklet(struct ieee80211_hw *hw)
900 {
901 struct rtl_priv *rtlpriv = rtl_priv(hw);
902 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
903 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
904 struct rtl8192_tx_ring *ring = NULL;
905 struct ieee80211_hdr *hdr = NULL;
906 struct ieee80211_tx_info *info = NULL;
907 struct sk_buff *pskb = NULL;
908 struct rtl_tx_desc *pdesc = NULL;
909 struct rtl_tcb_desc tcb_desc;
910 u8 temp_one = 1;
911
912 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
913 ring = &rtlpci->tx_ring[BEACON_QUEUE];
914 pskb = __skb_dequeue(&ring->queue);
915 if (pskb) {
916 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
917 pci_unmap_single(rtlpci->pdev, rtlpriv->cfg->ops->get_desc(
918 (u8 *) entry, true, HW_DESC_TXBUFF_ADDR),
919 pskb->len, PCI_DMA_TODEVICE);
920 kfree_skb(pskb);
921 }
922
923 /*NB: the beacon data buffer must be 32-bit aligned. */
924 pskb = ieee80211_beacon_get(hw, mac->vif);
925 if (pskb == NULL)
926 return;
927 hdr = rtl_get_hdr(pskb);
928 info = IEEE80211_SKB_CB(pskb);
929 pdesc = &ring->desc[0];
930 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *) pdesc,
931 info, pskb, BEACON_QUEUE, &tcb_desc);
932
933 __skb_queue_tail(&ring->queue, pskb);
934
935 rtlpriv->cfg->ops->set_desc((u8 *) pdesc, true, HW_DESC_OWN,
936 (u8 *)&temp_one);
937
938 return;
939 }
940
941 static void rtl_lps_leave_work_callback(struct work_struct *work)
942 {
943 struct rtl_works *rtlworks =
944 container_of(work, struct rtl_works, lps_leave_work);
945 struct ieee80211_hw *hw = rtlworks->hw;
946
947 rtl_lps_leave(hw);
948 }
949
950 static void _rtl_pci_init_trx_var(struct ieee80211_hw *hw)
951 {
952 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
953 u8 i;
954
955 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
956 rtlpci->txringcount[i] = RT_TXDESC_NUM;
957
958 /*
959 *we just alloc 2 desc for beacon queue,
960 *because we just need first desc in hw beacon.
961 */
962 rtlpci->txringcount[BEACON_QUEUE] = 2;
963
964 /*
965 *BE queue need more descriptor for performance
966 *consideration or, No more tx desc will happen,
967 *and may cause mac80211 mem leakage.
968 */
969 rtlpci->txringcount[BE_QUEUE] = RT_TXDESC_NUM_BE_QUEUE;
970
971 rtlpci->rxbuffersize = 9100; /*2048/1024; */
972 rtlpci->rxringcount = RTL_PCI_MAX_RX_COUNT; /*64; */
973 }
974
975 static void _rtl_pci_init_struct(struct ieee80211_hw *hw,
976 struct pci_dev *pdev)
977 {
978 struct rtl_priv *rtlpriv = rtl_priv(hw);
979 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
980 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
981 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
982
983 rtlpci->up_first_time = true;
984 rtlpci->being_init_adapter = false;
985
986 rtlhal->hw = hw;
987 rtlpci->pdev = pdev;
988
989 /*Tx/Rx related var */
990 _rtl_pci_init_trx_var(hw);
991
992 /*IBSS*/ mac->beacon_interval = 100;
993
994 /*AMPDU*/
995 mac->min_space_cfg = 0;
996 mac->max_mss_density = 0;
997 /*set sane AMPDU defaults */
998 mac->current_ampdu_density = 7;
999 mac->current_ampdu_factor = 3;
1000
1001 /*QOS*/
1002 rtlpci->acm_method = eAcmWay2_SW;
1003
1004 /*task */
1005 tasklet_init(&rtlpriv->works.irq_tasklet,
1006 (void (*)(unsigned long))_rtl_pci_irq_tasklet,
1007 (unsigned long)hw);
1008 tasklet_init(&rtlpriv->works.irq_prepare_bcn_tasklet,
1009 (void (*)(unsigned long))_rtl_pci_prepare_bcn_tasklet,
1010 (unsigned long)hw);
1011 INIT_WORK(&rtlpriv->works.lps_leave_work, rtl_lps_leave_work_callback);
1012 }
1013
1014 static int _rtl_pci_init_tx_ring(struct ieee80211_hw *hw,
1015 unsigned int prio, unsigned int entries)
1016 {
1017 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1018 struct rtl_priv *rtlpriv = rtl_priv(hw);
1019 struct rtl_tx_desc *ring;
1020 dma_addr_t dma;
1021 u32 nextdescaddress;
1022 int i;
1023
1024 ring = pci_alloc_consistent(rtlpci->pdev,
1025 sizeof(*ring) * entries, &dma);
1026
1027 if (!ring || (unsigned long)ring & 0xFF) {
1028 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1029 "Cannot allocate TX ring (prio = %d)\n", prio);
1030 return -ENOMEM;
1031 }
1032
1033 memset(ring, 0, sizeof(*ring) * entries);
1034 rtlpci->tx_ring[prio].desc = ring;
1035 rtlpci->tx_ring[prio].dma = dma;
1036 rtlpci->tx_ring[prio].idx = 0;
1037 rtlpci->tx_ring[prio].entries = entries;
1038 skb_queue_head_init(&rtlpci->tx_ring[prio].queue);
1039
1040 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "queue:%d, ring_addr:%p\n",
1041 prio, ring);
1042
1043 for (i = 0; i < entries; i++) {
1044 nextdescaddress = (u32) dma +
1045 ((i + 1) % entries) *
1046 sizeof(*ring);
1047
1048 rtlpriv->cfg->ops->set_desc((u8 *)&(ring[i]),
1049 true, HW_DESC_TX_NEXTDESC_ADDR,
1050 (u8 *)&nextdescaddress);
1051 }
1052
1053 return 0;
1054 }
1055
1056 static int _rtl_pci_init_rx_ring(struct ieee80211_hw *hw)
1057 {
1058 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1059 struct rtl_priv *rtlpriv = rtl_priv(hw);
1060 struct rtl_rx_desc *entry = NULL;
1061 int i, rx_queue_idx;
1062 u8 tmp_one = 1;
1063
1064 /*
1065 *rx_queue_idx 0:RX_MPDU_QUEUE
1066 *rx_queue_idx 1:RX_CMD_QUEUE
1067 */
1068 for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
1069 rx_queue_idx++) {
1070 rtlpci->rx_ring[rx_queue_idx].desc =
1071 pci_alloc_consistent(rtlpci->pdev,
1072 sizeof(*rtlpci->rx_ring[rx_queue_idx].
1073 desc) * rtlpci->rxringcount,
1074 &rtlpci->rx_ring[rx_queue_idx].dma);
1075
1076 if (!rtlpci->rx_ring[rx_queue_idx].desc ||
1077 (unsigned long)rtlpci->rx_ring[rx_queue_idx].desc & 0xFF) {
1078 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1079 "Cannot allocate RX ring\n");
1080 return -ENOMEM;
1081 }
1082
1083 memset(rtlpci->rx_ring[rx_queue_idx].desc, 0,
1084 sizeof(*rtlpci->rx_ring[rx_queue_idx].desc) *
1085 rtlpci->rxringcount);
1086
1087 rtlpci->rx_ring[rx_queue_idx].idx = 0;
1088
1089 /* If amsdu_8k is disabled, set buffersize to 4096. This
1090 * change will reduce memory fragmentation.
1091 */
1092 if (rtlpci->rxbuffersize > 4096 &&
1093 rtlpriv->rtlhal.disable_amsdu_8k)
1094 rtlpci->rxbuffersize = 4096;
1095
1096 for (i = 0; i < rtlpci->rxringcount; i++) {
1097 struct sk_buff *skb =
1098 dev_alloc_skb(rtlpci->rxbuffersize);
1099 u32 bufferaddress;
1100 if (!skb)
1101 return 0;
1102 entry = &rtlpci->rx_ring[rx_queue_idx].desc[i];
1103
1104 /*skb->dev = dev; */
1105
1106 rtlpci->rx_ring[rx_queue_idx].rx_buf[i] = skb;
1107
1108 /*
1109 *just set skb->cb to mapping addr
1110 *for pci_unmap_single use
1111 */
1112 *((dma_addr_t *) skb->cb) =
1113 pci_map_single(rtlpci->pdev, skb_tail_pointer(skb),
1114 rtlpci->rxbuffersize,
1115 PCI_DMA_FROMDEVICE);
1116
1117 bufferaddress = (*((dma_addr_t *)skb->cb));
1118 rtlpriv->cfg->ops->set_desc((u8 *)entry, false,
1119 HW_DESC_RXBUFF_ADDR,
1120 (u8 *)&bufferaddress);
1121 rtlpriv->cfg->ops->set_desc((u8 *)entry, false,
1122 HW_DESC_RXPKT_LEN,
1123 (u8 *)&rtlpci->
1124 rxbuffersize);
1125 rtlpriv->cfg->ops->set_desc((u8 *) entry, false,
1126 HW_DESC_RXOWN,
1127 (u8 *)&tmp_one);
1128 }
1129
1130 rtlpriv->cfg->ops->set_desc((u8 *) entry, false,
1131 HW_DESC_RXERO, (u8 *)&tmp_one);
1132 }
1133 return 0;
1134 }
1135
1136 static void _rtl_pci_free_tx_ring(struct ieee80211_hw *hw,
1137 unsigned int prio)
1138 {
1139 struct rtl_priv *rtlpriv = rtl_priv(hw);
1140 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1141 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
1142
1143 while (skb_queue_len(&ring->queue)) {
1144 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
1145 struct sk_buff *skb = __skb_dequeue(&ring->queue);
1146
1147 pci_unmap_single(rtlpci->pdev,
1148 rtlpriv->cfg->
1149 ops->get_desc((u8 *) entry, true,
1150 HW_DESC_TXBUFF_ADDR),
1151 skb->len, PCI_DMA_TODEVICE);
1152 kfree_skb(skb);
1153 ring->idx = (ring->idx + 1) % ring->entries;
1154 }
1155
1156 if (ring->desc) {
1157 pci_free_consistent(rtlpci->pdev,
1158 sizeof(*ring->desc) * ring->entries,
1159 ring->desc, ring->dma);
1160 ring->desc = NULL;
1161 }
1162 }
1163
1164 static void _rtl_pci_free_rx_ring(struct rtl_pci *rtlpci)
1165 {
1166 int i, rx_queue_idx;
1167
1168 /*rx_queue_idx 0:RX_MPDU_QUEUE */
1169 /*rx_queue_idx 1:RX_CMD_QUEUE */
1170 for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
1171 rx_queue_idx++) {
1172 for (i = 0; i < rtlpci->rxringcount; i++) {
1173 struct sk_buff *skb =
1174 rtlpci->rx_ring[rx_queue_idx].rx_buf[i];
1175 if (!skb)
1176 continue;
1177
1178 pci_unmap_single(rtlpci->pdev,
1179 *((dma_addr_t *) skb->cb),
1180 rtlpci->rxbuffersize,
1181 PCI_DMA_FROMDEVICE);
1182 kfree_skb(skb);
1183 }
1184
1185 if (rtlpci->rx_ring[rx_queue_idx].desc) {
1186 pci_free_consistent(rtlpci->pdev,
1187 sizeof(*rtlpci->rx_ring[rx_queue_idx].
1188 desc) * rtlpci->rxringcount,
1189 rtlpci->rx_ring[rx_queue_idx].desc,
1190 rtlpci->rx_ring[rx_queue_idx].dma);
1191 rtlpci->rx_ring[rx_queue_idx].desc = NULL;
1192 }
1193 }
1194 }
1195
1196 static int _rtl_pci_init_trx_ring(struct ieee80211_hw *hw)
1197 {
1198 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1199 int ret;
1200 int i;
1201
1202 ret = _rtl_pci_init_rx_ring(hw);
1203 if (ret)
1204 return ret;
1205
1206 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1207 ret = _rtl_pci_init_tx_ring(hw, i,
1208 rtlpci->txringcount[i]);
1209 if (ret)
1210 goto err_free_rings;
1211 }
1212
1213 return 0;
1214
1215 err_free_rings:
1216 _rtl_pci_free_rx_ring(rtlpci);
1217
1218 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1219 if (rtlpci->tx_ring[i].desc)
1220 _rtl_pci_free_tx_ring(hw, i);
1221
1222 return 1;
1223 }
1224
1225 static int _rtl_pci_deinit_trx_ring(struct ieee80211_hw *hw)
1226 {
1227 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1228 u32 i;
1229
1230 /*free rx rings */
1231 _rtl_pci_free_rx_ring(rtlpci);
1232
1233 /*free tx rings */
1234 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1235 _rtl_pci_free_tx_ring(hw, i);
1236
1237 return 0;
1238 }
1239
1240 int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw)
1241 {
1242 struct rtl_priv *rtlpriv = rtl_priv(hw);
1243 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1244 int i, rx_queue_idx;
1245 unsigned long flags;
1246 u8 tmp_one = 1;
1247
1248 /*rx_queue_idx 0:RX_MPDU_QUEUE */
1249 /*rx_queue_idx 1:RX_CMD_QUEUE */
1250 for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
1251 rx_queue_idx++) {
1252 /*
1253 *force the rx_ring[RX_MPDU_QUEUE/
1254 *RX_CMD_QUEUE].idx to the first one
1255 */
1256 if (rtlpci->rx_ring[rx_queue_idx].desc) {
1257 struct rtl_rx_desc *entry = NULL;
1258
1259 for (i = 0; i < rtlpci->rxringcount; i++) {
1260 entry = &rtlpci->rx_ring[rx_queue_idx].desc[i];
1261 rtlpriv->cfg->ops->set_desc((u8 *) entry,
1262 false,
1263 HW_DESC_RXOWN,
1264 (u8 *)&tmp_one);
1265 }
1266 rtlpci->rx_ring[rx_queue_idx].idx = 0;
1267 }
1268 }
1269
1270 /*
1271 *after reset, release previous pending packet,
1272 *and force the tx idx to the first one
1273 */
1274 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1275 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1276 if (rtlpci->tx_ring[i].desc) {
1277 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[i];
1278
1279 while (skb_queue_len(&ring->queue)) {
1280 struct rtl_tx_desc *entry =
1281 &ring->desc[ring->idx];
1282 struct sk_buff *skb =
1283 __skb_dequeue(&ring->queue);
1284
1285 pci_unmap_single(rtlpci->pdev,
1286 rtlpriv->cfg->ops->
1287 get_desc((u8 *)
1288 entry,
1289 true,
1290 HW_DESC_TXBUFF_ADDR),
1291 skb->len, PCI_DMA_TODEVICE);
1292 kfree_skb(skb);
1293 ring->idx = (ring->idx + 1) % ring->entries;
1294 }
1295 ring->idx = 0;
1296 }
1297 }
1298
1299 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1300
1301 return 0;
1302 }
1303
1304 static bool rtl_pci_tx_chk_waitq_insert(struct ieee80211_hw *hw,
1305 struct sk_buff *skb)
1306 {
1307 struct rtl_priv *rtlpriv = rtl_priv(hw);
1308 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1309 struct ieee80211_sta *sta = info->control.sta;
1310 struct rtl_sta_info *sta_entry = NULL;
1311 u8 tid = rtl_get_tid(skb);
1312
1313 if (!sta)
1314 return false;
1315 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1316
1317 if (!rtlpriv->rtlhal.earlymode_enable)
1318 return false;
1319 if (sta_entry->tids[tid].agg.agg_state != RTL_AGG_OPERATIONAL)
1320 return false;
1321 if (_rtl_mac_to_hwqueue(hw, skb) > VO_QUEUE)
1322 return false;
1323 if (tid > 7)
1324 return false;
1325
1326 /* maybe every tid should be checked */
1327 if (!rtlpriv->link_info.higher_busytxtraffic[tid])
1328 return false;
1329
1330 spin_lock_bh(&rtlpriv->locks.waitq_lock);
1331 skb_queue_tail(&rtlpriv->mac80211.skb_waitq[tid], skb);
1332 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
1333
1334 return true;
1335 }
1336
1337 static int rtl_pci_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
1338 struct rtl_tcb_desc *ptcb_desc)
1339 {
1340 struct rtl_priv *rtlpriv = rtl_priv(hw);
1341 struct rtl_sta_info *sta_entry = NULL;
1342 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1343 struct ieee80211_sta *sta = info->control.sta;
1344 struct rtl8192_tx_ring *ring;
1345 struct rtl_tx_desc *pdesc;
1346 u8 idx;
1347 u8 hw_queue = _rtl_mac_to_hwqueue(hw, skb);
1348 unsigned long flags;
1349 struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
1350 __le16 fc = rtl_get_fc(skb);
1351 u8 *pda_addr = hdr->addr1;
1352 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1353 /*ssn */
1354 u8 tid = 0;
1355 u16 seq_number = 0;
1356 u8 own;
1357 u8 temp_one = 1;
1358
1359 if (ieee80211_is_auth(fc)) {
1360 RT_TRACE(rtlpriv, COMP_SEND, DBG_DMESG, "MAC80211_LINKING\n");
1361 rtl_ips_nic_on(hw);
1362 }
1363
1364 if (rtlpriv->psc.sw_ps_enabled) {
1365 if (ieee80211_is_data(fc) && !ieee80211_is_nullfunc(fc) &&
1366 !ieee80211_has_pm(fc))
1367 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
1368 }
1369
1370 rtl_action_proc(hw, skb, true);
1371
1372 if (is_multicast_ether_addr(pda_addr))
1373 rtlpriv->stats.txbytesmulticast += skb->len;
1374 else if (is_broadcast_ether_addr(pda_addr))
1375 rtlpriv->stats.txbytesbroadcast += skb->len;
1376 else
1377 rtlpriv->stats.txbytesunicast += skb->len;
1378
1379 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1380 ring = &rtlpci->tx_ring[hw_queue];
1381 if (hw_queue != BEACON_QUEUE)
1382 idx = (ring->idx + skb_queue_len(&ring->queue)) %
1383 ring->entries;
1384 else
1385 idx = 0;
1386
1387 pdesc = &ring->desc[idx];
1388 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) pdesc,
1389 true, HW_DESC_OWN);
1390
1391 if ((own == 1) && (hw_queue != BEACON_QUEUE)) {
1392 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1393 "No more TX desc@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%d\n",
1394 hw_queue, ring->idx, idx,
1395 skb_queue_len(&ring->queue));
1396
1397 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1398 return skb->len;
1399 }
1400
1401 if (ieee80211_is_data_qos(fc)) {
1402 tid = rtl_get_tid(skb);
1403 if (sta) {
1404 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1405 seq_number = (le16_to_cpu(hdr->seq_ctrl) &
1406 IEEE80211_SCTL_SEQ) >> 4;
1407 seq_number += 1;
1408
1409 if (!ieee80211_has_morefrags(hdr->frame_control))
1410 sta_entry->tids[tid].seq_number = seq_number;
1411 }
1412 }
1413
1414 if (ieee80211_is_data(fc))
1415 rtlpriv->cfg->ops->led_control(hw, LED_CTL_TX);
1416
1417 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc,
1418 info, skb, hw_queue, ptcb_desc);
1419
1420 __skb_queue_tail(&ring->queue, skb);
1421
1422 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, true,
1423 HW_DESC_OWN, (u8 *)&temp_one);
1424
1425
1426 if ((ring->entries - skb_queue_len(&ring->queue)) < 2 &&
1427 hw_queue != BEACON_QUEUE) {
1428
1429 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
1430 "less desc left, stop skb_queue@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%d\n",
1431 hw_queue, ring->idx, idx,
1432 skb_queue_len(&ring->queue));
1433
1434 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
1435 }
1436
1437 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1438
1439 rtlpriv->cfg->ops->tx_polling(hw, hw_queue);
1440
1441 return 0;
1442 }
1443
1444 static void rtl_pci_flush(struct ieee80211_hw *hw, bool drop)
1445 {
1446 struct rtl_priv *rtlpriv = rtl_priv(hw);
1447 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1448 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1449 u16 i = 0;
1450 int queue_id;
1451 struct rtl8192_tx_ring *ring;
1452
1453 for (queue_id = RTL_PCI_MAX_TX_QUEUE_COUNT - 1; queue_id >= 0;) {
1454 u32 queue_len;
1455 ring = &pcipriv->dev.tx_ring[queue_id];
1456 queue_len = skb_queue_len(&ring->queue);
1457 if (queue_len == 0 || queue_id == BEACON_QUEUE ||
1458 queue_id == TXCMD_QUEUE) {
1459 queue_id--;
1460 continue;
1461 } else {
1462 msleep(20);
1463 i++;
1464 }
1465
1466 /* we just wait 1s for all queues */
1467 if (rtlpriv->psc.rfpwr_state == ERFOFF ||
1468 is_hal_stop(rtlhal) || i >= 200)
1469 return;
1470 }
1471 }
1472
1473 static void rtl_pci_deinit(struct ieee80211_hw *hw)
1474 {
1475 struct rtl_priv *rtlpriv = rtl_priv(hw);
1476 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1477
1478 _rtl_pci_deinit_trx_ring(hw);
1479
1480 synchronize_irq(rtlpci->pdev->irq);
1481 tasklet_kill(&rtlpriv->works.irq_tasklet);
1482 cancel_work_sync(&rtlpriv->works.lps_leave_work);
1483
1484 flush_workqueue(rtlpriv->works.rtl_wq);
1485 destroy_workqueue(rtlpriv->works.rtl_wq);
1486
1487 }
1488
1489 static int rtl_pci_init(struct ieee80211_hw *hw, struct pci_dev *pdev)
1490 {
1491 struct rtl_priv *rtlpriv = rtl_priv(hw);
1492 int err;
1493
1494 _rtl_pci_init_struct(hw, pdev);
1495
1496 err = _rtl_pci_init_trx_ring(hw);
1497 if (err) {
1498 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1499 "tx ring initialization failed\n");
1500 return err;
1501 }
1502
1503 return 0;
1504 }
1505
1506 static int rtl_pci_start(struct ieee80211_hw *hw)
1507 {
1508 struct rtl_priv *rtlpriv = rtl_priv(hw);
1509 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1510 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1511 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1512
1513 int err;
1514
1515 rtl_pci_reset_trx_ring(hw);
1516
1517 rtlpci->driver_is_goingto_unload = false;
1518 err = rtlpriv->cfg->ops->hw_init(hw);
1519 if (err) {
1520 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1521 "Failed to config hardware!\n");
1522 return err;
1523 }
1524
1525 rtlpriv->cfg->ops->enable_interrupt(hw);
1526 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "enable_interrupt OK\n");
1527
1528 rtl_init_rx_config(hw);
1529
1530 /*should be after adapter start and interrupt enable. */
1531 set_hal_start(rtlhal);
1532
1533 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1534
1535 rtlpci->up_first_time = false;
1536
1537 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "OK\n");
1538 return 0;
1539 }
1540
1541 static void rtl_pci_stop(struct ieee80211_hw *hw)
1542 {
1543 struct rtl_priv *rtlpriv = rtl_priv(hw);
1544 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1545 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1546 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1547 unsigned long flags;
1548 u8 RFInProgressTimeOut = 0;
1549
1550 /*
1551 *should be before disable interrupt&adapter
1552 *and will do it immediately.
1553 */
1554 set_hal_stop(rtlhal);
1555
1556 rtlpriv->cfg->ops->disable_interrupt(hw);
1557 cancel_work_sync(&rtlpriv->works.lps_leave_work);
1558
1559 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1560 while (ppsc->rfchange_inprogress) {
1561 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1562 if (RFInProgressTimeOut > 100) {
1563 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1564 break;
1565 }
1566 mdelay(1);
1567 RFInProgressTimeOut++;
1568 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1569 }
1570 ppsc->rfchange_inprogress = true;
1571 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1572
1573 rtlpci->driver_is_goingto_unload = true;
1574 rtlpriv->cfg->ops->hw_disable(hw);
1575 /* some things are not needed if firmware not available */
1576 if (!rtlpriv->max_fw_size)
1577 return;
1578 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1579
1580 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1581 ppsc->rfchange_inprogress = false;
1582 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1583
1584 rtl_pci_enable_aspm(hw);
1585 }
1586
1587 static bool _rtl_pci_find_adapter(struct pci_dev *pdev,
1588 struct ieee80211_hw *hw)
1589 {
1590 struct rtl_priv *rtlpriv = rtl_priv(hw);
1591 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1592 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1593 struct pci_dev *bridge_pdev = pdev->bus->self;
1594 u16 venderid;
1595 u16 deviceid;
1596 u8 revisionid;
1597 u16 irqline;
1598 u8 tmp;
1599
1600 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN;
1601 venderid = pdev->vendor;
1602 deviceid = pdev->device;
1603 pci_read_config_byte(pdev, 0x8, &revisionid);
1604 pci_read_config_word(pdev, 0x3C, &irqline);
1605
1606 /* PCI ID 0x10ec:0x8192 occurs for both RTL8192E, which uses
1607 * r8192e_pci, and RTL8192SE, which uses this driver. If the
1608 * revision ID is RTL_PCI_REVISION_ID_8192PCIE (0x01), then
1609 * the correct driver is r8192e_pci, thus this routine should
1610 * return false.
1611 */
1612 if (deviceid == RTL_PCI_8192SE_DID &&
1613 revisionid == RTL_PCI_REVISION_ID_8192PCIE)
1614 return false;
1615
1616 if (deviceid == RTL_PCI_8192_DID ||
1617 deviceid == RTL_PCI_0044_DID ||
1618 deviceid == RTL_PCI_0047_DID ||
1619 deviceid == RTL_PCI_8192SE_DID ||
1620 deviceid == RTL_PCI_8174_DID ||
1621 deviceid == RTL_PCI_8173_DID ||
1622 deviceid == RTL_PCI_8172_DID ||
1623 deviceid == RTL_PCI_8171_DID) {
1624 switch (revisionid) {
1625 case RTL_PCI_REVISION_ID_8192PCIE:
1626 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1627 "8192 PCI-E is found - vid/did=%x/%x\n",
1628 venderid, deviceid);
1629 rtlhal->hw_type = HARDWARE_TYPE_RTL8192E;
1630 break;
1631 case RTL_PCI_REVISION_ID_8192SE:
1632 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1633 "8192SE is found - vid/did=%x/%x\n",
1634 venderid, deviceid);
1635 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1636 break;
1637 default:
1638 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1639 "Err: Unknown device - vid/did=%x/%x\n",
1640 venderid, deviceid);
1641 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1642 break;
1643
1644 }
1645 } else if (deviceid == RTL_PCI_8192CET_DID ||
1646 deviceid == RTL_PCI_8192CE_DID ||
1647 deviceid == RTL_PCI_8191CE_DID ||
1648 deviceid == RTL_PCI_8188CE_DID) {
1649 rtlhal->hw_type = HARDWARE_TYPE_RTL8192CE;
1650 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1651 "8192C PCI-E is found - vid/did=%x/%x\n",
1652 venderid, deviceid);
1653 } else if (deviceid == RTL_PCI_8192DE_DID ||
1654 deviceid == RTL_PCI_8192DE_DID2) {
1655 rtlhal->hw_type = HARDWARE_TYPE_RTL8192DE;
1656 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1657 "8192D PCI-E is found - vid/did=%x/%x\n",
1658 venderid, deviceid);
1659 } else {
1660 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1661 "Err: Unknown device - vid/did=%x/%x\n",
1662 venderid, deviceid);
1663
1664 rtlhal->hw_type = RTL_DEFAULT_HARDWARE_TYPE;
1665 }
1666
1667 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) {
1668 if (revisionid == 0 || revisionid == 1) {
1669 if (revisionid == 0) {
1670 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1671 "Find 92DE MAC0\n");
1672 rtlhal->interfaceindex = 0;
1673 } else if (revisionid == 1) {
1674 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1675 "Find 92DE MAC1\n");
1676 rtlhal->interfaceindex = 1;
1677 }
1678 } else {
1679 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1680 "Unknown device - VendorID/DeviceID=%x/%x, Revision=%x\n",
1681 venderid, deviceid, revisionid);
1682 rtlhal->interfaceindex = 0;
1683 }
1684 }
1685 /*find bus info */
1686 pcipriv->ndis_adapter.busnumber = pdev->bus->number;
1687 pcipriv->ndis_adapter.devnumber = PCI_SLOT(pdev->devfn);
1688 pcipriv->ndis_adapter.funcnumber = PCI_FUNC(pdev->devfn);
1689
1690 if (bridge_pdev) {
1691 /*find bridge info if available */
1692 pcipriv->ndis_adapter.pcibridge_vendorid = bridge_pdev->vendor;
1693 for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) {
1694 if (bridge_pdev->vendor == pcibridge_vendors[tmp]) {
1695 pcipriv->ndis_adapter.pcibridge_vendor = tmp;
1696 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1697 "Pci Bridge Vendor is found index: %d\n",
1698 tmp);
1699 break;
1700 }
1701 }
1702 }
1703
1704 if (pcipriv->ndis_adapter.pcibridge_vendor !=
1705 PCI_BRIDGE_VENDOR_UNKNOWN) {
1706 pcipriv->ndis_adapter.pcibridge_busnum =
1707 bridge_pdev->bus->number;
1708 pcipriv->ndis_adapter.pcibridge_devnum =
1709 PCI_SLOT(bridge_pdev->devfn);
1710 pcipriv->ndis_adapter.pcibridge_funcnum =
1711 PCI_FUNC(bridge_pdev->devfn);
1712 pcipriv->ndis_adapter.pcibridge_pciehdr_offset =
1713 pci_pcie_cap(bridge_pdev);
1714 pcipriv->ndis_adapter.num4bytes =
1715 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10) / 4;
1716
1717 rtl_pci_get_linkcontrol_field(hw);
1718
1719 if (pcipriv->ndis_adapter.pcibridge_vendor ==
1720 PCI_BRIDGE_VENDOR_AMD) {
1721 pcipriv->ndis_adapter.amd_l1_patch =
1722 rtl_pci_get_amd_l1_patch(hw);
1723 }
1724 }
1725
1726 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1727 "pcidev busnumber:devnumber:funcnumber:vendor:link_ctl %d:%d:%d:%x:%x\n",
1728 pcipriv->ndis_adapter.busnumber,
1729 pcipriv->ndis_adapter.devnumber,
1730 pcipriv->ndis_adapter.funcnumber,
1731 pdev->vendor, pcipriv->ndis_adapter.linkctrl_reg);
1732
1733 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1734 "pci_bridge busnumber:devnumber:funcnumber:vendor:pcie_cap:link_ctl_reg:amd %d:%d:%d:%x:%x:%x:%x\n",
1735 pcipriv->ndis_adapter.pcibridge_busnum,
1736 pcipriv->ndis_adapter.pcibridge_devnum,
1737 pcipriv->ndis_adapter.pcibridge_funcnum,
1738 pcibridge_vendors[pcipriv->ndis_adapter.pcibridge_vendor],
1739 pcipriv->ndis_adapter.pcibridge_pciehdr_offset,
1740 pcipriv->ndis_adapter.pcibridge_linkctrlreg,
1741 pcipriv->ndis_adapter.amd_l1_patch);
1742
1743 rtl_pci_parse_configuration(pdev, hw);
1744
1745 return true;
1746 }
1747
1748 int __devinit rtl_pci_probe(struct pci_dev *pdev,
1749 const struct pci_device_id *id)
1750 {
1751 struct ieee80211_hw *hw = NULL;
1752
1753 struct rtl_priv *rtlpriv = NULL;
1754 struct rtl_pci_priv *pcipriv = NULL;
1755 struct rtl_pci *rtlpci;
1756 unsigned long pmem_start, pmem_len, pmem_flags;
1757 int err;
1758
1759 err = pci_enable_device(pdev);
1760 if (err) {
1761 RT_ASSERT(false, "%s : Cannot enable new PCI device\n",
1762 pci_name(pdev));
1763 return err;
1764 }
1765
1766 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
1767 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
1768 RT_ASSERT(false,
1769 "Unable to obtain 32bit DMA for consistent allocations\n");
1770 err = -ENOMEM;
1771 goto fail1;
1772 }
1773 }
1774
1775 pci_set_master(pdev);
1776
1777 hw = ieee80211_alloc_hw(sizeof(struct rtl_pci_priv) +
1778 sizeof(struct rtl_priv), &rtl_ops);
1779 if (!hw) {
1780 RT_ASSERT(false,
1781 "%s : ieee80211 alloc failed\n", pci_name(pdev));
1782 err = -ENOMEM;
1783 goto fail1;
1784 }
1785
1786 SET_IEEE80211_DEV(hw, &pdev->dev);
1787 pci_set_drvdata(pdev, hw);
1788
1789 rtlpriv = hw->priv;
1790 pcipriv = (void *)rtlpriv->priv;
1791 pcipriv->dev.pdev = pdev;
1792 init_completion(&rtlpriv->firmware_loading_complete);
1793
1794 /* init cfg & intf_ops */
1795 rtlpriv->rtlhal.interface = INTF_PCI;
1796 rtlpriv->cfg = (struct rtl_hal_cfg *)(id->driver_data);
1797 rtlpriv->intf_ops = &rtl_pci_ops;
1798
1799 /*
1800 *init dbgp flags before all
1801 *other functions, because we will
1802 *use it in other funtions like
1803 *RT_TRACE/RT_PRINT/RTL_PRINT_DATA
1804 *you can not use these macro
1805 *before this
1806 */
1807 rtl_dbgp_flag_init(hw);
1808
1809 /* MEM map */
1810 err = pci_request_regions(pdev, KBUILD_MODNAME);
1811 if (err) {
1812 RT_ASSERT(false, "Can't obtain PCI resources\n");
1813 goto fail1;
1814 }
1815
1816 pmem_start = pci_resource_start(pdev, rtlpriv->cfg->bar_id);
1817 pmem_len = pci_resource_len(pdev, rtlpriv->cfg->bar_id);
1818 pmem_flags = pci_resource_flags(pdev, rtlpriv->cfg->bar_id);
1819
1820 /*shared mem start */
1821 rtlpriv->io.pci_mem_start =
1822 (unsigned long)pci_iomap(pdev,
1823 rtlpriv->cfg->bar_id, pmem_len);
1824 if (rtlpriv->io.pci_mem_start == 0) {
1825 RT_ASSERT(false, "Can't map PCI mem\n");
1826 err = -ENOMEM;
1827 goto fail2;
1828 }
1829
1830 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1831 "mem mapped space: start: 0x%08lx len:%08lx flags:%08lx, after map:0x%08lx\n",
1832 pmem_start, pmem_len, pmem_flags,
1833 rtlpriv->io.pci_mem_start);
1834
1835 /* Disable Clk Request */
1836 pci_write_config_byte(pdev, 0x81, 0);
1837 /* leave D3 mode */
1838 pci_write_config_byte(pdev, 0x44, 0);
1839 pci_write_config_byte(pdev, 0x04, 0x06);
1840 pci_write_config_byte(pdev, 0x04, 0x07);
1841
1842 /* find adapter */
1843 if (!_rtl_pci_find_adapter(pdev, hw)) {
1844 err = -ENODEV;
1845 goto fail3;
1846 }
1847
1848 /* Init IO handler */
1849 _rtl_pci_io_handler_init(&pdev->dev, hw);
1850
1851 /*like read eeprom and so on */
1852 rtlpriv->cfg->ops->read_eeprom_info(hw);
1853
1854 if (rtlpriv->cfg->ops->init_sw_vars(hw)) {
1855 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Can't init_sw_vars\n");
1856 err = -ENODEV;
1857 goto fail3;
1858 }
1859
1860 rtlpriv->cfg->ops->init_sw_leds(hw);
1861
1862 /*aspm */
1863 rtl_pci_init_aspm(hw);
1864
1865 /* Init mac80211 sw */
1866 err = rtl_init_core(hw);
1867 if (err) {
1868 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1869 "Can't allocate sw for mac80211\n");
1870 goto fail3;
1871 }
1872
1873 /* Init PCI sw */
1874 err = rtl_pci_init(hw, pdev);
1875 if (err) {
1876 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Failed to init PCI\n");
1877 goto fail3;
1878 }
1879
1880 err = sysfs_create_group(&pdev->dev.kobj, &rtl_attribute_group);
1881 if (err) {
1882 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1883 "failed to create sysfs device attributes\n");
1884 goto fail3;
1885 }
1886
1887 rtlpci = rtl_pcidev(pcipriv);
1888 err = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt,
1889 IRQF_SHARED, KBUILD_MODNAME, hw);
1890 if (err) {
1891 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1892 "%s: failed to register IRQ handler\n",
1893 wiphy_name(hw->wiphy));
1894 goto fail3;
1895 }
1896 rtlpci->irq_alloc = 1;
1897
1898 return 0;
1899
1900 fail3:
1901 rtl_deinit_core(hw);
1902 _rtl_pci_io_handler_release(hw);
1903
1904 if (rtlpriv->io.pci_mem_start != 0)
1905 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
1906
1907 fail2:
1908 pci_release_regions(pdev);
1909 complete(&rtlpriv->firmware_loading_complete);
1910
1911 fail1:
1912 if (hw)
1913 ieee80211_free_hw(hw);
1914 pci_set_drvdata(pdev, NULL);
1915 pci_disable_device(pdev);
1916
1917 return err;
1918
1919 }
1920 EXPORT_SYMBOL(rtl_pci_probe);
1921
1922 void rtl_pci_disconnect(struct pci_dev *pdev)
1923 {
1924 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
1925 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1926 struct rtl_priv *rtlpriv = rtl_priv(hw);
1927 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
1928 struct rtl_mac *rtlmac = rtl_mac(rtlpriv);
1929
1930 /* just in case driver is removed before firmware callback */
1931 wait_for_completion(&rtlpriv->firmware_loading_complete);
1932 clear_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
1933
1934 sysfs_remove_group(&pdev->dev.kobj, &rtl_attribute_group);
1935
1936 /*ieee80211_unregister_hw will call ops_stop */
1937 if (rtlmac->mac80211_registered == 1) {
1938 ieee80211_unregister_hw(hw);
1939 rtlmac->mac80211_registered = 0;
1940 } else {
1941 rtl_deinit_deferred_work(hw);
1942 rtlpriv->intf_ops->adapter_stop(hw);
1943 }
1944
1945 /*deinit rfkill */
1946 rtl_deinit_rfkill(hw);
1947
1948 rtl_pci_deinit(hw);
1949 rtl_deinit_core(hw);
1950 _rtl_pci_io_handler_release(hw);
1951 rtlpriv->cfg->ops->deinit_sw_vars(hw);
1952
1953 if (rtlpci->irq_alloc) {
1954 free_irq(rtlpci->pdev->irq, hw);
1955 rtlpci->irq_alloc = 0;
1956 }
1957
1958 if (rtlpriv->io.pci_mem_start != 0) {
1959 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
1960 pci_release_regions(pdev);
1961 }
1962
1963 pci_disable_device(pdev);
1964
1965 rtl_pci_disable_aspm(hw);
1966
1967 pci_set_drvdata(pdev, NULL);
1968
1969 ieee80211_free_hw(hw);
1970 }
1971 EXPORT_SYMBOL(rtl_pci_disconnect);
1972
1973 /***************************************
1974 kernel pci power state define:
1975 PCI_D0 ((pci_power_t __force) 0)
1976 PCI_D1 ((pci_power_t __force) 1)
1977 PCI_D2 ((pci_power_t __force) 2)
1978 PCI_D3hot ((pci_power_t __force) 3)
1979 PCI_D3cold ((pci_power_t __force) 4)
1980 PCI_UNKNOWN ((pci_power_t __force) 5)
1981
1982 This function is called when system
1983 goes into suspend state mac80211 will
1984 call rtl_mac_stop() from the mac80211
1985 suspend function first, So there is
1986 no need to call hw_disable here.
1987 ****************************************/
1988 int rtl_pci_suspend(struct device *dev)
1989 {
1990 struct pci_dev *pdev = to_pci_dev(dev);
1991 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
1992 struct rtl_priv *rtlpriv = rtl_priv(hw);
1993
1994 rtlpriv->cfg->ops->hw_suspend(hw);
1995 rtl_deinit_rfkill(hw);
1996
1997 return 0;
1998 }
1999 EXPORT_SYMBOL(rtl_pci_suspend);
2000
2001 int rtl_pci_resume(struct device *dev)
2002 {
2003 struct pci_dev *pdev = to_pci_dev(dev);
2004 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2005 struct rtl_priv *rtlpriv = rtl_priv(hw);
2006
2007 rtlpriv->cfg->ops->hw_resume(hw);
2008 rtl_init_rfkill(hw);
2009 return 0;
2010 }
2011 EXPORT_SYMBOL(rtl_pci_resume);
2012
2013 struct rtl_intf_ops rtl_pci_ops = {
2014 .read_efuse_byte = read_efuse_byte,
2015 .adapter_start = rtl_pci_start,
2016 .adapter_stop = rtl_pci_stop,
2017 .adapter_tx = rtl_pci_tx,
2018 .flush = rtl_pci_flush,
2019 .reset_trx_ring = rtl_pci_reset_trx_ring,
2020 .waitq_insert = rtl_pci_tx_chk_waitq_insert,
2021
2022 .disable_aspm = rtl_pci_disable_aspm,
2023 .enable_aspm = rtl_pci_enable_aspm,
2024 };
Linux kernel - Deliverables
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