projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
PCI: Remove DEFINE_PCI_DEVICE_TABLE macro use
[deliverable/linux.git] / drivers / net / wireless / rtlwifi / pci.c
1 /******************************************************************************
2 *
3 * Copyright(c) 2009-2012 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30 #include "wifi.h"
31 #include "core.h"
32 #include "pci.h"
33 #include "base.h"
34 #include "ps.h"
35 #include "efuse.h"
36 #include <linux/export.h>
37 #include <linux/kmemleak.h>
38 #include <linux/module.h>
39
40 MODULE_AUTHOR("lizhaoming <chaoming_li@realsil.com.cn>");
41 MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>");
42 MODULE_AUTHOR("Larry Finger <Larry.FInger@lwfinger.net>");
43 MODULE_LICENSE("GPL");
44 MODULE_DESCRIPTION("PCI basic driver for rtlwifi");
45
46 static const u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = {
47 PCI_VENDOR_ID_INTEL,
48 PCI_VENDOR_ID_ATI,
49 PCI_VENDOR_ID_AMD,
50 PCI_VENDOR_ID_SI
51 };
52
53 static const u8 ac_to_hwq[] = {
54 VO_QUEUE,
55 VI_QUEUE,
56 BE_QUEUE,
57 BK_QUEUE
58 };
59
60 static u8 _rtl_mac_to_hwqueue(struct ieee80211_hw *hw,
61 struct sk_buff *skb)
62 {
63 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
64 __le16 fc = rtl_get_fc(skb);
65 u8 queue_index = skb_get_queue_mapping(skb);
66
67 if (unlikely(ieee80211_is_beacon(fc)))
68 return BEACON_QUEUE;
69 if (ieee80211_is_mgmt(fc) || ieee80211_is_ctl(fc))
70 return MGNT_QUEUE;
71 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
72 if (ieee80211_is_nullfunc(fc))
73 return HIGH_QUEUE;
74
75 return ac_to_hwq[queue_index];
76 }
77
78 /* Update PCI dependent default settings*/
79 static void _rtl_pci_update_default_setting(struct ieee80211_hw *hw)
80 {
81 struct rtl_priv *rtlpriv = rtl_priv(hw);
82 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
83 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
84 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
85 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
86 u8 init_aspm;
87
88 ppsc->reg_rfps_level = 0;
89 ppsc->support_aspm = false;
90
91 /*Update PCI ASPM setting */
92 ppsc->const_amdpci_aspm = rtlpci->const_amdpci_aspm;
93 switch (rtlpci->const_pci_aspm) {
94 case 0:
95 /*No ASPM */
96 break;
97
98 case 1:
99 /*ASPM dynamically enabled/disable. */
100 ppsc->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM;
101 break;
102
103 case 2:
104 /*ASPM with Clock Req dynamically enabled/disable. */
105 ppsc->reg_rfps_level |= (RT_RF_LPS_LEVEL_ASPM |
106 RT_RF_OFF_LEVL_CLK_REQ);
107 break;
108
109 case 3:
110 /*
111 * Always enable ASPM and Clock Req
112 * from initialization to halt.
113 * */
114 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM);
115 ppsc->reg_rfps_level |= (RT_RF_PS_LEVEL_ALWAYS_ASPM |
116 RT_RF_OFF_LEVL_CLK_REQ);
117 break;
118
119 case 4:
120 /*
121 * Always enable ASPM without Clock Req
122 * from initialization to halt.
123 * */
124 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM |
125 RT_RF_OFF_LEVL_CLK_REQ);
126 ppsc->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM;
127 break;
128 }
129
130 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
131
132 /*Update Radio OFF setting */
133 switch (rtlpci->const_hwsw_rfoff_d3) {
134 case 1:
135 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
136 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
137 break;
138
139 case 2:
140 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
141 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
142 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
143 break;
144
145 case 3:
146 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3;
147 break;
148 }
149
150 /*Set HW definition to determine if it supports ASPM. */
151 switch (rtlpci->const_support_pciaspm) {
152 case 0:{
153 /*Not support ASPM. */
154 bool support_aspm = false;
155 ppsc->support_aspm = support_aspm;
156 break;
157 }
158 case 1:{
159 /*Support ASPM. */
160 bool support_aspm = true;
161 bool support_backdoor = true;
162 ppsc->support_aspm = support_aspm;
163
164 /*if (priv->oem_id == RT_CID_TOSHIBA &&
165 !priv->ndis_adapter.amd_l1_patch)
166 support_backdoor = false; */
167
168 ppsc->support_backdoor = support_backdoor;
169
170 break;
171 }
172 case 2:
173 /*ASPM value set by chipset. */
174 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL) {
175 bool support_aspm = true;
176 ppsc->support_aspm = support_aspm;
177 }
178 break;
179 default:
180 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
181 "switch case not processed\n");
182 break;
183 }
184
185 /* toshiba aspm issue, toshiba will set aspm selfly
186 * so we should not set aspm in driver */
187 pci_read_config_byte(rtlpci->pdev, 0x80, &init_aspm);
188 if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8192SE &&
189 init_aspm == 0x43)
190 ppsc->support_aspm = false;
191 }
192
193 static bool _rtl_pci_platform_switch_device_pci_aspm(
194 struct ieee80211_hw *hw,
195 u8 value)
196 {
197 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
198 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
199
200 if (rtlhal->hw_type != HARDWARE_TYPE_RTL8192SE)
201 value |= 0x40;
202
203 pci_write_config_byte(rtlpci->pdev, 0x80, value);
204
205 return false;
206 }
207
208 /*When we set 0x01 to enable clk request. Set 0x0 to disable clk req.*/
209 static void _rtl_pci_switch_clk_req(struct ieee80211_hw *hw, u8 value)
210 {
211 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
212 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
213
214 pci_write_config_byte(rtlpci->pdev, 0x81, value);
215
216 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
217 udelay(100);
218 }
219
220 /*Disable RTL8192SE ASPM & Disable Pci Bridge ASPM*/
221 static void rtl_pci_disable_aspm(struct ieee80211_hw *hw)
222 {
223 struct rtl_priv *rtlpriv = rtl_priv(hw);
224 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
225 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
226 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
227 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
228 u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
229 /*Retrieve original configuration settings. */
230 u8 linkctrl_reg = pcipriv->ndis_adapter.linkctrl_reg;
231 u16 pcibridge_linkctrlreg = pcipriv->ndis_adapter.
232 pcibridge_linkctrlreg;
233 u16 aspmlevel = 0;
234 u8 tmp_u1b = 0;
235
236 if (!ppsc->support_aspm)
237 return;
238
239 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
240 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
241 "PCI(Bridge) UNKNOWN\n");
242
243 return;
244 }
245
246 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
247 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
248 _rtl_pci_switch_clk_req(hw, 0x0);
249 }
250
251 /*for promising device will in L0 state after an I/O. */
252 pci_read_config_byte(rtlpci->pdev, 0x80, &tmp_u1b);
253
254 /*Set corresponding value. */
255 aspmlevel |= BIT(0) | BIT(1);
256 linkctrl_reg &= ~aspmlevel;
257 pcibridge_linkctrlreg &= ~(BIT(0) | BIT(1));
258
259 _rtl_pci_platform_switch_device_pci_aspm(hw, linkctrl_reg);
260 udelay(50);
261
262 /*4 Disable Pci Bridge ASPM */
263 pci_write_config_byte(rtlpci->pdev, (num4bytes << 2),
264 pcibridge_linkctrlreg);
265
266 udelay(50);
267 }
268
269 /*
270 *Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for
271 *power saving We should follow the sequence to enable
272 *RTL8192SE first then enable Pci Bridge ASPM
273 *or the system will show bluescreen.
274 */
275 static void rtl_pci_enable_aspm(struct ieee80211_hw *hw)
276 {
277 struct rtl_priv *rtlpriv = rtl_priv(hw);
278 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
279 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
280 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
281 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
282 u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
283 u16 aspmlevel;
284 u8 u_pcibridge_aspmsetting;
285 u8 u_device_aspmsetting;
286
287 if (!ppsc->support_aspm)
288 return;
289
290 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
291 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
292 "PCI(Bridge) UNKNOWN\n");
293 return;
294 }
295
296 /*4 Enable Pci Bridge ASPM */
297
298 u_pcibridge_aspmsetting =
299 pcipriv->ndis_adapter.pcibridge_linkctrlreg |
300 rtlpci->const_hostpci_aspm_setting;
301
302 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL)
303 u_pcibridge_aspmsetting &= ~BIT(0);
304
305 pci_write_config_byte(rtlpci->pdev, (num4bytes << 2),
306 u_pcibridge_aspmsetting);
307
308 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
309 "PlatformEnableASPM(): Write reg[%x] = %x\n",
310 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10),
311 u_pcibridge_aspmsetting);
312
313 udelay(50);
314
315 /*Get ASPM level (with/without Clock Req) */
316 aspmlevel = rtlpci->const_devicepci_aspm_setting;
317 u_device_aspmsetting = pcipriv->ndis_adapter.linkctrl_reg;
318
319 /*_rtl_pci_platform_switch_device_pci_aspm(dev,*/
320 /*(priv->ndis_adapter.linkctrl_reg | ASPMLevel)); */
321
322 u_device_aspmsetting |= aspmlevel;
323
324 _rtl_pci_platform_switch_device_pci_aspm(hw, u_device_aspmsetting);
325
326 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
327 _rtl_pci_switch_clk_req(hw, (ppsc->reg_rfps_level &
328 RT_RF_OFF_LEVL_CLK_REQ) ? 1 : 0);
329 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
330 }
331 udelay(100);
332 }
333
334 static bool rtl_pci_get_amd_l1_patch(struct ieee80211_hw *hw)
335 {
336 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
337
338 bool status = false;
339 u8 offset_e0;
340 unsigned offset_e4;
341
342 pci_write_config_byte(rtlpci->pdev, 0xe0, 0xa0);
343
344 pci_read_config_byte(rtlpci->pdev, 0xe0, &offset_e0);
345
346 if (offset_e0 == 0xA0) {
347 pci_read_config_dword(rtlpci->pdev, 0xe4, &offset_e4);
348 if (offset_e4 & BIT(23))
349 status = true;
350 }
351
352 return status;
353 }
354
355 static bool rtl_pci_check_buddy_priv(struct ieee80211_hw *hw,
356 struct rtl_priv **buddy_priv)
357 {
358 struct rtl_priv *rtlpriv = rtl_priv(hw);
359 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
360 bool find_buddy_priv = false;
361 struct rtl_priv *tpriv = NULL;
362 struct rtl_pci_priv *tpcipriv = NULL;
363
364 if (!list_empty(&rtlpriv->glb_var->glb_priv_list)) {
365 list_for_each_entry(tpriv, &rtlpriv->glb_var->glb_priv_list,
366 list) {
367 if (tpriv) {
368 tpcipriv = (struct rtl_pci_priv *)tpriv->priv;
369 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
370 "pcipriv->ndis_adapter.funcnumber %x\n",
371 pcipriv->ndis_adapter.funcnumber);
372 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
373 "tpcipriv->ndis_adapter.funcnumber %x\n",
374 tpcipriv->ndis_adapter.funcnumber);
375
376 if ((pcipriv->ndis_adapter.busnumber ==
377 tpcipriv->ndis_adapter.busnumber) &&
378 (pcipriv->ndis_adapter.devnumber ==
379 tpcipriv->ndis_adapter.devnumber) &&
380 (pcipriv->ndis_adapter.funcnumber !=
381 tpcipriv->ndis_adapter.funcnumber)) {
382 find_buddy_priv = true;
383 break;
384 }
385 }
386 }
387 }
388
389 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
390 "find_buddy_priv %d\n", find_buddy_priv);
391
392 if (find_buddy_priv)
393 *buddy_priv = tpriv;
394
395 return find_buddy_priv;
396 }
397
398 static void rtl_pci_get_linkcontrol_field(struct ieee80211_hw *hw)
399 {
400 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
401 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
402 u8 capabilityoffset = pcipriv->ndis_adapter.pcibridge_pciehdr_offset;
403 u8 linkctrl_reg;
404 u8 num4bbytes;
405
406 num4bbytes = (capabilityoffset + 0x10) / 4;
407
408 /*Read Link Control Register */
409 pci_read_config_byte(rtlpci->pdev, (num4bbytes << 2), &linkctrl_reg);
410
411 pcipriv->ndis_adapter.pcibridge_linkctrlreg = linkctrl_reg;
412 }
413
414 static void rtl_pci_parse_configuration(struct pci_dev *pdev,
415 struct ieee80211_hw *hw)
416 {
417 struct rtl_priv *rtlpriv = rtl_priv(hw);
418 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
419
420 u8 tmp;
421 u16 linkctrl_reg;
422
423 /*Link Control Register */
424 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &linkctrl_reg);
425 pcipriv->ndis_adapter.linkctrl_reg = (u8)linkctrl_reg;
426
427 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Link Control Register =%x\n",
428 pcipriv->ndis_adapter.linkctrl_reg);
429
430 pci_read_config_byte(pdev, 0x98, &tmp);
431 tmp |= BIT(4);
432 pci_write_config_byte(pdev, 0x98, tmp);
433
434 tmp = 0x17;
435 pci_write_config_byte(pdev, 0x70f, tmp);
436 }
437
438 static void rtl_pci_init_aspm(struct ieee80211_hw *hw)
439 {
440 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
441
442 _rtl_pci_update_default_setting(hw);
443
444 if (ppsc->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM) {
445 /*Always enable ASPM & Clock Req. */
446 rtl_pci_enable_aspm(hw);
447 RT_SET_PS_LEVEL(ppsc, RT_RF_PS_LEVEL_ALWAYS_ASPM);
448 }
449
450 }
451
452 static void _rtl_pci_io_handler_init(struct device *dev,
453 struct ieee80211_hw *hw)
454 {
455 struct rtl_priv *rtlpriv = rtl_priv(hw);
456
457 rtlpriv->io.dev = dev;
458
459 rtlpriv->io.write8_async = pci_write8_async;
460 rtlpriv->io.write16_async = pci_write16_async;
461 rtlpriv->io.write32_async = pci_write32_async;
462
463 rtlpriv->io.read8_sync = pci_read8_sync;
464 rtlpriv->io.read16_sync = pci_read16_sync;
465 rtlpriv->io.read32_sync = pci_read32_sync;
466
467 }
468
469 static bool _rtl_update_earlymode_info(struct ieee80211_hw *hw,
470 struct sk_buff *skb, struct rtl_tcb_desc *tcb_desc, u8 tid)
471 {
472 struct rtl_priv *rtlpriv = rtl_priv(hw);
473 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
474 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
475 struct sk_buff *next_skb;
476 u8 additionlen = FCS_LEN;
477
478 /* here open is 4, wep/tkip is 8, aes is 12*/
479 if (info->control.hw_key)
480 additionlen += info->control.hw_key->icv_len;
481
482 /* The most skb num is 6 */
483 tcb_desc->empkt_num = 0;
484 spin_lock_bh(&rtlpriv->locks.waitq_lock);
485 skb_queue_walk(&rtlpriv->mac80211.skb_waitq[tid], next_skb) {
486 struct ieee80211_tx_info *next_info;
487
488 next_info = IEEE80211_SKB_CB(next_skb);
489 if (next_info->flags & IEEE80211_TX_CTL_AMPDU) {
490 tcb_desc->empkt_len[tcb_desc->empkt_num] =
491 next_skb->len + additionlen;
492 tcb_desc->empkt_num++;
493 } else {
494 break;
495 }
496
497 if (skb_queue_is_last(&rtlpriv->mac80211.skb_waitq[tid],
498 next_skb))
499 break;
500
501 if (tcb_desc->empkt_num >= rtlhal->max_earlymode_num)
502 break;
503 }
504 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
505
506 return true;
507 }
508
509 /* just for early mode now */
510 static void _rtl_pci_tx_chk_waitq(struct ieee80211_hw *hw)
511 {
512 struct rtl_priv *rtlpriv = rtl_priv(hw);
513 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
514 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
515 struct sk_buff *skb = NULL;
516 struct ieee80211_tx_info *info = NULL;
517 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
518 int tid;
519
520 if (!rtlpriv->rtlhal.earlymode_enable)
521 return;
522
523 if (rtlpriv->dm.supp_phymode_switch &&
524 (rtlpriv->easy_concurrent_ctl.switch_in_process ||
525 (rtlpriv->buddy_priv &&
526 rtlpriv->buddy_priv->easy_concurrent_ctl.switch_in_process)))
527 return;
528 /* we juse use em for BE/BK/VI/VO */
529 for (tid = 7; tid >= 0; tid--) {
530 u8 hw_queue = ac_to_hwq[rtl_tid_to_ac(tid)];
531 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];
532 while (!mac->act_scanning &&
533 rtlpriv->psc.rfpwr_state == ERFON) {
534 struct rtl_tcb_desc tcb_desc;
535 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
536
537 spin_lock_bh(&rtlpriv->locks.waitq_lock);
538 if (!skb_queue_empty(&mac->skb_waitq[tid]) &&
539 (ring->entries - skb_queue_len(&ring->queue) >
540 rtlhal->max_earlymode_num)) {
541 skb = skb_dequeue(&mac->skb_waitq[tid]);
542 } else {
543 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
544 break;
545 }
546 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
547
548 /* Some macaddr can't do early mode. like
549 * multicast/broadcast/no_qos data */
550 info = IEEE80211_SKB_CB(skb);
551 if (info->flags & IEEE80211_TX_CTL_AMPDU)
552 _rtl_update_earlymode_info(hw, skb,
553 &tcb_desc, tid);
554
555 rtlpriv->intf_ops->adapter_tx(hw, NULL, skb, &tcb_desc);
556 }
557 }
558 }
559
560
561 static void _rtl_pci_tx_isr(struct ieee80211_hw *hw, int prio)
562 {
563 struct rtl_priv *rtlpriv = rtl_priv(hw);
564 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
565
566 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
567
568 while (skb_queue_len(&ring->queue)) {
569 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
570 struct sk_buff *skb;
571 struct ieee80211_tx_info *info;
572 __le16 fc;
573 u8 tid;
574
575 u8 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) entry, true,
576 HW_DESC_OWN);
577
578 /*beacon packet will only use the first
579 *descriptor by defaut, and the own may not
580 *be cleared by the hardware
581 */
582 if (own)
583 return;
584 ring->idx = (ring->idx + 1) % ring->entries;
585
586 skb = __skb_dequeue(&ring->queue);
587 pci_unmap_single(rtlpci->pdev,
588 rtlpriv->cfg->ops->
589 get_desc((u8 *) entry, true,
590 HW_DESC_TXBUFF_ADDR),
591 skb->len, PCI_DMA_TODEVICE);
592
593 /* remove early mode header */
594 if (rtlpriv->rtlhal.earlymode_enable)
595 skb_pull(skb, EM_HDR_LEN);
596
597 RT_TRACE(rtlpriv, (COMP_INTR | COMP_SEND), DBG_TRACE,
598 "new ring->idx:%d, free: skb_queue_len:%d, free: seq:%x\n",
599 ring->idx,
600 skb_queue_len(&ring->queue),
601 *(u16 *) (skb->data + 22));
602
603 if (prio == TXCMD_QUEUE) {
604 dev_kfree_skb(skb);
605 goto tx_status_ok;
606
607 }
608
609 /* for sw LPS, just after NULL skb send out, we can
610 * sure AP knows we are sleeping, we should not let
611 * rf sleep
612 */
613 fc = rtl_get_fc(skb);
614 if (ieee80211_is_nullfunc(fc)) {
615 if (ieee80211_has_pm(fc)) {
616 rtlpriv->mac80211.offchan_delay = true;
617 rtlpriv->psc.state_inap = true;
618 } else {
619 rtlpriv->psc.state_inap = false;
620 }
621 }
622 if (ieee80211_is_action(fc)) {
623 struct ieee80211_mgmt *action_frame =
624 (struct ieee80211_mgmt *)skb->data;
625 if (action_frame->u.action.u.ht_smps.action ==
626 WLAN_HT_ACTION_SMPS) {
627 dev_kfree_skb(skb);
628 goto tx_status_ok;
629 }
630 }
631
632 /* update tid tx pkt num */
633 tid = rtl_get_tid(skb);
634 if (tid <= 7)
635 rtlpriv->link_info.tidtx_inperiod[tid]++;
636
637 info = IEEE80211_SKB_CB(skb);
638 ieee80211_tx_info_clear_status(info);
639
640 info->flags |= IEEE80211_TX_STAT_ACK;
641 /*info->status.rates[0].count = 1; */
642
643 ieee80211_tx_status_irqsafe(hw, skb);
644
645 if ((ring->entries - skb_queue_len(&ring->queue))
646 == 2) {
647
648 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
649 "more desc left, wake skb_queue@%d, ring->idx = %d, skb_queue_len = 0x%d\n",
650 prio, ring->idx,
651 skb_queue_len(&ring->queue));
652
653 ieee80211_wake_queue(hw,
654 skb_get_queue_mapping
655 (skb));
656 }
657 tx_status_ok:
658 skb = NULL;
659 }
660
661 if (((rtlpriv->link_info.num_rx_inperiod +
662 rtlpriv->link_info.num_tx_inperiod) > 8) ||
663 (rtlpriv->link_info.num_rx_inperiod > 2)) {
664 rtlpriv->enter_ps = false;
665 schedule_work(&rtlpriv->works.lps_change_work);
666 }
667 }
668
669 static void _rtl_receive_one(struct ieee80211_hw *hw, struct sk_buff *skb,
670 struct ieee80211_rx_status rx_status)
671 {
672 struct rtl_priv *rtlpriv = rtl_priv(hw);
673 struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
674 __le16 fc = rtl_get_fc(skb);
675 bool unicast = false;
676 struct sk_buff *uskb = NULL;
677 u8 *pdata;
678
679
680 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, sizeof(rx_status));
681
682 if (is_broadcast_ether_addr(hdr->addr1)) {
683 ;/*TODO*/
684 } else if (is_multicast_ether_addr(hdr->addr1)) {
685 ;/*TODO*/
686 } else {
687 unicast = true;
688 rtlpriv->stats.rxbytesunicast += skb->len;
689 }
690
691 if (ieee80211_is_data(fc)) {
692 rtlpriv->cfg->ops->led_control(hw, LED_CTL_RX);
693
694 if (unicast)
695 rtlpriv->link_info.num_rx_inperiod++;
696 }
697
698 /* static bcn for roaming */
699 rtl_beacon_statistic(hw, skb);
700 rtl_p2p_info(hw, (void *)skb->data, skb->len);
701
702 /* for sw lps */
703 rtl_swlps_beacon(hw, (void *)skb->data, skb->len);
704 rtl_recognize_peer(hw, (void *)skb->data, skb->len);
705 if ((rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP) &&
706 (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G) &&
707 (ieee80211_is_beacon(fc) || ieee80211_is_probe_resp(fc)))
708 return;
709
710 if (unlikely(!rtl_action_proc(hw, skb, false)))
711 return;
712
713 uskb = dev_alloc_skb(skb->len + 128);
714 if (!uskb)
715 return; /* exit if allocation failed */
716 memcpy(IEEE80211_SKB_RXCB(uskb), &rx_status, sizeof(rx_status));
717 pdata = (u8 *)skb_put(uskb, skb->len);
718 memcpy(pdata, skb->data, skb->len);
719
720 ieee80211_rx_irqsafe(hw, uskb);
721 }
722
723 static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw)
724 {
725 struct rtl_priv *rtlpriv = rtl_priv(hw);
726 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
727 int rx_queue_idx = RTL_PCI_RX_MPDU_QUEUE;
728
729 struct ieee80211_rx_status rx_status = { 0 };
730 unsigned int count = rtlpci->rxringcount;
731 u8 own;
732 u8 tmp_one;
733 u32 bufferaddress;
734
735 struct rtl_stats stats = {
736 .signal = 0,
737 .rate = 0,
738 };
739 int index = rtlpci->rx_ring[rx_queue_idx].idx;
740
741 if (rtlpci->driver_is_goingto_unload)
742 return;
743 /*RX NORMAL PKT */
744 while (count--) {
745 /*rx descriptor */
746 struct rtl_rx_desc *pdesc = &rtlpci->rx_ring[rx_queue_idx].desc[
747 index];
748 /*rx pkt */
749 struct sk_buff *skb = rtlpci->rx_ring[rx_queue_idx].rx_buf[
750 index];
751 struct sk_buff *new_skb = NULL;
752
753 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) pdesc,
754 false, HW_DESC_OWN);
755
756 /*wait data to be filled by hardware */
757 if (own)
758 break;
759
760 rtlpriv->cfg->ops->query_rx_desc(hw, &stats,
761 &rx_status,
762 (u8 *) pdesc, skb);
763
764 if (stats.crc || stats.hwerror)
765 goto done;
766
767 new_skb = dev_alloc_skb(rtlpci->rxbuffersize);
768 if (unlikely(!new_skb)) {
769 RT_TRACE(rtlpriv, (COMP_INTR | COMP_RECV), DBG_DMESG,
770 "can't alloc skb for rx\n");
771 goto done;
772 }
773 kmemleak_not_leak(new_skb);
774
775 pci_unmap_single(rtlpci->pdev,
776 *((dma_addr_t *) skb->cb),
777 rtlpci->rxbuffersize,
778 PCI_DMA_FROMDEVICE);
779
780 skb_put(skb, rtlpriv->cfg->ops->get_desc((u8 *) pdesc, false,
781 HW_DESC_RXPKT_LEN));
782 skb_reserve(skb, stats.rx_drvinfo_size + stats.rx_bufshift);
783
784 /*
785 * NOTICE This can not be use for mac80211,
786 * this is done in mac80211 code,
787 * if you done here sec DHCP will fail
788 * skb_trim(skb, skb->len - 4);
789 */
790
791 _rtl_receive_one(hw, skb, rx_status);
792
793 if (((rtlpriv->link_info.num_rx_inperiod +
794 rtlpriv->link_info.num_tx_inperiod) > 8) ||
795 (rtlpriv->link_info.num_rx_inperiod > 2)) {
796 rtlpriv->enter_ps = false;
797 schedule_work(&rtlpriv->works.lps_change_work);
798 }
799
800 dev_kfree_skb_any(skb);
801 skb = new_skb;
802
803 rtlpci->rx_ring[rx_queue_idx].rx_buf[index] = skb;
804 *((dma_addr_t *) skb->cb) =
805 pci_map_single(rtlpci->pdev, skb_tail_pointer(skb),
806 rtlpci->rxbuffersize,
807 PCI_DMA_FROMDEVICE);
808
809 done:
810 bufferaddress = (*((dma_addr_t *)skb->cb));
811 if (pci_dma_mapping_error(rtlpci->pdev, bufferaddress))
812 return;
813 tmp_one = 1;
814 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, false,
815 HW_DESC_RXBUFF_ADDR,
816 (u8 *)&bufferaddress);
817 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, false,
818 HW_DESC_RXPKT_LEN,
819 (u8 *)&rtlpci->rxbuffersize);
820
821 if (index == rtlpci->rxringcount - 1)
822 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, false,
823 HW_DESC_RXERO,
824 &tmp_one);
825
826 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, false, HW_DESC_RXOWN,
827 &tmp_one);
828
829 index = (index + 1) % rtlpci->rxringcount;
830 }
831
832 rtlpci->rx_ring[rx_queue_idx].idx = index;
833 }
834
835 static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id)
836 {
837 struct ieee80211_hw *hw = dev_id;
838 struct rtl_priv *rtlpriv = rtl_priv(hw);
839 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
840 unsigned long flags;
841 u32 inta = 0;
842 u32 intb = 0;
843 irqreturn_t ret = IRQ_HANDLED;
844
845 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
846
847 /*read ISR: 4/8bytes */
848 rtlpriv->cfg->ops->interrupt_recognized(hw, &inta, &intb);
849
850 /*Shared IRQ or HW disappared */
851 if (!inta || inta == 0xffff) {
852 ret = IRQ_NONE;
853 goto done;
854 }
855
856 /*<1> beacon related */
857 if (inta & rtlpriv->cfg->maps[RTL_IMR_TBDOK]) {
858 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
859 "beacon ok interrupt!\n");
860 }
861
862 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_TBDER])) {
863 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
864 "beacon err interrupt!\n");
865 }
866
867 if (inta & rtlpriv->cfg->maps[RTL_IMR_BDOK]) {
868 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, "beacon interrupt!\n");
869 }
870
871 if (inta & rtlpriv->cfg->maps[RTL_IMR_BCNINT]) {
872 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
873 "prepare beacon for interrupt!\n");
874 tasklet_schedule(&rtlpriv->works.irq_prepare_bcn_tasklet);
875 }
876
877 /*<3> Tx related */
878 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_TXFOVW]))
879 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, "IMR_TXFOVW!\n");
880
881 if (inta & rtlpriv->cfg->maps[RTL_IMR_MGNTDOK]) {
882 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
883 "Manage ok interrupt!\n");
884 _rtl_pci_tx_isr(hw, MGNT_QUEUE);
885 }
886
887 if (inta & rtlpriv->cfg->maps[RTL_IMR_HIGHDOK]) {
888 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
889 "HIGH_QUEUE ok interrupt!\n");
890 _rtl_pci_tx_isr(hw, HIGH_QUEUE);
891 }
892
893 if (inta & rtlpriv->cfg->maps[RTL_IMR_BKDOK]) {
894 rtlpriv->link_info.num_tx_inperiod++;
895
896 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
897 "BK Tx OK interrupt!\n");
898 _rtl_pci_tx_isr(hw, BK_QUEUE);
899 }
900
901 if (inta & rtlpriv->cfg->maps[RTL_IMR_BEDOK]) {
902 rtlpriv->link_info.num_tx_inperiod++;
903
904 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
905 "BE TX OK interrupt!\n");
906 _rtl_pci_tx_isr(hw, BE_QUEUE);
907 }
908
909 if (inta & rtlpriv->cfg->maps[RTL_IMR_VIDOK]) {
910 rtlpriv->link_info.num_tx_inperiod++;
911
912 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
913 "VI TX OK interrupt!\n");
914 _rtl_pci_tx_isr(hw, VI_QUEUE);
915 }
916
917 if (inta & rtlpriv->cfg->maps[RTL_IMR_VODOK]) {
918 rtlpriv->link_info.num_tx_inperiod++;
919
920 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
921 "Vo TX OK interrupt!\n");
922 _rtl_pci_tx_isr(hw, VO_QUEUE);
923 }
924
925 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) {
926 if (inta & rtlpriv->cfg->maps[RTL_IMR_COMDOK]) {
927 rtlpriv->link_info.num_tx_inperiod++;
928
929 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
930 "CMD TX OK interrupt!\n");
931 _rtl_pci_tx_isr(hw, TXCMD_QUEUE);
932 }
933 }
934
935 /*<2> Rx related */
936 if (inta & rtlpriv->cfg->maps[RTL_IMR_ROK]) {
937 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, "Rx ok interrupt!\n");
938 _rtl_pci_rx_interrupt(hw);
939 }
940
941 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_RDU])) {
942 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
943 "rx descriptor unavailable!\n");
944 _rtl_pci_rx_interrupt(hw);
945 }
946
947 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_RXFOVW])) {
948 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, "rx overflow !\n");
949 _rtl_pci_rx_interrupt(hw);
950 }
951
952 /*fw related*/
953 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8723AE) {
954 if (inta & rtlpriv->cfg->maps[RTL_IMR_C2HCMD]) {
955 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
956 "firmware interrupt!\n");
957 queue_delayed_work(rtlpriv->works.rtl_wq,
958 &rtlpriv->works.fwevt_wq, 0);
959 }
960 }
961
962 if (rtlpriv->rtlhal.earlymode_enable)
963 tasklet_schedule(&rtlpriv->works.irq_tasklet);
964
965 done:
966 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
967 return ret;
968 }
969
970 static void _rtl_pci_irq_tasklet(struct ieee80211_hw *hw)
971 {
972 _rtl_pci_tx_chk_waitq(hw);
973 }
974
975 static void _rtl_pci_prepare_bcn_tasklet(struct ieee80211_hw *hw)
976 {
977 struct rtl_priv *rtlpriv = rtl_priv(hw);
978 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
979 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
980 struct rtl8192_tx_ring *ring = NULL;
981 struct ieee80211_hdr *hdr = NULL;
982 struct ieee80211_tx_info *info = NULL;
983 struct sk_buff *pskb = NULL;
984 struct rtl_tx_desc *pdesc = NULL;
985 struct rtl_tcb_desc tcb_desc;
986 /*This is for new trx flow*/
987 struct rtl_tx_buffer_desc *pbuffer_desc = NULL;
988 u8 temp_one = 1;
989
990 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
991 ring = &rtlpci->tx_ring[BEACON_QUEUE];
992 pskb = __skb_dequeue(&ring->queue);
993 if (pskb) {
994 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
995 pci_unmap_single(rtlpci->pdev, rtlpriv->cfg->ops->get_desc(
996 (u8 *) entry, true, HW_DESC_TXBUFF_ADDR),
997 pskb->len, PCI_DMA_TODEVICE);
998 kfree_skb(pskb);
999 }
1000
1001 /*NB: the beacon data buffer must be 32-bit aligned. */
1002 pskb = ieee80211_beacon_get(hw, mac->vif);
1003 if (pskb == NULL)
1004 return;
1005 hdr = rtl_get_hdr(pskb);
1006 info = IEEE80211_SKB_CB(pskb);
1007 pdesc = &ring->desc[0];
1008 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *) pdesc,
1009 (u8 *)pbuffer_desc, info, NULL, pskb,
1010 BEACON_QUEUE, &tcb_desc);
1011
1012 __skb_queue_tail(&ring->queue, pskb);
1013
1014 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true, HW_DESC_OWN,
1015 &temp_one);
1016
1017 return;
1018 }
1019
1020 static void _rtl_pci_init_trx_var(struct ieee80211_hw *hw)
1021 {
1022 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1023 u8 i;
1024
1025 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1026 rtlpci->txringcount[i] = RT_TXDESC_NUM;
1027
1028 /*
1029 *we just alloc 2 desc for beacon queue,
1030 *because we just need first desc in hw beacon.
1031 */
1032 rtlpci->txringcount[BEACON_QUEUE] = 2;
1033
1034 /*
1035 *BE queue need more descriptor for performance
1036 *consideration or, No more tx desc will happen,
1037 *and may cause mac80211 mem leakage.
1038 */
1039 rtlpci->txringcount[BE_QUEUE] = RT_TXDESC_NUM_BE_QUEUE;
1040
1041 rtlpci->rxbuffersize = 9100; /*2048/1024; */
1042 rtlpci->rxringcount = RTL_PCI_MAX_RX_COUNT; /*64; */
1043 }
1044
1045 static void _rtl_pci_init_struct(struct ieee80211_hw *hw,
1046 struct pci_dev *pdev)
1047 {
1048 struct rtl_priv *rtlpriv = rtl_priv(hw);
1049 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1050 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1051 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1052
1053 rtlpci->up_first_time = true;
1054 rtlpci->being_init_adapter = false;
1055
1056 rtlhal->hw = hw;
1057 rtlpci->pdev = pdev;
1058
1059 /*Tx/Rx related var */
1060 _rtl_pci_init_trx_var(hw);
1061
1062 /*IBSS*/ mac->beacon_interval = 100;
1063
1064 /*AMPDU*/
1065 mac->min_space_cfg = 0;
1066 mac->max_mss_density = 0;
1067 /*set sane AMPDU defaults */
1068 mac->current_ampdu_density = 7;
1069 mac->current_ampdu_factor = 3;
1070
1071 /*QOS*/
1072 rtlpci->acm_method = EACMWAY2_SW;
1073
1074 /*task */
1075 tasklet_init(&rtlpriv->works.irq_tasklet,
1076 (void (*)(unsigned long))_rtl_pci_irq_tasklet,
1077 (unsigned long)hw);
1078 tasklet_init(&rtlpriv->works.irq_prepare_bcn_tasklet,
1079 (void (*)(unsigned long))_rtl_pci_prepare_bcn_tasklet,
1080 (unsigned long)hw);
1081 INIT_WORK(&rtlpriv->works.lps_change_work,
1082 rtl_lps_change_work_callback);
1083 }
1084
1085 static int _rtl_pci_init_tx_ring(struct ieee80211_hw *hw,
1086 unsigned int prio, unsigned int entries)
1087 {
1088 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1089 struct rtl_priv *rtlpriv = rtl_priv(hw);
1090 struct rtl_tx_desc *ring;
1091 dma_addr_t dma;
1092 u32 nextdescaddress;
1093 int i;
1094
1095 ring = pci_zalloc_consistent(rtlpci->pdev, sizeof(*ring) * entries,
1096 &dma);
1097 if (!ring || (unsigned long)ring & 0xFF) {
1098 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1099 "Cannot allocate TX ring (prio = %d)\n", prio);
1100 return -ENOMEM;
1101 }
1102
1103 rtlpci->tx_ring[prio].desc = ring;
1104 rtlpci->tx_ring[prio].dma = dma;
1105 rtlpci->tx_ring[prio].idx = 0;
1106 rtlpci->tx_ring[prio].entries = entries;
1107 skb_queue_head_init(&rtlpci->tx_ring[prio].queue);
1108
1109 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "queue:%d, ring_addr:%p\n",
1110 prio, ring);
1111
1112 for (i = 0; i < entries; i++) {
1113 nextdescaddress = (u32) dma +
1114 ((i + 1) % entries) *
1115 sizeof(*ring);
1116
1117 rtlpriv->cfg->ops->set_desc(hw, (u8 *)&(ring[i]),
1118 true, HW_DESC_TX_NEXTDESC_ADDR,
1119 (u8 *)&nextdescaddress);
1120 }
1121
1122 return 0;
1123 }
1124
1125 static int _rtl_pci_init_rx_ring(struct ieee80211_hw *hw)
1126 {
1127 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1128 struct rtl_priv *rtlpriv = rtl_priv(hw);
1129 struct rtl_rx_desc *entry = NULL;
1130 int i, rx_queue_idx;
1131 u8 tmp_one = 1;
1132
1133 /*
1134 *rx_queue_idx 0:RX_MPDU_QUEUE
1135 *rx_queue_idx 1:RX_CMD_QUEUE
1136 */
1137 for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
1138 rx_queue_idx++) {
1139 rtlpci->rx_ring[rx_queue_idx].desc =
1140 pci_zalloc_consistent(rtlpci->pdev,
1141 sizeof(*rtlpci->rx_ring[rx_queue_idx].desc) * rtlpci->rxringcount,
1142 &rtlpci->rx_ring[rx_queue_idx].dma);
1143
1144 if (!rtlpci->rx_ring[rx_queue_idx].desc ||
1145 (unsigned long)rtlpci->rx_ring[rx_queue_idx].desc & 0xFF) {
1146 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1147 "Cannot allocate RX ring\n");
1148 return -ENOMEM;
1149 }
1150
1151 rtlpci->rx_ring[rx_queue_idx].idx = 0;
1152
1153 /* If amsdu_8k is disabled, set buffersize to 4096. This
1154 * change will reduce memory fragmentation.
1155 */
1156 if (rtlpci->rxbuffersize > 4096 &&
1157 rtlpriv->rtlhal.disable_amsdu_8k)
1158 rtlpci->rxbuffersize = 4096;
1159
1160 for (i = 0; i < rtlpci->rxringcount; i++) {
1161 struct sk_buff *skb =
1162 dev_alloc_skb(rtlpci->rxbuffersize);
1163 u32 bufferaddress;
1164 if (!skb)
1165 return 0;
1166 kmemleak_not_leak(skb);
1167 entry = &rtlpci->rx_ring[rx_queue_idx].desc[i];
1168
1169 /*skb->dev = dev; */
1170
1171 rtlpci->rx_ring[rx_queue_idx].rx_buf[i] = skb;
1172
1173 /*
1174 *just set skb->cb to mapping addr
1175 *for pci_unmap_single use
1176 */
1177 *((dma_addr_t *) skb->cb) =
1178 pci_map_single(rtlpci->pdev, skb_tail_pointer(skb),
1179 rtlpci->rxbuffersize,
1180 PCI_DMA_FROMDEVICE);
1181
1182 bufferaddress = (*((dma_addr_t *)skb->cb));
1183 if (pci_dma_mapping_error(rtlpci->pdev, bufferaddress)) {
1184 dev_kfree_skb_any(skb);
1185 return 1;
1186 }
1187 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
1188 HW_DESC_RXBUFF_ADDR,
1189 (u8 *)&bufferaddress);
1190 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
1191 HW_DESC_RXPKT_LEN,
1192 (u8 *)&rtlpci->
1193 rxbuffersize);
1194 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
1195 HW_DESC_RXOWN,
1196 &tmp_one);
1197 }
1198
1199 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
1200 HW_DESC_RXERO, &tmp_one);
1201 }
1202 return 0;
1203 }
1204
1205 static void _rtl_pci_free_tx_ring(struct ieee80211_hw *hw,
1206 unsigned int prio)
1207 {
1208 struct rtl_priv *rtlpriv = rtl_priv(hw);
1209 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1210 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
1211
1212 while (skb_queue_len(&ring->queue)) {
1213 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
1214 struct sk_buff *skb = __skb_dequeue(&ring->queue);
1215
1216 pci_unmap_single(rtlpci->pdev,
1217 rtlpriv->cfg->
1218 ops->get_desc((u8 *) entry, true,
1219 HW_DESC_TXBUFF_ADDR),
1220 skb->len, PCI_DMA_TODEVICE);
1221 kfree_skb(skb);
1222 ring->idx = (ring->idx + 1) % ring->entries;
1223 }
1224
1225 if (ring->desc) {
1226 pci_free_consistent(rtlpci->pdev,
1227 sizeof(*ring->desc) * ring->entries,
1228 ring->desc, ring->dma);
1229 ring->desc = NULL;
1230 }
1231 }
1232
1233 static void _rtl_pci_free_rx_ring(struct rtl_pci *rtlpci)
1234 {
1235 int i, rx_queue_idx;
1236
1237 /*rx_queue_idx 0:RX_MPDU_QUEUE */
1238 /*rx_queue_idx 1:RX_CMD_QUEUE */
1239 for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
1240 rx_queue_idx++) {
1241 for (i = 0; i < rtlpci->rxringcount; i++) {
1242 struct sk_buff *skb =
1243 rtlpci->rx_ring[rx_queue_idx].rx_buf[i];
1244 if (!skb)
1245 continue;
1246
1247 pci_unmap_single(rtlpci->pdev,
1248 *((dma_addr_t *) skb->cb),
1249 rtlpci->rxbuffersize,
1250 PCI_DMA_FROMDEVICE);
1251 kfree_skb(skb);
1252 }
1253
1254 if (rtlpci->rx_ring[rx_queue_idx].desc) {
1255 pci_free_consistent(rtlpci->pdev,
1256 sizeof(*rtlpci->rx_ring[rx_queue_idx].
1257 desc) * rtlpci->rxringcount,
1258 rtlpci->rx_ring[rx_queue_idx].desc,
1259 rtlpci->rx_ring[rx_queue_idx].dma);
1260 rtlpci->rx_ring[rx_queue_idx].desc = NULL;
1261 }
1262 }
1263 }
1264
1265 static int _rtl_pci_init_trx_ring(struct ieee80211_hw *hw)
1266 {
1267 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1268 int ret;
1269 int i;
1270
1271 ret = _rtl_pci_init_rx_ring(hw);
1272 if (ret)
1273 return ret;
1274
1275 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1276 ret = _rtl_pci_init_tx_ring(hw, i,
1277 rtlpci->txringcount[i]);
1278 if (ret)
1279 goto err_free_rings;
1280 }
1281
1282 return 0;
1283
1284 err_free_rings:
1285 _rtl_pci_free_rx_ring(rtlpci);
1286
1287 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1288 if (rtlpci->tx_ring[i].desc)
1289 _rtl_pci_free_tx_ring(hw, i);
1290
1291 return 1;
1292 }
1293
1294 static int _rtl_pci_deinit_trx_ring(struct ieee80211_hw *hw)
1295 {
1296 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1297 u32 i;
1298
1299 /*free rx rings */
1300 _rtl_pci_free_rx_ring(rtlpci);
1301
1302 /*free tx rings */
1303 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1304 _rtl_pci_free_tx_ring(hw, i);
1305
1306 return 0;
1307 }
1308
1309 int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw)
1310 {
1311 struct rtl_priv *rtlpriv = rtl_priv(hw);
1312 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1313 int i, rx_queue_idx;
1314 unsigned long flags;
1315 u8 tmp_one = 1;
1316
1317 /*rx_queue_idx 0:RX_MPDU_QUEUE */
1318 /*rx_queue_idx 1:RX_CMD_QUEUE */
1319 for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
1320 rx_queue_idx++) {
1321 /*
1322 *force the rx_ring[RX_MPDU_QUEUE/
1323 *RX_CMD_QUEUE].idx to the first one
1324 */
1325 if (rtlpci->rx_ring[rx_queue_idx].desc) {
1326 struct rtl_rx_desc *entry = NULL;
1327
1328 for (i = 0; i < rtlpci->rxringcount; i++) {
1329 entry = &rtlpci->rx_ring[rx_queue_idx].desc[i];
1330 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry,
1331 false,
1332 HW_DESC_RXOWN,
1333 &tmp_one);
1334 }
1335 rtlpci->rx_ring[rx_queue_idx].idx = 0;
1336 }
1337 }
1338
1339 /*
1340 *after reset, release previous pending packet,
1341 *and force the tx idx to the first one
1342 */
1343 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1344 if (rtlpci->tx_ring[i].desc) {
1345 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[i];
1346
1347 while (skb_queue_len(&ring->queue)) {
1348 struct rtl_tx_desc *entry;
1349 struct sk_buff *skb;
1350
1351 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock,
1352 flags);
1353 entry = &ring->desc[ring->idx];
1354 skb = __skb_dequeue(&ring->queue);
1355 pci_unmap_single(rtlpci->pdev,
1356 rtlpriv->cfg->ops->
1357 get_desc((u8 *)
1358 entry,
1359 true,
1360 HW_DESC_TXBUFF_ADDR),
1361 skb->len, PCI_DMA_TODEVICE);
1362 ring->idx = (ring->idx + 1) % ring->entries;
1363 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock,
1364 flags);
1365 kfree_skb(skb);
1366 }
1367 ring->idx = 0;
1368 }
1369 }
1370
1371 return 0;
1372 }
1373
1374 static bool rtl_pci_tx_chk_waitq_insert(struct ieee80211_hw *hw,
1375 struct ieee80211_sta *sta,
1376 struct sk_buff *skb)
1377 {
1378 struct rtl_priv *rtlpriv = rtl_priv(hw);
1379 struct rtl_sta_info *sta_entry = NULL;
1380 u8 tid = rtl_get_tid(skb);
1381 __le16 fc = rtl_get_fc(skb);
1382
1383 if (!sta)
1384 return false;
1385 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1386
1387 if (!rtlpriv->rtlhal.earlymode_enable)
1388 return false;
1389 if (ieee80211_is_nullfunc(fc))
1390 return false;
1391 if (ieee80211_is_qos_nullfunc(fc))
1392 return false;
1393 if (ieee80211_is_pspoll(fc))
1394 return false;
1395 if (sta_entry->tids[tid].agg.agg_state != RTL_AGG_OPERATIONAL)
1396 return false;
1397 if (_rtl_mac_to_hwqueue(hw, skb) > VO_QUEUE)
1398 return false;
1399 if (tid > 7)
1400 return false;
1401
1402 /* maybe every tid should be checked */
1403 if (!rtlpriv->link_info.higher_busytxtraffic[tid])
1404 return false;
1405
1406 spin_lock_bh(&rtlpriv->locks.waitq_lock);
1407 skb_queue_tail(&rtlpriv->mac80211.skb_waitq[tid], skb);
1408 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
1409
1410 return true;
1411 }
1412
1413 static int rtl_pci_tx(struct ieee80211_hw *hw,
1414 struct ieee80211_sta *sta,
1415 struct sk_buff *skb,
1416 struct rtl_tcb_desc *ptcb_desc)
1417 {
1418 struct rtl_priv *rtlpriv = rtl_priv(hw);
1419 struct rtl_sta_info *sta_entry = NULL;
1420 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1421 struct rtl8192_tx_ring *ring;
1422 struct rtl_tx_desc *pdesc;
1423 struct rtl_tx_buffer_desc *ptx_bd_desc = NULL;
1424 u8 idx;
1425 u8 hw_queue = _rtl_mac_to_hwqueue(hw, skb);
1426 unsigned long flags;
1427 struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
1428 __le16 fc = rtl_get_fc(skb);
1429 u8 *pda_addr = hdr->addr1;
1430 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1431 /*ssn */
1432 u8 tid = 0;
1433 u16 seq_number = 0;
1434 u8 own;
1435 u8 temp_one = 1;
1436
1437 if (ieee80211_is_mgmt(fc))
1438 rtl_tx_mgmt_proc(hw, skb);
1439
1440 if (rtlpriv->psc.sw_ps_enabled) {
1441 if (ieee80211_is_data(fc) && !ieee80211_is_nullfunc(fc) &&
1442 !ieee80211_has_pm(fc))
1443 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
1444 }
1445
1446 rtl_action_proc(hw, skb, true);
1447
1448 if (is_multicast_ether_addr(pda_addr))
1449 rtlpriv->stats.txbytesmulticast += skb->len;
1450 else if (is_broadcast_ether_addr(pda_addr))
1451 rtlpriv->stats.txbytesbroadcast += skb->len;
1452 else
1453 rtlpriv->stats.txbytesunicast += skb->len;
1454
1455 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1456 ring = &rtlpci->tx_ring[hw_queue];
1457 if (hw_queue != BEACON_QUEUE)
1458 idx = (ring->idx + skb_queue_len(&ring->queue)) %
1459 ring->entries;
1460 else
1461 idx = 0;
1462
1463 pdesc = &ring->desc[idx];
1464 if (rtlpriv->use_new_trx_flow) {
1465 ptx_bd_desc = &ring->buffer_desc[idx];
1466 } else {
1467 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *)pdesc,
1468 true, HW_DESC_OWN);
1469
1470 if ((own == 1) && (hw_queue != BEACON_QUEUE)) {
1471 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1472 "No more TX desc@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%d\n",
1473 hw_queue, ring->idx, idx,
1474 skb_queue_len(&ring->queue));
1475
1476 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock,
1477 flags);
1478 return skb->len;
1479 }
1480 }
1481
1482 if (ieee80211_is_data_qos(fc)) {
1483 tid = rtl_get_tid(skb);
1484 if (sta) {
1485 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1486 seq_number = (le16_to_cpu(hdr->seq_ctrl) &
1487 IEEE80211_SCTL_SEQ) >> 4;
1488 seq_number += 1;
1489
1490 if (!ieee80211_has_morefrags(hdr->frame_control))
1491 sta_entry->tids[tid].seq_number = seq_number;
1492 }
1493 }
1494
1495 if (ieee80211_is_data(fc))
1496 rtlpriv->cfg->ops->led_control(hw, LED_CTL_TX);
1497
1498 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc,
1499 (u8 *)ptx_bd_desc, info, sta, skb, hw_queue, ptcb_desc);
1500
1501 __skb_queue_tail(&ring->queue, skb);
1502
1503 if (rtlpriv->use_new_trx_flow) {
1504 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true,
1505 HW_DESC_OWN, &hw_queue);
1506 } else {
1507 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true,
1508 HW_DESC_OWN, &temp_one);
1509 }
1510
1511 if ((ring->entries - skb_queue_len(&ring->queue)) < 2 &&
1512 hw_queue != BEACON_QUEUE) {
1513 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
1514 "less desc left, stop skb_queue@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%d\n",
1515 hw_queue, ring->idx, idx,
1516 skb_queue_len(&ring->queue));
1517
1518 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
1519 }
1520
1521 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1522
1523 rtlpriv->cfg->ops->tx_polling(hw, hw_queue);
1524
1525 return 0;
1526 }
1527
1528 static void rtl_pci_flush(struct ieee80211_hw *hw, bool drop)
1529 {
1530 struct rtl_priv *rtlpriv = rtl_priv(hw);
1531 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1532 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1533 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1534 u16 i = 0;
1535 int queue_id;
1536 struct rtl8192_tx_ring *ring;
1537
1538 if (mac->skip_scan)
1539 return;
1540
1541 for (queue_id = RTL_PCI_MAX_TX_QUEUE_COUNT - 1; queue_id >= 0;) {
1542 u32 queue_len;
1543 ring = &pcipriv->dev.tx_ring[queue_id];
1544 queue_len = skb_queue_len(&ring->queue);
1545 if (queue_len == 0 || queue_id == BEACON_QUEUE ||
1546 queue_id == TXCMD_QUEUE) {
1547 queue_id--;
1548 continue;
1549 } else {
1550 msleep(20);
1551 i++;
1552 }
1553
1554 /* we just wait 1s for all queues */
1555 if (rtlpriv->psc.rfpwr_state == ERFOFF ||
1556 is_hal_stop(rtlhal) || i >= 200)
1557 return;
1558 }
1559 }
1560
1561 static void rtl_pci_deinit(struct ieee80211_hw *hw)
1562 {
1563 struct rtl_priv *rtlpriv = rtl_priv(hw);
1564 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1565
1566 _rtl_pci_deinit_trx_ring(hw);
1567
1568 synchronize_irq(rtlpci->pdev->irq);
1569 tasklet_kill(&rtlpriv->works.irq_tasklet);
1570 cancel_work_sync(&rtlpriv->works.lps_change_work);
1571
1572 flush_workqueue(rtlpriv->works.rtl_wq);
1573 destroy_workqueue(rtlpriv->works.rtl_wq);
1574
1575 }
1576
1577 static int rtl_pci_init(struct ieee80211_hw *hw, struct pci_dev *pdev)
1578 {
1579 struct rtl_priv *rtlpriv = rtl_priv(hw);
1580 int err;
1581
1582 _rtl_pci_init_struct(hw, pdev);
1583
1584 err = _rtl_pci_init_trx_ring(hw);
1585 if (err) {
1586 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1587 "tx ring initialization failed\n");
1588 return err;
1589 }
1590
1591 return 0;
1592 }
1593
1594 static int rtl_pci_start(struct ieee80211_hw *hw)
1595 {
1596 struct rtl_priv *rtlpriv = rtl_priv(hw);
1597 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1598 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1599 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1600
1601 int err;
1602
1603 rtl_pci_reset_trx_ring(hw);
1604
1605 rtlpci->driver_is_goingto_unload = false;
1606 err = rtlpriv->cfg->ops->hw_init(hw);
1607 if (err) {
1608 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1609 "Failed to config hardware!\n");
1610 return err;
1611 }
1612
1613 rtlpriv->cfg->ops->enable_interrupt(hw);
1614 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "enable_interrupt OK\n");
1615
1616 rtl_init_rx_config(hw);
1617
1618 /*should be after adapter start and interrupt enable. */
1619 set_hal_start(rtlhal);
1620
1621 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1622
1623 rtlpci->up_first_time = false;
1624
1625 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "OK\n");
1626 return 0;
1627 }
1628
1629 static void rtl_pci_stop(struct ieee80211_hw *hw)
1630 {
1631 struct rtl_priv *rtlpriv = rtl_priv(hw);
1632 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1633 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1634 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1635 unsigned long flags;
1636 u8 RFInProgressTimeOut = 0;
1637
1638 /*
1639 *should be before disable interrupt&adapter
1640 *and will do it immediately.
1641 */
1642 set_hal_stop(rtlhal);
1643
1644 rtlpci->driver_is_goingto_unload = true;
1645 rtlpriv->cfg->ops->disable_interrupt(hw);
1646 cancel_work_sync(&rtlpriv->works.lps_change_work);
1647
1648 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1649 while (ppsc->rfchange_inprogress) {
1650 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1651 if (RFInProgressTimeOut > 100) {
1652 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1653 break;
1654 }
1655 mdelay(1);
1656 RFInProgressTimeOut++;
1657 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1658 }
1659 ppsc->rfchange_inprogress = true;
1660 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1661
1662 rtlpriv->cfg->ops->hw_disable(hw);
1663 /* some things are not needed if firmware not available */
1664 if (!rtlpriv->max_fw_size)
1665 return;
1666 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1667
1668 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1669 ppsc->rfchange_inprogress = false;
1670 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1671
1672 rtl_pci_enable_aspm(hw);
1673 }
1674
1675 static bool _rtl_pci_find_adapter(struct pci_dev *pdev,
1676 struct ieee80211_hw *hw)
1677 {
1678 struct rtl_priv *rtlpriv = rtl_priv(hw);
1679 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1680 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1681 struct pci_dev *bridge_pdev = pdev->bus->self;
1682 u16 venderid;
1683 u16 deviceid;
1684 u8 revisionid;
1685 u16 irqline;
1686 u8 tmp;
1687
1688 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN;
1689 venderid = pdev->vendor;
1690 deviceid = pdev->device;
1691 pci_read_config_byte(pdev, 0x8, &revisionid);
1692 pci_read_config_word(pdev, 0x3C, &irqline);
1693
1694 /* PCI ID 0x10ec:0x8192 occurs for both RTL8192E, which uses
1695 * r8192e_pci, and RTL8192SE, which uses this driver. If the
1696 * revision ID is RTL_PCI_REVISION_ID_8192PCIE (0x01), then
1697 * the correct driver is r8192e_pci, thus this routine should
1698 * return false.
1699 */
1700 if (deviceid == RTL_PCI_8192SE_DID &&
1701 revisionid == RTL_PCI_REVISION_ID_8192PCIE)
1702 return false;
1703
1704 if (deviceid == RTL_PCI_8192_DID ||
1705 deviceid == RTL_PCI_0044_DID ||
1706 deviceid == RTL_PCI_0047_DID ||
1707 deviceid == RTL_PCI_8192SE_DID ||
1708 deviceid == RTL_PCI_8174_DID ||
1709 deviceid == RTL_PCI_8173_DID ||
1710 deviceid == RTL_PCI_8172_DID ||
1711 deviceid == RTL_PCI_8171_DID) {
1712 switch (revisionid) {
1713 case RTL_PCI_REVISION_ID_8192PCIE:
1714 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1715 "8192 PCI-E is found - vid/did=%x/%x\n",
1716 venderid, deviceid);
1717 rtlhal->hw_type = HARDWARE_TYPE_RTL8192E;
1718 return false;
1719 case RTL_PCI_REVISION_ID_8192SE:
1720 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1721 "8192SE is found - vid/did=%x/%x\n",
1722 venderid, deviceid);
1723 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1724 break;
1725 default:
1726 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1727 "Err: Unknown device - vid/did=%x/%x\n",
1728 venderid, deviceid);
1729 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1730 break;
1731
1732 }
1733 } else if (deviceid == RTL_PCI_8723AE_DID) {
1734 rtlhal->hw_type = HARDWARE_TYPE_RTL8723AE;
1735 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1736 "8723AE PCI-E is found - "
1737 "vid/did=%x/%x\n", venderid, deviceid);
1738 } else if (deviceid == RTL_PCI_8192CET_DID ||
1739 deviceid == RTL_PCI_8192CE_DID ||
1740 deviceid == RTL_PCI_8191CE_DID ||
1741 deviceid == RTL_PCI_8188CE_DID) {
1742 rtlhal->hw_type = HARDWARE_TYPE_RTL8192CE;
1743 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1744 "8192C PCI-E is found - vid/did=%x/%x\n",
1745 venderid, deviceid);
1746 } else if (deviceid == RTL_PCI_8192DE_DID ||
1747 deviceid == RTL_PCI_8192DE_DID2) {
1748 rtlhal->hw_type = HARDWARE_TYPE_RTL8192DE;
1749 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1750 "8192D PCI-E is found - vid/did=%x/%x\n",
1751 venderid, deviceid);
1752 } else if (deviceid == RTL_PCI_8188EE_DID) {
1753 rtlhal->hw_type = HARDWARE_TYPE_RTL8188EE;
1754 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1755 "Find adapter, Hardware type is 8188EE\n");
1756 } else {
1757 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1758 "Err: Unknown device - vid/did=%x/%x\n",
1759 venderid, deviceid);
1760
1761 rtlhal->hw_type = RTL_DEFAULT_HARDWARE_TYPE;
1762 }
1763
1764 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) {
1765 if (revisionid == 0 || revisionid == 1) {
1766 if (revisionid == 0) {
1767 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1768 "Find 92DE MAC0\n");
1769 rtlhal->interfaceindex = 0;
1770 } else if (revisionid == 1) {
1771 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1772 "Find 92DE MAC1\n");
1773 rtlhal->interfaceindex = 1;
1774 }
1775 } else {
1776 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1777 "Unknown device - VendorID/DeviceID=%x/%x, Revision=%x\n",
1778 venderid, deviceid, revisionid);
1779 rtlhal->interfaceindex = 0;
1780 }
1781 }
1782 /*find bus info */
1783 pcipriv->ndis_adapter.busnumber = pdev->bus->number;
1784 pcipriv->ndis_adapter.devnumber = PCI_SLOT(pdev->devfn);
1785 pcipriv->ndis_adapter.funcnumber = PCI_FUNC(pdev->devfn);
1786
1787 /* some ARM have no bridge_pdev and will crash here
1788 * so we should check if bridge_pdev is NULL
1789 */
1790 if (bridge_pdev) {
1791 /*find bridge info if available */
1792 pcipriv->ndis_adapter.pcibridge_vendorid = bridge_pdev->vendor;
1793 for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) {
1794 if (bridge_pdev->vendor == pcibridge_vendors[tmp]) {
1795 pcipriv->ndis_adapter.pcibridge_vendor = tmp;
1796 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1797 "Pci Bridge Vendor is found index: %d\n",
1798 tmp);
1799 break;
1800 }
1801 }
1802 }
1803
1804 if (pcipriv->ndis_adapter.pcibridge_vendor !=
1805 PCI_BRIDGE_VENDOR_UNKNOWN) {
1806 pcipriv->ndis_adapter.pcibridge_busnum =
1807 bridge_pdev->bus->number;
1808 pcipriv->ndis_adapter.pcibridge_devnum =
1809 PCI_SLOT(bridge_pdev->devfn);
1810 pcipriv->ndis_adapter.pcibridge_funcnum =
1811 PCI_FUNC(bridge_pdev->devfn);
1812 pcipriv->ndis_adapter.pcibridge_pciehdr_offset =
1813 pci_pcie_cap(bridge_pdev);
1814 pcipriv->ndis_adapter.num4bytes =
1815 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10) / 4;
1816
1817 rtl_pci_get_linkcontrol_field(hw);
1818
1819 if (pcipriv->ndis_adapter.pcibridge_vendor ==
1820 PCI_BRIDGE_VENDOR_AMD) {
1821 pcipriv->ndis_adapter.amd_l1_patch =
1822 rtl_pci_get_amd_l1_patch(hw);
1823 }
1824 }
1825
1826 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1827 "pcidev busnumber:devnumber:funcnumber:vendor:link_ctl %d:%d:%d:%x:%x\n",
1828 pcipriv->ndis_adapter.busnumber,
1829 pcipriv->ndis_adapter.devnumber,
1830 pcipriv->ndis_adapter.funcnumber,
1831 pdev->vendor, pcipriv->ndis_adapter.linkctrl_reg);
1832
1833 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1834 "pci_bridge busnumber:devnumber:funcnumber:vendor:pcie_cap:link_ctl_reg:amd %d:%d:%d:%x:%x:%x:%x\n",
1835 pcipriv->ndis_adapter.pcibridge_busnum,
1836 pcipriv->ndis_adapter.pcibridge_devnum,
1837 pcipriv->ndis_adapter.pcibridge_funcnum,
1838 pcibridge_vendors[pcipriv->ndis_adapter.pcibridge_vendor],
1839 pcipriv->ndis_adapter.pcibridge_pciehdr_offset,
1840 pcipriv->ndis_adapter.pcibridge_linkctrlreg,
1841 pcipriv->ndis_adapter.amd_l1_patch);
1842
1843 rtl_pci_parse_configuration(pdev, hw);
1844 list_add_tail(&rtlpriv->list, &rtlpriv->glb_var->glb_priv_list);
1845
1846 return true;
1847 }
1848
1849 static int rtl_pci_intr_mode_msi(struct ieee80211_hw *hw)
1850 {
1851 struct rtl_priv *rtlpriv = rtl_priv(hw);
1852 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1853 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
1854 int ret;
1855
1856 ret = pci_enable_msi(rtlpci->pdev);
1857 if (ret < 0)
1858 return ret;
1859
1860 ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt,
1861 IRQF_SHARED, KBUILD_MODNAME, hw);
1862 if (ret < 0) {
1863 pci_disable_msi(rtlpci->pdev);
1864 return ret;
1865 }
1866
1867 rtlpci->using_msi = true;
1868
1869 RT_TRACE(rtlpriv, COMP_INIT|COMP_INTR, DBG_DMESG,
1870 "MSI Interrupt Mode!\n");
1871 return 0;
1872 }
1873
1874 static int rtl_pci_intr_mode_legacy(struct ieee80211_hw *hw)
1875 {
1876 struct rtl_priv *rtlpriv = rtl_priv(hw);
1877 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1878 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
1879 int ret;
1880
1881 ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt,
1882 IRQF_SHARED, KBUILD_MODNAME, hw);
1883 if (ret < 0)
1884 return ret;
1885
1886 rtlpci->using_msi = false;
1887 RT_TRACE(rtlpriv, COMP_INIT|COMP_INTR, DBG_DMESG,
1888 "Pin-based Interrupt Mode!\n");
1889 return 0;
1890 }
1891
1892 static int rtl_pci_intr_mode_decide(struct ieee80211_hw *hw)
1893 {
1894 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1895 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
1896 int ret;
1897
1898 if (rtlpci->msi_support) {
1899 ret = rtl_pci_intr_mode_msi(hw);
1900 if (ret < 0)
1901 ret = rtl_pci_intr_mode_legacy(hw);
1902 } else {
1903 ret = rtl_pci_intr_mode_legacy(hw);
1904 }
1905 return ret;
1906 }
1907
1908 int rtl_pci_probe(struct pci_dev *pdev,
1909 const struct pci_device_id *id)
1910 {
1911 struct ieee80211_hw *hw = NULL;
1912
1913 struct rtl_priv *rtlpriv = NULL;
1914 struct rtl_pci_priv *pcipriv = NULL;
1915 struct rtl_pci *rtlpci;
1916 unsigned long pmem_start, pmem_len, pmem_flags;
1917 int err;
1918
1919 err = pci_enable_device(pdev);
1920 if (err) {
1921 RT_ASSERT(false, "%s : Cannot enable new PCI device\n",
1922 pci_name(pdev));
1923 return err;
1924 }
1925
1926 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
1927 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
1928 RT_ASSERT(false,
1929 "Unable to obtain 32bit DMA for consistent allocations\n");
1930 err = -ENOMEM;
1931 goto fail1;
1932 }
1933 }
1934
1935 pci_set_master(pdev);
1936
1937 hw = ieee80211_alloc_hw(sizeof(struct rtl_pci_priv) +
1938 sizeof(struct rtl_priv), &rtl_ops);
1939 if (!hw) {
1940 RT_ASSERT(false,
1941 "%s : ieee80211 alloc failed\n", pci_name(pdev));
1942 err = -ENOMEM;
1943 goto fail1;
1944 }
1945
1946 SET_IEEE80211_DEV(hw, &pdev->dev);
1947 pci_set_drvdata(pdev, hw);
1948
1949 rtlpriv = hw->priv;
1950 rtlpriv->hw = hw;
1951 pcipriv = (void *)rtlpriv->priv;
1952 pcipriv->dev.pdev = pdev;
1953 init_completion(&rtlpriv->firmware_loading_complete);
1954
1955 /* init cfg & intf_ops */
1956 rtlpriv->rtlhal.interface = INTF_PCI;
1957 rtlpriv->cfg = (struct rtl_hal_cfg *)(id->driver_data);
1958 rtlpriv->intf_ops = &rtl_pci_ops;
1959 rtlpriv->glb_var = &rtl_global_var;
1960
1961 /*
1962 *init dbgp flags before all
1963 *other functions, because we will
1964 *use it in other funtions like
1965 *RT_TRACE/RT_PRINT/RTL_PRINT_DATA
1966 *you can not use these macro
1967 *before this
1968 */
1969 rtl_dbgp_flag_init(hw);
1970
1971 /* MEM map */
1972 err = pci_request_regions(pdev, KBUILD_MODNAME);
1973 if (err) {
1974 RT_ASSERT(false, "Can't obtain PCI resources\n");
1975 goto fail1;
1976 }
1977
1978 pmem_start = pci_resource_start(pdev, rtlpriv->cfg->bar_id);
1979 pmem_len = pci_resource_len(pdev, rtlpriv->cfg->bar_id);
1980 pmem_flags = pci_resource_flags(pdev, rtlpriv->cfg->bar_id);
1981
1982 /*shared mem start */
1983 rtlpriv->io.pci_mem_start =
1984 (unsigned long)pci_iomap(pdev,
1985 rtlpriv->cfg->bar_id, pmem_len);
1986 if (rtlpriv->io.pci_mem_start == 0) {
1987 RT_ASSERT(false, "Can't map PCI mem\n");
1988 err = -ENOMEM;
1989 goto fail2;
1990 }
1991
1992 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1993 "mem mapped space: start: 0x%08lx len:%08lx flags:%08lx, after map:0x%08lx\n",
1994 pmem_start, pmem_len, pmem_flags,
1995 rtlpriv->io.pci_mem_start);
1996
1997 /* Disable Clk Request */
1998 pci_write_config_byte(pdev, 0x81, 0);
1999 /* leave D3 mode */
2000 pci_write_config_byte(pdev, 0x44, 0);
2001 pci_write_config_byte(pdev, 0x04, 0x06);
2002 pci_write_config_byte(pdev, 0x04, 0x07);
2003
2004 /* find adapter */
2005 if (!_rtl_pci_find_adapter(pdev, hw)) {
2006 err = -ENODEV;
2007 goto fail3;
2008 }
2009
2010 /* Init IO handler */
2011 _rtl_pci_io_handler_init(&pdev->dev, hw);
2012
2013 /*like read eeprom and so on */
2014 rtlpriv->cfg->ops->read_eeprom_info(hw);
2015
2016 /*aspm */
2017 rtl_pci_init_aspm(hw);
2018
2019 /* Init mac80211 sw */
2020 err = rtl_init_core(hw);
2021 if (err) {
2022 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2023 "Can't allocate sw for mac80211\n");
2024 goto fail3;
2025 }
2026
2027 /* Init PCI sw */
2028 err = rtl_pci_init(hw, pdev);
2029 if (err) {
2030 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Failed to init PCI\n");
2031 goto fail3;
2032 }
2033
2034 if (rtlpriv->cfg->ops->init_sw_vars(hw)) {
2035 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Can't init_sw_vars\n");
2036 err = -ENODEV;
2037 goto fail3;
2038 }
2039
2040 rtlpriv->cfg->ops->init_sw_leds(hw);
2041
2042 err = sysfs_create_group(&pdev->dev.kobj, &rtl_attribute_group);
2043 if (err) {
2044 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2045 "failed to create sysfs device attributes\n");
2046 goto fail3;
2047 }
2048
2049 rtlpci = rtl_pcidev(pcipriv);
2050 err = rtl_pci_intr_mode_decide(hw);
2051 if (err) {
2052 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2053 "%s: failed to register IRQ handler\n",
2054 wiphy_name(hw->wiphy));
2055 goto fail3;
2056 }
2057 rtlpci->irq_alloc = 1;
2058
2059 return 0;
2060
2061 fail3:
2062 rtl_deinit_core(hw);
2063
2064 if (rtlpriv->io.pci_mem_start != 0)
2065 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
2066
2067 fail2:
2068 pci_release_regions(pdev);
2069 complete(&rtlpriv->firmware_loading_complete);
2070
2071 fail1:
2072 if (hw)
2073 ieee80211_free_hw(hw);
2074 pci_disable_device(pdev);
2075
2076 return err;
2077
2078 }
2079 EXPORT_SYMBOL(rtl_pci_probe);
2080
2081 void rtl_pci_disconnect(struct pci_dev *pdev)
2082 {
2083 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2084 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2085 struct rtl_priv *rtlpriv = rtl_priv(hw);
2086 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2087 struct rtl_mac *rtlmac = rtl_mac(rtlpriv);
2088
2089 /* just in case driver is removed before firmware callback */
2090 wait_for_completion(&rtlpriv->firmware_loading_complete);
2091 clear_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
2092
2093 sysfs_remove_group(&pdev->dev.kobj, &rtl_attribute_group);
2094
2095 /*ieee80211_unregister_hw will call ops_stop */
2096 if (rtlmac->mac80211_registered == 1) {
2097 ieee80211_unregister_hw(hw);
2098 rtlmac->mac80211_registered = 0;
2099 } else {
2100 rtl_deinit_deferred_work(hw);
2101 rtlpriv->intf_ops->adapter_stop(hw);
2102 }
2103 rtlpriv->cfg->ops->disable_interrupt(hw);
2104
2105 /*deinit rfkill */
2106 rtl_deinit_rfkill(hw);
2107
2108 rtl_pci_deinit(hw);
2109 rtl_deinit_core(hw);
2110 rtlpriv->cfg->ops->deinit_sw_vars(hw);
2111
2112 if (rtlpci->irq_alloc) {
2113 synchronize_irq(rtlpci->pdev->irq);
2114 free_irq(rtlpci->pdev->irq, hw);
2115 rtlpci->irq_alloc = 0;
2116 }
2117
2118 if (rtlpci->using_msi)
2119 pci_disable_msi(rtlpci->pdev);
2120
2121 list_del(&rtlpriv->list);
2122 if (rtlpriv->io.pci_mem_start != 0) {
2123 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
2124 pci_release_regions(pdev);
2125 }
2126
2127 pci_disable_device(pdev);
2128
2129 rtl_pci_disable_aspm(hw);
2130
2131 ieee80211_free_hw(hw);
2132 }
2133 EXPORT_SYMBOL(rtl_pci_disconnect);
2134
2135 #ifdef CONFIG_PM_SLEEP
2136 /***************************************
2137 kernel pci power state define:
2138 PCI_D0 ((pci_power_t __force) 0)
2139 PCI_D1 ((pci_power_t __force) 1)
2140 PCI_D2 ((pci_power_t __force) 2)
2141 PCI_D3hot ((pci_power_t __force) 3)
2142 PCI_D3cold ((pci_power_t __force) 4)
2143 PCI_UNKNOWN ((pci_power_t __force) 5)
2144
2145 This function is called when system
2146 goes into suspend state mac80211 will
2147 call rtl_mac_stop() from the mac80211
2148 suspend function first, So there is
2149 no need to call hw_disable here.
2150 ****************************************/
2151 int rtl_pci_suspend(struct device *dev)
2152 {
2153 struct pci_dev *pdev = to_pci_dev(dev);
2154 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2155 struct rtl_priv *rtlpriv = rtl_priv(hw);
2156
2157 rtlpriv->cfg->ops->hw_suspend(hw);
2158 rtl_deinit_rfkill(hw);
2159
2160 return 0;
2161 }
2162 EXPORT_SYMBOL(rtl_pci_suspend);
2163
2164 int rtl_pci_resume(struct device *dev)
2165 {
2166 struct pci_dev *pdev = to_pci_dev(dev);
2167 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2168 struct rtl_priv *rtlpriv = rtl_priv(hw);
2169
2170 rtlpriv->cfg->ops->hw_resume(hw);
2171 rtl_init_rfkill(hw);
2172 return 0;
2173 }
2174 EXPORT_SYMBOL(rtl_pci_resume);
2175 #endif /* CONFIG_PM_SLEEP */
2176
2177 struct rtl_intf_ops rtl_pci_ops = {
2178 .read_efuse_byte = read_efuse_byte,
2179 .adapter_start = rtl_pci_start,
2180 .adapter_stop = rtl_pci_stop,
2181 .check_buddy_priv = rtl_pci_check_buddy_priv,
2182 .adapter_tx = rtl_pci_tx,
2183 .flush = rtl_pci_flush,
2184 .reset_trx_ring = rtl_pci_reset_trx_ring,
2185 .waitq_insert = rtl_pci_tx_chk_waitq_insert,
2186
2187 .disable_aspm = rtl_pci_disable_aspm,
2188 .enable_aspm = rtl_pci_enable_aspm,
2189 };
Linux kernel - Deliverables
This page took 0.101374 seconds and 5 git commands to generate.