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rtlwifi: rtl8192c: rtl8192ce: rtl8192cu: rtl8192de: rtl8723ae: Add changes required...
[deliverable/linux.git] / drivers / net / wireless / rtlwifi / rtl8192c / dm_common.c
1 /******************************************************************************
2 *
3 * Copyright(c) 2009-2012 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30 #include <linux/export.h>
31 #include "dm_common.h"
32 #include "phy_common.h"
33 #include "../pci.h"
34 #include "../base.h"
35
36 #define BT_RSSI_STATE_NORMAL_POWER BIT_OFFSET_LEN_MASK_32(0, 1)
37 #define BT_RSSI_STATE_AMDPU_OFF BIT_OFFSET_LEN_MASK_32(1, 1)
38 #define BT_RSSI_STATE_SPECIAL_LOW BIT_OFFSET_LEN_MASK_32(2, 1)
39 #define BT_RSSI_STATE_BG_EDCA_LOW BIT_OFFSET_LEN_MASK_32(3, 1)
40 #define BT_RSSI_STATE_TXPOWER_LOW BIT_OFFSET_LEN_MASK_32(4, 1)
41
42 #define RTLPRIV (struct rtl_priv *)
43 #define GET_UNDECORATED_AVERAGE_RSSI(_priv) \
44 ((RTLPRIV(_priv))->mac80211.opmode == \
45 NL80211_IFTYPE_ADHOC) ? \
46 ((RTLPRIV(_priv))->dm.entry_min_undec_sm_pwdb) : \
47 ((RTLPRIV(_priv))->dm.undec_sm_pwdb)
48
49 static const u32 ofdmswing_table[OFDM_TABLE_SIZE] = {
50 0x7f8001fe,
51 0x788001e2,
52 0x71c001c7,
53 0x6b8001ae,
54 0x65400195,
55 0x5fc0017f,
56 0x5a400169,
57 0x55400155,
58 0x50800142,
59 0x4c000130,
60 0x47c0011f,
61 0x43c0010f,
62 0x40000100,
63 0x3c8000f2,
64 0x390000e4,
65 0x35c000d7,
66 0x32c000cb,
67 0x300000c0,
68 0x2d4000b5,
69 0x2ac000ab,
70 0x288000a2,
71 0x26000098,
72 0x24000090,
73 0x22000088,
74 0x20000080,
75 0x1e400079,
76 0x1c800072,
77 0x1b00006c,
78 0x19800066,
79 0x18000060,
80 0x16c0005b,
81 0x15800056,
82 0x14400051,
83 0x1300004c,
84 0x12000048,
85 0x11000044,
86 0x10000040,
87 };
88
89 static const u8 cckswing_table_ch1ch13[CCK_TABLE_SIZE][8] = {
90 {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04},
91 {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04},
92 {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03},
93 {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03},
94 {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03},
95 {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03},
96 {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03},
97 {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03},
98 {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02},
99 {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02},
100 {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02},
101 {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02},
102 {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02},
103 {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02},
104 {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02},
105 {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02},
106 {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01},
107 {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02},
108 {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01},
109 {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},
110 {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},
111 {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01},
112 {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01},
113 {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01},
114 {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01},
115 {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01},
116 {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01},
117 {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01},
118 {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01},
119 {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01},
120 {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01},
121 {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},
122 {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}
123 };
124
125 static const u8 cckswing_table_ch14[CCK_TABLE_SIZE][8] = {
126 {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00},
127 {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00},
128 {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00},
129 {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00},
130 {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00},
131 {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00},
132 {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00},
133 {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00},
134 {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00},
135 {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00},
136 {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00},
137 {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00},
138 {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00},
139 {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00},
140 {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00},
141 {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00},
142 {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00},
143 {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00},
144 {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00},
145 {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},
146 {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},
147 {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00},
148 {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00},
149 {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},
150 {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},
151 {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00},
152 {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},
153 {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},
154 {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},
155 {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},
156 {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},
157 {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},
158 {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}
159 };
160
161 static void rtl92c_dm_diginit(struct ieee80211_hw *hw)
162 {
163 struct rtl_priv *rtlpriv = rtl_priv(hw);
164 struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
165
166 dm_digtable->dig_enable_flag = true;
167 dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
168 dm_digtable->cur_igvalue = 0x20;
169 dm_digtable->pre_igvalue = 0x0;
170 dm_digtable->cursta_cstate = DIG_STA_DISCONNECT;
171 dm_digtable->presta_cstate = DIG_STA_DISCONNECT;
172 dm_digtable->curmultista_cstate = DIG_MULTISTA_DISCONNECT;
173 dm_digtable->rssi_lowthresh = DM_DIG_THRESH_LOW;
174 dm_digtable->rssi_highthresh = DM_DIG_THRESH_HIGH;
175 dm_digtable->fa_lowthresh = DM_FALSEALARM_THRESH_LOW;
176 dm_digtable->fa_highthresh = DM_FALSEALARM_THRESH_HIGH;
177 dm_digtable->rx_gain_max = DM_DIG_MAX;
178 dm_digtable->rx_gain_min = DM_DIG_MIN;
179 dm_digtable->back_val = DM_DIG_BACKOFF_DEFAULT;
180 dm_digtable->back_range_max = DM_DIG_BACKOFF_MAX;
181 dm_digtable->back_range_min = DM_DIG_BACKOFF_MIN;
182 dm_digtable->pre_cck_pd_state = CCK_PD_STAGE_MAX;
183 dm_digtable->cur_cck_pd_state = CCK_PD_STAGE_MAX;
184 }
185
186 static u8 rtl92c_dm_initial_gain_min_pwdb(struct ieee80211_hw *hw)
187 {
188 struct rtl_priv *rtlpriv = rtl_priv(hw);
189 struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
190 long rssi_val_min = 0;
191
192 if ((dm_digtable->curmultista_cstate == DIG_MULTISTA_CONNECT) &&
193 (dm_digtable->cursta_cstate == DIG_STA_CONNECT)) {
194 if (rtlpriv->dm.entry_min_undec_sm_pwdb != 0)
195 rssi_val_min =
196 (rtlpriv->dm.entry_min_undec_sm_pwdb >
197 rtlpriv->dm.undec_sm_pwdb) ?
198 rtlpriv->dm.undec_sm_pwdb :
199 rtlpriv->dm.entry_min_undec_sm_pwdb;
200 else
201 rssi_val_min = rtlpriv->dm.undec_sm_pwdb;
202 } else if (dm_digtable->cursta_cstate == DIG_STA_CONNECT ||
203 dm_digtable->cursta_cstate == DIG_STA_BEFORE_CONNECT) {
204 rssi_val_min = rtlpriv->dm.undec_sm_pwdb;
205 } else if (dm_digtable->curmultista_cstate == DIG_MULTISTA_CONNECT) {
206 rssi_val_min = rtlpriv->dm.entry_min_undec_sm_pwdb;
207 }
208
209 return (u8) rssi_val_min;
210 }
211
212 static void rtl92c_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw)
213 {
214 u32 ret_value;
215 struct rtl_priv *rtlpriv = rtl_priv(hw);
216 struct false_alarm_statistics *falsealm_cnt = &(rtlpriv->falsealm_cnt);
217
218 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER1, MASKDWORD);
219 falsealm_cnt->cnt_parity_fail = ((ret_value & 0xffff0000) >> 16);
220
221 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER2, MASKDWORD);
222 falsealm_cnt->cnt_rate_illegal = (ret_value & 0xffff);
223 falsealm_cnt->cnt_crc8_fail = ((ret_value & 0xffff0000) >> 16);
224
225 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER3, MASKDWORD);
226 falsealm_cnt->cnt_mcs_fail = (ret_value & 0xffff);
227 falsealm_cnt->cnt_ofdm_fail = falsealm_cnt->cnt_parity_fail +
228 falsealm_cnt->cnt_rate_illegal +
229 falsealm_cnt->cnt_crc8_fail + falsealm_cnt->cnt_mcs_fail;
230
231 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, BIT(14), 1);
232 ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERLOWER, MASKBYTE0);
233 falsealm_cnt->cnt_cck_fail = ret_value;
234
235 ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERUPPER, MASKBYTE3);
236 falsealm_cnt->cnt_cck_fail += (ret_value & 0xff) << 8;
237 falsealm_cnt->cnt_all = (falsealm_cnt->cnt_parity_fail +
238 falsealm_cnt->cnt_rate_illegal +
239 falsealm_cnt->cnt_crc8_fail +
240 falsealm_cnt->cnt_mcs_fail +
241 falsealm_cnt->cnt_cck_fail);
242
243 rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 1);
244 rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 0);
245 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 0);
246 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 2);
247
248 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
249 "cnt_parity_fail = %d, cnt_rate_illegal = %d, cnt_crc8_fail = %d, cnt_mcs_fail = %d\n",
250 falsealm_cnt->cnt_parity_fail,
251 falsealm_cnt->cnt_rate_illegal,
252 falsealm_cnt->cnt_crc8_fail, falsealm_cnt->cnt_mcs_fail);
253
254 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
255 "cnt_ofdm_fail = %x, cnt_cck_fail = %x, cnt_all = %x\n",
256 falsealm_cnt->cnt_ofdm_fail,
257 falsealm_cnt->cnt_cck_fail, falsealm_cnt->cnt_all);
258 }
259
260 static void rtl92c_dm_ctrl_initgain_by_fa(struct ieee80211_hw *hw)
261 {
262 struct rtl_priv *rtlpriv = rtl_priv(hw);
263 struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
264 u8 value_igi = dm_digtable->cur_igvalue;
265
266 if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH0)
267 value_igi--;
268 else if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH1)
269 value_igi += 0;
270 else if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH2)
271 value_igi++;
272 else if (rtlpriv->falsealm_cnt.cnt_all >= DM_DIG_FA_TH2)
273 value_igi += 2;
274 if (value_igi > DM_DIG_FA_UPPER)
275 value_igi = DM_DIG_FA_UPPER;
276 else if (value_igi < DM_DIG_FA_LOWER)
277 value_igi = DM_DIG_FA_LOWER;
278 if (rtlpriv->falsealm_cnt.cnt_all > 10000)
279 value_igi = 0x32;
280
281 dm_digtable->cur_igvalue = value_igi;
282 rtl92c_dm_write_dig(hw);
283 }
284
285 static void rtl92c_dm_ctrl_initgain_by_rssi(struct ieee80211_hw *hw)
286 {
287 struct rtl_priv *rtlpriv = rtl_priv(hw);
288 struct dig_t *digtable = &rtlpriv->dm_digtable;
289
290 if (rtlpriv->falsealm_cnt.cnt_all > digtable->fa_highthresh) {
291 if ((digtable->back_val - 2) < digtable->back_range_min)
292 digtable->back_val = digtable->back_range_min;
293 else
294 digtable->back_val -= 2;
295 } else if (rtlpriv->falsealm_cnt.cnt_all < digtable->fa_lowthresh) {
296 if ((digtable->back_val + 2) > digtable->back_range_max)
297 digtable->back_val = digtable->back_range_max;
298 else
299 digtable->back_val += 2;
300 }
301
302 if ((digtable->rssi_val_min + 10 - digtable->back_val) >
303 digtable->rx_gain_max)
304 digtable->cur_igvalue = digtable->rx_gain_max;
305 else if ((digtable->rssi_val_min + 10 -
306 digtable->back_val) < digtable->rx_gain_min)
307 digtable->cur_igvalue = digtable->rx_gain_min;
308 else
309 digtable->cur_igvalue = digtable->rssi_val_min + 10 -
310 digtable->back_val;
311
312 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
313 "rssi_val_min = %x back_val %x\n",
314 digtable->rssi_val_min, digtable->back_val);
315
316 rtl92c_dm_write_dig(hw);
317 }
318
319 static void rtl92c_dm_initial_gain_multi_sta(struct ieee80211_hw *hw)
320 {
321 static u8 initialized; /* initialized to false */
322 struct rtl_priv *rtlpriv = rtl_priv(hw);
323 struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
324 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
325 long rssi_strength = rtlpriv->dm.entry_min_undec_sm_pwdb;
326 bool multi_sta = false;
327
328 if (mac->opmode == NL80211_IFTYPE_ADHOC)
329 multi_sta = true;
330
331 if (!multi_sta ||
332 dm_digtable->cursta_cstate != DIG_STA_DISCONNECT) {
333 initialized = false;
334 dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
335 return;
336 } else if (initialized == false) {
337 initialized = true;
338 dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_0;
339 dm_digtable->cur_igvalue = 0x20;
340 rtl92c_dm_write_dig(hw);
341 }
342
343 if (dm_digtable->curmultista_cstate == DIG_MULTISTA_CONNECT) {
344 if ((rssi_strength < dm_digtable->rssi_lowthresh) &&
345 (dm_digtable->dig_ext_port_stage != DIG_EXT_PORT_STAGE_1)) {
346
347 if (dm_digtable->dig_ext_port_stage ==
348 DIG_EXT_PORT_STAGE_2) {
349 dm_digtable->cur_igvalue = 0x20;
350 rtl92c_dm_write_dig(hw);
351 }
352
353 dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_1;
354 } else if (rssi_strength > dm_digtable->rssi_highthresh) {
355 dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_2;
356 rtl92c_dm_ctrl_initgain_by_fa(hw);
357 }
358 } else if (dm_digtable->dig_ext_port_stage != DIG_EXT_PORT_STAGE_0) {
359 dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_0;
360 dm_digtable->cur_igvalue = 0x20;
361 rtl92c_dm_write_dig(hw);
362 }
363
364 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
365 "curmultista_cstate = %x dig_ext_port_stage %x\n",
366 dm_digtable->curmultista_cstate,
367 dm_digtable->dig_ext_port_stage);
368 }
369
370 static void rtl92c_dm_initial_gain_sta(struct ieee80211_hw *hw)
371 {
372 struct rtl_priv *rtlpriv = rtl_priv(hw);
373 struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
374
375 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
376 "presta_cstate = %x, cursta_cstate = %x\n",
377 dm_digtable->presta_cstate, dm_digtable->cursta_cstate);
378
379 if (dm_digtable->presta_cstate == dm_digtable->cursta_cstate ||
380 dm_digtable->cursta_cstate == DIG_STA_BEFORE_CONNECT ||
381 dm_digtable->cursta_cstate == DIG_STA_CONNECT) {
382
383 if (dm_digtable->cursta_cstate != DIG_STA_DISCONNECT) {
384 dm_digtable->rssi_val_min =
385 rtl92c_dm_initial_gain_min_pwdb(hw);
386 rtl92c_dm_ctrl_initgain_by_rssi(hw);
387 }
388 } else {
389 dm_digtable->rssi_val_min = 0;
390 dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
391 dm_digtable->back_val = DM_DIG_BACKOFF_DEFAULT;
392 dm_digtable->cur_igvalue = 0x20;
393 dm_digtable->pre_igvalue = 0;
394 rtl92c_dm_write_dig(hw);
395 }
396 }
397
398 static void rtl92c_dm_cck_packet_detection_thresh(struct ieee80211_hw *hw)
399 {
400 struct rtl_priv *rtlpriv = rtl_priv(hw);
401 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
402 struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
403
404 if (dm_digtable->cursta_cstate == DIG_STA_CONNECT) {
405 dm_digtable->rssi_val_min = rtl92c_dm_initial_gain_min_pwdb(hw);
406
407 if (dm_digtable->pre_cck_pd_state == CCK_PD_STAGE_LowRssi) {
408 if (dm_digtable->rssi_val_min <= 25)
409 dm_digtable->cur_cck_pd_state =
410 CCK_PD_STAGE_LowRssi;
411 else
412 dm_digtable->cur_cck_pd_state =
413 CCK_PD_STAGE_HighRssi;
414 } else {
415 if (dm_digtable->rssi_val_min <= 20)
416 dm_digtable->cur_cck_pd_state =
417 CCK_PD_STAGE_LowRssi;
418 else
419 dm_digtable->cur_cck_pd_state =
420 CCK_PD_STAGE_HighRssi;
421 }
422 } else {
423 dm_digtable->cur_cck_pd_state = CCK_PD_STAGE_MAX;
424 }
425
426 if (dm_digtable->pre_cck_pd_state != dm_digtable->cur_cck_pd_state) {
427 if (dm_digtable->cur_cck_pd_state == CCK_PD_STAGE_LowRssi) {
428 if (rtlpriv->falsealm_cnt.cnt_cck_fail > 800)
429 dm_digtable->cur_cck_fa_state =
430 CCK_FA_STAGE_High;
431 else
432 dm_digtable->cur_cck_fa_state = CCK_FA_STAGE_Low;
433
434 if (dm_digtable->pre_cck_fa_state !=
435 dm_digtable->cur_cck_fa_state) {
436 if (dm_digtable->cur_cck_fa_state ==
437 CCK_FA_STAGE_Low)
438 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2,
439 0x83);
440 else
441 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2,
442 0xcd);
443
444 dm_digtable->pre_cck_fa_state =
445 dm_digtable->cur_cck_fa_state;
446 }
447
448 rtl_set_bbreg(hw, RCCK0_SYSTEM, MASKBYTE1, 0x40);
449
450 if (IS_92C_SERIAL(rtlhal->version))
451 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT,
452 MASKBYTE2, 0xd7);
453 } else {
454 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd);
455 rtl_set_bbreg(hw, RCCK0_SYSTEM, MASKBYTE1, 0x47);
456
457 if (IS_92C_SERIAL(rtlhal->version))
458 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT,
459 MASKBYTE2, 0xd3);
460 }
461 dm_digtable->pre_cck_pd_state = dm_digtable->cur_cck_pd_state;
462 }
463
464 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE, "CCKPDStage=%x\n",
465 dm_digtable->cur_cck_pd_state);
466
467 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE, "is92C=%x\n",
468 IS_92C_SERIAL(rtlhal->version));
469 }
470
471 static void rtl92c_dm_ctrl_initgain_by_twoport(struct ieee80211_hw *hw)
472 {
473 struct rtl_priv *rtlpriv = rtl_priv(hw);
474 struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
475 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
476
477 if (mac->act_scanning)
478 return;
479
480 if (mac->link_state >= MAC80211_LINKED)
481 dm_digtable->cursta_cstate = DIG_STA_CONNECT;
482 else
483 dm_digtable->cursta_cstate = DIG_STA_DISCONNECT;
484
485 rtl92c_dm_initial_gain_sta(hw);
486 rtl92c_dm_initial_gain_multi_sta(hw);
487 rtl92c_dm_cck_packet_detection_thresh(hw);
488
489 dm_digtable->presta_cstate = dm_digtable->cursta_cstate;
490
491 }
492
493 static void rtl92c_dm_dig(struct ieee80211_hw *hw)
494 {
495 struct rtl_priv *rtlpriv = rtl_priv(hw);
496 struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
497
498 if (rtlpriv->dm.dm_initialgain_enable == false)
499 return;
500 if (dm_digtable->dig_enable_flag == false)
501 return;
502
503 rtl92c_dm_ctrl_initgain_by_twoport(hw);
504
505 }
506
507 static void rtl92c_dm_init_dynamic_txpower(struct ieee80211_hw *hw)
508 {
509 struct rtl_priv *rtlpriv = rtl_priv(hw);
510
511 rtlpriv->dm.dynamic_txpower_enable = false;
512
513 rtlpriv->dm.last_dtp_lvl = TXHIGHPWRLEVEL_NORMAL;
514 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
515 }
516
517 void rtl92c_dm_write_dig(struct ieee80211_hw *hw)
518 {
519 struct rtl_priv *rtlpriv = rtl_priv(hw);
520 struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
521
522 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
523 "cur_igvalue = 0x%x, pre_igvalue = 0x%x, back_val = %d\n",
524 dm_digtable->cur_igvalue, dm_digtable->pre_igvalue,
525 dm_digtable->back_val);
526
527 dm_digtable->cur_igvalue += 2;
528 if (dm_digtable->cur_igvalue > 0x3f)
529 dm_digtable->cur_igvalue = 0x3f;
530
531 if (dm_digtable->pre_igvalue != dm_digtable->cur_igvalue) {
532 rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, 0x7f,
533 dm_digtable->cur_igvalue);
534 rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, 0x7f,
535 dm_digtable->cur_igvalue);
536
537 dm_digtable->pre_igvalue = dm_digtable->cur_igvalue;
538 }
539 }
540 EXPORT_SYMBOL(rtl92c_dm_write_dig);
541
542 static void rtl92c_dm_pwdb_monitor(struct ieee80211_hw *hw)
543 {
544 struct rtl_priv *rtlpriv = rtl_priv(hw);
545 long tmpentry_max_pwdb = 0, tmpentry_min_pwdb = 0xff;
546
547 u8 h2c_parameter[3] = { 0 };
548
549 return;
550
551 if (tmpentry_max_pwdb != 0) {
552 rtlpriv->dm.entry_max_undec_sm_pwdb = tmpentry_max_pwdb;
553 } else {
554 rtlpriv->dm.entry_max_undec_sm_pwdb = 0;
555 }
556
557 if (tmpentry_min_pwdb != 0xff) {
558 rtlpriv->dm.entry_min_undec_sm_pwdb = tmpentry_min_pwdb;
559 } else {
560 rtlpriv->dm.entry_min_undec_sm_pwdb = 0;
561 }
562
563 h2c_parameter[2] = (u8) (rtlpriv->dm.undec_sm_pwdb & 0xFF);
564 h2c_parameter[0] = 0;
565
566 rtl92c_fill_h2c_cmd(hw, H2C_RSSI_REPORT, 3, h2c_parameter);
567 }
568
569 void rtl92c_dm_init_edca_turbo(struct ieee80211_hw *hw)
570 {
571 struct rtl_priv *rtlpriv = rtl_priv(hw);
572 rtlpriv->dm.current_turbo_edca = false;
573 rtlpriv->dm.is_any_nonbepkts = false;
574 rtlpriv->dm.is_cur_rdlstate = false;
575 }
576 EXPORT_SYMBOL(rtl92c_dm_init_edca_turbo);
577
578 static void rtl92c_dm_check_edca_turbo(struct ieee80211_hw *hw)
579 {
580 struct rtl_priv *rtlpriv = rtl_priv(hw);
581 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
582 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
583
584 static u64 last_txok_cnt;
585 static u64 last_rxok_cnt;
586 static u32 last_bt_edca_ul;
587 static u32 last_bt_edca_dl;
588 u64 cur_txok_cnt = 0;
589 u64 cur_rxok_cnt = 0;
590 u32 edca_be_ul = 0x5ea42b;
591 u32 edca_be_dl = 0x5ea42b;
592 bool bt_change_edca = false;
593
594 if ((last_bt_edca_ul != rtlpcipriv->bt_coexist.bt_edca_ul) ||
595 (last_bt_edca_dl != rtlpcipriv->bt_coexist.bt_edca_dl)) {
596 rtlpriv->dm.current_turbo_edca = false;
597 last_bt_edca_ul = rtlpcipriv->bt_coexist.bt_edca_ul;
598 last_bt_edca_dl = rtlpcipriv->bt_coexist.bt_edca_dl;
599 }
600
601 if (rtlpcipriv->bt_coexist.bt_edca_ul != 0) {
602 edca_be_ul = rtlpcipriv->bt_coexist.bt_edca_ul;
603 bt_change_edca = true;
604 }
605
606 if (rtlpcipriv->bt_coexist.bt_edca_dl != 0) {
607 edca_be_ul = rtlpcipriv->bt_coexist.bt_edca_dl;
608 bt_change_edca = true;
609 }
610
611 if (mac->link_state != MAC80211_LINKED) {
612 rtlpriv->dm.current_turbo_edca = false;
613 return;
614 }
615
616 if ((!mac->ht_enable) && (!rtlpcipriv->bt_coexist.bt_coexistence)) {
617 if (!(edca_be_ul & 0xffff0000))
618 edca_be_ul |= 0x005e0000;
619
620 if (!(edca_be_dl & 0xffff0000))
621 edca_be_dl |= 0x005e0000;
622 }
623
624 if ((bt_change_edca) || ((!rtlpriv->dm.is_any_nonbepkts) &&
625 (!rtlpriv->dm.disable_framebursting))) {
626
627 cur_txok_cnt = rtlpriv->stats.txbytesunicast - last_txok_cnt;
628 cur_rxok_cnt = rtlpriv->stats.rxbytesunicast - last_rxok_cnt;
629
630 if (cur_rxok_cnt > 4 * cur_txok_cnt) {
631 if (!rtlpriv->dm.is_cur_rdlstate ||
632 !rtlpriv->dm.current_turbo_edca) {
633 rtl_write_dword(rtlpriv,
634 REG_EDCA_BE_PARAM,
635 edca_be_dl);
636 rtlpriv->dm.is_cur_rdlstate = true;
637 }
638 } else {
639 if (rtlpriv->dm.is_cur_rdlstate ||
640 !rtlpriv->dm.current_turbo_edca) {
641 rtl_write_dword(rtlpriv,
642 REG_EDCA_BE_PARAM,
643 edca_be_ul);
644 rtlpriv->dm.is_cur_rdlstate = false;
645 }
646 }
647 rtlpriv->dm.current_turbo_edca = true;
648 } else {
649 if (rtlpriv->dm.current_turbo_edca) {
650 u8 tmp = AC0_BE;
651 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM,
652 &tmp);
653 rtlpriv->dm.current_turbo_edca = false;
654 }
655 }
656
657 rtlpriv->dm.is_any_nonbepkts = false;
658 last_txok_cnt = rtlpriv->stats.txbytesunicast;
659 last_rxok_cnt = rtlpriv->stats.rxbytesunicast;
660 }
661
662 static void rtl92c_dm_txpower_tracking_callback_thermalmeter(struct ieee80211_hw
663 *hw)
664 {
665 struct rtl_priv *rtlpriv = rtl_priv(hw);
666 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
667 struct rtl_phy *rtlphy = &(rtlpriv->phy);
668 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
669 u8 thermalvalue, delta, delta_lck, delta_iqk;
670 long ele_a, ele_d, temp_cck, val_x, value32;
671 long val_y, ele_c = 0;
672 u8 ofdm_index[2], ofdm_index_old[2], cck_index_old = 0;
673 s8 cck_index = 0;
674 int i;
675 bool is2t = IS_92C_SERIAL(rtlhal->version);
676 s8 txpwr_level[2] = {0, 0};
677 u8 ofdm_min_index = 6, rf;
678
679 rtlpriv->dm.txpower_trackinginit = true;
680 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
681 "rtl92c_dm_txpower_tracking_callback_thermalmeter\n");
682
683 thermalvalue = (u8) rtl_get_rfreg(hw, RF90_PATH_A, RF_T_METER, 0x1f);
684
685 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
686 "Readback Thermal Meter = 0x%x pre thermal meter 0x%x eeprom_thermalmeter 0x%x\n",
687 thermalvalue, rtlpriv->dm.thermalvalue,
688 rtlefuse->eeprom_thermalmeter);
689
690 rtl92c_phy_ap_calibrate(hw, (thermalvalue -
691 rtlefuse->eeprom_thermalmeter));
692 if (is2t)
693 rf = 2;
694 else
695 rf = 1;
696
697 if (thermalvalue) {
698 ele_d = rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
699 MASKDWORD) & MASKOFDM_D;
700
701 for (i = 0; i < OFDM_TABLE_LENGTH; i++) {
702 if (ele_d == (ofdmswing_table[i] & MASKOFDM_D)) {
703 ofdm_index_old[0] = (u8) i;
704
705 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
706 "Initial pathA ele_d reg0x%x = 0x%lx, ofdm_index=0x%x\n",
707 ROFDM0_XATXIQIMBALANCE,
708 ele_d, ofdm_index_old[0]);
709 break;
710 }
711 }
712
713 if (is2t) {
714 ele_d = rtl_get_bbreg(hw, ROFDM0_XBTXIQIMBALANCE,
715 MASKDWORD) & MASKOFDM_D;
716
717 for (i = 0; i < OFDM_TABLE_LENGTH; i++) {
718 if (ele_d == (ofdmswing_table[i] &
719 MASKOFDM_D)) {
720
721 RT_TRACE(rtlpriv, COMP_POWER_TRACKING,
722 DBG_LOUD,
723 "Initial pathB ele_d reg0x%x = 0x%lx, ofdm_index=0x%x\n",
724 ROFDM0_XBTXIQIMBALANCE, ele_d,
725 ofdm_index_old[1]);
726 break;
727 }
728 }
729 }
730
731 temp_cck =
732 rtl_get_bbreg(hw, RCCK0_TXFILTER2, MASKDWORD) & MASKCCK;
733
734 for (i = 0; i < CCK_TABLE_LENGTH; i++) {
735 if (rtlpriv->dm.cck_inch14) {
736 if (memcmp((void *)&temp_cck,
737 (void *)&cckswing_table_ch14[i][2],
738 4) == 0) {
739 cck_index_old = (u8) i;
740
741 RT_TRACE(rtlpriv, COMP_POWER_TRACKING,
742 DBG_LOUD,
743 "Initial reg0x%x = 0x%lx, cck_index=0x%x, ch 14 %d\n",
744 RCCK0_TXFILTER2, temp_cck,
745 cck_index_old,
746 rtlpriv->dm.cck_inch14);
747 break;
748 }
749 } else {
750 if (memcmp((void *)&temp_cck,
751 (void *)
752 &cckswing_table_ch1ch13[i][2],
753 4) == 0) {
754 cck_index_old = (u8) i;
755
756 RT_TRACE(rtlpriv, COMP_POWER_TRACKING,
757 DBG_LOUD,
758 "Initial reg0x%x = 0x%lx, cck_index=0x%x, ch14 %d\n",
759 RCCK0_TXFILTER2, temp_cck,
760 cck_index_old,
761 rtlpriv->dm.cck_inch14);
762 break;
763 }
764 }
765 }
766
767 if (!rtlpriv->dm.thermalvalue) {
768 rtlpriv->dm.thermalvalue =
769 rtlefuse->eeprom_thermalmeter;
770 rtlpriv->dm.thermalvalue_lck = thermalvalue;
771 rtlpriv->dm.thermalvalue_iqk = thermalvalue;
772 for (i = 0; i < rf; i++)
773 rtlpriv->dm.ofdm_index[i] = ofdm_index_old[i];
774 rtlpriv->dm.cck_index = cck_index_old;
775 }
776
777 delta = (thermalvalue > rtlpriv->dm.thermalvalue) ?
778 (thermalvalue - rtlpriv->dm.thermalvalue) :
779 (rtlpriv->dm.thermalvalue - thermalvalue);
780
781 delta_lck = (thermalvalue > rtlpriv->dm.thermalvalue_lck) ?
782 (thermalvalue - rtlpriv->dm.thermalvalue_lck) :
783 (rtlpriv->dm.thermalvalue_lck - thermalvalue);
784
785 delta_iqk = (thermalvalue > rtlpriv->dm.thermalvalue_iqk) ?
786 (thermalvalue - rtlpriv->dm.thermalvalue_iqk) :
787 (rtlpriv->dm.thermalvalue_iqk - thermalvalue);
788
789 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
790 "Readback Thermal Meter = 0x%x pre thermal meter 0x%x eeprom_thermalmeter 0x%x delta 0x%x delta_lck 0x%x delta_iqk 0x%x\n",
791 thermalvalue, rtlpriv->dm.thermalvalue,
792 rtlefuse->eeprom_thermalmeter, delta, delta_lck,
793 delta_iqk);
794
795 if (delta_lck > 1) {
796 rtlpriv->dm.thermalvalue_lck = thermalvalue;
797 rtl92c_phy_lc_calibrate(hw);
798 }
799
800 if (delta > 0 && rtlpriv->dm.txpower_track_control) {
801 if (thermalvalue > rtlpriv->dm.thermalvalue) {
802 for (i = 0; i < rf; i++)
803 rtlpriv->dm.ofdm_index[i] -= delta;
804 rtlpriv->dm.cck_index -= delta;
805 } else {
806 for (i = 0; i < rf; i++)
807 rtlpriv->dm.ofdm_index[i] += delta;
808 rtlpriv->dm.cck_index += delta;
809 }
810
811 if (is2t) {
812 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
813 "temp OFDM_A_index=0x%x, OFDM_B_index=0x%x, cck_index=0x%x\n",
814 rtlpriv->dm.ofdm_index[0],
815 rtlpriv->dm.ofdm_index[1],
816 rtlpriv->dm.cck_index);
817 } else {
818 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
819 "temp OFDM_A_index=0x%x, cck_index=0x%x\n",
820 rtlpriv->dm.ofdm_index[0],
821 rtlpriv->dm.cck_index);
822 }
823
824 if (thermalvalue > rtlefuse->eeprom_thermalmeter) {
825 for (i = 0; i < rf; i++)
826 ofdm_index[i] =
827 rtlpriv->dm.ofdm_index[i]
828 + 1;
829 cck_index = rtlpriv->dm.cck_index + 1;
830 } else {
831 for (i = 0; i < rf; i++)
832 ofdm_index[i] =
833 rtlpriv->dm.ofdm_index[i];
834 cck_index = rtlpriv->dm.cck_index;
835 }
836
837 for (i = 0; i < rf; i++) {
838 if (txpwr_level[i] >= 0 &&
839 txpwr_level[i] <= 26) {
840 if (thermalvalue >
841 rtlefuse->eeprom_thermalmeter) {
842 if (delta < 5)
843 ofdm_index[i] -= 1;
844
845 else
846 ofdm_index[i] -= 2;
847 } else if (delta > 5 && thermalvalue <
848 rtlefuse->
849 eeprom_thermalmeter) {
850 ofdm_index[i] += 1;
851 }
852 } else if (txpwr_level[i] >= 27 &&
853 txpwr_level[i] <= 32
854 && thermalvalue >
855 rtlefuse->eeprom_thermalmeter) {
856 if (delta < 5)
857 ofdm_index[i] -= 1;
858
859 else
860 ofdm_index[i] -= 2;
861 } else if (txpwr_level[i] >= 32 &&
862 txpwr_level[i] <= 38 &&
863 thermalvalue >
864 rtlefuse->eeprom_thermalmeter
865 && delta > 5) {
866 ofdm_index[i] -= 1;
867 }
868 }
869
870 if (txpwr_level[i] >= 0 && txpwr_level[i] <= 26) {
871 if (thermalvalue >
872 rtlefuse->eeprom_thermalmeter) {
873 if (delta < 5)
874 cck_index -= 1;
875
876 else
877 cck_index -= 2;
878 } else if (delta > 5 && thermalvalue <
879 rtlefuse->eeprom_thermalmeter) {
880 cck_index += 1;
881 }
882 } else if (txpwr_level[i] >= 27 &&
883 txpwr_level[i] <= 32 &&
884 thermalvalue >
885 rtlefuse->eeprom_thermalmeter) {
886 if (delta < 5)
887 cck_index -= 1;
888
889 else
890 cck_index -= 2;
891 } else if (txpwr_level[i] >= 32 &&
892 txpwr_level[i] <= 38 &&
893 thermalvalue > rtlefuse->eeprom_thermalmeter
894 && delta > 5) {
895 cck_index -= 1;
896 }
897
898 for (i = 0; i < rf; i++) {
899 if (ofdm_index[i] > OFDM_TABLE_SIZE - 1)
900 ofdm_index[i] = OFDM_TABLE_SIZE - 1;
901
902 else if (ofdm_index[i] < ofdm_min_index)
903 ofdm_index[i] = ofdm_min_index;
904 }
905
906 if (cck_index > CCK_TABLE_SIZE - 1)
907 cck_index = CCK_TABLE_SIZE - 1;
908 else if (cck_index < 0)
909 cck_index = 0;
910
911 if (is2t) {
912 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
913 "new OFDM_A_index=0x%x, OFDM_B_index=0x%x, cck_index=0x%x\n",
914 ofdm_index[0], ofdm_index[1],
915 cck_index);
916 } else {
917 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
918 "new OFDM_A_index=0x%x, cck_index=0x%x\n",
919 ofdm_index[0], cck_index);
920 }
921 }
922
923 if (rtlpriv->dm.txpower_track_control && delta != 0) {
924 ele_d =
925 (ofdmswing_table[ofdm_index[0]] & 0xFFC00000) >> 22;
926 val_x = rtlphy->reg_e94;
927 val_y = rtlphy->reg_e9c;
928
929 if (val_x != 0) {
930 if ((val_x & 0x00000200) != 0)
931 val_x = val_x | 0xFFFFFC00;
932 ele_a = ((val_x * ele_d) >> 8) & 0x000003FF;
933
934 if ((val_y & 0x00000200) != 0)
935 val_y = val_y | 0xFFFFFC00;
936 ele_c = ((val_y * ele_d) >> 8) & 0x000003FF;
937
938 value32 = (ele_d << 22) |
939 ((ele_c & 0x3F) << 16) | ele_a;
940
941 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
942 MASKDWORD, value32);
943
944 value32 = (ele_c & 0x000003C0) >> 6;
945 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, MASKH4BITS,
946 value32);
947
948 value32 = ((val_x * ele_d) >> 7) & 0x01;
949 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
950 BIT(31), value32);
951
952 value32 = ((val_y * ele_d) >> 7) & 0x01;
953 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
954 BIT(29), value32);
955 } else {
956 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
957 MASKDWORD,
958 ofdmswing_table[ofdm_index[0]]);
959
960 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, MASKH4BITS,
961 0x00);
962 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
963 BIT(31) | BIT(29), 0x00);
964 }
965
966 if (!rtlpriv->dm.cck_inch14) {
967 rtl_write_byte(rtlpriv, 0xa22,
968 cckswing_table_ch1ch13[cck_index]
969 [0]);
970 rtl_write_byte(rtlpriv, 0xa23,
971 cckswing_table_ch1ch13[cck_index]
972 [1]);
973 rtl_write_byte(rtlpriv, 0xa24,
974 cckswing_table_ch1ch13[cck_index]
975 [2]);
976 rtl_write_byte(rtlpriv, 0xa25,
977 cckswing_table_ch1ch13[cck_index]
978 [3]);
979 rtl_write_byte(rtlpriv, 0xa26,
980 cckswing_table_ch1ch13[cck_index]
981 [4]);
982 rtl_write_byte(rtlpriv, 0xa27,
983 cckswing_table_ch1ch13[cck_index]
984 [5]);
985 rtl_write_byte(rtlpriv, 0xa28,
986 cckswing_table_ch1ch13[cck_index]
987 [6]);
988 rtl_write_byte(rtlpriv, 0xa29,
989 cckswing_table_ch1ch13[cck_index]
990 [7]);
991 } else {
992 rtl_write_byte(rtlpriv, 0xa22,
993 cckswing_table_ch14[cck_index]
994 [0]);
995 rtl_write_byte(rtlpriv, 0xa23,
996 cckswing_table_ch14[cck_index]
997 [1]);
998 rtl_write_byte(rtlpriv, 0xa24,
999 cckswing_table_ch14[cck_index]
1000 [2]);
1001 rtl_write_byte(rtlpriv, 0xa25,
1002 cckswing_table_ch14[cck_index]
1003 [3]);
1004 rtl_write_byte(rtlpriv, 0xa26,
1005 cckswing_table_ch14[cck_index]
1006 [4]);
1007 rtl_write_byte(rtlpriv, 0xa27,
1008 cckswing_table_ch14[cck_index]
1009 [5]);
1010 rtl_write_byte(rtlpriv, 0xa28,
1011 cckswing_table_ch14[cck_index]
1012 [6]);
1013 rtl_write_byte(rtlpriv, 0xa29,
1014 cckswing_table_ch14[cck_index]
1015 [7]);
1016 }
1017
1018 if (is2t) {
1019 ele_d = (ofdmswing_table[ofdm_index[1]] &
1020 0xFFC00000) >> 22;
1021
1022 val_x = rtlphy->reg_eb4;
1023 val_y = rtlphy->reg_ebc;
1024
1025 if (val_x != 0) {
1026 if ((val_x & 0x00000200) != 0)
1027 val_x = val_x | 0xFFFFFC00;
1028 ele_a = ((val_x * ele_d) >> 8) &
1029 0x000003FF;
1030
1031 if ((val_y & 0x00000200) != 0)
1032 val_y = val_y | 0xFFFFFC00;
1033 ele_c = ((val_y * ele_d) >> 8) &
1034 0x00003FF;
1035
1036 value32 = (ele_d << 22) |
1037 ((ele_c & 0x3F) << 16) | ele_a;
1038 rtl_set_bbreg(hw,
1039 ROFDM0_XBTXIQIMBALANCE,
1040 MASKDWORD, value32);
1041
1042 value32 = (ele_c & 0x000003C0) >> 6;
1043 rtl_set_bbreg(hw, ROFDM0_XDTXAFE,
1044 MASKH4BITS, value32);
1045
1046 value32 = ((val_x * ele_d) >> 7) & 0x01;
1047 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
1048 BIT(27), value32);
1049
1050 value32 = ((val_y * ele_d) >> 7) & 0x01;
1051 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
1052 BIT(25), value32);
1053 } else {
1054 rtl_set_bbreg(hw,
1055 ROFDM0_XBTXIQIMBALANCE,
1056 MASKDWORD,
1057 ofdmswing_table[ofdm_index
1058 [1]]);
1059 rtl_set_bbreg(hw, ROFDM0_XDTXAFE,
1060 MASKH4BITS, 0x00);
1061 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
1062 BIT(27) | BIT(25), 0x00);
1063 }
1064
1065 }
1066 }
1067
1068 if (delta_iqk > 3) {
1069 rtlpriv->dm.thermalvalue_iqk = thermalvalue;
1070 rtl92c_phy_iq_calibrate(hw, false);
1071 }
1072
1073 if (rtlpriv->dm.txpower_track_control)
1074 rtlpriv->dm.thermalvalue = thermalvalue;
1075 }
1076
1077 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, "<===\n");
1078
1079 }
1080
1081 static void rtl92c_dm_initialize_txpower_tracking_thermalmeter(
1082 struct ieee80211_hw *hw)
1083 {
1084 struct rtl_priv *rtlpriv = rtl_priv(hw);
1085
1086 rtlpriv->dm.txpower_tracking = true;
1087 rtlpriv->dm.txpower_trackinginit = false;
1088
1089 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1090 "pMgntInfo->txpower_tracking = %d\n",
1091 rtlpriv->dm.txpower_tracking);
1092 }
1093
1094 static void rtl92c_dm_initialize_txpower_tracking(struct ieee80211_hw *hw)
1095 {
1096 rtl92c_dm_initialize_txpower_tracking_thermalmeter(hw);
1097 }
1098
1099 static void rtl92c_dm_txpower_tracking_directcall(struct ieee80211_hw *hw)
1100 {
1101 rtl92c_dm_txpower_tracking_callback_thermalmeter(hw);
1102 }
1103
1104 static void rtl92c_dm_check_txpower_tracking_thermal_meter(
1105 struct ieee80211_hw *hw)
1106 {
1107 struct rtl_priv *rtlpriv = rtl_priv(hw);
1108 static u8 tm_trigger;
1109
1110 if (!rtlpriv->dm.txpower_tracking)
1111 return;
1112
1113 if (!tm_trigger) {
1114 rtl_set_rfreg(hw, RF90_PATH_A, RF_T_METER, RFREG_OFFSET_MASK,
1115 0x60);
1116 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1117 "Trigger 92S Thermal Meter!!\n");
1118 tm_trigger = 1;
1119 return;
1120 } else {
1121 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1122 "Schedule TxPowerTracking direct call!!\n");
1123 rtl92c_dm_txpower_tracking_directcall(hw);
1124 tm_trigger = 0;
1125 }
1126 }
1127
1128 void rtl92c_dm_check_txpower_tracking(struct ieee80211_hw *hw)
1129 {
1130 rtl92c_dm_check_txpower_tracking_thermal_meter(hw);
1131 }
1132 EXPORT_SYMBOL(rtl92c_dm_check_txpower_tracking);
1133
1134 void rtl92c_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw)
1135 {
1136 struct rtl_priv *rtlpriv = rtl_priv(hw);
1137 struct rate_adaptive *p_ra = &(rtlpriv->ra);
1138
1139 p_ra->ratr_state = DM_RATR_STA_INIT;
1140 p_ra->pre_ratr_state = DM_RATR_STA_INIT;
1141
1142 if (rtlpriv->dm.dm_type == DM_TYPE_BYDRIVER)
1143 rtlpriv->dm.useramask = true;
1144 else
1145 rtlpriv->dm.useramask = false;
1146
1147 }
1148 EXPORT_SYMBOL(rtl92c_dm_init_rate_adaptive_mask);
1149
1150 static void rtl92c_dm_init_dynamic_bb_powersaving(struct ieee80211_hw *hw)
1151 {
1152 struct rtl_priv *rtlpriv = rtl_priv(hw);
1153 struct ps_t *dm_pstable = &rtlpriv->dm_pstable;
1154
1155 dm_pstable->pre_ccastate = CCA_MAX;
1156 dm_pstable->cur_ccasate = CCA_MAX;
1157 dm_pstable->pre_rfstate = RF_MAX;
1158 dm_pstable->cur_rfstate = RF_MAX;
1159 dm_pstable->rssi_val_min = 0;
1160 }
1161
1162 void rtl92c_dm_rf_saving(struct ieee80211_hw *hw, u8 bforce_in_normal)
1163 {
1164 struct rtl_priv *rtlpriv = rtl_priv(hw);
1165 struct ps_t *dm_pstable = &rtlpriv->dm_pstable;
1166 static u8 initialize;
1167 static u32 reg_874, reg_c70, reg_85c, reg_a74;
1168
1169 if (initialize == 0) {
1170 reg_874 = (rtl_get_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
1171 MASKDWORD) & 0x1CC000) >> 14;
1172
1173 reg_c70 = (rtl_get_bbreg(hw, ROFDM0_AGCPARAMETER1,
1174 MASKDWORD) & BIT(3)) >> 3;
1175
1176 reg_85c = (rtl_get_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL,
1177 MASKDWORD) & 0xFF000000) >> 24;
1178
1179 reg_a74 = (rtl_get_bbreg(hw, 0xa74, MASKDWORD) & 0xF000) >> 12;
1180
1181 initialize = 1;
1182 }
1183
1184 if (!bforce_in_normal) {
1185 if (dm_pstable->rssi_val_min != 0) {
1186 if (dm_pstable->pre_rfstate == RF_NORMAL) {
1187 if (dm_pstable->rssi_val_min >= 30)
1188 dm_pstable->cur_rfstate = RF_SAVE;
1189 else
1190 dm_pstable->cur_rfstate = RF_NORMAL;
1191 } else {
1192 if (dm_pstable->rssi_val_min <= 25)
1193 dm_pstable->cur_rfstate = RF_NORMAL;
1194 else
1195 dm_pstable->cur_rfstate = RF_SAVE;
1196 }
1197 } else {
1198 dm_pstable->cur_rfstate = RF_MAX;
1199 }
1200 } else {
1201 dm_pstable->cur_rfstate = RF_NORMAL;
1202 }
1203
1204 if (dm_pstable->pre_rfstate != dm_pstable->cur_rfstate) {
1205 if (dm_pstable->cur_rfstate == RF_SAVE) {
1206 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
1207 0x1C0000, 0x2);
1208 rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, BIT(3), 0);
1209 rtl_set_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL,
1210 0xFF000000, 0x63);
1211 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
1212 0xC000, 0x2);
1213 rtl_set_bbreg(hw, 0xa74, 0xF000, 0x3);
1214 rtl_set_bbreg(hw, 0x818, BIT(28), 0x0);
1215 rtl_set_bbreg(hw, 0x818, BIT(28), 0x1);
1216 } else {
1217 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
1218 0x1CC000, reg_874);
1219 rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, BIT(3),
1220 reg_c70);
1221 rtl_set_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL, 0xFF000000,
1222 reg_85c);
1223 rtl_set_bbreg(hw, 0xa74, 0xF000, reg_a74);
1224 rtl_set_bbreg(hw, 0x818, BIT(28), 0x0);
1225 }
1226
1227 dm_pstable->pre_rfstate = dm_pstable->cur_rfstate;
1228 }
1229 }
1230 EXPORT_SYMBOL(rtl92c_dm_rf_saving);
1231
1232 static void rtl92c_dm_dynamic_bb_powersaving(struct ieee80211_hw *hw)
1233 {
1234 struct rtl_priv *rtlpriv = rtl_priv(hw);
1235 struct ps_t *dm_pstable = &rtlpriv->dm_pstable;
1236 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1237 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1238
1239 if (((mac->link_state == MAC80211_NOLINK)) &&
1240 (rtlpriv->dm.entry_min_undec_sm_pwdb == 0)) {
1241 dm_pstable->rssi_val_min = 0;
1242 RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD, "Not connected to any\n");
1243 }
1244
1245 if (mac->link_state == MAC80211_LINKED) {
1246 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
1247 dm_pstable->rssi_val_min =
1248 rtlpriv->dm.entry_min_undec_sm_pwdb;
1249 RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
1250 "AP Client PWDB = 0x%lx\n",
1251 dm_pstable->rssi_val_min);
1252 } else {
1253 dm_pstable->rssi_val_min = rtlpriv->dm.undec_sm_pwdb;
1254 RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
1255 "STA Default Port PWDB = 0x%lx\n",
1256 dm_pstable->rssi_val_min);
1257 }
1258 } else {
1259 dm_pstable->rssi_val_min =
1260 rtlpriv->dm.entry_min_undec_sm_pwdb;
1261
1262 RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
1263 "AP Ext Port PWDB = 0x%lx\n",
1264 dm_pstable->rssi_val_min);
1265 }
1266
1267 if (IS_92C_SERIAL(rtlhal->version))
1268 ;/* rtl92c_dm_1r_cca(hw); */
1269 else
1270 rtl92c_dm_rf_saving(hw, false);
1271 }
1272
1273 void rtl92c_dm_init(struct ieee80211_hw *hw)
1274 {
1275 struct rtl_priv *rtlpriv = rtl_priv(hw);
1276
1277 rtlpriv->dm.dm_type = DM_TYPE_BYDRIVER;
1278 rtl92c_dm_diginit(hw);
1279 rtl92c_dm_init_dynamic_txpower(hw);
1280 rtl92c_dm_init_edca_turbo(hw);
1281 rtl92c_dm_init_rate_adaptive_mask(hw);
1282 rtl92c_dm_initialize_txpower_tracking(hw);
1283 rtl92c_dm_init_dynamic_bb_powersaving(hw);
1284 }
1285 EXPORT_SYMBOL(rtl92c_dm_init);
1286
1287 void rtl92c_dm_dynamic_txpower(struct ieee80211_hw *hw)
1288 {
1289 struct rtl_priv *rtlpriv = rtl_priv(hw);
1290 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1291 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1292 long undec_sm_pwdb;
1293
1294 if (!rtlpriv->dm.dynamic_txpower_enable)
1295 return;
1296
1297 if (rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) {
1298 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
1299 return;
1300 }
1301
1302 if ((mac->link_state < MAC80211_LINKED) &&
1303 (rtlpriv->dm.entry_min_undec_sm_pwdb == 0)) {
1304 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
1305 "Not connected to any\n");
1306
1307 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
1308
1309 rtlpriv->dm.last_dtp_lvl = TXHIGHPWRLEVEL_NORMAL;
1310 return;
1311 }
1312
1313 if (mac->link_state >= MAC80211_LINKED) {
1314 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
1315 undec_sm_pwdb = rtlpriv->dm.entry_min_undec_sm_pwdb;
1316 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
1317 "AP Client PWDB = 0x%lx\n",
1318 undec_sm_pwdb);
1319 } else {
1320 undec_sm_pwdb = rtlpriv->dm.undec_sm_pwdb;
1321 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
1322 "STA Default Port PWDB = 0x%lx\n",
1323 undec_sm_pwdb);
1324 }
1325 } else {
1326 undec_sm_pwdb = rtlpriv->dm.entry_min_undec_sm_pwdb;
1327
1328 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
1329 "AP Ext Port PWDB = 0x%lx\n",
1330 undec_sm_pwdb);
1331 }
1332
1333 if (undec_sm_pwdb >= TX_POWER_NEAR_FIELD_THRESH_LVL2) {
1334 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_LEVEL1;
1335 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
1336 "TXHIGHPWRLEVEL_LEVEL1 (TxPwr=0x0)\n");
1337 } else if ((undec_sm_pwdb < (TX_POWER_NEAR_FIELD_THRESH_LVL2 - 3)) &&
1338 (undec_sm_pwdb >= TX_POWER_NEAR_FIELD_THRESH_LVL1)) {
1339
1340 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_LEVEL1;
1341 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
1342 "TXHIGHPWRLEVEL_LEVEL1 (TxPwr=0x10)\n");
1343 } else if (undec_sm_pwdb < (TX_POWER_NEAR_FIELD_THRESH_LVL1 - 5)) {
1344 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
1345 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
1346 "TXHIGHPWRLEVEL_NORMAL\n");
1347 }
1348
1349 if ((rtlpriv->dm.dynamic_txhighpower_lvl != rtlpriv->dm.last_dtp_lvl)) {
1350 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
1351 "PHY_SetTxPowerLevel8192S() Channel = %d\n",
1352 rtlphy->current_channel);
1353 rtl92c_phy_set_txpower_level(hw, rtlphy->current_channel);
1354 }
1355
1356 rtlpriv->dm.last_dtp_lvl = rtlpriv->dm.dynamic_txhighpower_lvl;
1357 }
1358
1359 void rtl92c_dm_watchdog(struct ieee80211_hw *hw)
1360 {
1361 struct rtl_priv *rtlpriv = rtl_priv(hw);
1362 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1363 bool fw_current_inpsmode = false;
1364 bool fw_ps_awake = true;
1365
1366 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
1367 (u8 *) (&fw_current_inpsmode));
1368 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FWLPS_RF_ON,
1369 (u8 *) (&fw_ps_awake));
1370
1371 if (ppsc->p2p_ps_info.p2p_ps_mode)
1372 fw_ps_awake = false;
1373
1374 if ((ppsc->rfpwr_state == ERFON) && ((!fw_current_inpsmode) &&
1375 fw_ps_awake)
1376 && (!ppsc->rfchange_inprogress)) {
1377 rtl92c_dm_pwdb_monitor(hw);
1378 rtl92c_dm_dig(hw);
1379 rtl92c_dm_false_alarm_counter_statistics(hw);
1380 rtl92c_dm_dynamic_bb_powersaving(hw);
1381 rtl92c_dm_dynamic_txpower(hw);
1382 rtl92c_dm_check_txpower_tracking(hw);
1383 /* rtl92c_dm_refresh_rate_adaptive_mask(hw); */
1384 rtl92c_dm_bt_coexist(hw);
1385 rtl92c_dm_check_edca_turbo(hw);
1386 }
1387 }
1388 EXPORT_SYMBOL(rtl92c_dm_watchdog);
1389
1390 u8 rtl92c_bt_rssi_state_change(struct ieee80211_hw *hw)
1391 {
1392 struct rtl_priv *rtlpriv = rtl_priv(hw);
1393 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1394 long undec_sm_pwdb;
1395 u8 curr_bt_rssi_state = 0x00;
1396
1397 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1398 undec_sm_pwdb = GET_UNDECORATED_AVERAGE_RSSI(rtlpriv);
1399 } else {
1400 if (rtlpriv->dm.entry_min_undec_sm_pwdb == 0)
1401 undec_sm_pwdb = 100;
1402 else
1403 undec_sm_pwdb = rtlpriv->dm.entry_min_undec_sm_pwdb;
1404 }
1405
1406 /* Check RSSI to determine HighPower/NormalPower state for
1407 * BT coexistence. */
1408 if (undec_sm_pwdb >= 67)
1409 curr_bt_rssi_state &= (~BT_RSSI_STATE_NORMAL_POWER);
1410 else if (undec_sm_pwdb < 62)
1411 curr_bt_rssi_state |= BT_RSSI_STATE_NORMAL_POWER;
1412
1413 /* Check RSSI to determine AMPDU setting for BT coexistence. */
1414 if (undec_sm_pwdb >= 40)
1415 curr_bt_rssi_state &= (~BT_RSSI_STATE_AMDPU_OFF);
1416 else if (undec_sm_pwdb <= 32)
1417 curr_bt_rssi_state |= BT_RSSI_STATE_AMDPU_OFF;
1418
1419 /* Marked RSSI state. It will be used to determine BT coexistence
1420 * setting later. */
1421 if (undec_sm_pwdb < 35)
1422 curr_bt_rssi_state |= BT_RSSI_STATE_SPECIAL_LOW;
1423 else
1424 curr_bt_rssi_state &= (~BT_RSSI_STATE_SPECIAL_LOW);
1425
1426 /* Set Tx Power according to BT status. */
1427 if (undec_sm_pwdb >= 30)
1428 curr_bt_rssi_state |= BT_RSSI_STATE_TXPOWER_LOW;
1429 else if (undec_sm_pwdb < 25)
1430 curr_bt_rssi_state &= (~BT_RSSI_STATE_TXPOWER_LOW);
1431
1432 /* Check BT state related to BT_Idle in B/G mode. */
1433 if (undec_sm_pwdb < 15)
1434 curr_bt_rssi_state |= BT_RSSI_STATE_BG_EDCA_LOW;
1435 else
1436 curr_bt_rssi_state &= (~BT_RSSI_STATE_BG_EDCA_LOW);
1437
1438 if (curr_bt_rssi_state != rtlpcipriv->bt_coexist.bt_rssi_state) {
1439 rtlpcipriv->bt_coexist.bt_rssi_state = curr_bt_rssi_state;
1440 return true;
1441 } else {
1442 return false;
1443 }
1444 }
1445 EXPORT_SYMBOL(rtl92c_bt_rssi_state_change);
1446
1447 static bool rtl92c_bt_state_change(struct ieee80211_hw *hw)
1448 {
1449 struct rtl_priv *rtlpriv = rtl_priv(hw);
1450 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1451
1452 u32 polling, ratio_tx, ratio_pri;
1453 u32 bt_tx, bt_pri;
1454 u8 bt_state;
1455 u8 cur_service_type;
1456
1457 if (rtlpriv->mac80211.link_state < MAC80211_LINKED)
1458 return false;
1459
1460 bt_state = rtl_read_byte(rtlpriv, 0x4fd);
1461 bt_tx = rtl_read_dword(rtlpriv, 0x488);
1462 bt_tx = bt_tx & 0x00ffffff;
1463 bt_pri = rtl_read_dword(rtlpriv, 0x48c);
1464 bt_pri = bt_pri & 0x00ffffff;
1465 polling = rtl_read_dword(rtlpriv, 0x490);
1466
1467 if (bt_tx == 0xffffffff && bt_pri == 0xffffffff &&
1468 polling == 0xffffffff && bt_state == 0xff)
1469 return false;
1470
1471 bt_state &= BIT_OFFSET_LEN_MASK_32(0, 1);
1472 if (bt_state != rtlpcipriv->bt_coexist.bt_cur_state) {
1473 rtlpcipriv->bt_coexist.bt_cur_state = bt_state;
1474
1475 if (rtlpcipriv->bt_coexist.reg_bt_sco == 3) {
1476 rtlpcipriv->bt_coexist.bt_service = BT_IDLE;
1477
1478 bt_state = bt_state |
1479 ((rtlpcipriv->bt_coexist.bt_ant_isolation == 1) ?
1480 0 : BIT_OFFSET_LEN_MASK_32(1, 1)) |
1481 BIT_OFFSET_LEN_MASK_32(2, 1);
1482 rtl_write_byte(rtlpriv, 0x4fd, bt_state);
1483 }
1484 return true;
1485 }
1486
1487 ratio_tx = bt_tx * 1000 / polling;
1488 ratio_pri = bt_pri * 1000 / polling;
1489 rtlpcipriv->bt_coexist.ratio_tx = ratio_tx;
1490 rtlpcipriv->bt_coexist.ratio_pri = ratio_pri;
1491
1492 if (bt_state && rtlpcipriv->bt_coexist.reg_bt_sco == 3) {
1493
1494 if ((ratio_tx < 30) && (ratio_pri < 30))
1495 cur_service_type = BT_IDLE;
1496 else if ((ratio_pri > 110) && (ratio_pri < 250))
1497 cur_service_type = BT_SCO;
1498 else if ((ratio_tx >= 200) && (ratio_pri >= 200))
1499 cur_service_type = BT_BUSY;
1500 else if ((ratio_tx >= 350) && (ratio_tx < 500))
1501 cur_service_type = BT_OTHERBUSY;
1502 else if (ratio_tx >= 500)
1503 cur_service_type = BT_PAN;
1504 else
1505 cur_service_type = BT_OTHER_ACTION;
1506
1507 if (cur_service_type != rtlpcipriv->bt_coexist.bt_service) {
1508 rtlpcipriv->bt_coexist.bt_service = cur_service_type;
1509 bt_state = bt_state |
1510 ((rtlpcipriv->bt_coexist.bt_ant_isolation == 1) ?
1511 0 : BIT_OFFSET_LEN_MASK_32(1, 1)) |
1512 ((rtlpcipriv->bt_coexist.bt_service != BT_IDLE) ?
1513 0 : BIT_OFFSET_LEN_MASK_32(2, 1));
1514
1515 /* Add interrupt migration when bt is not ini
1516 * idle state (no traffic). */
1517 if (rtlpcipriv->bt_coexist.bt_service != BT_IDLE) {
1518 rtl_write_word(rtlpriv, 0x504, 0x0ccc);
1519 rtl_write_byte(rtlpriv, 0x506, 0x54);
1520 rtl_write_byte(rtlpriv, 0x507, 0x54);
1521 } else {
1522 rtl_write_byte(rtlpriv, 0x506, 0x00);
1523 rtl_write_byte(rtlpriv, 0x507, 0x00);
1524 }
1525
1526 rtl_write_byte(rtlpriv, 0x4fd, bt_state);
1527 return true;
1528 }
1529 }
1530
1531 return false;
1532
1533 }
1534
1535 static bool rtl92c_bt_wifi_connect_change(struct ieee80211_hw *hw)
1536 {
1537 struct rtl_priv *rtlpriv = rtl_priv(hw);
1538 static bool media_connect;
1539
1540 if (rtlpriv->mac80211.link_state < MAC80211_LINKED) {
1541 media_connect = false;
1542 } else {
1543 if (!media_connect) {
1544 media_connect = true;
1545 return true;
1546 }
1547 media_connect = true;
1548 }
1549
1550 return false;
1551 }
1552
1553 static void rtl92c_bt_set_normal(struct ieee80211_hw *hw)
1554 {
1555 struct rtl_priv *rtlpriv = rtl_priv(hw);
1556 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1557
1558
1559 if (rtlpcipriv->bt_coexist.bt_service == BT_OTHERBUSY) {
1560 rtlpcipriv->bt_coexist.bt_edca_ul = 0x5ea72b;
1561 rtlpcipriv->bt_coexist.bt_edca_dl = 0x5ea72b;
1562 } else if (rtlpcipriv->bt_coexist.bt_service == BT_BUSY) {
1563 rtlpcipriv->bt_coexist.bt_edca_ul = 0x5eb82f;
1564 rtlpcipriv->bt_coexist.bt_edca_dl = 0x5eb82f;
1565 } else if (rtlpcipriv->bt_coexist.bt_service == BT_SCO) {
1566 if (rtlpcipriv->bt_coexist.ratio_tx > 160) {
1567 rtlpcipriv->bt_coexist.bt_edca_ul = 0x5ea72f;
1568 rtlpcipriv->bt_coexist.bt_edca_dl = 0x5ea72f;
1569 } else {
1570 rtlpcipriv->bt_coexist.bt_edca_ul = 0x5ea32b;
1571 rtlpcipriv->bt_coexist.bt_edca_dl = 0x5ea42b;
1572 }
1573 } else {
1574 rtlpcipriv->bt_coexist.bt_edca_ul = 0;
1575 rtlpcipriv->bt_coexist.bt_edca_dl = 0;
1576 }
1577
1578 if ((rtlpcipriv->bt_coexist.bt_service != BT_IDLE) &&
1579 (rtlpriv->mac80211.mode == WIRELESS_MODE_G ||
1580 (rtlpriv->mac80211.mode == (WIRELESS_MODE_G | WIRELESS_MODE_B))) &&
1581 (rtlpcipriv->bt_coexist.bt_rssi_state &
1582 BT_RSSI_STATE_BG_EDCA_LOW)) {
1583 rtlpcipriv->bt_coexist.bt_edca_ul = 0x5eb82b;
1584 rtlpcipriv->bt_coexist.bt_edca_dl = 0x5eb82b;
1585 }
1586 }
1587
1588 static void rtl92c_bt_ant_isolation(struct ieee80211_hw *hw, u8 tmp1byte)
1589 {
1590 struct rtl_priv *rtlpriv = rtl_priv(hw);
1591 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1592
1593
1594 /* Only enable HW BT coexist when BT in "Busy" state. */
1595 if (rtlpriv->mac80211.vendor == PEER_CISCO &&
1596 rtlpcipriv->bt_coexist.bt_service == BT_OTHER_ACTION) {
1597 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0);
1598 } else {
1599 if ((rtlpcipriv->bt_coexist.bt_service == BT_BUSY) &&
1600 (rtlpcipriv->bt_coexist.bt_rssi_state &
1601 BT_RSSI_STATE_NORMAL_POWER)) {
1602 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0);
1603 } else if ((rtlpcipriv->bt_coexist.bt_service ==
1604 BT_OTHER_ACTION) && (rtlpriv->mac80211.mode <
1605 WIRELESS_MODE_N_24G) &&
1606 (rtlpcipriv->bt_coexist.bt_rssi_state &
1607 BT_RSSI_STATE_SPECIAL_LOW)) {
1608 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0);
1609 } else if (rtlpcipriv->bt_coexist.bt_service == BT_PAN) {
1610 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, tmp1byte);
1611 } else {
1612 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, tmp1byte);
1613 }
1614 }
1615
1616 if (rtlpcipriv->bt_coexist.bt_service == BT_PAN)
1617 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x10100);
1618 else
1619 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x0);
1620
1621 if (rtlpcipriv->bt_coexist.bt_rssi_state &
1622 BT_RSSI_STATE_NORMAL_POWER) {
1623 rtl92c_bt_set_normal(hw);
1624 } else {
1625 rtlpcipriv->bt_coexist.bt_edca_ul = 0;
1626 rtlpcipriv->bt_coexist.bt_edca_dl = 0;
1627 }
1628
1629 if (rtlpcipriv->bt_coexist.bt_service != BT_IDLE) {
1630 rtlpriv->cfg->ops->set_rfreg(hw,
1631 RF90_PATH_A,
1632 0x1e,
1633 0xf0, 0xf);
1634 } else {
1635 rtlpriv->cfg->ops->set_rfreg(hw,
1636 RF90_PATH_A, 0x1e, 0xf0,
1637 rtlpcipriv->bt_coexist.bt_rfreg_origin_1e);
1638 }
1639
1640 if (!rtlpriv->dm.dynamic_txpower_enable) {
1641 if (rtlpcipriv->bt_coexist.bt_service != BT_IDLE) {
1642 if (rtlpcipriv->bt_coexist.bt_rssi_state &
1643 BT_RSSI_STATE_TXPOWER_LOW) {
1644 rtlpriv->dm.dynamic_txhighpower_lvl =
1645 TXHIGHPWRLEVEL_BT2;
1646 } else {
1647 rtlpriv->dm.dynamic_txhighpower_lvl =
1648 TXHIGHPWRLEVEL_BT1;
1649 }
1650 } else {
1651 rtlpriv->dm.dynamic_txhighpower_lvl =
1652 TXHIGHPWRLEVEL_NORMAL;
1653 }
1654 rtl92c_phy_set_txpower_level(hw,
1655 rtlpriv->phy.current_channel);
1656 }
1657 }
1658
1659 static void rtl92c_check_bt_change(struct ieee80211_hw *hw)
1660 {
1661 struct rtl_priv *rtlpriv = rtl_priv(hw);
1662 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1663 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1664 u8 tmp1byte = 0;
1665
1666 if (IS_81xxC_VENDOR_UMC_B_CUT(rtlhal->version) &&
1667 rtlpcipriv->bt_coexist.bt_coexistence)
1668 tmp1byte |= BIT(5);
1669 if (rtlpcipriv->bt_coexist.bt_cur_state) {
1670 if (rtlpcipriv->bt_coexist.bt_ant_isolation)
1671 rtl92c_bt_ant_isolation(hw, tmp1byte);
1672 } else {
1673 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, tmp1byte);
1674 rtlpriv->cfg->ops->set_rfreg(hw, RF90_PATH_A, 0x1e, 0xf0,
1675 rtlpcipriv->bt_coexist.bt_rfreg_origin_1e);
1676
1677 rtlpcipriv->bt_coexist.bt_edca_ul = 0;
1678 rtlpcipriv->bt_coexist.bt_edca_dl = 0;
1679 }
1680 }
1681
1682 void rtl92c_dm_bt_coexist(struct ieee80211_hw *hw)
1683 {
1684 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1685
1686 bool wifi_connect_change;
1687 bool bt_state_change;
1688 bool rssi_state_change;
1689
1690 if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
1691 (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4)) {
1692
1693 wifi_connect_change = rtl92c_bt_wifi_connect_change(hw);
1694 bt_state_change = rtl92c_bt_state_change(hw);
1695 rssi_state_change = rtl92c_bt_rssi_state_change(hw);
1696
1697 if (wifi_connect_change || bt_state_change || rssi_state_change)
1698 rtl92c_check_bt_change(hw);
1699 }
1700 }
1701 EXPORT_SYMBOL(rtl92c_dm_bt_coexist);
Linux kernel - Deliverables
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