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Merge tag 'fbdev-updates-for-3.5' of git://github.com/schandinat/linux-2.6
[deliverable/linux.git] / drivers / net / wireless / rtlwifi / rtl8192c / dm_common.c
1 /******************************************************************************
2 *
3 * Copyright(c) 2009-2012 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30 #include <linux/export.h>
31 #include "dm_common.h"
32 #include "phy_common.h"
33 #include "../pci.h"
34 #include "../base.h"
35
36 #define BT_RSSI_STATE_NORMAL_POWER BIT_OFFSET_LEN_MASK_32(0, 1)
37 #define BT_RSSI_STATE_AMDPU_OFF BIT_OFFSET_LEN_MASK_32(1, 1)
38 #define BT_RSSI_STATE_SPECIAL_LOW BIT_OFFSET_LEN_MASK_32(2, 1)
39 #define BT_RSSI_STATE_BG_EDCA_LOW BIT_OFFSET_LEN_MASK_32(3, 1)
40 #define BT_RSSI_STATE_TXPOWER_LOW BIT_OFFSET_LEN_MASK_32(4, 1)
41
42 #define RTLPRIV (struct rtl_priv *)
43 #define GET_UNDECORATED_AVERAGE_RSSI(_priv) \
44 ((RTLPRIV(_priv))->mac80211.opmode == \
45 NL80211_IFTYPE_ADHOC) ? \
46 ((RTLPRIV(_priv))->dm.entry_min_undecoratedsmoothed_pwdb) : \
47 ((RTLPRIV(_priv))->dm.undecorated_smoothed_pwdb)
48
49 static const u32 ofdmswing_table[OFDM_TABLE_SIZE] = {
50 0x7f8001fe,
51 0x788001e2,
52 0x71c001c7,
53 0x6b8001ae,
54 0x65400195,
55 0x5fc0017f,
56 0x5a400169,
57 0x55400155,
58 0x50800142,
59 0x4c000130,
60 0x47c0011f,
61 0x43c0010f,
62 0x40000100,
63 0x3c8000f2,
64 0x390000e4,
65 0x35c000d7,
66 0x32c000cb,
67 0x300000c0,
68 0x2d4000b5,
69 0x2ac000ab,
70 0x288000a2,
71 0x26000098,
72 0x24000090,
73 0x22000088,
74 0x20000080,
75 0x1e400079,
76 0x1c800072,
77 0x1b00006c,
78 0x19800066,
79 0x18000060,
80 0x16c0005b,
81 0x15800056,
82 0x14400051,
83 0x1300004c,
84 0x12000048,
85 0x11000044,
86 0x10000040,
87 };
88
89 static const u8 cckswing_table_ch1ch13[CCK_TABLE_SIZE][8] = {
90 {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04},
91 {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04},
92 {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03},
93 {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03},
94 {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03},
95 {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03},
96 {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03},
97 {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03},
98 {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02},
99 {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02},
100 {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02},
101 {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02},
102 {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02},
103 {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02},
104 {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02},
105 {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02},
106 {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01},
107 {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02},
108 {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01},
109 {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},
110 {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},
111 {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01},
112 {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01},
113 {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01},
114 {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01},
115 {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01},
116 {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01},
117 {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01},
118 {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01},
119 {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01},
120 {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01},
121 {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},
122 {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}
123 };
124
125 static const u8 cckswing_table_ch14[CCK_TABLE_SIZE][8] = {
126 {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00},
127 {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00},
128 {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00},
129 {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00},
130 {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00},
131 {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00},
132 {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00},
133 {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00},
134 {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00},
135 {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00},
136 {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00},
137 {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00},
138 {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00},
139 {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00},
140 {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00},
141 {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00},
142 {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00},
143 {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00},
144 {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00},
145 {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},
146 {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},
147 {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00},
148 {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00},
149 {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},
150 {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},
151 {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00},
152 {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},
153 {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},
154 {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},
155 {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},
156 {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},
157 {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},
158 {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}
159 };
160
161 static void rtl92c_dm_diginit(struct ieee80211_hw *hw)
162 {
163 struct rtl_priv *rtlpriv = rtl_priv(hw);
164 struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
165
166 dm_digtable->dig_enable_flag = true;
167 dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
168 dm_digtable->cur_igvalue = 0x20;
169 dm_digtable->pre_igvalue = 0x0;
170 dm_digtable->cursta_connectctate = DIG_STA_DISCONNECT;
171 dm_digtable->presta_connectstate = DIG_STA_DISCONNECT;
172 dm_digtable->curmultista_connectstate = DIG_MULTISTA_DISCONNECT;
173 dm_digtable->rssi_lowthresh = DM_DIG_THRESH_LOW;
174 dm_digtable->rssi_highthresh = DM_DIG_THRESH_HIGH;
175 dm_digtable->fa_lowthresh = DM_FALSEALARM_THRESH_LOW;
176 dm_digtable->fa_highthresh = DM_FALSEALARM_THRESH_HIGH;
177 dm_digtable->rx_gain_range_max = DM_DIG_MAX;
178 dm_digtable->rx_gain_range_min = DM_DIG_MIN;
179 dm_digtable->backoff_val = DM_DIG_BACKOFF_DEFAULT;
180 dm_digtable->backoff_val_range_max = DM_DIG_BACKOFF_MAX;
181 dm_digtable->backoff_val_range_min = DM_DIG_BACKOFF_MIN;
182 dm_digtable->pre_cck_pd_state = CCK_PD_STAGE_MAX;
183 dm_digtable->cur_cck_pd_state = CCK_PD_STAGE_MAX;
184 }
185
186 static u8 rtl92c_dm_initial_gain_min_pwdb(struct ieee80211_hw *hw)
187 {
188 struct rtl_priv *rtlpriv = rtl_priv(hw);
189 struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
190 long rssi_val_min = 0;
191
192 if ((dm_digtable->curmultista_connectstate == DIG_MULTISTA_CONNECT) &&
193 (dm_digtable->cursta_connectctate == DIG_STA_CONNECT)) {
194 if (rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb != 0)
195 rssi_val_min =
196 (rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb >
197 rtlpriv->dm.undecorated_smoothed_pwdb) ?
198 rtlpriv->dm.undecorated_smoothed_pwdb :
199 rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
200 else
201 rssi_val_min = rtlpriv->dm.undecorated_smoothed_pwdb;
202 } else if (dm_digtable->cursta_connectctate == DIG_STA_CONNECT ||
203 dm_digtable->cursta_connectctate == DIG_STA_BEFORE_CONNECT) {
204 rssi_val_min = rtlpriv->dm.undecorated_smoothed_pwdb;
205 } else if (dm_digtable->curmultista_connectstate ==
206 DIG_MULTISTA_CONNECT) {
207 rssi_val_min = rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
208 }
209
210 return (u8) rssi_val_min;
211 }
212
213 static void rtl92c_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw)
214 {
215 u32 ret_value;
216 struct rtl_priv *rtlpriv = rtl_priv(hw);
217 struct false_alarm_statistics *falsealm_cnt = &(rtlpriv->falsealm_cnt);
218
219 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER1, MASKDWORD);
220 falsealm_cnt->cnt_parity_fail = ((ret_value & 0xffff0000) >> 16);
221
222 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER2, MASKDWORD);
223 falsealm_cnt->cnt_rate_illegal = (ret_value & 0xffff);
224 falsealm_cnt->cnt_crc8_fail = ((ret_value & 0xffff0000) >> 16);
225
226 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER3, MASKDWORD);
227 falsealm_cnt->cnt_mcs_fail = (ret_value & 0xffff);
228 falsealm_cnt->cnt_ofdm_fail = falsealm_cnt->cnt_parity_fail +
229 falsealm_cnt->cnt_rate_illegal +
230 falsealm_cnt->cnt_crc8_fail + falsealm_cnt->cnt_mcs_fail;
231
232 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, BIT(14), 1);
233 ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERLOWER, MASKBYTE0);
234 falsealm_cnt->cnt_cck_fail = ret_value;
235
236 ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERUPPER, MASKBYTE3);
237 falsealm_cnt->cnt_cck_fail += (ret_value & 0xff) << 8;
238 falsealm_cnt->cnt_all = (falsealm_cnt->cnt_parity_fail +
239 falsealm_cnt->cnt_rate_illegal +
240 falsealm_cnt->cnt_crc8_fail +
241 falsealm_cnt->cnt_mcs_fail +
242 falsealm_cnt->cnt_cck_fail);
243
244 rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 1);
245 rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 0);
246 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 0);
247 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 2);
248
249 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
250 "cnt_parity_fail = %d, cnt_rate_illegal = %d, cnt_crc8_fail = %d, cnt_mcs_fail = %d\n",
251 falsealm_cnt->cnt_parity_fail,
252 falsealm_cnt->cnt_rate_illegal,
253 falsealm_cnt->cnt_crc8_fail, falsealm_cnt->cnt_mcs_fail);
254
255 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
256 "cnt_ofdm_fail = %x, cnt_cck_fail = %x, cnt_all = %x\n",
257 falsealm_cnt->cnt_ofdm_fail,
258 falsealm_cnt->cnt_cck_fail, falsealm_cnt->cnt_all);
259 }
260
261 static void rtl92c_dm_ctrl_initgain_by_fa(struct ieee80211_hw *hw)
262 {
263 struct rtl_priv *rtlpriv = rtl_priv(hw);
264 struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
265 u8 value_igi = dm_digtable->cur_igvalue;
266
267 if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH0)
268 value_igi--;
269 else if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH1)
270 value_igi += 0;
271 else if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH2)
272 value_igi++;
273 else if (rtlpriv->falsealm_cnt.cnt_all >= DM_DIG_FA_TH2)
274 value_igi += 2;
275 if (value_igi > DM_DIG_FA_UPPER)
276 value_igi = DM_DIG_FA_UPPER;
277 else if (value_igi < DM_DIG_FA_LOWER)
278 value_igi = DM_DIG_FA_LOWER;
279 if (rtlpriv->falsealm_cnt.cnt_all > 10000)
280 value_igi = 0x32;
281
282 dm_digtable->cur_igvalue = value_igi;
283 rtl92c_dm_write_dig(hw);
284 }
285
286 static void rtl92c_dm_ctrl_initgain_by_rssi(struct ieee80211_hw *hw)
287 {
288 struct rtl_priv *rtlpriv = rtl_priv(hw);
289 struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
290
291 if (rtlpriv->falsealm_cnt.cnt_all > dm_digtable->fa_highthresh) {
292 if ((dm_digtable->backoff_val - 2) <
293 dm_digtable->backoff_val_range_min)
294 dm_digtable->backoff_val =
295 dm_digtable->backoff_val_range_min;
296 else
297 dm_digtable->backoff_val -= 2;
298 } else if (rtlpriv->falsealm_cnt.cnt_all < dm_digtable->fa_lowthresh) {
299 if ((dm_digtable->backoff_val + 2) >
300 dm_digtable->backoff_val_range_max)
301 dm_digtable->backoff_val =
302 dm_digtable->backoff_val_range_max;
303 else
304 dm_digtable->backoff_val += 2;
305 }
306
307 if ((dm_digtable->rssi_val_min + 10 - dm_digtable->backoff_val) >
308 dm_digtable->rx_gain_range_max)
309 dm_digtable->cur_igvalue = dm_digtable->rx_gain_range_max;
310 else if ((dm_digtable->rssi_val_min + 10 -
311 dm_digtable->backoff_val) < dm_digtable->rx_gain_range_min)
312 dm_digtable->cur_igvalue = dm_digtable->rx_gain_range_min;
313 else
314 dm_digtable->cur_igvalue = dm_digtable->rssi_val_min + 10 -
315 dm_digtable->backoff_val;
316
317 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
318 "rssi_val_min = %x backoff_val %x\n",
319 dm_digtable->rssi_val_min, dm_digtable->backoff_val);
320
321 rtl92c_dm_write_dig(hw);
322 }
323
324 static void rtl92c_dm_initial_gain_multi_sta(struct ieee80211_hw *hw)
325 {
326 static u8 initialized; /* initialized to false */
327 struct rtl_priv *rtlpriv = rtl_priv(hw);
328 struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
329 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
330 long rssi_strength = rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
331 bool multi_sta = false;
332
333 if (mac->opmode == NL80211_IFTYPE_ADHOC)
334 multi_sta = true;
335
336 if (!multi_sta ||
337 dm_digtable->cursta_connectctate != DIG_STA_DISCONNECT) {
338 initialized = false;
339 dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
340 return;
341 } else if (initialized == false) {
342 initialized = true;
343 dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_0;
344 dm_digtable->cur_igvalue = 0x20;
345 rtl92c_dm_write_dig(hw);
346 }
347
348 if (dm_digtable->curmultista_connectstate == DIG_MULTISTA_CONNECT) {
349 if ((rssi_strength < dm_digtable->rssi_lowthresh) &&
350 (dm_digtable->dig_ext_port_stage != DIG_EXT_PORT_STAGE_1)) {
351
352 if (dm_digtable->dig_ext_port_stage ==
353 DIG_EXT_PORT_STAGE_2) {
354 dm_digtable->cur_igvalue = 0x20;
355 rtl92c_dm_write_dig(hw);
356 }
357
358 dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_1;
359 } else if (rssi_strength > dm_digtable->rssi_highthresh) {
360 dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_2;
361 rtl92c_dm_ctrl_initgain_by_fa(hw);
362 }
363 } else if (dm_digtable->dig_ext_port_stage != DIG_EXT_PORT_STAGE_0) {
364 dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_0;
365 dm_digtable->cur_igvalue = 0x20;
366 rtl92c_dm_write_dig(hw);
367 }
368
369 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
370 "curmultista_connectstate = %x dig_ext_port_stage %x\n",
371 dm_digtable->curmultista_connectstate,
372 dm_digtable->dig_ext_port_stage);
373 }
374
375 static void rtl92c_dm_initial_gain_sta(struct ieee80211_hw *hw)
376 {
377 struct rtl_priv *rtlpriv = rtl_priv(hw);
378 struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
379
380 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
381 "presta_connectstate = %x, cursta_connectctate = %x\n",
382 dm_digtable->presta_connectstate,
383 dm_digtable->cursta_connectctate);
384
385 if (dm_digtable->presta_connectstate == dm_digtable->cursta_connectctate
386 || dm_digtable->cursta_connectctate == DIG_STA_BEFORE_CONNECT
387 || dm_digtable->cursta_connectctate == DIG_STA_CONNECT) {
388
389 if (dm_digtable->cursta_connectctate != DIG_STA_DISCONNECT) {
390 dm_digtable->rssi_val_min =
391 rtl92c_dm_initial_gain_min_pwdb(hw);
392 rtl92c_dm_ctrl_initgain_by_rssi(hw);
393 }
394 } else {
395 dm_digtable->rssi_val_min = 0;
396 dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
397 dm_digtable->backoff_val = DM_DIG_BACKOFF_DEFAULT;
398 dm_digtable->cur_igvalue = 0x20;
399 dm_digtable->pre_igvalue = 0;
400 rtl92c_dm_write_dig(hw);
401 }
402 }
403
404 static void rtl92c_dm_cck_packet_detection_thresh(struct ieee80211_hw *hw)
405 {
406 struct rtl_priv *rtlpriv = rtl_priv(hw);
407 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
408 struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
409
410 if (dm_digtable->cursta_connectctate == DIG_STA_CONNECT) {
411 dm_digtable->rssi_val_min = rtl92c_dm_initial_gain_min_pwdb(hw);
412
413 if (dm_digtable->pre_cck_pd_state == CCK_PD_STAGE_LowRssi) {
414 if (dm_digtable->rssi_val_min <= 25)
415 dm_digtable->cur_cck_pd_state =
416 CCK_PD_STAGE_LowRssi;
417 else
418 dm_digtable->cur_cck_pd_state =
419 CCK_PD_STAGE_HighRssi;
420 } else {
421 if (dm_digtable->rssi_val_min <= 20)
422 dm_digtable->cur_cck_pd_state =
423 CCK_PD_STAGE_LowRssi;
424 else
425 dm_digtable->cur_cck_pd_state =
426 CCK_PD_STAGE_HighRssi;
427 }
428 } else {
429 dm_digtable->cur_cck_pd_state = CCK_PD_STAGE_MAX;
430 }
431
432 if (dm_digtable->pre_cck_pd_state != dm_digtable->cur_cck_pd_state) {
433 if (dm_digtable->cur_cck_pd_state == CCK_PD_STAGE_LowRssi) {
434 if (rtlpriv->falsealm_cnt.cnt_cck_fail > 800)
435 dm_digtable->cur_cck_fa_state =
436 CCK_FA_STAGE_High;
437 else
438 dm_digtable->cur_cck_fa_state = CCK_FA_STAGE_Low;
439
440 if (dm_digtable->pre_cck_fa_state !=
441 dm_digtable->cur_cck_fa_state) {
442 if (dm_digtable->cur_cck_fa_state ==
443 CCK_FA_STAGE_Low)
444 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2,
445 0x83);
446 else
447 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2,
448 0xcd);
449
450 dm_digtable->pre_cck_fa_state =
451 dm_digtable->cur_cck_fa_state;
452 }
453
454 rtl_set_bbreg(hw, RCCK0_SYSTEM, MASKBYTE1, 0x40);
455
456 if (IS_92C_SERIAL(rtlhal->version))
457 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT,
458 MASKBYTE2, 0xd7);
459 } else {
460 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd);
461 rtl_set_bbreg(hw, RCCK0_SYSTEM, MASKBYTE1, 0x47);
462
463 if (IS_92C_SERIAL(rtlhal->version))
464 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT,
465 MASKBYTE2, 0xd3);
466 }
467 dm_digtable->pre_cck_pd_state = dm_digtable->cur_cck_pd_state;
468 }
469
470 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE, "CCKPDStage=%x\n",
471 dm_digtable->cur_cck_pd_state);
472
473 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE, "is92C=%x\n",
474 IS_92C_SERIAL(rtlhal->version));
475 }
476
477 static void rtl92c_dm_ctrl_initgain_by_twoport(struct ieee80211_hw *hw)
478 {
479 struct rtl_priv *rtlpriv = rtl_priv(hw);
480 struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
481 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
482
483 if (mac->act_scanning)
484 return;
485
486 if (mac->link_state >= MAC80211_LINKED)
487 dm_digtable->cursta_connectctate = DIG_STA_CONNECT;
488 else
489 dm_digtable->cursta_connectctate = DIG_STA_DISCONNECT;
490
491 rtl92c_dm_initial_gain_sta(hw);
492 rtl92c_dm_initial_gain_multi_sta(hw);
493 rtl92c_dm_cck_packet_detection_thresh(hw);
494
495 dm_digtable->presta_connectstate = dm_digtable->cursta_connectctate;
496
497 }
498
499 static void rtl92c_dm_dig(struct ieee80211_hw *hw)
500 {
501 struct rtl_priv *rtlpriv = rtl_priv(hw);
502 struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
503
504 if (rtlpriv->dm.dm_initialgain_enable == false)
505 return;
506 if (dm_digtable->dig_enable_flag == false)
507 return;
508
509 rtl92c_dm_ctrl_initgain_by_twoport(hw);
510
511 }
512
513 static void rtl92c_dm_init_dynamic_txpower(struct ieee80211_hw *hw)
514 {
515 struct rtl_priv *rtlpriv = rtl_priv(hw);
516
517 rtlpriv->dm.dynamic_txpower_enable = false;
518
519 rtlpriv->dm.last_dtp_lvl = TXHIGHPWRLEVEL_NORMAL;
520 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
521 }
522
523 void rtl92c_dm_write_dig(struct ieee80211_hw *hw)
524 {
525 struct rtl_priv *rtlpriv = rtl_priv(hw);
526 struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
527
528 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
529 "cur_igvalue = 0x%x, pre_igvalue = 0x%x, backoff_val = %d\n",
530 dm_digtable->cur_igvalue, dm_digtable->pre_igvalue,
531 dm_digtable->backoff_val);
532
533 dm_digtable->cur_igvalue += 2;
534 if (dm_digtable->cur_igvalue > 0x3f)
535 dm_digtable->cur_igvalue = 0x3f;
536
537 if (dm_digtable->pre_igvalue != dm_digtable->cur_igvalue) {
538 rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, 0x7f,
539 dm_digtable->cur_igvalue);
540 rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, 0x7f,
541 dm_digtable->cur_igvalue);
542
543 dm_digtable->pre_igvalue = dm_digtable->cur_igvalue;
544 }
545 }
546 EXPORT_SYMBOL(rtl92c_dm_write_dig);
547
548 static void rtl92c_dm_pwdb_monitor(struct ieee80211_hw *hw)
549 {
550 struct rtl_priv *rtlpriv = rtl_priv(hw);
551 long tmpentry_max_pwdb = 0, tmpentry_min_pwdb = 0xff;
552
553 u8 h2c_parameter[3] = { 0 };
554
555 return;
556
557 if (tmpentry_max_pwdb != 0) {
558 rtlpriv->dm.entry_max_undecoratedsmoothed_pwdb =
559 tmpentry_max_pwdb;
560 } else {
561 rtlpriv->dm.entry_max_undecoratedsmoothed_pwdb = 0;
562 }
563
564 if (tmpentry_min_pwdb != 0xff) {
565 rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb =
566 tmpentry_min_pwdb;
567 } else {
568 rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb = 0;
569 }
570
571 h2c_parameter[2] = (u8) (rtlpriv->dm.undecorated_smoothed_pwdb & 0xFF);
572 h2c_parameter[0] = 0;
573
574 rtl92c_fill_h2c_cmd(hw, H2C_RSSI_REPORT, 3, h2c_parameter);
575 }
576
577 void rtl92c_dm_init_edca_turbo(struct ieee80211_hw *hw)
578 {
579 struct rtl_priv *rtlpriv = rtl_priv(hw);
580 rtlpriv->dm.current_turbo_edca = false;
581 rtlpriv->dm.is_any_nonbepkts = false;
582 rtlpriv->dm.is_cur_rdlstate = false;
583 }
584 EXPORT_SYMBOL(rtl92c_dm_init_edca_turbo);
585
586 static void rtl92c_dm_check_edca_turbo(struct ieee80211_hw *hw)
587 {
588 struct rtl_priv *rtlpriv = rtl_priv(hw);
589 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
590 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
591
592 static u64 last_txok_cnt;
593 static u64 last_rxok_cnt;
594 static u32 last_bt_edca_ul;
595 static u32 last_bt_edca_dl;
596 u64 cur_txok_cnt = 0;
597 u64 cur_rxok_cnt = 0;
598 u32 edca_be_ul = 0x5ea42b;
599 u32 edca_be_dl = 0x5ea42b;
600 bool bt_change_edca = false;
601
602 if ((last_bt_edca_ul != rtlpcipriv->bt_coexist.bt_edca_ul) ||
603 (last_bt_edca_dl != rtlpcipriv->bt_coexist.bt_edca_dl)) {
604 rtlpriv->dm.current_turbo_edca = false;
605 last_bt_edca_ul = rtlpcipriv->bt_coexist.bt_edca_ul;
606 last_bt_edca_dl = rtlpcipriv->bt_coexist.bt_edca_dl;
607 }
608
609 if (rtlpcipriv->bt_coexist.bt_edca_ul != 0) {
610 edca_be_ul = rtlpcipriv->bt_coexist.bt_edca_ul;
611 bt_change_edca = true;
612 }
613
614 if (rtlpcipriv->bt_coexist.bt_edca_dl != 0) {
615 edca_be_ul = rtlpcipriv->bt_coexist.bt_edca_dl;
616 bt_change_edca = true;
617 }
618
619 if (mac->link_state != MAC80211_LINKED) {
620 rtlpriv->dm.current_turbo_edca = false;
621 return;
622 }
623
624 if ((!mac->ht_enable) && (!rtlpcipriv->bt_coexist.bt_coexistence)) {
625 if (!(edca_be_ul & 0xffff0000))
626 edca_be_ul |= 0x005e0000;
627
628 if (!(edca_be_dl & 0xffff0000))
629 edca_be_dl |= 0x005e0000;
630 }
631
632 if ((bt_change_edca) || ((!rtlpriv->dm.is_any_nonbepkts) &&
633 (!rtlpriv->dm.disable_framebursting))) {
634
635 cur_txok_cnt = rtlpriv->stats.txbytesunicast - last_txok_cnt;
636 cur_rxok_cnt = rtlpriv->stats.rxbytesunicast - last_rxok_cnt;
637
638 if (cur_rxok_cnt > 4 * cur_txok_cnt) {
639 if (!rtlpriv->dm.is_cur_rdlstate ||
640 !rtlpriv->dm.current_turbo_edca) {
641 rtl_write_dword(rtlpriv,
642 REG_EDCA_BE_PARAM,
643 edca_be_dl);
644 rtlpriv->dm.is_cur_rdlstate = true;
645 }
646 } else {
647 if (rtlpriv->dm.is_cur_rdlstate ||
648 !rtlpriv->dm.current_turbo_edca) {
649 rtl_write_dword(rtlpriv,
650 REG_EDCA_BE_PARAM,
651 edca_be_ul);
652 rtlpriv->dm.is_cur_rdlstate = false;
653 }
654 }
655 rtlpriv->dm.current_turbo_edca = true;
656 } else {
657 if (rtlpriv->dm.current_turbo_edca) {
658 u8 tmp = AC0_BE;
659 rtlpriv->cfg->ops->set_hw_reg(hw,
660 HW_VAR_AC_PARAM,
661 (u8 *) (&tmp));
662 rtlpriv->dm.current_turbo_edca = false;
663 }
664 }
665
666 rtlpriv->dm.is_any_nonbepkts = false;
667 last_txok_cnt = rtlpriv->stats.txbytesunicast;
668 last_rxok_cnt = rtlpriv->stats.rxbytesunicast;
669 }
670
671 static void rtl92c_dm_txpower_tracking_callback_thermalmeter(struct ieee80211_hw
672 *hw)
673 {
674 struct rtl_priv *rtlpriv = rtl_priv(hw);
675 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
676 struct rtl_phy *rtlphy = &(rtlpriv->phy);
677 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
678 u8 thermalvalue, delta, delta_lck, delta_iqk;
679 long ele_a, ele_d, temp_cck, val_x, value32;
680 long val_y, ele_c = 0;
681 u8 ofdm_index[2], cck_index = 0, ofdm_index_old[2], cck_index_old = 0;
682 int i;
683 bool is2t = IS_92C_SERIAL(rtlhal->version);
684 s8 txpwr_level[2] = {0, 0};
685 u8 ofdm_min_index = 6, rf;
686
687 rtlpriv->dm.txpower_trackinginit = true;
688 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
689 "rtl92c_dm_txpower_tracking_callback_thermalmeter\n");
690
691 thermalvalue = (u8) rtl_get_rfreg(hw, RF90_PATH_A, RF_T_METER, 0x1f);
692
693 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
694 "Readback Thermal Meter = 0x%x pre thermal meter 0x%x eeprom_thermalmeter 0x%x\n",
695 thermalvalue, rtlpriv->dm.thermalvalue,
696 rtlefuse->eeprom_thermalmeter);
697
698 rtl92c_phy_ap_calibrate(hw, (thermalvalue -
699 rtlefuse->eeprom_thermalmeter));
700 if (is2t)
701 rf = 2;
702 else
703 rf = 1;
704
705 if (thermalvalue) {
706 ele_d = rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
707 MASKDWORD) & MASKOFDM_D;
708
709 for (i = 0; i < OFDM_TABLE_LENGTH; i++) {
710 if (ele_d == (ofdmswing_table[i] & MASKOFDM_D)) {
711 ofdm_index_old[0] = (u8) i;
712
713 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
714 "Initial pathA ele_d reg0x%x = 0x%lx, ofdm_index=0x%x\n",
715 ROFDM0_XATXIQIMBALANCE,
716 ele_d, ofdm_index_old[0]);
717 break;
718 }
719 }
720
721 if (is2t) {
722 ele_d = rtl_get_bbreg(hw, ROFDM0_XBTXIQIMBALANCE,
723 MASKDWORD) & MASKOFDM_D;
724
725 for (i = 0; i < OFDM_TABLE_LENGTH; i++) {
726 if (ele_d == (ofdmswing_table[i] &
727 MASKOFDM_D)) {
728
729 RT_TRACE(rtlpriv, COMP_POWER_TRACKING,
730 DBG_LOUD,
731 "Initial pathB ele_d reg0x%x = 0x%lx, ofdm_index=0x%x\n",
732 ROFDM0_XBTXIQIMBALANCE, ele_d,
733 ofdm_index_old[1]);
734 break;
735 }
736 }
737 }
738
739 temp_cck =
740 rtl_get_bbreg(hw, RCCK0_TXFILTER2, MASKDWORD) & MASKCCK;
741
742 for (i = 0; i < CCK_TABLE_LENGTH; i++) {
743 if (rtlpriv->dm.cck_inch14) {
744 if (memcmp((void *)&temp_cck,
745 (void *)&cckswing_table_ch14[i][2],
746 4) == 0) {
747 cck_index_old = (u8) i;
748
749 RT_TRACE(rtlpriv, COMP_POWER_TRACKING,
750 DBG_LOUD,
751 "Initial reg0x%x = 0x%lx, cck_index=0x%x, ch 14 %d\n",
752 RCCK0_TXFILTER2, temp_cck,
753 cck_index_old,
754 rtlpriv->dm.cck_inch14);
755 break;
756 }
757 } else {
758 if (memcmp((void *)&temp_cck,
759 (void *)
760 &cckswing_table_ch1ch13[i][2],
761 4) == 0) {
762 cck_index_old = (u8) i;
763
764 RT_TRACE(rtlpriv, COMP_POWER_TRACKING,
765 DBG_LOUD,
766 "Initial reg0x%x = 0x%lx, cck_index=0x%x, ch14 %d\n",
767 RCCK0_TXFILTER2, temp_cck,
768 cck_index_old,
769 rtlpriv->dm.cck_inch14);
770 break;
771 }
772 }
773 }
774
775 if (!rtlpriv->dm.thermalvalue) {
776 rtlpriv->dm.thermalvalue =
777 rtlefuse->eeprom_thermalmeter;
778 rtlpriv->dm.thermalvalue_lck = thermalvalue;
779 rtlpriv->dm.thermalvalue_iqk = thermalvalue;
780 for (i = 0; i < rf; i++)
781 rtlpriv->dm.ofdm_index[i] = ofdm_index_old[i];
782 rtlpriv->dm.cck_index = cck_index_old;
783 }
784
785 delta = (thermalvalue > rtlpriv->dm.thermalvalue) ?
786 (thermalvalue - rtlpriv->dm.thermalvalue) :
787 (rtlpriv->dm.thermalvalue - thermalvalue);
788
789 delta_lck = (thermalvalue > rtlpriv->dm.thermalvalue_lck) ?
790 (thermalvalue - rtlpriv->dm.thermalvalue_lck) :
791 (rtlpriv->dm.thermalvalue_lck - thermalvalue);
792
793 delta_iqk = (thermalvalue > rtlpriv->dm.thermalvalue_iqk) ?
794 (thermalvalue - rtlpriv->dm.thermalvalue_iqk) :
795 (rtlpriv->dm.thermalvalue_iqk - thermalvalue);
796
797 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
798 "Readback Thermal Meter = 0x%x pre thermal meter 0x%x eeprom_thermalmeter 0x%x delta 0x%x delta_lck 0x%x delta_iqk 0x%x\n",
799 thermalvalue, rtlpriv->dm.thermalvalue,
800 rtlefuse->eeprom_thermalmeter, delta, delta_lck,
801 delta_iqk);
802
803 if (delta_lck > 1) {
804 rtlpriv->dm.thermalvalue_lck = thermalvalue;
805 rtl92c_phy_lc_calibrate(hw);
806 }
807
808 if (delta > 0 && rtlpriv->dm.txpower_track_control) {
809 if (thermalvalue > rtlpriv->dm.thermalvalue) {
810 for (i = 0; i < rf; i++)
811 rtlpriv->dm.ofdm_index[i] -= delta;
812 rtlpriv->dm.cck_index -= delta;
813 } else {
814 for (i = 0; i < rf; i++)
815 rtlpriv->dm.ofdm_index[i] += delta;
816 rtlpriv->dm.cck_index += delta;
817 }
818
819 if (is2t) {
820 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
821 "temp OFDM_A_index=0x%x, OFDM_B_index=0x%x, cck_index=0x%x\n",
822 rtlpriv->dm.ofdm_index[0],
823 rtlpriv->dm.ofdm_index[1],
824 rtlpriv->dm.cck_index);
825 } else {
826 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
827 "temp OFDM_A_index=0x%x, cck_index=0x%x\n",
828 rtlpriv->dm.ofdm_index[0],
829 rtlpriv->dm.cck_index);
830 }
831
832 if (thermalvalue > rtlefuse->eeprom_thermalmeter) {
833 for (i = 0; i < rf; i++)
834 ofdm_index[i] =
835 rtlpriv->dm.ofdm_index[i]
836 + 1;
837 cck_index = rtlpriv->dm.cck_index + 1;
838 } else {
839 for (i = 0; i < rf; i++)
840 ofdm_index[i] =
841 rtlpriv->dm.ofdm_index[i];
842 cck_index = rtlpriv->dm.cck_index;
843 }
844
845 for (i = 0; i < rf; i++) {
846 if (txpwr_level[i] >= 0 &&
847 txpwr_level[i] <= 26) {
848 if (thermalvalue >
849 rtlefuse->eeprom_thermalmeter) {
850 if (delta < 5)
851 ofdm_index[i] -= 1;
852
853 else
854 ofdm_index[i] -= 2;
855 } else if (delta > 5 && thermalvalue <
856 rtlefuse->
857 eeprom_thermalmeter) {
858 ofdm_index[i] += 1;
859 }
860 } else if (txpwr_level[i] >= 27 &&
861 txpwr_level[i] <= 32
862 && thermalvalue >
863 rtlefuse->eeprom_thermalmeter) {
864 if (delta < 5)
865 ofdm_index[i] -= 1;
866
867 else
868 ofdm_index[i] -= 2;
869 } else if (txpwr_level[i] >= 32 &&
870 txpwr_level[i] <= 38 &&
871 thermalvalue >
872 rtlefuse->eeprom_thermalmeter
873 && delta > 5) {
874 ofdm_index[i] -= 1;
875 }
876 }
877
878 if (txpwr_level[i] >= 0 && txpwr_level[i] <= 26) {
879 if (thermalvalue >
880 rtlefuse->eeprom_thermalmeter) {
881 if (delta < 5)
882 cck_index -= 1;
883
884 else
885 cck_index -= 2;
886 } else if (delta > 5 && thermalvalue <
887 rtlefuse->eeprom_thermalmeter) {
888 cck_index += 1;
889 }
890 } else if (txpwr_level[i] >= 27 &&
891 txpwr_level[i] <= 32 &&
892 thermalvalue >
893 rtlefuse->eeprom_thermalmeter) {
894 if (delta < 5)
895 cck_index -= 1;
896
897 else
898 cck_index -= 2;
899 } else if (txpwr_level[i] >= 32 &&
900 txpwr_level[i] <= 38 &&
901 thermalvalue > rtlefuse->eeprom_thermalmeter
902 && delta > 5) {
903 cck_index -= 1;
904 }
905
906 for (i = 0; i < rf; i++) {
907 if (ofdm_index[i] > OFDM_TABLE_SIZE - 1)
908 ofdm_index[i] = OFDM_TABLE_SIZE - 1;
909
910 else if (ofdm_index[i] < ofdm_min_index)
911 ofdm_index[i] = ofdm_min_index;
912 }
913
914 if (cck_index > CCK_TABLE_SIZE - 1)
915 cck_index = CCK_TABLE_SIZE - 1;
916 else if (cck_index < 0)
917 cck_index = 0;
918
919 if (is2t) {
920 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
921 "new OFDM_A_index=0x%x, OFDM_B_index=0x%x, cck_index=0x%x\n",
922 ofdm_index[0], ofdm_index[1],
923 cck_index);
924 } else {
925 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
926 "new OFDM_A_index=0x%x, cck_index=0x%x\n",
927 ofdm_index[0], cck_index);
928 }
929 }
930
931 if (rtlpriv->dm.txpower_track_control && delta != 0) {
932 ele_d =
933 (ofdmswing_table[ofdm_index[0]] & 0xFFC00000) >> 22;
934 val_x = rtlphy->reg_e94;
935 val_y = rtlphy->reg_e9c;
936
937 if (val_x != 0) {
938 if ((val_x & 0x00000200) != 0)
939 val_x = val_x | 0xFFFFFC00;
940 ele_a = ((val_x * ele_d) >> 8) & 0x000003FF;
941
942 if ((val_y & 0x00000200) != 0)
943 val_y = val_y | 0xFFFFFC00;
944 ele_c = ((val_y * ele_d) >> 8) & 0x000003FF;
945
946 value32 = (ele_d << 22) |
947 ((ele_c & 0x3F) << 16) | ele_a;
948
949 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
950 MASKDWORD, value32);
951
952 value32 = (ele_c & 0x000003C0) >> 6;
953 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, MASKH4BITS,
954 value32);
955
956 value32 = ((val_x * ele_d) >> 7) & 0x01;
957 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
958 BIT(31), value32);
959
960 value32 = ((val_y * ele_d) >> 7) & 0x01;
961 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
962 BIT(29), value32);
963 } else {
964 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
965 MASKDWORD,
966 ofdmswing_table[ofdm_index[0]]);
967
968 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, MASKH4BITS,
969 0x00);
970 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
971 BIT(31) | BIT(29), 0x00);
972 }
973
974 if (!rtlpriv->dm.cck_inch14) {
975 rtl_write_byte(rtlpriv, 0xa22,
976 cckswing_table_ch1ch13[cck_index]
977 [0]);
978 rtl_write_byte(rtlpriv, 0xa23,
979 cckswing_table_ch1ch13[cck_index]
980 [1]);
981 rtl_write_byte(rtlpriv, 0xa24,
982 cckswing_table_ch1ch13[cck_index]
983 [2]);
984 rtl_write_byte(rtlpriv, 0xa25,
985 cckswing_table_ch1ch13[cck_index]
986 [3]);
987 rtl_write_byte(rtlpriv, 0xa26,
988 cckswing_table_ch1ch13[cck_index]
989 [4]);
990 rtl_write_byte(rtlpriv, 0xa27,
991 cckswing_table_ch1ch13[cck_index]
992 [5]);
993 rtl_write_byte(rtlpriv, 0xa28,
994 cckswing_table_ch1ch13[cck_index]
995 [6]);
996 rtl_write_byte(rtlpriv, 0xa29,
997 cckswing_table_ch1ch13[cck_index]
998 [7]);
999 } else {
1000 rtl_write_byte(rtlpriv, 0xa22,
1001 cckswing_table_ch14[cck_index]
1002 [0]);
1003 rtl_write_byte(rtlpriv, 0xa23,
1004 cckswing_table_ch14[cck_index]
1005 [1]);
1006 rtl_write_byte(rtlpriv, 0xa24,
1007 cckswing_table_ch14[cck_index]
1008 [2]);
1009 rtl_write_byte(rtlpriv, 0xa25,
1010 cckswing_table_ch14[cck_index]
1011 [3]);
1012 rtl_write_byte(rtlpriv, 0xa26,
1013 cckswing_table_ch14[cck_index]
1014 [4]);
1015 rtl_write_byte(rtlpriv, 0xa27,
1016 cckswing_table_ch14[cck_index]
1017 [5]);
1018 rtl_write_byte(rtlpriv, 0xa28,
1019 cckswing_table_ch14[cck_index]
1020 [6]);
1021 rtl_write_byte(rtlpriv, 0xa29,
1022 cckswing_table_ch14[cck_index]
1023 [7]);
1024 }
1025
1026 if (is2t) {
1027 ele_d = (ofdmswing_table[ofdm_index[1]] &
1028 0xFFC00000) >> 22;
1029
1030 val_x = rtlphy->reg_eb4;
1031 val_y = rtlphy->reg_ebc;
1032
1033 if (val_x != 0) {
1034 if ((val_x & 0x00000200) != 0)
1035 val_x = val_x | 0xFFFFFC00;
1036 ele_a = ((val_x * ele_d) >> 8) &
1037 0x000003FF;
1038
1039 if ((val_y & 0x00000200) != 0)
1040 val_y = val_y | 0xFFFFFC00;
1041 ele_c = ((val_y * ele_d) >> 8) &
1042 0x00003FF;
1043
1044 value32 = (ele_d << 22) |
1045 ((ele_c & 0x3F) << 16) | ele_a;
1046 rtl_set_bbreg(hw,
1047 ROFDM0_XBTXIQIMBALANCE,
1048 MASKDWORD, value32);
1049
1050 value32 = (ele_c & 0x000003C0) >> 6;
1051 rtl_set_bbreg(hw, ROFDM0_XDTXAFE,
1052 MASKH4BITS, value32);
1053
1054 value32 = ((val_x * ele_d) >> 7) & 0x01;
1055 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
1056 BIT(27), value32);
1057
1058 value32 = ((val_y * ele_d) >> 7) & 0x01;
1059 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
1060 BIT(25), value32);
1061 } else {
1062 rtl_set_bbreg(hw,
1063 ROFDM0_XBTXIQIMBALANCE,
1064 MASKDWORD,
1065 ofdmswing_table[ofdm_index
1066 [1]]);
1067 rtl_set_bbreg(hw, ROFDM0_XDTXAFE,
1068 MASKH4BITS, 0x00);
1069 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
1070 BIT(27) | BIT(25), 0x00);
1071 }
1072
1073 }
1074 }
1075
1076 if (delta_iqk > 3) {
1077 rtlpriv->dm.thermalvalue_iqk = thermalvalue;
1078 rtl92c_phy_iq_calibrate(hw, false);
1079 }
1080
1081 if (rtlpriv->dm.txpower_track_control)
1082 rtlpriv->dm.thermalvalue = thermalvalue;
1083 }
1084
1085 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, "<===\n");
1086
1087 }
1088
1089 static void rtl92c_dm_initialize_txpower_tracking_thermalmeter(
1090 struct ieee80211_hw *hw)
1091 {
1092 struct rtl_priv *rtlpriv = rtl_priv(hw);
1093
1094 rtlpriv->dm.txpower_tracking = true;
1095 rtlpriv->dm.txpower_trackinginit = false;
1096
1097 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1098 "pMgntInfo->txpower_tracking = %d\n",
1099 rtlpriv->dm.txpower_tracking);
1100 }
1101
1102 static void rtl92c_dm_initialize_txpower_tracking(struct ieee80211_hw *hw)
1103 {
1104 rtl92c_dm_initialize_txpower_tracking_thermalmeter(hw);
1105 }
1106
1107 static void rtl92c_dm_txpower_tracking_directcall(struct ieee80211_hw *hw)
1108 {
1109 rtl92c_dm_txpower_tracking_callback_thermalmeter(hw);
1110 }
1111
1112 static void rtl92c_dm_check_txpower_tracking_thermal_meter(
1113 struct ieee80211_hw *hw)
1114 {
1115 struct rtl_priv *rtlpriv = rtl_priv(hw);
1116 static u8 tm_trigger;
1117
1118 if (!rtlpriv->dm.txpower_tracking)
1119 return;
1120
1121 if (!tm_trigger) {
1122 rtl_set_rfreg(hw, RF90_PATH_A, RF_T_METER, RFREG_OFFSET_MASK,
1123 0x60);
1124 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1125 "Trigger 92S Thermal Meter!!\n");
1126 tm_trigger = 1;
1127 return;
1128 } else {
1129 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1130 "Schedule TxPowerTracking direct call!!\n");
1131 rtl92c_dm_txpower_tracking_directcall(hw);
1132 tm_trigger = 0;
1133 }
1134 }
1135
1136 void rtl92c_dm_check_txpower_tracking(struct ieee80211_hw *hw)
1137 {
1138 rtl92c_dm_check_txpower_tracking_thermal_meter(hw);
1139 }
1140 EXPORT_SYMBOL(rtl92c_dm_check_txpower_tracking);
1141
1142 void rtl92c_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw)
1143 {
1144 struct rtl_priv *rtlpriv = rtl_priv(hw);
1145 struct rate_adaptive *p_ra = &(rtlpriv->ra);
1146
1147 p_ra->ratr_state = DM_RATR_STA_INIT;
1148 p_ra->pre_ratr_state = DM_RATR_STA_INIT;
1149
1150 if (rtlpriv->dm.dm_type == DM_TYPE_BYDRIVER)
1151 rtlpriv->dm.useramask = true;
1152 else
1153 rtlpriv->dm.useramask = false;
1154
1155 }
1156 EXPORT_SYMBOL(rtl92c_dm_init_rate_adaptive_mask);
1157
1158 static void rtl92c_dm_refresh_rate_adaptive_mask(struct ieee80211_hw *hw)
1159 {
1160 struct rtl_priv *rtlpriv = rtl_priv(hw);
1161 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1162 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1163 struct rate_adaptive *p_ra = &(rtlpriv->ra);
1164 u32 low_rssithresh_for_ra, high_rssithresh_for_ra;
1165 struct ieee80211_sta *sta = NULL;
1166
1167 if (is_hal_stop(rtlhal)) {
1168 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
1169 "<---- driver is going to unload\n");
1170 return;
1171 }
1172
1173 if (!rtlpriv->dm.useramask) {
1174 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
1175 "<---- driver does not control rate adaptive mask\n");
1176 return;
1177 }
1178
1179 if (mac->link_state == MAC80211_LINKED &&
1180 mac->opmode == NL80211_IFTYPE_STATION) {
1181 switch (p_ra->pre_ratr_state) {
1182 case DM_RATR_STA_HIGH:
1183 high_rssithresh_for_ra = 50;
1184 low_rssithresh_for_ra = 20;
1185 break;
1186 case DM_RATR_STA_MIDDLE:
1187 high_rssithresh_for_ra = 55;
1188 low_rssithresh_for_ra = 20;
1189 break;
1190 case DM_RATR_STA_LOW:
1191 high_rssithresh_for_ra = 50;
1192 low_rssithresh_for_ra = 25;
1193 break;
1194 default:
1195 high_rssithresh_for_ra = 50;
1196 low_rssithresh_for_ra = 20;
1197 break;
1198 }
1199
1200 if (rtlpriv->dm.undecorated_smoothed_pwdb >
1201 (long)high_rssithresh_for_ra)
1202 p_ra->ratr_state = DM_RATR_STA_HIGH;
1203 else if (rtlpriv->dm.undecorated_smoothed_pwdb >
1204 (long)low_rssithresh_for_ra)
1205 p_ra->ratr_state = DM_RATR_STA_MIDDLE;
1206 else
1207 p_ra->ratr_state = DM_RATR_STA_LOW;
1208
1209 if (p_ra->pre_ratr_state != p_ra->ratr_state) {
1210 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD, "RSSI = %ld\n",
1211 rtlpriv->dm.undecorated_smoothed_pwdb);
1212 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
1213 "RSSI_LEVEL = %d\n", p_ra->ratr_state);
1214 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
1215 "PreState = %d, CurState = %d\n",
1216 p_ra->pre_ratr_state, p_ra->ratr_state);
1217
1218 /* Only the PCI card uses sta in the update rate table
1219 * callback routine */
1220 if (rtlhal->interface == INTF_PCI) {
1221 rcu_read_lock();
1222 sta = ieee80211_find_sta(mac->vif, mac->bssid);
1223 }
1224 rtlpriv->cfg->ops->update_rate_tbl(hw, sta,
1225 p_ra->ratr_state);
1226
1227 p_ra->pre_ratr_state = p_ra->ratr_state;
1228 if (rtlhal->interface == INTF_PCI)
1229 rcu_read_unlock();
1230 }
1231 }
1232 }
1233
1234 static void rtl92c_dm_init_dynamic_bb_powersaving(struct ieee80211_hw *hw)
1235 {
1236 struct rtl_priv *rtlpriv = rtl_priv(hw);
1237 struct ps_t *dm_pstable = &rtlpriv->dm_pstable;
1238
1239 dm_pstable->pre_ccastate = CCA_MAX;
1240 dm_pstable->cur_ccasate = CCA_MAX;
1241 dm_pstable->pre_rfstate = RF_MAX;
1242 dm_pstable->cur_rfstate = RF_MAX;
1243 dm_pstable->rssi_val_min = 0;
1244 }
1245
1246 void rtl92c_dm_rf_saving(struct ieee80211_hw *hw, u8 bforce_in_normal)
1247 {
1248 struct rtl_priv *rtlpriv = rtl_priv(hw);
1249 struct ps_t *dm_pstable = &rtlpriv->dm_pstable;
1250 static u8 initialize;
1251 static u32 reg_874, reg_c70, reg_85c, reg_a74;
1252
1253 if (initialize == 0) {
1254 reg_874 = (rtl_get_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
1255 MASKDWORD) & 0x1CC000) >> 14;
1256
1257 reg_c70 = (rtl_get_bbreg(hw, ROFDM0_AGCPARAMETER1,
1258 MASKDWORD) & BIT(3)) >> 3;
1259
1260 reg_85c = (rtl_get_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL,
1261 MASKDWORD) & 0xFF000000) >> 24;
1262
1263 reg_a74 = (rtl_get_bbreg(hw, 0xa74, MASKDWORD) & 0xF000) >> 12;
1264
1265 initialize = 1;
1266 }
1267
1268 if (!bforce_in_normal) {
1269 if (dm_pstable->rssi_val_min != 0) {
1270 if (dm_pstable->pre_rfstate == RF_NORMAL) {
1271 if (dm_pstable->rssi_val_min >= 30)
1272 dm_pstable->cur_rfstate = RF_SAVE;
1273 else
1274 dm_pstable->cur_rfstate = RF_NORMAL;
1275 } else {
1276 if (dm_pstable->rssi_val_min <= 25)
1277 dm_pstable->cur_rfstate = RF_NORMAL;
1278 else
1279 dm_pstable->cur_rfstate = RF_SAVE;
1280 }
1281 } else {
1282 dm_pstable->cur_rfstate = RF_MAX;
1283 }
1284 } else {
1285 dm_pstable->cur_rfstate = RF_NORMAL;
1286 }
1287
1288 if (dm_pstable->pre_rfstate != dm_pstable->cur_rfstate) {
1289 if (dm_pstable->cur_rfstate == RF_SAVE) {
1290 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
1291 0x1C0000, 0x2);
1292 rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, BIT(3), 0);
1293 rtl_set_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL,
1294 0xFF000000, 0x63);
1295 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
1296 0xC000, 0x2);
1297 rtl_set_bbreg(hw, 0xa74, 0xF000, 0x3);
1298 rtl_set_bbreg(hw, 0x818, BIT(28), 0x0);
1299 rtl_set_bbreg(hw, 0x818, BIT(28), 0x1);
1300 } else {
1301 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
1302 0x1CC000, reg_874);
1303 rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, BIT(3),
1304 reg_c70);
1305 rtl_set_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL, 0xFF000000,
1306 reg_85c);
1307 rtl_set_bbreg(hw, 0xa74, 0xF000, reg_a74);
1308 rtl_set_bbreg(hw, 0x818, BIT(28), 0x0);
1309 }
1310
1311 dm_pstable->pre_rfstate = dm_pstable->cur_rfstate;
1312 }
1313 }
1314 EXPORT_SYMBOL(rtl92c_dm_rf_saving);
1315
1316 static void rtl92c_dm_dynamic_bb_powersaving(struct ieee80211_hw *hw)
1317 {
1318 struct rtl_priv *rtlpriv = rtl_priv(hw);
1319 struct ps_t *dm_pstable = &rtlpriv->dm_pstable;
1320 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1321 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1322
1323 if (((mac->link_state == MAC80211_NOLINK)) &&
1324 (rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb == 0)) {
1325 dm_pstable->rssi_val_min = 0;
1326 RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD, "Not connected to any\n");
1327 }
1328
1329 if (mac->link_state == MAC80211_LINKED) {
1330 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
1331 dm_pstable->rssi_val_min =
1332 rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
1333 RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
1334 "AP Client PWDB = 0x%lx\n",
1335 dm_pstable->rssi_val_min);
1336 } else {
1337 dm_pstable->rssi_val_min =
1338 rtlpriv->dm.undecorated_smoothed_pwdb;
1339 RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
1340 "STA Default Port PWDB = 0x%lx\n",
1341 dm_pstable->rssi_val_min);
1342 }
1343 } else {
1344 dm_pstable->rssi_val_min =
1345 rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
1346
1347 RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
1348 "AP Ext Port PWDB = 0x%lx\n",
1349 dm_pstable->rssi_val_min);
1350 }
1351
1352 if (IS_92C_SERIAL(rtlhal->version))
1353 ;/* rtl92c_dm_1r_cca(hw); */
1354 else
1355 rtl92c_dm_rf_saving(hw, false);
1356 }
1357
1358 void rtl92c_dm_init(struct ieee80211_hw *hw)
1359 {
1360 struct rtl_priv *rtlpriv = rtl_priv(hw);
1361
1362 rtlpriv->dm.dm_type = DM_TYPE_BYDRIVER;
1363 rtl92c_dm_diginit(hw);
1364 rtl92c_dm_init_dynamic_txpower(hw);
1365 rtl92c_dm_init_edca_turbo(hw);
1366 rtl92c_dm_init_rate_adaptive_mask(hw);
1367 rtl92c_dm_initialize_txpower_tracking(hw);
1368 rtl92c_dm_init_dynamic_bb_powersaving(hw);
1369 }
1370 EXPORT_SYMBOL(rtl92c_dm_init);
1371
1372 void rtl92c_dm_dynamic_txpower(struct ieee80211_hw *hw)
1373 {
1374 struct rtl_priv *rtlpriv = rtl_priv(hw);
1375 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1376 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1377 long undecorated_smoothed_pwdb;
1378
1379 if (!rtlpriv->dm.dynamic_txpower_enable)
1380 return;
1381
1382 if (rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) {
1383 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
1384 return;
1385 }
1386
1387 if ((mac->link_state < MAC80211_LINKED) &&
1388 (rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb == 0)) {
1389 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
1390 "Not connected to any\n");
1391
1392 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
1393
1394 rtlpriv->dm.last_dtp_lvl = TXHIGHPWRLEVEL_NORMAL;
1395 return;
1396 }
1397
1398 if (mac->link_state >= MAC80211_LINKED) {
1399 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
1400 undecorated_smoothed_pwdb =
1401 rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
1402 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
1403 "AP Client PWDB = 0x%lx\n",
1404 undecorated_smoothed_pwdb);
1405 } else {
1406 undecorated_smoothed_pwdb =
1407 rtlpriv->dm.undecorated_smoothed_pwdb;
1408 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
1409 "STA Default Port PWDB = 0x%lx\n",
1410 undecorated_smoothed_pwdb);
1411 }
1412 } else {
1413 undecorated_smoothed_pwdb =
1414 rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
1415
1416 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
1417 "AP Ext Port PWDB = 0x%lx\n",
1418 undecorated_smoothed_pwdb);
1419 }
1420
1421 if (undecorated_smoothed_pwdb >= TX_POWER_NEAR_FIELD_THRESH_LVL2) {
1422 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_LEVEL1;
1423 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
1424 "TXHIGHPWRLEVEL_LEVEL1 (TxPwr=0x0)\n");
1425 } else if ((undecorated_smoothed_pwdb <
1426 (TX_POWER_NEAR_FIELD_THRESH_LVL2 - 3)) &&
1427 (undecorated_smoothed_pwdb >=
1428 TX_POWER_NEAR_FIELD_THRESH_LVL1)) {
1429
1430 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_LEVEL1;
1431 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
1432 "TXHIGHPWRLEVEL_LEVEL1 (TxPwr=0x10)\n");
1433 } else if (undecorated_smoothed_pwdb <
1434 (TX_POWER_NEAR_FIELD_THRESH_LVL1 - 5)) {
1435 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
1436 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
1437 "TXHIGHPWRLEVEL_NORMAL\n");
1438 }
1439
1440 if ((rtlpriv->dm.dynamic_txhighpower_lvl != rtlpriv->dm.last_dtp_lvl)) {
1441 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
1442 "PHY_SetTxPowerLevel8192S() Channel = %d\n",
1443 rtlphy->current_channel);
1444 rtl92c_phy_set_txpower_level(hw, rtlphy->current_channel);
1445 }
1446
1447 rtlpriv->dm.last_dtp_lvl = rtlpriv->dm.dynamic_txhighpower_lvl;
1448 }
1449
1450 void rtl92c_dm_watchdog(struct ieee80211_hw *hw)
1451 {
1452 struct rtl_priv *rtlpriv = rtl_priv(hw);
1453 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1454 bool fw_current_inpsmode = false;
1455 bool fw_ps_awake = true;
1456
1457 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
1458 (u8 *) (&fw_current_inpsmode));
1459 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FWLPS_RF_ON,
1460 (u8 *) (&fw_ps_awake));
1461
1462 if ((ppsc->rfpwr_state == ERFON) && ((!fw_current_inpsmode) &&
1463 fw_ps_awake)
1464 && (!ppsc->rfchange_inprogress)) {
1465 rtl92c_dm_pwdb_monitor(hw);
1466 rtl92c_dm_dig(hw);
1467 rtl92c_dm_false_alarm_counter_statistics(hw);
1468 rtl92c_dm_dynamic_bb_powersaving(hw);
1469 rtl92c_dm_dynamic_txpower(hw);
1470 rtl92c_dm_check_txpower_tracking(hw);
1471 rtl92c_dm_refresh_rate_adaptive_mask(hw);
1472 rtl92c_dm_bt_coexist(hw);
1473 rtl92c_dm_check_edca_turbo(hw);
1474 }
1475 }
1476 EXPORT_SYMBOL(rtl92c_dm_watchdog);
1477
1478 u8 rtl92c_bt_rssi_state_change(struct ieee80211_hw *hw)
1479 {
1480 struct rtl_priv *rtlpriv = rtl_priv(hw);
1481 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1482 long undecorated_smoothed_pwdb;
1483 u8 curr_bt_rssi_state = 0x00;
1484
1485 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1486 undecorated_smoothed_pwdb =
1487 GET_UNDECORATED_AVERAGE_RSSI(rtlpriv);
1488 } else {
1489 if (rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb == 0)
1490 undecorated_smoothed_pwdb = 100;
1491 else
1492 undecorated_smoothed_pwdb =
1493 rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
1494 }
1495
1496 /* Check RSSI to determine HighPower/NormalPower state for
1497 * BT coexistence. */
1498 if (undecorated_smoothed_pwdb >= 67)
1499 curr_bt_rssi_state &= (~BT_RSSI_STATE_NORMAL_POWER);
1500 else if (undecorated_smoothed_pwdb < 62)
1501 curr_bt_rssi_state |= BT_RSSI_STATE_NORMAL_POWER;
1502
1503 /* Check RSSI to determine AMPDU setting for BT coexistence. */
1504 if (undecorated_smoothed_pwdb >= 40)
1505 curr_bt_rssi_state &= (~BT_RSSI_STATE_AMDPU_OFF);
1506 else if (undecorated_smoothed_pwdb <= 32)
1507 curr_bt_rssi_state |= BT_RSSI_STATE_AMDPU_OFF;
1508
1509 /* Marked RSSI state. It will be used to determine BT coexistence
1510 * setting later. */
1511 if (undecorated_smoothed_pwdb < 35)
1512 curr_bt_rssi_state |= BT_RSSI_STATE_SPECIAL_LOW;
1513 else
1514 curr_bt_rssi_state &= (~BT_RSSI_STATE_SPECIAL_LOW);
1515
1516 /* Set Tx Power according to BT status. */
1517 if (undecorated_smoothed_pwdb >= 30)
1518 curr_bt_rssi_state |= BT_RSSI_STATE_TXPOWER_LOW;
1519 else if (undecorated_smoothed_pwdb < 25)
1520 curr_bt_rssi_state &= (~BT_RSSI_STATE_TXPOWER_LOW);
1521
1522 /* Check BT state related to BT_Idle in B/G mode. */
1523 if (undecorated_smoothed_pwdb < 15)
1524 curr_bt_rssi_state |= BT_RSSI_STATE_BG_EDCA_LOW;
1525 else
1526 curr_bt_rssi_state &= (~BT_RSSI_STATE_BG_EDCA_LOW);
1527
1528 if (curr_bt_rssi_state != rtlpcipriv->bt_coexist.bt_rssi_state) {
1529 rtlpcipriv->bt_coexist.bt_rssi_state = curr_bt_rssi_state;
1530 return true;
1531 } else {
1532 return false;
1533 }
1534 }
1535 EXPORT_SYMBOL(rtl92c_bt_rssi_state_change);
1536
1537 static bool rtl92c_bt_state_change(struct ieee80211_hw *hw)
1538 {
1539 struct rtl_priv *rtlpriv = rtl_priv(hw);
1540 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1541
1542 u32 polling, ratio_tx, ratio_pri;
1543 u32 bt_tx, bt_pri;
1544 u8 bt_state;
1545 u8 cur_service_type;
1546
1547 if (rtlpriv->mac80211.link_state < MAC80211_LINKED)
1548 return false;
1549
1550 bt_state = rtl_read_byte(rtlpriv, 0x4fd);
1551 bt_tx = rtl_read_dword(rtlpriv, 0x488);
1552 bt_tx = bt_tx & 0x00ffffff;
1553 bt_pri = rtl_read_dword(rtlpriv, 0x48c);
1554 bt_pri = bt_pri & 0x00ffffff;
1555 polling = rtl_read_dword(rtlpriv, 0x490);
1556
1557 if (bt_tx == 0xffffffff && bt_pri == 0xffffffff &&
1558 polling == 0xffffffff && bt_state == 0xff)
1559 return false;
1560
1561 bt_state &= BIT_OFFSET_LEN_MASK_32(0, 1);
1562 if (bt_state != rtlpcipriv->bt_coexist.bt_cur_state) {
1563 rtlpcipriv->bt_coexist.bt_cur_state = bt_state;
1564
1565 if (rtlpcipriv->bt_coexist.reg_bt_sco == 3) {
1566 rtlpcipriv->bt_coexist.bt_service = BT_IDLE;
1567
1568 bt_state = bt_state |
1569 ((rtlpcipriv->bt_coexist.bt_ant_isolation == 1) ?
1570 0 : BIT_OFFSET_LEN_MASK_32(1, 1)) |
1571 BIT_OFFSET_LEN_MASK_32(2, 1);
1572 rtl_write_byte(rtlpriv, 0x4fd, bt_state);
1573 }
1574 return true;
1575 }
1576
1577 ratio_tx = bt_tx * 1000 / polling;
1578 ratio_pri = bt_pri * 1000 / polling;
1579 rtlpcipriv->bt_coexist.ratio_tx = ratio_tx;
1580 rtlpcipriv->bt_coexist.ratio_pri = ratio_pri;
1581
1582 if (bt_state && rtlpcipriv->bt_coexist.reg_bt_sco == 3) {
1583
1584 if ((ratio_tx < 30) && (ratio_pri < 30))
1585 cur_service_type = BT_IDLE;
1586 else if ((ratio_pri > 110) && (ratio_pri < 250))
1587 cur_service_type = BT_SCO;
1588 else if ((ratio_tx >= 200) && (ratio_pri >= 200))
1589 cur_service_type = BT_BUSY;
1590 else if ((ratio_tx >= 350) && (ratio_tx < 500))
1591 cur_service_type = BT_OTHERBUSY;
1592 else if (ratio_tx >= 500)
1593 cur_service_type = BT_PAN;
1594 else
1595 cur_service_type = BT_OTHER_ACTION;
1596
1597 if (cur_service_type != rtlpcipriv->bt_coexist.bt_service) {
1598 rtlpcipriv->bt_coexist.bt_service = cur_service_type;
1599 bt_state = bt_state |
1600 ((rtlpcipriv->bt_coexist.bt_ant_isolation == 1) ?
1601 0 : BIT_OFFSET_LEN_MASK_32(1, 1)) |
1602 ((rtlpcipriv->bt_coexist.bt_service != BT_IDLE) ?
1603 0 : BIT_OFFSET_LEN_MASK_32(2, 1));
1604
1605 /* Add interrupt migration when bt is not ini
1606 * idle state (no traffic). */
1607 if (rtlpcipriv->bt_coexist.bt_service != BT_IDLE) {
1608 rtl_write_word(rtlpriv, 0x504, 0x0ccc);
1609 rtl_write_byte(rtlpriv, 0x506, 0x54);
1610 rtl_write_byte(rtlpriv, 0x507, 0x54);
1611 } else {
1612 rtl_write_byte(rtlpriv, 0x506, 0x00);
1613 rtl_write_byte(rtlpriv, 0x507, 0x00);
1614 }
1615
1616 rtl_write_byte(rtlpriv, 0x4fd, bt_state);
1617 return true;
1618 }
1619 }
1620
1621 return false;
1622
1623 }
1624
1625 static bool rtl92c_bt_wifi_connect_change(struct ieee80211_hw *hw)
1626 {
1627 struct rtl_priv *rtlpriv = rtl_priv(hw);
1628 static bool media_connect;
1629
1630 if (rtlpriv->mac80211.link_state < MAC80211_LINKED) {
1631 media_connect = false;
1632 } else {
1633 if (!media_connect) {
1634 media_connect = true;
1635 return true;
1636 }
1637 media_connect = true;
1638 }
1639
1640 return false;
1641 }
1642
1643 static void rtl92c_bt_set_normal(struct ieee80211_hw *hw)
1644 {
1645 struct rtl_priv *rtlpriv = rtl_priv(hw);
1646 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1647
1648
1649 if (rtlpcipriv->bt_coexist.bt_service == BT_OTHERBUSY) {
1650 rtlpcipriv->bt_coexist.bt_edca_ul = 0x5ea72b;
1651 rtlpcipriv->bt_coexist.bt_edca_dl = 0x5ea72b;
1652 } else if (rtlpcipriv->bt_coexist.bt_service == BT_BUSY) {
1653 rtlpcipriv->bt_coexist.bt_edca_ul = 0x5eb82f;
1654 rtlpcipriv->bt_coexist.bt_edca_dl = 0x5eb82f;
1655 } else if (rtlpcipriv->bt_coexist.bt_service == BT_SCO) {
1656 if (rtlpcipriv->bt_coexist.ratio_tx > 160) {
1657 rtlpcipriv->bt_coexist.bt_edca_ul = 0x5ea72f;
1658 rtlpcipriv->bt_coexist.bt_edca_dl = 0x5ea72f;
1659 } else {
1660 rtlpcipriv->bt_coexist.bt_edca_ul = 0x5ea32b;
1661 rtlpcipriv->bt_coexist.bt_edca_dl = 0x5ea42b;
1662 }
1663 } else {
1664 rtlpcipriv->bt_coexist.bt_edca_ul = 0;
1665 rtlpcipriv->bt_coexist.bt_edca_dl = 0;
1666 }
1667
1668 if ((rtlpcipriv->bt_coexist.bt_service != BT_IDLE) &&
1669 (rtlpriv->mac80211.mode == WIRELESS_MODE_G ||
1670 (rtlpriv->mac80211.mode == (WIRELESS_MODE_G | WIRELESS_MODE_B))) &&
1671 (rtlpcipriv->bt_coexist.bt_rssi_state &
1672 BT_RSSI_STATE_BG_EDCA_LOW)) {
1673 rtlpcipriv->bt_coexist.bt_edca_ul = 0x5eb82b;
1674 rtlpcipriv->bt_coexist.bt_edca_dl = 0x5eb82b;
1675 }
1676 }
1677
1678 static void rtl92c_bt_ant_isolation(struct ieee80211_hw *hw)
1679 {
1680 struct rtl_priv *rtlpriv = rtl_priv(hw);
1681 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1682
1683
1684 /* Only enable HW BT coexist when BT in "Busy" state. */
1685 if (rtlpriv->mac80211.vendor == PEER_CISCO &&
1686 rtlpcipriv->bt_coexist.bt_service == BT_OTHER_ACTION) {
1687 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0);
1688 } else {
1689 if ((rtlpcipriv->bt_coexist.bt_service == BT_BUSY) &&
1690 (rtlpcipriv->bt_coexist.bt_rssi_state &
1691 BT_RSSI_STATE_NORMAL_POWER)) {
1692 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0);
1693 } else if ((rtlpcipriv->bt_coexist.bt_service ==
1694 BT_OTHER_ACTION) && (rtlpriv->mac80211.mode <
1695 WIRELESS_MODE_N_24G) &&
1696 (rtlpcipriv->bt_coexist.bt_rssi_state &
1697 BT_RSSI_STATE_SPECIAL_LOW)) {
1698 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0);
1699 } else if (rtlpcipriv->bt_coexist.bt_service == BT_PAN) {
1700 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0x00);
1701 } else {
1702 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0x00);
1703 }
1704 }
1705
1706 if (rtlpcipriv->bt_coexist.bt_service == BT_PAN)
1707 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x10100);
1708 else
1709 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x0);
1710
1711 if (rtlpcipriv->bt_coexist.bt_rssi_state &
1712 BT_RSSI_STATE_NORMAL_POWER) {
1713 rtl92c_bt_set_normal(hw);
1714 } else {
1715 rtlpcipriv->bt_coexist.bt_edca_ul = 0;
1716 rtlpcipriv->bt_coexist.bt_edca_dl = 0;
1717 }
1718
1719 if (rtlpcipriv->bt_coexist.bt_service != BT_IDLE) {
1720 rtlpriv->cfg->ops->set_rfreg(hw,
1721 RF90_PATH_A,
1722 0x1e,
1723 0xf0, 0xf);
1724 } else {
1725 rtlpriv->cfg->ops->set_rfreg(hw,
1726 RF90_PATH_A, 0x1e, 0xf0,
1727 rtlpcipriv->bt_coexist.bt_rfreg_origin_1e);
1728 }
1729
1730 if (!rtlpriv->dm.dynamic_txpower_enable) {
1731 if (rtlpcipriv->bt_coexist.bt_service != BT_IDLE) {
1732 if (rtlpcipriv->bt_coexist.bt_rssi_state &
1733 BT_RSSI_STATE_TXPOWER_LOW) {
1734 rtlpriv->dm.dynamic_txhighpower_lvl =
1735 TXHIGHPWRLEVEL_BT2;
1736 } else {
1737 rtlpriv->dm.dynamic_txhighpower_lvl =
1738 TXHIGHPWRLEVEL_BT1;
1739 }
1740 } else {
1741 rtlpriv->dm.dynamic_txhighpower_lvl =
1742 TXHIGHPWRLEVEL_NORMAL;
1743 }
1744 rtl92c_phy_set_txpower_level(hw,
1745 rtlpriv->phy.current_channel);
1746 }
1747 }
1748
1749 static void rtl92c_check_bt_change(struct ieee80211_hw *hw)
1750 {
1751 struct rtl_priv *rtlpriv = rtl_priv(hw);
1752 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1753
1754 if (rtlpcipriv->bt_coexist.bt_cur_state) {
1755 if (rtlpcipriv->bt_coexist.bt_ant_isolation)
1756 rtl92c_bt_ant_isolation(hw);
1757 } else {
1758 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0x00);
1759 rtlpriv->cfg->ops->set_rfreg(hw, RF90_PATH_A, 0x1e, 0xf0,
1760 rtlpcipriv->bt_coexist.bt_rfreg_origin_1e);
1761
1762 rtlpcipriv->bt_coexist.bt_edca_ul = 0;
1763 rtlpcipriv->bt_coexist.bt_edca_dl = 0;
1764 }
1765 }
1766
1767 void rtl92c_dm_bt_coexist(struct ieee80211_hw *hw)
1768 {
1769 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1770
1771 bool wifi_connect_change;
1772 bool bt_state_change;
1773 bool rssi_state_change;
1774
1775 if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
1776 (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4)) {
1777
1778 wifi_connect_change = rtl92c_bt_wifi_connect_change(hw);
1779 bt_state_change = rtl92c_bt_state_change(hw);
1780 rssi_state_change = rtl92c_bt_rssi_state_change(hw);
1781
1782 if (wifi_connect_change || bt_state_change || rssi_state_change)
1783 rtl92c_check_bt_change(hw);
1784 }
1785 }
1786 EXPORT_SYMBOL(rtl92c_dm_bt_coexist);
Linux kernel - Deliverables
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