projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge branch 'fortglx/3.15/time' of git://git.linaro.org/people/john.stultz/linux...
[deliverable/linux.git] / drivers / net / wireless / rtlwifi / rtl8192c / phy_common.c
1 /******************************************************************************
2 *
3 * Copyright(c) 2009-2012 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30 #include <linux/export.h>
31 #include "../wifi.h"
32 #include "../rtl8192ce/reg.h"
33 #include "../rtl8192ce/def.h"
34 #include "dm_common.h"
35 #include "phy_common.h"
36
37 u32 rtl92c_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask)
38 {
39 struct rtl_priv *rtlpriv = rtl_priv(hw);
40 u32 returnvalue, originalvalue, bitshift;
41
42 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "regaddr(%#x), bitmask(%#x)\n",
43 regaddr, bitmask);
44 originalvalue = rtl_read_dword(rtlpriv, regaddr);
45 bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
46 returnvalue = (originalvalue & bitmask) >> bitshift;
47
48 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
49 "BBR MASK=0x%x Addr[0x%x]=0x%x\n",
50 bitmask, regaddr, originalvalue);
51
52 return returnvalue;
53
54 }
55 EXPORT_SYMBOL(rtl92c_phy_query_bb_reg);
56
57 void rtl92c_phy_set_bb_reg(struct ieee80211_hw *hw,
58 u32 regaddr, u32 bitmask, u32 data)
59 {
60 struct rtl_priv *rtlpriv = rtl_priv(hw);
61 u32 originalvalue, bitshift;
62
63 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
64 "regaddr(%#x), bitmask(%#x), data(%#x)\n",
65 regaddr, bitmask, data);
66
67 if (bitmask != MASKDWORD) {
68 originalvalue = rtl_read_dword(rtlpriv, regaddr);
69 bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
70 data = ((originalvalue & (~bitmask)) | (data << bitshift));
71 }
72
73 rtl_write_dword(rtlpriv, regaddr, data);
74
75 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
76 "regaddr(%#x), bitmask(%#x), data(%#x)\n",
77 regaddr, bitmask, data);
78
79 }
80 EXPORT_SYMBOL(rtl92c_phy_set_bb_reg);
81
82 u32 _rtl92c_phy_fw_rf_serial_read(struct ieee80211_hw *hw,
83 enum radio_path rfpath, u32 offset)
84 {
85 RT_ASSERT(false, "deprecated!\n");
86 return 0;
87
88 }
89 EXPORT_SYMBOL(_rtl92c_phy_fw_rf_serial_read);
90
91 void _rtl92c_phy_fw_rf_serial_write(struct ieee80211_hw *hw,
92 enum radio_path rfpath, u32 offset,
93 u32 data)
94 {
95 RT_ASSERT(false, "deprecated!\n");
96 }
97 EXPORT_SYMBOL(_rtl92c_phy_fw_rf_serial_write);
98
99 u32 _rtl92c_phy_rf_serial_read(struct ieee80211_hw *hw,
100 enum radio_path rfpath, u32 offset)
101 {
102 struct rtl_priv *rtlpriv = rtl_priv(hw);
103 struct rtl_phy *rtlphy = &(rtlpriv->phy);
104 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
105 u32 newoffset;
106 u32 tmplong, tmplong2;
107 u8 rfpi_enable = 0;
108 u32 retvalue;
109
110 offset &= 0x3f;
111 newoffset = offset;
112 if (RT_CANNOT_IO(hw)) {
113 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "return all one\n");
114 return 0xFFFFFFFF;
115 }
116 tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD);
117 if (rfpath == RF90_PATH_A)
118 tmplong2 = tmplong;
119 else
120 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD);
121 tmplong2 = (tmplong2 & (~BLSSIREADADDRESS)) |
122 (newoffset << 23) | BLSSIREADEDGE;
123 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
124 tmplong & (~BLSSIREADEDGE));
125 mdelay(1);
126 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2);
127 mdelay(1);
128 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
129 tmplong | BLSSIREADEDGE);
130 mdelay(1);
131 if (rfpath == RF90_PATH_A)
132 rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,
133 BIT(8));
134 else if (rfpath == RF90_PATH_B)
135 rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1,
136 BIT(8));
137 if (rfpi_enable)
138 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rbpi,
139 BLSSIREADBACKDATA);
140 else
141 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb,
142 BLSSIREADBACKDATA);
143 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFR-%d Addr[0x%x]=0x%x\n",
144 rfpath, pphyreg->rf_rb, retvalue);
145 return retvalue;
146 }
147 EXPORT_SYMBOL(_rtl92c_phy_rf_serial_read);
148
149 void _rtl92c_phy_rf_serial_write(struct ieee80211_hw *hw,
150 enum radio_path rfpath, u32 offset,
151 u32 data)
152 {
153 u32 data_and_addr;
154 u32 newoffset;
155 struct rtl_priv *rtlpriv = rtl_priv(hw);
156 struct rtl_phy *rtlphy = &(rtlpriv->phy);
157 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
158
159 if (RT_CANNOT_IO(hw)) {
160 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "stop\n");
161 return;
162 }
163 offset &= 0x3f;
164 newoffset = offset;
165 data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff;
166 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);
167 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFW-%d Addr[0x%x]=0x%x\n",
168 rfpath, pphyreg->rf3wire_offset, data_and_addr);
169 }
170 EXPORT_SYMBOL(_rtl92c_phy_rf_serial_write);
171
172 u32 _rtl92c_phy_calculate_bit_shift(u32 bitmask)
173 {
174 u32 i;
175
176 for (i = 0; i <= 31; i++) {
177 if ((bitmask >> i) & 0x1)
178 break;
179 }
180 return i;
181 }
182 EXPORT_SYMBOL(_rtl92c_phy_calculate_bit_shift);
183
184 static void _rtl92c_phy_bb_config_1t(struct ieee80211_hw *hw)
185 {
186 rtl_set_bbreg(hw, RFPGA0_TXINFO, 0x3, 0x2);
187 rtl_set_bbreg(hw, RFPGA1_TXINFO, 0x300033, 0x200022);
188 rtl_set_bbreg(hw, RCCK0_AFESETTING, MASKBYTE3, 0x45);
189 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x23);
190 rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, 0x30, 0x1);
191 rtl_set_bbreg(hw, 0xe74, 0x0c000000, 0x2);
192 rtl_set_bbreg(hw, 0xe78, 0x0c000000, 0x2);
193 rtl_set_bbreg(hw, 0xe7c, 0x0c000000, 0x2);
194 rtl_set_bbreg(hw, 0xe80, 0x0c000000, 0x2);
195 rtl_set_bbreg(hw, 0xe88, 0x0c000000, 0x2);
196 }
197
198 bool rtl92c_phy_rf_config(struct ieee80211_hw *hw)
199 {
200 struct rtl_priv *rtlpriv = rtl_priv(hw);
201
202 return rtlpriv->cfg->ops->phy_rf6052_config(hw);
203 }
204 EXPORT_SYMBOL(rtl92c_phy_rf_config);
205
206 bool _rtl92c_phy_bb8192c_config_parafile(struct ieee80211_hw *hw)
207 {
208 struct rtl_priv *rtlpriv = rtl_priv(hw);
209 struct rtl_phy *rtlphy = &(rtlpriv->phy);
210 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
211 bool rtstatus;
212
213 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "==>\n");
214 rtstatus = rtlpriv->cfg->ops->config_bb_with_headerfile(hw,
215 BASEBAND_CONFIG_PHY_REG);
216 if (!rtstatus) {
217 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Write BB Reg Fail!!\n");
218 return false;
219 }
220 if (rtlphy->rf_type == RF_1T2R) {
221 _rtl92c_phy_bb_config_1t(hw);
222 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Config to 1T!!\n");
223 }
224 if (rtlefuse->autoload_failflag == false) {
225 rtlphy->pwrgroup_cnt = 0;
226 rtstatus = rtlpriv->cfg->ops->config_bb_with_pgheaderfile(hw,
227 BASEBAND_CONFIG_PHY_REG);
228 }
229 if (!rtstatus) {
230 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "BB_PG Reg Fail!!\n");
231 return false;
232 }
233 rtstatus = rtlpriv->cfg->ops->config_bb_with_headerfile(hw,
234 BASEBAND_CONFIG_AGC_TAB);
235 if (!rtstatus) {
236 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "AGC Table Fail\n");
237 return false;
238 }
239 rtlphy->cck_high_power = (bool) (rtl_get_bbreg(hw,
240 RFPGA0_XA_HSSIPARAMETER2,
241 0x200));
242
243 return true;
244 }
245 EXPORT_SYMBOL(_rtl92c_phy_bb8192c_config_parafile);
246
247 void _rtl92c_store_pwrIndex_diffrate_offset(struct ieee80211_hw *hw,
248 u32 regaddr, u32 bitmask,
249 u32 data)
250 {
251 struct rtl_priv *rtlpriv = rtl_priv(hw);
252 struct rtl_phy *rtlphy = &(rtlpriv->phy);
253 int index;
254
255 if (regaddr == RTXAGC_A_RATE18_06)
256 index = 0;
257 else if (regaddr == RTXAGC_A_RATE54_24)
258 index = 1;
259 else if (regaddr == RTXAGC_A_CCK1_MCS32)
260 index = 6;
261 else if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00)
262 index = 7;
263 else if (regaddr == RTXAGC_A_MCS03_MCS00)
264 index = 2;
265 else if (regaddr == RTXAGC_A_MCS07_MCS04)
266 index = 3;
267 else if (regaddr == RTXAGC_A_MCS11_MCS08)
268 index = 4;
269 else if (regaddr == RTXAGC_A_MCS15_MCS12)
270 index = 5;
271 else if (regaddr == RTXAGC_B_RATE18_06)
272 index = 8;
273 else if (regaddr == RTXAGC_B_RATE54_24)
274 index = 9;
275 else if (regaddr == RTXAGC_B_CCK1_55_MCS32)
276 index = 14;
277 else if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff)
278 index = 15;
279 else if (regaddr == RTXAGC_B_MCS03_MCS00)
280 index = 10;
281 else if (regaddr == RTXAGC_B_MCS07_MCS04)
282 index = 11;
283 else if (regaddr == RTXAGC_B_MCS11_MCS08)
284 index = 12;
285 else if (regaddr == RTXAGC_B_MCS15_MCS12)
286 index = 13;
287 else
288 return;
289
290 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][index] = data;
291 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
292 "MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n",
293 rtlphy->pwrgroup_cnt, index,
294 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][index]);
295
296 if (index == 13)
297 rtlphy->pwrgroup_cnt++;
298 }
299 EXPORT_SYMBOL(_rtl92c_store_pwrIndex_diffrate_offset);
300
301 void rtl92c_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
302 {
303 struct rtl_priv *rtlpriv = rtl_priv(hw);
304 struct rtl_phy *rtlphy = &(rtlpriv->phy);
305
306 rtlphy->default_initialgain[0] =
307 (u8) rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0);
308 rtlphy->default_initialgain[1] =
309 (u8) rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0);
310 rtlphy->default_initialgain[2] =
311 (u8) rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0);
312 rtlphy->default_initialgain[3] =
313 (u8) rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0);
314
315 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
316 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n",
317 rtlphy->default_initialgain[0],
318 rtlphy->default_initialgain[1],
319 rtlphy->default_initialgain[2],
320 rtlphy->default_initialgain[3]);
321
322 rtlphy->framesync = (u8) rtl_get_bbreg(hw,
323 ROFDM0_RXDETECTOR3, MASKBYTE0);
324 rtlphy->framesync_c34 = rtl_get_bbreg(hw,
325 ROFDM0_RXDETECTOR2, MASKDWORD);
326
327 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
328 "Default framesync (0x%x) = 0x%x\n",
329 ROFDM0_RXDETECTOR3, rtlphy->framesync);
330 }
331
332 void _rtl92c_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw)
333 {
334 struct rtl_priv *rtlpriv = rtl_priv(hw);
335 struct rtl_phy *rtlphy = &(rtlpriv->phy);
336
337 rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;
338 rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;
339 rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW;
340 rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW;
341
342 rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB;
343 rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB;
344 rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB;
345 rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB;
346
347 rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE;
348 rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;
349
350 rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE;
351 rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;
352
353 rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset =
354 RFPGA0_XA_LSSIPARAMETER;
355 rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset =
356 RFPGA0_XB_LSSIPARAMETER;
357
358 rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = rFPGA0_XAB_RFPARAMETER;
359 rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = rFPGA0_XAB_RFPARAMETER;
360 rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = rFPGA0_XCD_RFPARAMETER;
361 rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = rFPGA0_XCD_RFPARAMETER;
362
363 rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE;
364 rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE;
365 rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE;
366 rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE;
367
368 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1;
369 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1;
370
371 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2;
372 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2;
373
374 rtlphy->phyreg_def[RF90_PATH_A].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;
375 rtlphy->phyreg_def[RF90_PATH_B].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;
376 rtlphy->phyreg_def[RF90_PATH_C].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;
377 rtlphy->phyreg_def[RF90_PATH_D].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;
378
379 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1;
380 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1;
381 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1;
382 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1;
383
384 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2;
385 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2;
386 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2;
387 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2;
388
389 rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbal = ROFDM0_XARXIQIMBALANCE;
390 rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbal = ROFDM0_XBRXIQIMBALANCE;
391 rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbal = ROFDM0_XCRXIQIMBANLANCE;
392 rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbal = ROFDM0_XDRXIQIMBALANCE;
393
394 rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE;
395 rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE;
396 rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE;
397 rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE;
398
399 rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbal = ROFDM0_XATXIQIMBALANCE;
400 rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbal = ROFDM0_XBTXIQIMBALANCE;
401 rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbal = ROFDM0_XCTXIQIMBALANCE;
402 rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTXIQIMBALANCE;
403
404 rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATXAFE;
405 rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTXAFE;
406 rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTXAFE;
407 rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTXAFE;
408
409 rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK;
410 rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK;
411 rtlphy->phyreg_def[RF90_PATH_C].rf_rb = RFPGA0_XC_LSSIREADBACK;
412 rtlphy->phyreg_def[RF90_PATH_D].rf_rb = RFPGA0_XD_LSSIREADBACK;
413
414 rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVEA_HSPI_READBACK;
415 rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVEB_HSPI_READBACK;
416
417 }
418 EXPORT_SYMBOL(_rtl92c_phy_init_bb_rf_register_definition);
419
420 void rtl92c_phy_get_txpower_level(struct ieee80211_hw *hw, long *powerlevel)
421 {
422 struct rtl_priv *rtlpriv = rtl_priv(hw);
423 struct rtl_phy *rtlphy = &(rtlpriv->phy);
424 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
425 u8 txpwr_level;
426 long txpwr_dbm;
427
428 txpwr_level = rtlphy->cur_cck_txpwridx;
429 txpwr_dbm = _rtl92c_phy_txpwr_idx_to_dbm(hw,
430 WIRELESS_MODE_B, txpwr_level);
431 txpwr_level = rtlphy->cur_ofdm24g_txpwridx +
432 rtlefuse->legacy_ht_txpowerdiff;
433 if (_rtl92c_phy_txpwr_idx_to_dbm(hw,
434 WIRELESS_MODE_G,
435 txpwr_level) > txpwr_dbm)
436 txpwr_dbm =
437 _rtl92c_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G,
438 txpwr_level);
439 txpwr_level = rtlphy->cur_ofdm24g_txpwridx;
440 if (_rtl92c_phy_txpwr_idx_to_dbm(hw,
441 WIRELESS_MODE_N_24G,
442 txpwr_level) > txpwr_dbm)
443 txpwr_dbm =
444 _rtl92c_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_N_24G,
445 txpwr_level);
446 *powerlevel = txpwr_dbm;
447 }
448
449 static void _rtl92c_get_txpower_index(struct ieee80211_hw *hw, u8 channel,
450 u8 *cckpowerlevel, u8 *ofdmpowerlevel)
451 {
452 struct rtl_priv *rtlpriv = rtl_priv(hw);
453 struct rtl_phy *rtlphy = &(rtlpriv->phy);
454 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
455 u8 index = (channel - 1);
456
457 cckpowerlevel[RF90_PATH_A] =
458 rtlefuse->txpwrlevel_cck[RF90_PATH_A][index];
459 cckpowerlevel[RF90_PATH_B] =
460 rtlefuse->txpwrlevel_cck[RF90_PATH_B][index];
461 if (get_rf_type(rtlphy) == RF_1T2R || get_rf_type(rtlphy) == RF_1T1R) {
462 ofdmpowerlevel[RF90_PATH_A] =
463 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_A][index];
464 ofdmpowerlevel[RF90_PATH_B] =
465 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_B][index];
466 } else if (get_rf_type(rtlphy) == RF_2T2R) {
467 ofdmpowerlevel[RF90_PATH_A] =
468 rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_A][index];
469 ofdmpowerlevel[RF90_PATH_B] =
470 rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_B][index];
471 }
472 }
473
474 static void _rtl92c_ccxpower_index_check(struct ieee80211_hw *hw,
475 u8 channel, u8 *cckpowerlevel,
476 u8 *ofdmpowerlevel)
477 {
478 struct rtl_priv *rtlpriv = rtl_priv(hw);
479 struct rtl_phy *rtlphy = &(rtlpriv->phy);
480
481 rtlphy->cur_cck_txpwridx = cckpowerlevel[0];
482 rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0];
483
484 }
485
486 void rtl92c_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel)
487 {
488 struct rtl_priv *rtlpriv = rtl_priv(hw);
489 struct rtl_efuse *rtlefuse = rtl_efuse(rtlpriv);
490 u8 cckpowerlevel[2], ofdmpowerlevel[2];
491
492 if (!rtlefuse->txpwr_fromeprom)
493 return;
494 _rtl92c_get_txpower_index(hw, channel,
495 &cckpowerlevel[0], &ofdmpowerlevel[0]);
496 _rtl92c_ccxpower_index_check(hw,
497 channel, &cckpowerlevel[0],
498 &ofdmpowerlevel[0]);
499 rtlpriv->cfg->ops->phy_rf6052_set_cck_txpower(hw, &cckpowerlevel[0]);
500 rtlpriv->cfg->ops->phy_rf6052_set_ofdm_txpower(hw, &ofdmpowerlevel[0],
501 channel);
502 }
503 EXPORT_SYMBOL(rtl92c_phy_set_txpower_level);
504
505 bool rtl92c_phy_update_txpower_dbm(struct ieee80211_hw *hw, long power_indbm)
506 {
507 struct rtl_priv *rtlpriv = rtl_priv(hw);
508 struct rtl_phy *rtlphy = &(rtlpriv->phy);
509 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
510 u8 idx;
511 u8 rf_path;
512 u8 ccktxpwridx = _rtl92c_phy_dbm_to_txpwr_Idx(hw,
513 WIRELESS_MODE_B,
514 power_indbm);
515 u8 ofdmtxpwridx = _rtl92c_phy_dbm_to_txpwr_Idx(hw,
516 WIRELESS_MODE_N_24G,
517 power_indbm);
518 if (ofdmtxpwridx - rtlefuse->legacy_ht_txpowerdiff > 0)
519 ofdmtxpwridx -= rtlefuse->legacy_ht_txpowerdiff;
520 else
521 ofdmtxpwridx = 0;
522 RT_TRACE(rtlpriv, COMP_TXAGC, DBG_TRACE,
523 "%lx dBm, ccktxpwridx = %d, ofdmtxpwridx = %d\n",
524 power_indbm, ccktxpwridx, ofdmtxpwridx);
525 for (idx = 0; idx < 14; idx++) {
526 for (rf_path = 0; rf_path < 2; rf_path++) {
527 rtlefuse->txpwrlevel_cck[rf_path][idx] = ccktxpwridx;
528 rtlefuse->txpwrlevel_ht40_1s[rf_path][idx] =
529 ofdmtxpwridx;
530 rtlefuse->txpwrlevel_ht40_2s[rf_path][idx] =
531 ofdmtxpwridx;
532 }
533 }
534 rtl92c_phy_set_txpower_level(hw, rtlphy->current_channel);
535 return true;
536 }
537 EXPORT_SYMBOL(rtl92c_phy_update_txpower_dbm);
538
539 u8 _rtl92c_phy_dbm_to_txpwr_Idx(struct ieee80211_hw *hw,
540 enum wireless_mode wirelessmode,
541 long power_indbm)
542 {
543 u8 txpwridx;
544 long offset;
545
546 switch (wirelessmode) {
547 case WIRELESS_MODE_B:
548 offset = -7;
549 break;
550 case WIRELESS_MODE_G:
551 case WIRELESS_MODE_N_24G:
552 offset = -8;
553 break;
554 default:
555 offset = -8;
556 break;
557 }
558
559 if ((power_indbm - offset) > 0)
560 txpwridx = (u8) ((power_indbm - offset) * 2);
561 else
562 txpwridx = 0;
563
564 if (txpwridx > MAX_TXPWR_IDX_NMODE_92S)
565 txpwridx = MAX_TXPWR_IDX_NMODE_92S;
566
567 return txpwridx;
568 }
569 EXPORT_SYMBOL(_rtl92c_phy_dbm_to_txpwr_Idx);
570
571 long _rtl92c_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
572 enum wireless_mode wirelessmode,
573 u8 txpwridx)
574 {
575 long offset;
576 long pwrout_dbm;
577
578 switch (wirelessmode) {
579 case WIRELESS_MODE_B:
580 offset = -7;
581 break;
582 case WIRELESS_MODE_G:
583 case WIRELESS_MODE_N_24G:
584 offset = -8;
585 break;
586 default:
587 offset = -8;
588 break;
589 }
590 pwrout_dbm = txpwridx / 2 + offset;
591 return pwrout_dbm;
592 }
593 EXPORT_SYMBOL(_rtl92c_phy_txpwr_idx_to_dbm);
594
595 void rtl92c_phy_set_bw_mode(struct ieee80211_hw *hw,
596 enum nl80211_channel_type ch_type)
597 {
598 struct rtl_priv *rtlpriv = rtl_priv(hw);
599 struct rtl_phy *rtlphy = &(rtlpriv->phy);
600 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
601 u8 tmp_bw = rtlphy->current_chan_bw;
602
603 if (rtlphy->set_bwmode_inprogress)
604 return;
605 rtlphy->set_bwmode_inprogress = true;
606 if ((!is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) {
607 rtlpriv->cfg->ops->phy_set_bw_mode_callback(hw);
608 } else {
609 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
610 "FALSE driver sleep or unload\n");
611 rtlphy->set_bwmode_inprogress = false;
612 rtlphy->current_chan_bw = tmp_bw;
613 }
614 }
615 EXPORT_SYMBOL(rtl92c_phy_set_bw_mode);
616
617 void rtl92c_phy_sw_chnl_callback(struct ieee80211_hw *hw)
618 {
619 struct rtl_priv *rtlpriv = rtl_priv(hw);
620 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
621 struct rtl_phy *rtlphy = &(rtlpriv->phy);
622 u32 delay;
623
624 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
625 "switch to channel%d\n", rtlphy->current_channel);
626 if (is_hal_stop(rtlhal))
627 return;
628 do {
629 if (!rtlphy->sw_chnl_inprogress)
630 break;
631 if (!_rtl92c_phy_sw_chnl_step_by_step
632 (hw, rtlphy->current_channel, &rtlphy->sw_chnl_stage,
633 &rtlphy->sw_chnl_step, &delay)) {
634 if (delay > 0)
635 mdelay(delay);
636 else
637 continue;
638 } else {
639 rtlphy->sw_chnl_inprogress = false;
640 }
641 break;
642 } while (true);
643 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
644 }
645 EXPORT_SYMBOL(rtl92c_phy_sw_chnl_callback);
646
647 u8 rtl92c_phy_sw_chnl(struct ieee80211_hw *hw)
648 {
649 struct rtl_priv *rtlpriv = rtl_priv(hw);
650 struct rtl_phy *rtlphy = &(rtlpriv->phy);
651 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
652
653 if (rtlphy->sw_chnl_inprogress)
654 return 0;
655 if (rtlphy->set_bwmode_inprogress)
656 return 0;
657 RT_ASSERT((rtlphy->current_channel <= 14),
658 "WIRELESS_MODE_G but channel>14\n");
659 rtlphy->sw_chnl_inprogress = true;
660 rtlphy->sw_chnl_stage = 0;
661 rtlphy->sw_chnl_step = 0;
662 if (!(is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) {
663 rtl92c_phy_sw_chnl_callback(hw);
664 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD,
665 "sw_chnl_inprogress false schedule workitem\n");
666 rtlphy->sw_chnl_inprogress = false;
667 } else {
668 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD,
669 "sw_chnl_inprogress false driver sleep or unload\n");
670 rtlphy->sw_chnl_inprogress = false;
671 }
672 return 1;
673 }
674 EXPORT_SYMBOL(rtl92c_phy_sw_chnl);
675
676 static void _rtl92c_phy_sw_rf_setting(struct ieee80211_hw *hw, u8 channel)
677 {
678 struct rtl_priv *rtlpriv = rtl_priv(hw);
679 struct rtl_phy *rtlphy = &(rtlpriv->phy);
680 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
681
682 if (IS_81xxC_VENDOR_UMC_B_CUT(rtlhal->version)) {
683 if (channel == 6 && rtlphy->current_chan_bw ==
684 HT_CHANNEL_WIDTH_20)
685 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD,
686 0x00255);
687 else{
688 u32 backupRF0x1A = (u32)rtl_get_rfreg(hw, RF90_PATH_A,
689 RF_RX_G1, RFREG_OFFSET_MASK);
690 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD,
691 backupRF0x1A);
692 }
693 }
694 }
695
696 static bool _rtl92c_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
697 u32 cmdtableidx, u32 cmdtablesz,
698 enum swchnlcmd_id cmdid,
699 u32 para1, u32 para2, u32 msdelay)
700 {
701 struct swchnlcmd *pcmd;
702
703 if (cmdtable == NULL) {
704 RT_ASSERT(false, "cmdtable cannot be NULL\n");
705 return false;
706 }
707
708 if (cmdtableidx >= cmdtablesz)
709 return false;
710
711 pcmd = cmdtable + cmdtableidx;
712 pcmd->cmdid = cmdid;
713 pcmd->para1 = para1;
714 pcmd->para2 = para2;
715 pcmd->msdelay = msdelay;
716 return true;
717 }
718
719 bool _rtl92c_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
720 u8 channel, u8 *stage, u8 *step,
721 u32 *delay)
722 {
723 struct rtl_priv *rtlpriv = rtl_priv(hw);
724 struct rtl_phy *rtlphy = &(rtlpriv->phy);
725 struct swchnlcmd precommoncmd[MAX_PRECMD_CNT];
726 u32 precommoncmdcnt;
727 struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT];
728 u32 postcommoncmdcnt;
729 struct swchnlcmd rfdependcmd[MAX_RFDEPENDCMD_CNT];
730 u32 rfdependcmdcnt;
731 struct swchnlcmd *currentcmd = NULL;
732 u8 rfpath;
733 u8 num_total_rfpath = rtlphy->num_total_rfpath;
734
735 precommoncmdcnt = 0;
736 _rtl92c_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
737 MAX_PRECMD_CNT,
738 CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0);
739 _rtl92c_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
740 MAX_PRECMD_CNT, CMDID_END, 0, 0, 0);
741
742 postcommoncmdcnt = 0;
743
744 _rtl92c_phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++,
745 MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0);
746
747 rfdependcmdcnt = 0;
748
749 RT_ASSERT((channel >= 1 && channel <= 14),
750 "invalid channel for Zebra: %d\n", channel);
751
752 _rtl92c_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
753 MAX_RFDEPENDCMD_CNT, CMDID_RF_WRITEREG,
754 RF_CHNLBW, channel, 10);
755
756 _rtl92c_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
757 MAX_RFDEPENDCMD_CNT, CMDID_END, 0, 0,
758 0);
759
760 do {
761 switch (*stage) {
762 case 0:
763 currentcmd = &precommoncmd[*step];
764 break;
765 case 1:
766 currentcmd = &rfdependcmd[*step];
767 break;
768 case 2:
769 currentcmd = &postcommoncmd[*step];
770 break;
771 }
772
773 if (currentcmd->cmdid == CMDID_END) {
774 if ((*stage) == 2) {
775 return true;
776 } else {
777 (*stage)++;
778 (*step) = 0;
779 continue;
780 }
781 }
782
783 switch (currentcmd->cmdid) {
784 case CMDID_SET_TXPOWEROWER_LEVEL:
785 rtl92c_phy_set_txpower_level(hw, channel);
786 break;
787 case CMDID_WRITEPORT_ULONG:
788 rtl_write_dword(rtlpriv, currentcmd->para1,
789 currentcmd->para2);
790 break;
791 case CMDID_WRITEPORT_USHORT:
792 rtl_write_word(rtlpriv, currentcmd->para1,
793 (u16) currentcmd->para2);
794 break;
795 case CMDID_WRITEPORT_UCHAR:
796 rtl_write_byte(rtlpriv, currentcmd->para1,
797 (u8) currentcmd->para2);
798 break;
799 case CMDID_RF_WRITEREG:
800 for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) {
801 rtlphy->rfreg_chnlval[rfpath] =
802 ((rtlphy->rfreg_chnlval[rfpath] &
803 0xfffffc00) | currentcmd->para2);
804
805 rtl_set_rfreg(hw, (enum radio_path)rfpath,
806 currentcmd->para1,
807 RFREG_OFFSET_MASK,
808 rtlphy->rfreg_chnlval[rfpath]);
809 _rtl92c_phy_sw_rf_setting(hw, channel);
810 }
811 break;
812 default:
813 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
814 "switch case not processed\n");
815 break;
816 }
817
818 break;
819 } while (true);
820
821 (*delay) = currentcmd->msdelay;
822 (*step)++;
823 return false;
824 }
825
826 bool rtl8192_phy_check_is_legal_rfpath(struct ieee80211_hw *hw, u32 rfpath)
827 {
828 return true;
829 }
830 EXPORT_SYMBOL(rtl8192_phy_check_is_legal_rfpath);
831
832 static u8 _rtl92c_phy_path_a_iqk(struct ieee80211_hw *hw, bool config_pathb)
833 {
834 u32 reg_eac, reg_e94, reg_e9c, reg_ea4;
835 u8 result = 0x00;
836
837 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c1f);
838 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c1f);
839 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140102);
840 rtl_set_bbreg(hw, 0xe3c, MASKDWORD,
841 config_pathb ? 0x28160202 : 0x28160502);
842
843 if (config_pathb) {
844 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x10008c22);
845 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x10008c22);
846 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140102);
847 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x28160202);
848 }
849
850 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x001028d1);
851 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000);
852 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000);
853
854 mdelay(IQK_DELAY_TIME);
855
856 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
857 reg_e94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD);
858 reg_e9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD);
859 reg_ea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD);
860
861 if (!(reg_eac & BIT(28)) &&
862 (((reg_e94 & 0x03FF0000) >> 16) != 0x142) &&
863 (((reg_e9c & 0x03FF0000) >> 16) != 0x42))
864 result |= 0x01;
865 else
866 return result;
867
868 if (!(reg_eac & BIT(27)) &&
869 (((reg_ea4 & 0x03FF0000) >> 16) != 0x132) &&
870 (((reg_eac & 0x03FF0000) >> 16) != 0x36))
871 result |= 0x02;
872 return result;
873 }
874
875 static u8 _rtl92c_phy_path_b_iqk(struct ieee80211_hw *hw)
876 {
877 u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc;
878 u8 result = 0x00;
879
880 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000002);
881 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000000);
882 mdelay(IQK_DELAY_TIME);
883 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
884 reg_eb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD);
885 reg_ebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD);
886 reg_ec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD);
887 reg_ecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD);
888
889 if (!(reg_eac & BIT(31)) &&
890 (((reg_eb4 & 0x03FF0000) >> 16) != 0x142) &&
891 (((reg_ebc & 0x03FF0000) >> 16) != 0x42))
892 result |= 0x01;
893 else
894 return result;
895 if (!(reg_eac & BIT(30)) &&
896 (((reg_ec4 & 0x03FF0000) >> 16) != 0x132) &&
897 (((reg_ecc & 0x03FF0000) >> 16) != 0x36))
898 result |= 0x02;
899 return result;
900 }
901
902 static void _rtl92c_phy_path_a_fill_iqk_matrix(struct ieee80211_hw *hw,
903 bool iqk_ok, long result[][8],
904 u8 final_candidate, bool btxonly)
905 {
906 u32 oldval_0, x, tx0_a, reg;
907 long y, tx0_c;
908
909 if (final_candidate == 0xFF) {
910 return;
911 } else if (iqk_ok) {
912 oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
913 MASKDWORD) >> 22) & 0x3FF;
914 x = result[final_candidate][0];
915 if ((x & 0x00000200) != 0)
916 x = x | 0xFFFFFC00;
917 tx0_a = (x * oldval_0) >> 8;
918 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx0_a);
919 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(31),
920 ((x * oldval_0 >> 7) & 0x1));
921 y = result[final_candidate][1];
922 if ((y & 0x00000200) != 0)
923 y = y | 0xFFFFFC00;
924 tx0_c = (y * oldval_0) >> 8;
925 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000,
926 ((tx0_c & 0x3C0) >> 6));
927 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x003F0000,
928 (tx0_c & 0x3F));
929 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(29),
930 ((y * oldval_0 >> 7) & 0x1));
931 if (btxonly)
932 return;
933 reg = result[final_candidate][2];
934 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg);
935 reg = result[final_candidate][3] & 0x3F;
936 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg);
937 reg = (result[final_candidate][3] >> 6) & 0xF;
938 rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg);
939 }
940 }
941
942 static void _rtl92c_phy_path_b_fill_iqk_matrix(struct ieee80211_hw *hw,
943 bool iqk_ok, long result[][8],
944 u8 final_candidate, bool btxonly)
945 {
946 u32 oldval_1, x, tx1_a, reg;
947 long y, tx1_c;
948
949 if (final_candidate == 0xFF) {
950 return;
951 } else if (iqk_ok) {
952 oldval_1 = (rtl_get_bbreg(hw, ROFDM0_XBTXIQIMBALANCE,
953 MASKDWORD) >> 22) & 0x3FF;
954 x = result[final_candidate][4];
955 if ((x & 0x00000200) != 0)
956 x = x | 0xFFFFFC00;
957 tx1_a = (x * oldval_1) >> 8;
958 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x3FF, tx1_a);
959 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(27),
960 ((x * oldval_1 >> 7) & 0x1));
961 y = result[final_candidate][5];
962 if ((y & 0x00000200) != 0)
963 y = y | 0xFFFFFC00;
964 tx1_c = (y * oldval_1) >> 8;
965 rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 0xF0000000,
966 ((tx1_c & 0x3C0) >> 6));
967 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x003F0000,
968 (tx1_c & 0x3F));
969 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(25),
970 ((y * oldval_1 >> 7) & 0x1));
971 if (btxonly)
972 return;
973 reg = result[final_candidate][6];
974 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg);
975 reg = result[final_candidate][7] & 0x3F;
976 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg);
977 reg = (result[final_candidate][7] >> 6) & 0xF;
978 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, reg);
979 }
980 }
981
982 static void _rtl92c_phy_save_adda_registers(struct ieee80211_hw *hw,
983 u32 *addareg, u32 *addabackup,
984 u32 registernum)
985 {
986 u32 i;
987
988 for (i = 0; i < registernum; i++)
989 addabackup[i] = rtl_get_bbreg(hw, addareg[i], MASKDWORD);
990 }
991
992 static void _rtl92c_phy_save_mac_registers(struct ieee80211_hw *hw,
993 u32 *macreg, u32 *macbackup)
994 {
995 struct rtl_priv *rtlpriv = rtl_priv(hw);
996 u32 i;
997
998 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
999 macbackup[i] = rtl_read_byte(rtlpriv, macreg[i]);
1000 macbackup[i] = rtl_read_dword(rtlpriv, macreg[i]);
1001 }
1002
1003 static void _rtl92c_phy_reload_adda_registers(struct ieee80211_hw *hw,
1004 u32 *addareg, u32 *addabackup,
1005 u32 regiesternum)
1006 {
1007 u32 i;
1008
1009 for (i = 0; i < regiesternum; i++)
1010 rtl_set_bbreg(hw, addareg[i], MASKDWORD, addabackup[i]);
1011 }
1012
1013 static void _rtl92c_phy_reload_mac_registers(struct ieee80211_hw *hw,
1014 u32 *macreg, u32 *macbackup)
1015 {
1016 struct rtl_priv *rtlpriv = rtl_priv(hw);
1017 u32 i;
1018
1019 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1020 rtl_write_byte(rtlpriv, macreg[i], (u8) macbackup[i]);
1021 rtl_write_dword(rtlpriv, macreg[i], macbackup[i]);
1022 }
1023
1024 static void _rtl92c_phy_path_adda_on(struct ieee80211_hw *hw,
1025 u32 *addareg, bool is_patha_on, bool is2t)
1026 {
1027 u32 pathOn;
1028 u32 i;
1029
1030 pathOn = is_patha_on ? 0x04db25a4 : 0x0b1b25a4;
1031 if (false == is2t) {
1032 pathOn = 0x0bdb25a0;
1033 rtl_set_bbreg(hw, addareg[0], MASKDWORD, 0x0b1b25a0);
1034 } else {
1035 rtl_set_bbreg(hw, addareg[0], MASKDWORD, pathOn);
1036 }
1037
1038 for (i = 1; i < IQK_ADDA_REG_NUM; i++)
1039 rtl_set_bbreg(hw, addareg[i], MASKDWORD, pathOn);
1040 }
1041
1042 static void _rtl92c_phy_mac_setting_calibration(struct ieee80211_hw *hw,
1043 u32 *macreg, u32 *macbackup)
1044 {
1045 struct rtl_priv *rtlpriv = rtl_priv(hw);
1046 u32 i;
1047
1048 rtl_write_byte(rtlpriv, macreg[0], 0x3F);
1049
1050 for (i = 1; i < (IQK_MAC_REG_NUM - 1); i++)
1051 rtl_write_byte(rtlpriv, macreg[i],
1052 (u8) (macbackup[i] & (~BIT(3))));
1053 rtl_write_byte(rtlpriv, macreg[i], (u8) (macbackup[i] & (~BIT(5))));
1054 }
1055
1056 static void _rtl92c_phy_path_a_standby(struct ieee80211_hw *hw)
1057 {
1058 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0);
1059 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000);
1060 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
1061 }
1062
1063 static void _rtl92c_phy_pi_mode_switch(struct ieee80211_hw *hw, bool pi_mode)
1064 {
1065 u32 mode;
1066
1067 mode = pi_mode ? 0x01000100 : 0x01000000;
1068 rtl_set_bbreg(hw, 0x820, MASKDWORD, mode);
1069 rtl_set_bbreg(hw, 0x828, MASKDWORD, mode);
1070 }
1071
1072 static bool _rtl92c_phy_simularity_compare(struct ieee80211_hw *hw,
1073 long result[][8], u8 c1, u8 c2)
1074 {
1075 u32 i, j, diff, simularity_bitmap, bound;
1076 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1077
1078 u8 final_candidate[2] = { 0xFF, 0xFF };
1079 bool bresult = true, is2t = IS_92C_SERIAL(rtlhal->version);
1080
1081 if (is2t)
1082 bound = 8;
1083 else
1084 bound = 4;
1085
1086 simularity_bitmap = 0;
1087
1088 for (i = 0; i < bound; i++) {
1089 diff = (result[c1][i] > result[c2][i]) ?
1090 (result[c1][i] - result[c2][i]) :
1091 (result[c2][i] - result[c1][i]);
1092
1093 if (diff > MAX_TOLERANCE) {
1094 if ((i == 2 || i == 6) && !simularity_bitmap) {
1095 if (result[c1][i] + result[c1][i + 1] == 0)
1096 final_candidate[(i / 4)] = c2;
1097 else if (result[c2][i] + result[c2][i + 1] == 0)
1098 final_candidate[(i / 4)] = c1;
1099 else
1100 simularity_bitmap = simularity_bitmap |
1101 (1 << i);
1102 } else
1103 simularity_bitmap =
1104 simularity_bitmap | (1 << i);
1105 }
1106 }
1107
1108 if (simularity_bitmap == 0) {
1109 for (i = 0; i < (bound / 4); i++) {
1110 if (final_candidate[i] != 0xFF) {
1111 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
1112 result[3][j] =
1113 result[final_candidate[i]][j];
1114 bresult = false;
1115 }
1116 }
1117 return bresult;
1118 } else if (!(simularity_bitmap & 0x0F)) {
1119 for (i = 0; i < 4; i++)
1120 result[3][i] = result[c1][i];
1121 return false;
1122 } else if (!(simularity_bitmap & 0xF0) && is2t) {
1123 for (i = 4; i < 8; i++)
1124 result[3][i] = result[c1][i];
1125 return false;
1126 } else {
1127 return false;
1128 }
1129
1130 }
1131
1132 static void _rtl92c_phy_iq_calibrate(struct ieee80211_hw *hw,
1133 long result[][8], u8 t, bool is2t)
1134 {
1135 struct rtl_priv *rtlpriv = rtl_priv(hw);
1136 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1137 u32 i;
1138 u8 patha_ok, pathb_ok;
1139 u32 adda_reg[IQK_ADDA_REG_NUM] = {
1140 0x85c, 0xe6c, 0xe70, 0xe74,
1141 0xe78, 0xe7c, 0xe80, 0xe84,
1142 0xe88, 0xe8c, 0xed0, 0xed4,
1143 0xed8, 0xedc, 0xee0, 0xeec
1144 };
1145
1146 u32 iqk_mac_reg[IQK_MAC_REG_NUM] = {
1147 0x522, 0x550, 0x551, 0x040
1148 };
1149
1150 u32 iqk_bb_reg_92C[9] = {
1151 0xc04, 0xc08, 0x874, 0xb68,
1152 0xb6c, 0x870, 0x860, 0x864,
1153 0x800
1154 };
1155
1156 const u32 retrycount = 2;
1157
1158 if (t == 0) {
1159 /* dummy read */
1160 rtl_get_bbreg(hw, 0x800, MASKDWORD);
1161
1162 _rtl92c_phy_save_adda_registers(hw, adda_reg,
1163 rtlphy->adda_backup, 16);
1164 _rtl92c_phy_save_mac_registers(hw, iqk_mac_reg,
1165 rtlphy->iqk_mac_backup);
1166 _rtl92c_phy_save_adda_registers(hw, iqk_bb_reg_92C,
1167 rtlphy->iqk_bb_backup, 9);
1168 }
1169 _rtl92c_phy_path_adda_on(hw, adda_reg, true, is2t);
1170 if (t == 0) {
1171 rtlphy->rfpi_enable = (u8) rtl_get_bbreg(hw,
1172 RFPGA0_XA_HSSIPARAMETER1,
1173 BIT(8));
1174 }
1175
1176 if (!rtlphy->rfpi_enable)
1177 _rtl92c_phy_pi_mode_switch(hw, true);
1178
1179 rtl_set_bbreg(hw, 0x800, BIT(24), 0x0);
1180
1181 rtl_set_bbreg(hw, 0xc04, MASKDWORD, 0x03a05600);
1182 rtl_set_bbreg(hw, 0xc08, MASKDWORD, 0x000800e4);
1183 rtl_set_bbreg(hw, 0x874, MASKDWORD, 0x22204000);
1184
1185 rtl_set_bbreg(hw, 0x870, BIT(10), 0x1);
1186 rtl_set_bbreg(hw, 0x870, BIT(26), 0x1);
1187 rtl_set_bbreg(hw, 0x860, BIT(10), 0x0);
1188 rtl_set_bbreg(hw, 0x864, BIT(10), 0x0);
1189
1190 if (is2t) {
1191 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000);
1192 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00010000);
1193 }
1194 _rtl92c_phy_mac_setting_calibration(hw, iqk_mac_reg,
1195 rtlphy->iqk_mac_backup);
1196 rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x00080000);
1197 if (is2t)
1198 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x00080000);
1199 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
1200 rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x01007c00);
1201 rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800);
1202 for (i = 0; i < retrycount; i++) {
1203 patha_ok = _rtl92c_phy_path_a_iqk(hw, is2t);
1204 if (patha_ok == 0x03) {
1205 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &
1206 0x3FF0000) >> 16;
1207 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &
1208 0x3FF0000) >> 16;
1209 result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) &
1210 0x3FF0000) >> 16;
1211 result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) &
1212 0x3FF0000) >> 16;
1213 break;
1214 } else if (i == (retrycount - 1) && patha_ok == 0x01)
1215
1216 result[t][0] = (rtl_get_bbreg(hw, 0xe94,
1217 MASKDWORD) & 0x3FF0000) >>
1218 16;
1219 result[t][1] =
1220 (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & 0x3FF0000) >> 16;
1221
1222 }
1223
1224 if (is2t) {
1225 _rtl92c_phy_path_a_standby(hw);
1226 _rtl92c_phy_path_adda_on(hw, adda_reg, false, is2t);
1227 for (i = 0; i < retrycount; i++) {
1228 pathb_ok = _rtl92c_phy_path_b_iqk(hw);
1229 if (pathb_ok == 0x03) {
1230 result[t][4] = (rtl_get_bbreg(hw,
1231 0xeb4,
1232 MASKDWORD) &
1233 0x3FF0000) >> 16;
1234 result[t][5] =
1235 (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
1236 0x3FF0000) >> 16;
1237 result[t][6] =
1238 (rtl_get_bbreg(hw, 0xec4, MASKDWORD) &
1239 0x3FF0000) >> 16;
1240 result[t][7] =
1241 (rtl_get_bbreg(hw, 0xecc, MASKDWORD) &
1242 0x3FF0000) >> 16;
1243 break;
1244 } else if (i == (retrycount - 1) && pathb_ok == 0x01) {
1245 result[t][4] = (rtl_get_bbreg(hw,
1246 0xeb4,
1247 MASKDWORD) &
1248 0x3FF0000) >> 16;
1249 }
1250 result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
1251 0x3FF0000) >> 16;
1252 }
1253 }
1254
1255 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0);
1256
1257 if (t != 0) {
1258 if (!rtlphy->rfpi_enable)
1259 _rtl92c_phy_pi_mode_switch(hw, false);
1260 _rtl92c_phy_reload_adda_registers(hw, adda_reg,
1261 rtlphy->adda_backup, 16);
1262 _rtl92c_phy_reload_mac_registers(hw, iqk_mac_reg,
1263 rtlphy->iqk_mac_backup);
1264 _rtl92c_phy_reload_adda_registers(hw, iqk_bb_reg_92C,
1265 rtlphy->iqk_bb_backup, 9);
1266
1267 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00032ed3);
1268 if (is2t)
1269 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00032ed3);
1270
1271 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x01008c00);
1272 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x01008c00);
1273 }
1274 }
1275
1276 static void _rtl92c_phy_ap_calibrate(struct ieee80211_hw *hw,
1277 char delta, bool is2t)
1278 {
1279 #if 0 /* This routine is deliberately dummied out for later fixes */
1280 struct rtl_priv *rtlpriv = rtl_priv(hw);
1281 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1282 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1283
1284 u32 reg_d[PATH_NUM];
1285 u32 tmpreg, index, offset, path, i, pathbound = PATH_NUM, apkbound;
1286
1287 u32 bb_backup[APK_BB_REG_NUM];
1288 u32 bb_reg[APK_BB_REG_NUM] = {
1289 0x904, 0xc04, 0x800, 0xc08, 0x874
1290 };
1291 u32 bb_ap_mode[APK_BB_REG_NUM] = {
1292 0x00000020, 0x00a05430, 0x02040000,
1293 0x000800e4, 0x00204000
1294 };
1295 u32 bb_normal_ap_mode[APK_BB_REG_NUM] = {
1296 0x00000020, 0x00a05430, 0x02040000,
1297 0x000800e4, 0x22204000
1298 };
1299
1300 u32 afe_backup[APK_AFE_REG_NUM];
1301 u32 afe_reg[APK_AFE_REG_NUM] = {
1302 0x85c, 0xe6c, 0xe70, 0xe74, 0xe78,
1303 0xe7c, 0xe80, 0xe84, 0xe88, 0xe8c,
1304 0xed0, 0xed4, 0xed8, 0xedc, 0xee0,
1305 0xeec
1306 };
1307
1308 u32 mac_backup[IQK_MAC_REG_NUM];
1309 u32 mac_reg[IQK_MAC_REG_NUM] = {
1310 0x522, 0x550, 0x551, 0x040
1311 };
1312
1313 u32 apk_rf_init_value[PATH_NUM][APK_BB_REG_NUM] = {
1314 {0x0852c, 0x1852c, 0x5852c, 0x1852c, 0x5852c},
1315 {0x2852e, 0x0852e, 0x3852e, 0x0852e, 0x0852e}
1316 };
1317
1318 u32 apk_normal_rf_init_value[PATH_NUM][APK_BB_REG_NUM] = {
1319 {0x0852c, 0x0a52c, 0x3a52c, 0x5a52c, 0x5a52c},
1320 {0x0852c, 0x0a52c, 0x5a52c, 0x5a52c, 0x5a52c}
1321 };
1322
1323 u32 apk_rf_value_0[PATH_NUM][APK_BB_REG_NUM] = {
1324 {0x52019, 0x52014, 0x52013, 0x5200f, 0x5208d},
1325 {0x5201a, 0x52019, 0x52016, 0x52033, 0x52050}
1326 };
1327
1328 u32 apk_normal_rf_value_0[PATH_NUM][APK_BB_REG_NUM] = {
1329 {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a},
1330 {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}
1331 };
1332
1333 u32 afe_on_off[PATH_NUM] = {
1334 0x04db25a4, 0x0b1b25a4
1335 };
1336
1337 const u32 apk_offset[PATH_NUM] = { 0xb68, 0xb6c };
1338
1339 u32 apk_normal_offset[PATH_NUM] = { 0xb28, 0xb98 };
1340
1341 u32 apk_value[PATH_NUM] = { 0x92fc0000, 0x12fc0000 };
1342
1343 u32 apk_normal_value[PATH_NUM] = { 0x92680000, 0x12680000 };
1344
1345 const char apk_delta_mapping[APK_BB_REG_NUM][13] = {
1346 {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6},
1347 {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6},
1348 {-6, -4, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6},
1349 {-1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, 6},
1350 {-11, -9, -7, -5, -3, -1, 0, 0, 0, 0, 0, 0, 0}
1351 };
1352
1353 const u32 apk_normal_setting_value_1[13] = {
1354 0x01017018, 0xf7ed8f84, 0x1b1a1816, 0x2522201e, 0x322e2b28,
1355 0x433f3a36, 0x5b544e49, 0x7b726a62, 0xa69a8f84, 0xdfcfc0b3,
1356 0x12680000, 0x00880000, 0x00880000
1357 };
1358
1359 const u32 apk_normal_setting_value_2[16] = {
1360 0x01c7021d, 0x01670183, 0x01000123, 0x00bf00e2, 0x008d00a3,
1361 0x0068007b, 0x004d0059, 0x003a0042, 0x002b0031, 0x001f0025,
1362 0x0017001b, 0x00110014, 0x000c000f, 0x0009000b, 0x00070008,
1363 0x00050006
1364 };
1365
1366 u32 apk_result[PATH_NUM][APK_BB_REG_NUM];
1367
1368 long bb_offset, delta_v, delta_offset;
1369
1370 if (!is2t)
1371 pathbound = 1;
1372
1373 return;
1374
1375 for (index = 0; index < PATH_NUM; index++) {
1376 apk_offset[index] = apk_normal_offset[index];
1377 apk_value[index] = apk_normal_value[index];
1378 afe_on_off[index] = 0x6fdb25a4;
1379 }
1380
1381 for (index = 0; index < APK_BB_REG_NUM; index++) {
1382 for (path = 0; path < pathbound; path++) {
1383 apk_rf_init_value[path][index] =
1384 apk_normal_rf_init_value[path][index];
1385 apk_rf_value_0[path][index] =
1386 apk_normal_rf_value_0[path][index];
1387 }
1388 bb_ap_mode[index] = bb_normal_ap_mode[index];
1389
1390 apkbound = 6;
1391 }
1392
1393 for (index = 0; index < APK_BB_REG_NUM; index++) {
1394 if (index == 0)
1395 continue;
1396 bb_backup[index] = rtl_get_bbreg(hw, bb_reg[index], MASKDWORD);
1397 }
1398
1399 _rtl92c_phy_save_mac_registers(hw, mac_reg, mac_backup);
1400
1401 _rtl92c_phy_save_adda_registers(hw, afe_reg, afe_backup, 16);
1402
1403 for (path = 0; path < pathbound; path++) {
1404 if (path == RF90_PATH_A) {
1405 offset = 0xb00;
1406 for (index = 0; index < 11; index++) {
1407 rtl_set_bbreg(hw, offset, MASKDWORD,
1408 apk_normal_setting_value_1
1409 [index]);
1410
1411 offset += 0x04;
1412 }
1413
1414 rtl_set_bbreg(hw, 0xb98, MASKDWORD, 0x12680000);
1415
1416 offset = 0xb68;
1417 for (; index < 13; index++) {
1418 rtl_set_bbreg(hw, offset, MASKDWORD,
1419 apk_normal_setting_value_1
1420 [index]);
1421
1422 offset += 0x04;
1423 }
1424
1425 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x40000000);
1426
1427 offset = 0xb00;
1428 for (index = 0; index < 16; index++) {
1429 rtl_set_bbreg(hw, offset, MASKDWORD,
1430 apk_normal_setting_value_2
1431 [index]);
1432
1433 offset += 0x04;
1434 }
1435 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x00000000);
1436 } else if (path == RF90_PATH_B) {
1437 offset = 0xb70;
1438 for (index = 0; index < 10; index++) {
1439 rtl_set_bbreg(hw, offset, MASKDWORD,
1440 apk_normal_setting_value_1
1441 [index]);
1442
1443 offset += 0x04;
1444 }
1445 rtl_set_bbreg(hw, 0xb28, MASKDWORD, 0x12680000);
1446 rtl_set_bbreg(hw, 0xb98, MASKDWORD, 0x12680000);
1447
1448 offset = 0xb68;
1449 index = 11;
1450 for (; index < 13; index++) {
1451 rtl_set_bbreg(hw, offset, MASKDWORD,
1452 apk_normal_setting_value_1
1453 [index]);
1454
1455 offset += 0x04;
1456 }
1457
1458 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x40000000);
1459
1460 offset = 0xb60;
1461 for (index = 0; index < 16; index++) {
1462 rtl_set_bbreg(hw, offset, MASKDWORD,
1463 apk_normal_setting_value_2
1464 [index]);
1465
1466 offset += 0x04;
1467 }
1468 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x00000000);
1469 }
1470
1471 reg_d[path] = rtl_get_rfreg(hw, (enum radio_path)path,
1472 0xd, MASKDWORD);
1473
1474 for (index = 0; index < APK_AFE_REG_NUM; index++)
1475 rtl_set_bbreg(hw, afe_reg[index], MASKDWORD,
1476 afe_on_off[path]);
1477
1478 if (path == RF90_PATH_A) {
1479 for (index = 0; index < APK_BB_REG_NUM; index++) {
1480 if (index == 0)
1481 continue;
1482 rtl_set_bbreg(hw, bb_reg[index], MASKDWORD,
1483 bb_ap_mode[index]);
1484 }
1485 }
1486
1487 _rtl92c_phy_mac_setting_calibration(hw, mac_reg, mac_backup);
1488
1489 if (path == 0) {
1490 rtl_set_rfreg(hw, RF90_PATH_B, 0x0, MASKDWORD, 0x10000);
1491 } else {
1492 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASKDWORD,
1493 0x10000);
1494 rtl_set_rfreg(hw, RF90_PATH_A, 0x10, MASKDWORD,
1495 0x1000f);
1496 rtl_set_rfreg(hw, RF90_PATH_A, 0x11, MASKDWORD,
1497 0x20103);
1498 }
1499
1500 delta_offset = ((delta + 14) / 2);
1501 if (delta_offset < 0)
1502 delta_offset = 0;
1503 else if (delta_offset > 12)
1504 delta_offset = 12;
1505
1506 for (index = 0; index < APK_BB_REG_NUM; index++) {
1507 if (index != 1)
1508 continue;
1509
1510 tmpreg = apk_rf_init_value[path][index];
1511
1512 if (!rtlefuse->apk_thermalmeterignore) {
1513 bb_offset = (tmpreg & 0xF0000) >> 16;
1514
1515 if (!(tmpreg & BIT(15)))
1516 bb_offset = -bb_offset;
1517
1518 delta_v =
1519 apk_delta_mapping[index][delta_offset];
1520
1521 bb_offset += delta_v;
1522
1523 if (bb_offset < 0) {
1524 tmpreg = tmpreg & (~BIT(15));
1525 bb_offset = -bb_offset;
1526 } else {
1527 tmpreg = tmpreg | BIT(15);
1528 }
1529
1530 tmpreg =
1531 (tmpreg & 0xFFF0FFFF) | (bb_offset << 16);
1532 }
1533
1534 rtl_set_rfreg(hw, (enum radio_path)path, 0xc,
1535 MASKDWORD, 0x8992e);
1536 rtl_set_rfreg(hw, (enum radio_path)path, 0x0,
1537 MASKDWORD, apk_rf_value_0[path][index]);
1538 rtl_set_rfreg(hw, (enum radio_path)path, 0xd,
1539 MASKDWORD, tmpreg);
1540
1541 i = 0;
1542 do {
1543 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80000000);
1544 rtl_set_bbreg(hw, apk_offset[path],
1545 MASKDWORD, apk_value[0]);
1546 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1547 ("PHY_APCalibrate() offset 0x%x "
1548 "value 0x%x\n",
1549 apk_offset[path],
1550 rtl_get_bbreg(hw, apk_offset[path],
1551 MASKDWORD)));
1552
1553 mdelay(3);
1554
1555 rtl_set_bbreg(hw, apk_offset[path],
1556 MASKDWORD, apk_value[1]);
1557 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1558 ("PHY_APCalibrate() offset 0x%x "
1559 "value 0x%x\n",
1560 apk_offset[path],
1561 rtl_get_bbreg(hw, apk_offset[path],
1562 MASKDWORD)));
1563
1564 mdelay(20);
1565
1566 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x00000000);
1567
1568 if (path == RF90_PATH_A)
1569 tmpreg = rtl_get_bbreg(hw, 0xbd8,
1570 0x03E00000);
1571 else
1572 tmpreg = rtl_get_bbreg(hw, 0xbd8,
1573 0xF8000000);
1574
1575 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1576 ("PHY_APCalibrate() offset "
1577 "0xbd8[25:21] %x\n", tmpreg));
1578
1579 i++;
1580
1581 } while (tmpreg > apkbound && i < 4);
1582
1583 apk_result[path][index] = tmpreg;
1584 }
1585 }
1586
1587 _rtl92c_phy_reload_mac_registers(hw, mac_reg, mac_backup);
1588
1589 for (index = 0; index < APK_BB_REG_NUM; index++) {
1590 if (index == 0)
1591 continue;
1592 rtl_set_bbreg(hw, bb_reg[index], MASKDWORD, bb_backup[index]);
1593 }
1594
1595 _rtl92c_phy_reload_adda_registers(hw, afe_reg, afe_backup, 16);
1596
1597 for (path = 0; path < pathbound; path++) {
1598 rtl_set_rfreg(hw, (enum radio_path)path, 0xd,
1599 MASKDWORD, reg_d[path]);
1600
1601 if (path == RF90_PATH_B) {
1602 rtl_set_rfreg(hw, RF90_PATH_A, 0x10, MASKDWORD,
1603 0x1000f);
1604 rtl_set_rfreg(hw, RF90_PATH_A, 0x11, MASKDWORD,
1605 0x20101);
1606 }
1607
1608 if (apk_result[path][1] > 6)
1609 apk_result[path][1] = 6;
1610 }
1611
1612 for (path = 0; path < pathbound; path++) {
1613 rtl_set_rfreg(hw, (enum radio_path)path, 0x3, MASKDWORD,
1614 ((apk_result[path][1] << 15) |
1615 (apk_result[path][1] << 10) |
1616 (apk_result[path][1] << 5) |
1617 apk_result[path][1]));
1618
1619 if (path == RF90_PATH_A)
1620 rtl_set_rfreg(hw, (enum radio_path)path, 0x4, MASKDWORD,
1621 ((apk_result[path][1] << 15) |
1622 (apk_result[path][1] << 10) |
1623 (0x00 << 5) | 0x05));
1624 else
1625 rtl_set_rfreg(hw, (enum radio_path)path, 0x4, MASKDWORD,
1626 ((apk_result[path][1] << 15) |
1627 (apk_result[path][1] << 10) |
1628 (0x02 << 5) | 0x05));
1629
1630 rtl_set_rfreg(hw, (enum radio_path)path, 0xe, MASKDWORD,
1631 ((0x08 << 15) | (0x08 << 10) | (0x08 << 5) |
1632 0x08));
1633
1634 }
1635 rtlphy->b_apk_done = true;
1636 #endif
1637 }
1638
1639 static void _rtl92c_phy_set_rfpath_switch(struct ieee80211_hw *hw,
1640 bool bmain, bool is2t)
1641 {
1642 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1643
1644 if (is_hal_stop(rtlhal)) {
1645 rtl_set_bbreg(hw, REG_LEDCFG0, BIT(23), 0x01);
1646 rtl_set_bbreg(hw, rFPGA0_XAB_RFPARAMETER, BIT(13), 0x01);
1647 }
1648 if (is2t) {
1649 if (bmain)
1650 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
1651 BIT(5) | BIT(6), 0x1);
1652 else
1653 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
1654 BIT(5) | BIT(6), 0x2);
1655 } else {
1656 if (bmain)
1657 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 0x300, 0x2);
1658 else
1659 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 0x300, 0x1);
1660
1661 }
1662
1663 }
1664
1665 #undef IQK_ADDA_REG_NUM
1666 #undef IQK_DELAY_TIME
1667
1668 void rtl92c_phy_iq_calibrate(struct ieee80211_hw *hw, bool recovery)
1669 {
1670 struct rtl_priv *rtlpriv = rtl_priv(hw);
1671 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1672 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1673
1674 long result[4][8];
1675 u8 i, final_candidate;
1676 bool patha_ok, pathb_ok;
1677 long reg_e94, reg_e9c, reg_ea4, reg_eb4, reg_ebc, reg_ec4, reg_tmp = 0;
1678 bool is12simular, is13simular, is23simular;
1679 bool start_conttx = false, singletone = false;
1680 u32 iqk_bb_reg[10] = {
1681 ROFDM0_XARXIQIMBALANCE,
1682 ROFDM0_XBRXIQIMBALANCE,
1683 ROFDM0_ECCATHRESHOLD,
1684 ROFDM0_AGCRSSITABLE,
1685 ROFDM0_XATXIQIMBALANCE,
1686 ROFDM0_XBTXIQIMBALANCE,
1687 ROFDM0_XCTXIQIMBALANCE,
1688 ROFDM0_XCTXAFE,
1689 ROFDM0_XDTXAFE,
1690 ROFDM0_RXIQEXTANTA
1691 };
1692
1693 if (recovery) {
1694 _rtl92c_phy_reload_adda_registers(hw,
1695 iqk_bb_reg,
1696 rtlphy->iqk_bb_backup, 10);
1697 return;
1698 }
1699 if (start_conttx || singletone)
1700 return;
1701 for (i = 0; i < 8; i++) {
1702 result[0][i] = 0;
1703 result[1][i] = 0;
1704 result[2][i] = 0;
1705 result[3][i] = 0;
1706 }
1707 final_candidate = 0xff;
1708 patha_ok = false;
1709 pathb_ok = false;
1710 is12simular = false;
1711 is23simular = false;
1712 is13simular = false;
1713 for (i = 0; i < 3; i++) {
1714 if (IS_92C_SERIAL(rtlhal->version))
1715 _rtl92c_phy_iq_calibrate(hw, result, i, true);
1716 else
1717 _rtl92c_phy_iq_calibrate(hw, result, i, false);
1718 if (i == 1) {
1719 is12simular = _rtl92c_phy_simularity_compare(hw,
1720 result, 0,
1721 1);
1722 if (is12simular) {
1723 final_candidate = 0;
1724 break;
1725 }
1726 }
1727 if (i == 2) {
1728 is13simular = _rtl92c_phy_simularity_compare(hw,
1729 result, 0,
1730 2);
1731 if (is13simular) {
1732 final_candidate = 0;
1733 break;
1734 }
1735 is23simular = _rtl92c_phy_simularity_compare(hw,
1736 result, 1,
1737 2);
1738 if (is23simular)
1739 final_candidate = 1;
1740 else {
1741 for (i = 0; i < 8; i++)
1742 reg_tmp += result[3][i];
1743
1744 if (reg_tmp != 0)
1745 final_candidate = 3;
1746 else
1747 final_candidate = 0xFF;
1748 }
1749 }
1750 }
1751 for (i = 0; i < 4; i++) {
1752 reg_e94 = result[i][0];
1753 reg_e9c = result[i][1];
1754 reg_ea4 = result[i][2];
1755 reg_eb4 = result[i][4];
1756 reg_ebc = result[i][5];
1757 reg_ec4 = result[i][6];
1758 }
1759 if (final_candidate != 0xff) {
1760 rtlphy->reg_e94 = reg_e94 = result[final_candidate][0];
1761 rtlphy->reg_e9c = reg_e9c = result[final_candidate][1];
1762 reg_ea4 = result[final_candidate][2];
1763 rtlphy->reg_eb4 = reg_eb4 = result[final_candidate][4];
1764 rtlphy->reg_ebc = reg_ebc = result[final_candidate][5];
1765 reg_ec4 = result[final_candidate][6];
1766 patha_ok = pathb_ok = true;
1767 } else {
1768 rtlphy->reg_e94 = rtlphy->reg_eb4 = 0x100;
1769 rtlphy->reg_e9c = rtlphy->reg_ebc = 0x0;
1770 }
1771 if (reg_e94 != 0) /*&&(reg_ea4 != 0) */
1772 _rtl92c_phy_path_a_fill_iqk_matrix(hw, patha_ok, result,
1773 final_candidate,
1774 (reg_ea4 == 0));
1775 if (IS_92C_SERIAL(rtlhal->version)) {
1776 if (reg_eb4 != 0) /*&&(reg_ec4 != 0) */
1777 _rtl92c_phy_path_b_fill_iqk_matrix(hw, pathb_ok,
1778 result,
1779 final_candidate,
1780 (reg_ec4 == 0));
1781 }
1782 _rtl92c_phy_save_adda_registers(hw, iqk_bb_reg,
1783 rtlphy->iqk_bb_backup, 10);
1784 }
1785 EXPORT_SYMBOL(rtl92c_phy_iq_calibrate);
1786
1787 void rtl92c_phy_lc_calibrate(struct ieee80211_hw *hw)
1788 {
1789 struct rtl_priv *rtlpriv = rtl_priv(hw);
1790 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1791 bool start_conttx = false, singletone = false;
1792
1793 if (start_conttx || singletone)
1794 return;
1795 if (IS_92C_SERIAL(rtlhal->version))
1796 rtlpriv->cfg->ops->phy_lc_calibrate(hw, true);
1797 else
1798 rtlpriv->cfg->ops->phy_lc_calibrate(hw, false);
1799 }
1800 EXPORT_SYMBOL(rtl92c_phy_lc_calibrate);
1801
1802 void rtl92c_phy_ap_calibrate(struct ieee80211_hw *hw, char delta)
1803 {
1804 struct rtl_priv *rtlpriv = rtl_priv(hw);
1805 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1806 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1807
1808 if (rtlphy->apk_done)
1809 return;
1810 if (IS_92C_SERIAL(rtlhal->version))
1811 _rtl92c_phy_ap_calibrate(hw, delta, true);
1812 else
1813 _rtl92c_phy_ap_calibrate(hw, delta, false);
1814 }
1815 EXPORT_SYMBOL(rtl92c_phy_ap_calibrate);
1816
1817 void rtl92c_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain)
1818 {
1819 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1820
1821 if (IS_92C_SERIAL(rtlhal->version))
1822 _rtl92c_phy_set_rfpath_switch(hw, bmain, true);
1823 else
1824 _rtl92c_phy_set_rfpath_switch(hw, bmain, false);
1825 }
1826 EXPORT_SYMBOL(rtl92c_phy_set_rfpath_switch);
1827
1828 bool rtl92c_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype)
1829 {
1830 struct rtl_priv *rtlpriv = rtl_priv(hw);
1831 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1832 bool postprocessing = false;
1833
1834 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1835 "-->IO Cmd(%#x), set_io_inprogress(%d)\n",
1836 iotype, rtlphy->set_io_inprogress);
1837 do {
1838 switch (iotype) {
1839 case IO_CMD_RESUME_DM_BY_SCAN:
1840 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1841 "[IO CMD] Resume DM after scan\n");
1842 postprocessing = true;
1843 break;
1844 case IO_CMD_PAUSE_DM_BY_SCAN:
1845 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1846 "[IO CMD] Pause DM before scan\n");
1847 postprocessing = true;
1848 break;
1849 default:
1850 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1851 "switch case not processed\n");
1852 break;
1853 }
1854 } while (false);
1855 if (postprocessing && !rtlphy->set_io_inprogress) {
1856 rtlphy->set_io_inprogress = true;
1857 rtlphy->current_io_type = iotype;
1858 } else {
1859 return false;
1860 }
1861 rtl92c_phy_set_io(hw);
1862 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, "<--IO Type(%#x)\n", iotype);
1863 return true;
1864 }
1865 EXPORT_SYMBOL(rtl92c_phy_set_io_cmd);
1866
1867 void rtl92c_phy_set_io(struct ieee80211_hw *hw)
1868 {
1869 struct rtl_priv *rtlpriv = rtl_priv(hw);
1870 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1871 struct dig_t dm_digtable = rtlpriv->dm_digtable;
1872
1873 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1874 "--->Cmd(%#x), set_io_inprogress(%d)\n",
1875 rtlphy->current_io_type, rtlphy->set_io_inprogress);
1876 switch (rtlphy->current_io_type) {
1877 case IO_CMD_RESUME_DM_BY_SCAN:
1878 dm_digtable.cur_igvalue = rtlphy->initgain_backup.xaagccore1;
1879 rtl92c_dm_write_dig(hw);
1880 rtl92c_phy_set_txpower_level(hw, rtlphy->current_channel);
1881 break;
1882 case IO_CMD_PAUSE_DM_BY_SCAN:
1883 rtlphy->initgain_backup.xaagccore1 = dm_digtable.cur_igvalue;
1884 dm_digtable.cur_igvalue = 0x37;
1885 rtl92c_dm_write_dig(hw);
1886 break;
1887 default:
1888 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1889 "switch case not processed\n");
1890 break;
1891 }
1892 rtlphy->set_io_inprogress = false;
1893 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, "<---(%#x)\n",
1894 rtlphy->current_io_type);
1895 }
1896 EXPORT_SYMBOL(rtl92c_phy_set_io);
1897
1898 void rtl92ce_phy_set_rf_on(struct ieee80211_hw *hw)
1899 {
1900 struct rtl_priv *rtlpriv = rtl_priv(hw);
1901
1902 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
1903 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
1904 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
1905 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
1906 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
1907 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
1908 }
1909 EXPORT_SYMBOL(rtl92ce_phy_set_rf_on);
1910
1911 void _rtl92c_phy_set_rf_sleep(struct ieee80211_hw *hw)
1912 {
1913 u32 u4b_tmp;
1914 u8 delay = 5;
1915 struct rtl_priv *rtlpriv = rtl_priv(hw);
1916
1917 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1918 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
1919 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
1920 u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
1921 while (u4b_tmp != 0 && delay > 0) {
1922 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x0);
1923 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
1924 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
1925 u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
1926 delay--;
1927 }
1928 if (delay == 0) {
1929 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
1930 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
1931 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
1932 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
1933 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
1934 "Switch RF timeout !!!\n");
1935 return;
1936 }
1937 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
1938 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22);
1939 }
1940 EXPORT_SYMBOL(_rtl92c_phy_set_rf_sleep);
Linux kernel - Deliverables
This page took 0.720766 seconds and 5 git commands to generate.