1 /******************************************************************************
3 * Copyright(c) 2009-2012 Realtek Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
26 * Larry Finger <Larry.Finger@lwfinger.net>
28 *****************************************************************************/
40 #include "../rtl8192c/fw_common.h"
47 static void _rtl92ce_set_bcn_ctrl_reg(struct ieee80211_hw
*hw
,
48 u8 set_bits
, u8 clear_bits
)
50 struct rtl_pci
*rtlpci
= rtl_pcidev(rtl_pcipriv(hw
));
51 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
53 rtlpci
->reg_bcn_ctrl_val
|= set_bits
;
54 rtlpci
->reg_bcn_ctrl_val
&= ~clear_bits
;
56 rtl_write_byte(rtlpriv
, REG_BCN_CTRL
, (u8
) rtlpci
->reg_bcn_ctrl_val
);
59 static void _rtl92ce_stop_tx_beacon(struct ieee80211_hw
*hw
)
61 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
64 tmp1byte
= rtl_read_byte(rtlpriv
, REG_FWHW_TXQ_CTRL
+ 2);
65 rtl_write_byte(rtlpriv
, REG_FWHW_TXQ_CTRL
+ 2, tmp1byte
& (~BIT(6)));
66 rtl_write_byte(rtlpriv
, REG_TBTT_PROHIBIT
+ 1, 0x64);
67 tmp1byte
= rtl_read_byte(rtlpriv
, REG_TBTT_PROHIBIT
+ 2);
68 tmp1byte
&= ~(BIT(0));
69 rtl_write_byte(rtlpriv
, REG_TBTT_PROHIBIT
+ 2, tmp1byte
);
72 static void _rtl92ce_resume_tx_beacon(struct ieee80211_hw
*hw
)
74 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
77 tmp1byte
= rtl_read_byte(rtlpriv
, REG_FWHW_TXQ_CTRL
+ 2);
78 rtl_write_byte(rtlpriv
, REG_FWHW_TXQ_CTRL
+ 2, tmp1byte
| BIT(6));
79 rtl_write_byte(rtlpriv
, REG_TBTT_PROHIBIT
+ 1, 0xff);
80 tmp1byte
= rtl_read_byte(rtlpriv
, REG_TBTT_PROHIBIT
+ 2);
82 rtl_write_byte(rtlpriv
, REG_TBTT_PROHIBIT
+ 2, tmp1byte
);
85 static void _rtl92ce_enable_bcn_sub_func(struct ieee80211_hw
*hw
)
87 _rtl92ce_set_bcn_ctrl_reg(hw
, 0, BIT(1));
90 static void _rtl92ce_disable_bcn_sub_func(struct ieee80211_hw
*hw
)
92 _rtl92ce_set_bcn_ctrl_reg(hw
, BIT(1), 0);
95 void rtl92ce_get_hw_reg(struct ieee80211_hw
*hw
, u8 variable
, u8
*val
)
97 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
98 struct rtl_ps_ctl
*ppsc
= rtl_psc(rtl_priv(hw
));
99 struct rtl_pci
*rtlpci
= rtl_pcidev(rtl_pcipriv(hw
));
103 *((u32
*) (val
)) = rtlpci
->receive_config
;
105 case HW_VAR_RF_STATE
:
106 *((enum rf_pwrstate
*)(val
)) = ppsc
->rfpwr_state
;
108 case HW_VAR_FWLPS_RF_ON
:{
109 enum rf_pwrstate rfState
;
112 rtlpriv
->cfg
->ops
->get_hw_reg(hw
,
115 if (rfState
== ERFOFF
) {
116 *((bool *) (val
)) = true;
118 val_rcr
= rtl_read_dword(rtlpriv
, REG_RCR
);
119 val_rcr
&= 0x00070000;
121 *((bool *) (val
)) = false;
123 *((bool *) (val
)) = true;
127 case HW_VAR_FW_PSMODE_STATUS
:
128 *((bool *) (val
)) = ppsc
->fw_current_inpsmode
;
130 case HW_VAR_CORRECT_TSF
:{
132 u32
*ptsf_low
= (u32
*)&tsf
;
133 u32
*ptsf_high
= ((u32
*)&tsf
) + 1;
135 *ptsf_high
= rtl_read_dword(rtlpriv
, (REG_TSFTR
+ 4));
136 *ptsf_low
= rtl_read_dword(rtlpriv
, REG_TSFTR
);
138 *((u64
*) (val
)) = tsf
;
143 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
,
144 "switch case not processed\n");
149 void rtl92ce_set_hw_reg(struct ieee80211_hw
*hw
, u8 variable
, u8
*val
)
151 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
152 struct rtl_pci_priv
*rtlpcipriv
= rtl_pcipriv(hw
);
153 struct rtl_pci
*rtlpci
= rtl_pcidev(rtl_pcipriv(hw
));
154 struct rtl_mac
*mac
= rtl_mac(rtl_priv(hw
));
155 struct rtl_hal
*rtlhal
= rtl_hal(rtl_priv(hw
));
156 struct rtl_efuse
*rtlefuse
= rtl_efuse(rtl_priv(hw
));
157 struct rtl_ps_ctl
*ppsc
= rtl_psc(rtl_priv(hw
));
161 case HW_VAR_ETHER_ADDR
:{
162 for (idx
= 0; idx
< ETH_ALEN
; idx
++) {
163 rtl_write_byte(rtlpriv
, (REG_MACID
+ idx
),
168 case HW_VAR_BASIC_RATE
:{
169 u16 rate_cfg
= ((u16
*) val
)[0];
173 rtl_write_byte(rtlpriv
, REG_RRSR
, rate_cfg
& 0xff);
174 rtl_write_byte(rtlpriv
, REG_RRSR
+ 1,
175 (rate_cfg
>> 8) & 0xff);
176 while (rate_cfg
> 0x1) {
177 rate_cfg
= (rate_cfg
>> 1);
180 rtl_write_byte(rtlpriv
, REG_INIRTS_RATE_SEL
,
185 for (idx
= 0; idx
< ETH_ALEN
; idx
++) {
186 rtl_write_byte(rtlpriv
, (REG_BSSID
+ idx
),
192 rtl_write_byte(rtlpriv
, REG_SIFS_CTX
+ 1, val
[0]);
193 rtl_write_byte(rtlpriv
, REG_SIFS_TRX
+ 1, val
[1]);
195 rtl_write_byte(rtlpriv
, REG_SPEC_SIFS
+ 1, val
[0]);
196 rtl_write_byte(rtlpriv
, REG_MAC_SPEC_SIFS
+ 1, val
[0]);
199 rtl_write_word(rtlpriv
, REG_RESP_SIFS_OFDM
,
202 rtl_write_word(rtlpriv
, REG_RESP_SIFS_OFDM
,
206 case HW_VAR_SLOT_TIME
:{
209 RT_TRACE(rtlpriv
, COMP_MLME
, DBG_LOUD
,
210 "HW_VAR_SLOT_TIME %x\n", val
[0]);
212 rtl_write_byte(rtlpriv
, REG_SLOT
, val
[0]);
214 for (e_aci
= 0; e_aci
< AC_MAX
; e_aci
++) {
215 rtlpriv
->cfg
->ops
->set_hw_reg(hw
,
221 case HW_VAR_ACK_PREAMBLE
:{
223 u8 short_preamble
= (bool)*val
;
224 reg_tmp
= (mac
->cur_40_prime_sc
) << 5;
228 rtl_write_byte(rtlpriv
, REG_RRSR
+ 2, reg_tmp
);
231 case HW_VAR_AMPDU_MIN_SPACE
:{
232 u8 min_spacing_to_set
;
235 min_spacing_to_set
= *val
;
236 if (min_spacing_to_set
<= 7) {
239 if (min_spacing_to_set
< sec_min_space
)
240 min_spacing_to_set
= sec_min_space
;
242 mac
->min_space_cfg
= ((mac
->min_space_cfg
&
246 *val
= min_spacing_to_set
;
248 RT_TRACE(rtlpriv
, COMP_MLME
, DBG_LOUD
,
249 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
252 rtl_write_byte(rtlpriv
, REG_AMPDU_MIN_SPACE
,
257 case HW_VAR_SHORTGI_DENSITY
:{
260 density_to_set
= *val
;
261 mac
->min_space_cfg
|= (density_to_set
<< 3);
263 RT_TRACE(rtlpriv
, COMP_MLME
, DBG_LOUD
,
264 "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
267 rtl_write_byte(rtlpriv
, REG_AMPDU_MIN_SPACE
,
272 case HW_VAR_AMPDU_FACTOR
:{
273 u8 regtoset_normal
[4] = {0x41, 0xa8, 0x72, 0xb9};
274 u8 regtoset_bt
[4] = {0x31, 0x74, 0x42, 0x97};
277 u8
*p_regtoset
= NULL
;
280 if ((rtlpcipriv
->bt_coexist
.bt_coexistence
) &&
281 (rtlpcipriv
->bt_coexist
.bt_coexist_type
==
283 p_regtoset
= regtoset_bt
;
285 p_regtoset
= regtoset_normal
;
287 factor_toset
= *(val
);
288 if (factor_toset
<= 3) {
289 factor_toset
= (1 << (factor_toset
+ 2));
290 if (factor_toset
> 0xf)
293 for (index
= 0; index
< 4; index
++) {
294 if ((p_regtoset
[index
] & 0xf0) >
297 (p_regtoset
[index
] & 0x0f) |
300 if ((p_regtoset
[index
] & 0x0f) >
303 (p_regtoset
[index
] & 0xf0) |
306 rtl_write_byte(rtlpriv
,
307 (REG_AGGLEN_LMT
+ index
),
312 RT_TRACE(rtlpriv
, COMP_MLME
, DBG_LOUD
,
313 "Set HW_VAR_AMPDU_FACTOR: %#x\n",
318 case HW_VAR_AC_PARAM
:{
320 rtl92c_dm_init_edca_turbo(hw
);
322 if (rtlpci
->acm_method
!= eAcmWay2_SW
)
323 rtlpriv
->cfg
->ops
->set_hw_reg(hw
,
328 case HW_VAR_ACM_CTRL
:{
330 union aci_aifsn
*p_aci_aifsn
=
331 (union aci_aifsn
*)(&(mac
->ac
[0].aifs
));
332 u8 acm
= p_aci_aifsn
->f
.acm
;
333 u8 acm_ctrl
= rtl_read_byte(rtlpriv
, REG_ACMHWCTRL
);
336 acm_ctrl
| ((rtlpci
->acm_method
== 2) ? 0x0 : 0x1);
341 acm_ctrl
|= AcmHw_BeqEn
;
344 acm_ctrl
|= AcmHw_ViqEn
;
347 acm_ctrl
|= AcmHw_VoqEn
;
350 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_WARNING
,
351 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
358 acm_ctrl
&= (~AcmHw_BeqEn
);
361 acm_ctrl
&= (~AcmHw_ViqEn
);
364 acm_ctrl
&= (~AcmHw_BeqEn
);
367 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
,
368 "switch case not processed\n");
373 RT_TRACE(rtlpriv
, COMP_QOS
, DBG_TRACE
,
374 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
376 rtl_write_byte(rtlpriv
, REG_ACMHWCTRL
, acm_ctrl
);
380 rtl_write_dword(rtlpriv
, REG_RCR
, ((u32
*) (val
))[0]);
381 rtlpci
->receive_config
= ((u32
*) (val
))[0];
384 case HW_VAR_RETRY_LIMIT
:{
385 u8 retry_limit
= val
[0];
387 rtl_write_word(rtlpriv
, REG_RL
,
388 retry_limit
<< RETRY_LIMIT_SHORT_SHIFT
|
389 retry_limit
<< RETRY_LIMIT_LONG_SHIFT
);
392 case HW_VAR_DUAL_TSF_RST
:
393 rtl_write_byte(rtlpriv
, REG_DUAL_TSF_RST
, (BIT(0) | BIT(1)));
395 case HW_VAR_EFUSE_BYTES
:
396 rtlefuse
->efuse_usedbytes
= *((u16
*) val
);
398 case HW_VAR_EFUSE_USAGE
:
399 rtlefuse
->efuse_usedpercentage
= *val
;
402 rtl92c_phy_set_io_cmd(hw
, (*(enum io_type
*)val
));
404 case HW_VAR_WPA_CONFIG
:
405 rtl_write_byte(rtlpriv
, REG_SECCFG
, *val
);
407 case HW_VAR_SET_RPWM
:{
410 rpwm_val
= rtl_read_byte(rtlpriv
, REG_PCIE_HRPWM
);
413 if (rpwm_val
& BIT(7)) {
414 rtl_write_byte(rtlpriv
, REG_PCIE_HRPWM
, *val
);
416 rtl_write_byte(rtlpriv
, REG_PCIE_HRPWM
,
422 case HW_VAR_H2C_FW_PWRMODE
:{
425 if ((psmode
!= FW_PS_ACTIVE_MODE
) &&
426 (!IS_92C_SERIAL(rtlhal
->version
))) {
427 rtl92c_dm_rf_saving(hw
, true);
430 rtl92c_set_fw_pwrmode_cmd(hw
, *val
);
433 case HW_VAR_FW_PSMODE_STATUS
:
434 ppsc
->fw_current_inpsmode
= *((bool *) val
);
436 case HW_VAR_H2C_FW_JOINBSSRPT
:{
438 u8 tmp_regcr
, tmp_reg422
;
439 bool recover
= false;
441 if (mstatus
== RT_MEDIA_CONNECT
) {
442 rtlpriv
->cfg
->ops
->set_hw_reg(hw
, HW_VAR_AID
,
445 tmp_regcr
= rtl_read_byte(rtlpriv
, REG_CR
+ 1);
446 rtl_write_byte(rtlpriv
, REG_CR
+ 1,
447 (tmp_regcr
| BIT(0)));
449 _rtl92ce_set_bcn_ctrl_reg(hw
, 0, BIT(3));
450 _rtl92ce_set_bcn_ctrl_reg(hw
, BIT(4), 0);
453 rtl_read_byte(rtlpriv
,
454 REG_FWHW_TXQ_CTRL
+ 2);
455 if (tmp_reg422
& BIT(6))
457 rtl_write_byte(rtlpriv
, REG_FWHW_TXQ_CTRL
+ 2,
458 tmp_reg422
& (~BIT(6)));
460 rtl92c_set_fw_rsvdpagepkt(hw
, 0);
462 _rtl92ce_set_bcn_ctrl_reg(hw
, BIT(3), 0);
463 _rtl92ce_set_bcn_ctrl_reg(hw
, 0, BIT(4));
466 rtl_write_byte(rtlpriv
,
467 REG_FWHW_TXQ_CTRL
+ 2,
471 rtl_write_byte(rtlpriv
, REG_CR
+ 1,
472 (tmp_regcr
& ~(BIT(0))));
474 rtl92c_set_fw_joinbss_report_cmd(hw
, *val
);
480 u2btmp
= rtl_read_word(rtlpriv
, REG_BCN_PSR_RPT
);
482 rtl_write_word(rtlpriv
, REG_BCN_PSR_RPT
, (u2btmp
|
487 case HW_VAR_CORRECT_TSF
:{
488 u8 btype_ibss
= val
[0];
491 _rtl92ce_stop_tx_beacon(hw
);
493 _rtl92ce_set_bcn_ctrl_reg(hw
, 0, BIT(3));
495 rtl_write_dword(rtlpriv
, REG_TSFTR
,
496 (u32
) (mac
->tsf
& 0xffffffff));
497 rtl_write_dword(rtlpriv
, REG_TSFTR
+ 4,
498 (u32
) ((mac
->tsf
>> 32) & 0xffffffff));
500 _rtl92ce_set_bcn_ctrl_reg(hw
, BIT(3), 0);
503 _rtl92ce_resume_tx_beacon(hw
);
509 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
,
510 "switch case not processed\n");
515 static bool _rtl92ce_llt_write(struct ieee80211_hw
*hw
, u32 address
, u32 data
)
517 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
520 u32 value
= _LLT_INIT_ADDR(address
) |
521 _LLT_INIT_DATA(data
) | _LLT_OP(_LLT_WRITE_ACCESS
);
523 rtl_write_dword(rtlpriv
, REG_LLT_INIT
, value
);
526 value
= rtl_read_dword(rtlpriv
, REG_LLT_INIT
);
527 if (_LLT_NO_ACTIVE
== _LLT_OP_VALUE(value
))
530 if (count
> POLLING_LLT_THRESHOLD
) {
531 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
,
532 "Failed to polling write LLT done at address %d!\n",
542 static bool _rtl92ce_llt_table_init(struct ieee80211_hw
*hw
)
544 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
553 #elif LLT_CONFIG == 2
556 #elif LLT_CONFIG == 3
559 #elif LLT_CONFIG == 4
562 #elif LLT_CONFIG == 5
568 rtl_write_byte(rtlpriv
, REG_RQPN_NPQ
, 0x1c);
569 rtl_write_dword(rtlpriv
, REG_RQPN
, 0x80a71c1c);
570 #elif LLT_CONFIG == 2
571 rtl_write_dword(rtlpriv
, REG_RQPN
, 0x845B1010);
572 #elif LLT_CONFIG == 3
573 rtl_write_dword(rtlpriv
, REG_RQPN
, 0x84838484);
574 #elif LLT_CONFIG == 4
575 rtl_write_dword(rtlpriv
, REG_RQPN
, 0x80bd1c1c);
576 #elif LLT_CONFIG == 5
577 rtl_write_word(rtlpriv
, REG_RQPN_NPQ
, 0x0000);
579 rtl_write_dword(rtlpriv
, REG_RQPN
, 0x80b01c29);
582 rtl_write_dword(rtlpriv
, REG_TRXFF_BNDY
, (0x27FF0000 | txpktbuf_bndy
));
583 rtl_write_byte(rtlpriv
, REG_TDECTRL
+ 1, txpktbuf_bndy
);
585 rtl_write_byte(rtlpriv
, REG_TXPKTBUF_BCNQ_BDNY
, txpktbuf_bndy
);
586 rtl_write_byte(rtlpriv
, REG_TXPKTBUF_MGQ_BDNY
, txpktbuf_bndy
);
588 rtl_write_byte(rtlpriv
, 0x45D, txpktbuf_bndy
);
589 rtl_write_byte(rtlpriv
, REG_PBP
, 0x11);
590 rtl_write_byte(rtlpriv
, REG_RX_DRVINFO_SZ
, 0x4);
592 for (i
= 0; i
< (txpktbuf_bndy
- 1); i
++) {
593 status
= _rtl92ce_llt_write(hw
, i
, i
+ 1);
598 status
= _rtl92ce_llt_write(hw
, (txpktbuf_bndy
- 1), 0xFF);
602 for (i
= txpktbuf_bndy
; i
< maxPage
; i
++) {
603 status
= _rtl92ce_llt_write(hw
, i
, (i
+ 1));
608 status
= _rtl92ce_llt_write(hw
, maxPage
, txpktbuf_bndy
);
615 static void _rtl92ce_gen_refresh_led_state(struct ieee80211_hw
*hw
)
617 struct rtl_pci_priv
*pcipriv
= rtl_pcipriv(hw
);
618 struct rtl_pci
*rtlpci
= rtl_pcidev(rtl_pcipriv(hw
));
619 struct rtl_ps_ctl
*ppsc
= rtl_psc(rtl_priv(hw
));
620 struct rtl_led
*pLed0
= &(pcipriv
->ledctl
.sw_led0
);
622 if (rtlpci
->up_first_time
)
625 if (ppsc
->rfoff_reason
== RF_CHANGE_BY_IPS
)
626 rtl92ce_sw_led_on(hw
, pLed0
);
627 else if (ppsc
->rfoff_reason
== RF_CHANGE_BY_INIT
)
628 rtl92ce_sw_led_on(hw
, pLed0
);
630 rtl92ce_sw_led_off(hw
, pLed0
);
633 static bool _rtl92ce_init_mac(struct ieee80211_hw
*hw
)
635 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
636 struct rtl_pci_priv
*rtlpcipriv
= rtl_pcipriv(hw
);
637 struct rtl_pci
*rtlpci
= rtl_pcidev(rtl_pcipriv(hw
));
638 struct rtl_hal
*rtlhal
= rtl_hal(rtl_priv(hw
));
640 unsigned char bytetmp
;
641 unsigned short wordtmp
;
644 rtl_write_byte(rtlpriv
, REG_RSV_CTRL
, 0x00);
645 if (rtlpcipriv
->bt_coexist
.bt_coexistence
) {
647 value32
= rtl_read_dword(rtlpriv
, REG_APS_FSMCO
);
648 value32
|= (SOP_ABG
| SOP_AMB
| XOP_BTCK
);
649 rtl_write_dword(rtlpriv
, REG_APS_FSMCO
, value32
);
651 rtl_write_byte(rtlpriv
, REG_SPS0_CTRL
, 0x2b);
652 rtl_write_byte(rtlpriv
, REG_AFE_XTAL_CTRL
, 0x0F);
654 if (rtlpcipriv
->bt_coexist
.bt_coexistence
) {
655 u32 u4b_tmp
= rtl_read_dword(rtlpriv
, REG_AFE_XTAL_CTRL
);
657 u4b_tmp
&= (~0x00024800);
658 rtl_write_dword(rtlpriv
, REG_AFE_XTAL_CTRL
, u4b_tmp
);
661 bytetmp
= rtl_read_byte(rtlpriv
, REG_APS_FSMCO
+ 1) | BIT(0);
664 rtl_write_byte(rtlpriv
, REG_APS_FSMCO
+ 1, bytetmp
);
667 bytetmp
= rtl_read_byte(rtlpriv
, REG_APS_FSMCO
+ 1);
671 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_LOUD
, "reg0xec:%x:%x\n",
672 rtl_read_dword(rtlpriv
, 0xEC), bytetmp
);
674 while ((bytetmp
& BIT(0)) && retry
< 1000) {
677 bytetmp
= rtl_read_byte(rtlpriv
, REG_APS_FSMCO
+ 1);
678 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_LOUD
, "reg0xec:%x:%x\n",
679 rtl_read_dword(rtlpriv
, 0xEC), bytetmp
);
683 rtl_write_word(rtlpriv
, REG_APS_FSMCO
, 0x1012);
685 rtl_write_byte(rtlpriv
, REG_SYS_ISO_CTRL
+ 1, 0x82);
688 if (rtlpcipriv
->bt_coexist
.bt_coexistence
) {
689 bytetmp
= rtl_read_byte(rtlpriv
, REG_AFE_XTAL_CTRL
+2) & 0xfd;
690 rtl_write_byte(rtlpriv
, REG_AFE_XTAL_CTRL
+2, bytetmp
);
693 rtl_write_word(rtlpriv
, REG_CR
, 0x2ff);
695 if (!_rtl92ce_llt_table_init(hw
))
698 rtl_write_dword(rtlpriv
, REG_HISR
, 0xffffffff);
699 rtl_write_byte(rtlpriv
, REG_HISRE
, 0xff);
701 rtl_write_word(rtlpriv
, REG_TRXFF_BNDY
+ 2, 0x27ff);
703 wordtmp
= rtl_read_word(rtlpriv
, REG_TRXDMA_CTRL
);
706 rtl_write_word(rtlpriv
, REG_TRXDMA_CTRL
, wordtmp
);
708 rtl_write_byte(rtlpriv
, REG_FWHW_TXQ_CTRL
+ 1, 0x1F);
709 rtl_write_dword(rtlpriv
, REG_RCR
, rtlpci
->receive_config
);
710 rtl_write_dword(rtlpriv
, REG_TCR
, rtlpci
->transmit_config
);
712 rtl_write_byte(rtlpriv
, 0x4d0, 0x0);
714 rtl_write_dword(rtlpriv
, REG_BCNQ_DESA
,
715 ((u64
) rtlpci
->tx_ring
[BEACON_QUEUE
].dma
) &
717 rtl_write_dword(rtlpriv
, REG_MGQ_DESA
,
718 (u64
) rtlpci
->tx_ring
[MGNT_QUEUE
].dma
&
720 rtl_write_dword(rtlpriv
, REG_VOQ_DESA
,
721 (u64
) rtlpci
->tx_ring
[VO_QUEUE
].dma
& DMA_BIT_MASK(32));
722 rtl_write_dword(rtlpriv
, REG_VIQ_DESA
,
723 (u64
) rtlpci
->tx_ring
[VI_QUEUE
].dma
& DMA_BIT_MASK(32));
724 rtl_write_dword(rtlpriv
, REG_BEQ_DESA
,
725 (u64
) rtlpci
->tx_ring
[BE_QUEUE
].dma
& DMA_BIT_MASK(32));
726 rtl_write_dword(rtlpriv
, REG_BKQ_DESA
,
727 (u64
) rtlpci
->tx_ring
[BK_QUEUE
].dma
& DMA_BIT_MASK(32));
728 rtl_write_dword(rtlpriv
, REG_HQ_DESA
,
729 (u64
) rtlpci
->tx_ring
[HIGH_QUEUE
].dma
&
731 rtl_write_dword(rtlpriv
, REG_RX_DESA
,
732 (u64
) rtlpci
->rx_ring
[RX_MPDU_QUEUE
].dma
&
735 if (IS_92C_SERIAL(rtlhal
->version
))
736 rtl_write_byte(rtlpriv
, REG_PCIE_CTRL_REG
+ 3, 0x77);
738 rtl_write_byte(rtlpriv
, REG_PCIE_CTRL_REG
+ 3, 0x22);
740 rtl_write_dword(rtlpriv
, REG_INT_MIG
, 0);
742 bytetmp
= rtl_read_byte(rtlpriv
, REG_APSD_CTRL
);
743 rtl_write_byte(rtlpriv
, REG_APSD_CTRL
, bytetmp
& ~BIT(6));
746 bytetmp
= rtl_read_byte(rtlpriv
, REG_APSD_CTRL
);
747 } while ((retry
< 200) && (bytetmp
& BIT(7)));
749 _rtl92ce_gen_refresh_led_state(hw
);
751 rtl_write_dword(rtlpriv
, REG_MCUTST_1
, 0x0);
756 static void _rtl92ce_hw_configure(struct ieee80211_hw
*hw
)
758 struct rtl_pci
*rtlpci
= rtl_pcidev(rtl_pcipriv(hw
));
759 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
760 struct rtl_pci_priv
*rtlpcipriv
= rtl_pcipriv(hw
);
764 reg_bw_opmode
= BW_OPMODE_20MHZ
;
765 reg_prsr
= RATE_ALL_CCK
| RATE_ALL_OFDM_AG
;
767 rtl_write_byte(rtlpriv
, REG_INIRTS_RATE_SEL
, 0x8);
769 rtl_write_byte(rtlpriv
, REG_BWOPMODE
, reg_bw_opmode
);
771 rtl_write_dword(rtlpriv
, REG_RRSR
, reg_prsr
);
773 rtl_write_byte(rtlpriv
, REG_SLOT
, 0x09);
775 rtl_write_byte(rtlpriv
, REG_AMPDU_MIN_SPACE
, 0x0);
777 rtl_write_word(rtlpriv
, REG_FWHW_TXQ_CTRL
, 0x1F80);
779 rtl_write_word(rtlpriv
, REG_RL
, 0x0707);
781 rtl_write_dword(rtlpriv
, REG_BAR_MODE_CTRL
, 0x02012802);
783 rtl_write_byte(rtlpriv
, REG_HWSEQ_CTRL
, 0xFF);
785 rtl_write_dword(rtlpriv
, REG_DARFRC
, 0x01000000);
786 rtl_write_dword(rtlpriv
, REG_DARFRC
+ 4, 0x07060504);
787 rtl_write_dword(rtlpriv
, REG_RARFRC
, 0x01000000);
788 rtl_write_dword(rtlpriv
, REG_RARFRC
+ 4, 0x07060504);
790 if ((rtlpcipriv
->bt_coexist
.bt_coexistence
) &&
791 (rtlpcipriv
->bt_coexist
.bt_coexist_type
== BT_CSR_BC4
))
792 rtl_write_dword(rtlpriv
, REG_AGGLEN_LMT
, 0x97427431);
794 rtl_write_dword(rtlpriv
, REG_AGGLEN_LMT
, 0xb972a841);
796 rtl_write_byte(rtlpriv
, REG_ATIMWND
, 0x2);
798 rtl_write_byte(rtlpriv
, REG_BCN_MAX_ERR
, 0xff);
800 rtlpci
->reg_bcn_ctrl_val
= 0x1f;
801 rtl_write_byte(rtlpriv
, REG_BCN_CTRL
, rtlpci
->reg_bcn_ctrl_val
);
803 rtl_write_byte(rtlpriv
, REG_TBTT_PROHIBIT
+ 1, 0xff);
805 rtl_write_byte(rtlpriv
, REG_TBTT_PROHIBIT
+ 1, 0xff);
807 rtl_write_byte(rtlpriv
, REG_PIFS
, 0x1C);
808 rtl_write_byte(rtlpriv
, REG_AGGR_BREAK_TIME
, 0x16);
810 if ((rtlpcipriv
->bt_coexist
.bt_coexistence
) &&
811 (rtlpcipriv
->bt_coexist
.bt_coexist_type
== BT_CSR_BC4
)) {
812 rtl_write_word(rtlpriv
, REG_NAV_PROT_LEN
, 0x0020);
813 rtl_write_word(rtlpriv
, REG_PROT_MODE_CTRL
, 0x0402);
815 rtl_write_word(rtlpriv
, REG_NAV_PROT_LEN
, 0x0020);
816 rtl_write_word(rtlpriv
, REG_NAV_PROT_LEN
, 0x0020);
819 if ((rtlpcipriv
->bt_coexist
.bt_coexistence
) &&
820 (rtlpcipriv
->bt_coexist
.bt_coexist_type
== BT_CSR_BC4
))
821 rtl_write_dword(rtlpriv
, REG_FAST_EDCA_CTRL
, 0x03086666);
823 rtl_write_dword(rtlpriv
, REG_FAST_EDCA_CTRL
, 0x086666);
825 rtl_write_byte(rtlpriv
, REG_ACKTO
, 0x40);
827 rtl_write_word(rtlpriv
, REG_SPEC_SIFS
, 0x1010);
828 rtl_write_word(rtlpriv
, REG_MAC_SPEC_SIFS
, 0x1010);
830 rtl_write_word(rtlpriv
, REG_SIFS_CTX
, 0x1010);
832 rtl_write_word(rtlpriv
, REG_SIFS_TRX
, 0x1010);
834 rtl_write_dword(rtlpriv
, REG_MAR
, 0xffffffff);
835 rtl_write_dword(rtlpriv
, REG_MAR
+ 4, 0xffffffff);
839 static void _rtl92ce_enable_aspm_back_door(struct ieee80211_hw
*hw
)
841 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
842 struct rtl_ps_ctl
*ppsc
= rtl_psc(rtl_priv(hw
));
844 rtl_write_byte(rtlpriv
, 0x34b, 0x93);
845 rtl_write_word(rtlpriv
, 0x350, 0x870c);
846 rtl_write_byte(rtlpriv
, 0x352, 0x1);
848 if (ppsc
->support_backdoor
)
849 rtl_write_byte(rtlpriv
, 0x349, 0x1b);
851 rtl_write_byte(rtlpriv
, 0x349, 0x03);
853 rtl_write_word(rtlpriv
, 0x350, 0x2718);
854 rtl_write_byte(rtlpriv
, 0x352, 0x1);
857 void rtl92ce_enable_hw_security_config(struct ieee80211_hw
*hw
)
859 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
862 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_LOUD
,
863 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
864 rtlpriv
->sec
.pairwise_enc_algorithm
,
865 rtlpriv
->sec
.group_enc_algorithm
);
867 if (rtlpriv
->cfg
->mod_params
->sw_crypto
|| rtlpriv
->sec
.use_sw_sec
) {
868 RT_TRACE(rtlpriv
, COMP_SEC
, DBG_DMESG
,
869 "not open hw encryption\n");
873 sec_reg_value
= SCR_TxEncEnable
| SCR_RxDecEnable
;
875 if (rtlpriv
->sec
.use_defaultkey
) {
876 sec_reg_value
|= SCR_TxUseDK
;
877 sec_reg_value
|= SCR_RxUseDK
;
880 sec_reg_value
|= (SCR_RXBCUSEDK
| SCR_TXBCUSEDK
);
882 rtl_write_byte(rtlpriv
, REG_CR
+ 1, 0x02);
884 RT_TRACE(rtlpriv
, COMP_SEC
, DBG_LOUD
,
885 "The SECR-value %x\n", sec_reg_value
);
887 rtlpriv
->cfg
->ops
->set_hw_reg(hw
, HW_VAR_WPA_CONFIG
, &sec_reg_value
);
891 int rtl92ce_hw_init(struct ieee80211_hw
*hw
)
893 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
894 struct rtl_hal
*rtlhal
= rtl_hal(rtl_priv(hw
));
895 struct rtl_mac
*mac
= rtl_mac(rtl_priv(hw
));
896 struct rtl_phy
*rtlphy
= &(rtlpriv
->phy
);
897 struct rtl_pci
*rtlpci
= rtl_pcidev(rtl_pcipriv(hw
));
898 struct rtl_ps_ctl
*ppsc
= rtl_psc(rtl_priv(hw
));
899 static bool iqk_initialized
; /* initialized to false */
900 bool rtstatus
= true;
905 rtlpci
->being_init_adapter
= true;
906 rtlpriv
->intf_ops
->disable_aspm(hw
);
907 rtstatus
= _rtl92ce_init_mac(hw
);
909 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
, "Init MAC failed\n");
914 err
= rtl92c_download_fw(hw
);
916 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_WARNING
,
917 "Failed to download FW. Init HW without FW now..\n");
922 rtlhal
->last_hmeboxnum
= 0;
923 rtl92c_phy_mac_config(hw
);
924 rtl92c_phy_bb_config(hw
);
925 rtlphy
->rf_mode
= RF_OP_BY_SW_3WIRE
;
926 rtl92c_phy_rf_config(hw
);
927 rtlphy
->rfreg_chnlval
[0] = rtl_get_rfreg(hw
, (enum radio_path
)0,
928 RF_CHNLBW
, RFREG_OFFSET_MASK
);
929 rtlphy
->rfreg_chnlval
[1] = rtl_get_rfreg(hw
, (enum radio_path
)1,
930 RF_CHNLBW
, RFREG_OFFSET_MASK
);
931 rtl_set_bbreg(hw
, RFPGA0_RFMOD
, BCCKEN
, 0x1);
932 rtl_set_bbreg(hw
, RFPGA0_RFMOD
, BOFDMEN
, 0x1);
933 rtl_set_bbreg(hw
, RFPGA0_ANALOGPARAMETER2
, BIT(10), 1);
934 _rtl92ce_hw_configure(hw
);
935 rtl_cam_reset_all_entry(hw
);
936 rtl92ce_enable_hw_security_config(hw
);
938 ppsc
->rfpwr_state
= ERFON
;
940 rtlpriv
->cfg
->ops
->set_hw_reg(hw
, HW_VAR_ETHER_ADDR
, mac
->mac_addr
);
941 _rtl92ce_enable_aspm_back_door(hw
);
942 rtlpriv
->intf_ops
->enable_aspm(hw
);
944 rtl8192ce_bt_hw_init(hw
);
946 if (ppsc
->rfpwr_state
== ERFON
) {
947 rtl92c_phy_set_rfpath_switch(hw
, 1);
948 if (iqk_initialized
) {
949 rtl92c_phy_iq_calibrate(hw
, true);
951 rtl92c_phy_iq_calibrate(hw
, false);
952 iqk_initialized
= true;
955 rtl92c_dm_check_txpower_tracking(hw
);
956 rtl92c_phy_lc_calibrate(hw
);
959 is92c
= IS_92C_SERIAL(rtlhal
->version
);
960 tmp_u1b
= efuse_read_1byte(hw
, 0x1FA);
961 if (!(tmp_u1b
& BIT(0))) {
962 rtl_set_rfreg(hw
, RF90_PATH_A
, 0x15, 0x0F, 0x05);
963 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_TRACE
, "PA BIAS path A\n");
966 if (!(tmp_u1b
& BIT(1)) && is92c
) {
967 rtl_set_rfreg(hw
, RF90_PATH_B
, 0x15, 0x0F, 0x05);
968 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_TRACE
, "PA BIAS path B\n");
971 if (!(tmp_u1b
& BIT(4))) {
972 tmp_u1b
= rtl_read_byte(rtlpriv
, 0x16);
974 rtl_write_byte(rtlpriv
, 0x16, tmp_u1b
| 0x80);
976 rtl_write_byte(rtlpriv
, 0x16, tmp_u1b
| 0x90);
977 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_TRACE
, "under 1.5V\n");
980 rtlpci
->being_init_adapter
= false;
984 static enum version_8192c
_rtl92ce_read_chip_version(struct ieee80211_hw
*hw
)
986 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
987 struct rtl_phy
*rtlphy
= &(rtlpriv
->phy
);
988 enum version_8192c version
= VERSION_UNKNOWN
;
990 const char *versionid
;
992 value32
= rtl_read_dword(rtlpriv
, REG_SYS_CFG
);
993 if (value32
& TRP_VAUX_EN
) {
994 version
= (value32
& TYPE_ID
) ? VERSION_A_CHIP_92C
:
997 version
= (value32
& TYPE_ID
) ? VERSION_B_CHIP_92C
:
1002 case VERSION_B_CHIP_92C
:
1003 versionid
= "B_CHIP_92C";
1005 case VERSION_B_CHIP_88C
:
1006 versionid
= "B_CHIP_88C";
1008 case VERSION_A_CHIP_92C
:
1009 versionid
= "A_CHIP_92C";
1011 case VERSION_A_CHIP_88C
:
1012 versionid
= "A_CHIP_88C";
1015 versionid
= "Unknown. Bug?";
1019 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_TRACE
,
1020 "Chip Version ID: %s\n", versionid
);
1022 switch (version
& 0x3) {
1024 rtlphy
->rf_type
= RF_1T1R
;
1027 rtlphy
->rf_type
= RF_2T2R
;
1030 rtlphy
->rf_type
= RF_1T2R
;
1033 rtlphy
->rf_type
= RF_1T1R
;
1034 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
,
1035 "ERROR RF_Type is set!!\n");
1039 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_LOUD
, "Chip RF Type: %s\n",
1040 rtlphy
->rf_type
== RF_2T2R
? "RF_2T2R" : "RF_1T1R");
1045 static int _rtl92ce_set_media_status(struct ieee80211_hw
*hw
,
1046 enum nl80211_iftype type
)
1048 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1049 u8 bt_msr
= rtl_read_byte(rtlpriv
, MSR
);
1050 enum led_ctl_mode ledaction
= LED_CTL_NO_LINK
;
1053 if (type
== NL80211_IFTYPE_UNSPECIFIED
||
1054 type
== NL80211_IFTYPE_STATION
) {
1055 _rtl92ce_stop_tx_beacon(hw
);
1056 _rtl92ce_enable_bcn_sub_func(hw
);
1057 } else if (type
== NL80211_IFTYPE_ADHOC
|| type
== NL80211_IFTYPE_AP
) {
1058 _rtl92ce_resume_tx_beacon(hw
);
1059 _rtl92ce_disable_bcn_sub_func(hw
);
1061 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_WARNING
,
1062 "Set HW_VAR_MEDIA_STATUS: No such media status(%x)\n",
1067 case NL80211_IFTYPE_UNSPECIFIED
:
1068 bt_msr
|= MSR_NOLINK
;
1069 ledaction
= LED_CTL_LINK
;
1070 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_TRACE
,
1071 "Set Network type to NO LINK!\n");
1073 case NL80211_IFTYPE_ADHOC
:
1074 bt_msr
|= MSR_ADHOC
;
1075 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_TRACE
,
1076 "Set Network type to Ad Hoc!\n");
1078 case NL80211_IFTYPE_STATION
:
1079 bt_msr
|= MSR_INFRA
;
1080 ledaction
= LED_CTL_LINK
;
1081 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_TRACE
,
1082 "Set Network type to STA!\n");
1084 case NL80211_IFTYPE_AP
:
1086 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_TRACE
,
1087 "Set Network type to AP!\n");
1090 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
,
1091 "Network type %d not supported!\n", type
);
1097 rtl_write_byte(rtlpriv
, (MSR
), bt_msr
);
1098 rtlpriv
->cfg
->ops
->led_control(hw
, ledaction
);
1099 if ((bt_msr
& 0xfc) == MSR_AP
)
1100 rtl_write_byte(rtlpriv
, REG_BCNTCFG
+ 1, 0x00);
1102 rtl_write_byte(rtlpriv
, REG_BCNTCFG
+ 1, 0x66);
1106 void rtl92ce_set_check_bssid(struct ieee80211_hw
*hw
, bool check_bssid
)
1108 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1109 u32 reg_rcr
= rtl_read_dword(rtlpriv
, REG_RCR
);
1111 if (rtlpriv
->psc
.rfpwr_state
!= ERFON
)
1115 reg_rcr
|= (RCR_CBSSID_DATA
| RCR_CBSSID_BCN
);
1116 rtlpriv
->cfg
->ops
->set_hw_reg(hw
, HW_VAR_RCR
,
1118 _rtl92ce_set_bcn_ctrl_reg(hw
, 0, BIT(4));
1119 } else if (!check_bssid
) {
1120 reg_rcr
&= (~(RCR_CBSSID_DATA
| RCR_CBSSID_BCN
));
1121 _rtl92ce_set_bcn_ctrl_reg(hw
, BIT(4), 0);
1122 rtlpriv
->cfg
->ops
->set_hw_reg(hw
,
1123 HW_VAR_RCR
, (u8
*) (®_rcr
));
1128 int rtl92ce_set_network_type(struct ieee80211_hw
*hw
, enum nl80211_iftype type
)
1130 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1132 if (_rtl92ce_set_media_status(hw
, type
))
1135 if (rtlpriv
->mac80211
.link_state
== MAC80211_LINKED
) {
1136 if (type
!= NL80211_IFTYPE_AP
)
1137 rtl92ce_set_check_bssid(hw
, true);
1139 rtl92ce_set_check_bssid(hw
, false);
1145 /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */
1146 void rtl92ce_set_qos(struct ieee80211_hw
*hw
, int aci
)
1148 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1149 rtl92c_dm_init_edca_turbo(hw
);
1152 rtl_write_dword(rtlpriv
, REG_EDCA_BK_PARAM
, 0xa44f);
1155 /* rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, u4b_ac_param); */
1158 rtl_write_dword(rtlpriv
, REG_EDCA_VI_PARAM
, 0x5e4322);
1161 rtl_write_dword(rtlpriv
, REG_EDCA_VO_PARAM
, 0x2f3222);
1164 RT_ASSERT(false, "invalid aci: %d !\n", aci
);
1169 void rtl92ce_enable_interrupt(struct ieee80211_hw
*hw
)
1171 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1172 struct rtl_pci
*rtlpci
= rtl_pcidev(rtl_pcipriv(hw
));
1174 rtl_write_dword(rtlpriv
, REG_HIMR
, rtlpci
->irq_mask
[0] & 0xFFFFFFFF);
1175 rtl_write_dword(rtlpriv
, REG_HIMRE
, rtlpci
->irq_mask
[1] & 0xFFFFFFFF);
1178 void rtl92ce_disable_interrupt(struct ieee80211_hw
*hw
)
1180 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1181 struct rtl_pci
*rtlpci
= rtl_pcidev(rtl_pcipriv(hw
));
1183 rtl_write_dword(rtlpriv
, REG_HIMR
, IMR8190_DISABLED
);
1184 rtl_write_dword(rtlpriv
, REG_HIMRE
, IMR8190_DISABLED
);
1185 synchronize_irq(rtlpci
->pdev
->irq
);
1188 static void _rtl92ce_poweroff_adapter(struct ieee80211_hw
*hw
)
1190 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1191 struct rtl_pci_priv
*rtlpcipriv
= rtl_pcipriv(hw
);
1195 rtlpriv
->intf_ops
->enable_aspm(hw
);
1196 rtl_write_byte(rtlpriv
, REG_TXPAUSE
, 0xFF);
1197 rtl_set_rfreg(hw
, RF90_PATH_A
, 0x00, RFREG_OFFSET_MASK
, 0x00);
1198 rtl_write_byte(rtlpriv
, REG_RF_CTRL
, 0x00);
1199 rtl_write_byte(rtlpriv
, REG_APSD_CTRL
, 0x40);
1200 rtl_write_byte(rtlpriv
, REG_SYS_FUNC_EN
, 0xE2);
1201 rtl_write_byte(rtlpriv
, REG_SYS_FUNC_EN
, 0xE0);
1202 if (rtl_read_byte(rtlpriv
, REG_MCUFWDL
) & BIT(7))
1203 rtl92c_firmware_selfreset(hw
);
1204 rtl_write_byte(rtlpriv
, REG_SYS_FUNC_EN
+ 1, 0x51);
1205 rtl_write_byte(rtlpriv
, REG_MCUFWDL
, 0x00);
1206 rtl_write_dword(rtlpriv
, REG_GPIO_PIN_CTRL
, 0x00000000);
1207 u1b_tmp
= rtl_read_byte(rtlpriv
, REG_GPIO_PIN_CTRL
);
1208 if ((rtlpcipriv
->bt_coexist
.bt_coexistence
) &&
1209 ((rtlpcipriv
->bt_coexist
.bt_coexist_type
== BT_CSR_BC4
) ||
1210 (rtlpcipriv
->bt_coexist
.bt_coexist_type
== BT_CSR_BC8
))) {
1211 rtl_write_dword(rtlpriv
, REG_GPIO_PIN_CTRL
, 0x00F30000 |
1214 rtl_write_dword(rtlpriv
, REG_GPIO_PIN_CTRL
, 0x00FF0000 |
1217 rtl_write_word(rtlpriv
, REG_GPIO_IO_SEL
, 0x0790);
1218 rtl_write_word(rtlpriv
, REG_LEDCFG0
, 0x8080);
1219 rtl_write_byte(rtlpriv
, REG_AFE_PLL_CTRL
, 0x80);
1220 rtl_write_byte(rtlpriv
, REG_SPS0_CTRL
, 0x23);
1221 if (rtlpcipriv
->bt_coexist
.bt_coexistence
) {
1222 u4b_tmp
= rtl_read_dword(rtlpriv
, REG_AFE_XTAL_CTRL
);
1223 u4b_tmp
|= 0x03824800;
1224 rtl_write_dword(rtlpriv
, REG_AFE_XTAL_CTRL
, u4b_tmp
);
1226 rtl_write_dword(rtlpriv
, REG_AFE_XTAL_CTRL
, 0x0e);
1229 rtl_write_byte(rtlpriv
, REG_RSV_CTRL
, 0x0e);
1230 rtl_write_byte(rtlpriv
, REG_APS_FSMCO
+ 1, 0x10);
1233 void rtl92ce_card_disable(struct ieee80211_hw
*hw
)
1235 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1236 struct rtl_ps_ctl
*ppsc
= rtl_psc(rtl_priv(hw
));
1237 struct rtl_pci
*rtlpci
= rtl_pcidev(rtl_pcipriv(hw
));
1238 struct rtl_mac
*mac
= rtl_mac(rtl_priv(hw
));
1239 enum nl80211_iftype opmode
;
1241 mac
->link_state
= MAC80211_NOLINK
;
1242 opmode
= NL80211_IFTYPE_UNSPECIFIED
;
1243 _rtl92ce_set_media_status(hw
, opmode
);
1244 if (rtlpci
->driver_is_goingto_unload
||
1245 ppsc
->rfoff_reason
> RF_CHANGE_BY_PS
)
1246 rtlpriv
->cfg
->ops
->led_control(hw
, LED_CTL_POWER_OFF
);
1247 RT_SET_PS_LEVEL(ppsc
, RT_RF_OFF_LEVL_HALT_NIC
);
1248 _rtl92ce_poweroff_adapter(hw
);
1251 void rtl92ce_interrupt_recognized(struct ieee80211_hw
*hw
,
1252 u32
*p_inta
, u32
*p_intb
)
1254 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1255 struct rtl_pci
*rtlpci
= rtl_pcidev(rtl_pcipriv(hw
));
1257 *p_inta
= rtl_read_dword(rtlpriv
, ISR
) & rtlpci
->irq_mask
[0];
1258 rtl_write_dword(rtlpriv
, ISR
, *p_inta
);
1261 * *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1];
1262 * rtl_write_dword(rtlpriv, ISR + 4, *p_intb);
1266 void rtl92ce_set_beacon_related_registers(struct ieee80211_hw
*hw
)
1269 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1270 struct rtl_mac
*mac
= rtl_mac(rtl_priv(hw
));
1271 u16 bcn_interval
, atim_window
;
1273 bcn_interval
= mac
->beacon_interval
;
1274 atim_window
= 2; /*FIX MERGE */
1275 rtl92ce_disable_interrupt(hw
);
1276 rtl_write_word(rtlpriv
, REG_ATIMWND
, atim_window
);
1277 rtl_write_word(rtlpriv
, REG_BCN_INTERVAL
, bcn_interval
);
1278 rtl_write_word(rtlpriv
, REG_BCNTCFG
, 0x660f);
1279 rtl_write_byte(rtlpriv
, REG_RXTSF_OFFSET_CCK
, 0x18);
1280 rtl_write_byte(rtlpriv
, REG_RXTSF_OFFSET_OFDM
, 0x18);
1281 rtl_write_byte(rtlpriv
, 0x606, 0x30);
1282 rtl92ce_enable_interrupt(hw
);
1285 void rtl92ce_set_beacon_interval(struct ieee80211_hw
*hw
)
1287 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1288 struct rtl_mac
*mac
= rtl_mac(rtl_priv(hw
));
1289 u16 bcn_interval
= mac
->beacon_interval
;
1291 RT_TRACE(rtlpriv
, COMP_BEACON
, DBG_DMESG
,
1292 "beacon_interval:%d\n", bcn_interval
);
1293 rtl92ce_disable_interrupt(hw
);
1294 rtl_write_word(rtlpriv
, REG_BCN_INTERVAL
, bcn_interval
);
1295 rtl92ce_enable_interrupt(hw
);
1298 void rtl92ce_update_interrupt_mask(struct ieee80211_hw
*hw
,
1299 u32 add_msr
, u32 rm_msr
)
1301 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1302 struct rtl_pci
*rtlpci
= rtl_pcidev(rtl_pcipriv(hw
));
1304 RT_TRACE(rtlpriv
, COMP_INTR
, DBG_LOUD
, "add_msr:%x, rm_msr:%x\n",
1308 rtlpci
->irq_mask
[0] |= add_msr
;
1310 rtlpci
->irq_mask
[0] &= (~rm_msr
);
1311 rtl92ce_disable_interrupt(hw
);
1312 rtl92ce_enable_interrupt(hw
);
1315 static void _rtl92ce_read_txpower_info_from_hwpg(struct ieee80211_hw
*hw
,
1319 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1320 struct rtl_efuse
*rtlefuse
= rtl_efuse(rtl_priv(hw
));
1321 u8 rf_path
, index
, tempval
;
1324 for (rf_path
= 0; rf_path
< 2; rf_path
++) {
1325 for (i
= 0; i
< 3; i
++) {
1326 if (!autoload_fail
) {
1328 eeprom_chnlarea_txpwr_cck
[rf_path
][i
] =
1329 hwinfo
[EEPROM_TXPOWERCCK
+ rf_path
* 3 + i
];
1331 eeprom_chnlarea_txpwr_ht40_1s
[rf_path
][i
] =
1332 hwinfo
[EEPROM_TXPOWERHT40_1S
+ rf_path
* 3 +
1336 eeprom_chnlarea_txpwr_cck
[rf_path
][i
] =
1337 EEPROM_DEFAULT_TXPOWERLEVEL
;
1339 eeprom_chnlarea_txpwr_ht40_1s
[rf_path
][i
] =
1340 EEPROM_DEFAULT_TXPOWERLEVEL
;
1345 for (i
= 0; i
< 3; i
++) {
1347 tempval
= hwinfo
[EEPROM_TXPOWERHT40_2SDIFF
+ i
];
1349 tempval
= EEPROM_DEFAULT_HT40_2SDIFF
;
1350 rtlefuse
->eeprom_chnlarea_txpwr_ht40_2sdiif
[RF90_PATH_A
][i
] =
1352 rtlefuse
->eeprom_chnlarea_txpwr_ht40_2sdiif
[RF90_PATH_B
][i
] =
1353 ((tempval
& 0xf0) >> 4);
1356 for (rf_path
= 0; rf_path
< 2; rf_path
++)
1357 for (i
= 0; i
< 3; i
++)
1358 RTPRINT(rtlpriv
, FINIT
, INIT_EEPROM
,
1359 "RF(%d) EEPROM CCK Area(%d) = 0x%x\n",
1362 eeprom_chnlarea_txpwr_cck
[rf_path
][i
]);
1363 for (rf_path
= 0; rf_path
< 2; rf_path
++)
1364 for (i
= 0; i
< 3; i
++)
1365 RTPRINT(rtlpriv
, FINIT
, INIT_EEPROM
,
1366 "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
1369 eeprom_chnlarea_txpwr_ht40_1s
[rf_path
][i
]);
1370 for (rf_path
= 0; rf_path
< 2; rf_path
++)
1371 for (i
= 0; i
< 3; i
++)
1372 RTPRINT(rtlpriv
, FINIT
, INIT_EEPROM
,
1373 "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
1376 eeprom_chnlarea_txpwr_ht40_2sdiif
[rf_path
][i
]);
1378 for (rf_path
= 0; rf_path
< 2; rf_path
++) {
1379 for (i
= 0; i
< 14; i
++) {
1380 index
= _rtl92c_get_chnl_group((u8
) i
);
1382 rtlefuse
->txpwrlevel_cck
[rf_path
][i
] =
1383 rtlefuse
->eeprom_chnlarea_txpwr_cck
[rf_path
][index
];
1384 rtlefuse
->txpwrlevel_ht40_1s
[rf_path
][i
] =
1386 eeprom_chnlarea_txpwr_ht40_1s
[rf_path
][index
];
1389 eeprom_chnlarea_txpwr_ht40_1s
[rf_path
][index
] -
1391 eeprom_chnlarea_txpwr_ht40_2sdiif
[rf_path
][index
])
1393 rtlefuse
->txpwrlevel_ht40_2s
[rf_path
][i
] =
1395 eeprom_chnlarea_txpwr_ht40_1s
[rf_path
]
1398 eeprom_chnlarea_txpwr_ht40_2sdiif
[rf_path
]
1401 rtlefuse
->txpwrlevel_ht40_2s
[rf_path
][i
] = 0;
1405 for (i
= 0; i
< 14; i
++) {
1406 RTPRINT(rtlpriv
, FINIT
, INIT_TxPower
,
1407 "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n",
1409 rtlefuse
->txpwrlevel_cck
[rf_path
][i
],
1410 rtlefuse
->txpwrlevel_ht40_1s
[rf_path
][i
],
1411 rtlefuse
->txpwrlevel_ht40_2s
[rf_path
][i
]);
1415 for (i
= 0; i
< 3; i
++) {
1416 if (!autoload_fail
) {
1417 rtlefuse
->eeprom_pwrlimit_ht40
[i
] =
1418 hwinfo
[EEPROM_TXPWR_GROUP
+ i
];
1419 rtlefuse
->eeprom_pwrlimit_ht20
[i
] =
1420 hwinfo
[EEPROM_TXPWR_GROUP
+ 3 + i
];
1422 rtlefuse
->eeprom_pwrlimit_ht40
[i
] = 0;
1423 rtlefuse
->eeprom_pwrlimit_ht20
[i
] = 0;
1427 for (rf_path
= 0; rf_path
< 2; rf_path
++) {
1428 for (i
= 0; i
< 14; i
++) {
1429 index
= _rtl92c_get_chnl_group((u8
) i
);
1431 if (rf_path
== RF90_PATH_A
) {
1432 rtlefuse
->pwrgroup_ht20
[rf_path
][i
] =
1433 (rtlefuse
->eeprom_pwrlimit_ht20
[index
]
1435 rtlefuse
->pwrgroup_ht40
[rf_path
][i
] =
1436 (rtlefuse
->eeprom_pwrlimit_ht40
[index
]
1438 } else if (rf_path
== RF90_PATH_B
) {
1439 rtlefuse
->pwrgroup_ht20
[rf_path
][i
] =
1440 ((rtlefuse
->eeprom_pwrlimit_ht20
[index
]
1442 rtlefuse
->pwrgroup_ht40
[rf_path
][i
] =
1443 ((rtlefuse
->eeprom_pwrlimit_ht40
[index
]
1447 RTPRINT(rtlpriv
, FINIT
, INIT_TxPower
,
1448 "RF-%d pwrgroup_ht20[%d] = 0x%x\n",
1450 rtlefuse
->pwrgroup_ht20
[rf_path
][i
]);
1451 RTPRINT(rtlpriv
, FINIT
, INIT_TxPower
,
1452 "RF-%d pwrgroup_ht40[%d] = 0x%x\n",
1454 rtlefuse
->pwrgroup_ht40
[rf_path
][i
]);
1458 for (i
= 0; i
< 14; i
++) {
1459 index
= _rtl92c_get_chnl_group((u8
) i
);
1462 tempval
= hwinfo
[EEPROM_TXPOWERHT20DIFF
+ index
];
1464 tempval
= EEPROM_DEFAULT_HT20_DIFF
;
1466 rtlefuse
->txpwr_ht20diff
[RF90_PATH_A
][i
] = (tempval
& 0xF);
1467 rtlefuse
->txpwr_ht20diff
[RF90_PATH_B
][i
] =
1468 ((tempval
>> 4) & 0xF);
1470 if (rtlefuse
->txpwr_ht20diff
[RF90_PATH_A
][i
] & BIT(3))
1471 rtlefuse
->txpwr_ht20diff
[RF90_PATH_A
][i
] |= 0xF0;
1473 if (rtlefuse
->txpwr_ht20diff
[RF90_PATH_B
][i
] & BIT(3))
1474 rtlefuse
->txpwr_ht20diff
[RF90_PATH_B
][i
] |= 0xF0;
1476 index
= _rtl92c_get_chnl_group((u8
) i
);
1479 tempval
= hwinfo
[EEPROM_TXPOWER_OFDMDIFF
+ index
];
1481 tempval
= EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF
;
1483 rtlefuse
->txpwr_legacyhtdiff
[RF90_PATH_A
][i
] = (tempval
& 0xF);
1484 rtlefuse
->txpwr_legacyhtdiff
[RF90_PATH_B
][i
] =
1485 ((tempval
>> 4) & 0xF);
1488 rtlefuse
->legacy_ht_txpowerdiff
=
1489 rtlefuse
->txpwr_legacyhtdiff
[RF90_PATH_A
][7];
1491 for (i
= 0; i
< 14; i
++)
1492 RTPRINT(rtlpriv
, FINIT
, INIT_TxPower
,
1493 "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n",
1494 i
, rtlefuse
->txpwr_ht20diff
[RF90_PATH_A
][i
]);
1495 for (i
= 0; i
< 14; i
++)
1496 RTPRINT(rtlpriv
, FINIT
, INIT_TxPower
,
1497 "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n",
1498 i
, rtlefuse
->txpwr_legacyhtdiff
[RF90_PATH_A
][i
]);
1499 for (i
= 0; i
< 14; i
++)
1500 RTPRINT(rtlpriv
, FINIT
, INIT_TxPower
,
1501 "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n",
1502 i
, rtlefuse
->txpwr_ht20diff
[RF90_PATH_B
][i
]);
1503 for (i
= 0; i
< 14; i
++)
1504 RTPRINT(rtlpriv
, FINIT
, INIT_TxPower
,
1505 "RF-B Legacy to HT40 Diff[%d] = 0x%x\n",
1506 i
, rtlefuse
->txpwr_legacyhtdiff
[RF90_PATH_B
][i
]);
1509 rtlefuse
->eeprom_regulatory
= (hwinfo
[RF_OPTION1
] & 0x7);
1511 rtlefuse
->eeprom_regulatory
= 0;
1512 RTPRINT(rtlpriv
, FINIT
, INIT_TxPower
,
1513 "eeprom_regulatory = 0x%x\n", rtlefuse
->eeprom_regulatory
);
1515 if (!autoload_fail
) {
1516 rtlefuse
->eeprom_tssi
[RF90_PATH_A
] = hwinfo
[EEPROM_TSSI_A
];
1517 rtlefuse
->eeprom_tssi
[RF90_PATH_B
] = hwinfo
[EEPROM_TSSI_B
];
1519 rtlefuse
->eeprom_tssi
[RF90_PATH_A
] = EEPROM_DEFAULT_TSSI
;
1520 rtlefuse
->eeprom_tssi
[RF90_PATH_B
] = EEPROM_DEFAULT_TSSI
;
1522 RTPRINT(rtlpriv
, FINIT
, INIT_TxPower
, "TSSI_A = 0x%x, TSSI_B = 0x%x\n",
1523 rtlefuse
->eeprom_tssi
[RF90_PATH_A
],
1524 rtlefuse
->eeprom_tssi
[RF90_PATH_B
]);
1527 tempval
= hwinfo
[EEPROM_THERMAL_METER
];
1529 tempval
= EEPROM_DEFAULT_THERMALMETER
;
1530 rtlefuse
->eeprom_thermalmeter
= (tempval
& 0x1f);
1532 if (rtlefuse
->eeprom_thermalmeter
== 0x1f || autoload_fail
)
1533 rtlefuse
->apk_thermalmeterignore
= true;
1535 rtlefuse
->thermalmeter
[0] = rtlefuse
->eeprom_thermalmeter
;
1536 RTPRINT(rtlpriv
, FINIT
, INIT_TxPower
,
1537 "thermalmeter = 0x%x\n", rtlefuse
->eeprom_thermalmeter
);
1540 static void _rtl92ce_read_adapter_info(struct ieee80211_hw
*hw
)
1542 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1543 struct rtl_efuse
*rtlefuse
= rtl_efuse(rtl_priv(hw
));
1544 struct rtl_hal
*rtlhal
= rtl_hal(rtl_priv(hw
));
1546 u8 hwinfo
[HWSET_MAX_SIZE
];
1549 if (rtlefuse
->epromtype
== EEPROM_BOOT_EFUSE
) {
1550 rtl_efuse_shadow_map_update(hw
);
1552 memcpy((void *)hwinfo
,
1553 (void *)&rtlefuse
->efuse_map
[EFUSE_INIT_MAP
][0],
1555 } else if (rtlefuse
->epromtype
== EEPROM_93C46
) {
1556 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
,
1557 "RTL819X Not boot from eeprom, check it !!");
1560 RT_PRINT_DATA(rtlpriv
, COMP_INIT
, DBG_DMESG
, "MAP",
1561 hwinfo
, HWSET_MAX_SIZE
);
1563 eeprom_id
= *((u16
*)&hwinfo
[0]);
1564 if (eeprom_id
!= RTL8190_EEPROM_ID
) {
1565 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_WARNING
,
1566 "EEPROM ID(%#x) is invalid!!\n", eeprom_id
);
1567 rtlefuse
->autoload_failflag
= true;
1569 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_LOUD
, "Autoload OK\n");
1570 rtlefuse
->autoload_failflag
= false;
1573 if (rtlefuse
->autoload_failflag
)
1576 for (i
= 0; i
< 6; i
+= 2) {
1577 usvalue
= *(u16
*)&hwinfo
[EEPROM_MAC_ADDR
+ i
];
1578 *((u16
*) (&rtlefuse
->dev_addr
[i
])) = usvalue
;
1581 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_DMESG
, "%pM\n", rtlefuse
->dev_addr
);
1583 _rtl92ce_read_txpower_info_from_hwpg(hw
,
1584 rtlefuse
->autoload_failflag
,
1587 rtl8192ce_read_bt_coexist_info_from_hwpg(hw
,
1588 rtlefuse
->autoload_failflag
,
1591 rtlefuse
->eeprom_channelplan
= *&hwinfo
[EEPROM_CHANNELPLAN
];
1592 rtlefuse
->eeprom_version
= *(u16
*)&hwinfo
[EEPROM_VERSION
];
1593 rtlefuse
->txpwr_fromeprom
= true;
1594 rtlefuse
->eeprom_oemid
= *&hwinfo
[EEPROM_CUSTOMER_ID
];
1596 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_LOUD
,
1597 "EEPROM Customer ID: 0x%2x\n", rtlefuse
->eeprom_oemid
);
1599 /* set channel paln to world wide 13 */
1600 rtlefuse
->channel_plan
= COUNTRY_CODE_WORLD_WIDE_13
;
1602 if (rtlhal
->oem_id
== RT_CID_DEFAULT
) {
1603 switch (rtlefuse
->eeprom_oemid
) {
1604 case EEPROM_CID_DEFAULT
:
1605 if (rtlefuse
->eeprom_did
== 0x8176) {
1606 if ((rtlefuse
->eeprom_svid
== 0x103C &&
1607 rtlefuse
->eeprom_smid
== 0x1629))
1608 rtlhal
->oem_id
= RT_CID_819x_HP
;
1610 rtlhal
->oem_id
= RT_CID_DEFAULT
;
1612 rtlhal
->oem_id
= RT_CID_DEFAULT
;
1615 case EEPROM_CID_TOSHIBA
:
1616 rtlhal
->oem_id
= RT_CID_TOSHIBA
;
1618 case EEPROM_CID_QMI
:
1619 rtlhal
->oem_id
= RT_CID_819x_QMI
;
1621 case EEPROM_CID_WHQL
:
1623 rtlhal
->oem_id
= RT_CID_DEFAULT
;
1631 static void _rtl92ce_hal_customized_behavior(struct ieee80211_hw
*hw
)
1633 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1634 struct rtl_pci_priv
*pcipriv
= rtl_pcipriv(hw
);
1635 struct rtl_hal
*rtlhal
= rtl_hal(rtl_priv(hw
));
1637 switch (rtlhal
->oem_id
) {
1638 case RT_CID_819x_HP
:
1639 pcipriv
->ledctl
.led_opendrain
= true;
1641 case RT_CID_819x_Lenovo
:
1642 case RT_CID_DEFAULT
:
1643 case RT_CID_TOSHIBA
:
1645 case RT_CID_819x_Acer
:
1650 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_DMESG
,
1651 "RT Customized ID: 0x%02X\n", rtlhal
->oem_id
);
1654 void rtl92ce_read_eeprom_info(struct ieee80211_hw
*hw
)
1656 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1657 struct rtl_efuse
*rtlefuse
= rtl_efuse(rtl_priv(hw
));
1658 struct rtl_phy
*rtlphy
= &(rtlpriv
->phy
);
1659 struct rtl_hal
*rtlhal
= rtl_hal(rtl_priv(hw
));
1662 rtlhal
->version
= _rtl92ce_read_chip_version(hw
);
1663 if (get_rf_type(rtlphy
) == RF_1T1R
)
1664 rtlpriv
->dm
.rfpath_rxenable
[0] = true;
1666 rtlpriv
->dm
.rfpath_rxenable
[0] =
1667 rtlpriv
->dm
.rfpath_rxenable
[1] = true;
1668 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_LOUD
, "VersionID = 0x%4x\n",
1670 tmp_u1b
= rtl_read_byte(rtlpriv
, REG_9346CR
);
1671 if (tmp_u1b
& BIT(4)) {
1672 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_DMESG
, "Boot from EEPROM\n");
1673 rtlefuse
->epromtype
= EEPROM_93C46
;
1675 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_DMESG
, "Boot from EFUSE\n");
1676 rtlefuse
->epromtype
= EEPROM_BOOT_EFUSE
;
1678 if (tmp_u1b
& BIT(5)) {
1679 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_LOUD
, "Autoload OK\n");
1680 rtlefuse
->autoload_failflag
= false;
1681 _rtl92ce_read_adapter_info(hw
);
1683 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
, "Autoload ERR!!\n");
1685 _rtl92ce_hal_customized_behavior(hw
);
1688 static void rtl92ce_update_hal_rate_table(struct ieee80211_hw
*hw
,
1689 struct ieee80211_sta
*sta
)
1691 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1692 struct rtl_pci_priv
*rtlpcipriv
= rtl_pcipriv(hw
);
1693 struct rtl_phy
*rtlphy
= &(rtlpriv
->phy
);
1694 struct rtl_mac
*mac
= rtl_mac(rtl_priv(hw
));
1695 struct rtl_hal
*rtlhal
= rtl_hal(rtl_priv(hw
));
1698 u8 nmode
= mac
->ht_enable
;
1699 u8 mimo_ps
= IEEE80211_SMPS_OFF
;
1702 u8 curtxbw_40mhz
= mac
->bw_40
;
1703 u8 curshortgi_40mhz
= (sta
->ht_cap
.cap
& IEEE80211_HT_CAP_SGI_40
) ?
1705 u8 curshortgi_20mhz
= (sta
->ht_cap
.cap
& IEEE80211_HT_CAP_SGI_20
) ?
1707 enum wireless_mode wirelessmode
= mac
->mode
;
1709 if (rtlhal
->current_bandtype
== BAND_ON_5G
)
1710 ratr_value
= sta
->supp_rates
[1] << 4;
1712 ratr_value
= sta
->supp_rates
[0];
1713 ratr_value
|= (sta
->ht_cap
.mcs
.rx_mask
[1] << 20 |
1714 sta
->ht_cap
.mcs
.rx_mask
[0] << 12);
1715 switch (wirelessmode
) {
1716 case WIRELESS_MODE_B
:
1717 if (ratr_value
& 0x0000000c)
1718 ratr_value
&= 0x0000000d;
1720 ratr_value
&= 0x0000000f;
1722 case WIRELESS_MODE_G
:
1723 ratr_value
&= 0x00000FF5;
1725 case WIRELESS_MODE_N_24G
:
1726 case WIRELESS_MODE_N_5G
:
1728 if (mimo_ps
== IEEE80211_SMPS_STATIC
) {
1729 ratr_value
&= 0x0007F005;
1733 if (get_rf_type(rtlphy
) == RF_1T2R
||
1734 get_rf_type(rtlphy
) == RF_1T1R
)
1735 ratr_mask
= 0x000ff005;
1737 ratr_mask
= 0x0f0ff005;
1739 ratr_value
&= ratr_mask
;
1743 if (rtlphy
->rf_type
== RF_1T2R
)
1744 ratr_value
&= 0x000ff0ff;
1746 ratr_value
&= 0x0f0ff0ff;
1751 if ((rtlpcipriv
->bt_coexist
.bt_coexistence
) &&
1752 (rtlpcipriv
->bt_coexist
.bt_coexist_type
== BT_CSR_BC4
) &&
1753 (rtlpcipriv
->bt_coexist
.bt_cur_state
) &&
1754 (rtlpcipriv
->bt_coexist
.bt_ant_isolation
) &&
1755 ((rtlpcipriv
->bt_coexist
.bt_service
== BT_SCO
) ||
1756 (rtlpcipriv
->bt_coexist
.bt_service
== BT_BUSY
)))
1757 ratr_value
&= 0x0fffcfc0;
1759 ratr_value
&= 0x0FFFFFFF;
1761 if (nmode
&& ((curtxbw_40mhz
&&
1762 curshortgi_40mhz
) || (!curtxbw_40mhz
&&
1763 curshortgi_20mhz
))) {
1765 ratr_value
|= 0x10000000;
1766 tmp_ratr_value
= (ratr_value
>> 12);
1768 for (shortgi_rate
= 15; shortgi_rate
> 0; shortgi_rate
--) {
1769 if ((1 << shortgi_rate
) & tmp_ratr_value
)
1773 shortgi_rate
= (shortgi_rate
<< 12) | (shortgi_rate
<< 8) |
1774 (shortgi_rate
<< 4) | (shortgi_rate
);
1777 rtl_write_dword(rtlpriv
, REG_ARFR0
+ ratr_index
* 4, ratr_value
);
1779 RT_TRACE(rtlpriv
, COMP_RATR
, DBG_DMESG
, "%x\n",
1780 rtl_read_dword(rtlpriv
, REG_ARFR0
));
1783 static void rtl92ce_update_hal_rate_mask(struct ieee80211_hw
*hw
,
1784 struct ieee80211_sta
*sta
, u8 rssi_level
)
1786 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1787 struct rtl_phy
*rtlphy
= &(rtlpriv
->phy
);
1788 struct rtl_mac
*mac
= rtl_mac(rtl_priv(hw
));
1789 struct rtl_hal
*rtlhal
= rtl_hal(rtl_priv(hw
));
1790 struct rtl_sta_info
*sta_entry
= NULL
;
1793 u8 curtxbw_40mhz
= (sta
->ht_cap
.cap
& IEEE80211_HT_CAP_SUP_WIDTH_20_40
)
1795 u8 curshortgi_40mhz
= (sta
->ht_cap
.cap
& IEEE80211_HT_CAP_SGI_40
) ?
1797 u8 curshortgi_20mhz
= (sta
->ht_cap
.cap
& IEEE80211_HT_CAP_SGI_20
) ?
1799 enum wireless_mode wirelessmode
= 0;
1800 bool shortgi
= false;
1803 u8 mimo_ps
= IEEE80211_SMPS_OFF
;
1805 sta_entry
= (struct rtl_sta_info
*) sta
->drv_priv
;
1806 wirelessmode
= sta_entry
->wireless_mode
;
1807 if (mac
->opmode
== NL80211_IFTYPE_STATION
)
1808 curtxbw_40mhz
= mac
->bw_40
;
1809 else if (mac
->opmode
== NL80211_IFTYPE_AP
||
1810 mac
->opmode
== NL80211_IFTYPE_ADHOC
)
1811 macid
= sta
->aid
+ 1;
1813 if (rtlhal
->current_bandtype
== BAND_ON_5G
)
1814 ratr_bitmap
= sta
->supp_rates
[1] << 4;
1816 ratr_bitmap
= sta
->supp_rates
[0];
1817 ratr_bitmap
|= (sta
->ht_cap
.mcs
.rx_mask
[1] << 20 |
1818 sta
->ht_cap
.mcs
.rx_mask
[0] << 12);
1819 switch (wirelessmode
) {
1820 case WIRELESS_MODE_B
:
1821 ratr_index
= RATR_INX_WIRELESS_B
;
1822 if (ratr_bitmap
& 0x0000000c)
1823 ratr_bitmap
&= 0x0000000d;
1825 ratr_bitmap
&= 0x0000000f;
1827 case WIRELESS_MODE_G
:
1828 ratr_index
= RATR_INX_WIRELESS_GB
;
1830 if (rssi_level
== 1)
1831 ratr_bitmap
&= 0x00000f00;
1832 else if (rssi_level
== 2)
1833 ratr_bitmap
&= 0x00000ff0;
1835 ratr_bitmap
&= 0x00000ff5;
1837 case WIRELESS_MODE_A
:
1838 ratr_index
= RATR_INX_WIRELESS_A
;
1839 ratr_bitmap
&= 0x00000ff0;
1841 case WIRELESS_MODE_N_24G
:
1842 case WIRELESS_MODE_N_5G
:
1843 ratr_index
= RATR_INX_WIRELESS_NGB
;
1845 if (mimo_ps
== IEEE80211_SMPS_STATIC
) {
1846 if (rssi_level
== 1)
1847 ratr_bitmap
&= 0x00070000;
1848 else if (rssi_level
== 2)
1849 ratr_bitmap
&= 0x0007f000;
1851 ratr_bitmap
&= 0x0007f005;
1853 if (rtlphy
->rf_type
== RF_1T2R
||
1854 rtlphy
->rf_type
== RF_1T1R
) {
1855 if (curtxbw_40mhz
) {
1856 if (rssi_level
== 1)
1857 ratr_bitmap
&= 0x000f0000;
1858 else if (rssi_level
== 2)
1859 ratr_bitmap
&= 0x000ff000;
1861 ratr_bitmap
&= 0x000ff015;
1863 if (rssi_level
== 1)
1864 ratr_bitmap
&= 0x000f0000;
1865 else if (rssi_level
== 2)
1866 ratr_bitmap
&= 0x000ff000;
1868 ratr_bitmap
&= 0x000ff005;
1871 if (curtxbw_40mhz
) {
1872 if (rssi_level
== 1)
1873 ratr_bitmap
&= 0x0f0f0000;
1874 else if (rssi_level
== 2)
1875 ratr_bitmap
&= 0x0f0ff000;
1877 ratr_bitmap
&= 0x0f0ff015;
1879 if (rssi_level
== 1)
1880 ratr_bitmap
&= 0x0f0f0000;
1881 else if (rssi_level
== 2)
1882 ratr_bitmap
&= 0x0f0ff000;
1884 ratr_bitmap
&= 0x0f0ff005;
1889 if ((curtxbw_40mhz
&& curshortgi_40mhz
) ||
1890 (!curtxbw_40mhz
&& curshortgi_20mhz
)) {
1894 else if (macid
== 1)
1899 ratr_index
= RATR_INX_WIRELESS_NGB
;
1901 if (rtlphy
->rf_type
== RF_1T2R
)
1902 ratr_bitmap
&= 0x000ff0ff;
1904 ratr_bitmap
&= 0x0f0ff0ff;
1907 RT_TRACE(rtlpriv
, COMP_RATR
, DBG_DMESG
,
1908 "ratr_bitmap :%x\n", ratr_bitmap
);
1909 *(u32
*)&rate_mask
= (ratr_bitmap
& 0x0fffffff) |
1911 rate_mask
[4] = macid
| (shortgi
? 0x20 : 0x00) | 0x80;
1912 RT_TRACE(rtlpriv
, COMP_RATR
, DBG_DMESG
,
1913 "Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x\n",
1914 ratr_index
, ratr_bitmap
,
1915 rate_mask
[0], rate_mask
[1], rate_mask
[2], rate_mask
[3],
1917 rtl92c_fill_h2c_cmd(hw
, H2C_RA_MASK
, 5, rate_mask
);
1920 sta_entry
->ratr_index
= ratr_index
;
1923 void rtl92ce_update_hal_rate_tbl(struct ieee80211_hw
*hw
,
1924 struct ieee80211_sta
*sta
, u8 rssi_level
)
1926 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1928 if (rtlpriv
->dm
.useramask
)
1929 rtl92ce_update_hal_rate_mask(hw
, sta
, rssi_level
);
1931 rtl92ce_update_hal_rate_table(hw
, sta
);
1934 void rtl92ce_update_channel_access_setting(struct ieee80211_hw
*hw
)
1936 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1937 struct rtl_mac
*mac
= rtl_mac(rtl_priv(hw
));
1940 rtlpriv
->cfg
->ops
->set_hw_reg(hw
, HW_VAR_SLOT_TIME
,
1942 if (!mac
->ht_enable
)
1943 sifs_timer
= 0x0a0a;
1945 sifs_timer
= 0x1010;
1946 rtlpriv
->cfg
->ops
->set_hw_reg(hw
, HW_VAR_SIFS
, (u8
*)&sifs_timer
);
1949 bool rtl92ce_gpio_radio_on_off_checking(struct ieee80211_hw
*hw
, u8
*valid
)
1951 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1952 struct rtl_ps_ctl
*ppsc
= rtl_psc(rtl_priv(hw
));
1953 struct rtl_pci
*rtlpci
= rtl_pcidev(rtl_pcipriv(hw
));
1954 enum rf_pwrstate e_rfpowerstate_toset
;
1956 bool actuallyset
= false;
1959 if (rtlpci
->being_init_adapter
)
1962 if (ppsc
->swrf_processing
)
1965 spin_lock_irqsave(&rtlpriv
->locks
.rf_ps_lock
, flag
);
1966 if (ppsc
->rfchange_inprogress
) {
1967 spin_unlock_irqrestore(&rtlpriv
->locks
.rf_ps_lock
, flag
);
1970 ppsc
->rfchange_inprogress
= true;
1971 spin_unlock_irqrestore(&rtlpriv
->locks
.rf_ps_lock
, flag
);
1974 rtl_write_byte(rtlpriv
, REG_MAC_PINMUX_CFG
, rtl_read_byte(rtlpriv
,
1975 REG_MAC_PINMUX_CFG
)&~(BIT(3)));
1977 u1tmp
= rtl_read_byte(rtlpriv
, REG_GPIO_IO_SEL
);
1978 e_rfpowerstate_toset
= (u1tmp
& BIT(3)) ? ERFON
: ERFOFF
;
1980 if ((ppsc
->hwradiooff
) && (e_rfpowerstate_toset
== ERFON
)) {
1981 RT_TRACE(rtlpriv
, COMP_RF
, DBG_DMESG
,
1982 "GPIOChangeRF - HW Radio ON, RF ON\n");
1984 e_rfpowerstate_toset
= ERFON
;
1985 ppsc
->hwradiooff
= false;
1987 } else if (!ppsc
->hwradiooff
&& (e_rfpowerstate_toset
== ERFOFF
)) {
1988 RT_TRACE(rtlpriv
, COMP_RF
, DBG_DMESG
,
1989 "GPIOChangeRF - HW Radio OFF, RF OFF\n");
1991 e_rfpowerstate_toset
= ERFOFF
;
1992 ppsc
->hwradiooff
= true;
1997 spin_lock_irqsave(&rtlpriv
->locks
.rf_ps_lock
, flag
);
1998 ppsc
->rfchange_inprogress
= false;
1999 spin_unlock_irqrestore(&rtlpriv
->locks
.rf_ps_lock
, flag
);
2001 if (ppsc
->reg_rfps_level
& RT_RF_OFF_LEVL_HALT_NIC
)
2002 RT_SET_PS_LEVEL(ppsc
, RT_RF_OFF_LEVL_HALT_NIC
);
2004 spin_lock_irqsave(&rtlpriv
->locks
.rf_ps_lock
, flag
);
2005 ppsc
->rfchange_inprogress
= false;
2006 spin_unlock_irqrestore(&rtlpriv
->locks
.rf_ps_lock
, flag
);
2010 return !ppsc
->hwradiooff
;
2014 void rtl92ce_set_key(struct ieee80211_hw
*hw
, u32 key_index
,
2015 u8
*p_macaddr
, bool is_group
, u8 enc_algo
,
2016 bool is_wepkey
, bool clear_all
)
2018 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
2019 struct rtl_mac
*mac
= rtl_mac(rtl_priv(hw
));
2020 struct rtl_efuse
*rtlefuse
= rtl_efuse(rtl_priv(hw
));
2021 u8
*macaddr
= p_macaddr
;
2023 bool is_pairwise
= false;
2025 static u8 cam_const_addr
[4][6] = {
2026 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2027 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2028 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2029 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2031 static u8 cam_const_broad
[] = {
2032 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2038 u8 clear_number
= 5;
2040 RT_TRACE(rtlpriv
, COMP_SEC
, DBG_DMESG
, "clear_all\n");
2042 for (idx
= 0; idx
< clear_number
; idx
++) {
2043 rtl_cam_mark_invalid(hw
, cam_offset
+ idx
);
2044 rtl_cam_empty_entry(hw
, cam_offset
+ idx
);
2047 memset(rtlpriv
->sec
.key_buf
[idx
], 0,
2049 rtlpriv
->sec
.key_len
[idx
] = 0;
2055 case WEP40_ENCRYPTION
:
2056 enc_algo
= CAM_WEP40
;
2058 case WEP104_ENCRYPTION
:
2059 enc_algo
= CAM_WEP104
;
2061 case TKIP_ENCRYPTION
:
2062 enc_algo
= CAM_TKIP
;
2064 case AESCCMP_ENCRYPTION
:
2068 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
,
2069 "switch case not processed\n");
2070 enc_algo
= CAM_TKIP
;
2074 if (is_wepkey
|| rtlpriv
->sec
.use_defaultkey
) {
2075 macaddr
= cam_const_addr
[key_index
];
2076 entry_id
= key_index
;
2079 macaddr
= cam_const_broad
;
2080 entry_id
= key_index
;
2082 if (mac
->opmode
== NL80211_IFTYPE_AP
) {
2083 entry_id
= rtl_cam_get_free_entry(hw
,
2085 if (entry_id
>= TOTAL_CAM_ENTRY
) {
2086 RT_TRACE(rtlpriv
, COMP_SEC
,
2088 "Can not find free hw security cam entry\n");
2092 entry_id
= CAM_PAIRWISE_KEY_POSITION
;
2095 key_index
= PAIRWISE_KEYIDX
;
2100 if (rtlpriv
->sec
.key_len
[key_index
] == 0) {
2101 RT_TRACE(rtlpriv
, COMP_SEC
, DBG_DMESG
,
2102 "delete one entry, entry_id is %d\n",
2104 if (mac
->opmode
== NL80211_IFTYPE_AP
)
2105 rtl_cam_del_entry(hw
, p_macaddr
);
2106 rtl_cam_delete_one_entry(hw
, p_macaddr
, entry_id
);
2108 RT_TRACE(rtlpriv
, COMP_SEC
, DBG_LOUD
,
2109 "The insert KEY length is %d\n",
2110 rtlpriv
->sec
.key_len
[PAIRWISE_KEYIDX
]);
2111 RT_TRACE(rtlpriv
, COMP_SEC
, DBG_LOUD
,
2112 "The insert KEY is %x %x\n",
2113 rtlpriv
->sec
.key_buf
[0][0],
2114 rtlpriv
->sec
.key_buf
[0][1]);
2116 RT_TRACE(rtlpriv
, COMP_SEC
, DBG_DMESG
,
2119 RT_PRINT_DATA(rtlpriv
, COMP_SEC
, DBG_LOUD
,
2120 "Pairwise Key content",
2121 rtlpriv
->sec
.pairwise_key
,
2123 key_len
[PAIRWISE_KEYIDX
]);
2125 RT_TRACE(rtlpriv
, COMP_SEC
, DBG_DMESG
,
2126 "set Pairwise key\n");
2128 rtl_cam_add_one_entry(hw
, macaddr
, key_index
,
2130 CAM_CONFIG_NO_USEDK
,
2132 key_buf
[key_index
]);
2134 RT_TRACE(rtlpriv
, COMP_SEC
, DBG_DMESG
,
2137 if (mac
->opmode
== NL80211_IFTYPE_ADHOC
) {
2138 rtl_cam_add_one_entry(hw
,
2141 CAM_PAIRWISE_KEY_POSITION
,
2143 CAM_CONFIG_NO_USEDK
,
2144 rtlpriv
->sec
.key_buf
2148 rtl_cam_add_one_entry(hw
, macaddr
, key_index
,
2150 CAM_CONFIG_NO_USEDK
,
2151 rtlpriv
->sec
.key_buf
[entry_id
]);
2158 static void rtl8192ce_bt_var_init(struct ieee80211_hw
*hw
)
2160 struct rtl_pci_priv
*rtlpcipriv
= rtl_pcipriv(hw
);
2162 rtlpcipriv
->bt_coexist
.bt_coexistence
=
2163 rtlpcipriv
->bt_coexist
.eeprom_bt_coexist
;
2164 rtlpcipriv
->bt_coexist
.bt_ant_num
=
2165 rtlpcipriv
->bt_coexist
.eeprom_bt_ant_num
;
2166 rtlpcipriv
->bt_coexist
.bt_coexist_type
=
2167 rtlpcipriv
->bt_coexist
.eeprom_bt_type
;
2169 if (rtlpcipriv
->bt_coexist
.reg_bt_iso
== 2)
2170 rtlpcipriv
->bt_coexist
.bt_ant_isolation
=
2171 rtlpcipriv
->bt_coexist
.eeprom_bt_ant_isolation
;
2173 rtlpcipriv
->bt_coexist
.bt_ant_isolation
=
2174 rtlpcipriv
->bt_coexist
.reg_bt_iso
;
2176 rtlpcipriv
->bt_coexist
.bt_radio_shared_type
=
2177 rtlpcipriv
->bt_coexist
.eeprom_bt_radio_shared
;
2179 if (rtlpcipriv
->bt_coexist
.bt_coexistence
) {
2181 if (rtlpcipriv
->bt_coexist
.reg_bt_sco
== 1)
2182 rtlpcipriv
->bt_coexist
.bt_service
= BT_OTHER_ACTION
;
2183 else if (rtlpcipriv
->bt_coexist
.reg_bt_sco
== 2)
2184 rtlpcipriv
->bt_coexist
.bt_service
= BT_SCO
;
2185 else if (rtlpcipriv
->bt_coexist
.reg_bt_sco
== 4)
2186 rtlpcipriv
->bt_coexist
.bt_service
= BT_BUSY
;
2187 else if (rtlpcipriv
->bt_coexist
.reg_bt_sco
== 5)
2188 rtlpcipriv
->bt_coexist
.bt_service
= BT_OTHERBUSY
;
2190 rtlpcipriv
->bt_coexist
.bt_service
= BT_IDLE
;
2192 rtlpcipriv
->bt_coexist
.bt_edca_ul
= 0;
2193 rtlpcipriv
->bt_coexist
.bt_edca_dl
= 0;
2194 rtlpcipriv
->bt_coexist
.bt_rssi_state
= 0xff;
2198 void rtl8192ce_read_bt_coexist_info_from_hwpg(struct ieee80211_hw
*hw
,
2199 bool auto_load_fail
, u8
*hwinfo
)
2201 struct rtl_pci_priv
*rtlpcipriv
= rtl_pcipriv(hw
);
2204 if (!auto_load_fail
) {
2205 rtlpcipriv
->bt_coexist
.eeprom_bt_coexist
=
2206 ((hwinfo
[RF_OPTION1
] & 0xe0) >> 5);
2207 value
= hwinfo
[RF_OPTION4
];
2208 rtlpcipriv
->bt_coexist
.eeprom_bt_type
= ((value
& 0xe) >> 1);
2209 rtlpcipriv
->bt_coexist
.eeprom_bt_ant_num
= (value
& 0x1);
2210 rtlpcipriv
->bt_coexist
.eeprom_bt_ant_isolation
=
2211 ((value
& 0x10) >> 4);
2212 rtlpcipriv
->bt_coexist
.eeprom_bt_radio_shared
=
2213 ((value
& 0x20) >> 5);
2215 rtlpcipriv
->bt_coexist
.eeprom_bt_coexist
= 0;
2216 rtlpcipriv
->bt_coexist
.eeprom_bt_type
= BT_2WIRE
;
2217 rtlpcipriv
->bt_coexist
.eeprom_bt_ant_num
= ANT_X2
;
2218 rtlpcipriv
->bt_coexist
.eeprom_bt_ant_isolation
= 0;
2219 rtlpcipriv
->bt_coexist
.eeprom_bt_radio_shared
= BT_RADIO_SHARED
;
2222 rtl8192ce_bt_var_init(hw
);
2225 void rtl8192ce_bt_reg_init(struct ieee80211_hw
*hw
)
2227 struct rtl_pci_priv
*rtlpcipriv
= rtl_pcipriv(hw
);
2229 /* 0:Low, 1:High, 2:From Efuse. */
2230 rtlpcipriv
->bt_coexist
.reg_bt_iso
= 2;
2231 /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
2232 rtlpcipriv
->bt_coexist
.reg_bt_sco
= 3;
2233 /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
2234 rtlpcipriv
->bt_coexist
.reg_bt_sco
= 0;
2238 void rtl8192ce_bt_hw_init(struct ieee80211_hw
*hw
)
2240 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
2241 struct rtl_phy
*rtlphy
= &(rtlpriv
->phy
);
2242 struct rtl_pci_priv
*rtlpcipriv
= rtl_pcipriv(hw
);
2246 if (rtlpcipriv
->bt_coexist
.bt_coexistence
&&
2247 ((rtlpcipriv
->bt_coexist
.bt_coexist_type
== BT_CSR_BC4
) ||
2248 rtlpcipriv
->bt_coexist
.bt_coexist_type
== BT_CSR_BC8
)) {
2250 if (rtlpcipriv
->bt_coexist
.bt_ant_isolation
)
2251 rtl_write_byte(rtlpriv
, REG_GPIO_MUXCFG
, 0xa0);
2253 u1_tmp
= rtl_read_byte(rtlpriv
, 0x4fd) &
2254 BIT_OFFSET_LEN_MASK_32(0, 1);
2256 ((rtlpcipriv
->bt_coexist
.bt_ant_isolation
== 1) ?
2257 0 : BIT_OFFSET_LEN_MASK_32(1, 1)) |
2258 ((rtlpcipriv
->bt_coexist
.bt_service
== BT_SCO
) ?
2259 0 : BIT_OFFSET_LEN_MASK_32(2, 1));
2260 rtl_write_byte(rtlpriv
, 0x4fd, u1_tmp
);
2262 rtl_write_dword(rtlpriv
, REG_BT_COEX_TABLE
+4, 0xaaaa9aaa);
2263 rtl_write_dword(rtlpriv
, REG_BT_COEX_TABLE
+8, 0xffbd0040);
2264 rtl_write_dword(rtlpriv
, REG_BT_COEX_TABLE
+0xc, 0x40000010);
2266 /* Config to 1T1R. */
2267 if (rtlphy
->rf_type
== RF_1T1R
) {
2268 u1_tmp
= rtl_read_byte(rtlpriv
, ROFDM0_TRXPATHENABLE
);
2269 u1_tmp
&= ~(BIT_OFFSET_LEN_MASK_32(1, 1));
2270 rtl_write_byte(rtlpriv
, ROFDM0_TRXPATHENABLE
, u1_tmp
);
2272 u1_tmp
= rtl_read_byte(rtlpriv
, ROFDM1_TRXPATHENABLE
);
2273 u1_tmp
&= ~(BIT_OFFSET_LEN_MASK_32(1, 1));
2274 rtl_write_byte(rtlpriv
, ROFDM1_TRXPATHENABLE
, u1_tmp
);
2279 void rtl92ce_suspend(struct ieee80211_hw
*hw
)
2283 void rtl92ce_resume(struct ieee80211_hw
*hw
)