1 /******************************************************************************
3 * Copyright(c) 2009-2012 Realtek Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
26 * Larry Finger <Larry.Finger@lwfinger.net>
28 *****************************************************************************/
40 #include "../rtl8192c/fw_common.h"
47 static void _rtl92ce_set_bcn_ctrl_reg(struct ieee80211_hw
*hw
,
48 u8 set_bits
, u8 clear_bits
)
50 struct rtl_pci
*rtlpci
= rtl_pcidev(rtl_pcipriv(hw
));
51 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
53 rtlpci
->reg_bcn_ctrl_val
|= set_bits
;
54 rtlpci
->reg_bcn_ctrl_val
&= ~clear_bits
;
56 rtl_write_byte(rtlpriv
, REG_BCN_CTRL
, (u8
) rtlpci
->reg_bcn_ctrl_val
);
59 static void _rtl92ce_stop_tx_beacon(struct ieee80211_hw
*hw
)
61 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
64 tmp1byte
= rtl_read_byte(rtlpriv
, REG_FWHW_TXQ_CTRL
+ 2);
65 rtl_write_byte(rtlpriv
, REG_FWHW_TXQ_CTRL
+ 2, tmp1byte
& (~BIT(6)));
66 rtl_write_byte(rtlpriv
, REG_TBTT_PROHIBIT
+ 1, 0x64);
67 tmp1byte
= rtl_read_byte(rtlpriv
, REG_TBTT_PROHIBIT
+ 2);
68 tmp1byte
&= ~(BIT(0));
69 rtl_write_byte(rtlpriv
, REG_TBTT_PROHIBIT
+ 2, tmp1byte
);
72 static void _rtl92ce_resume_tx_beacon(struct ieee80211_hw
*hw
)
74 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
77 tmp1byte
= rtl_read_byte(rtlpriv
, REG_FWHW_TXQ_CTRL
+ 2);
78 rtl_write_byte(rtlpriv
, REG_FWHW_TXQ_CTRL
+ 2, tmp1byte
| BIT(6));
79 rtl_write_byte(rtlpriv
, REG_TBTT_PROHIBIT
+ 1, 0xff);
80 tmp1byte
= rtl_read_byte(rtlpriv
, REG_TBTT_PROHIBIT
+ 2);
82 rtl_write_byte(rtlpriv
, REG_TBTT_PROHIBIT
+ 2, tmp1byte
);
85 static void _rtl92ce_enable_bcn_sub_func(struct ieee80211_hw
*hw
)
87 _rtl92ce_set_bcn_ctrl_reg(hw
, 0, BIT(1));
90 static void _rtl92ce_disable_bcn_sub_func(struct ieee80211_hw
*hw
)
92 _rtl92ce_set_bcn_ctrl_reg(hw
, BIT(1), 0);
95 void rtl92ce_get_hw_reg(struct ieee80211_hw
*hw
, u8 variable
, u8
*val
)
97 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
98 struct rtl_ps_ctl
*ppsc
= rtl_psc(rtl_priv(hw
));
99 struct rtl_pci
*rtlpci
= rtl_pcidev(rtl_pcipriv(hw
));
103 *((u32
*) (val
)) = rtlpci
->receive_config
;
105 case HW_VAR_RF_STATE
:
106 *((enum rf_pwrstate
*)(val
)) = ppsc
->rfpwr_state
;
108 case HW_VAR_FWLPS_RF_ON
:{
109 enum rf_pwrstate rfState
;
112 rtlpriv
->cfg
->ops
->get_hw_reg(hw
,
115 if (rfState
== ERFOFF
) {
116 *((bool *) (val
)) = true;
118 val_rcr
= rtl_read_dword(rtlpriv
, REG_RCR
);
119 val_rcr
&= 0x00070000;
121 *((bool *) (val
)) = false;
123 *((bool *) (val
)) = true;
127 case HW_VAR_FW_PSMODE_STATUS
:
128 *((bool *) (val
)) = ppsc
->fw_current_inpsmode
;
130 case HW_VAR_CORRECT_TSF
:{
132 u32
*ptsf_low
= (u32
*)&tsf
;
133 u32
*ptsf_high
= ((u32
*)&tsf
) + 1;
135 *ptsf_high
= rtl_read_dword(rtlpriv
, (REG_TSFTR
+ 4));
136 *ptsf_low
= rtl_read_dword(rtlpriv
, REG_TSFTR
);
138 *((u64
*) (val
)) = tsf
;
143 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
,
144 "switch case not processed\n");
149 void rtl92ce_set_hw_reg(struct ieee80211_hw
*hw
, u8 variable
, u8
*val
)
151 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
152 struct rtl_pci_priv
*rtlpcipriv
= rtl_pcipriv(hw
);
153 struct rtl_pci
*rtlpci
= rtl_pcidev(rtl_pcipriv(hw
));
154 struct rtl_mac
*mac
= rtl_mac(rtl_priv(hw
));
155 struct rtl_hal
*rtlhal
= rtl_hal(rtl_priv(hw
));
156 struct rtl_efuse
*rtlefuse
= rtl_efuse(rtl_priv(hw
));
157 struct rtl_ps_ctl
*ppsc
= rtl_psc(rtl_priv(hw
));
161 case HW_VAR_ETHER_ADDR
:{
162 for (idx
= 0; idx
< ETH_ALEN
; idx
++) {
163 rtl_write_byte(rtlpriv
, (REG_MACID
+ idx
),
168 case HW_VAR_BASIC_RATE
:{
169 u16 rate_cfg
= ((u16
*) val
)[0];
173 rtl_write_byte(rtlpriv
, REG_RRSR
, rate_cfg
& 0xff);
174 rtl_write_byte(rtlpriv
, REG_RRSR
+ 1,
175 (rate_cfg
>> 8) & 0xff);
176 while (rate_cfg
> 0x1) {
177 rate_cfg
= (rate_cfg
>> 1);
180 rtl_write_byte(rtlpriv
, REG_INIRTS_RATE_SEL
,
185 for (idx
= 0; idx
< ETH_ALEN
; idx
++) {
186 rtl_write_byte(rtlpriv
, (REG_BSSID
+ idx
),
192 rtl_write_byte(rtlpriv
, REG_SIFS_CTX
+ 1, val
[0]);
193 rtl_write_byte(rtlpriv
, REG_SIFS_TRX
+ 1, val
[1]);
195 rtl_write_byte(rtlpriv
, REG_SPEC_SIFS
+ 1, val
[0]);
196 rtl_write_byte(rtlpriv
, REG_MAC_SPEC_SIFS
+ 1, val
[0]);
199 rtl_write_word(rtlpriv
, REG_RESP_SIFS_OFDM
,
202 rtl_write_word(rtlpriv
, REG_RESP_SIFS_OFDM
,
206 case HW_VAR_SLOT_TIME
:{
209 RT_TRACE(rtlpriv
, COMP_MLME
, DBG_LOUD
,
210 "HW_VAR_SLOT_TIME %x\n", val
[0]);
212 rtl_write_byte(rtlpriv
, REG_SLOT
, val
[0]);
214 for (e_aci
= 0; e_aci
< AC_MAX
; e_aci
++) {
215 rtlpriv
->cfg
->ops
->set_hw_reg(hw
,
221 case HW_VAR_ACK_PREAMBLE
:{
223 u8 short_preamble
= (bool) (*(u8
*) val
);
224 reg_tmp
= (mac
->cur_40_prime_sc
) << 5;
228 rtl_write_byte(rtlpriv
, REG_RRSR
+ 2, reg_tmp
);
231 case HW_VAR_AMPDU_MIN_SPACE
:{
232 u8 min_spacing_to_set
;
235 min_spacing_to_set
= *((u8
*) val
);
236 if (min_spacing_to_set
<= 7) {
239 if (min_spacing_to_set
< sec_min_space
)
240 min_spacing_to_set
= sec_min_space
;
242 mac
->min_space_cfg
= ((mac
->min_space_cfg
&
246 *val
= min_spacing_to_set
;
248 RT_TRACE(rtlpriv
, COMP_MLME
, DBG_LOUD
,
249 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
252 rtl_write_byte(rtlpriv
, REG_AMPDU_MIN_SPACE
,
257 case HW_VAR_SHORTGI_DENSITY
:{
260 density_to_set
= *((u8
*) val
);
261 mac
->min_space_cfg
|= (density_to_set
<< 3);
263 RT_TRACE(rtlpriv
, COMP_MLME
, DBG_LOUD
,
264 "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
267 rtl_write_byte(rtlpriv
, REG_AMPDU_MIN_SPACE
,
272 case HW_VAR_AMPDU_FACTOR
:{
273 u8 regtoset_normal
[4] = {0x41, 0xa8, 0x72, 0xb9};
274 u8 regtoset_bt
[4] = {0x31, 0x74, 0x42, 0x97};
277 u8
*p_regtoset
= NULL
;
280 if ((rtlpcipriv
->bt_coexist
.bt_coexistence
) &&
281 (rtlpcipriv
->bt_coexist
.bt_coexist_type
==
283 p_regtoset
= regtoset_bt
;
285 p_regtoset
= regtoset_normal
;
287 factor_toset
= *((u8
*) val
);
288 if (factor_toset
<= 3) {
289 factor_toset
= (1 << (factor_toset
+ 2));
290 if (factor_toset
> 0xf)
293 for (index
= 0; index
< 4; index
++) {
294 if ((p_regtoset
[index
] & 0xf0) >
297 (p_regtoset
[index
] & 0x0f) |
300 if ((p_regtoset
[index
] & 0x0f) >
303 (p_regtoset
[index
] & 0xf0) |
306 rtl_write_byte(rtlpriv
,
307 (REG_AGGLEN_LMT
+ index
),
312 RT_TRACE(rtlpriv
, COMP_MLME
, DBG_LOUD
,
313 "Set HW_VAR_AMPDU_FACTOR: %#x\n",
318 case HW_VAR_AC_PARAM
:{
319 u8 e_aci
= *((u8
*) val
);
320 rtl92c_dm_init_edca_turbo(hw
);
322 if (rtlpci
->acm_method
!= eAcmWay2_SW
)
323 rtlpriv
->cfg
->ops
->set_hw_reg(hw
,
328 case HW_VAR_ACM_CTRL
:{
329 u8 e_aci
= *((u8
*) val
);
330 union aci_aifsn
*p_aci_aifsn
=
331 (union aci_aifsn
*)(&(mac
->ac
[0].aifs
));
332 u8 acm
= p_aci_aifsn
->f
.acm
;
333 u8 acm_ctrl
= rtl_read_byte(rtlpriv
, REG_ACMHWCTRL
);
336 acm_ctrl
| ((rtlpci
->acm_method
== 2) ? 0x0 : 0x1);
341 acm_ctrl
|= AcmHw_BeqEn
;
344 acm_ctrl
|= AcmHw_ViqEn
;
347 acm_ctrl
|= AcmHw_VoqEn
;
350 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_WARNING
,
351 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
358 acm_ctrl
&= (~AcmHw_BeqEn
);
361 acm_ctrl
&= (~AcmHw_ViqEn
);
364 acm_ctrl
&= (~AcmHw_BeqEn
);
367 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
,
368 "switch case not processed\n");
373 RT_TRACE(rtlpriv
, COMP_QOS
, DBG_TRACE
,
374 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
376 rtl_write_byte(rtlpriv
, REG_ACMHWCTRL
, acm_ctrl
);
380 rtl_write_dword(rtlpriv
, REG_RCR
, ((u32
*) (val
))[0]);
381 rtlpci
->receive_config
= ((u32
*) (val
))[0];
384 case HW_VAR_RETRY_LIMIT
:{
385 u8 retry_limit
= ((u8
*) (val
))[0];
387 rtl_write_word(rtlpriv
, REG_RL
,
388 retry_limit
<< RETRY_LIMIT_SHORT_SHIFT
|
389 retry_limit
<< RETRY_LIMIT_LONG_SHIFT
);
392 case HW_VAR_DUAL_TSF_RST
:
393 rtl_write_byte(rtlpriv
, REG_DUAL_TSF_RST
, (BIT(0) | BIT(1)));
395 case HW_VAR_EFUSE_BYTES
:
396 rtlefuse
->efuse_usedbytes
= *((u16
*) val
);
398 case HW_VAR_EFUSE_USAGE
:
399 rtlefuse
->efuse_usedpercentage
= *((u8
*) val
);
402 rtl92c_phy_set_io_cmd(hw
, (*(enum io_type
*)val
));
404 case HW_VAR_WPA_CONFIG
:
405 rtl_write_byte(rtlpriv
, REG_SECCFG
, *((u8
*) val
));
407 case HW_VAR_SET_RPWM
:{
410 rpwm_val
= rtl_read_byte(rtlpriv
, REG_PCIE_HRPWM
);
413 if (rpwm_val
& BIT(7)) {
414 rtl_write_byte(rtlpriv
, REG_PCIE_HRPWM
,
417 rtl_write_byte(rtlpriv
, REG_PCIE_HRPWM
,
418 ((*(u8
*) val
) | BIT(7)));
423 case HW_VAR_H2C_FW_PWRMODE
:{
424 u8 psmode
= (*(u8
*) val
);
426 if ((psmode
!= FW_PS_ACTIVE_MODE
) &&
427 (!IS_92C_SERIAL(rtlhal
->version
))) {
428 rtl92c_dm_rf_saving(hw
, true);
431 rtl92c_set_fw_pwrmode_cmd(hw
, (*(u8
*) val
));
434 case HW_VAR_FW_PSMODE_STATUS
:
435 ppsc
->fw_current_inpsmode
= *((bool *) val
);
437 case HW_VAR_H2C_FW_JOINBSSRPT
:{
438 u8 mstatus
= (*(u8
*) val
);
439 u8 tmp_regcr
, tmp_reg422
;
440 bool recover
= false;
442 if (mstatus
== RT_MEDIA_CONNECT
) {
443 rtlpriv
->cfg
->ops
->set_hw_reg(hw
, HW_VAR_AID
,
446 tmp_regcr
= rtl_read_byte(rtlpriv
, REG_CR
+ 1);
447 rtl_write_byte(rtlpriv
, REG_CR
+ 1,
448 (tmp_regcr
| BIT(0)));
450 _rtl92ce_set_bcn_ctrl_reg(hw
, 0, BIT(3));
451 _rtl92ce_set_bcn_ctrl_reg(hw
, BIT(4), 0);
454 rtl_read_byte(rtlpriv
,
455 REG_FWHW_TXQ_CTRL
+ 2);
456 if (tmp_reg422
& BIT(6))
458 rtl_write_byte(rtlpriv
, REG_FWHW_TXQ_CTRL
+ 2,
459 tmp_reg422
& (~BIT(6)));
461 rtl92c_set_fw_rsvdpagepkt(hw
, 0);
463 _rtl92ce_set_bcn_ctrl_reg(hw
, BIT(3), 0);
464 _rtl92ce_set_bcn_ctrl_reg(hw
, 0, BIT(4));
467 rtl_write_byte(rtlpriv
,
468 REG_FWHW_TXQ_CTRL
+ 2,
472 rtl_write_byte(rtlpriv
, REG_CR
+ 1,
473 (tmp_regcr
& ~(BIT(0))));
475 rtl92c_set_fw_joinbss_report_cmd(hw
, (*(u8
*) val
));
481 u2btmp
= rtl_read_word(rtlpriv
, REG_BCN_PSR_RPT
);
483 rtl_write_word(rtlpriv
, REG_BCN_PSR_RPT
, (u2btmp
|
488 case HW_VAR_CORRECT_TSF
:{
489 u8 btype_ibss
= ((u8
*) (val
))[0];
492 _rtl92ce_stop_tx_beacon(hw
);
494 _rtl92ce_set_bcn_ctrl_reg(hw
, 0, BIT(3));
496 rtl_write_dword(rtlpriv
, REG_TSFTR
,
497 (u32
) (mac
->tsf
& 0xffffffff));
498 rtl_write_dword(rtlpriv
, REG_TSFTR
+ 4,
499 (u32
) ((mac
->tsf
>> 32) & 0xffffffff));
501 _rtl92ce_set_bcn_ctrl_reg(hw
, BIT(3), 0);
504 _rtl92ce_resume_tx_beacon(hw
);
510 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
,
511 "switch case not processed\n");
516 static bool _rtl92ce_llt_write(struct ieee80211_hw
*hw
, u32 address
, u32 data
)
518 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
521 u32 value
= _LLT_INIT_ADDR(address
) |
522 _LLT_INIT_DATA(data
) | _LLT_OP(_LLT_WRITE_ACCESS
);
524 rtl_write_dword(rtlpriv
, REG_LLT_INIT
, value
);
527 value
= rtl_read_dword(rtlpriv
, REG_LLT_INIT
);
528 if (_LLT_NO_ACTIVE
== _LLT_OP_VALUE(value
))
531 if (count
> POLLING_LLT_THRESHOLD
) {
532 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
,
533 "Failed to polling write LLT done at address %d!\n",
543 static bool _rtl92ce_llt_table_init(struct ieee80211_hw
*hw
)
545 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
554 #elif LLT_CONFIG == 2
557 #elif LLT_CONFIG == 3
560 #elif LLT_CONFIG == 4
563 #elif LLT_CONFIG == 5
569 rtl_write_byte(rtlpriv
, REG_RQPN_NPQ
, 0x1c);
570 rtl_write_dword(rtlpriv
, REG_RQPN
, 0x80a71c1c);
571 #elif LLT_CONFIG == 2
572 rtl_write_dword(rtlpriv
, REG_RQPN
, 0x845B1010);
573 #elif LLT_CONFIG == 3
574 rtl_write_dword(rtlpriv
, REG_RQPN
, 0x84838484);
575 #elif LLT_CONFIG == 4
576 rtl_write_dword(rtlpriv
, REG_RQPN
, 0x80bd1c1c);
577 #elif LLT_CONFIG == 5
578 rtl_write_word(rtlpriv
, REG_RQPN_NPQ
, 0x0000);
580 rtl_write_dword(rtlpriv
, REG_RQPN
, 0x80b01c29);
583 rtl_write_dword(rtlpriv
, REG_TRXFF_BNDY
, (0x27FF0000 | txpktbuf_bndy
));
584 rtl_write_byte(rtlpriv
, REG_TDECTRL
+ 1, txpktbuf_bndy
);
586 rtl_write_byte(rtlpriv
, REG_TXPKTBUF_BCNQ_BDNY
, txpktbuf_bndy
);
587 rtl_write_byte(rtlpriv
, REG_TXPKTBUF_MGQ_BDNY
, txpktbuf_bndy
);
589 rtl_write_byte(rtlpriv
, 0x45D, txpktbuf_bndy
);
590 rtl_write_byte(rtlpriv
, REG_PBP
, 0x11);
591 rtl_write_byte(rtlpriv
, REG_RX_DRVINFO_SZ
, 0x4);
593 for (i
= 0; i
< (txpktbuf_bndy
- 1); i
++) {
594 status
= _rtl92ce_llt_write(hw
, i
, i
+ 1);
599 status
= _rtl92ce_llt_write(hw
, (txpktbuf_bndy
- 1), 0xFF);
603 for (i
= txpktbuf_bndy
; i
< maxPage
; i
++) {
604 status
= _rtl92ce_llt_write(hw
, i
, (i
+ 1));
609 status
= _rtl92ce_llt_write(hw
, maxPage
, txpktbuf_bndy
);
616 static void _rtl92ce_gen_refresh_led_state(struct ieee80211_hw
*hw
)
618 struct rtl_pci_priv
*pcipriv
= rtl_pcipriv(hw
);
619 struct rtl_pci
*rtlpci
= rtl_pcidev(rtl_pcipriv(hw
));
620 struct rtl_ps_ctl
*ppsc
= rtl_psc(rtl_priv(hw
));
621 struct rtl_led
*pLed0
= &(pcipriv
->ledctl
.sw_led0
);
623 if (rtlpci
->up_first_time
)
626 if (ppsc
->rfoff_reason
== RF_CHANGE_BY_IPS
)
627 rtl92ce_sw_led_on(hw
, pLed0
);
628 else if (ppsc
->rfoff_reason
== RF_CHANGE_BY_INIT
)
629 rtl92ce_sw_led_on(hw
, pLed0
);
631 rtl92ce_sw_led_off(hw
, pLed0
);
634 static bool _rtl92ce_init_mac(struct ieee80211_hw
*hw
)
636 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
637 struct rtl_pci_priv
*rtlpcipriv
= rtl_pcipriv(hw
);
638 struct rtl_pci
*rtlpci
= rtl_pcidev(rtl_pcipriv(hw
));
639 struct rtl_hal
*rtlhal
= rtl_hal(rtl_priv(hw
));
641 unsigned char bytetmp
;
642 unsigned short wordtmp
;
645 rtl_write_byte(rtlpriv
, REG_RSV_CTRL
, 0x00);
646 if (rtlpcipriv
->bt_coexist
.bt_coexistence
) {
648 value32
= rtl_read_dword(rtlpriv
, REG_APS_FSMCO
);
649 value32
|= (SOP_ABG
| SOP_AMB
| XOP_BTCK
);
650 rtl_write_dword(rtlpriv
, REG_APS_FSMCO
, value32
);
652 rtl_write_byte(rtlpriv
, REG_SPS0_CTRL
, 0x2b);
653 rtl_write_byte(rtlpriv
, REG_AFE_XTAL_CTRL
, 0x0F);
655 if (rtlpcipriv
->bt_coexist
.bt_coexistence
) {
656 u32 u4b_tmp
= rtl_read_dword(rtlpriv
, REG_AFE_XTAL_CTRL
);
658 u4b_tmp
&= (~0x00024800);
659 rtl_write_dword(rtlpriv
, REG_AFE_XTAL_CTRL
, u4b_tmp
);
662 bytetmp
= rtl_read_byte(rtlpriv
, REG_APS_FSMCO
+ 1) | BIT(0);
665 rtl_write_byte(rtlpriv
, REG_APS_FSMCO
+ 1, bytetmp
);
668 bytetmp
= rtl_read_byte(rtlpriv
, REG_APS_FSMCO
+ 1);
672 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_LOUD
, "reg0xec:%x:%x\n",
673 rtl_read_dword(rtlpriv
, 0xEC), bytetmp
);
675 while ((bytetmp
& BIT(0)) && retry
< 1000) {
678 bytetmp
= rtl_read_byte(rtlpriv
, REG_APS_FSMCO
+ 1);
679 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_LOUD
, "reg0xec:%x:%x\n",
680 rtl_read_dword(rtlpriv
, 0xEC), bytetmp
);
684 rtl_write_word(rtlpriv
, REG_APS_FSMCO
, 0x1012);
686 rtl_write_byte(rtlpriv
, REG_SYS_ISO_CTRL
+ 1, 0x82);
689 if (rtlpcipriv
->bt_coexist
.bt_coexistence
) {
690 bytetmp
= rtl_read_byte(rtlpriv
, REG_AFE_XTAL_CTRL
+2) & 0xfd;
691 rtl_write_byte(rtlpriv
, REG_AFE_XTAL_CTRL
+2, bytetmp
);
694 rtl_write_word(rtlpriv
, REG_CR
, 0x2ff);
696 if (!_rtl92ce_llt_table_init(hw
))
699 rtl_write_dword(rtlpriv
, REG_HISR
, 0xffffffff);
700 rtl_write_byte(rtlpriv
, REG_HISRE
, 0xff);
702 rtl_write_word(rtlpriv
, REG_TRXFF_BNDY
+ 2, 0x27ff);
704 wordtmp
= rtl_read_word(rtlpriv
, REG_TRXDMA_CTRL
);
707 rtl_write_word(rtlpriv
, REG_TRXDMA_CTRL
, wordtmp
);
709 rtl_write_byte(rtlpriv
, REG_FWHW_TXQ_CTRL
+ 1, 0x1F);
710 rtl_write_dword(rtlpriv
, REG_RCR
, rtlpci
->receive_config
);
711 rtl_write_dword(rtlpriv
, REG_TCR
, rtlpci
->transmit_config
);
713 rtl_write_byte(rtlpriv
, 0x4d0, 0x0);
715 rtl_write_dword(rtlpriv
, REG_BCNQ_DESA
,
716 ((u64
) rtlpci
->tx_ring
[BEACON_QUEUE
].dma
) &
718 rtl_write_dword(rtlpriv
, REG_MGQ_DESA
,
719 (u64
) rtlpci
->tx_ring
[MGNT_QUEUE
].dma
&
721 rtl_write_dword(rtlpriv
, REG_VOQ_DESA
,
722 (u64
) rtlpci
->tx_ring
[VO_QUEUE
].dma
& DMA_BIT_MASK(32));
723 rtl_write_dword(rtlpriv
, REG_VIQ_DESA
,
724 (u64
) rtlpci
->tx_ring
[VI_QUEUE
].dma
& DMA_BIT_MASK(32));
725 rtl_write_dword(rtlpriv
, REG_BEQ_DESA
,
726 (u64
) rtlpci
->tx_ring
[BE_QUEUE
].dma
& DMA_BIT_MASK(32));
727 rtl_write_dword(rtlpriv
, REG_BKQ_DESA
,
728 (u64
) rtlpci
->tx_ring
[BK_QUEUE
].dma
& DMA_BIT_MASK(32));
729 rtl_write_dword(rtlpriv
, REG_HQ_DESA
,
730 (u64
) rtlpci
->tx_ring
[HIGH_QUEUE
].dma
&
732 rtl_write_dword(rtlpriv
, REG_RX_DESA
,
733 (u64
) rtlpci
->rx_ring
[RX_MPDU_QUEUE
].dma
&
736 if (IS_92C_SERIAL(rtlhal
->version
))
737 rtl_write_byte(rtlpriv
, REG_PCIE_CTRL_REG
+ 3, 0x77);
739 rtl_write_byte(rtlpriv
, REG_PCIE_CTRL_REG
+ 3, 0x22);
741 rtl_write_dword(rtlpriv
, REG_INT_MIG
, 0);
743 bytetmp
= rtl_read_byte(rtlpriv
, REG_APSD_CTRL
);
744 rtl_write_byte(rtlpriv
, REG_APSD_CTRL
, bytetmp
& ~BIT(6));
747 bytetmp
= rtl_read_byte(rtlpriv
, REG_APSD_CTRL
);
748 } while ((retry
< 200) && (bytetmp
& BIT(7)));
750 _rtl92ce_gen_refresh_led_state(hw
);
752 rtl_write_dword(rtlpriv
, REG_MCUTST_1
, 0x0);
757 static void _rtl92ce_hw_configure(struct ieee80211_hw
*hw
)
759 struct rtl_pci
*rtlpci
= rtl_pcidev(rtl_pcipriv(hw
));
760 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
761 struct rtl_pci_priv
*rtlpcipriv
= rtl_pcipriv(hw
);
765 reg_bw_opmode
= BW_OPMODE_20MHZ
;
766 reg_prsr
= RATE_ALL_CCK
| RATE_ALL_OFDM_AG
;
768 rtl_write_byte(rtlpriv
, REG_INIRTS_RATE_SEL
, 0x8);
770 rtl_write_byte(rtlpriv
, REG_BWOPMODE
, reg_bw_opmode
);
772 rtl_write_dword(rtlpriv
, REG_RRSR
, reg_prsr
);
774 rtl_write_byte(rtlpriv
, REG_SLOT
, 0x09);
776 rtl_write_byte(rtlpriv
, REG_AMPDU_MIN_SPACE
, 0x0);
778 rtl_write_word(rtlpriv
, REG_FWHW_TXQ_CTRL
, 0x1F80);
780 rtl_write_word(rtlpriv
, REG_RL
, 0x0707);
782 rtl_write_dword(rtlpriv
, REG_BAR_MODE_CTRL
, 0x02012802);
784 rtl_write_byte(rtlpriv
, REG_HWSEQ_CTRL
, 0xFF);
786 rtl_write_dword(rtlpriv
, REG_DARFRC
, 0x01000000);
787 rtl_write_dword(rtlpriv
, REG_DARFRC
+ 4, 0x07060504);
788 rtl_write_dword(rtlpriv
, REG_RARFRC
, 0x01000000);
789 rtl_write_dword(rtlpriv
, REG_RARFRC
+ 4, 0x07060504);
791 if ((rtlpcipriv
->bt_coexist
.bt_coexistence
) &&
792 (rtlpcipriv
->bt_coexist
.bt_coexist_type
== BT_CSR_BC4
))
793 rtl_write_dword(rtlpriv
, REG_AGGLEN_LMT
, 0x97427431);
795 rtl_write_dword(rtlpriv
, REG_AGGLEN_LMT
, 0xb972a841);
797 rtl_write_byte(rtlpriv
, REG_ATIMWND
, 0x2);
799 rtl_write_byte(rtlpriv
, REG_BCN_MAX_ERR
, 0xff);
801 rtlpci
->reg_bcn_ctrl_val
= 0x1f;
802 rtl_write_byte(rtlpriv
, REG_BCN_CTRL
, rtlpci
->reg_bcn_ctrl_val
);
804 rtl_write_byte(rtlpriv
, REG_TBTT_PROHIBIT
+ 1, 0xff);
806 rtl_write_byte(rtlpriv
, REG_TBTT_PROHIBIT
+ 1, 0xff);
808 rtl_write_byte(rtlpriv
, REG_PIFS
, 0x1C);
809 rtl_write_byte(rtlpriv
, REG_AGGR_BREAK_TIME
, 0x16);
811 if ((rtlpcipriv
->bt_coexist
.bt_coexistence
) &&
812 (rtlpcipriv
->bt_coexist
.bt_coexist_type
== BT_CSR_BC4
)) {
813 rtl_write_word(rtlpriv
, REG_NAV_PROT_LEN
, 0x0020);
814 rtl_write_word(rtlpriv
, REG_PROT_MODE_CTRL
, 0x0402);
816 rtl_write_word(rtlpriv
, REG_NAV_PROT_LEN
, 0x0020);
817 rtl_write_word(rtlpriv
, REG_NAV_PROT_LEN
, 0x0020);
820 if ((rtlpcipriv
->bt_coexist
.bt_coexistence
) &&
821 (rtlpcipriv
->bt_coexist
.bt_coexist_type
== BT_CSR_BC4
))
822 rtl_write_dword(rtlpriv
, REG_FAST_EDCA_CTRL
, 0x03086666);
824 rtl_write_dword(rtlpriv
, REG_FAST_EDCA_CTRL
, 0x086666);
826 rtl_write_byte(rtlpriv
, REG_ACKTO
, 0x40);
828 rtl_write_word(rtlpriv
, REG_SPEC_SIFS
, 0x1010);
829 rtl_write_word(rtlpriv
, REG_MAC_SPEC_SIFS
, 0x1010);
831 rtl_write_word(rtlpriv
, REG_SIFS_CTX
, 0x1010);
833 rtl_write_word(rtlpriv
, REG_SIFS_TRX
, 0x1010);
835 rtl_write_dword(rtlpriv
, REG_MAR
, 0xffffffff);
836 rtl_write_dword(rtlpriv
, REG_MAR
+ 4, 0xffffffff);
840 static void _rtl92ce_enable_aspm_back_door(struct ieee80211_hw
*hw
)
842 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
843 struct rtl_ps_ctl
*ppsc
= rtl_psc(rtl_priv(hw
));
845 rtl_write_byte(rtlpriv
, 0x34b, 0x93);
846 rtl_write_word(rtlpriv
, 0x350, 0x870c);
847 rtl_write_byte(rtlpriv
, 0x352, 0x1);
849 if (ppsc
->support_backdoor
)
850 rtl_write_byte(rtlpriv
, 0x349, 0x1b);
852 rtl_write_byte(rtlpriv
, 0x349, 0x03);
854 rtl_write_word(rtlpriv
, 0x350, 0x2718);
855 rtl_write_byte(rtlpriv
, 0x352, 0x1);
858 void rtl92ce_enable_hw_security_config(struct ieee80211_hw
*hw
)
860 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
863 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_LOUD
,
864 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
865 rtlpriv
->sec
.pairwise_enc_algorithm
,
866 rtlpriv
->sec
.group_enc_algorithm
);
868 if (rtlpriv
->cfg
->mod_params
->sw_crypto
|| rtlpriv
->sec
.use_sw_sec
) {
869 RT_TRACE(rtlpriv
, COMP_SEC
, DBG_DMESG
,
870 "not open hw encryption\n");
874 sec_reg_value
= SCR_TxEncEnable
| SCR_RxDecEnable
;
876 if (rtlpriv
->sec
.use_defaultkey
) {
877 sec_reg_value
|= SCR_TxUseDK
;
878 sec_reg_value
|= SCR_RxUseDK
;
881 sec_reg_value
|= (SCR_RXBCUSEDK
| SCR_TXBCUSEDK
);
883 rtl_write_byte(rtlpriv
, REG_CR
+ 1, 0x02);
885 RT_TRACE(rtlpriv
, COMP_SEC
, DBG_LOUD
,
886 "The SECR-value %x\n", sec_reg_value
);
888 rtlpriv
->cfg
->ops
->set_hw_reg(hw
, HW_VAR_WPA_CONFIG
, &sec_reg_value
);
892 int rtl92ce_hw_init(struct ieee80211_hw
*hw
)
894 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
895 struct rtl_hal
*rtlhal
= rtl_hal(rtl_priv(hw
));
896 struct rtl_mac
*mac
= rtl_mac(rtl_priv(hw
));
897 struct rtl_phy
*rtlphy
= &(rtlpriv
->phy
);
898 struct rtl_pci
*rtlpci
= rtl_pcidev(rtl_pcipriv(hw
));
899 struct rtl_ps_ctl
*ppsc
= rtl_psc(rtl_priv(hw
));
900 static bool iqk_initialized
; /* initialized to false */
901 bool rtstatus
= true;
906 rtlpci
->being_init_adapter
= true;
907 rtlpriv
->intf_ops
->disable_aspm(hw
);
908 rtstatus
= _rtl92ce_init_mac(hw
);
910 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
, "Init MAC failed\n");
915 err
= rtl92c_download_fw(hw
);
917 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_WARNING
,
918 "Failed to download FW. Init HW without FW now..\n");
923 rtlhal
->last_hmeboxnum
= 0;
924 rtl92c_phy_mac_config(hw
);
925 rtl92c_phy_bb_config(hw
);
926 rtlphy
->rf_mode
= RF_OP_BY_SW_3WIRE
;
927 rtl92c_phy_rf_config(hw
);
928 rtlphy
->rfreg_chnlval
[0] = rtl_get_rfreg(hw
, (enum radio_path
)0,
929 RF_CHNLBW
, RFREG_OFFSET_MASK
);
930 rtlphy
->rfreg_chnlval
[1] = rtl_get_rfreg(hw
, (enum radio_path
)1,
931 RF_CHNLBW
, RFREG_OFFSET_MASK
);
932 rtl_set_bbreg(hw
, RFPGA0_RFMOD
, BCCKEN
, 0x1);
933 rtl_set_bbreg(hw
, RFPGA0_RFMOD
, BOFDMEN
, 0x1);
934 rtl_set_bbreg(hw
, RFPGA0_ANALOGPARAMETER2
, BIT(10), 1);
935 _rtl92ce_hw_configure(hw
);
936 rtl_cam_reset_all_entry(hw
);
937 rtl92ce_enable_hw_security_config(hw
);
939 ppsc
->rfpwr_state
= ERFON
;
941 rtlpriv
->cfg
->ops
->set_hw_reg(hw
, HW_VAR_ETHER_ADDR
, mac
->mac_addr
);
942 _rtl92ce_enable_aspm_back_door(hw
);
943 rtlpriv
->intf_ops
->enable_aspm(hw
);
945 rtl8192ce_bt_hw_init(hw
);
947 if (ppsc
->rfpwr_state
== ERFON
) {
948 rtl92c_phy_set_rfpath_switch(hw
, 1);
949 if (iqk_initialized
) {
950 rtl92c_phy_iq_calibrate(hw
, true);
952 rtl92c_phy_iq_calibrate(hw
, false);
953 iqk_initialized
= true;
956 rtl92c_dm_check_txpower_tracking(hw
);
957 rtl92c_phy_lc_calibrate(hw
);
960 is92c
= IS_92C_SERIAL(rtlhal
->version
);
961 tmp_u1b
= efuse_read_1byte(hw
, 0x1FA);
962 if (!(tmp_u1b
& BIT(0))) {
963 rtl_set_rfreg(hw
, RF90_PATH_A
, 0x15, 0x0F, 0x05);
964 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_TRACE
, "PA BIAS path A\n");
967 if (!(tmp_u1b
& BIT(1)) && is92c
) {
968 rtl_set_rfreg(hw
, RF90_PATH_B
, 0x15, 0x0F, 0x05);
969 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_TRACE
, "PA BIAS path B\n");
972 if (!(tmp_u1b
& BIT(4))) {
973 tmp_u1b
= rtl_read_byte(rtlpriv
, 0x16);
975 rtl_write_byte(rtlpriv
, 0x16, tmp_u1b
| 0x80);
977 rtl_write_byte(rtlpriv
, 0x16, tmp_u1b
| 0x90);
978 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_TRACE
, "under 1.5V\n");
981 rtlpci
->being_init_adapter
= false;
985 static enum version_8192c
_rtl92ce_read_chip_version(struct ieee80211_hw
*hw
)
987 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
988 struct rtl_phy
*rtlphy
= &(rtlpriv
->phy
);
989 enum version_8192c version
= VERSION_UNKNOWN
;
991 const char *versionid
;
993 value32
= rtl_read_dword(rtlpriv
, REG_SYS_CFG
);
994 if (value32
& TRP_VAUX_EN
) {
995 version
= (value32
& TYPE_ID
) ? VERSION_A_CHIP_92C
:
998 version
= (value32
& TYPE_ID
) ? VERSION_B_CHIP_92C
:
1003 case VERSION_B_CHIP_92C
:
1004 versionid
= "B_CHIP_92C";
1006 case VERSION_B_CHIP_88C
:
1007 versionid
= "B_CHIP_88C";
1009 case VERSION_A_CHIP_92C
:
1010 versionid
= "A_CHIP_92C";
1012 case VERSION_A_CHIP_88C
:
1013 versionid
= "A_CHIP_88C";
1016 versionid
= "Unknown. Bug?";
1020 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_TRACE
,
1021 "Chip Version ID: %s\n", versionid
);
1023 switch (version
& 0x3) {
1025 rtlphy
->rf_type
= RF_1T1R
;
1028 rtlphy
->rf_type
= RF_2T2R
;
1031 rtlphy
->rf_type
= RF_1T2R
;
1034 rtlphy
->rf_type
= RF_1T1R
;
1035 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
,
1036 "ERROR RF_Type is set!!\n");
1040 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_LOUD
, "Chip RF Type: %s\n",
1041 rtlphy
->rf_type
== RF_2T2R
? "RF_2T2R" : "RF_1T1R");
1046 static int _rtl92ce_set_media_status(struct ieee80211_hw
*hw
,
1047 enum nl80211_iftype type
)
1049 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1050 u8 bt_msr
= rtl_read_byte(rtlpriv
, MSR
);
1051 enum led_ctl_mode ledaction
= LED_CTL_NO_LINK
;
1054 if (type
== NL80211_IFTYPE_UNSPECIFIED
||
1055 type
== NL80211_IFTYPE_STATION
) {
1056 _rtl92ce_stop_tx_beacon(hw
);
1057 _rtl92ce_enable_bcn_sub_func(hw
);
1058 } else if (type
== NL80211_IFTYPE_ADHOC
|| type
== NL80211_IFTYPE_AP
) {
1059 _rtl92ce_resume_tx_beacon(hw
);
1060 _rtl92ce_disable_bcn_sub_func(hw
);
1062 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_WARNING
,
1063 "Set HW_VAR_MEDIA_STATUS: No such media status(%x)\n",
1068 case NL80211_IFTYPE_UNSPECIFIED
:
1069 bt_msr
|= MSR_NOLINK
;
1070 ledaction
= LED_CTL_LINK
;
1071 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_TRACE
,
1072 "Set Network type to NO LINK!\n");
1074 case NL80211_IFTYPE_ADHOC
:
1075 bt_msr
|= MSR_ADHOC
;
1076 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_TRACE
,
1077 "Set Network type to Ad Hoc!\n");
1079 case NL80211_IFTYPE_STATION
:
1080 bt_msr
|= MSR_INFRA
;
1081 ledaction
= LED_CTL_LINK
;
1082 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_TRACE
,
1083 "Set Network type to STA!\n");
1085 case NL80211_IFTYPE_AP
:
1087 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_TRACE
,
1088 "Set Network type to AP!\n");
1091 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
,
1092 "Network type %d not supported!\n", type
);
1098 rtl_write_byte(rtlpriv
, (MSR
), bt_msr
);
1099 rtlpriv
->cfg
->ops
->led_control(hw
, ledaction
);
1100 if ((bt_msr
& 0xfc) == MSR_AP
)
1101 rtl_write_byte(rtlpriv
, REG_BCNTCFG
+ 1, 0x00);
1103 rtl_write_byte(rtlpriv
, REG_BCNTCFG
+ 1, 0x66);
1107 void rtl92ce_set_check_bssid(struct ieee80211_hw
*hw
, bool check_bssid
)
1109 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1110 u32 reg_rcr
= rtl_read_dword(rtlpriv
, REG_RCR
);
1112 if (rtlpriv
->psc
.rfpwr_state
!= ERFON
)
1116 reg_rcr
|= (RCR_CBSSID_DATA
| RCR_CBSSID_BCN
);
1117 rtlpriv
->cfg
->ops
->set_hw_reg(hw
, HW_VAR_RCR
,
1119 _rtl92ce_set_bcn_ctrl_reg(hw
, 0, BIT(4));
1120 } else if (!check_bssid
) {
1121 reg_rcr
&= (~(RCR_CBSSID_DATA
| RCR_CBSSID_BCN
));
1122 _rtl92ce_set_bcn_ctrl_reg(hw
, BIT(4), 0);
1123 rtlpriv
->cfg
->ops
->set_hw_reg(hw
,
1124 HW_VAR_RCR
, (u8
*) (®_rcr
));
1129 int rtl92ce_set_network_type(struct ieee80211_hw
*hw
, enum nl80211_iftype type
)
1131 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1133 if (_rtl92ce_set_media_status(hw
, type
))
1136 if (rtlpriv
->mac80211
.link_state
== MAC80211_LINKED
) {
1137 if (type
!= NL80211_IFTYPE_AP
)
1138 rtl92ce_set_check_bssid(hw
, true);
1140 rtl92ce_set_check_bssid(hw
, false);
1146 /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */
1147 void rtl92ce_set_qos(struct ieee80211_hw
*hw
, int aci
)
1149 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1150 rtl92c_dm_init_edca_turbo(hw
);
1153 rtl_write_dword(rtlpriv
, REG_EDCA_BK_PARAM
, 0xa44f);
1156 /* rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, u4b_ac_param); */
1159 rtl_write_dword(rtlpriv
, REG_EDCA_VI_PARAM
, 0x5e4322);
1162 rtl_write_dword(rtlpriv
, REG_EDCA_VO_PARAM
, 0x2f3222);
1165 RT_ASSERT(false, "invalid aci: %d !\n", aci
);
1170 void rtl92ce_enable_interrupt(struct ieee80211_hw
*hw
)
1172 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1173 struct rtl_pci
*rtlpci
= rtl_pcidev(rtl_pcipriv(hw
));
1175 rtl_write_dword(rtlpriv
, REG_HIMR
, rtlpci
->irq_mask
[0] & 0xFFFFFFFF);
1176 rtl_write_dword(rtlpriv
, REG_HIMRE
, rtlpci
->irq_mask
[1] & 0xFFFFFFFF);
1179 void rtl92ce_disable_interrupt(struct ieee80211_hw
*hw
)
1181 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1182 struct rtl_pci
*rtlpci
= rtl_pcidev(rtl_pcipriv(hw
));
1184 rtl_write_dword(rtlpriv
, REG_HIMR
, IMR8190_DISABLED
);
1185 rtl_write_dword(rtlpriv
, REG_HIMRE
, IMR8190_DISABLED
);
1186 synchronize_irq(rtlpci
->pdev
->irq
);
1189 static void _rtl92ce_poweroff_adapter(struct ieee80211_hw
*hw
)
1191 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1192 struct rtl_pci_priv
*rtlpcipriv
= rtl_pcipriv(hw
);
1196 rtlpriv
->intf_ops
->enable_aspm(hw
);
1197 rtl_write_byte(rtlpriv
, REG_TXPAUSE
, 0xFF);
1198 rtl_set_rfreg(hw
, RF90_PATH_A
, 0x00, RFREG_OFFSET_MASK
, 0x00);
1199 rtl_write_byte(rtlpriv
, REG_RF_CTRL
, 0x00);
1200 rtl_write_byte(rtlpriv
, REG_APSD_CTRL
, 0x40);
1201 rtl_write_byte(rtlpriv
, REG_SYS_FUNC_EN
, 0xE2);
1202 rtl_write_byte(rtlpriv
, REG_SYS_FUNC_EN
, 0xE0);
1203 if (rtl_read_byte(rtlpriv
, REG_MCUFWDL
) & BIT(7))
1204 rtl92c_firmware_selfreset(hw
);
1205 rtl_write_byte(rtlpriv
, REG_SYS_FUNC_EN
+ 1, 0x51);
1206 rtl_write_byte(rtlpriv
, REG_MCUFWDL
, 0x00);
1207 rtl_write_dword(rtlpriv
, REG_GPIO_PIN_CTRL
, 0x00000000);
1208 u1b_tmp
= rtl_read_byte(rtlpriv
, REG_GPIO_PIN_CTRL
);
1209 if ((rtlpcipriv
->bt_coexist
.bt_coexistence
) &&
1210 ((rtlpcipriv
->bt_coexist
.bt_coexist_type
== BT_CSR_BC4
) ||
1211 (rtlpcipriv
->bt_coexist
.bt_coexist_type
== BT_CSR_BC8
))) {
1212 rtl_write_dword(rtlpriv
, REG_GPIO_PIN_CTRL
, 0x00F30000 |
1215 rtl_write_dword(rtlpriv
, REG_GPIO_PIN_CTRL
, 0x00FF0000 |
1218 rtl_write_word(rtlpriv
, REG_GPIO_IO_SEL
, 0x0790);
1219 rtl_write_word(rtlpriv
, REG_LEDCFG0
, 0x8080);
1220 rtl_write_byte(rtlpriv
, REG_AFE_PLL_CTRL
, 0x80);
1221 rtl_write_byte(rtlpriv
, REG_SPS0_CTRL
, 0x23);
1222 if (rtlpcipriv
->bt_coexist
.bt_coexistence
) {
1223 u4b_tmp
= rtl_read_dword(rtlpriv
, REG_AFE_XTAL_CTRL
);
1224 u4b_tmp
|= 0x03824800;
1225 rtl_write_dword(rtlpriv
, REG_AFE_XTAL_CTRL
, u4b_tmp
);
1227 rtl_write_dword(rtlpriv
, REG_AFE_XTAL_CTRL
, 0x0e);
1230 rtl_write_byte(rtlpriv
, REG_RSV_CTRL
, 0x0e);
1231 rtl_write_byte(rtlpriv
, REG_APS_FSMCO
+ 1, 0x10);
1234 void rtl92ce_card_disable(struct ieee80211_hw
*hw
)
1236 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1237 struct rtl_ps_ctl
*ppsc
= rtl_psc(rtl_priv(hw
));
1238 struct rtl_pci
*rtlpci
= rtl_pcidev(rtl_pcipriv(hw
));
1239 struct rtl_mac
*mac
= rtl_mac(rtl_priv(hw
));
1240 enum nl80211_iftype opmode
;
1242 mac
->link_state
= MAC80211_NOLINK
;
1243 opmode
= NL80211_IFTYPE_UNSPECIFIED
;
1244 _rtl92ce_set_media_status(hw
, opmode
);
1245 if (rtlpci
->driver_is_goingto_unload
||
1246 ppsc
->rfoff_reason
> RF_CHANGE_BY_PS
)
1247 rtlpriv
->cfg
->ops
->led_control(hw
, LED_CTL_POWER_OFF
);
1248 RT_SET_PS_LEVEL(ppsc
, RT_RF_OFF_LEVL_HALT_NIC
);
1249 _rtl92ce_poweroff_adapter(hw
);
1252 void rtl92ce_interrupt_recognized(struct ieee80211_hw
*hw
,
1253 u32
*p_inta
, u32
*p_intb
)
1255 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1256 struct rtl_pci
*rtlpci
= rtl_pcidev(rtl_pcipriv(hw
));
1258 *p_inta
= rtl_read_dword(rtlpriv
, ISR
) & rtlpci
->irq_mask
[0];
1259 rtl_write_dword(rtlpriv
, ISR
, *p_inta
);
1262 * *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1];
1263 * rtl_write_dword(rtlpriv, ISR + 4, *p_intb);
1267 void rtl92ce_set_beacon_related_registers(struct ieee80211_hw
*hw
)
1270 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1271 struct rtl_mac
*mac
= rtl_mac(rtl_priv(hw
));
1272 u16 bcn_interval
, atim_window
;
1274 bcn_interval
= mac
->beacon_interval
;
1275 atim_window
= 2; /*FIX MERGE */
1276 rtl92ce_disable_interrupt(hw
);
1277 rtl_write_word(rtlpriv
, REG_ATIMWND
, atim_window
);
1278 rtl_write_word(rtlpriv
, REG_BCN_INTERVAL
, bcn_interval
);
1279 rtl_write_word(rtlpriv
, REG_BCNTCFG
, 0x660f);
1280 rtl_write_byte(rtlpriv
, REG_RXTSF_OFFSET_CCK
, 0x18);
1281 rtl_write_byte(rtlpriv
, REG_RXTSF_OFFSET_OFDM
, 0x18);
1282 rtl_write_byte(rtlpriv
, 0x606, 0x30);
1283 rtl92ce_enable_interrupt(hw
);
1286 void rtl92ce_set_beacon_interval(struct ieee80211_hw
*hw
)
1288 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1289 struct rtl_mac
*mac
= rtl_mac(rtl_priv(hw
));
1290 u16 bcn_interval
= mac
->beacon_interval
;
1292 RT_TRACE(rtlpriv
, COMP_BEACON
, DBG_DMESG
,
1293 "beacon_interval:%d\n", bcn_interval
);
1294 rtl92ce_disable_interrupt(hw
);
1295 rtl_write_word(rtlpriv
, REG_BCN_INTERVAL
, bcn_interval
);
1296 rtl92ce_enable_interrupt(hw
);
1299 void rtl92ce_update_interrupt_mask(struct ieee80211_hw
*hw
,
1300 u32 add_msr
, u32 rm_msr
)
1302 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1303 struct rtl_pci
*rtlpci
= rtl_pcidev(rtl_pcipriv(hw
));
1305 RT_TRACE(rtlpriv
, COMP_INTR
, DBG_LOUD
, "add_msr:%x, rm_msr:%x\n",
1309 rtlpci
->irq_mask
[0] |= add_msr
;
1311 rtlpci
->irq_mask
[0] &= (~rm_msr
);
1312 rtl92ce_disable_interrupt(hw
);
1313 rtl92ce_enable_interrupt(hw
);
1316 static void _rtl92ce_read_txpower_info_from_hwpg(struct ieee80211_hw
*hw
,
1320 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1321 struct rtl_efuse
*rtlefuse
= rtl_efuse(rtl_priv(hw
));
1322 u8 rf_path
, index
, tempval
;
1325 for (rf_path
= 0; rf_path
< 2; rf_path
++) {
1326 for (i
= 0; i
< 3; i
++) {
1327 if (!autoload_fail
) {
1329 eeprom_chnlarea_txpwr_cck
[rf_path
][i
] =
1330 hwinfo
[EEPROM_TXPOWERCCK
+ rf_path
* 3 + i
];
1332 eeprom_chnlarea_txpwr_ht40_1s
[rf_path
][i
] =
1333 hwinfo
[EEPROM_TXPOWERHT40_1S
+ rf_path
* 3 +
1337 eeprom_chnlarea_txpwr_cck
[rf_path
][i
] =
1338 EEPROM_DEFAULT_TXPOWERLEVEL
;
1340 eeprom_chnlarea_txpwr_ht40_1s
[rf_path
][i
] =
1341 EEPROM_DEFAULT_TXPOWERLEVEL
;
1346 for (i
= 0; i
< 3; i
++) {
1348 tempval
= hwinfo
[EEPROM_TXPOWERHT40_2SDIFF
+ i
];
1350 tempval
= EEPROM_DEFAULT_HT40_2SDIFF
;
1351 rtlefuse
->eeprom_chnlarea_txpwr_ht40_2sdiif
[RF90_PATH_A
][i
] =
1353 rtlefuse
->eeprom_chnlarea_txpwr_ht40_2sdiif
[RF90_PATH_B
][i
] =
1354 ((tempval
& 0xf0) >> 4);
1357 for (rf_path
= 0; rf_path
< 2; rf_path
++)
1358 for (i
= 0; i
< 3; i
++)
1359 RTPRINT(rtlpriv
, FINIT
, INIT_EEPROM
,
1360 "RF(%d) EEPROM CCK Area(%d) = 0x%x\n",
1363 eeprom_chnlarea_txpwr_cck
[rf_path
][i
]);
1364 for (rf_path
= 0; rf_path
< 2; rf_path
++)
1365 for (i
= 0; i
< 3; i
++)
1366 RTPRINT(rtlpriv
, FINIT
, INIT_EEPROM
,
1367 "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
1370 eeprom_chnlarea_txpwr_ht40_1s
[rf_path
][i
]);
1371 for (rf_path
= 0; rf_path
< 2; rf_path
++)
1372 for (i
= 0; i
< 3; i
++)
1373 RTPRINT(rtlpriv
, FINIT
, INIT_EEPROM
,
1374 "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
1377 eeprom_chnlarea_txpwr_ht40_2sdiif
[rf_path
][i
]);
1379 for (rf_path
= 0; rf_path
< 2; rf_path
++) {
1380 for (i
= 0; i
< 14; i
++) {
1381 index
= _rtl92c_get_chnl_group((u8
) i
);
1383 rtlefuse
->txpwrlevel_cck
[rf_path
][i
] =
1384 rtlefuse
->eeprom_chnlarea_txpwr_cck
[rf_path
][index
];
1385 rtlefuse
->txpwrlevel_ht40_1s
[rf_path
][i
] =
1387 eeprom_chnlarea_txpwr_ht40_1s
[rf_path
][index
];
1390 eeprom_chnlarea_txpwr_ht40_1s
[rf_path
][index
] -
1392 eeprom_chnlarea_txpwr_ht40_2sdiif
[rf_path
][index
])
1394 rtlefuse
->txpwrlevel_ht40_2s
[rf_path
][i
] =
1396 eeprom_chnlarea_txpwr_ht40_1s
[rf_path
]
1399 eeprom_chnlarea_txpwr_ht40_2sdiif
[rf_path
]
1402 rtlefuse
->txpwrlevel_ht40_2s
[rf_path
][i
] = 0;
1406 for (i
= 0; i
< 14; i
++) {
1407 RTPRINT(rtlpriv
, FINIT
, INIT_TxPower
,
1408 "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n",
1410 rtlefuse
->txpwrlevel_cck
[rf_path
][i
],
1411 rtlefuse
->txpwrlevel_ht40_1s
[rf_path
][i
],
1412 rtlefuse
->txpwrlevel_ht40_2s
[rf_path
][i
]);
1416 for (i
= 0; i
< 3; i
++) {
1417 if (!autoload_fail
) {
1418 rtlefuse
->eeprom_pwrlimit_ht40
[i
] =
1419 hwinfo
[EEPROM_TXPWR_GROUP
+ i
];
1420 rtlefuse
->eeprom_pwrlimit_ht20
[i
] =
1421 hwinfo
[EEPROM_TXPWR_GROUP
+ 3 + i
];
1423 rtlefuse
->eeprom_pwrlimit_ht40
[i
] = 0;
1424 rtlefuse
->eeprom_pwrlimit_ht20
[i
] = 0;
1428 for (rf_path
= 0; rf_path
< 2; rf_path
++) {
1429 for (i
= 0; i
< 14; i
++) {
1430 index
= _rtl92c_get_chnl_group((u8
) i
);
1432 if (rf_path
== RF90_PATH_A
) {
1433 rtlefuse
->pwrgroup_ht20
[rf_path
][i
] =
1434 (rtlefuse
->eeprom_pwrlimit_ht20
[index
]
1436 rtlefuse
->pwrgroup_ht40
[rf_path
][i
] =
1437 (rtlefuse
->eeprom_pwrlimit_ht40
[index
]
1439 } else if (rf_path
== RF90_PATH_B
) {
1440 rtlefuse
->pwrgroup_ht20
[rf_path
][i
] =
1441 ((rtlefuse
->eeprom_pwrlimit_ht20
[index
]
1443 rtlefuse
->pwrgroup_ht40
[rf_path
][i
] =
1444 ((rtlefuse
->eeprom_pwrlimit_ht40
[index
]
1448 RTPRINT(rtlpriv
, FINIT
, INIT_TxPower
,
1449 "RF-%d pwrgroup_ht20[%d] = 0x%x\n",
1451 rtlefuse
->pwrgroup_ht20
[rf_path
][i
]);
1452 RTPRINT(rtlpriv
, FINIT
, INIT_TxPower
,
1453 "RF-%d pwrgroup_ht40[%d] = 0x%x\n",
1455 rtlefuse
->pwrgroup_ht40
[rf_path
][i
]);
1459 for (i
= 0; i
< 14; i
++) {
1460 index
= _rtl92c_get_chnl_group((u8
) i
);
1463 tempval
= hwinfo
[EEPROM_TXPOWERHT20DIFF
+ index
];
1465 tempval
= EEPROM_DEFAULT_HT20_DIFF
;
1467 rtlefuse
->txpwr_ht20diff
[RF90_PATH_A
][i
] = (tempval
& 0xF);
1468 rtlefuse
->txpwr_ht20diff
[RF90_PATH_B
][i
] =
1469 ((tempval
>> 4) & 0xF);
1471 if (rtlefuse
->txpwr_ht20diff
[RF90_PATH_A
][i
] & BIT(3))
1472 rtlefuse
->txpwr_ht20diff
[RF90_PATH_A
][i
] |= 0xF0;
1474 if (rtlefuse
->txpwr_ht20diff
[RF90_PATH_B
][i
] & BIT(3))
1475 rtlefuse
->txpwr_ht20diff
[RF90_PATH_B
][i
] |= 0xF0;
1477 index
= _rtl92c_get_chnl_group((u8
) i
);
1480 tempval
= hwinfo
[EEPROM_TXPOWER_OFDMDIFF
+ index
];
1482 tempval
= EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF
;
1484 rtlefuse
->txpwr_legacyhtdiff
[RF90_PATH_A
][i
] = (tempval
& 0xF);
1485 rtlefuse
->txpwr_legacyhtdiff
[RF90_PATH_B
][i
] =
1486 ((tempval
>> 4) & 0xF);
1489 rtlefuse
->legacy_ht_txpowerdiff
=
1490 rtlefuse
->txpwr_legacyhtdiff
[RF90_PATH_A
][7];
1492 for (i
= 0; i
< 14; i
++)
1493 RTPRINT(rtlpriv
, FINIT
, INIT_TxPower
,
1494 "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n",
1495 i
, rtlefuse
->txpwr_ht20diff
[RF90_PATH_A
][i
]);
1496 for (i
= 0; i
< 14; i
++)
1497 RTPRINT(rtlpriv
, FINIT
, INIT_TxPower
,
1498 "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n",
1499 i
, rtlefuse
->txpwr_legacyhtdiff
[RF90_PATH_A
][i
]);
1500 for (i
= 0; i
< 14; i
++)
1501 RTPRINT(rtlpriv
, FINIT
, INIT_TxPower
,
1502 "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n",
1503 i
, rtlefuse
->txpwr_ht20diff
[RF90_PATH_B
][i
]);
1504 for (i
= 0; i
< 14; i
++)
1505 RTPRINT(rtlpriv
, FINIT
, INIT_TxPower
,
1506 "RF-B Legacy to HT40 Diff[%d] = 0x%x\n",
1507 i
, rtlefuse
->txpwr_legacyhtdiff
[RF90_PATH_B
][i
]);
1510 rtlefuse
->eeprom_regulatory
= (hwinfo
[RF_OPTION1
] & 0x7);
1512 rtlefuse
->eeprom_regulatory
= 0;
1513 RTPRINT(rtlpriv
, FINIT
, INIT_TxPower
,
1514 "eeprom_regulatory = 0x%x\n", rtlefuse
->eeprom_regulatory
);
1516 if (!autoload_fail
) {
1517 rtlefuse
->eeprom_tssi
[RF90_PATH_A
] = hwinfo
[EEPROM_TSSI_A
];
1518 rtlefuse
->eeprom_tssi
[RF90_PATH_B
] = hwinfo
[EEPROM_TSSI_B
];
1520 rtlefuse
->eeprom_tssi
[RF90_PATH_A
] = EEPROM_DEFAULT_TSSI
;
1521 rtlefuse
->eeprom_tssi
[RF90_PATH_B
] = EEPROM_DEFAULT_TSSI
;
1523 RTPRINT(rtlpriv
, FINIT
, INIT_TxPower
, "TSSI_A = 0x%x, TSSI_B = 0x%x\n",
1524 rtlefuse
->eeprom_tssi
[RF90_PATH_A
],
1525 rtlefuse
->eeprom_tssi
[RF90_PATH_B
]);
1528 tempval
= hwinfo
[EEPROM_THERMAL_METER
];
1530 tempval
= EEPROM_DEFAULT_THERMALMETER
;
1531 rtlefuse
->eeprom_thermalmeter
= (tempval
& 0x1f);
1533 if (rtlefuse
->eeprom_thermalmeter
== 0x1f || autoload_fail
)
1534 rtlefuse
->apk_thermalmeterignore
= true;
1536 rtlefuse
->thermalmeter
[0] = rtlefuse
->eeprom_thermalmeter
;
1537 RTPRINT(rtlpriv
, FINIT
, INIT_TxPower
,
1538 "thermalmeter = 0x%x\n", rtlefuse
->eeprom_thermalmeter
);
1541 static void _rtl92ce_read_adapter_info(struct ieee80211_hw
*hw
)
1543 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1544 struct rtl_efuse
*rtlefuse
= rtl_efuse(rtl_priv(hw
));
1545 struct rtl_hal
*rtlhal
= rtl_hal(rtl_priv(hw
));
1547 u8 hwinfo
[HWSET_MAX_SIZE
];
1550 if (rtlefuse
->epromtype
== EEPROM_BOOT_EFUSE
) {
1551 rtl_efuse_shadow_map_update(hw
);
1553 memcpy((void *)hwinfo
,
1554 (void *)&rtlefuse
->efuse_map
[EFUSE_INIT_MAP
][0],
1556 } else if (rtlefuse
->epromtype
== EEPROM_93C46
) {
1557 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
,
1558 "RTL819X Not boot from eeprom, check it !!");
1561 RT_PRINT_DATA(rtlpriv
, COMP_INIT
, DBG_DMESG
, "MAP",
1562 hwinfo
, HWSET_MAX_SIZE
);
1564 eeprom_id
= *((u16
*)&hwinfo
[0]);
1565 if (eeprom_id
!= RTL8190_EEPROM_ID
) {
1566 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_WARNING
,
1567 "EEPROM ID(%#x) is invalid!!\n", eeprom_id
);
1568 rtlefuse
->autoload_failflag
= true;
1570 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_LOUD
, "Autoload OK\n");
1571 rtlefuse
->autoload_failflag
= false;
1574 if (rtlefuse
->autoload_failflag
)
1577 for (i
= 0; i
< 6; i
+= 2) {
1578 usvalue
= *(u16
*)&hwinfo
[EEPROM_MAC_ADDR
+ i
];
1579 *((u16
*) (&rtlefuse
->dev_addr
[i
])) = usvalue
;
1582 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_DMESG
, "%pM\n", rtlefuse
->dev_addr
);
1584 _rtl92ce_read_txpower_info_from_hwpg(hw
,
1585 rtlefuse
->autoload_failflag
,
1588 rtl8192ce_read_bt_coexist_info_from_hwpg(hw
,
1589 rtlefuse
->autoload_failflag
,
1592 rtlefuse
->eeprom_channelplan
= *(u8
*)&hwinfo
[EEPROM_CHANNELPLAN
];
1593 rtlefuse
->eeprom_version
= *(u16
*)&hwinfo
[EEPROM_VERSION
];
1594 rtlefuse
->txpwr_fromeprom
= true;
1595 rtlefuse
->eeprom_oemid
= *(u8
*)&hwinfo
[EEPROM_CUSTOMER_ID
];
1597 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_LOUD
,
1598 "EEPROM Customer ID: 0x%2x\n", rtlefuse
->eeprom_oemid
);
1600 /* set channel paln to world wide 13 */
1601 rtlefuse
->channel_plan
= COUNTRY_CODE_WORLD_WIDE_13
;
1603 if (rtlhal
->oem_id
== RT_CID_DEFAULT
) {
1604 switch (rtlefuse
->eeprom_oemid
) {
1605 case EEPROM_CID_DEFAULT
:
1606 if (rtlefuse
->eeprom_did
== 0x8176) {
1607 if ((rtlefuse
->eeprom_svid
== 0x103C &&
1608 rtlefuse
->eeprom_smid
== 0x1629))
1609 rtlhal
->oem_id
= RT_CID_819x_HP
;
1611 rtlhal
->oem_id
= RT_CID_DEFAULT
;
1613 rtlhal
->oem_id
= RT_CID_DEFAULT
;
1616 case EEPROM_CID_TOSHIBA
:
1617 rtlhal
->oem_id
= RT_CID_TOSHIBA
;
1619 case EEPROM_CID_QMI
:
1620 rtlhal
->oem_id
= RT_CID_819x_QMI
;
1622 case EEPROM_CID_WHQL
:
1624 rtlhal
->oem_id
= RT_CID_DEFAULT
;
1632 static void _rtl92ce_hal_customized_behavior(struct ieee80211_hw
*hw
)
1634 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1635 struct rtl_pci_priv
*pcipriv
= rtl_pcipriv(hw
);
1636 struct rtl_hal
*rtlhal
= rtl_hal(rtl_priv(hw
));
1638 switch (rtlhal
->oem_id
) {
1639 case RT_CID_819x_HP
:
1640 pcipriv
->ledctl
.led_opendrain
= true;
1642 case RT_CID_819x_Lenovo
:
1643 case RT_CID_DEFAULT
:
1644 case RT_CID_TOSHIBA
:
1646 case RT_CID_819x_Acer
:
1651 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_DMESG
,
1652 "RT Customized ID: 0x%02X\n", rtlhal
->oem_id
);
1655 void rtl92ce_read_eeprom_info(struct ieee80211_hw
*hw
)
1657 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1658 struct rtl_efuse
*rtlefuse
= rtl_efuse(rtl_priv(hw
));
1659 struct rtl_phy
*rtlphy
= &(rtlpriv
->phy
);
1660 struct rtl_hal
*rtlhal
= rtl_hal(rtl_priv(hw
));
1663 rtlhal
->version
= _rtl92ce_read_chip_version(hw
);
1664 if (get_rf_type(rtlphy
) == RF_1T1R
)
1665 rtlpriv
->dm
.rfpath_rxenable
[0] = true;
1667 rtlpriv
->dm
.rfpath_rxenable
[0] =
1668 rtlpriv
->dm
.rfpath_rxenable
[1] = true;
1669 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_LOUD
, "VersionID = 0x%4x\n",
1671 tmp_u1b
= rtl_read_byte(rtlpriv
, REG_9346CR
);
1672 if (tmp_u1b
& BIT(4)) {
1673 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_DMESG
, "Boot from EEPROM\n");
1674 rtlefuse
->epromtype
= EEPROM_93C46
;
1676 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_DMESG
, "Boot from EFUSE\n");
1677 rtlefuse
->epromtype
= EEPROM_BOOT_EFUSE
;
1679 if (tmp_u1b
& BIT(5)) {
1680 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_LOUD
, "Autoload OK\n");
1681 rtlefuse
->autoload_failflag
= false;
1682 _rtl92ce_read_adapter_info(hw
);
1684 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
, "Autoload ERR!!\n");
1686 _rtl92ce_hal_customized_behavior(hw
);
1689 static void rtl92ce_update_hal_rate_table(struct ieee80211_hw
*hw
,
1690 struct ieee80211_sta
*sta
)
1692 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1693 struct rtl_pci_priv
*rtlpcipriv
= rtl_pcipriv(hw
);
1694 struct rtl_phy
*rtlphy
= &(rtlpriv
->phy
);
1695 struct rtl_mac
*mac
= rtl_mac(rtl_priv(hw
));
1696 struct rtl_hal
*rtlhal
= rtl_hal(rtl_priv(hw
));
1699 u8 nmode
= mac
->ht_enable
;
1700 u8 mimo_ps
= IEEE80211_SMPS_OFF
;
1703 u8 curtxbw_40mhz
= mac
->bw_40
;
1704 u8 curshortgi_40mhz
= (sta
->ht_cap
.cap
& IEEE80211_HT_CAP_SGI_40
) ?
1706 u8 curshortgi_20mhz
= (sta
->ht_cap
.cap
& IEEE80211_HT_CAP_SGI_20
) ?
1708 enum wireless_mode wirelessmode
= mac
->mode
;
1710 if (rtlhal
->current_bandtype
== BAND_ON_5G
)
1711 ratr_value
= sta
->supp_rates
[1] << 4;
1713 ratr_value
= sta
->supp_rates
[0];
1714 ratr_value
|= (sta
->ht_cap
.mcs
.rx_mask
[1] << 20 |
1715 sta
->ht_cap
.mcs
.rx_mask
[0] << 12);
1716 switch (wirelessmode
) {
1717 case WIRELESS_MODE_B
:
1718 if (ratr_value
& 0x0000000c)
1719 ratr_value
&= 0x0000000d;
1721 ratr_value
&= 0x0000000f;
1723 case WIRELESS_MODE_G
:
1724 ratr_value
&= 0x00000FF5;
1726 case WIRELESS_MODE_N_24G
:
1727 case WIRELESS_MODE_N_5G
:
1729 if (mimo_ps
== IEEE80211_SMPS_STATIC
) {
1730 ratr_value
&= 0x0007F005;
1734 if (get_rf_type(rtlphy
) == RF_1T2R
||
1735 get_rf_type(rtlphy
) == RF_1T1R
)
1736 ratr_mask
= 0x000ff005;
1738 ratr_mask
= 0x0f0ff005;
1740 ratr_value
&= ratr_mask
;
1744 if (rtlphy
->rf_type
== RF_1T2R
)
1745 ratr_value
&= 0x000ff0ff;
1747 ratr_value
&= 0x0f0ff0ff;
1752 if ((rtlpcipriv
->bt_coexist
.bt_coexistence
) &&
1753 (rtlpcipriv
->bt_coexist
.bt_coexist_type
== BT_CSR_BC4
) &&
1754 (rtlpcipriv
->bt_coexist
.bt_cur_state
) &&
1755 (rtlpcipriv
->bt_coexist
.bt_ant_isolation
) &&
1756 ((rtlpcipriv
->bt_coexist
.bt_service
== BT_SCO
) ||
1757 (rtlpcipriv
->bt_coexist
.bt_service
== BT_BUSY
)))
1758 ratr_value
&= 0x0fffcfc0;
1760 ratr_value
&= 0x0FFFFFFF;
1762 if (nmode
&& ((curtxbw_40mhz
&&
1763 curshortgi_40mhz
) || (!curtxbw_40mhz
&&
1764 curshortgi_20mhz
))) {
1766 ratr_value
|= 0x10000000;
1767 tmp_ratr_value
= (ratr_value
>> 12);
1769 for (shortgi_rate
= 15; shortgi_rate
> 0; shortgi_rate
--) {
1770 if ((1 << shortgi_rate
) & tmp_ratr_value
)
1774 shortgi_rate
= (shortgi_rate
<< 12) | (shortgi_rate
<< 8) |
1775 (shortgi_rate
<< 4) | (shortgi_rate
);
1778 rtl_write_dword(rtlpriv
, REG_ARFR0
+ ratr_index
* 4, ratr_value
);
1780 RT_TRACE(rtlpriv
, COMP_RATR
, DBG_DMESG
, "%x\n",
1781 rtl_read_dword(rtlpriv
, REG_ARFR0
));
1784 static void rtl92ce_update_hal_rate_mask(struct ieee80211_hw
*hw
,
1785 struct ieee80211_sta
*sta
, u8 rssi_level
)
1787 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1788 struct rtl_phy
*rtlphy
= &(rtlpriv
->phy
);
1789 struct rtl_mac
*mac
= rtl_mac(rtl_priv(hw
));
1790 struct rtl_hal
*rtlhal
= rtl_hal(rtl_priv(hw
));
1791 struct rtl_sta_info
*sta_entry
= NULL
;
1794 u8 curtxbw_40mhz
= (sta
->ht_cap
.cap
& IEEE80211_HT_CAP_SUP_WIDTH_20_40
)
1796 u8 curshortgi_40mhz
= (sta
->ht_cap
.cap
& IEEE80211_HT_CAP_SGI_40
) ?
1798 u8 curshortgi_20mhz
= (sta
->ht_cap
.cap
& IEEE80211_HT_CAP_SGI_20
) ?
1800 enum wireless_mode wirelessmode
= 0;
1801 bool shortgi
= false;
1804 u8 mimo_ps
= IEEE80211_SMPS_OFF
;
1806 sta_entry
= (struct rtl_sta_info
*) sta
->drv_priv
;
1807 wirelessmode
= sta_entry
->wireless_mode
;
1808 if (mac
->opmode
== NL80211_IFTYPE_STATION
)
1809 curtxbw_40mhz
= mac
->bw_40
;
1810 else if (mac
->opmode
== NL80211_IFTYPE_AP
||
1811 mac
->opmode
== NL80211_IFTYPE_ADHOC
)
1812 macid
= sta
->aid
+ 1;
1814 if (rtlhal
->current_bandtype
== BAND_ON_5G
)
1815 ratr_bitmap
= sta
->supp_rates
[1] << 4;
1817 ratr_bitmap
= sta
->supp_rates
[0];
1818 ratr_bitmap
|= (sta
->ht_cap
.mcs
.rx_mask
[1] << 20 |
1819 sta
->ht_cap
.mcs
.rx_mask
[0] << 12);
1820 switch (wirelessmode
) {
1821 case WIRELESS_MODE_B
:
1822 ratr_index
= RATR_INX_WIRELESS_B
;
1823 if (ratr_bitmap
& 0x0000000c)
1824 ratr_bitmap
&= 0x0000000d;
1826 ratr_bitmap
&= 0x0000000f;
1828 case WIRELESS_MODE_G
:
1829 ratr_index
= RATR_INX_WIRELESS_GB
;
1831 if (rssi_level
== 1)
1832 ratr_bitmap
&= 0x00000f00;
1833 else if (rssi_level
== 2)
1834 ratr_bitmap
&= 0x00000ff0;
1836 ratr_bitmap
&= 0x00000ff5;
1838 case WIRELESS_MODE_A
:
1839 ratr_index
= RATR_INX_WIRELESS_A
;
1840 ratr_bitmap
&= 0x00000ff0;
1842 case WIRELESS_MODE_N_24G
:
1843 case WIRELESS_MODE_N_5G
:
1844 ratr_index
= RATR_INX_WIRELESS_NGB
;
1846 if (mimo_ps
== IEEE80211_SMPS_STATIC
) {
1847 if (rssi_level
== 1)
1848 ratr_bitmap
&= 0x00070000;
1849 else if (rssi_level
== 2)
1850 ratr_bitmap
&= 0x0007f000;
1852 ratr_bitmap
&= 0x0007f005;
1854 if (rtlphy
->rf_type
== RF_1T2R
||
1855 rtlphy
->rf_type
== RF_1T1R
) {
1856 if (curtxbw_40mhz
) {
1857 if (rssi_level
== 1)
1858 ratr_bitmap
&= 0x000f0000;
1859 else if (rssi_level
== 2)
1860 ratr_bitmap
&= 0x000ff000;
1862 ratr_bitmap
&= 0x000ff015;
1864 if (rssi_level
== 1)
1865 ratr_bitmap
&= 0x000f0000;
1866 else if (rssi_level
== 2)
1867 ratr_bitmap
&= 0x000ff000;
1869 ratr_bitmap
&= 0x000ff005;
1872 if (curtxbw_40mhz
) {
1873 if (rssi_level
== 1)
1874 ratr_bitmap
&= 0x0f0f0000;
1875 else if (rssi_level
== 2)
1876 ratr_bitmap
&= 0x0f0ff000;
1878 ratr_bitmap
&= 0x0f0ff015;
1880 if (rssi_level
== 1)
1881 ratr_bitmap
&= 0x0f0f0000;
1882 else if (rssi_level
== 2)
1883 ratr_bitmap
&= 0x0f0ff000;
1885 ratr_bitmap
&= 0x0f0ff005;
1890 if ((curtxbw_40mhz
&& curshortgi_40mhz
) ||
1891 (!curtxbw_40mhz
&& curshortgi_20mhz
)) {
1895 else if (macid
== 1)
1900 ratr_index
= RATR_INX_WIRELESS_NGB
;
1902 if (rtlphy
->rf_type
== RF_1T2R
)
1903 ratr_bitmap
&= 0x000ff0ff;
1905 ratr_bitmap
&= 0x0f0ff0ff;
1908 RT_TRACE(rtlpriv
, COMP_RATR
, DBG_DMESG
,
1909 "ratr_bitmap :%x\n", ratr_bitmap
);
1910 *(u32
*)&rate_mask
= EF4BYTE((ratr_bitmap
& 0x0fffffff) |
1911 (ratr_index
<< 28));
1912 rate_mask
[4] = macid
| (shortgi
? 0x20 : 0x00) | 0x80;
1913 RT_TRACE(rtlpriv
, COMP_RATR
, DBG_DMESG
,
1914 "Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x\n",
1915 ratr_index
, ratr_bitmap
,
1916 rate_mask
[0], rate_mask
[1], rate_mask
[2], rate_mask
[3],
1918 rtl92c_fill_h2c_cmd(hw
, H2C_RA_MASK
, 5, rate_mask
);
1921 sta_entry
->ratr_index
= ratr_index
;
1924 void rtl92ce_update_hal_rate_tbl(struct ieee80211_hw
*hw
,
1925 struct ieee80211_sta
*sta
, u8 rssi_level
)
1927 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1929 if (rtlpriv
->dm
.useramask
)
1930 rtl92ce_update_hal_rate_mask(hw
, sta
, rssi_level
);
1932 rtl92ce_update_hal_rate_table(hw
, sta
);
1935 void rtl92ce_update_channel_access_setting(struct ieee80211_hw
*hw
)
1937 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1938 struct rtl_mac
*mac
= rtl_mac(rtl_priv(hw
));
1941 rtlpriv
->cfg
->ops
->set_hw_reg(hw
, HW_VAR_SLOT_TIME
,
1942 (u8
*)&mac
->slot_time
);
1943 if (!mac
->ht_enable
)
1944 sifs_timer
= 0x0a0a;
1946 sifs_timer
= 0x1010;
1947 rtlpriv
->cfg
->ops
->set_hw_reg(hw
, HW_VAR_SIFS
, (u8
*)&sifs_timer
);
1950 bool rtl92ce_gpio_radio_on_off_checking(struct ieee80211_hw
*hw
, u8
*valid
)
1952 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1953 struct rtl_ps_ctl
*ppsc
= rtl_psc(rtl_priv(hw
));
1954 struct rtl_pci
*rtlpci
= rtl_pcidev(rtl_pcipriv(hw
));
1955 enum rf_pwrstate e_rfpowerstate_toset
;
1957 bool actuallyset
= false;
1960 if (rtlpci
->being_init_adapter
)
1963 if (ppsc
->swrf_processing
)
1966 spin_lock_irqsave(&rtlpriv
->locks
.rf_ps_lock
, flag
);
1967 if (ppsc
->rfchange_inprogress
) {
1968 spin_unlock_irqrestore(&rtlpriv
->locks
.rf_ps_lock
, flag
);
1971 ppsc
->rfchange_inprogress
= true;
1972 spin_unlock_irqrestore(&rtlpriv
->locks
.rf_ps_lock
, flag
);
1975 rtl_write_byte(rtlpriv
, REG_MAC_PINMUX_CFG
, rtl_read_byte(rtlpriv
,
1976 REG_MAC_PINMUX_CFG
)&~(BIT(3)));
1978 u1tmp
= rtl_read_byte(rtlpriv
, REG_GPIO_IO_SEL
);
1979 e_rfpowerstate_toset
= (u1tmp
& BIT(3)) ? ERFON
: ERFOFF
;
1981 if ((ppsc
->hwradiooff
) && (e_rfpowerstate_toset
== ERFON
)) {
1982 RT_TRACE(rtlpriv
, COMP_RF
, DBG_DMESG
,
1983 "GPIOChangeRF - HW Radio ON, RF ON\n");
1985 e_rfpowerstate_toset
= ERFON
;
1986 ppsc
->hwradiooff
= false;
1988 } else if (!ppsc
->hwradiooff
&& (e_rfpowerstate_toset
== ERFOFF
)) {
1989 RT_TRACE(rtlpriv
, COMP_RF
, DBG_DMESG
,
1990 "GPIOChangeRF - HW Radio OFF, RF OFF\n");
1992 e_rfpowerstate_toset
= ERFOFF
;
1993 ppsc
->hwradiooff
= true;
1998 spin_lock_irqsave(&rtlpriv
->locks
.rf_ps_lock
, flag
);
1999 ppsc
->rfchange_inprogress
= false;
2000 spin_unlock_irqrestore(&rtlpriv
->locks
.rf_ps_lock
, flag
);
2002 if (ppsc
->reg_rfps_level
& RT_RF_OFF_LEVL_HALT_NIC
)
2003 RT_SET_PS_LEVEL(ppsc
, RT_RF_OFF_LEVL_HALT_NIC
);
2005 spin_lock_irqsave(&rtlpriv
->locks
.rf_ps_lock
, flag
);
2006 ppsc
->rfchange_inprogress
= false;
2007 spin_unlock_irqrestore(&rtlpriv
->locks
.rf_ps_lock
, flag
);
2011 return !ppsc
->hwradiooff
;
2015 void rtl92ce_set_key(struct ieee80211_hw
*hw
, u32 key_index
,
2016 u8
*p_macaddr
, bool is_group
, u8 enc_algo
,
2017 bool is_wepkey
, bool clear_all
)
2019 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
2020 struct rtl_mac
*mac
= rtl_mac(rtl_priv(hw
));
2021 struct rtl_efuse
*rtlefuse
= rtl_efuse(rtl_priv(hw
));
2022 u8
*macaddr
= p_macaddr
;
2024 bool is_pairwise
= false;
2026 static u8 cam_const_addr
[4][6] = {
2027 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2028 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2029 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2030 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2032 static u8 cam_const_broad
[] = {
2033 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2039 u8 clear_number
= 5;
2041 RT_TRACE(rtlpriv
, COMP_SEC
, DBG_DMESG
, "clear_all\n");
2043 for (idx
= 0; idx
< clear_number
; idx
++) {
2044 rtl_cam_mark_invalid(hw
, cam_offset
+ idx
);
2045 rtl_cam_empty_entry(hw
, cam_offset
+ idx
);
2048 memset(rtlpriv
->sec
.key_buf
[idx
], 0,
2050 rtlpriv
->sec
.key_len
[idx
] = 0;
2056 case WEP40_ENCRYPTION
:
2057 enc_algo
= CAM_WEP40
;
2059 case WEP104_ENCRYPTION
:
2060 enc_algo
= CAM_WEP104
;
2062 case TKIP_ENCRYPTION
:
2063 enc_algo
= CAM_TKIP
;
2065 case AESCCMP_ENCRYPTION
:
2069 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
,
2070 "switch case not processed\n");
2071 enc_algo
= CAM_TKIP
;
2075 if (is_wepkey
|| rtlpriv
->sec
.use_defaultkey
) {
2076 macaddr
= cam_const_addr
[key_index
];
2077 entry_id
= key_index
;
2080 macaddr
= cam_const_broad
;
2081 entry_id
= key_index
;
2083 if (mac
->opmode
== NL80211_IFTYPE_AP
) {
2084 entry_id
= rtl_cam_get_free_entry(hw
,
2086 if (entry_id
>= TOTAL_CAM_ENTRY
) {
2087 RT_TRACE(rtlpriv
, COMP_SEC
,
2089 "Can not find free hw security cam entry\n");
2093 entry_id
= CAM_PAIRWISE_KEY_POSITION
;
2096 key_index
= PAIRWISE_KEYIDX
;
2101 if (rtlpriv
->sec
.key_len
[key_index
] == 0) {
2102 RT_TRACE(rtlpriv
, COMP_SEC
, DBG_DMESG
,
2103 "delete one entry, entry_id is %d\n",
2105 if (mac
->opmode
== NL80211_IFTYPE_AP
)
2106 rtl_cam_del_entry(hw
, p_macaddr
);
2107 rtl_cam_delete_one_entry(hw
, p_macaddr
, entry_id
);
2109 RT_TRACE(rtlpriv
, COMP_SEC
, DBG_LOUD
,
2110 "The insert KEY length is %d\n",
2111 rtlpriv
->sec
.key_len
[PAIRWISE_KEYIDX
]);
2112 RT_TRACE(rtlpriv
, COMP_SEC
, DBG_LOUD
,
2113 "The insert KEY is %x %x\n",
2114 rtlpriv
->sec
.key_buf
[0][0],
2115 rtlpriv
->sec
.key_buf
[0][1]);
2117 RT_TRACE(rtlpriv
, COMP_SEC
, DBG_DMESG
,
2120 RT_PRINT_DATA(rtlpriv
, COMP_SEC
, DBG_LOUD
,
2121 "Pairwise Key content",
2122 rtlpriv
->sec
.pairwise_key
,
2124 key_len
[PAIRWISE_KEYIDX
]);
2126 RT_TRACE(rtlpriv
, COMP_SEC
, DBG_DMESG
,
2127 "set Pairwise key\n");
2129 rtl_cam_add_one_entry(hw
, macaddr
, key_index
,
2131 CAM_CONFIG_NO_USEDK
,
2133 key_buf
[key_index
]);
2135 RT_TRACE(rtlpriv
, COMP_SEC
, DBG_DMESG
,
2138 if (mac
->opmode
== NL80211_IFTYPE_ADHOC
) {
2139 rtl_cam_add_one_entry(hw
,
2142 CAM_PAIRWISE_KEY_POSITION
,
2144 CAM_CONFIG_NO_USEDK
,
2145 rtlpriv
->sec
.key_buf
2149 rtl_cam_add_one_entry(hw
, macaddr
, key_index
,
2151 CAM_CONFIG_NO_USEDK
,
2152 rtlpriv
->sec
.key_buf
[entry_id
]);
2159 static void rtl8192ce_bt_var_init(struct ieee80211_hw
*hw
)
2161 struct rtl_pci_priv
*rtlpcipriv
= rtl_pcipriv(hw
);
2163 rtlpcipriv
->bt_coexist
.bt_coexistence
=
2164 rtlpcipriv
->bt_coexist
.eeprom_bt_coexist
;
2165 rtlpcipriv
->bt_coexist
.bt_ant_num
=
2166 rtlpcipriv
->bt_coexist
.eeprom_bt_ant_num
;
2167 rtlpcipriv
->bt_coexist
.bt_coexist_type
=
2168 rtlpcipriv
->bt_coexist
.eeprom_bt_type
;
2170 if (rtlpcipriv
->bt_coexist
.reg_bt_iso
== 2)
2171 rtlpcipriv
->bt_coexist
.bt_ant_isolation
=
2172 rtlpcipriv
->bt_coexist
.eeprom_bt_ant_isolation
;
2174 rtlpcipriv
->bt_coexist
.bt_ant_isolation
=
2175 rtlpcipriv
->bt_coexist
.reg_bt_iso
;
2177 rtlpcipriv
->bt_coexist
.bt_radio_shared_type
=
2178 rtlpcipriv
->bt_coexist
.eeprom_bt_radio_shared
;
2180 if (rtlpcipriv
->bt_coexist
.bt_coexistence
) {
2182 if (rtlpcipriv
->bt_coexist
.reg_bt_sco
== 1)
2183 rtlpcipriv
->bt_coexist
.bt_service
= BT_OTHER_ACTION
;
2184 else if (rtlpcipriv
->bt_coexist
.reg_bt_sco
== 2)
2185 rtlpcipriv
->bt_coexist
.bt_service
= BT_SCO
;
2186 else if (rtlpcipriv
->bt_coexist
.reg_bt_sco
== 4)
2187 rtlpcipriv
->bt_coexist
.bt_service
= BT_BUSY
;
2188 else if (rtlpcipriv
->bt_coexist
.reg_bt_sco
== 5)
2189 rtlpcipriv
->bt_coexist
.bt_service
= BT_OTHERBUSY
;
2191 rtlpcipriv
->bt_coexist
.bt_service
= BT_IDLE
;
2193 rtlpcipriv
->bt_coexist
.bt_edca_ul
= 0;
2194 rtlpcipriv
->bt_coexist
.bt_edca_dl
= 0;
2195 rtlpcipriv
->bt_coexist
.bt_rssi_state
= 0xff;
2199 void rtl8192ce_read_bt_coexist_info_from_hwpg(struct ieee80211_hw
*hw
,
2200 bool auto_load_fail
, u8
*hwinfo
)
2202 struct rtl_pci_priv
*rtlpcipriv
= rtl_pcipriv(hw
);
2205 if (!auto_load_fail
) {
2206 rtlpcipriv
->bt_coexist
.eeprom_bt_coexist
=
2207 ((hwinfo
[RF_OPTION1
] & 0xe0) >> 5);
2208 value
= hwinfo
[RF_OPTION4
];
2209 rtlpcipriv
->bt_coexist
.eeprom_bt_type
= ((value
& 0xe) >> 1);
2210 rtlpcipriv
->bt_coexist
.eeprom_bt_ant_num
= (value
& 0x1);
2211 rtlpcipriv
->bt_coexist
.eeprom_bt_ant_isolation
=
2212 ((value
& 0x10) >> 4);
2213 rtlpcipriv
->bt_coexist
.eeprom_bt_radio_shared
=
2214 ((value
& 0x20) >> 5);
2216 rtlpcipriv
->bt_coexist
.eeprom_bt_coexist
= 0;
2217 rtlpcipriv
->bt_coexist
.eeprom_bt_type
= BT_2WIRE
;
2218 rtlpcipriv
->bt_coexist
.eeprom_bt_ant_num
= ANT_X2
;
2219 rtlpcipriv
->bt_coexist
.eeprom_bt_ant_isolation
= 0;
2220 rtlpcipriv
->bt_coexist
.eeprom_bt_radio_shared
= BT_RADIO_SHARED
;
2223 rtl8192ce_bt_var_init(hw
);
2226 void rtl8192ce_bt_reg_init(struct ieee80211_hw
*hw
)
2228 struct rtl_pci_priv
*rtlpcipriv
= rtl_pcipriv(hw
);
2230 /* 0:Low, 1:High, 2:From Efuse. */
2231 rtlpcipriv
->bt_coexist
.reg_bt_iso
= 2;
2232 /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
2233 rtlpcipriv
->bt_coexist
.reg_bt_sco
= 3;
2234 /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
2235 rtlpcipriv
->bt_coexist
.reg_bt_sco
= 0;
2239 void rtl8192ce_bt_hw_init(struct ieee80211_hw
*hw
)
2241 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
2242 struct rtl_phy
*rtlphy
= &(rtlpriv
->phy
);
2243 struct rtl_pci_priv
*rtlpcipriv
= rtl_pcipriv(hw
);
2247 if (rtlpcipriv
->bt_coexist
.bt_coexistence
&&
2248 ((rtlpcipriv
->bt_coexist
.bt_coexist_type
== BT_CSR_BC4
) ||
2249 rtlpcipriv
->bt_coexist
.bt_coexist_type
== BT_CSR_BC8
)) {
2251 if (rtlpcipriv
->bt_coexist
.bt_ant_isolation
)
2252 rtl_write_byte(rtlpriv
, REG_GPIO_MUXCFG
, 0xa0);
2254 u1_tmp
= rtl_read_byte(rtlpriv
, 0x4fd) &
2255 BIT_OFFSET_LEN_MASK_32(0, 1);
2257 ((rtlpcipriv
->bt_coexist
.bt_ant_isolation
== 1) ?
2258 0 : BIT_OFFSET_LEN_MASK_32(1, 1)) |
2259 ((rtlpcipriv
->bt_coexist
.bt_service
== BT_SCO
) ?
2260 0 : BIT_OFFSET_LEN_MASK_32(2, 1));
2261 rtl_write_byte(rtlpriv
, 0x4fd, u1_tmp
);
2263 rtl_write_dword(rtlpriv
, REG_BT_COEX_TABLE
+4, 0xaaaa9aaa);
2264 rtl_write_dword(rtlpriv
, REG_BT_COEX_TABLE
+8, 0xffbd0040);
2265 rtl_write_dword(rtlpriv
, REG_BT_COEX_TABLE
+0xc, 0x40000010);
2267 /* Config to 1T1R. */
2268 if (rtlphy
->rf_type
== RF_1T1R
) {
2269 u1_tmp
= rtl_read_byte(rtlpriv
, ROFDM0_TRXPATHENABLE
);
2270 u1_tmp
&= ~(BIT_OFFSET_LEN_MASK_32(1, 1));
2271 rtl_write_byte(rtlpriv
, ROFDM0_TRXPATHENABLE
, u1_tmp
);
2273 u1_tmp
= rtl_read_byte(rtlpriv
, ROFDM1_TRXPATHENABLE
);
2274 u1_tmp
&= ~(BIT_OFFSET_LEN_MASK_32(1, 1));
2275 rtl_write_byte(rtlpriv
, ROFDM1_TRXPATHENABLE
, u1_tmp
);
2280 void rtl92ce_suspend(struct ieee80211_hw
*hw
)
2284 void rtl92ce_resume(struct ieee80211_hw
*hw
)