drivers/net/wireless/rtlwifi/rtl8192ce/phy.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2010  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * wlanfae <wlanfae@realtek.com>
  23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24  * Hsinchu 300, Taiwan.
  25  *
  26  * Larry Finger <Larry.Finger@lwfinger.net>
  27  *
  28  *****************************************************************************/
  29
  30 #include "../wifi.h"
  31 #include "../pci.h"
  32 #include "../ps.h"
  33 #include "reg.h"
  34 #include "def.h"
  35 #include "hw.h"
  36 #include "phy.h"
  37 #include "rf.h"
  38 #include "dm.h"
  39 #include "table.h"
  40
  41 u32 rtl92ce_phy_query_rf_reg(struct ieee80211_hw *hw,
  42                             enum radio_path rfpath, u32 regaddr, u32 bitmask)
  43 {
  44         struct rtl_priv *rtlpriv = rtl_priv(hw);
  45         u32 original_value, readback_value, bitshift;
  46         struct rtl_phy *rtlphy = &(rtlpriv->phy);
  47         unsigned long flags;
  48
  49         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), "
  50                                                "rfpath(%#x), bitmask(%#x)\n",
  51                                                regaddr, rfpath, bitmask));
  52
  53         spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
  54
  55         if (rtlphy->rf_mode != RF_OP_BY_FW) {
  56                 original_value = _rtl92c_phy_rf_serial_read(hw,
  57                                                             rfpath, regaddr);
  58         } else {
  59                 original_value = _rtl92c_phy_fw_rf_serial_read(hw,
  60                                                                rfpath, regaddr);
  61         }
  62
  63         bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
  64         readback_value = (original_value & bitmask) >> bitshift;
  65
  66         spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
  67
  68         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
  69                  ("regaddr(%#x), rfpath(%#x), "
  70                   "bitmask(%#x), original_value(%#x)\n",
  71                   regaddr, rfpath, bitmask, original_value));
  72
  73         return readback_value;
  74 }
  75
  76 void rtl92ce_phy_set_rf_reg(struct ieee80211_hw *hw,
  77                            enum radio_path rfpath,
  78                            u32 regaddr, u32 bitmask, u32 data)
  79 {
  80         struct rtl_priv *rtlpriv = rtl_priv(hw);
  81         struct rtl_phy *rtlphy = &(rtlpriv->phy);
  82         u32 original_value, bitshift;
  83         unsigned long flags;
  84
  85         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
  86                  ("regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
  87                   regaddr, bitmask, data, rfpath));
  88
  89         spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
  90
  91         if (rtlphy->rf_mode != RF_OP_BY_FW) {
  92                 if (bitmask != RFREG_OFFSET_MASK) {
  93                         original_value = _rtl92c_phy_rf_serial_read(hw,
  94                                                                     rfpath,
  95                                                                     regaddr);
  96                         bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
  97                         data =
  98                             ((original_value & (~bitmask)) |
  99                              (data << bitshift));
 100                 }
 101
 102                 _rtl92c_phy_rf_serial_write(hw, rfpath, regaddr, data);
 103         } else {
 104                 if (bitmask != RFREG_OFFSET_MASK) {
 105                         original_value = _rtl92c_phy_fw_rf_serial_read(hw,
 106                                                                        rfpath,
 107                                                                        regaddr);
 108                         bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
 109                         data =
 110                             ((original_value & (~bitmask)) |
 111                              (data << bitshift));
 112                 }
 113                 _rtl92c_phy_fw_rf_serial_write(hw, rfpath, regaddr, data);
 114         }
 115
 116         spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
 117
 118         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), "
 119                                                "bitmask(%#x), data(%#x), "
 120                                                "rfpath(%#x)\n", regaddr,
 121                                                bitmask, data, rfpath));
 122 }
 123
 124 bool rtl92ce_phy_mac_config(struct ieee80211_hw *hw)
 125 {
 126         struct rtl_priv *rtlpriv = rtl_priv(hw);
 127         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 128         bool is92c = IS_92C_SERIAL(rtlhal->version);
 129         bool rtstatus = _rtl92ce_phy_config_mac_with_headerfile(hw);
 130
 131         if (is92c)
 132                 rtl_write_byte(rtlpriv, 0x14, 0x71);
 133         return rtstatus;
 134 }
 135
 136 bool rtl92ce_phy_bb_config(struct ieee80211_hw *hw)
 137 {
 138         bool rtstatus = true;
 139         struct rtl_priv *rtlpriv = rtl_priv(hw);
 140         u16 regval;
 141         u32 regvaldw;
 142         u8 reg_hwparafile = 1;
 143
 144         _rtl92c_phy_init_bb_rf_register_definition(hw);
 145         regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
 146         rtl_write_word(rtlpriv, REG_SYS_FUNC_EN,
 147                        regval | BIT(13) | BIT(0) | BIT(1));
 148         rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x83);
 149         rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL + 1, 0xdb);
 150         rtl_write_byte(rtlpriv, REG_RF_CTRL, RF_EN | RF_RSTB | RF_SDMRSTB);
 151         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN,
 152                        FEN_PPLL | FEN_PCIEA | FEN_DIO_PCIE |
 153                        FEN_BB_GLB_RSTn | FEN_BBRSTB);
 154         rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80);
 155         regvaldw = rtl_read_dword(rtlpriv, REG_LEDCFG0);
 156         rtl_write_dword(rtlpriv, REG_LEDCFG0, regvaldw | BIT(23));
 157         if (reg_hwparafile == 1)
 158                 rtstatus = _rtl92c_phy_bb8192c_config_parafile(hw);
 159         return rtstatus;
 160 }
 161
 162 bool _rtl92ce_phy_config_mac_with_headerfile(struct ieee80211_hw *hw)
 163 {
 164         struct rtl_priv *rtlpriv = rtl_priv(hw);
 165         u32 i;
 166         u32 arraylength;
 167         u32 *ptrarray;
 168
 169         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("Read Rtl819XMACPHY_Array\n"));
 170         arraylength = MAC_2T_ARRAYLENGTH;
 171         ptrarray = RTL8192CEMAC_2T_ARRAY;
 172         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 173                  ("Img:RTL8192CEMAC_2T_ARRAY\n"));
 174         for (i = 0; i < arraylength; i = i + 2)
 175                 rtl_write_byte(rtlpriv, ptrarray[i], (u8) ptrarray[i + 1]);
 176         return true;
 177 }
 178
 179 bool _rtl92ce_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
 180                                                   u8 configtype)
 181 {
 182         int i;
 183         u32 *phy_regarray_table;
 184         u32 *agctab_array_table;
 185         u16 phy_reg_arraylen, agctab_arraylen;
 186         struct rtl_priv *rtlpriv = rtl_priv(hw);
 187         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 188
 189         if (IS_92C_SERIAL(rtlhal->version)) {
 190                 agctab_arraylen = AGCTAB_2TARRAYLENGTH;
 191                 agctab_array_table = RTL8192CEAGCTAB_2TARRAY;
 192                 phy_reg_arraylen = PHY_REG_2TARRAY_LENGTH;
 193                 phy_regarray_table = RTL8192CEPHY_REG_2TARRAY;
 194         } else {
 195                 agctab_arraylen = AGCTAB_1TARRAYLENGTH;
 196                 agctab_array_table = RTL8192CEAGCTAB_1TARRAY;
 197                 phy_reg_arraylen = PHY_REG_1TARRAY_LENGTH;
 198                 phy_regarray_table = RTL8192CEPHY_REG_1TARRAY;
 199         }
 200         if (configtype == BASEBAND_CONFIG_PHY_REG) {
 201                 for (i = 0; i < phy_reg_arraylen; i = i + 2) {
 202                         if (phy_regarray_table[i] == 0xfe)
 203                                 mdelay(50);
 204                         else if (phy_regarray_table[i] == 0xfd)
 205                                 mdelay(5);
 206                         else if (phy_regarray_table[i] == 0xfc)
 207                                 mdelay(1);
 208                         else if (phy_regarray_table[i] == 0xfb)
 209                                 udelay(50);
 210                         else if (phy_regarray_table[i] == 0xfa)
 211                                 udelay(5);
 212                         else if (phy_regarray_table[i] == 0xf9)
 213                                 udelay(1);
 214                         rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD,
 215                                       phy_regarray_table[i + 1]);
 216                         udelay(1);
 217                         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 218                                  ("The phy_regarray_table[0] is %x"
 219                                   " Rtl819XPHY_REGArray[1] is %x\n",
 220                                   phy_regarray_table[i],
 221                                   phy_regarray_table[i + 1]));
 222                 }
 223         } else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
 224                 for (i = 0; i < agctab_arraylen; i = i + 2) {
 225                         rtl_set_bbreg(hw, agctab_array_table[i], MASKDWORD,
 226                                       agctab_array_table[i + 1]);
 227                         udelay(1);
 228                         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 229                                  ("The agctab_array_table[0] is "
 230                                   "%x Rtl819XPHY_REGArray[1] is %x\n",
 231                                   agctab_array_table[i],
 232                                   agctab_array_table[i + 1]));
 233                 }
 234         }
 235         return true;
 236 }
 237
 238 bool _rtl92ce_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
 239                                                     u8 configtype)
 240 {
 241         struct rtl_priv *rtlpriv = rtl_priv(hw);
 242         int i;
 243         u32 *phy_regarray_table_pg;
 244         u16 phy_regarray_pg_len;
 245
 246         phy_regarray_pg_len = PHY_REG_ARRAY_PGLENGTH;
 247         phy_regarray_table_pg = RTL8192CEPHY_REG_ARRAY_PG;
 248
 249         if (configtype == BASEBAND_CONFIG_PHY_REG) {
 250                 for (i = 0; i < phy_regarray_pg_len; i = i + 3) {
 251                         if (phy_regarray_table_pg[i] == 0xfe)
 252                                 mdelay(50);
 253                         else if (phy_regarray_table_pg[i] == 0xfd)
 254                                 mdelay(5);
 255                         else if (phy_regarray_table_pg[i] == 0xfc)
 256                                 mdelay(1);
 257                         else if (phy_regarray_table_pg[i] == 0xfb)
 258                                 udelay(50);
 259                         else if (phy_regarray_table_pg[i] == 0xfa)
 260                                 udelay(5);
 261                         else if (phy_regarray_table_pg[i] == 0xf9)
 262                                 udelay(1);
 263
 264                         _rtl92c_store_pwrIndex_diffrate_offset(hw,
 265                                                phy_regarray_table_pg[i],
 266                                                phy_regarray_table_pg[i + 1],
 267                                                phy_regarray_table_pg[i + 2]);
 268                 }
 269         } else {
 270
 271                 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
 272                          ("configtype != BaseBand_Config_PHY_REG\n"));
 273         }
 274         return true;
 275 }
 276
 277 bool rtl92ce_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
 278                                           enum radio_path rfpath)
 279 {
 280
 281         int i;
 282         bool rtstatus = true;
 283         u32 *radioa_array_table;
 284         u32 *radiob_array_table;
 285         u16 radioa_arraylen, radiob_arraylen;
 286         struct rtl_priv *rtlpriv = rtl_priv(hw);
 287         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 288
 289         if (IS_92C_SERIAL(rtlhal->version)) {
 290                 radioa_arraylen = RADIOA_2TARRAYLENGTH;
 291                 radioa_array_table = RTL8192CERADIOA_2TARRAY;
 292                 radiob_arraylen = RADIOB_2TARRAYLENGTH;
 293                 radiob_array_table = RTL8192CE_RADIOB_2TARRAY;
 294                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 295                          ("Radio_A:RTL8192CERADIOA_2TARRAY\n"));
 296                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 297                          ("Radio_B:RTL8192CE_RADIOB_2TARRAY\n"));
 298         } else {
 299                 radioa_arraylen = RADIOA_1TARRAYLENGTH;
 300                 radioa_array_table = RTL8192CE_RADIOA_1TARRAY;
 301                 radiob_arraylen = RADIOB_1TARRAYLENGTH;
 302                 radiob_array_table = RTL8192CE_RADIOB_1TARRAY;
 303                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 304                          ("Radio_A:RTL8192CE_RADIOA_1TARRAY\n"));
 305                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 306                          ("Radio_B:RTL8192CE_RADIOB_1TARRAY\n"));
 307         }
 308         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("Radio No %x\n", rfpath));
 309         rtstatus = true;
 310         switch (rfpath) {
 311         case RF90_PATH_A:
 312                 for (i = 0; i < radioa_arraylen; i = i + 2) {
 313                         if (radioa_array_table[i] == 0xfe)
 314                                 mdelay(50);
 315                         else if (radioa_array_table[i] == 0xfd)
 316                                 mdelay(5);
 317                         else if (radioa_array_table[i] == 0xfc)
 318                                 mdelay(1);
 319                         else if (radioa_array_table[i] == 0xfb)
 320                                 udelay(50);
 321                         else if (radioa_array_table[i] == 0xfa)
 322                                 udelay(5);
 323                         else if (radioa_array_table[i] == 0xf9)
 324                                 udelay(1);
 325                         else {
 326                                 rtl_set_rfreg(hw, rfpath, radioa_array_table[i],
 327                                               RFREG_OFFSET_MASK,
 328                                               radioa_array_table[i + 1]);
 329                                 udelay(1);
 330                         }
 331                 }
 332                 break;
 333         case RF90_PATH_B:
 334                 for (i = 0; i < radiob_arraylen; i = i + 2) {
 335                         if (radiob_array_table[i] == 0xfe) {
 336                                 mdelay(50);
 337                         } else if (radiob_array_table[i] == 0xfd)
 338                                 mdelay(5);
 339                         else if (radiob_array_table[i] == 0xfc)
 340                                 mdelay(1);
 341                         else if (radiob_array_table[i] == 0xfb)
 342                                 udelay(50);
 343                         else if (radiob_array_table[i] == 0xfa)
 344                                 udelay(5);
 345                         else if (radiob_array_table[i] == 0xf9)
 346                                 udelay(1);
 347                         else {
 348                                 rtl_set_rfreg(hw, rfpath, radiob_array_table[i],
 349                                               RFREG_OFFSET_MASK,
 350                                               radiob_array_table[i + 1]);
 351                                 udelay(1);
 352                         }
 353                 }
 354                 break;
 355         case RF90_PATH_C:
 356                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 357                          ("switch case not process\n"));
 358                 break;
 359         case RF90_PATH_D:
 360                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 361                          ("switch case not process\n"));
 362                 break;
 363         }
 364         return true;
 365 }
 366
 367 void rtl92ce_phy_set_bw_mode_callback(struct ieee80211_hw *hw)
 368 {
 369         struct rtl_priv *rtlpriv = rtl_priv(hw);
 370         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 371         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 372         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 373         u8 reg_bw_opmode;
 374         u8 reg_prsr_rsc;
 375
 376         RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
 377                  ("Switch to %s bandwidth\n",
 378                   rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
 379                   "20MHz" : "40MHz"))
 380
 381             if (is_hal_stop(rtlhal))
 382                 return;
 383
 384         reg_bw_opmode = rtl_read_byte(rtlpriv, REG_BWOPMODE);
 385         reg_prsr_rsc = rtl_read_byte(rtlpriv, REG_RRSR + 2);
 386
 387         switch (rtlphy->current_chan_bw) {
 388         case HT_CHANNEL_WIDTH_20:
 389                 reg_bw_opmode |= BW_OPMODE_20MHZ;
 390                 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
 391                 break;
 392
 393         case HT_CHANNEL_WIDTH_20_40:
 394                 reg_bw_opmode &= ~BW_OPMODE_20MHZ;
 395                 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
 396
 397                 reg_prsr_rsc =
 398                     (reg_prsr_rsc & 0x90) | (mac->cur_40_prime_sc << 5);
 399                 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_prsr_rsc);
 400                 break;
 401
 402         default:
 403                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 404                          ("unknown bandwidth: %#X\n", rtlphy->current_chan_bw));
 405                 break;
 406         }
 407
 408         switch (rtlphy->current_chan_bw) {
 409         case HT_CHANNEL_WIDTH_20:
 410                 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0);
 411                 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);
 412                 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);
 413                 break;
 414         case HT_CHANNEL_WIDTH_20_40:
 415                 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1);
 416                 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);
 417                 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND,
 418                               (mac->cur_40_prime_sc >> 1));
 419                 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc);
 420                 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 0);
 421                 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)),
 422                               (mac->cur_40_prime_sc ==
 423                                HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
 424                 break;
 425         default:
 426                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 427                          ("unknown bandwidth: %#X\n", rtlphy->current_chan_bw));
 428                 break;
 429         }
 430         rtl92c_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
 431         rtlphy->set_bwmode_inprogress = false;
 432         RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, ("<==\n"));
 433 }
 434
 435 void _rtl92ce_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t)
 436 {
 437         u8 tmpreg;
 438         u32 rf_a_mode = 0, rf_b_mode = 0, lc_cal;
 439         struct rtl_priv *rtlpriv = rtl_priv(hw);
 440
 441         tmpreg = rtl_read_byte(rtlpriv, 0xd03);
 442
 443         if ((tmpreg & 0x70) != 0)
 444                 rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F);
 445         else
 446                 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
 447
 448         if ((tmpreg & 0x70) != 0) {
 449                 rf_a_mode = rtl_get_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS);
 450
 451                 if (is2t)
 452                         rf_b_mode = rtl_get_rfreg(hw, RF90_PATH_B, 0x00,
 453                                                   MASK12BITS);
 454
 455                 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS,
 456                               (rf_a_mode & 0x8FFFF) | 0x10000);
 457
 458                 if (is2t)
 459                         rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
 460                                       (rf_b_mode & 0x8FFFF) | 0x10000);
 461         }
 462         lc_cal = rtl_get_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS);
 463
 464         rtl_set_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS, lc_cal | 0x08000);
 465
 466         mdelay(100);
 467
 468         if ((tmpreg & 0x70) != 0) {
 469                 rtl_write_byte(rtlpriv, 0xd03, tmpreg);
 470                 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, rf_a_mode);
 471
 472                 if (is2t)
 473                         rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
 474                                       rf_b_mode);
 475         } else {
 476                 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
 477         }
 478 }
 479
 480 static bool _rtl92ce_phy_set_rf_power_state(struct ieee80211_hw *hw,
 481                                             enum rf_pwrstate rfpwr_state)
 482 {
 483         struct rtl_priv *rtlpriv = rtl_priv(hw);
 484         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
 485         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 486         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 487         bool bresult = true;
 488         u8 i, queue_id;
 489         struct rtl8192_tx_ring *ring = NULL;
 490
 491         ppsc->set_rfpowerstate_inprogress = true;
 492         switch (rfpwr_state) {
 493         case ERFON:{
 494                         if ((ppsc->rfpwr_state == ERFOFF) &&
 495                             RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
 496                                 bool rtstatus;
 497                                 u32 InitializeCount = 0;
 498                                 do {
 499                                         InitializeCount++;
 500                                         RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
 501                                                  ("IPS Set eRf nic enable\n"));
 502                                         rtstatus = rtl_ps_enable_nic(hw);
 503                                 } while ((rtstatus != true)
 504                                          && (InitializeCount < 10));
 505                                 RT_CLEAR_PS_LEVEL(ppsc,
 506                                                   RT_RF_OFF_LEVL_HALT_NIC);
 507                         } else {
 508                                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
 509                                          ("Set ERFON sleeped:%d ms\n",
 510                                           jiffies_to_msecs(jiffies -
 511                                                    ppsc->
 512                                                    last_sleep_jiffies)));
 513                                 ppsc->last_awake_jiffies = jiffies;
 514                                 rtl92ce_phy_set_rf_on(hw);
 515                         }
 516                         if (mac->link_state == MAC80211_LINKED) {
 517                                 rtlpriv->cfg->ops->led_control(hw,
 518                                                                LED_CTL_LINK);
 519                         } else {
 520                                 rtlpriv->cfg->ops->led_control(hw,
 521                                                                LED_CTL_NO_LINK);
 522                         }
 523                         break;
 524                 }
 525         case ERFOFF:{
 526                         for (queue_id = 0, i = 0;
 527                              queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
 528                                 ring = &pcipriv->dev.tx_ring[queue_id];
 529                                 if (skb_queue_len(&ring->queue) == 0 ||
 530                                     queue_id == BEACON_QUEUE) {
 531                                         queue_id++;
 532                                         continue;
 533                                 } else {
 534                                         RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 535                                                  ("eRf Off/Sleep: %d times "
 536                                                   "TcbBusyQueue[%d] "
 537                                                   "=%d before doze!\n", (i + 1),
 538                                                   queue_id,
 539                                                   skb_queue_len(&ring->queue)));
 540                                         udelay(10);
 541                                         i++;
 542                                 }
 543                                 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
 544                                         RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 545                                                  ("\nERFOFF: %d times "
 546                                                   "TcbBusyQueue[%d] = %d !\n",
 547                                                   MAX_DOZE_WAITING_TIMES_9x,
 548                                                   queue_id,
 549                                                   skb_queue_len(&ring->queue)));
 550                                         break;
 551                                 }
 552                         }
 553                         if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
 554                                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
 555                                          ("IPS Set eRf nic disable\n"));
 556                                 rtl_ps_disable_nic(hw);
 557                                 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
 558                         } else {
 559                                 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) {
 560                                         rtlpriv->cfg->ops->led_control(hw,
 561                                                                LED_CTL_NO_LINK);
 562                                 } else {
 563                                         rtlpriv->cfg->ops->led_control(hw,
 564                                                              LED_CTL_POWER_OFF);
 565                                 }
 566                         }
 567                         break;
 568                 }
 569         case ERFSLEEP:{
 570                         if (ppsc->rfpwr_state == ERFOFF)
 571                                 break;
 572                         for (queue_id = 0, i = 0;
 573                              queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
 574                                 ring = &pcipriv->dev.tx_ring[queue_id];
 575                                 if (skb_queue_len(&ring->queue) == 0) {
 576                                         queue_id++;
 577                                         continue;
 578                                 } else {
 579                                         RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 580                                                  ("eRf Off/Sleep: %d times "
 581                                                   "TcbBusyQueue[%d] =%d before "
 582                                                   "doze!\n", (i + 1), queue_id,
 583                                                   skb_queue_len(&ring->queue)));
 584                                         udelay(10);
 585                                         i++;
 586                                 }
 587                                 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
 588                                         RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 589                                                  ("\n ERFSLEEP: %d times "
 590                                                   "TcbBusyQueue[%d] = %d !\n",
 591                                                   MAX_DOZE_WAITING_TIMES_9x,
 592                                                   queue_id,
 593                                                   skb_queue_len(&ring->queue)));
 594                                         break;
 595                                 }
 596                         }
 597                         RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
 598                                  ("Set ERFSLEEP awaked:%d ms\n",
 599                                   jiffies_to_msecs(jiffies -
 600                                                    ppsc->last_awake_jiffies)));
 601                         ppsc->last_sleep_jiffies = jiffies;
 602                         _rtl92c_phy_set_rf_sleep(hw);
 603                         break;
 604                 }
 605         default:
 606                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 607                          ("switch case not process\n"));
 608                 bresult = false;
 609                 break;
 610         }
 611         if (bresult)
 612                 ppsc->rfpwr_state = rfpwr_state;
 613         ppsc->set_rfpowerstate_inprogress = false;
 614         return bresult;
 615 }
 616
 617 bool rtl92ce_phy_set_rf_power_state(struct ieee80211_hw *hw,
 618                                    enum rf_pwrstate rfpwr_state)
 619 {
 620         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 621         bool bresult = false;
 622
 623         if (rfpwr_state == ppsc->rfpwr_state)
 624                 return bresult;
 625         bresult = _rtl92ce_phy_set_rf_power_state(hw, rfpwr_state);
 626         return bresult;
 627 }