2119313a737bab21e9c304627b2acb56d2a3ab43
1 /******************************************************************************
3 * Copyright(c) 2009-2012 Realtek Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
26 * Larry Finger <Larry.Finger@lwfinger.net>
28 *****************************************************************************/
37 static bool _rtl92c_phy_rf6052_config_parafile(struct ieee80211_hw
*hw
);
39 void rtl92cu_phy_rf6052_set_bandwidth(struct ieee80211_hw
*hw
, u8 bandwidth
)
41 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
42 struct rtl_phy
*rtlphy
= &(rtlpriv
->phy
);
45 case HT_CHANNEL_WIDTH_20
:
46 rtlphy
->rfreg_chnlval
[0] = ((rtlphy
->rfreg_chnlval
[0] &
47 0xfffff3ff) | 0x0400);
48 rtl_set_rfreg(hw
, RF90_PATH_A
, RF_CHNLBW
, RFREG_OFFSET_MASK
,
49 rtlphy
->rfreg_chnlval
[0]);
51 case HT_CHANNEL_WIDTH_20_40
:
52 rtlphy
->rfreg_chnlval
[0] = ((rtlphy
->rfreg_chnlval
[0] &
54 rtl_set_rfreg(hw
, RF90_PATH_A
, RF_CHNLBW
, RFREG_OFFSET_MASK
,
55 rtlphy
->rfreg_chnlval
[0]);
58 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
,
59 "unknown bandwidth: %#X\n", bandwidth
);
64 void rtl92cu_phy_rf6052_set_cck_txpower(struct ieee80211_hw
*hw
,
67 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
68 struct rtl_phy
*rtlphy
= &(rtlpriv
->phy
);
69 struct rtl_hal
*rtlhal
= rtl_hal(rtlpriv
);
70 struct rtl_mac
*mac
= rtl_mac(rtl_priv(hw
));
71 struct rtl_efuse
*rtlefuse
= rtl_efuse(rtl_priv(hw
));
72 u32 tx_agc
[2] = { 0, 0 }, tmpval
= 0;
73 bool turbo_scanoff
= false;
77 if (rtlhal
->interface
== INTF_PCI
) {
78 if (rtlefuse
->eeprom_regulatory
!= 0)
81 if ((rtlefuse
->eeprom_regulatory
!= 0) ||
82 (rtlefuse
->external_pa
))
85 if (mac
->act_scanning
) {
86 tx_agc
[RF90_PATH_A
] = 0x3f3f3f3f;
87 tx_agc
[RF90_PATH_B
] = 0x3f3f3f3f;
89 for (idx1
= RF90_PATH_A
; idx1
<= RF90_PATH_B
; idx1
++) {
90 tx_agc
[idx1
] = ppowerlevel
[idx1
] |
91 (ppowerlevel
[idx1
] << 8) |
92 (ppowerlevel
[idx1
] << 16) |
93 (ppowerlevel
[idx1
] << 24);
94 if (rtlhal
->interface
== INTF_USB
) {
95 if (tx_agc
[idx1
] > 0x20 &&
96 rtlefuse
->external_pa
)
102 if (rtlpriv
->dm
.dynamic_txhighpower_lvl
==
103 TXHIGHPWRLEVEL_LEVEL1
) {
104 tx_agc
[RF90_PATH_A
] = 0x10101010;
105 tx_agc
[RF90_PATH_B
] = 0x10101010;
106 } else if (rtlpriv
->dm
.dynamic_txhighpower_lvl
==
107 TXHIGHPWRLEVEL_LEVEL2
) {
108 tx_agc
[RF90_PATH_A
] = 0x00000000;
109 tx_agc
[RF90_PATH_B
] = 0x00000000;
111 for (idx1
= RF90_PATH_A
; idx1
<= RF90_PATH_B
; idx1
++) {
112 tx_agc
[idx1
] = ppowerlevel
[idx1
] |
113 (ppowerlevel
[idx1
] << 8) |
114 (ppowerlevel
[idx1
] << 16) |
115 (ppowerlevel
[idx1
] << 24);
117 if (rtlefuse
->eeprom_regulatory
== 0) {
118 tmpval
= (rtlphy
->mcs_offset
[0][6]) +
119 (rtlphy
->mcs_offset
[0][7] << 8);
120 tx_agc
[RF90_PATH_A
] += tmpval
;
121 tmpval
= (rtlphy
->mcs_offset
[0][14]) +
122 (rtlphy
->mcs_offset
[0][15] << 24);
123 tx_agc
[RF90_PATH_B
] += tmpval
;
127 for (idx1
= RF90_PATH_A
; idx1
<= RF90_PATH_B
; idx1
++) {
128 ptr
= (u8
*) (&(tx_agc
[idx1
]));
129 for (idx2
= 0; idx2
< 4; idx2
++) {
130 if (*ptr
> RF6052_MAX_TX_PWR
)
131 *ptr
= RF6052_MAX_TX_PWR
;
135 tmpval
= tx_agc
[RF90_PATH_A
] & 0xff;
136 rtl_set_bbreg(hw
, RTXAGC_A_CCK1_MCS32
, MASKBYTE1
, tmpval
);
138 RTPRINT(rtlpriv
, FPHY
, PHY_TXPWR
,
139 "CCK PWR 1M (rf-A) = 0x%x (reg 0x%x)\n",
140 tmpval
, RTXAGC_A_CCK1_MCS32
);
142 tmpval
= tx_agc
[RF90_PATH_A
] >> 8;
143 if (mac
->mode
== WIRELESS_MODE_B
)
144 tmpval
= tmpval
& 0xff00ffff;
145 rtl_set_bbreg(hw
, RTXAGC_B_CCK11_A_CCK2_11
, 0xffffff00, tmpval
);
146 RTPRINT(rtlpriv
, FPHY
, PHY_TXPWR
,
147 "CCK PWR 2~11M (rf-A) = 0x%x (reg 0x%x)\n",
148 tmpval
, RTXAGC_B_CCK11_A_CCK2_11
);
149 tmpval
= tx_agc
[RF90_PATH_B
] >> 24;
150 rtl_set_bbreg(hw
, RTXAGC_B_CCK11_A_CCK2_11
, MASKBYTE0
, tmpval
);
151 RTPRINT(rtlpriv
, FPHY
, PHY_TXPWR
,
152 "CCK PWR 11M (rf-B) = 0x%x (reg 0x%x)\n",
153 tmpval
, RTXAGC_B_CCK11_A_CCK2_11
);
154 tmpval
= tx_agc
[RF90_PATH_B
] & 0x00ffffff;
155 rtl_set_bbreg(hw
, RTXAGC_B_CCK1_55_MCS32
, 0xffffff00, tmpval
);
156 RTPRINT(rtlpriv
, FPHY
, PHY_TXPWR
,
157 "CCK PWR 1~5.5M (rf-B) = 0x%x (reg 0x%x)\n",
158 tmpval
, RTXAGC_B_CCK1_55_MCS32
);
161 static void rtl92c_phy_get_power_base(struct ieee80211_hw
*hw
,
162 u8
*ppowerlevel
, u8 channel
,
163 u32
*ofdmbase
, u32
*mcsbase
)
165 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
166 struct rtl_phy
*rtlphy
= &(rtlpriv
->phy
);
167 struct rtl_efuse
*rtlefuse
= rtl_efuse(rtl_priv(hw
));
168 u32 powerBase0
, powerBase1
;
169 u8 legacy_pwrdiff
= 0, ht20_pwrdiff
= 0;
172 for (i
= 0; i
< 2; i
++) {
173 powerlevel
[i
] = ppowerlevel
[i
];
174 legacy_pwrdiff
= rtlefuse
->txpwr_legacyhtdiff
[i
][channel
- 1];
175 powerBase0
= powerlevel
[i
] + legacy_pwrdiff
;
176 powerBase0
= (powerBase0
<< 24) | (powerBase0
<< 16) |
177 (powerBase0
<< 8) | powerBase0
;
178 *(ofdmbase
+ i
) = powerBase0
;
179 RTPRINT(rtlpriv
, FPHY
, PHY_TXPWR
,
180 " [OFDM power base index rf(%c) = 0x%x]\n",
181 i
== 0 ? 'A' : 'B', *(ofdmbase
+ i
));
183 for (i
= 0; i
< 2; i
++) {
184 if (rtlphy
->current_chan_bw
== HT_CHANNEL_WIDTH_20
) {
185 ht20_pwrdiff
= rtlefuse
->txpwr_ht20diff
[i
][channel
- 1];
186 powerlevel
[i
] += ht20_pwrdiff
;
188 powerBase1
= powerlevel
[i
];
189 powerBase1
= (powerBase1
<< 24) |
190 (powerBase1
<< 16) | (powerBase1
<< 8) | powerBase1
;
191 *(mcsbase
+ i
) = powerBase1
;
192 RTPRINT(rtlpriv
, FPHY
, PHY_TXPWR
,
193 " [MCS power base index rf(%c) = 0x%x]\n",
194 i
== 0 ? 'A' : 'B', *(mcsbase
+ i
));
198 static void _rtl92c_get_txpower_writeval_by_regulatory(struct ieee80211_hw
*hw
,
199 u8 channel
, u8 index
,
204 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
205 struct rtl_phy
*rtlphy
= &(rtlpriv
->phy
);
206 struct rtl_efuse
*rtlefuse
= rtl_efuse(rtl_priv(hw
));
207 u8 i
, chnlgroup
= 0, pwr_diff_limit
[4];
208 u32 writeVal
, customer_limit
, rf
;
210 for (rf
= 0; rf
< 2; rf
++) {
211 switch (rtlefuse
->eeprom_regulatory
) {
214 writeVal
= rtlphy
->mcs_offset
215 [chnlgroup
][index
+ (rf
? 8 : 0)]
216 + ((index
< 2) ? powerBase0
[rf
] : powerBase1
[rf
]);
217 RTPRINT(rtlpriv
, FPHY
, PHY_TXPWR
,
218 "RTK better performance,writeVal(%c) = 0x%x\n",
219 rf
== 0 ? 'A' : 'B', writeVal
);
222 if (rtlphy
->pwrgroup_cnt
== 1)
224 if (rtlphy
->pwrgroup_cnt
>= 3) {
227 else if (channel
>= 4 && channel
<= 9)
229 else if (channel
> 9)
231 if (rtlphy
->current_chan_bw
==
237 writeVal
= rtlphy
->mcs_offset
[chnlgroup
][index
+
239 ((index
< 2) ? powerBase0
[rf
] :
241 RTPRINT(rtlpriv
, FPHY
, PHY_TXPWR
,
242 "Realtek regulatory, 20MHz, writeVal(%c) = 0x%x\n",
243 rf
== 0 ? 'A' : 'B', writeVal
);
246 writeVal
= ((index
< 2) ? powerBase0
[rf
] :
248 RTPRINT(rtlpriv
, FPHY
, PHY_TXPWR
,
249 "Better regulatory,writeVal(%c) = 0x%x\n",
250 rf
== 0 ? 'A' : 'B', writeVal
);
254 if (rtlphy
->current_chan_bw
==
255 HT_CHANNEL_WIDTH_20_40
) {
256 RTPRINT(rtlpriv
, FPHY
, PHY_TXPWR
,
257 "customer's limit, 40MHzrf(%c) = 0x%x\n",
259 rtlefuse
->pwrgroup_ht40
[rf
]
262 RTPRINT(rtlpriv
, FPHY
, PHY_TXPWR
,
263 "customer's limit, 20MHz rf(%c) = 0x%x\n",
265 rtlefuse
->pwrgroup_ht20
[rf
]
268 for (i
= 0; i
< 4; i
++) {
269 pwr_diff_limit
[i
] = (u8
) ((rtlphy
->mcs_offset
270 [chnlgroup
][index
+ (rf
? 8 : 0)]
271 & (0x7f << (i
* 8))) >> (i
* 8));
272 if (rtlphy
->current_chan_bw
==
273 HT_CHANNEL_WIDTH_20_40
) {
274 if (pwr_diff_limit
[i
] >
275 rtlefuse
->pwrgroup_ht40
[rf
]
277 pwr_diff_limit
[i
] = rtlefuse
->
281 if (pwr_diff_limit
[i
] >
282 rtlefuse
->pwrgroup_ht20
[rf
]
285 rtlefuse
->pwrgroup_ht20
[rf
]
289 customer_limit
= (pwr_diff_limit
[3] << 24) |
290 (pwr_diff_limit
[2] << 16) |
291 (pwr_diff_limit
[1] << 8) | (pwr_diff_limit
[0]);
292 RTPRINT(rtlpriv
, FPHY
, PHY_TXPWR
,
293 "Customer's limit rf(%c) = 0x%x\n",
294 rf
== 0 ? 'A' : 'B', customer_limit
);
295 writeVal
= customer_limit
+ ((index
< 2) ?
296 powerBase0
[rf
] : powerBase1
[rf
]);
297 RTPRINT(rtlpriv
, FPHY
, PHY_TXPWR
,
298 "Customer, writeVal rf(%c)= 0x%x\n",
299 rf
== 0 ? 'A' : 'B', writeVal
);
303 writeVal
= rtlphy
->mcs_offset
[chnlgroup
]
304 [index
+ (rf
? 8 : 0)] + ((index
< 2) ?
305 powerBase0
[rf
] : powerBase1
[rf
]);
306 RTPRINT(rtlpriv
, FPHY
, PHY_TXPWR
,
307 "RTK better performance, writeValrf(%c) = 0x%x\n",
308 rf
== 0 ? 'A' : 'B', writeVal
);
311 if (rtlpriv
->dm
.dynamic_txhighpower_lvl
==
312 TXHIGHPWRLEVEL_LEVEL1
)
313 writeVal
= 0x14141414;
314 else if (rtlpriv
->dm
.dynamic_txhighpower_lvl
==
315 TXHIGHPWRLEVEL_LEVEL2
)
316 writeVal
= 0x00000000;
317 if (rtlpriv
->dm
.dynamic_txhighpower_lvl
== TXHIGHPWRLEVEL_BT1
)
318 writeVal
= writeVal
- 0x06060606;
319 else if (rtlpriv
->dm
.dynamic_txhighpower_lvl
==
322 *(p_outwriteval
+ rf
) = writeVal
;
326 static void _rtl92c_write_ofdm_power_reg(struct ieee80211_hw
*hw
,
327 u8 index
, u32
*pValue
)
329 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
330 struct rtl_phy
*rtlphy
= &(rtlpriv
->phy
);
331 u16 regoffset_a
[6] = {
332 RTXAGC_A_RATE18_06
, RTXAGC_A_RATE54_24
,
333 RTXAGC_A_MCS03_MCS00
, RTXAGC_A_MCS07_MCS04
,
334 RTXAGC_A_MCS11_MCS08
, RTXAGC_A_MCS15_MCS12
336 u16 regoffset_b
[6] = {
337 RTXAGC_B_RATE18_06
, RTXAGC_B_RATE54_24
,
338 RTXAGC_B_MCS03_MCS00
, RTXAGC_B_MCS07_MCS04
,
339 RTXAGC_B_MCS11_MCS08
, RTXAGC_B_MCS15_MCS12
341 u8 i
, rf
, pwr_val
[4];
345 for (rf
= 0; rf
< 2; rf
++) {
346 writeVal
= pValue
[rf
];
347 for (i
= 0; i
< 4; i
++) {
348 pwr_val
[i
] = (u8
)((writeVal
& (0x7f << (i
* 8))) >>
350 if (pwr_val
[i
] > RF6052_MAX_TX_PWR
)
351 pwr_val
[i
] = RF6052_MAX_TX_PWR
;
353 writeVal
= (pwr_val
[3] << 24) | (pwr_val
[2] << 16) |
354 (pwr_val
[1] << 8) | pwr_val
[0];
356 regoffset
= regoffset_a
[index
];
358 regoffset
= regoffset_b
[index
];
359 rtl_set_bbreg(hw
, regoffset
, MASKDWORD
, writeVal
);
360 RTPRINT(rtlpriv
, FPHY
, PHY_TXPWR
,
361 "Set 0x%x = %08x\n", regoffset
, writeVal
);
362 if (((get_rf_type(rtlphy
) == RF_2T2R
) &&
363 (regoffset
== RTXAGC_A_MCS15_MCS12
||
364 regoffset
== RTXAGC_B_MCS15_MCS12
)) ||
365 ((get_rf_type(rtlphy
) != RF_2T2R
) &&
366 (regoffset
== RTXAGC_A_MCS07_MCS04
||
367 regoffset
== RTXAGC_B_MCS07_MCS04
))) {
368 writeVal
= pwr_val
[3];
369 if (regoffset
== RTXAGC_A_MCS15_MCS12
||
370 regoffset
== RTXAGC_A_MCS07_MCS04
)
372 if (regoffset
== RTXAGC_B_MCS15_MCS12
||
373 regoffset
== RTXAGC_B_MCS07_MCS04
)
375 for (i
= 0; i
< 3; i
++) {
376 writeVal
= (writeVal
> 6) ? (writeVal
- 6) : 0;
377 rtl_write_byte(rtlpriv
, (u32
)(regoffset
+ i
),
384 void rtl92cu_phy_rf6052_set_ofdm_txpower(struct ieee80211_hw
*hw
,
385 u8
*ppowerlevel
, u8 channel
)
387 u32 writeVal
[2], powerBase0
[2], powerBase1
[2];
390 rtl92c_phy_get_power_base(hw
, ppowerlevel
,
391 channel
, &powerBase0
[0], &powerBase1
[0]);
392 for (index
= 0; index
< 6; index
++) {
393 _rtl92c_get_txpower_writeval_by_regulatory(hw
,
398 _rtl92c_write_ofdm_power_reg(hw
, index
, &writeVal
[0]);
402 bool rtl92cu_phy_rf6052_config(struct ieee80211_hw
*hw
)
404 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
405 struct rtl_phy
*rtlphy
= &(rtlpriv
->phy
);
406 bool rtstatus
= true;
407 u8 b_reg_hwparafile
= 1;
409 if (rtlphy
->rf_type
== RF_1T1R
)
410 rtlphy
->num_total_rfpath
= 1;
412 rtlphy
->num_total_rfpath
= 2;
413 if (b_reg_hwparafile
== 1)
414 rtstatus
= _rtl92c_phy_rf6052_config_parafile(hw
);
418 static bool _rtl92c_phy_rf6052_config_parafile(struct ieee80211_hw
*hw
)
420 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
421 struct rtl_phy
*rtlphy
= &(rtlpriv
->phy
);
424 bool rtstatus
= true;
425 struct bb_reg_def
*pphyreg
;
427 for (rfpath
= 0; rfpath
< rtlphy
->num_total_rfpath
; rfpath
++) {
428 pphyreg
= &rtlphy
->phyreg_def
[rfpath
];
432 u4_regvalue
= rtl_get_bbreg(hw
, pphyreg
->rfintfs
,
437 u4_regvalue
= rtl_get_bbreg(hw
, pphyreg
->rfintfs
,
441 rtl_set_bbreg(hw
, pphyreg
->rfintfe
, BRFSI_RFENV
<< 16, 0x1);
443 rtl_set_bbreg(hw
, pphyreg
->rfintfo
, BRFSI_RFENV
, 0x1);
445 rtl_set_bbreg(hw
, pphyreg
->rfhssi_para2
,
446 B3WIREADDREAALENGTH
, 0x0);
448 rtl_set_bbreg(hw
, pphyreg
->rfhssi_para2
, B3WIREDATALENGTH
, 0x0);
452 rtstatus
= rtl92cu_phy_config_rf_with_headerfile(hw
,
453 (enum radio_path
) rfpath
);
456 rtstatus
= rtl92cu_phy_config_rf_with_headerfile(hw
,
457 (enum radio_path
) rfpath
);
467 rtl_set_bbreg(hw
, pphyreg
->rfintfs
,
468 BRFSI_RFENV
, u4_regvalue
);
472 rtl_set_bbreg(hw
, pphyreg
->rfintfs
,
473 BRFSI_RFENV
<< 16, u4_regvalue
);
477 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_TRACE
,
478 "Radio[%d] Fail!!", rfpath
);
479 goto phy_rf_cfg_fail
;
482 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_TRACE
, "<---\n");
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