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rtlwifi: rtl8192c: rtl8192ce: rtl8192cu: rtl8192de: rtl8723ae: Add changes required...
[deliverable/linux.git] / drivers / net / wireless / rtlwifi / rtl8192se / hw.c
1 /******************************************************************************
2 *
3 * Copyright(c) 2009-2012 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30 #include "../wifi.h"
31 #include "../efuse.h"
32 #include "../base.h"
33 #include "../regd.h"
34 #include "../cam.h"
35 #include "../ps.h"
36 #include "../pci.h"
37 #include "reg.h"
38 #include "def.h"
39 #include "phy.h"
40 #include "dm.h"
41 #include "fw.h"
42 #include "led.h"
43 #include "hw.h"
44
45 void rtl92se_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
46 {
47 struct rtl_priv *rtlpriv = rtl_priv(hw);
48 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
49 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
50
51 switch (variable) {
52 case HW_VAR_RCR: {
53 *((u32 *) (val)) = rtlpci->receive_config;
54 break;
55 }
56 case HW_VAR_RF_STATE: {
57 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
58 break;
59 }
60 case HW_VAR_FW_PSMODE_STATUS: {
61 *((bool *) (val)) = ppsc->fw_current_inpsmode;
62 break;
63 }
64 case HW_VAR_CORRECT_TSF: {
65 u64 tsf;
66 u32 *ptsf_low = (u32 *)&tsf;
67 u32 *ptsf_high = ((u32 *)&tsf) + 1;
68
69 *ptsf_high = rtl_read_dword(rtlpriv, (TSFR + 4));
70 *ptsf_low = rtl_read_dword(rtlpriv, TSFR);
71
72 *((u64 *) (val)) = tsf;
73
74 break;
75 }
76 case HW_VAR_MRC: {
77 *((bool *)(val)) = rtlpriv->dm.current_mrc_switch;
78 break;
79 }
80 default: {
81 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
82 "switch case not processed\n");
83 break;
84 }
85 }
86 }
87
88 void rtl92se_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
89 {
90 struct rtl_priv *rtlpriv = rtl_priv(hw);
91 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
92 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
93 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
94 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
95 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
96
97 switch (variable) {
98 case HW_VAR_ETHER_ADDR:{
99 rtl_write_dword(rtlpriv, IDR0, ((u32 *)(val))[0]);
100 rtl_write_word(rtlpriv, IDR4, ((u16 *)(val + 4))[0]);
101 break;
102 }
103 case HW_VAR_BASIC_RATE:{
104 u16 rate_cfg = ((u16 *) val)[0];
105 u8 rate_index = 0;
106
107 if (rtlhal->version == VERSION_8192S_ACUT)
108 rate_cfg = rate_cfg & 0x150;
109 else
110 rate_cfg = rate_cfg & 0x15f;
111
112 rate_cfg |= 0x01;
113
114 rtl_write_byte(rtlpriv, RRSR, rate_cfg & 0xff);
115 rtl_write_byte(rtlpriv, RRSR + 1,
116 (rate_cfg >> 8) & 0xff);
117
118 while (rate_cfg > 0x1) {
119 rate_cfg = (rate_cfg >> 1);
120 rate_index++;
121 }
122 rtl_write_byte(rtlpriv, INIRTSMCS_SEL, rate_index);
123
124 break;
125 }
126 case HW_VAR_BSSID:{
127 rtl_write_dword(rtlpriv, BSSIDR, ((u32 *)(val))[0]);
128 rtl_write_word(rtlpriv, BSSIDR + 4,
129 ((u16 *)(val + 4))[0]);
130 break;
131 }
132 case HW_VAR_SIFS:{
133 rtl_write_byte(rtlpriv, SIFS_OFDM, val[0]);
134 rtl_write_byte(rtlpriv, SIFS_OFDM + 1, val[1]);
135 break;
136 }
137 case HW_VAR_SLOT_TIME:{
138 u8 e_aci;
139
140 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
141 "HW_VAR_SLOT_TIME %x\n", val[0]);
142
143 rtl_write_byte(rtlpriv, SLOT_TIME, val[0]);
144
145 for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
146 rtlpriv->cfg->ops->set_hw_reg(hw,
147 HW_VAR_AC_PARAM,
148 (&e_aci));
149 }
150 break;
151 }
152 case HW_VAR_ACK_PREAMBLE:{
153 u8 reg_tmp;
154 u8 short_preamble = (bool) (*val);
155 reg_tmp = (mac->cur_40_prime_sc) << 5;
156 if (short_preamble)
157 reg_tmp |= 0x80;
158
159 rtl_write_byte(rtlpriv, RRSR + 2, reg_tmp);
160 break;
161 }
162 case HW_VAR_AMPDU_MIN_SPACE:{
163 u8 min_spacing_to_set;
164 u8 sec_min_space;
165
166 min_spacing_to_set = *val;
167 if (min_spacing_to_set <= 7) {
168 if (rtlpriv->sec.pairwise_enc_algorithm ==
169 NO_ENCRYPTION)
170 sec_min_space = 0;
171 else
172 sec_min_space = 1;
173
174 if (min_spacing_to_set < sec_min_space)
175 min_spacing_to_set = sec_min_space;
176 if (min_spacing_to_set > 5)
177 min_spacing_to_set = 5;
178
179 mac->min_space_cfg =
180 ((mac->min_space_cfg & 0xf8) |
181 min_spacing_to_set);
182
183 *val = min_spacing_to_set;
184
185 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
186 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
187 mac->min_space_cfg);
188
189 rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE,
190 mac->min_space_cfg);
191 }
192 break;
193 }
194 case HW_VAR_SHORTGI_DENSITY:{
195 u8 density_to_set;
196
197 density_to_set = *val;
198 mac->min_space_cfg = rtlpriv->rtlhal.minspace_cfg;
199 mac->min_space_cfg |= (density_to_set << 3);
200
201 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
202 "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
203 mac->min_space_cfg);
204
205 rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE,
206 mac->min_space_cfg);
207
208 break;
209 }
210 case HW_VAR_AMPDU_FACTOR:{
211 u8 factor_toset;
212 u8 regtoset;
213 u8 factorlevel[18] = {
214 2, 4, 4, 7, 7, 13, 13,
215 13, 2, 7, 7, 13, 13,
216 15, 15, 15, 15, 0};
217 u8 index = 0;
218
219 factor_toset = *val;
220 if (factor_toset <= 3) {
221 factor_toset = (1 << (factor_toset + 2));
222 if (factor_toset > 0xf)
223 factor_toset = 0xf;
224
225 for (index = 0; index < 17; index++) {
226 if (factorlevel[index] > factor_toset)
227 factorlevel[index] =
228 factor_toset;
229 }
230
231 for (index = 0; index < 8; index++) {
232 regtoset = ((factorlevel[index * 2]) |
233 (factorlevel[index *
234 2 + 1] << 4));
235 rtl_write_byte(rtlpriv,
236 AGGLEN_LMT_L + index,
237 regtoset);
238 }
239
240 regtoset = ((factorlevel[16]) |
241 (factorlevel[17] << 4));
242 rtl_write_byte(rtlpriv, AGGLEN_LMT_H, regtoset);
243
244 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
245 "Set HW_VAR_AMPDU_FACTOR: %#x\n",
246 factor_toset);
247 }
248 break;
249 }
250 case HW_VAR_AC_PARAM:{
251 u8 e_aci = *val;
252 rtl92s_dm_init_edca_turbo(hw);
253
254 if (rtlpci->acm_method != eAcmWay2_SW)
255 rtlpriv->cfg->ops->set_hw_reg(hw,
256 HW_VAR_ACM_CTRL,
257 &e_aci);
258 break;
259 }
260 case HW_VAR_ACM_CTRL:{
261 u8 e_aci = *val;
262 union aci_aifsn *p_aci_aifsn = (union aci_aifsn *)(&(
263 mac->ac[0].aifs));
264 u8 acm = p_aci_aifsn->f.acm;
265 u8 acm_ctrl = rtl_read_byte(rtlpriv, AcmHwCtrl);
266
267 acm_ctrl = acm_ctrl | ((rtlpci->acm_method == 2) ?
268 0x0 : 0x1);
269
270 if (acm) {
271 switch (e_aci) {
272 case AC0_BE:
273 acm_ctrl |= AcmHw_BeqEn;
274 break;
275 case AC2_VI:
276 acm_ctrl |= AcmHw_ViqEn;
277 break;
278 case AC3_VO:
279 acm_ctrl |= AcmHw_VoqEn;
280 break;
281 default:
282 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
283 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
284 acm);
285 break;
286 }
287 } else {
288 switch (e_aci) {
289 case AC0_BE:
290 acm_ctrl &= (~AcmHw_BeqEn);
291 break;
292 case AC2_VI:
293 acm_ctrl &= (~AcmHw_ViqEn);
294 break;
295 case AC3_VO:
296 acm_ctrl &= (~AcmHw_BeqEn);
297 break;
298 default:
299 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
300 "switch case not processed\n");
301 break;
302 }
303 }
304
305 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
306 "HW_VAR_ACM_CTRL Write 0x%X\n", acm_ctrl);
307 rtl_write_byte(rtlpriv, AcmHwCtrl, acm_ctrl);
308 break;
309 }
310 case HW_VAR_RCR:{
311 rtl_write_dword(rtlpriv, RCR, ((u32 *) (val))[0]);
312 rtlpci->receive_config = ((u32 *) (val))[0];
313 break;
314 }
315 case HW_VAR_RETRY_LIMIT:{
316 u8 retry_limit = val[0];
317
318 rtl_write_word(rtlpriv, RETRY_LIMIT,
319 retry_limit << RETRY_LIMIT_SHORT_SHIFT |
320 retry_limit << RETRY_LIMIT_LONG_SHIFT);
321 break;
322 }
323 case HW_VAR_DUAL_TSF_RST: {
324 break;
325 }
326 case HW_VAR_EFUSE_BYTES: {
327 rtlefuse->efuse_usedbytes = *((u16 *) val);
328 break;
329 }
330 case HW_VAR_EFUSE_USAGE: {
331 rtlefuse->efuse_usedpercentage = *val;
332 break;
333 }
334 case HW_VAR_IO_CMD: {
335 break;
336 }
337 case HW_VAR_WPA_CONFIG: {
338 rtl_write_byte(rtlpriv, REG_SECR, *val);
339 break;
340 }
341 case HW_VAR_SET_RPWM:{
342 break;
343 }
344 case HW_VAR_H2C_FW_PWRMODE:{
345 break;
346 }
347 case HW_VAR_FW_PSMODE_STATUS: {
348 ppsc->fw_current_inpsmode = *((bool *) val);
349 break;
350 }
351 case HW_VAR_H2C_FW_JOINBSSRPT:{
352 break;
353 }
354 case HW_VAR_AID:{
355 break;
356 }
357 case HW_VAR_CORRECT_TSF:{
358 break;
359 }
360 case HW_VAR_MRC: {
361 bool bmrc_toset = *((bool *)val);
362 u8 u1bdata = 0;
363
364 if (bmrc_toset) {
365 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
366 MASKBYTE0, 0x33);
367 u1bdata = (u8)rtl_get_bbreg(hw,
368 ROFDM1_TRXPATHENABLE,
369 MASKBYTE0);
370 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE,
371 MASKBYTE0,
372 ((u1bdata & 0xf0) | 0x03));
373 u1bdata = (u8)rtl_get_bbreg(hw,
374 ROFDM0_TRXPATHENABLE,
375 MASKBYTE1);
376 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
377 MASKBYTE1,
378 (u1bdata | 0x04));
379
380 /* Update current settings. */
381 rtlpriv->dm.current_mrc_switch = bmrc_toset;
382 } else {
383 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
384 MASKBYTE0, 0x13);
385 u1bdata = (u8)rtl_get_bbreg(hw,
386 ROFDM1_TRXPATHENABLE,
387 MASKBYTE0);
388 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE,
389 MASKBYTE0,
390 ((u1bdata & 0xf0) | 0x01));
391 u1bdata = (u8)rtl_get_bbreg(hw,
392 ROFDM0_TRXPATHENABLE,
393 MASKBYTE1);
394 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
395 MASKBYTE1, (u1bdata & 0xfb));
396
397 /* Update current settings. */
398 rtlpriv->dm.current_mrc_switch = bmrc_toset;
399 }
400
401 break;
402 }
403 case HW_VAR_FW_LPS_ACTION: {
404 bool enter_fwlps = *((bool *)val);
405 u8 rpwm_val, fw_pwrmode;
406 bool fw_current_inps;
407
408 if (enter_fwlps) {
409 rpwm_val = 0x02; /* RF off */
410 fw_current_inps = true;
411 rtlpriv->cfg->ops->set_hw_reg(hw,
412 HW_VAR_FW_PSMODE_STATUS,
413 (u8 *)(&fw_current_inps));
414 rtlpriv->cfg->ops->set_hw_reg(hw,
415 HW_VAR_H2C_FW_PWRMODE,
416 (u8 *)(&ppsc->fwctrl_psmode));
417
418 rtlpriv->cfg->ops->set_hw_reg(hw,
419 HW_VAR_SET_RPWM,
420 (u8 *)(&rpwm_val));
421 } else {
422 rpwm_val = 0x0C; /* RF on */
423 fw_pwrmode = FW_PS_ACTIVE_MODE;
424 fw_current_inps = false;
425 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
426 (u8 *)(&rpwm_val));
427 rtlpriv->cfg->ops->set_hw_reg(hw,
428 HW_VAR_H2C_FW_PWRMODE,
429 (u8 *)(&fw_pwrmode));
430
431 rtlpriv->cfg->ops->set_hw_reg(hw,
432 HW_VAR_FW_PSMODE_STATUS,
433 (u8 *)(&fw_current_inps));
434 }
435 break; }
436 default:
437 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
438 "switch case not processed\n");
439 break;
440 }
441
442 }
443
444 void rtl92se_enable_hw_security_config(struct ieee80211_hw *hw)
445 {
446 struct rtl_priv *rtlpriv = rtl_priv(hw);
447 u8 sec_reg_value = 0x0;
448
449 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
450 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
451 rtlpriv->sec.pairwise_enc_algorithm,
452 rtlpriv->sec.group_enc_algorithm);
453
454 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
455 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
456 "not open hw encryption\n");
457 return;
458 }
459
460 sec_reg_value = SCR_TXENCENABLE | SCR_RXENCENABLE;
461
462 if (rtlpriv->sec.use_defaultkey) {
463 sec_reg_value |= SCR_TXUSEDK;
464 sec_reg_value |= SCR_RXUSEDK;
465 }
466
467 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, "The SECR-value %x\n",
468 sec_reg_value);
469
470 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
471
472 }
473
474 static u8 _rtl92se_halset_sysclk(struct ieee80211_hw *hw, u8 data)
475 {
476 struct rtl_priv *rtlpriv = rtl_priv(hw);
477 u8 waitcount = 100;
478 bool bresult = false;
479 u8 tmpvalue;
480
481 rtl_write_byte(rtlpriv, SYS_CLKR + 1, data);
482
483 /* Wait the MAC synchronized. */
484 udelay(400);
485
486 /* Check if it is set ready. */
487 tmpvalue = rtl_read_byte(rtlpriv, SYS_CLKR + 1);
488 bresult = ((tmpvalue & BIT(7)) == (data & BIT(7)));
489
490 if ((data & (BIT(6) | BIT(7))) == false) {
491 waitcount = 100;
492 tmpvalue = 0;
493
494 while (1) {
495 waitcount--;
496
497 tmpvalue = rtl_read_byte(rtlpriv, SYS_CLKR + 1);
498 if ((tmpvalue & BIT(6)))
499 break;
500
501 pr_err("wait for BIT(6) return value %x\n", tmpvalue);
502 if (waitcount == 0)
503 break;
504
505 udelay(10);
506 }
507
508 if (waitcount == 0)
509 bresult = false;
510 else
511 bresult = true;
512 }
513
514 return bresult;
515 }
516
517 void rtl8192se_gpiobit3_cfg_inputmode(struct ieee80211_hw *hw)
518 {
519 struct rtl_priv *rtlpriv = rtl_priv(hw);
520 u8 u1tmp;
521
522 /* The following config GPIO function */
523 rtl_write_byte(rtlpriv, MAC_PINMUX_CFG, (GPIOMUX_EN | GPIOSEL_GPIO));
524 u1tmp = rtl_read_byte(rtlpriv, GPIO_IO_SEL);
525
526 /* config GPIO3 to input */
527 u1tmp &= HAL_8192S_HW_GPIO_OFF_MASK;
528 rtl_write_byte(rtlpriv, GPIO_IO_SEL, u1tmp);
529
530 }
531
532 static u8 _rtl92se_rf_onoff_detect(struct ieee80211_hw *hw)
533 {
534 struct rtl_priv *rtlpriv = rtl_priv(hw);
535 u8 u1tmp;
536 u8 retval = ERFON;
537
538 /* The following config GPIO function */
539 rtl_write_byte(rtlpriv, MAC_PINMUX_CFG, (GPIOMUX_EN | GPIOSEL_GPIO));
540 u1tmp = rtl_read_byte(rtlpriv, GPIO_IO_SEL);
541
542 /* config GPIO3 to input */
543 u1tmp &= HAL_8192S_HW_GPIO_OFF_MASK;
544 rtl_write_byte(rtlpriv, GPIO_IO_SEL, u1tmp);
545
546 /* On some of the platform, driver cannot read correct
547 * value without delay between Write_GPIO_SEL and Read_GPIO_IN */
548 mdelay(10);
549
550 /* check GPIO3 */
551 u1tmp = rtl_read_byte(rtlpriv, GPIO_IN_SE);
552 retval = (u1tmp & HAL_8192S_HW_GPIO_OFF_BIT) ? ERFON : ERFOFF;
553
554 return retval;
555 }
556
557 static void _rtl92se_macconfig_before_fwdownload(struct ieee80211_hw *hw)
558 {
559 struct rtl_priv *rtlpriv = rtl_priv(hw);
560 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
561 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
562
563 u8 i;
564 u8 tmpu1b;
565 u16 tmpu2b;
566 u8 pollingcnt = 20;
567
568 if (rtlpci->first_init) {
569 /* Reset PCIE Digital */
570 tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
571 tmpu1b &= 0xFE;
572 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b);
573 udelay(1);
574 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b | BIT(0));
575 }
576
577 /* Switch to SW IO control */
578 tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
579 if (tmpu1b & BIT(7)) {
580 tmpu1b &= ~(BIT(6) | BIT(7));
581
582 /* Set failed, return to prevent hang. */
583 if (!_rtl92se_halset_sysclk(hw, tmpu1b))
584 return;
585 }
586
587 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, 0x0);
588 udelay(50);
589 rtl_write_byte(rtlpriv, LDOA15_CTRL, 0x34);
590 udelay(50);
591
592 /* Clear FW RPWM for FW control LPS.*/
593 rtl_write_byte(rtlpriv, RPWM, 0x0);
594
595 /* Reset MAC-IO and CPU and Core Digital BIT(10)/11/15 */
596 tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
597 tmpu1b &= 0x73;
598 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b);
599 /* wait for BIT 10/11/15 to pull high automatically!! */
600 mdelay(1);
601
602 rtl_write_byte(rtlpriv, CMDR, 0);
603 rtl_write_byte(rtlpriv, TCR, 0);
604
605 /* Data sheet not define 0x562!!! Copy from WMAC!!!!! */
606 tmpu1b = rtl_read_byte(rtlpriv, 0x562);
607 tmpu1b |= 0x08;
608 rtl_write_byte(rtlpriv, 0x562, tmpu1b);
609 tmpu1b &= ~(BIT(3));
610 rtl_write_byte(rtlpriv, 0x562, tmpu1b);
611
612 /* Enable AFE clock source */
613 tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL);
614 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL, (tmpu1b | 0x01));
615 /* Delay 1.5ms */
616 mdelay(2);
617 tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL + 1);
618 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL + 1, (tmpu1b & 0xfb));
619
620 /* Enable AFE Macro Block's Bandgap */
621 tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC);
622 rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | BIT(0)));
623 mdelay(1);
624
625 /* Enable AFE Mbias */
626 tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC);
627 rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | 0x02));
628 mdelay(1);
629
630 /* Enable LDOA15 block */
631 tmpu1b = rtl_read_byte(rtlpriv, LDOA15_CTRL);
632 rtl_write_byte(rtlpriv, LDOA15_CTRL, (tmpu1b | BIT(0)));
633
634 /* Set Digital Vdd to Retention isolation Path. */
635 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_ISO_CTRL);
636 rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, (tmpu2b | BIT(11)));
637
638 /* For warm reboot NIC disappera bug. */
639 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
640 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(13)));
641
642 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x68);
643
644 /* Enable AFE PLL Macro Block */
645 /* We need to delay 100u before enabling PLL. */
646 udelay(200);
647 tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL);
648 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4)));
649
650 /* for divider reset */
651 udelay(100);
652 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) |
653 BIT(4) | BIT(6)));
654 udelay(10);
655 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4)));
656 udelay(10);
657
658 /* Enable MAC 80MHZ clock */
659 tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL + 1);
660 rtl_write_byte(rtlpriv, AFE_PLL_CTRL + 1, (tmpu1b | BIT(0)));
661 mdelay(1);
662
663 /* Release isolation AFE PLL & MD */
664 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, 0xA6);
665
666 /* Enable MAC clock */
667 tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR);
668 rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b | BIT(12) | BIT(11)));
669
670 /* Enable Core digital and enable IOREG R/W */
671 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
672 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11)));
673
674 tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
675 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b & ~(BIT(7)));
676
677 /* enable REG_EN */
678 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11) | BIT(15)));
679
680 /* Switch the control path. */
681 tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR);
682 rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b & (~BIT(2))));
683
684 tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
685 tmpu1b = ((tmpu1b | BIT(7)) & (~BIT(6)));
686 if (!_rtl92se_halset_sysclk(hw, tmpu1b))
687 return; /* Set failed, return to prevent hang. */
688
689 rtl_write_word(rtlpriv, CMDR, 0x07FC);
690
691 /* MH We must enable the section of code to prevent load IMEM fail. */
692 /* Load MAC register from WMAc temporarily We simulate macreg. */
693 /* txt HW will provide MAC txt later */
694 rtl_write_byte(rtlpriv, 0x6, 0x30);
695 rtl_write_byte(rtlpriv, 0x49, 0xf0);
696
697 rtl_write_byte(rtlpriv, 0x4b, 0x81);
698
699 rtl_write_byte(rtlpriv, 0xb5, 0x21);
700
701 rtl_write_byte(rtlpriv, 0xdc, 0xff);
702 rtl_write_byte(rtlpriv, 0xdd, 0xff);
703 rtl_write_byte(rtlpriv, 0xde, 0xff);
704 rtl_write_byte(rtlpriv, 0xdf, 0xff);
705
706 rtl_write_byte(rtlpriv, 0x11a, 0x00);
707 rtl_write_byte(rtlpriv, 0x11b, 0x00);
708
709 for (i = 0; i < 32; i++)
710 rtl_write_byte(rtlpriv, INIMCS_SEL + i, 0x1b);
711
712 rtl_write_byte(rtlpriv, 0x236, 0xff);
713
714 rtl_write_byte(rtlpriv, 0x503, 0x22);
715
716 if (ppsc->support_aspm && !ppsc->support_backdoor)
717 rtl_write_byte(rtlpriv, 0x560, 0x40);
718 else
719 rtl_write_byte(rtlpriv, 0x560, 0x00);
720
721 rtl_write_byte(rtlpriv, DBG_PORT, 0x91);
722
723 /* Set RX Desc Address */
724 rtl_write_dword(rtlpriv, RDQDA, rtlpci->rx_ring[RX_MPDU_QUEUE].dma);
725 rtl_write_dword(rtlpriv, RCDA, rtlpci->rx_ring[RX_CMD_QUEUE].dma);
726
727 /* Set TX Desc Address */
728 rtl_write_dword(rtlpriv, TBKDA, rtlpci->tx_ring[BK_QUEUE].dma);
729 rtl_write_dword(rtlpriv, TBEDA, rtlpci->tx_ring[BE_QUEUE].dma);
730 rtl_write_dword(rtlpriv, TVIDA, rtlpci->tx_ring[VI_QUEUE].dma);
731 rtl_write_dword(rtlpriv, TVODA, rtlpci->tx_ring[VO_QUEUE].dma);
732 rtl_write_dword(rtlpriv, TBDA, rtlpci->tx_ring[BEACON_QUEUE].dma);
733 rtl_write_dword(rtlpriv, TCDA, rtlpci->tx_ring[TXCMD_QUEUE].dma);
734 rtl_write_dword(rtlpriv, TMDA, rtlpci->tx_ring[MGNT_QUEUE].dma);
735 rtl_write_dword(rtlpriv, THPDA, rtlpci->tx_ring[HIGH_QUEUE].dma);
736 rtl_write_dword(rtlpriv, HDA, rtlpci->tx_ring[HCCA_QUEUE].dma);
737
738 rtl_write_word(rtlpriv, CMDR, 0x37FC);
739
740 /* To make sure that TxDMA can ready to download FW. */
741 /* We should reset TxDMA if IMEM RPT was not ready. */
742 do {
743 tmpu1b = rtl_read_byte(rtlpriv, TCR);
744 if ((tmpu1b & TXDMA_INIT_VALUE) == TXDMA_INIT_VALUE)
745 break;
746
747 udelay(5);
748 } while (pollingcnt--);
749
750 if (pollingcnt <= 0) {
751 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
752 "Polling TXDMA_INIT_VALUE timeout!! Current TCR(%#x)\n",
753 tmpu1b);
754 tmpu1b = rtl_read_byte(rtlpriv, CMDR);
755 rtl_write_byte(rtlpriv, CMDR, tmpu1b & (~TXDMA_EN));
756 udelay(2);
757 /* Reset TxDMA */
758 rtl_write_byte(rtlpriv, CMDR, tmpu1b | TXDMA_EN);
759 }
760
761 /* After MACIO reset,we must refresh LED state. */
762 if ((ppsc->rfoff_reason == RF_CHANGE_BY_IPS) ||
763 (ppsc->rfoff_reason == 0)) {
764 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
765 struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
766 enum rf_pwrstate rfpwr_state_toset;
767 rfpwr_state_toset = _rtl92se_rf_onoff_detect(hw);
768
769 if (rfpwr_state_toset == ERFON)
770 rtl92se_sw_led_on(hw, pLed0);
771 }
772 }
773
774 static void _rtl92se_macconfig_after_fwdownload(struct ieee80211_hw *hw)
775 {
776 struct rtl_priv *rtlpriv = rtl_priv(hw);
777 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
778 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
779 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
780 u8 i;
781 u16 tmpu2b;
782
783 /* 1. System Configure Register (Offset: 0x0000 - 0x003F) */
784
785 /* 2. Command Control Register (Offset: 0x0040 - 0x004F) */
786 /* Turn on 0x40 Command register */
787 rtl_write_word(rtlpriv, CMDR, (BBRSTN | BB_GLB_RSTN |
788 SCHEDULE_EN | MACRXEN | MACTXEN | DDMA_EN | FW2HW_EN |
789 RXDMA_EN | TXDMA_EN | HCI_RXDMA_EN | HCI_TXDMA_EN));
790
791 /* Set TCR TX DMA pre 2 FULL enable bit */
792 rtl_write_dword(rtlpriv, TCR, rtl_read_dword(rtlpriv, TCR) |
793 TXDMAPRE2FULL);
794
795 /* Set RCR */
796 rtl_write_dword(rtlpriv, RCR, rtlpci->receive_config);
797
798 /* 3. MACID Setting Register (Offset: 0x0050 - 0x007F) */
799
800 /* 4. Timing Control Register (Offset: 0x0080 - 0x009F) */
801 /* Set CCK/OFDM SIFS */
802 /* CCK SIFS shall always be 10us. */
803 rtl_write_word(rtlpriv, SIFS_CCK, 0x0a0a);
804 rtl_write_word(rtlpriv, SIFS_OFDM, 0x1010);
805
806 /* Set AckTimeout */
807 rtl_write_byte(rtlpriv, ACK_TIMEOUT, 0x40);
808
809 /* Beacon related */
810 rtl_write_word(rtlpriv, BCN_INTERVAL, 100);
811 rtl_write_word(rtlpriv, ATIMWND, 2);
812
813 /* 5. FIFO Control Register (Offset: 0x00A0 - 0x015F) */
814 /* 5.1 Initialize Number of Reserved Pages in Firmware Queue */
815 /* Firmware allocate now, associate with FW internal setting.!!! */
816
817 /* 5.2 Setting TX/RX page size 0/1/2/3/4=64/128/256/512/1024 */
818 /* 5.3 Set driver info, we only accept PHY status now. */
819 /* 5.4 Set RXDMA arbitration to control RXDMA/MAC/FW R/W for RXFIFO */
820 rtl_write_byte(rtlpriv, RXDMA, rtl_read_byte(rtlpriv, RXDMA) | BIT(6));
821
822 /* 6. Adaptive Control Register (Offset: 0x0160 - 0x01CF) */
823 /* Set RRSR to all legacy rate and HT rate
824 * CCK rate is supported by default.
825 * CCK rate will be filtered out only when associated
826 * AP does not support it.
827 * Only enable ACK rate to OFDM 24M
828 * Disable RRSR for CCK rate in A-Cut */
829
830 if (rtlhal->version == VERSION_8192S_ACUT)
831 rtl_write_byte(rtlpriv, RRSR, 0xf0);
832 else if (rtlhal->version == VERSION_8192S_BCUT)
833 rtl_write_byte(rtlpriv, RRSR, 0xff);
834 rtl_write_byte(rtlpriv, RRSR + 1, 0x01);
835 rtl_write_byte(rtlpriv, RRSR + 2, 0x00);
836
837 /* A-Cut IC do not support CCK rate. We forbid ARFR to */
838 /* fallback to CCK rate */
839 for (i = 0; i < 8; i++) {
840 /*Disable RRSR for CCK rate in A-Cut */
841 if (rtlhal->version == VERSION_8192S_ACUT)
842 rtl_write_dword(rtlpriv, ARFR0 + i * 4, 0x1f0ff0f0);
843 }
844
845 /* Different rate use different AMPDU size */
846 /* MCS32/ MCS15_SG use max AMPDU size 15*2=30K */
847 rtl_write_byte(rtlpriv, AGGLEN_LMT_H, 0x0f);
848 /* MCS0/1/2/3 use max AMPDU size 4*2=8K */
849 rtl_write_word(rtlpriv, AGGLEN_LMT_L, 0x7442);
850 /* MCS4/5 use max AMPDU size 8*2=16K 6/7 use 10*2=20K */
851 rtl_write_word(rtlpriv, AGGLEN_LMT_L + 2, 0xddd7);
852 /* MCS8/9 use max AMPDU size 8*2=16K 10/11 use 10*2=20K */
853 rtl_write_word(rtlpriv, AGGLEN_LMT_L + 4, 0xd772);
854 /* MCS12/13/14/15 use max AMPDU size 15*2=30K */
855 rtl_write_word(rtlpriv, AGGLEN_LMT_L + 6, 0xfffd);
856
857 /* Set Data / Response auto rate fallack retry count */
858 rtl_write_dword(rtlpriv, DARFRC, 0x04010000);
859 rtl_write_dword(rtlpriv, DARFRC + 4, 0x09070605);
860 rtl_write_dword(rtlpriv, RARFRC, 0x04010000);
861 rtl_write_dword(rtlpriv, RARFRC + 4, 0x09070605);
862
863 /* 7. EDCA Setting Register (Offset: 0x01D0 - 0x01FF) */
864 /* Set all rate to support SG */
865 rtl_write_word(rtlpriv, SG_RATE, 0xFFFF);
866
867 /* 8. WMAC, BA, and CCX related Register (Offset: 0x0200 - 0x023F) */
868 /* Set NAV protection length */
869 rtl_write_word(rtlpriv, NAV_PROT_LEN, 0x0080);
870 /* CF-END Threshold */
871 rtl_write_byte(rtlpriv, CFEND_TH, 0xFF);
872 /* Set AMPDU minimum space */
873 rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE, 0x07);
874 /* Set TXOP stall control for several queue/HI/BCN/MGT/ */
875 rtl_write_byte(rtlpriv, TXOP_STALL_CTRL, 0x00);
876
877 /* 9. Security Control Register (Offset: 0x0240 - 0x025F) */
878 /* 10. Power Save Control Register (Offset: 0x0260 - 0x02DF) */
879 /* 11. General Purpose Register (Offset: 0x02E0 - 0x02FF) */
880 /* 12. Host Interrupt Status Register (Offset: 0x0300 - 0x030F) */
881 /* 13. Test Mode and Debug Control Register (Offset: 0x0310 - 0x034F) */
882
883 /* 14. Set driver info, we only accept PHY status now. */
884 rtl_write_byte(rtlpriv, RXDRVINFO_SZ, 4);
885
886 /* 15. For EEPROM R/W Workaround */
887 /* 16. For EFUSE to share REG_SYS_FUNC_EN with EEPROM!!! */
888 tmpu2b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN);
889 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, tmpu2b | BIT(13));
890 tmpu2b = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL);
891 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, tmpu2b & (~BIT(8)));
892
893 /* 17. For EFUSE */
894 /* We may R/W EFUSE in EEPROM mode */
895 if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
896 u8 tempval;
897
898 tempval = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL + 1);
899 tempval &= 0xFE;
900 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, tempval);
901
902 /* Change Program timing */
903 rtl_write_byte(rtlpriv, REG_EFUSE_CTRL + 3, 0x72);
904 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "EFUSE CONFIG OK\n");
905 }
906
907 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "OK\n");
908
909 }
910
911 static void _rtl92se_hw_configure(struct ieee80211_hw *hw)
912 {
913 struct rtl_priv *rtlpriv = rtl_priv(hw);
914 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
915 struct rtl_phy *rtlphy = &(rtlpriv->phy);
916 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
917
918 u8 reg_bw_opmode = 0;
919 u32 reg_rrsr = 0;
920 u8 regtmp = 0;
921
922 reg_bw_opmode = BW_OPMODE_20MHZ;
923 reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
924
925 regtmp = rtl_read_byte(rtlpriv, INIRTSMCS_SEL);
926 reg_rrsr = ((reg_rrsr & 0x000fffff) << 8) | regtmp;
927 rtl_write_dword(rtlpriv, INIRTSMCS_SEL, reg_rrsr);
928 rtl_write_byte(rtlpriv, BW_OPMODE, reg_bw_opmode);
929
930 /* Set Retry Limit here */
931 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RETRY_LIMIT,
932 (u8 *)(&rtlpci->shortretry_limit));
933
934 rtl_write_byte(rtlpriv, MLT, 0x8f);
935
936 /* For Min Spacing configuration. */
937 switch (rtlphy->rf_type) {
938 case RF_1T2R:
939 case RF_1T1R:
940 rtlhal->minspace_cfg = (MAX_MSS_DENSITY_1T << 3);
941 break;
942 case RF_2T2R:
943 case RF_2T2R_GREEN:
944 rtlhal->minspace_cfg = (MAX_MSS_DENSITY_2T << 3);
945 break;
946 }
947 rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE, rtlhal->minspace_cfg);
948 }
949
950 int rtl92se_hw_init(struct ieee80211_hw *hw)
951 {
952 struct rtl_priv *rtlpriv = rtl_priv(hw);
953 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
954 struct rtl_phy *rtlphy = &(rtlpriv->phy);
955 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
956 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
957 u8 tmp_byte = 0;
958
959 bool rtstatus = true;
960 u8 tmp_u1b;
961 int err = false;
962 u8 i;
963 int wdcapra_add[] = {
964 EDCAPARA_BE, EDCAPARA_BK,
965 EDCAPARA_VI, EDCAPARA_VO};
966 u8 secr_value = 0x0;
967
968 rtlpci->being_init_adapter = true;
969
970 rtlpriv->intf_ops->disable_aspm(hw);
971
972 /* 1. MAC Initialize */
973 /* Before FW download, we have to set some MAC register */
974 _rtl92se_macconfig_before_fwdownload(hw);
975
976 rtlhal->version = (enum version_8192s)((rtl_read_dword(rtlpriv,
977 PMC_FSM) >> 16) & 0xF);
978
979 rtl8192se_gpiobit3_cfg_inputmode(hw);
980
981 /* 2. download firmware */
982 rtstatus = rtl92s_download_fw(hw);
983 if (!rtstatus) {
984 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
985 "Failed to download FW. Init HW without FW now... "
986 "Please copy FW into /lib/firmware/rtlwifi\n");
987 return 1;
988 }
989
990 /* After FW download, we have to reset MAC register */
991 _rtl92se_macconfig_after_fwdownload(hw);
992
993 /*Retrieve default FW Cmd IO map. */
994 rtlhal->fwcmd_iomap = rtl_read_word(rtlpriv, LBUS_MON_ADDR);
995 rtlhal->fwcmd_ioparam = rtl_read_dword(rtlpriv, LBUS_ADDR_MASK);
996
997 /* 3. Initialize MAC/PHY Config by MACPHY_reg.txt */
998 if (!rtl92s_phy_mac_config(hw)) {
999 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "MAC Config failed\n");
1000 return rtstatus;
1001 }
1002
1003 /* because last function modify RCR, so we update
1004 * rcr var here, or TP will unstable for receive_config
1005 * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx
1006 * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252
1007 */
1008 rtlpci->receive_config = rtl_read_dword(rtlpriv, RCR);
1009 rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
1010 rtl_write_dword(rtlpriv, RCR, rtlpci->receive_config);
1011
1012 /* Make sure BB/RF write OK. We should prevent enter IPS. radio off. */
1013 /* We must set flag avoid BB/RF config period later!! */
1014 rtl_write_dword(rtlpriv, CMDR, 0x37FC);
1015
1016 /* 4. Initialize BB After MAC Config PHY_reg.txt, AGC_Tab.txt */
1017 if (!rtl92s_phy_bb_config(hw)) {
1018 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG, "BB Config failed\n");
1019 return rtstatus;
1020 }
1021
1022 /* 5. Initiailze RF RAIO_A.txt RF RAIO_B.txt */
1023 /* Before initalizing RF. We can not use FW to do RF-R/W. */
1024
1025 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
1026
1027 /* Before RF-R/W we must execute the IO from Scott's suggestion. */
1028 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL + 1, 0xDB);
1029 if (rtlhal->version == VERSION_8192S_ACUT)
1030 rtl_write_byte(rtlpriv, SPS1_CTRL + 3, 0x07);
1031 else
1032 rtl_write_byte(rtlpriv, RF_CTRL, 0x07);
1033
1034 if (!rtl92s_phy_rf_config(hw)) {
1035 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "RF Config failed\n");
1036 return rtstatus;
1037 }
1038
1039 /* After read predefined TXT, we must set BB/MAC/RF
1040 * register as our requirement */
1041
1042 rtlphy->rfreg_chnlval[0] = rtl92s_phy_query_rf_reg(hw,
1043 (enum radio_path)0,
1044 RF_CHNLBW,
1045 RFREG_OFFSET_MASK);
1046 rtlphy->rfreg_chnlval[1] = rtl92s_phy_query_rf_reg(hw,
1047 (enum radio_path)1,
1048 RF_CHNLBW,
1049 RFREG_OFFSET_MASK);
1050
1051 /*---- Set CCK and OFDM Block "ON"----*/
1052 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
1053 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
1054
1055 /*3 Set Hardware(Do nothing now) */
1056 _rtl92se_hw_configure(hw);
1057
1058 /* Read EEPROM TX power index and PHY_REG_PG.txt to capture correct */
1059 /* TX power index for different rate set. */
1060 /* Get original hw reg values */
1061 rtl92s_phy_get_hw_reg_originalvalue(hw);
1062 /* Write correct tx power index */
1063 rtl92s_phy_set_txpower(hw, rtlphy->current_channel);
1064
1065 /* We must set MAC address after firmware download. */
1066 for (i = 0; i < 6; i++)
1067 rtl_write_byte(rtlpriv, MACIDR0 + i, rtlefuse->dev_addr[i]);
1068
1069 /* EEPROM R/W workaround */
1070 tmp_u1b = rtl_read_byte(rtlpriv, MAC_PINMUX_CFG);
1071 rtl_write_byte(rtlpriv, MAC_PINMUX_CFG, tmp_u1b & (~BIT(3)));
1072
1073 rtl_write_byte(rtlpriv, 0x4d, 0x0);
1074
1075 if (hal_get_firmwareversion(rtlpriv) >= 0x49) {
1076 tmp_byte = rtl_read_byte(rtlpriv, FW_RSVD_PG_CRTL) & (~BIT(4));
1077 tmp_byte = tmp_byte | BIT(5);
1078 rtl_write_byte(rtlpriv, FW_RSVD_PG_CRTL, tmp_byte);
1079 rtl_write_dword(rtlpriv, TXDESC_MSK, 0xFFFFCFFF);
1080 }
1081
1082 /* We enable high power and RA related mechanism after NIC
1083 * initialized. */
1084 if (hal_get_firmwareversion(rtlpriv) >= 0x35) {
1085 /* Fw v.53 and later. */
1086 rtl92s_phy_set_fw_cmd(hw, FW_CMD_RA_INIT);
1087 } else if (hal_get_firmwareversion(rtlpriv) == 0x34) {
1088 /* Fw v.52. */
1089 rtl_write_dword(rtlpriv, WFM5, FW_RA_INIT);
1090 rtl92s_phy_chk_fwcmd_iodone(hw);
1091 } else {
1092 /* Compatible earlier FW version. */
1093 rtl_write_dword(rtlpriv, WFM5, FW_RA_RESET);
1094 rtl92s_phy_chk_fwcmd_iodone(hw);
1095 rtl_write_dword(rtlpriv, WFM5, FW_RA_ACTIVE);
1096 rtl92s_phy_chk_fwcmd_iodone(hw);
1097 rtl_write_dword(rtlpriv, WFM5, FW_RA_REFRESH);
1098 rtl92s_phy_chk_fwcmd_iodone(hw);
1099 }
1100
1101 /* Add to prevent ASPM bug. */
1102 /* Always enable hst and NIC clock request. */
1103 rtl92s_phy_switch_ephy_parameter(hw);
1104
1105 /* Security related
1106 * 1. Clear all H/W keys.
1107 * 2. Enable H/W encryption/decryption. */
1108 rtl_cam_reset_all_entry(hw);
1109 secr_value |= SCR_TXENCENABLE;
1110 secr_value |= SCR_RXENCENABLE;
1111 secr_value |= SCR_NOSKMC;
1112 rtl_write_byte(rtlpriv, REG_SECR, secr_value);
1113
1114 for (i = 0; i < 4; i++)
1115 rtl_write_dword(rtlpriv, wdcapra_add[i], 0x5e4322);
1116
1117 if (rtlphy->rf_type == RF_1T2R) {
1118 bool mrc2set = true;
1119 /* Turn on B-Path */
1120 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_MRC, (u8 *)&mrc2set);
1121 }
1122
1123 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_ON);
1124 rtl92s_dm_init(hw);
1125 rtlpci->being_init_adapter = false;
1126
1127 return err;
1128 }
1129
1130 void rtl92se_set_mac_addr(struct rtl_io *io, const u8 *addr)
1131 {
1132 /* This is a stub. */
1133 }
1134
1135 void rtl92se_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1136 {
1137 struct rtl_priv *rtlpriv = rtl_priv(hw);
1138 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1139 u32 reg_rcr = rtlpci->receive_config;
1140
1141 if (rtlpriv->psc.rfpwr_state != ERFON)
1142 return;
1143
1144 if (check_bssid) {
1145 reg_rcr |= (RCR_CBSSID);
1146 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(&reg_rcr));
1147 } else if (!check_bssid) {
1148 reg_rcr &= (~RCR_CBSSID);
1149 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(&reg_rcr));
1150 }
1151
1152 }
1153
1154 static int _rtl92se_set_media_status(struct ieee80211_hw *hw,
1155 enum nl80211_iftype type)
1156 {
1157 struct rtl_priv *rtlpriv = rtl_priv(hw);
1158 u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1159 u32 temp;
1160 bt_msr &= ~MSR_LINK_MASK;
1161
1162 switch (type) {
1163 case NL80211_IFTYPE_UNSPECIFIED:
1164 bt_msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT);
1165 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1166 "Set Network type to NO LINK!\n");
1167 break;
1168 case NL80211_IFTYPE_ADHOC:
1169 bt_msr |= (MSR_LINK_ADHOC << MSR_LINK_SHIFT);
1170 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1171 "Set Network type to Ad Hoc!\n");
1172 break;
1173 case NL80211_IFTYPE_STATION:
1174 bt_msr |= (MSR_LINK_MANAGED << MSR_LINK_SHIFT);
1175 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1176 "Set Network type to STA!\n");
1177 break;
1178 case NL80211_IFTYPE_AP:
1179 bt_msr |= (MSR_LINK_MASTER << MSR_LINK_SHIFT);
1180 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1181 "Set Network type to AP!\n");
1182 break;
1183 default:
1184 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1185 "Network type %d not supported!\n", type);
1186 return 1;
1187 break;
1188
1189 }
1190
1191 rtl_write_byte(rtlpriv, (MSR), bt_msr);
1192
1193 temp = rtl_read_dword(rtlpriv, TCR);
1194 rtl_write_dword(rtlpriv, TCR, temp & (~BIT(8)));
1195 rtl_write_dword(rtlpriv, TCR, temp | BIT(8));
1196
1197
1198 return 0;
1199 }
1200
1201 /* HW_VAR_MEDIA_STATUS & HW_VAR_CECHK_BSSID */
1202 int rtl92se_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1203 {
1204 struct rtl_priv *rtlpriv = rtl_priv(hw);
1205
1206 if (_rtl92se_set_media_status(hw, type))
1207 return -EOPNOTSUPP;
1208
1209 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1210 if (type != NL80211_IFTYPE_AP)
1211 rtl92se_set_check_bssid(hw, true);
1212 } else {
1213 rtl92se_set_check_bssid(hw, false);
1214 }
1215
1216 return 0;
1217 }
1218
1219 /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */
1220 void rtl92se_set_qos(struct ieee80211_hw *hw, int aci)
1221 {
1222 struct rtl_priv *rtlpriv = rtl_priv(hw);
1223 rtl92s_dm_init_edca_turbo(hw);
1224
1225 switch (aci) {
1226 case AC1_BK:
1227 rtl_write_dword(rtlpriv, EDCAPARA_BK, 0xa44f);
1228 break;
1229 case AC0_BE:
1230 /* rtl_write_dword(rtlpriv, EDCAPARA_BE, u4b_ac_param); */
1231 break;
1232 case AC2_VI:
1233 rtl_write_dword(rtlpriv, EDCAPARA_VI, 0x5e4322);
1234 break;
1235 case AC3_VO:
1236 rtl_write_dword(rtlpriv, EDCAPARA_VO, 0x2f3222);
1237 break;
1238 default:
1239 RT_ASSERT(false, "invalid aci: %d !\n", aci);
1240 break;
1241 }
1242 }
1243
1244 void rtl92se_enable_interrupt(struct ieee80211_hw *hw)
1245 {
1246 struct rtl_priv *rtlpriv = rtl_priv(hw);
1247 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1248
1249 rtl_write_dword(rtlpriv, INTA_MASK, rtlpci->irq_mask[0]);
1250 /* Support Bit 32-37(Assign as Bit 0-5) interrupt setting now */
1251 rtl_write_dword(rtlpriv, INTA_MASK + 4, rtlpci->irq_mask[1] & 0x3F);
1252 }
1253
1254 void rtl92se_disable_interrupt(struct ieee80211_hw *hw)
1255 {
1256 struct rtl_priv *rtlpriv;
1257 struct rtl_pci *rtlpci;
1258
1259 rtlpriv = rtl_priv(hw);
1260 /* if firmware not available, no interrupts */
1261 if (!rtlpriv || !rtlpriv->max_fw_size)
1262 return;
1263 rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1264 rtl_write_dword(rtlpriv, INTA_MASK, 0);
1265 rtl_write_dword(rtlpriv, INTA_MASK + 4, 0);
1266
1267 synchronize_irq(rtlpci->pdev->irq);
1268 }
1269
1270 static u8 _rtl92s_set_sysclk(struct ieee80211_hw *hw, u8 data)
1271 {
1272 struct rtl_priv *rtlpriv = rtl_priv(hw);
1273 u8 waitcnt = 100;
1274 bool result = false;
1275 u8 tmp;
1276
1277 rtl_write_byte(rtlpriv, SYS_CLKR + 1, data);
1278
1279 /* Wait the MAC synchronized. */
1280 udelay(400);
1281
1282 /* Check if it is set ready. */
1283 tmp = rtl_read_byte(rtlpriv, SYS_CLKR + 1);
1284 result = ((tmp & BIT(7)) == (data & BIT(7)));
1285
1286 if ((data & (BIT(6) | BIT(7))) == false) {
1287 waitcnt = 100;
1288 tmp = 0;
1289
1290 while (1) {
1291 waitcnt--;
1292 tmp = rtl_read_byte(rtlpriv, SYS_CLKR + 1);
1293
1294 if ((tmp & BIT(6)))
1295 break;
1296
1297 pr_err("wait for BIT(6) return value %x\n", tmp);
1298
1299 if (waitcnt == 0)
1300 break;
1301 udelay(10);
1302 }
1303
1304 if (waitcnt == 0)
1305 result = false;
1306 else
1307 result = true;
1308 }
1309
1310 return result;
1311 }
1312
1313 static void _rtl92s_phy_set_rfhalt(struct ieee80211_hw *hw)
1314 {
1315 struct rtl_priv *rtlpriv = rtl_priv(hw);
1316 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1317 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1318 u8 u1btmp;
1319
1320 if (rtlhal->driver_going2unload)
1321 rtl_write_byte(rtlpriv, 0x560, 0x0);
1322
1323 /* Power save for BB/RF */
1324 u1btmp = rtl_read_byte(rtlpriv, LDOV12D_CTRL);
1325 u1btmp |= BIT(0);
1326 rtl_write_byte(rtlpriv, LDOV12D_CTRL, u1btmp);
1327 rtl_write_byte(rtlpriv, SPS1_CTRL, 0x0);
1328 rtl_write_byte(rtlpriv, TXPAUSE, 0xFF);
1329 rtl_write_word(rtlpriv, CMDR, 0x57FC);
1330 udelay(100);
1331 rtl_write_word(rtlpriv, CMDR, 0x77FC);
1332 rtl_write_byte(rtlpriv, PHY_CCA, 0x0);
1333 udelay(10);
1334 rtl_write_word(rtlpriv, CMDR, 0x37FC);
1335 udelay(10);
1336 rtl_write_word(rtlpriv, CMDR, 0x77FC);
1337 udelay(10);
1338 rtl_write_word(rtlpriv, CMDR, 0x57FC);
1339 rtl_write_word(rtlpriv, CMDR, 0x0000);
1340
1341 if (rtlhal->driver_going2unload) {
1342 u1btmp = rtl_read_byte(rtlpriv, (REG_SYS_FUNC_EN + 1));
1343 u1btmp &= ~(BIT(0));
1344 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, u1btmp);
1345 }
1346
1347 u1btmp = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
1348
1349 /* Add description. After switch control path. register
1350 * after page1 will be invisible. We can not do any IO
1351 * for register>0x40. After resume&MACIO reset, we need
1352 * to remember previous reg content. */
1353 if (u1btmp & BIT(7)) {
1354 u1btmp &= ~(BIT(6) | BIT(7));
1355 if (!_rtl92s_set_sysclk(hw, u1btmp)) {
1356 pr_err("Switch ctrl path fail\n");
1357 return;
1358 }
1359 }
1360
1361 /* Power save for MAC */
1362 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS &&
1363 !rtlhal->driver_going2unload) {
1364 /* enable LED function */
1365 rtl_write_byte(rtlpriv, 0x03, 0xF9);
1366 /* SW/HW radio off or halt adapter!! For example S3/S4 */
1367 } else {
1368 /* LED function disable. Power range is about 8mA now. */
1369 /* if write 0xF1 disconnet_pci power
1370 * ifconfig wlan0 down power are both high 35:70 */
1371 /* if write oxF9 disconnet_pci power
1372 * ifconfig wlan0 down power are both low 12:45*/
1373 rtl_write_byte(rtlpriv, 0x03, 0xF9);
1374 }
1375
1376 rtl_write_byte(rtlpriv, SYS_CLKR + 1, 0x70);
1377 rtl_write_byte(rtlpriv, AFE_PLL_CTRL + 1, 0x68);
1378 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, 0x00);
1379 rtl_write_byte(rtlpriv, LDOA15_CTRL, 0x34);
1380 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL, 0x0E);
1381 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1382
1383 }
1384
1385 static void _rtl92se_gen_refreshledstate(struct ieee80211_hw *hw)
1386 {
1387 struct rtl_priv *rtlpriv = rtl_priv(hw);
1388 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1389 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1390 struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
1391
1392 if (rtlpci->up_first_time == 1)
1393 return;
1394
1395 if (rtlpriv->psc.rfoff_reason == RF_CHANGE_BY_IPS)
1396 rtl92se_sw_led_on(hw, pLed0);
1397 else
1398 rtl92se_sw_led_off(hw, pLed0);
1399 }
1400
1401
1402 static void _rtl92se_power_domain_init(struct ieee80211_hw *hw)
1403 {
1404 struct rtl_priv *rtlpriv = rtl_priv(hw);
1405 u16 tmpu2b;
1406 u8 tmpu1b;
1407
1408 rtlpriv->psc.pwrdomain_protect = true;
1409
1410 tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
1411 if (tmpu1b & BIT(7)) {
1412 tmpu1b &= ~(BIT(6) | BIT(7));
1413 if (!_rtl92s_set_sysclk(hw, tmpu1b)) {
1414 rtlpriv->psc.pwrdomain_protect = false;
1415 return;
1416 }
1417 }
1418
1419 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, 0x0);
1420 rtl_write_byte(rtlpriv, LDOA15_CTRL, 0x34);
1421
1422 /* Reset MAC-IO and CPU and Core Digital BIT10/11/15 */
1423 tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1424
1425 /* If IPS we need to turn LED on. So we not
1426 * not disable BIT 3/7 of reg3. */
1427 if (rtlpriv->psc.rfoff_reason & (RF_CHANGE_BY_IPS | RF_CHANGE_BY_HW))
1428 tmpu1b &= 0xFB;
1429 else
1430 tmpu1b &= 0x73;
1431
1432 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b);
1433 /* wait for BIT 10/11/15 to pull high automatically!! */
1434 mdelay(1);
1435
1436 rtl_write_byte(rtlpriv, CMDR, 0);
1437 rtl_write_byte(rtlpriv, TCR, 0);
1438
1439 /* Data sheet not define 0x562!!! Copy from WMAC!!!!! */
1440 tmpu1b = rtl_read_byte(rtlpriv, 0x562);
1441 tmpu1b |= 0x08;
1442 rtl_write_byte(rtlpriv, 0x562, tmpu1b);
1443 tmpu1b &= ~(BIT(3));
1444 rtl_write_byte(rtlpriv, 0x562, tmpu1b);
1445
1446 /* Enable AFE clock source */
1447 tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL);
1448 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL, (tmpu1b | 0x01));
1449 /* Delay 1.5ms */
1450 udelay(1500);
1451 tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL + 1);
1452 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL + 1, (tmpu1b & 0xfb));
1453
1454 /* Enable AFE Macro Block's Bandgap */
1455 tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC);
1456 rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | BIT(0)));
1457 mdelay(1);
1458
1459 /* Enable AFE Mbias */
1460 tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC);
1461 rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | 0x02));
1462 mdelay(1);
1463
1464 /* Enable LDOA15 block */
1465 tmpu1b = rtl_read_byte(rtlpriv, LDOA15_CTRL);
1466 rtl_write_byte(rtlpriv, LDOA15_CTRL, (tmpu1b | BIT(0)));
1467
1468 /* Set Digital Vdd to Retention isolation Path. */
1469 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_ISO_CTRL);
1470 rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, (tmpu2b | BIT(11)));
1471
1472
1473 /* For warm reboot NIC disappera bug. */
1474 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
1475 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(13)));
1476
1477 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x68);
1478
1479 /* Enable AFE PLL Macro Block */
1480 tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL);
1481 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4)));
1482 /* Enable MAC 80MHZ clock */
1483 tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL + 1);
1484 rtl_write_byte(rtlpriv, AFE_PLL_CTRL + 1, (tmpu1b | BIT(0)));
1485 mdelay(1);
1486
1487 /* Release isolation AFE PLL & MD */
1488 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, 0xA6);
1489
1490 /* Enable MAC clock */
1491 tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR);
1492 rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b | BIT(12) | BIT(11)));
1493
1494 /* Enable Core digital and enable IOREG R/W */
1495 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
1496 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11)));
1497 /* enable REG_EN */
1498 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11) | BIT(15)));
1499
1500 /* Switch the control path. */
1501 tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR);
1502 rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b & (~BIT(2))));
1503
1504 tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
1505 tmpu1b = ((tmpu1b | BIT(7)) & (~BIT(6)));
1506 if (!_rtl92s_set_sysclk(hw, tmpu1b)) {
1507 rtlpriv->psc.pwrdomain_protect = false;
1508 return;
1509 }
1510
1511 rtl_write_word(rtlpriv, CMDR, 0x37FC);
1512
1513 /* After MACIO reset,we must refresh LED state. */
1514 _rtl92se_gen_refreshledstate(hw);
1515
1516 rtlpriv->psc.pwrdomain_protect = false;
1517 }
1518
1519 void rtl92se_card_disable(struct ieee80211_hw *hw)
1520 {
1521 struct rtl_priv *rtlpriv = rtl_priv(hw);
1522 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1523 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1524 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1525 enum nl80211_iftype opmode;
1526 u8 wait = 30;
1527
1528 rtlpriv->intf_ops->enable_aspm(hw);
1529
1530 if (rtlpci->driver_is_goingto_unload ||
1531 ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1532 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1533
1534 /* we should chnge GPIO to input mode
1535 * this will drop away current about 25mA*/
1536 rtl8192se_gpiobit3_cfg_inputmode(hw);
1537
1538 /* this is very important for ips power save */
1539 while (wait-- >= 10 && rtlpriv->psc.pwrdomain_protect) {
1540 if (rtlpriv->psc.pwrdomain_protect)
1541 mdelay(20);
1542 else
1543 break;
1544 }
1545
1546 mac->link_state = MAC80211_NOLINK;
1547 opmode = NL80211_IFTYPE_UNSPECIFIED;
1548 _rtl92se_set_media_status(hw, opmode);
1549
1550 _rtl92s_phy_set_rfhalt(hw);
1551 udelay(100);
1552 }
1553
1554 void rtl92se_interrupt_recognized(struct ieee80211_hw *hw, u32 *p_inta,
1555 u32 *p_intb)
1556 {
1557 struct rtl_priv *rtlpriv = rtl_priv(hw);
1558 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1559
1560 *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1561 rtl_write_dword(rtlpriv, ISR, *p_inta);
1562
1563 *p_intb = rtl_read_dword(rtlpriv, ISR + 4) & rtlpci->irq_mask[1];
1564 rtl_write_dword(rtlpriv, ISR + 4, *p_intb);
1565 }
1566
1567 void rtl92se_set_beacon_related_registers(struct ieee80211_hw *hw)
1568 {
1569 struct rtl_priv *rtlpriv = rtl_priv(hw);
1570 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1571 u16 bcntime_cfg = 0;
1572 u16 bcn_cw = 6, bcn_ifs = 0xf;
1573 u16 atim_window = 2;
1574
1575 /* ATIM Window (in unit of TU). */
1576 rtl_write_word(rtlpriv, ATIMWND, atim_window);
1577
1578 /* Beacon interval (in unit of TU). */
1579 rtl_write_word(rtlpriv, BCN_INTERVAL, mac->beacon_interval);
1580
1581 /* DrvErlyInt (in unit of TU). (Time to send
1582 * interrupt to notify driver to change
1583 * beacon content) */
1584 rtl_write_word(rtlpriv, BCN_DRV_EARLY_INT, 10 << 4);
1585
1586 /* BcnDMATIM(in unit of us). Indicates the
1587 * time before TBTT to perform beacon queue DMA */
1588 rtl_write_word(rtlpriv, BCN_DMATIME, 256);
1589
1590 /* Force beacon frame transmission even
1591 * after receiving beacon frame from
1592 * other ad hoc STA */
1593 rtl_write_byte(rtlpriv, BCN_ERR_THRESH, 100);
1594
1595 /* Beacon Time Configuration */
1596 if (mac->opmode == NL80211_IFTYPE_ADHOC)
1597 bcntime_cfg |= (bcn_cw << BCN_TCFG_CW_SHIFT);
1598
1599 /* TODO: bcn_ifs may required to be changed on ASIC */
1600 bcntime_cfg |= bcn_ifs << BCN_TCFG_IFS;
1601
1602 /*for beacon changed */
1603 rtl92s_phy_set_beacon_hwreg(hw, mac->beacon_interval);
1604 }
1605
1606 void rtl92se_set_beacon_interval(struct ieee80211_hw *hw)
1607 {
1608 struct rtl_priv *rtlpriv = rtl_priv(hw);
1609 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1610 u16 bcn_interval = mac->beacon_interval;
1611
1612 /* Beacon interval (in unit of TU). */
1613 rtl_write_word(rtlpriv, BCN_INTERVAL, bcn_interval);
1614 /* 2008.10.24 added by tynli for beacon changed. */
1615 rtl92s_phy_set_beacon_hwreg(hw, bcn_interval);
1616 }
1617
1618 void rtl92se_update_interrupt_mask(struct ieee80211_hw *hw,
1619 u32 add_msr, u32 rm_msr)
1620 {
1621 struct rtl_priv *rtlpriv = rtl_priv(hw);
1622 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1623
1624 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD, "add_msr:%x, rm_msr:%x\n",
1625 add_msr, rm_msr);
1626
1627 if (add_msr)
1628 rtlpci->irq_mask[0] |= add_msr;
1629
1630 if (rm_msr)
1631 rtlpci->irq_mask[0] &= (~rm_msr);
1632
1633 rtl92se_disable_interrupt(hw);
1634 rtl92se_enable_interrupt(hw);
1635 }
1636
1637 static void _rtl8192se_get_IC_Inferiority(struct ieee80211_hw *hw)
1638 {
1639 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1640 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1641 u8 efuse_id;
1642
1643 rtlhal->ic_class = IC_INFERIORITY_A;
1644
1645 /* Only retrieving while using EFUSE. */
1646 if ((rtlefuse->epromtype == EEPROM_BOOT_EFUSE) &&
1647 !rtlefuse->autoload_failflag) {
1648 efuse_id = efuse_read_1byte(hw, EFUSE_IC_ID_OFFSET);
1649
1650 if (efuse_id == 0xfe)
1651 rtlhal->ic_class = IC_INFERIORITY_B;
1652 }
1653 }
1654
1655 static void _rtl92se_read_adapter_info(struct ieee80211_hw *hw)
1656 {
1657 struct rtl_priv *rtlpriv = rtl_priv(hw);
1658 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1659 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1660 u16 i, usvalue;
1661 u16 eeprom_id;
1662 u8 tempval;
1663 u8 hwinfo[HWSET_MAX_SIZE_92S];
1664 u8 rf_path, index;
1665
1666 if (rtlefuse->epromtype == EEPROM_93C46) {
1667 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1668 "RTL819X Not boot from eeprom, check it !!\n");
1669 } else if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
1670 rtl_efuse_shadow_map_update(hw);
1671
1672 memcpy((void *)hwinfo, (void *)
1673 &rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
1674 HWSET_MAX_SIZE_92S);
1675 }
1676
1677 RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, "MAP",
1678 hwinfo, HWSET_MAX_SIZE_92S);
1679
1680 eeprom_id = *((u16 *)&hwinfo[0]);
1681 if (eeprom_id != RTL8190_EEPROM_ID) {
1682 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1683 "EEPROM ID(%#x) is invalid!!\n", eeprom_id);
1684 rtlefuse->autoload_failflag = true;
1685 } else {
1686 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1687 rtlefuse->autoload_failflag = false;
1688 }
1689
1690 if (rtlefuse->autoload_failflag)
1691 return;
1692
1693 _rtl8192se_get_IC_Inferiority(hw);
1694
1695 /* Read IC Version && Channel Plan */
1696 /* VID, DID SE 0xA-D */
1697 rtlefuse->eeprom_vid = *(u16 *)&hwinfo[EEPROM_VID];
1698 rtlefuse->eeprom_did = *(u16 *)&hwinfo[EEPROM_DID];
1699 rtlefuse->eeprom_svid = *(u16 *)&hwinfo[EEPROM_SVID];
1700 rtlefuse->eeprom_smid = *(u16 *)&hwinfo[EEPROM_SMID];
1701 rtlefuse->eeprom_version = *(u16 *)&hwinfo[EEPROM_VERSION];
1702
1703 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1704 "EEPROMId = 0x%4x\n", eeprom_id);
1705 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1706 "EEPROM VID = 0x%4x\n", rtlefuse->eeprom_vid);
1707 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1708 "EEPROM DID = 0x%4x\n", rtlefuse->eeprom_did);
1709 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1710 "EEPROM SVID = 0x%4x\n", rtlefuse->eeprom_svid);
1711 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1712 "EEPROM SMID = 0x%4x\n", rtlefuse->eeprom_smid);
1713
1714 for (i = 0; i < 6; i += 2) {
1715 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i];
1716 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
1717 }
1718
1719 for (i = 0; i < 6; i++)
1720 rtl_write_byte(rtlpriv, MACIDR0 + i, rtlefuse->dev_addr[i]);
1721
1722 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "%pM\n", rtlefuse->dev_addr);
1723
1724 /* Get Tx Power Level by Channel */
1725 /* Read Tx power of Channel 1 ~ 14 from EEPROM. */
1726 /* 92S suupport RF A & B */
1727 for (rf_path = 0; rf_path < 2; rf_path++) {
1728 for (i = 0; i < 3; i++) {
1729 /* Read CCK RF A & B Tx power */
1730 rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][i] =
1731 hwinfo[EEPROM_TXPOWERBASE + rf_path * 3 + i];
1732
1733 /* Read OFDM RF A & B Tx power for 1T */
1734 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
1735 hwinfo[EEPROM_TXPOWERBASE + 6 + rf_path * 3 + i];
1736
1737 /* Read OFDM RF A & B Tx power for 2T */
1738 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[rf_path][i]
1739 = hwinfo[EEPROM_TXPOWERBASE + 12 +
1740 rf_path * 3 + i];
1741 }
1742 }
1743
1744 for (rf_path = 0; rf_path < 2; rf_path++)
1745 for (i = 0; i < 3; i++)
1746 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1747 "RF(%d) EEPROM CCK Area(%d) = 0x%x\n",
1748 rf_path, i,
1749 rtlefuse->eeprom_chnlarea_txpwr_cck
1750 [rf_path][i]);
1751 for (rf_path = 0; rf_path < 2; rf_path++)
1752 for (i = 0; i < 3; i++)
1753 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1754 "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
1755 rf_path, i,
1756 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1757 [rf_path][i]);
1758 for (rf_path = 0; rf_path < 2; rf_path++)
1759 for (i = 0; i < 3; i++)
1760 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1761 "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
1762 rf_path, i,
1763 rtlefuse->eprom_chnl_txpwr_ht40_2sdf
1764 [rf_path][i]);
1765
1766 for (rf_path = 0; rf_path < 2; rf_path++) {
1767
1768 /* Assign dedicated channel tx power */
1769 for (i = 0; i < 14; i++) {
1770 /* channel 1~3 use the same Tx Power Level. */
1771 if (i < 3)
1772 index = 0;
1773 /* Channel 4-8 */
1774 else if (i < 8)
1775 index = 1;
1776 /* Channel 9-14 */
1777 else
1778 index = 2;
1779
1780 /* Record A & B CCK /OFDM - 1T/2T Channel area
1781 * tx power */
1782 rtlefuse->txpwrlevel_cck[rf_path][i] =
1783 rtlefuse->eeprom_chnlarea_txpwr_cck
1784 [rf_path][index];
1785 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
1786 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1787 [rf_path][index];
1788 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] =
1789 rtlefuse->eprom_chnl_txpwr_ht40_2sdf
1790 [rf_path][index];
1791 }
1792
1793 for (i = 0; i < 14; i++) {
1794 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1795 "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n",
1796 rf_path, i,
1797 rtlefuse->txpwrlevel_cck[rf_path][i],
1798 rtlefuse->txpwrlevel_ht40_1s[rf_path][i],
1799 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]);
1800 }
1801 }
1802
1803 for (rf_path = 0; rf_path < 2; rf_path++) {
1804 for (i = 0; i < 3; i++) {
1805 /* Read Power diff limit. */
1806 rtlefuse->eeprom_pwrgroup[rf_path][i] =
1807 hwinfo[EEPROM_TXPWRGROUP + rf_path * 3 + i];
1808 }
1809 }
1810
1811 for (rf_path = 0; rf_path < 2; rf_path++) {
1812 /* Fill Pwr group */
1813 for (i = 0; i < 14; i++) {
1814 /* Chanel 1-3 */
1815 if (i < 3)
1816 index = 0;
1817 /* Channel 4-8 */
1818 else if (i < 8)
1819 index = 1;
1820 /* Channel 9-13 */
1821 else
1822 index = 2;
1823
1824 rtlefuse->pwrgroup_ht20[rf_path][i] =
1825 (rtlefuse->eeprom_pwrgroup[rf_path][index] &
1826 0xf);
1827 rtlefuse->pwrgroup_ht40[rf_path][i] =
1828 ((rtlefuse->eeprom_pwrgroup[rf_path][index] &
1829 0xf0) >> 4);
1830
1831 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1832 "RF-%d pwrgroup_ht20[%d] = 0x%x\n",
1833 rf_path, i,
1834 rtlefuse->pwrgroup_ht20[rf_path][i]);
1835 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1836 "RF-%d pwrgroup_ht40[%d] = 0x%x\n",
1837 rf_path, i,
1838 rtlefuse->pwrgroup_ht40[rf_path][i]);
1839 }
1840 }
1841
1842 for (i = 0; i < 14; i++) {
1843 /* Read tx power difference between HT OFDM 20/40 MHZ */
1844 /* channel 1-3 */
1845 if (i < 3)
1846 index = 0;
1847 /* Channel 4-8 */
1848 else if (i < 8)
1849 index = 1;
1850 /* Channel 9-14 */
1851 else
1852 index = 2;
1853
1854 tempval = hwinfo[EEPROM_TX_PWR_HT20_DIFF + index] & 0xff;
1855 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF);
1856 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] =
1857 ((tempval >> 4) & 0xF);
1858
1859 /* Read OFDM<->HT tx power diff */
1860 /* Channel 1-3 */
1861 if (i < 3)
1862 index = 0;
1863 /* Channel 4-8 */
1864 else if (i < 8)
1865 index = 0x11;
1866 /* Channel 9-14 */
1867 else
1868 index = 1;
1869
1870 tempval = hwinfo[EEPROM_TX_PWR_OFDM_DIFF + index] & 0xff;
1871 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] =
1872 (tempval & 0xF);
1873 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] =
1874 ((tempval >> 4) & 0xF);
1875
1876 tempval = hwinfo[TX_PWR_SAFETY_CHK];
1877 rtlefuse->txpwr_safetyflag = (tempval & 0x01);
1878 }
1879
1880 rtlefuse->eeprom_regulatory = 0;
1881 if (rtlefuse->eeprom_version >= 2) {
1882 /* BIT(0)~2 */
1883 if (rtlefuse->eeprom_version >= 4)
1884 rtlefuse->eeprom_regulatory =
1885 (hwinfo[EEPROM_REGULATORY] & 0x7);
1886 else /* BIT(0) */
1887 rtlefuse->eeprom_regulatory =
1888 (hwinfo[EEPROM_REGULATORY] & 0x1);
1889 }
1890 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1891 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
1892
1893 for (i = 0; i < 14; i++)
1894 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1895 "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n",
1896 i, rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]);
1897 for (i = 0; i < 14; i++)
1898 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1899 "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n",
1900 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]);
1901 for (i = 0; i < 14; i++)
1902 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1903 "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n",
1904 i, rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]);
1905 for (i = 0; i < 14; i++)
1906 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1907 "RF-B Legacy to HT40 Diff[%d] = 0x%x\n",
1908 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]);
1909
1910 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1911 "TxPwrSafetyFlag = %d\n", rtlefuse->txpwr_safetyflag);
1912
1913 /* Read RF-indication and Tx Power gain
1914 * index diff of legacy to HT OFDM rate. */
1915 tempval = hwinfo[EEPROM_RFIND_POWERDIFF] & 0xff;
1916 rtlefuse->eeprom_txpowerdiff = tempval;
1917 rtlefuse->legacy_httxpowerdiff =
1918 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][0];
1919
1920 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1921 "TxPowerDiff = %#x\n", rtlefuse->eeprom_txpowerdiff);
1922
1923 /* Get TSSI value for each path. */
1924 usvalue = *(u16 *)&hwinfo[EEPROM_TSSI_A];
1925 rtlefuse->eeprom_tssi[RF90_PATH_A] = (u8)((usvalue & 0xff00) >> 8);
1926 usvalue = hwinfo[EEPROM_TSSI_B];
1927 rtlefuse->eeprom_tssi[RF90_PATH_B] = (u8)(usvalue & 0xff);
1928
1929 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, "TSSI_A = 0x%x, TSSI_B = 0x%x\n",
1930 rtlefuse->eeprom_tssi[RF90_PATH_A],
1931 rtlefuse->eeprom_tssi[RF90_PATH_B]);
1932
1933 /* Read antenna tx power offset of B/C/D to A from EEPROM */
1934 /* and read ThermalMeter from EEPROM */
1935 tempval = hwinfo[EEPROM_THERMALMETER];
1936 rtlefuse->eeprom_thermalmeter = tempval;
1937 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1938 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
1939
1940 /* ThermalMeter, BIT(0)~3 for RFIC1, BIT(4)~7 for RFIC2 */
1941 rtlefuse->thermalmeter[0] = (rtlefuse->eeprom_thermalmeter & 0x1f);
1942 rtlefuse->tssi_13dbm = rtlefuse->eeprom_thermalmeter * 100;
1943
1944 /* Read CrystalCap from EEPROM */
1945 tempval = hwinfo[EEPROM_CRYSTALCAP] >> 4;
1946 rtlefuse->eeprom_crystalcap = tempval;
1947 /* CrystalCap, BIT(12)~15 */
1948 rtlefuse->crystalcap = rtlefuse->eeprom_crystalcap;
1949
1950 /* Read IC Version && Channel Plan */
1951 /* Version ID, Channel plan */
1952 rtlefuse->eeprom_channelplan = hwinfo[EEPROM_CHANNELPLAN];
1953 rtlefuse->txpwr_fromeprom = true;
1954 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1955 "EEPROM ChannelPlan = 0x%4x\n", rtlefuse->eeprom_channelplan);
1956
1957 /* Read Customer ID or Board Type!!! */
1958 tempval = hwinfo[EEPROM_BOARDTYPE];
1959 /* Change RF type definition */
1960 if (tempval == 0)
1961 rtlphy->rf_type = RF_2T2R;
1962 else if (tempval == 1)
1963 rtlphy->rf_type = RF_1T2R;
1964 else if (tempval == 2)
1965 rtlphy->rf_type = RF_1T2R;
1966 else if (tempval == 3)
1967 rtlphy->rf_type = RF_1T1R;
1968
1969 /* 1T2R but 1SS (1x1 receive combining) */
1970 rtlefuse->b1x1_recvcombine = false;
1971 if (rtlphy->rf_type == RF_1T2R) {
1972 tempval = rtl_read_byte(rtlpriv, 0x07);
1973 if (!(tempval & BIT(0))) {
1974 rtlefuse->b1x1_recvcombine = true;
1975 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1976 "RF_TYPE=1T2R but only 1SS\n");
1977 }
1978 }
1979 rtlefuse->b1ss_support = rtlefuse->b1x1_recvcombine;
1980 rtlefuse->eeprom_oemid = *&hwinfo[EEPROM_CUSTOMID];
1981
1982 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "EEPROM Customer ID: 0x%2x",
1983 rtlefuse->eeprom_oemid);
1984
1985 /* set channel paln to world wide 13 */
1986 rtlefuse->channel_plan = COUNTRY_CODE_WORLD_WIDE_13;
1987 }
1988
1989 void rtl92se_read_eeprom_info(struct ieee80211_hw *hw)
1990 {
1991 struct rtl_priv *rtlpriv = rtl_priv(hw);
1992 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1993 u8 tmp_u1b = 0;
1994
1995 tmp_u1b = rtl_read_byte(rtlpriv, EPROM_CMD);
1996
1997 if (tmp_u1b & BIT(4)) {
1998 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
1999 rtlefuse->epromtype = EEPROM_93C46;
2000 } else {
2001 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
2002 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
2003 }
2004
2005 if (tmp_u1b & BIT(5)) {
2006 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
2007 rtlefuse->autoload_failflag = false;
2008 _rtl92se_read_adapter_info(hw);
2009 } else {
2010 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Autoload ERR!!\n");
2011 rtlefuse->autoload_failflag = true;
2012 }
2013 }
2014
2015 static void rtl92se_update_hal_rate_table(struct ieee80211_hw *hw,
2016 struct ieee80211_sta *sta)
2017 {
2018 struct rtl_priv *rtlpriv = rtl_priv(hw);
2019 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2020 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2021 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2022 u32 ratr_value;
2023 u8 ratr_index = 0;
2024 u8 nmode = mac->ht_enable;
2025 u8 mimo_ps = IEEE80211_SMPS_OFF;
2026 u16 shortgi_rate = 0;
2027 u32 tmp_ratr_value = 0;
2028 u8 curtxbw_40mhz = mac->bw_40;
2029 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2030 1 : 0;
2031 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2032 1 : 0;
2033 enum wireless_mode wirelessmode = mac->mode;
2034
2035 if (rtlhal->current_bandtype == BAND_ON_5G)
2036 ratr_value = sta->supp_rates[1] << 4;
2037 else
2038 ratr_value = sta->supp_rates[0];
2039 if (mac->opmode == NL80211_IFTYPE_ADHOC)
2040 ratr_value = 0xfff;
2041 ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2042 sta->ht_cap.mcs.rx_mask[0] << 12);
2043 switch (wirelessmode) {
2044 case WIRELESS_MODE_B:
2045 ratr_value &= 0x0000000D;
2046 break;
2047 case WIRELESS_MODE_G:
2048 ratr_value &= 0x00000FF5;
2049 break;
2050 case WIRELESS_MODE_N_24G:
2051 case WIRELESS_MODE_N_5G:
2052 nmode = 1;
2053 if (mimo_ps == IEEE80211_SMPS_STATIC) {
2054 ratr_value &= 0x0007F005;
2055 } else {
2056 u32 ratr_mask;
2057
2058 if (get_rf_type(rtlphy) == RF_1T2R ||
2059 get_rf_type(rtlphy) == RF_1T1R) {
2060 if (curtxbw_40mhz)
2061 ratr_mask = 0x000ff015;
2062 else
2063 ratr_mask = 0x000ff005;
2064 } else {
2065 if (curtxbw_40mhz)
2066 ratr_mask = 0x0f0ff015;
2067 else
2068 ratr_mask = 0x0f0ff005;
2069 }
2070
2071 ratr_value &= ratr_mask;
2072 }
2073 break;
2074 default:
2075 if (rtlphy->rf_type == RF_1T2R)
2076 ratr_value &= 0x000ff0ff;
2077 else
2078 ratr_value &= 0x0f0ff0ff;
2079
2080 break;
2081 }
2082
2083 if (rtlpriv->rtlhal.version >= VERSION_8192S_BCUT)
2084 ratr_value &= 0x0FFFFFFF;
2085 else if (rtlpriv->rtlhal.version == VERSION_8192S_ACUT)
2086 ratr_value &= 0x0FFFFFF0;
2087
2088 if (nmode && ((curtxbw_40mhz &&
2089 curshortgi_40mhz) || (!curtxbw_40mhz &&
2090 curshortgi_20mhz))) {
2091
2092 ratr_value |= 0x10000000;
2093 tmp_ratr_value = (ratr_value >> 12);
2094
2095 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
2096 if ((1 << shortgi_rate) & tmp_ratr_value)
2097 break;
2098 }
2099
2100 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
2101 (shortgi_rate << 4) | (shortgi_rate);
2102
2103 rtl_write_byte(rtlpriv, SG_RATE, shortgi_rate);
2104 }
2105
2106 rtl_write_dword(rtlpriv, ARFR0 + ratr_index * 4, ratr_value);
2107 if (ratr_value & 0xfffff000)
2108 rtl92s_phy_set_fw_cmd(hw, FW_CMD_RA_REFRESH_N);
2109 else
2110 rtl92s_phy_set_fw_cmd(hw, FW_CMD_RA_REFRESH_BG);
2111
2112 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n",
2113 rtl_read_dword(rtlpriv, ARFR0));
2114 }
2115
2116 static void rtl92se_update_hal_rate_mask(struct ieee80211_hw *hw,
2117 struct ieee80211_sta *sta,
2118 u8 rssi_level)
2119 {
2120 struct rtl_priv *rtlpriv = rtl_priv(hw);
2121 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2122 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2123 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2124 struct rtl_sta_info *sta_entry = NULL;
2125 u32 ratr_bitmap;
2126 u8 ratr_index = 0;
2127 u8 curtxbw_40mhz = (sta->bandwidth >= IEEE80211_STA_RX_BW_40) ? 1 : 0;
2128 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2129 1 : 0;
2130 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2131 1 : 0;
2132 enum wireless_mode wirelessmode = 0;
2133 bool shortgi = false;
2134 u32 ratr_value = 0;
2135 u8 shortgi_rate = 0;
2136 u32 mask = 0;
2137 u32 band = 0;
2138 bool bmulticast = false;
2139 u8 macid = 0;
2140 u8 mimo_ps = IEEE80211_SMPS_OFF;
2141
2142 sta_entry = (struct rtl_sta_info *) sta->drv_priv;
2143 wirelessmode = sta_entry->wireless_mode;
2144 if (mac->opmode == NL80211_IFTYPE_STATION)
2145 curtxbw_40mhz = mac->bw_40;
2146 else if (mac->opmode == NL80211_IFTYPE_AP ||
2147 mac->opmode == NL80211_IFTYPE_ADHOC)
2148 macid = sta->aid + 1;
2149
2150 if (rtlhal->current_bandtype == BAND_ON_5G)
2151 ratr_bitmap = sta->supp_rates[1] << 4;
2152 else
2153 ratr_bitmap = sta->supp_rates[0];
2154 if (mac->opmode == NL80211_IFTYPE_ADHOC)
2155 ratr_bitmap = 0xfff;
2156 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2157 sta->ht_cap.mcs.rx_mask[0] << 12);
2158 switch (wirelessmode) {
2159 case WIRELESS_MODE_B:
2160 band |= WIRELESS_11B;
2161 ratr_index = RATR_INX_WIRELESS_B;
2162 if (ratr_bitmap & 0x0000000c)
2163 ratr_bitmap &= 0x0000000d;
2164 else
2165 ratr_bitmap &= 0x0000000f;
2166 break;
2167 case WIRELESS_MODE_G:
2168 band |= (WIRELESS_11G | WIRELESS_11B);
2169 ratr_index = RATR_INX_WIRELESS_GB;
2170
2171 if (rssi_level == 1)
2172 ratr_bitmap &= 0x00000f00;
2173 else if (rssi_level == 2)
2174 ratr_bitmap &= 0x00000ff0;
2175 else
2176 ratr_bitmap &= 0x00000ff5;
2177 break;
2178 case WIRELESS_MODE_A:
2179 band |= WIRELESS_11A;
2180 ratr_index = RATR_INX_WIRELESS_A;
2181 ratr_bitmap &= 0x00000ff0;
2182 break;
2183 case WIRELESS_MODE_N_24G:
2184 case WIRELESS_MODE_N_5G:
2185 band |= (WIRELESS_11N | WIRELESS_11G | WIRELESS_11B);
2186 ratr_index = RATR_INX_WIRELESS_NGB;
2187
2188 if (mimo_ps == IEEE80211_SMPS_STATIC) {
2189 if (rssi_level == 1)
2190 ratr_bitmap &= 0x00070000;
2191 else if (rssi_level == 2)
2192 ratr_bitmap &= 0x0007f000;
2193 else
2194 ratr_bitmap &= 0x0007f005;
2195 } else {
2196 if (rtlphy->rf_type == RF_1T2R ||
2197 rtlphy->rf_type == RF_1T1R) {
2198 if (rssi_level == 1) {
2199 ratr_bitmap &= 0x000f0000;
2200 } else if (rssi_level == 3) {
2201 ratr_bitmap &= 0x000fc000;
2202 } else if (rssi_level == 5) {
2203 ratr_bitmap &= 0x000ff000;
2204 } else {
2205 if (curtxbw_40mhz)
2206 ratr_bitmap &= 0x000ff015;
2207 else
2208 ratr_bitmap &= 0x000ff005;
2209 }
2210 } else {
2211 if (rssi_level == 1) {
2212 ratr_bitmap &= 0x0f8f0000;
2213 } else if (rssi_level == 3) {
2214 ratr_bitmap &= 0x0f8fc000;
2215 } else if (rssi_level == 5) {
2216 ratr_bitmap &= 0x0f8ff000;
2217 } else {
2218 if (curtxbw_40mhz)
2219 ratr_bitmap &= 0x0f8ff015;
2220 else
2221 ratr_bitmap &= 0x0f8ff005;
2222 }
2223 }
2224 }
2225
2226 if ((curtxbw_40mhz && curshortgi_40mhz) ||
2227 (!curtxbw_40mhz && curshortgi_20mhz)) {
2228 if (macid == 0)
2229 shortgi = true;
2230 else if (macid == 1)
2231 shortgi = false;
2232 }
2233 break;
2234 default:
2235 band |= (WIRELESS_11N | WIRELESS_11G | WIRELESS_11B);
2236 ratr_index = RATR_INX_WIRELESS_NGB;
2237
2238 if (rtlphy->rf_type == RF_1T2R)
2239 ratr_bitmap &= 0x000ff0ff;
2240 else
2241 ratr_bitmap &= 0x0f8ff0ff;
2242 break;
2243 }
2244 sta_entry->ratr_index = ratr_index;
2245
2246 if (rtlpriv->rtlhal.version >= VERSION_8192S_BCUT)
2247 ratr_bitmap &= 0x0FFFFFFF;
2248 else if (rtlpriv->rtlhal.version == VERSION_8192S_ACUT)
2249 ratr_bitmap &= 0x0FFFFFF0;
2250
2251 if (shortgi) {
2252 ratr_bitmap |= 0x10000000;
2253 /* Get MAX MCS available. */
2254 ratr_value = (ratr_bitmap >> 12);
2255 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
2256 if ((1 << shortgi_rate) & ratr_value)
2257 break;
2258 }
2259
2260 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
2261 (shortgi_rate << 4) | (shortgi_rate);
2262 rtl_write_byte(rtlpriv, SG_RATE, shortgi_rate);
2263 }
2264
2265 mask |= (bmulticast ? 1 : 0) << 9 | (macid & 0x1f) << 4 | (band & 0xf);
2266
2267 RT_TRACE(rtlpriv, COMP_RATR, DBG_TRACE, "mask = %x, bitmap = %x\n",
2268 mask, ratr_bitmap);
2269 rtl_write_dword(rtlpriv, 0x2c4, ratr_bitmap);
2270 rtl_write_dword(rtlpriv, WFM5, (FW_RA_UPDATE_MASK | (mask << 8)));
2271
2272 if (macid != 0)
2273 sta_entry->ratr_index = ratr_index;
2274 }
2275
2276 void rtl92se_update_hal_rate_tbl(struct ieee80211_hw *hw,
2277 struct ieee80211_sta *sta, u8 rssi_level)
2278 {
2279 struct rtl_priv *rtlpriv = rtl_priv(hw);
2280
2281 if (rtlpriv->dm.useramask)
2282 rtl92se_update_hal_rate_mask(hw, sta, rssi_level);
2283 else
2284 rtl92se_update_hal_rate_table(hw, sta);
2285 }
2286
2287 void rtl92se_update_channel_access_setting(struct ieee80211_hw *hw)
2288 {
2289 struct rtl_priv *rtlpriv = rtl_priv(hw);
2290 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2291 u16 sifs_timer;
2292
2293 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
2294 &mac->slot_time);
2295 sifs_timer = 0x0e0e;
2296 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2297
2298 }
2299
2300 /* this ifunction is for RFKILL, it's different with windows,
2301 * because UI will disable wireless when GPIO Radio Off.
2302 * And here we not check or Disable/Enable ASPM like windows*/
2303 bool rtl92se_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2304 {
2305 struct rtl_priv *rtlpriv = rtl_priv(hw);
2306 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2307 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2308 enum rf_pwrstate rfpwr_toset /*, cur_rfstate */;
2309 unsigned long flag = 0;
2310 bool actuallyset = false;
2311 bool turnonbypowerdomain = false;
2312
2313 /* just 8191se can check gpio before firstup, 92c/92d have fixed it */
2314 if ((rtlpci->up_first_time == 1) || (rtlpci->being_init_adapter))
2315 return false;
2316
2317 if (ppsc->swrf_processing)
2318 return false;
2319
2320 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2321 if (ppsc->rfchange_inprogress) {
2322 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2323 return false;
2324 } else {
2325 ppsc->rfchange_inprogress = true;
2326 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2327 }
2328
2329 /* cur_rfstate = ppsc->rfpwr_state;*/
2330
2331 /* because after _rtl92s_phy_set_rfhalt, all power
2332 * closed, so we must open some power for GPIO check,
2333 * or we will always check GPIO RFOFF here,
2334 * And we should close power after GPIO check */
2335 if (RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
2336 _rtl92se_power_domain_init(hw);
2337 turnonbypowerdomain = true;
2338 }
2339
2340 rfpwr_toset = _rtl92se_rf_onoff_detect(hw);
2341
2342 if ((ppsc->hwradiooff) && (rfpwr_toset == ERFON)) {
2343 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2344 "RFKILL-HW Radio ON, RF ON\n");
2345
2346 rfpwr_toset = ERFON;
2347 ppsc->hwradiooff = false;
2348 actuallyset = true;
2349 } else if ((!ppsc->hwradiooff) && (rfpwr_toset == ERFOFF)) {
2350 RT_TRACE(rtlpriv, COMP_RF,
2351 DBG_DMESG, "RFKILL-HW Radio OFF, RF OFF\n");
2352
2353 rfpwr_toset = ERFOFF;
2354 ppsc->hwradiooff = true;
2355 actuallyset = true;
2356 }
2357
2358 if (actuallyset) {
2359 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2360 ppsc->rfchange_inprogress = false;
2361 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2362
2363 /* this not include ifconfig wlan0 down case */
2364 /* } else if (rfpwr_toset == ERFOFF || cur_rfstate == ERFOFF) { */
2365 } else {
2366 /* because power_domain_init may be happen when
2367 * _rtl92s_phy_set_rfhalt, this will open some powers
2368 * and cause current increasing about 40 mA for ips,
2369 * rfoff and ifconfig down, so we set
2370 * _rtl92s_phy_set_rfhalt again here */
2371 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC &&
2372 turnonbypowerdomain) {
2373 _rtl92s_phy_set_rfhalt(hw);
2374 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2375 }
2376
2377 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2378 ppsc->rfchange_inprogress = false;
2379 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2380 }
2381
2382 *valid = 1;
2383 return !ppsc->hwradiooff;
2384
2385 }
2386
2387 /* Is_wepkey just used for WEP used as group & pairwise key
2388 * if pairwise is AES ang group is WEP Is_wepkey == false.*/
2389 void rtl92se_set_key(struct ieee80211_hw *hw, u32 key_index, u8 *p_macaddr,
2390 bool is_group, u8 enc_algo, bool is_wepkey, bool clear_all)
2391 {
2392 struct rtl_priv *rtlpriv = rtl_priv(hw);
2393 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2394 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2395 u8 *macaddr = p_macaddr;
2396
2397 u32 entry_id = 0;
2398 bool is_pairwise = false;
2399
2400 static u8 cam_const_addr[4][6] = {
2401 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2402 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2403 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2404 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2405 };
2406 static u8 cam_const_broad[] = {
2407 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2408 };
2409
2410 if (clear_all) {
2411 u8 idx = 0;
2412 u8 cam_offset = 0;
2413 u8 clear_number = 5;
2414
2415 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
2416
2417 for (idx = 0; idx < clear_number; idx++) {
2418 rtl_cam_mark_invalid(hw, cam_offset + idx);
2419 rtl_cam_empty_entry(hw, cam_offset + idx);
2420
2421 if (idx < 5) {
2422 memset(rtlpriv->sec.key_buf[idx], 0,
2423 MAX_KEY_LEN);
2424 rtlpriv->sec.key_len[idx] = 0;
2425 }
2426 }
2427
2428 } else {
2429 switch (enc_algo) {
2430 case WEP40_ENCRYPTION:
2431 enc_algo = CAM_WEP40;
2432 break;
2433 case WEP104_ENCRYPTION:
2434 enc_algo = CAM_WEP104;
2435 break;
2436 case TKIP_ENCRYPTION:
2437 enc_algo = CAM_TKIP;
2438 break;
2439 case AESCCMP_ENCRYPTION:
2440 enc_algo = CAM_AES;
2441 break;
2442 default:
2443 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2444 "switch case not processed\n");
2445 enc_algo = CAM_TKIP;
2446 break;
2447 }
2448
2449 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2450 macaddr = cam_const_addr[key_index];
2451 entry_id = key_index;
2452 } else {
2453 if (is_group) {
2454 macaddr = cam_const_broad;
2455 entry_id = key_index;
2456 } else {
2457 if (mac->opmode == NL80211_IFTYPE_AP) {
2458 entry_id = rtl_cam_get_free_entry(hw,
2459 p_macaddr);
2460 if (entry_id >= TOTAL_CAM_ENTRY) {
2461 RT_TRACE(rtlpriv,
2462 COMP_SEC, DBG_EMERG,
2463 "Can not find free hw security cam entry\n");
2464 return;
2465 }
2466 } else {
2467 entry_id = CAM_PAIRWISE_KEY_POSITION;
2468 }
2469
2470 key_index = PAIRWISE_KEYIDX;
2471 is_pairwise = true;
2472 }
2473 }
2474
2475 if (rtlpriv->sec.key_len[key_index] == 0) {
2476 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2477 "delete one entry, entry_id is %d\n",
2478 entry_id);
2479 if (mac->opmode == NL80211_IFTYPE_AP)
2480 rtl_cam_del_entry(hw, p_macaddr);
2481 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2482 } else {
2483 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2484 "add one entry\n");
2485 if (is_pairwise) {
2486 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2487 "set Pairwise key\n");
2488
2489 rtl_cam_add_one_entry(hw, macaddr, key_index,
2490 entry_id, enc_algo,
2491 CAM_CONFIG_NO_USEDK,
2492 rtlpriv->sec.key_buf[key_index]);
2493 } else {
2494 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2495 "set group key\n");
2496
2497 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2498 rtl_cam_add_one_entry(hw,
2499 rtlefuse->dev_addr,
2500 PAIRWISE_KEYIDX,
2501 CAM_PAIRWISE_KEY_POSITION,
2502 enc_algo, CAM_CONFIG_NO_USEDK,
2503 rtlpriv->sec.key_buf[entry_id]);
2504 }
2505
2506 rtl_cam_add_one_entry(hw, macaddr, key_index,
2507 entry_id, enc_algo,
2508 CAM_CONFIG_NO_USEDK,
2509 rtlpriv->sec.key_buf[entry_id]);
2510 }
2511
2512 }
2513 }
2514 }
2515
2516 void rtl92se_suspend(struct ieee80211_hw *hw)
2517 {
2518 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2519
2520 rtlpci->up_first_time = true;
2521 }
2522
2523 void rtl92se_resume(struct ieee80211_hw *hw)
2524 {
2525 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2526 u32 val;
2527
2528 pci_read_config_dword(rtlpci->pdev, 0x40, &val);
2529 if ((val & 0x0000ff00) != 0)
2530 pci_write_config_dword(rtlpci->pdev, 0x40,
2531 val & 0xffff00ff);
2532 }
2533
2534 /* Turn on AAP (RCR:bit 0) for promicuous mode. */
2535 void rtl92se_allow_all_destaddr(struct ieee80211_hw *hw,
2536 bool allow_all_da, bool write_into_reg)
2537 {
2538 struct rtl_priv *rtlpriv = rtl_priv(hw);
2539 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2540
2541 if (allow_all_da) /* Set BIT0 */
2542 rtlpci->receive_config |= RCR_AAP;
2543 else /* Clear BIT0 */
2544 rtlpci->receive_config &= ~RCR_AAP;
2545
2546 if (write_into_reg)
2547 rtl_write_dword(rtlpriv, RCR, rtlpci->receive_config);
2548
2549 RT_TRACE(rtlpriv, COMP_TURBO | COMP_INIT, DBG_LOUD,
2550 "receive_config=0x%08X, write_into_reg=%d\n",
2551 rtlpci->receive_config, write_into_reg);
2552 }
Linux kernel - Deliverables
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