1 /******************************************************************************
3 * Copyright(c) 2009-2012 Realtek Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
26 * Larry Finger <Larry.Finger@lwfinger.net>
28 *****************************************************************************/
42 static u32
_rtl92s_phy_calculate_bit_shift(u32 bitmask
)
46 for (i
= 0; i
<= 31; i
++) {
47 if (((bitmask
>> i
) & 0x1) == 1)
54 u32
rtl92s_phy_query_bb_reg(struct ieee80211_hw
*hw
, u32 regaddr
, u32 bitmask
)
56 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
57 u32 returnvalue
= 0, originalvalue
, bitshift
;
59 RT_TRACE(rtlpriv
, COMP_RF
, DBG_TRACE
, "regaddr(%#x), bitmask(%#x)\n",
62 originalvalue
= rtl_read_dword(rtlpriv
, regaddr
);
63 bitshift
= _rtl92s_phy_calculate_bit_shift(bitmask
);
64 returnvalue
= (originalvalue
& bitmask
) >> bitshift
;
66 RT_TRACE(rtlpriv
, COMP_RF
, DBG_TRACE
, "BBR MASK=0x%x Addr[0x%x]=0x%x\n",
67 bitmask
, regaddr
, originalvalue
);
73 void rtl92s_phy_set_bb_reg(struct ieee80211_hw
*hw
, u32 regaddr
, u32 bitmask
,
76 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
77 u32 originalvalue
, bitshift
;
79 RT_TRACE(rtlpriv
, COMP_RF
, DBG_TRACE
,
80 "regaddr(%#x), bitmask(%#x), data(%#x)\n",
81 regaddr
, bitmask
, data
);
83 if (bitmask
!= MASKDWORD
) {
84 originalvalue
= rtl_read_dword(rtlpriv
, regaddr
);
85 bitshift
= _rtl92s_phy_calculate_bit_shift(bitmask
);
86 data
= ((originalvalue
& (~bitmask
)) | (data
<< bitshift
));
89 rtl_write_dword(rtlpriv
, regaddr
, data
);
91 RT_TRACE(rtlpriv
, COMP_RF
, DBG_TRACE
,
92 "regaddr(%#x), bitmask(%#x), data(%#x)\n",
93 regaddr
, bitmask
, data
);
97 static u32
_rtl92s_phy_rf_serial_read(struct ieee80211_hw
*hw
,
98 enum radio_path rfpath
, u32 offset
)
101 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
102 struct rtl_phy
*rtlphy
= &(rtlpriv
->phy
);
103 struct bb_reg_def
*pphyreg
= &rtlphy
->phyreg_def
[rfpath
];
105 u32 tmplong
, tmplong2
;
112 tmplong
= rtl_get_bbreg(hw
, RFPGA0_XA_HSSIPARAMETER2
, MASKDWORD
);
114 if (rfpath
== RF90_PATH_A
)
117 tmplong2
= rtl_get_bbreg(hw
, pphyreg
->rfhssi_para2
, MASKDWORD
);
119 tmplong2
= (tmplong2
& (~BLSSI_READADDRESS
)) | (newoffset
<< 23) |
122 rtl_set_bbreg(hw
, RFPGA0_XA_HSSIPARAMETER2
, MASKDWORD
,
123 tmplong
& (~BLSSI_READEDGE
));
127 rtl_set_bbreg(hw
, pphyreg
->rfhssi_para2
, MASKDWORD
, tmplong2
);
130 rtl_set_bbreg(hw
, RFPGA0_XA_HSSIPARAMETER2
, MASKDWORD
, tmplong
|
134 if (rfpath
== RF90_PATH_A
)
135 rfpi_enable
= (u8
)rtl_get_bbreg(hw
, RFPGA0_XA_HSSIPARAMETER1
,
137 else if (rfpath
== RF90_PATH_B
)
138 rfpi_enable
= (u8
)rtl_get_bbreg(hw
, RFPGA0_XB_HSSIPARAMETER1
,
142 retvalue
= rtl_get_bbreg(hw
, pphyreg
->rflssi_readbackpi
,
143 BLSSI_READBACK_DATA
);
145 retvalue
= rtl_get_bbreg(hw
, pphyreg
->rflssi_readback
,
146 BLSSI_READBACK_DATA
);
148 retvalue
= rtl_get_bbreg(hw
, pphyreg
->rflssi_readback
,
149 BLSSI_READBACK_DATA
);
151 RT_TRACE(rtlpriv
, COMP_RF
, DBG_TRACE
, "RFR-%d Addr[0x%x]=0x%x\n",
152 rfpath
, pphyreg
->rflssi_readback
, retvalue
);
158 static void _rtl92s_phy_rf_serial_write(struct ieee80211_hw
*hw
,
159 enum radio_path rfpath
, u32 offset
,
162 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
163 struct rtl_phy
*rtlphy
= &(rtlpriv
->phy
);
164 struct bb_reg_def
*pphyreg
= &rtlphy
->phyreg_def
[rfpath
];
165 u32 data_and_addr
= 0;
171 data_and_addr
= ((newoffset
<< 20) | (data
& 0x000fffff)) & 0x0fffffff;
172 rtl_set_bbreg(hw
, pphyreg
->rf3wire_offset
, MASKDWORD
, data_and_addr
);
174 RT_TRACE(rtlpriv
, COMP_RF
, DBG_TRACE
, "RFW-%d Addr[0x%x]=0x%x\n",
175 rfpath
, pphyreg
->rf3wire_offset
, data_and_addr
);
179 u32
rtl92s_phy_query_rf_reg(struct ieee80211_hw
*hw
, enum radio_path rfpath
,
180 u32 regaddr
, u32 bitmask
)
182 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
183 u32 original_value
, readback_value
, bitshift
;
185 RT_TRACE(rtlpriv
, COMP_RF
, DBG_TRACE
,
186 "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n",
187 regaddr
, rfpath
, bitmask
);
189 spin_lock(&rtlpriv
->locks
.rf_lock
);
191 original_value
= _rtl92s_phy_rf_serial_read(hw
, rfpath
, regaddr
);
193 bitshift
= _rtl92s_phy_calculate_bit_shift(bitmask
);
194 readback_value
= (original_value
& bitmask
) >> bitshift
;
196 spin_unlock(&rtlpriv
->locks
.rf_lock
);
198 RT_TRACE(rtlpriv
, COMP_RF
, DBG_TRACE
,
199 "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n",
200 regaddr
, rfpath
, bitmask
, original_value
);
202 return readback_value
;
205 void rtl92s_phy_set_rf_reg(struct ieee80211_hw
*hw
, enum radio_path rfpath
,
206 u32 regaddr
, u32 bitmask
, u32 data
)
208 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
209 struct rtl_phy
*rtlphy
= &(rtlpriv
->phy
);
210 u32 original_value
, bitshift
;
212 if (!((rtlphy
->rf_pathmap
>> rfpath
) & 0x1))
215 RT_TRACE(rtlpriv
, COMP_RF
, DBG_TRACE
,
216 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
217 regaddr
, bitmask
, data
, rfpath
);
219 spin_lock(&rtlpriv
->locks
.rf_lock
);
221 if (bitmask
!= RFREG_OFFSET_MASK
) {
222 original_value
= _rtl92s_phy_rf_serial_read(hw
, rfpath
,
224 bitshift
= _rtl92s_phy_calculate_bit_shift(bitmask
);
225 data
= ((original_value
& (~bitmask
)) | (data
<< bitshift
));
228 _rtl92s_phy_rf_serial_write(hw
, rfpath
, regaddr
, data
);
230 spin_unlock(&rtlpriv
->locks
.rf_lock
);
232 RT_TRACE(rtlpriv
, COMP_RF
, DBG_TRACE
,
233 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
234 regaddr
, bitmask
, data
, rfpath
);
238 void rtl92s_phy_scan_operation_backup(struct ieee80211_hw
*hw
,
241 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
242 struct rtl_hal
*rtlhal
= rtl_hal(rtl_priv(hw
));
244 if (!is_hal_stop(rtlhal
)) {
246 case SCAN_OPT_BACKUP
:
247 rtl92s_phy_set_fw_cmd(hw
, FW_CMD_PAUSE_DM_BY_SCAN
);
249 case SCAN_OPT_RESTORE
:
250 rtl92s_phy_set_fw_cmd(hw
, FW_CMD_RESUME_DM_BY_SCAN
);
253 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
,
254 "Unknown operation\n");
260 void rtl92s_phy_set_bw_mode(struct ieee80211_hw
*hw
,
261 enum nl80211_channel_type ch_type
)
263 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
264 struct rtl_hal
*rtlhal
= rtl_hal(rtl_priv(hw
));
265 struct rtl_phy
*rtlphy
= &(rtlpriv
->phy
);
266 struct rtl_mac
*mac
= rtl_mac(rtl_priv(hw
));
269 RT_TRACE(rtlpriv
, COMP_SCAN
, DBG_TRACE
, "Switch to %s bandwidth\n",
270 rtlphy
->current_chan_bw
== HT_CHANNEL_WIDTH_20
?
273 if (rtlphy
->set_bwmode_inprogress
)
275 if (is_hal_stop(rtlhal
))
278 rtlphy
->set_bwmode_inprogress
= true;
280 reg_bw_opmode
= rtl_read_byte(rtlpriv
, BW_OPMODE
);
282 rtl_read_byte(rtlpriv
, RRSR
+ 2);
284 switch (rtlphy
->current_chan_bw
) {
285 case HT_CHANNEL_WIDTH_20
:
286 reg_bw_opmode
|= BW_OPMODE_20MHZ
;
287 rtl_write_byte(rtlpriv
, BW_OPMODE
, reg_bw_opmode
);
289 case HT_CHANNEL_WIDTH_20_40
:
290 reg_bw_opmode
&= ~BW_OPMODE_20MHZ
;
291 rtl_write_byte(rtlpriv
, BW_OPMODE
, reg_bw_opmode
);
294 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
,
295 "unknown bandwidth: %#X\n", rtlphy
->current_chan_bw
);
299 switch (rtlphy
->current_chan_bw
) {
300 case HT_CHANNEL_WIDTH_20
:
301 rtl_set_bbreg(hw
, RFPGA0_RFMOD
, BRFMOD
, 0x0);
302 rtl_set_bbreg(hw
, RFPGA1_RFMOD
, BRFMOD
, 0x0);
304 if (rtlhal
->version
>= VERSION_8192S_BCUT
)
305 rtl_write_byte(rtlpriv
, RFPGA0_ANALOGPARAMETER2
, 0x58);
307 case HT_CHANNEL_WIDTH_20_40
:
308 rtl_set_bbreg(hw
, RFPGA0_RFMOD
, BRFMOD
, 0x1);
309 rtl_set_bbreg(hw
, RFPGA1_RFMOD
, BRFMOD
, 0x1);
311 rtl_set_bbreg(hw
, RCCK0_SYSTEM
, BCCK_SIDEBAND
,
312 (mac
->cur_40_prime_sc
>> 1));
313 rtl_set_bbreg(hw
, ROFDM1_LSTF
, 0xC00, mac
->cur_40_prime_sc
);
315 if (rtlhal
->version
>= VERSION_8192S_BCUT
)
316 rtl_write_byte(rtlpriv
, RFPGA0_ANALOGPARAMETER2
, 0x18);
319 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
,
320 "unknown bandwidth: %#X\n", rtlphy
->current_chan_bw
);
324 rtl92s_phy_rf6052_set_bandwidth(hw
, rtlphy
->current_chan_bw
);
325 rtlphy
->set_bwmode_inprogress
= false;
326 RT_TRACE(rtlpriv
, COMP_SCAN
, DBG_TRACE
, "<==\n");
329 static bool _rtl92s_phy_set_sw_chnl_cmdarray(struct swchnlcmd
*cmdtable
,
330 u32 cmdtableidx
, u32 cmdtablesz
, enum swchnlcmd_id cmdid
,
331 u32 para1
, u32 para2
, u32 msdelay
)
333 struct swchnlcmd
*pcmd
;
335 if (cmdtable
== NULL
) {
336 RT_ASSERT(false, "cmdtable cannot be NULL\n");
340 if (cmdtableidx
>= cmdtablesz
)
343 pcmd
= cmdtable
+ cmdtableidx
;
347 pcmd
->msdelay
= msdelay
;
352 static bool _rtl92s_phy_sw_chnl_step_by_step(struct ieee80211_hw
*hw
,
353 u8 channel
, u8
*stage
, u8
*step
, u32
*delay
)
355 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
356 struct rtl_phy
*rtlphy
= &(rtlpriv
->phy
);
357 struct swchnlcmd precommoncmd
[MAX_PRECMD_CNT
];
359 struct swchnlcmd postcommoncmd
[MAX_POSTCMD_CNT
];
360 u32 postcommoncmdcnt
;
361 struct swchnlcmd rfdependcmd
[MAX_RFDEPENDCMD_CNT
];
363 struct swchnlcmd
*currentcmd
= NULL
;
365 u8 num_total_rfpath
= rtlphy
->num_total_rfpath
;
368 _rtl92s_phy_set_sw_chnl_cmdarray(precommoncmd
, precommoncmdcnt
++,
369 MAX_PRECMD_CNT
, CMDID_SET_TXPOWEROWER_LEVEL
, 0, 0, 0);
370 _rtl92s_phy_set_sw_chnl_cmdarray(precommoncmd
, precommoncmdcnt
++,
371 MAX_PRECMD_CNT
, CMDID_END
, 0, 0, 0);
373 postcommoncmdcnt
= 0;
375 _rtl92s_phy_set_sw_chnl_cmdarray(postcommoncmd
, postcommoncmdcnt
++,
376 MAX_POSTCMD_CNT
, CMDID_END
, 0, 0, 0);
380 RT_ASSERT((channel
>= 1 && channel
<= 14),
381 "invalid channel for Zebra: %d\n", channel
);
383 _rtl92s_phy_set_sw_chnl_cmdarray(rfdependcmd
, rfdependcmdcnt
++,
384 MAX_RFDEPENDCMD_CNT
, CMDID_RF_WRITEREG
,
385 RF_CHNLBW
, channel
, 10);
387 _rtl92s_phy_set_sw_chnl_cmdarray(rfdependcmd
, rfdependcmdcnt
++,
388 MAX_RFDEPENDCMD_CNT
, CMDID_END
, 0, 0, 0);
393 currentcmd
= &precommoncmd
[*step
];
396 currentcmd
= &rfdependcmd
[*step
];
399 currentcmd
= &postcommoncmd
[*step
];
403 if (currentcmd
->cmdid
== CMDID_END
) {
413 switch (currentcmd
->cmdid
) {
414 case CMDID_SET_TXPOWEROWER_LEVEL
:
415 rtl92s_phy_set_txpower(hw
, channel
);
417 case CMDID_WRITEPORT_ULONG
:
418 rtl_write_dword(rtlpriv
, currentcmd
->para1
,
421 case CMDID_WRITEPORT_USHORT
:
422 rtl_write_word(rtlpriv
, currentcmd
->para1
,
423 (u16
)currentcmd
->para2
);
425 case CMDID_WRITEPORT_UCHAR
:
426 rtl_write_byte(rtlpriv
, currentcmd
->para1
,
427 (u8
)currentcmd
->para2
);
429 case CMDID_RF_WRITEREG
:
430 for (rfpath
= 0; rfpath
< num_total_rfpath
; rfpath
++) {
431 rtlphy
->rfreg_chnlval
[rfpath
] =
432 ((rtlphy
->rfreg_chnlval
[rfpath
] &
433 0xfffffc00) | currentcmd
->para2
);
434 rtl_set_rfreg(hw
, (enum radio_path
)rfpath
,
437 rtlphy
->rfreg_chnlval
[rfpath
]);
441 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
,
442 "switch case not processed\n");
449 (*delay
) = currentcmd
->msdelay
;
454 u8
rtl92s_phy_sw_chnl(struct ieee80211_hw
*hw
)
456 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
457 struct rtl_hal
*rtlhal
= rtl_hal(rtl_priv(hw
));
458 struct rtl_phy
*rtlphy
= &(rtlpriv
->phy
);
462 RT_TRACE(rtlpriv
, COMP_SCAN
, DBG_TRACE
, "switch to channel%d\n",
463 rtlphy
->current_channel
);
465 if (rtlphy
->sw_chnl_inprogress
)
468 if (rtlphy
->set_bwmode_inprogress
)
471 if (is_hal_stop(rtlhal
))
474 rtlphy
->sw_chnl_inprogress
= true;
475 rtlphy
->sw_chnl_stage
= 0;
476 rtlphy
->sw_chnl_step
= 0;
479 if (!rtlphy
->sw_chnl_inprogress
)
482 ret
= _rtl92s_phy_sw_chnl_step_by_step(hw
,
483 rtlphy
->current_channel
,
484 &rtlphy
->sw_chnl_stage
,
485 &rtlphy
->sw_chnl_step
, &delay
);
492 rtlphy
->sw_chnl_inprogress
= false;
497 rtlphy
->sw_chnl_inprogress
= false;
499 RT_TRACE(rtlpriv
, COMP_SCAN
, DBG_TRACE
, "<==\n");
504 static void _rtl92se_phy_set_rf_sleep(struct ieee80211_hw
*hw
)
506 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
509 u1btmp
= rtl_read_byte(rtlpriv
, LDOV12D_CTRL
);
512 rtl_write_byte(rtlpriv
, LDOV12D_CTRL
, u1btmp
);
513 rtl_write_byte(rtlpriv
, SPS1_CTRL
, 0x0);
514 rtl_write_byte(rtlpriv
, TXPAUSE
, 0xFF);
515 rtl_write_word(rtlpriv
, CMDR
, 0x57FC);
518 rtl_write_word(rtlpriv
, CMDR
, 0x77FC);
519 rtl_write_byte(rtlpriv
, PHY_CCA
, 0x0);
522 rtl_write_word(rtlpriv
, CMDR
, 0x37FC);
525 rtl_write_word(rtlpriv
, CMDR
, 0x77FC);
528 rtl_write_word(rtlpriv
, CMDR
, 0x57FC);
530 /* we should chnge GPIO to input mode
531 * this will drop away current about 25mA*/
532 rtl8192se_gpiobit3_cfg_inputmode(hw
);
535 bool rtl92s_phy_set_rf_power_state(struct ieee80211_hw
*hw
,
536 enum rf_pwrstate rfpwr_state
)
538 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
539 struct rtl_pci_priv
*pcipriv
= rtl_pcipriv(hw
);
540 struct rtl_mac
*mac
= rtl_mac(rtl_priv(hw
));
541 struct rtl_ps_ctl
*ppsc
= rtl_psc(rtl_priv(hw
));
544 struct rtl8192_tx_ring
*ring
= NULL
;
546 if (rfpwr_state
== ppsc
->rfpwr_state
)
549 switch (rfpwr_state
) {
551 if ((ppsc
->rfpwr_state
== ERFOFF
) &&
552 RT_IN_PS_LEVEL(ppsc
, RT_RF_OFF_LEVL_HALT_NIC
)) {
555 u32 InitializeCount
= 0;
558 RT_TRACE(rtlpriv
, COMP_RF
, DBG_DMESG
,
559 "IPS Set eRf nic enable\n");
560 rtstatus
= rtl_ps_enable_nic(hw
);
561 } while ((rtstatus
!= true) &&
562 (InitializeCount
< 10));
564 RT_CLEAR_PS_LEVEL(ppsc
,
565 RT_RF_OFF_LEVL_HALT_NIC
);
567 RT_TRACE(rtlpriv
, COMP_POWER
, DBG_DMESG
,
568 "awake, sleeped:%d ms state_inap:%x\n",
569 jiffies_to_msecs(jiffies
-
572 rtlpriv
->psc
.state_inap
);
573 ppsc
->last_awake_jiffies
= jiffies
;
574 rtl_write_word(rtlpriv
, CMDR
, 0x37FC);
575 rtl_write_byte(rtlpriv
, TXPAUSE
, 0x00);
576 rtl_write_byte(rtlpriv
, PHY_CCA
, 0x3);
579 if (mac
->link_state
== MAC80211_LINKED
)
580 rtlpriv
->cfg
->ops
->led_control(hw
,
583 rtlpriv
->cfg
->ops
->led_control(hw
,
588 if (ppsc
->reg_rfps_level
& RT_RF_OFF_LEVL_HALT_NIC
) {
589 RT_TRACE(rtlpriv
, COMP_RF
, DBG_DMESG
,
590 "IPS Set eRf nic disable\n");
591 rtl_ps_disable_nic(hw
);
592 RT_SET_PS_LEVEL(ppsc
, RT_RF_OFF_LEVL_HALT_NIC
);
594 if (ppsc
->rfoff_reason
== RF_CHANGE_BY_IPS
)
595 rtlpriv
->cfg
->ops
->led_control(hw
,
598 rtlpriv
->cfg
->ops
->led_control(hw
,
604 if (ppsc
->rfpwr_state
== ERFOFF
)
607 for (queue_id
= 0, i
= 0;
608 queue_id
< RTL_PCI_MAX_TX_QUEUE_COUNT
;) {
609 ring
= &pcipriv
->dev
.tx_ring
[queue_id
];
610 if (skb_queue_len(&ring
->queue
) == 0 ||
611 queue_id
== BEACON_QUEUE
) {
615 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_WARNING
,
616 "eRf Off/Sleep: %d times TcbBusyQueue[%d] = %d before doze!\n",
618 skb_queue_len(&ring
->queue
));
624 if (i
>= MAX_DOZE_WAITING_TIMES_9x
) {
625 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_WARNING
,
626 "ERFOFF: %d times TcbBusyQueue[%d] = %d !\n",
627 MAX_DOZE_WAITING_TIMES_9x
,
629 skb_queue_len(&ring
->queue
));
634 RT_TRACE(rtlpriv
, COMP_POWER
, DBG_DMESG
,
635 "Set ERFSLEEP awaked:%d ms\n",
636 jiffies_to_msecs(jiffies
-
637 ppsc
->last_awake_jiffies
));
639 RT_TRACE(rtlpriv
, COMP_POWER
, DBG_DMESG
,
640 "sleep awaked:%d ms state_inap:%x\n",
641 jiffies_to_msecs(jiffies
-
642 ppsc
->last_awake_jiffies
),
643 rtlpriv
->psc
.state_inap
);
644 ppsc
->last_sleep_jiffies
= jiffies
;
645 _rtl92se_phy_set_rf_sleep(hw
);
648 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
,
649 "switch case not processed\n");
655 ppsc
->rfpwr_state
= rfpwr_state
;
660 static bool _rtl92s_phy_config_rfpa_bias_current(struct ieee80211_hw
*hw
,
661 enum radio_path rfpath
)
663 struct rtl_hal
*rtlhal
= rtl_hal(rtl_priv(hw
));
664 bool rtstatus
= true;
667 /* If inferiority IC, we have to increase the PA bias current */
668 if (rtlhal
->ic_class
!= IC_INFERIORITY_A
) {
669 tmpval
= rtl92s_phy_query_rf_reg(hw
, rfpath
, RF_IPA
, 0xf);
670 rtl92s_phy_set_rf_reg(hw
, rfpath
, RF_IPA
, 0xf, tmpval
+ 1);
676 static void _rtl92s_store_pwrindex_diffrate_offset(struct ieee80211_hw
*hw
,
677 u32 reg_addr
, u32 bitmask
, u32 data
)
679 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
680 struct rtl_phy
*rtlphy
= &(rtlpriv
->phy
);
682 if (reg_addr
== RTXAGC_RATE18_06
)
683 rtlphy
->mcs_txpwrlevel_origoffset
[rtlphy
->pwrgroup_cnt
][0] =
685 if (reg_addr
== RTXAGC_RATE54_24
)
686 rtlphy
->mcs_txpwrlevel_origoffset
[rtlphy
->pwrgroup_cnt
][1] =
688 if (reg_addr
== RTXAGC_CCK_MCS32
)
689 rtlphy
->mcs_txpwrlevel_origoffset
[rtlphy
->pwrgroup_cnt
][6] =
691 if (reg_addr
== RTXAGC_MCS03_MCS00
)
692 rtlphy
->mcs_txpwrlevel_origoffset
[rtlphy
->pwrgroup_cnt
][2] =
694 if (reg_addr
== RTXAGC_MCS07_MCS04
)
695 rtlphy
->mcs_txpwrlevel_origoffset
[rtlphy
->pwrgroup_cnt
][3] =
697 if (reg_addr
== RTXAGC_MCS11_MCS08
)
698 rtlphy
->mcs_txpwrlevel_origoffset
[rtlphy
->pwrgroup_cnt
][4] =
700 if (reg_addr
== RTXAGC_MCS15_MCS12
) {
701 rtlphy
->mcs_txpwrlevel_origoffset
[rtlphy
->pwrgroup_cnt
][5] =
703 rtlphy
->pwrgroup_cnt
++;
707 static void _rtl92s_phy_init_register_definition(struct ieee80211_hw
*hw
)
709 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
710 struct rtl_phy
*rtlphy
= &(rtlpriv
->phy
);
712 /*RF Interface Sowrtware Control */
713 rtlphy
->phyreg_def
[RF90_PATH_A
].rfintfs
= RFPGA0_XAB_RFINTERFACESW
;
714 rtlphy
->phyreg_def
[RF90_PATH_B
].rfintfs
= RFPGA0_XAB_RFINTERFACESW
;
715 rtlphy
->phyreg_def
[RF90_PATH_C
].rfintfs
= RFPGA0_XCD_RFINTERFACESW
;
716 rtlphy
->phyreg_def
[RF90_PATH_D
].rfintfs
= RFPGA0_XCD_RFINTERFACESW
;
718 /* RF Interface Readback Value */
719 rtlphy
->phyreg_def
[RF90_PATH_A
].rfintfi
= RFPGA0_XAB_RFINTERFACERB
;
720 rtlphy
->phyreg_def
[RF90_PATH_B
].rfintfi
= RFPGA0_XAB_RFINTERFACERB
;
721 rtlphy
->phyreg_def
[RF90_PATH_C
].rfintfi
= RFPGA0_XCD_RFINTERFACERB
;
722 rtlphy
->phyreg_def
[RF90_PATH_D
].rfintfi
= RFPGA0_XCD_RFINTERFACERB
;
724 /* RF Interface Output (and Enable) */
725 rtlphy
->phyreg_def
[RF90_PATH_A
].rfintfo
= RFPGA0_XA_RFINTERFACEOE
;
726 rtlphy
->phyreg_def
[RF90_PATH_B
].rfintfo
= RFPGA0_XB_RFINTERFACEOE
;
727 rtlphy
->phyreg_def
[RF90_PATH_C
].rfintfo
= RFPGA0_XC_RFINTERFACEOE
;
728 rtlphy
->phyreg_def
[RF90_PATH_D
].rfintfo
= RFPGA0_XD_RFINTERFACEOE
;
730 /* RF Interface (Output and) Enable */
731 rtlphy
->phyreg_def
[RF90_PATH_A
].rfintfe
= RFPGA0_XA_RFINTERFACEOE
;
732 rtlphy
->phyreg_def
[RF90_PATH_B
].rfintfe
= RFPGA0_XB_RFINTERFACEOE
;
733 rtlphy
->phyreg_def
[RF90_PATH_C
].rfintfe
= RFPGA0_XC_RFINTERFACEOE
;
734 rtlphy
->phyreg_def
[RF90_PATH_D
].rfintfe
= RFPGA0_XD_RFINTERFACEOE
;
736 /* Addr of LSSI. Wirte RF register by driver */
737 rtlphy
->phyreg_def
[RF90_PATH_A
].rf3wire_offset
=
738 RFPGA0_XA_LSSIPARAMETER
;
739 rtlphy
->phyreg_def
[RF90_PATH_B
].rf3wire_offset
=
740 RFPGA0_XB_LSSIPARAMETER
;
741 rtlphy
->phyreg_def
[RF90_PATH_C
].rf3wire_offset
=
742 RFPGA0_XC_LSSIPARAMETER
;
743 rtlphy
->phyreg_def
[RF90_PATH_D
].rf3wire_offset
=
744 RFPGA0_XD_LSSIPARAMETER
;
747 rtlphy
->phyreg_def
[RF90_PATH_A
].rflssi_select
= RFPGA0_XAB_RFPARAMETER
;
748 rtlphy
->phyreg_def
[RF90_PATH_B
].rflssi_select
= RFPGA0_XAB_RFPARAMETER
;
749 rtlphy
->phyreg_def
[RF90_PATH_C
].rflssi_select
= RFPGA0_XCD_RFPARAMETER
;
750 rtlphy
->phyreg_def
[RF90_PATH_D
].rflssi_select
= RFPGA0_XCD_RFPARAMETER
;
752 /* Tx AGC Gain Stage (same for all path. Should we remove this?) */
753 rtlphy
->phyreg_def
[RF90_PATH_A
].rftxgain_stage
= RFPGA0_TXGAINSTAGE
;
754 rtlphy
->phyreg_def
[RF90_PATH_B
].rftxgain_stage
= RFPGA0_TXGAINSTAGE
;
755 rtlphy
->phyreg_def
[RF90_PATH_C
].rftxgain_stage
= RFPGA0_TXGAINSTAGE
;
756 rtlphy
->phyreg_def
[RF90_PATH_D
].rftxgain_stage
= RFPGA0_TXGAINSTAGE
;
758 /* Tranceiver A~D HSSI Parameter-1 */
759 rtlphy
->phyreg_def
[RF90_PATH_A
].rfhssi_para1
= RFPGA0_XA_HSSIPARAMETER1
;
760 rtlphy
->phyreg_def
[RF90_PATH_B
].rfhssi_para1
= RFPGA0_XB_HSSIPARAMETER1
;
761 rtlphy
->phyreg_def
[RF90_PATH_C
].rfhssi_para1
= RFPGA0_XC_HSSIPARAMETER1
;
762 rtlphy
->phyreg_def
[RF90_PATH_D
].rfhssi_para1
= RFPGA0_XD_HSSIPARAMETER1
;
764 /* Tranceiver A~D HSSI Parameter-2 */
765 rtlphy
->phyreg_def
[RF90_PATH_A
].rfhssi_para2
= RFPGA0_XA_HSSIPARAMETER2
;
766 rtlphy
->phyreg_def
[RF90_PATH_B
].rfhssi_para2
= RFPGA0_XB_HSSIPARAMETER2
;
767 rtlphy
->phyreg_def
[RF90_PATH_C
].rfhssi_para2
= RFPGA0_XC_HSSIPARAMETER2
;
768 rtlphy
->phyreg_def
[RF90_PATH_D
].rfhssi_para2
= RFPGA0_XD_HSSIPARAMETER2
;
770 /* RF switch Control */
771 rtlphy
->phyreg_def
[RF90_PATH_A
].rfswitch_control
=
772 RFPGA0_XAB_SWITCHCONTROL
;
773 rtlphy
->phyreg_def
[RF90_PATH_B
].rfswitch_control
=
774 RFPGA0_XAB_SWITCHCONTROL
;
775 rtlphy
->phyreg_def
[RF90_PATH_C
].rfswitch_control
=
776 RFPGA0_XCD_SWITCHCONTROL
;
777 rtlphy
->phyreg_def
[RF90_PATH_D
].rfswitch_control
=
778 RFPGA0_XCD_SWITCHCONTROL
;
781 rtlphy
->phyreg_def
[RF90_PATH_A
].rfagc_control1
= ROFDM0_XAAGCCORE1
;
782 rtlphy
->phyreg_def
[RF90_PATH_B
].rfagc_control1
= ROFDM0_XBAGCCORE1
;
783 rtlphy
->phyreg_def
[RF90_PATH_C
].rfagc_control1
= ROFDM0_XCAGCCORE1
;
784 rtlphy
->phyreg_def
[RF90_PATH_D
].rfagc_control1
= ROFDM0_XDAGCCORE1
;
787 rtlphy
->phyreg_def
[RF90_PATH_A
].rfagc_control2
= ROFDM0_XAAGCCORE2
;
788 rtlphy
->phyreg_def
[RF90_PATH_B
].rfagc_control2
= ROFDM0_XBAGCCORE2
;
789 rtlphy
->phyreg_def
[RF90_PATH_C
].rfagc_control2
= ROFDM0_XCAGCCORE2
;
790 rtlphy
->phyreg_def
[RF90_PATH_D
].rfagc_control2
= ROFDM0_XDAGCCORE2
;
792 /* RX AFE control 1 */
793 rtlphy
->phyreg_def
[RF90_PATH_A
].rfrxiq_imbalance
=
794 ROFDM0_XARXIQIMBALANCE
;
795 rtlphy
->phyreg_def
[RF90_PATH_B
].rfrxiq_imbalance
=
796 ROFDM0_XBRXIQIMBALANCE
;
797 rtlphy
->phyreg_def
[RF90_PATH_C
].rfrxiq_imbalance
=
798 ROFDM0_XCRXIQIMBALANCE
;
799 rtlphy
->phyreg_def
[RF90_PATH_D
].rfrxiq_imbalance
=
800 ROFDM0_XDRXIQIMBALANCE
;
802 /* RX AFE control 1 */
803 rtlphy
->phyreg_def
[RF90_PATH_A
].rfrx_afe
= ROFDM0_XARXAFE
;
804 rtlphy
->phyreg_def
[RF90_PATH_B
].rfrx_afe
= ROFDM0_XBRXAFE
;
805 rtlphy
->phyreg_def
[RF90_PATH_C
].rfrx_afe
= ROFDM0_XCRXAFE
;
806 rtlphy
->phyreg_def
[RF90_PATH_D
].rfrx_afe
= ROFDM0_XDRXAFE
;
808 /* Tx AFE control 1 */
809 rtlphy
->phyreg_def
[RF90_PATH_A
].rftxiq_imbalance
=
810 ROFDM0_XATXIQIMBALANCE
;
811 rtlphy
->phyreg_def
[RF90_PATH_B
].rftxiq_imbalance
=
812 ROFDM0_XBTXIQIMBALANCE
;
813 rtlphy
->phyreg_def
[RF90_PATH_C
].rftxiq_imbalance
=
814 ROFDM0_XCTXIQIMBALANCE
;
815 rtlphy
->phyreg_def
[RF90_PATH_D
].rftxiq_imbalance
=
816 ROFDM0_XDTXIQIMBALANCE
;
818 /* Tx AFE control 2 */
819 rtlphy
->phyreg_def
[RF90_PATH_A
].rftx_afe
= ROFDM0_XATXAFE
;
820 rtlphy
->phyreg_def
[RF90_PATH_B
].rftx_afe
= ROFDM0_XBTXAFE
;
821 rtlphy
->phyreg_def
[RF90_PATH_C
].rftx_afe
= ROFDM0_XCTXAFE
;
822 rtlphy
->phyreg_def
[RF90_PATH_D
].rftx_afe
= ROFDM0_XDTXAFE
;
824 /* Tranceiver LSSI Readback */
825 rtlphy
->phyreg_def
[RF90_PATH_A
].rflssi_readback
=
826 RFPGA0_XA_LSSIREADBACK
;
827 rtlphy
->phyreg_def
[RF90_PATH_B
].rflssi_readback
=
828 RFPGA0_XB_LSSIREADBACK
;
829 rtlphy
->phyreg_def
[RF90_PATH_C
].rflssi_readback
=
830 RFPGA0_XC_LSSIREADBACK
;
831 rtlphy
->phyreg_def
[RF90_PATH_D
].rflssi_readback
=
832 RFPGA0_XD_LSSIREADBACK
;
834 /* Tranceiver LSSI Readback PI mode */
835 rtlphy
->phyreg_def
[RF90_PATH_A
].rflssi_readbackpi
=
836 TRANSCEIVERA_HSPI_READBACK
;
837 rtlphy
->phyreg_def
[RF90_PATH_B
].rflssi_readbackpi
=
838 TRANSCEIVERB_HSPI_READBACK
;
842 static bool _rtl92s_phy_config_bb(struct ieee80211_hw
*hw
, u8 configtype
)
847 u16 phy_reg_len
, agc_len
;
849 agc_len
= AGCTAB_ARRAYLENGTH
;
850 agc_table
= rtl8192seagctab_array
;
851 /* Default RF_type: 2T2R */
852 phy_reg_len
= PHY_REG_2T2RARRAYLENGTH
;
853 phy_reg_table
= rtl8192sephy_reg_2t2rarray
;
855 if (configtype
== BASEBAND_CONFIG_PHY_REG
) {
856 for (i
= 0; i
< phy_reg_len
; i
= i
+ 2) {
857 if (phy_reg_table
[i
] == 0xfe)
859 else if (phy_reg_table
[i
] == 0xfd)
861 else if (phy_reg_table
[i
] == 0xfc)
863 else if (phy_reg_table
[i
] == 0xfb)
865 else if (phy_reg_table
[i
] == 0xfa)
867 else if (phy_reg_table
[i
] == 0xf9)
870 /* Add delay for ECS T20 & LG malow platform, */
873 rtl92s_phy_set_bb_reg(hw
, phy_reg_table
[i
], MASKDWORD
,
874 phy_reg_table
[i
+ 1]);
876 } else if (configtype
== BASEBAND_CONFIG_AGC_TAB
) {
877 for (i
= 0; i
< agc_len
; i
= i
+ 2) {
878 rtl92s_phy_set_bb_reg(hw
, agc_table
[i
], MASKDWORD
,
881 /* Add delay for ECS T20 & LG malow platform */
889 static bool _rtl92s_phy_set_bb_to_diff_rf(struct ieee80211_hw
*hw
,
892 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
893 struct rtl_phy
*rtlphy
= &(rtlpriv
->phy
);
894 u32
*phy_regarray2xtxr_table
;
895 u16 phy_regarray2xtxr_len
;
898 if (rtlphy
->rf_type
== RF_1T1R
) {
899 phy_regarray2xtxr_table
= rtl8192sephy_changeto_1t1rarray
;
900 phy_regarray2xtxr_len
= PHY_CHANGETO_1T1RARRAYLENGTH
;
901 } else if (rtlphy
->rf_type
== RF_1T2R
) {
902 phy_regarray2xtxr_table
= rtl8192sephy_changeto_1t2rarray
;
903 phy_regarray2xtxr_len
= PHY_CHANGETO_1T2RARRAYLENGTH
;
908 if (configtype
== BASEBAND_CONFIG_PHY_REG
) {
909 for (i
= 0; i
< phy_regarray2xtxr_len
; i
= i
+ 3) {
910 if (phy_regarray2xtxr_table
[i
] == 0xfe)
912 else if (phy_regarray2xtxr_table
[i
] == 0xfd)
914 else if (phy_regarray2xtxr_table
[i
] == 0xfc)
916 else if (phy_regarray2xtxr_table
[i
] == 0xfb)
918 else if (phy_regarray2xtxr_table
[i
] == 0xfa)
920 else if (phy_regarray2xtxr_table
[i
] == 0xf9)
923 rtl92s_phy_set_bb_reg(hw
, phy_regarray2xtxr_table
[i
],
924 phy_regarray2xtxr_table
[i
+ 1],
925 phy_regarray2xtxr_table
[i
+ 2]);
932 static bool _rtl92s_phy_config_bb_with_pg(struct ieee80211_hw
*hw
,
939 phy_pg_len
= PHY_REG_ARRAY_PGLENGTH
;
940 phy_table_pg
= rtl8192sephy_reg_array_pg
;
942 if (configtype
== BASEBAND_CONFIG_PHY_REG
) {
943 for (i
= 0; i
< phy_pg_len
; i
= i
+ 3) {
944 if (phy_table_pg
[i
] == 0xfe)
946 else if (phy_table_pg
[i
] == 0xfd)
948 else if (phy_table_pg
[i
] == 0xfc)
950 else if (phy_table_pg
[i
] == 0xfb)
952 else if (phy_table_pg
[i
] == 0xfa)
954 else if (phy_table_pg
[i
] == 0xf9)
957 _rtl92s_store_pwrindex_diffrate_offset(hw
,
960 phy_table_pg
[i
+ 2]);
961 rtl92s_phy_set_bb_reg(hw
, phy_table_pg
[i
],
963 phy_table_pg
[i
+ 2]);
970 static bool _rtl92s_phy_bb_config_parafile(struct ieee80211_hw
*hw
)
972 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
973 struct rtl_phy
*rtlphy
= &(rtlpriv
->phy
);
974 struct rtl_efuse
*rtlefuse
= rtl_efuse(rtl_priv(hw
));
975 bool rtstatus
= true;
977 /* 1. Read PHY_REG.TXT BB INIT!! */
978 /* We will separate as 1T1R/1T2R/1T2R_GREEN/2T2R */
979 if (rtlphy
->rf_type
== RF_1T2R
|| rtlphy
->rf_type
== RF_2T2R
||
980 rtlphy
->rf_type
== RF_1T1R
|| rtlphy
->rf_type
== RF_2T2R_GREEN
) {
981 rtstatus
= _rtl92s_phy_config_bb(hw
, BASEBAND_CONFIG_PHY_REG
);
983 if (rtlphy
->rf_type
!= RF_2T2R
&&
984 rtlphy
->rf_type
!= RF_2T2R_GREEN
)
985 /* so we should reconfig BB reg with the right
987 rtstatus
= _rtl92s_phy_set_bb_to_diff_rf(hw
,
988 BASEBAND_CONFIG_PHY_REG
);
993 if (rtstatus
!= true) {
994 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_EMERG
,
995 "Write BB Reg Fail!!\n");
996 goto phy_BB8190_Config_ParaFile_Fail
;
999 /* 2. If EEPROM or EFUSE autoload OK, We must config by
1001 if (rtlefuse
->autoload_failflag
== false) {
1002 rtlphy
->pwrgroup_cnt
= 0;
1004 rtstatus
= _rtl92s_phy_config_bb_with_pg(hw
,
1005 BASEBAND_CONFIG_PHY_REG
);
1007 if (rtstatus
!= true) {
1008 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_EMERG
,
1009 "_rtl92s_phy_bb_config_parafile(): BB_PG Reg Fail!!\n");
1010 goto phy_BB8190_Config_ParaFile_Fail
;
1013 /* 3. BB AGC table Initialization */
1014 rtstatus
= _rtl92s_phy_config_bb(hw
, BASEBAND_CONFIG_AGC_TAB
);
1016 if (rtstatus
!= true) {
1017 pr_err("%s(): AGC Table Fail\n", __func__
);
1018 goto phy_BB8190_Config_ParaFile_Fail
;
1021 /* Check if the CCK HighPower is turned ON. */
1022 /* This is used to calculate PWDB. */
1023 rtlphy
->cck_high_power
= (bool)(rtl92s_phy_query_bb_reg(hw
,
1024 RFPGA0_XA_HSSIPARAMETER2
, 0x200));
1026 phy_BB8190_Config_ParaFile_Fail
:
1030 u8
rtl92s_phy_config_rf(struct ieee80211_hw
*hw
, enum radio_path rfpath
)
1032 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1033 struct rtl_phy
*rtlphy
= &(rtlpriv
->phy
);
1035 bool rtstatus
= true;
1038 u16 radio_a_tblen
, radio_b_tblen
;
1040 radio_a_tblen
= RADIOA_1T_ARRAYLENGTH
;
1041 radio_a_table
= rtl8192seradioa_1t_array
;
1043 /* Using Green mode array table for RF_2T2R_GREEN */
1044 if (rtlphy
->rf_type
== RF_2T2R_GREEN
) {
1045 radio_b_table
= rtl8192seradiob_gm_array
;
1046 radio_b_tblen
= RADIOB_GM_ARRAYLENGTH
;
1048 radio_b_table
= rtl8192seradiob_array
;
1049 radio_b_tblen
= RADIOB_ARRAYLENGTH
;
1052 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_LOUD
, "Radio No %x\n", rfpath
);
1057 for (i
= 0; i
< radio_a_tblen
; i
= i
+ 2) {
1058 if (radio_a_table
[i
] == 0xfe)
1059 /* Delay specific ms. Only RF configuration
1060 * requires delay. */
1062 else if (radio_a_table
[i
] == 0xfd)
1064 else if (radio_a_table
[i
] == 0xfc)
1066 else if (radio_a_table
[i
] == 0xfb)
1068 else if (radio_a_table
[i
] == 0xfa)
1070 else if (radio_a_table
[i
] == 0xf9)
1073 rtl92s_phy_set_rf_reg(hw
, rfpath
,
1076 radio_a_table
[i
+ 1]);
1078 /* Add delay for ECS T20 & LG malow platform */
1082 /* PA Bias current for inferiority IC */
1083 _rtl92s_phy_config_rfpa_bias_current(hw
, rfpath
);
1086 for (i
= 0; i
< radio_b_tblen
; i
= i
+ 2) {
1087 if (radio_b_table
[i
] == 0xfe)
1088 /* Delay specific ms. Only RF configuration
1091 else if (radio_b_table
[i
] == 0xfd)
1093 else if (radio_b_table
[i
] == 0xfc)
1095 else if (radio_b_table
[i
] == 0xfb)
1097 else if (radio_b_table
[i
] == 0xfa)
1099 else if (radio_b_table
[i
] == 0xf9)
1102 rtl92s_phy_set_rf_reg(hw
, rfpath
,
1105 radio_b_table
[i
+ 1]);
1107 /* Add delay for ECS T20 & LG malow platform */
1125 bool rtl92s_phy_mac_config(struct ieee80211_hw
*hw
)
1127 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1132 arraylength
= MAC_2T_ARRAYLENGTH
;
1133 ptraArray
= rtl8192semac_2t_array
;
1135 for (i
= 0; i
< arraylength
; i
= i
+ 2)
1136 rtl_write_byte(rtlpriv
, ptraArray
[i
], (u8
)ptraArray
[i
+ 1]);
1142 bool rtl92s_phy_bb_config(struct ieee80211_hw
*hw
)
1144 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1145 struct rtl_phy
*rtlphy
= &(rtlpriv
->phy
);
1146 bool rtstatus
= true;
1147 u8 pathmap
, index
, rf_num
= 0;
1150 _rtl92s_phy_init_register_definition(hw
);
1152 /* Config BB and AGC */
1153 rtstatus
= _rtl92s_phy_bb_config_parafile(hw
);
1156 /* Check BB/RF confiuration setting. */
1157 /* We only need to configure RF which is turned on. */
1158 path1
= (u8
)(rtl92s_phy_query_bb_reg(hw
, RFPGA0_TXINFO
, 0xf));
1160 path2
= (u8
)(rtl92s_phy_query_bb_reg(hw
, ROFDM0_TRXPATHENABLE
, 0xf));
1161 pathmap
= path1
| path2
;
1163 rtlphy
->rf_pathmap
= pathmap
;
1164 for (index
= 0; index
< 4; index
++) {
1165 if ((pathmap
>> index
) & 0x1)
1169 if ((rtlphy
->rf_type
== RF_1T1R
&& rf_num
!= 1) ||
1170 (rtlphy
->rf_type
== RF_1T2R
&& rf_num
!= 2) ||
1171 (rtlphy
->rf_type
== RF_2T2R
&& rf_num
!= 2) ||
1172 (rtlphy
->rf_type
== RF_2T2R_GREEN
&& rf_num
!= 2)) {
1173 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_EMERG
,
1174 "RF_Type(%x) does not match RF_Num(%x)!!\n",
1175 rtlphy
->rf_type
, rf_num
);
1176 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_EMERG
,
1177 "path1 0x%x, path2 0x%x, pathmap 0x%x\n",
1178 path1
, path2
, pathmap
);
1184 bool rtl92s_phy_rf_config(struct ieee80211_hw
*hw
)
1186 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1187 struct rtl_phy
*rtlphy
= &(rtlpriv
->phy
);
1189 /* Initialize general global value */
1190 if (rtlphy
->rf_type
== RF_1T1R
)
1191 rtlphy
->num_total_rfpath
= 1;
1193 rtlphy
->num_total_rfpath
= 2;
1195 /* Config BB and RF */
1196 return rtl92s_phy_rf6052_config(hw
);
1199 void rtl92s_phy_get_hw_reg_originalvalue(struct ieee80211_hw
*hw
)
1201 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1202 struct rtl_phy
*rtlphy
= &(rtlpriv
->phy
);
1204 /* read rx initial gain */
1205 rtlphy
->default_initialgain
[0] = rtl_get_bbreg(hw
,
1206 ROFDM0_XAAGCCORE1
, MASKBYTE0
);
1207 rtlphy
->default_initialgain
[1] = rtl_get_bbreg(hw
,
1208 ROFDM0_XBAGCCORE1
, MASKBYTE0
);
1209 rtlphy
->default_initialgain
[2] = rtl_get_bbreg(hw
,
1210 ROFDM0_XCAGCCORE1
, MASKBYTE0
);
1211 rtlphy
->default_initialgain
[3] = rtl_get_bbreg(hw
,
1212 ROFDM0_XDAGCCORE1
, MASKBYTE0
);
1213 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_LOUD
,
1214 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x)\n",
1215 rtlphy
->default_initialgain
[0],
1216 rtlphy
->default_initialgain
[1],
1217 rtlphy
->default_initialgain
[2],
1218 rtlphy
->default_initialgain
[3]);
1220 /* read framesync */
1221 rtlphy
->framesync
= rtl_get_bbreg(hw
, ROFDM0_RXDETECTOR3
, MASKBYTE0
);
1222 rtlphy
->framesync_c34
= rtl_get_bbreg(hw
, ROFDM0_RXDETECTOR2
,
1224 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_LOUD
,
1225 "Default framesync (0x%x) = 0x%x\n",
1226 ROFDM0_RXDETECTOR3
, rtlphy
->framesync
);
1230 static void _rtl92s_phy_get_txpower_index(struct ieee80211_hw
*hw
, u8 channel
,
1231 u8
*cckpowerlevel
, u8
*ofdmpowerLevel
)
1233 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1234 struct rtl_phy
*rtlphy
= &(rtlpriv
->phy
);
1235 struct rtl_efuse
*rtlefuse
= rtl_efuse(rtl_priv(hw
));
1236 u8 index
= (channel
- 1);
1240 cckpowerlevel
[0] = rtlefuse
->txpwrlevel_cck
[0][index
];
1242 cckpowerlevel
[1] = rtlefuse
->txpwrlevel_cck
[1][index
];
1244 /* 2. OFDM for 1T or 2T */
1245 if (rtlphy
->rf_type
== RF_1T2R
|| rtlphy
->rf_type
== RF_1T1R
) {
1246 /* Read HT 40 OFDM TX power */
1247 ofdmpowerLevel
[0] = rtlefuse
->txpwrlevel_ht40_1s
[0][index
];
1248 ofdmpowerLevel
[1] = rtlefuse
->txpwrlevel_ht40_1s
[1][index
];
1249 } else if (rtlphy
->rf_type
== RF_2T2R
) {
1250 /* Read HT 40 OFDM TX power */
1251 ofdmpowerLevel
[0] = rtlefuse
->txpwrlevel_ht40_2s
[0][index
];
1252 ofdmpowerLevel
[1] = rtlefuse
->txpwrlevel_ht40_2s
[1][index
];
1256 static void _rtl92s_phy_ccxpower_indexcheck(struct ieee80211_hw
*hw
,
1257 u8 channel
, u8
*cckpowerlevel
, u8
*ofdmpowerlevel
)
1259 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1260 struct rtl_phy
*rtlphy
= &(rtlpriv
->phy
);
1262 rtlphy
->cur_cck_txpwridx
= cckpowerlevel
[0];
1263 rtlphy
->cur_ofdm24g_txpwridx
= ofdmpowerlevel
[0];
1266 void rtl92s_phy_set_txpower(struct ieee80211_hw
*hw
, u8 channel
)
1268 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1269 struct rtl_efuse
*rtlefuse
= rtl_efuse(rtl_priv(hw
));
1270 /* [0]:RF-A, [1]:RF-B */
1271 u8 cckpowerlevel
[2], ofdmpowerLevel
[2];
1273 if (rtlefuse
->txpwr_fromeprom
== false)
1276 /* Mainly we use RF-A Tx Power to write the Tx Power registers,
1277 * but the RF-B Tx Power must be calculated by the antenna diff.
1278 * So we have to rewrite Antenna gain offset register here.
1279 * Please refer to BB register 0x80c
1281 * 2. For OFDM 1T or 2T */
1282 _rtl92s_phy_get_txpower_index(hw
, channel
, &cckpowerlevel
[0],
1283 &ofdmpowerLevel
[0]);
1285 RT_TRACE(rtlpriv
, COMP_POWER
, DBG_LOUD
,
1286 "Channel-%d, cckPowerLevel (A / B) = 0x%x / 0x%x, ofdmPowerLevel (A / B) = 0x%x / 0x%x\n",
1287 channel
, cckpowerlevel
[0], cckpowerlevel
[1],
1288 ofdmpowerLevel
[0], ofdmpowerLevel
[1]);
1290 _rtl92s_phy_ccxpower_indexcheck(hw
, channel
, &cckpowerlevel
[0],
1291 &ofdmpowerLevel
[0]);
1293 rtl92s_phy_rf6052_set_ccktxpower(hw
, cckpowerlevel
[0]);
1294 rtl92s_phy_rf6052_set_ofdmtxpower(hw
, &ofdmpowerLevel
[0], channel
);
1298 void rtl92s_phy_chk_fwcmd_iodone(struct ieee80211_hw
*hw
)
1300 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1301 u16 pollingcnt
= 10000;
1304 /* Make sure that CMD IO has be accepted by FW. */
1308 tmpvalue
= rtl_read_dword(rtlpriv
, WFM5
);
1311 } while (--pollingcnt
);
1313 if (pollingcnt
== 0)
1314 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
, "Set FW Cmd fail!!\n");
1318 static void _rtl92s_phy_set_fwcmd_io(struct ieee80211_hw
*hw
)
1320 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1321 struct rtl_hal
*rtlhal
= rtl_hal(rtl_priv(hw
));
1322 struct rtl_phy
*rtlphy
= &(rtlpriv
->phy
);
1323 u32 input
, current_aid
= 0;
1325 if (is_hal_stop(rtlhal
))
1328 /* We re-map RA related CMD IO to combinational ones */
1329 /* if FW version is v.52 or later. */
1330 switch (rtlhal
->current_fwcmd_io
) {
1331 case FW_CMD_RA_REFRESH_N
:
1332 rtlhal
->current_fwcmd_io
= FW_CMD_RA_REFRESH_N_COMB
;
1334 case FW_CMD_RA_REFRESH_BG
:
1335 rtlhal
->current_fwcmd_io
= FW_CMD_RA_REFRESH_BG_COMB
;
1341 switch (rtlhal
->current_fwcmd_io
) {
1342 case FW_CMD_RA_RESET
:
1343 RT_TRACE(rtlpriv
, COMP_CMD
, DBG_DMESG
, "FW_CMD_RA_RESET\n");
1344 rtl_write_dword(rtlpriv
, WFM5
, FW_RA_RESET
);
1345 rtl92s_phy_chk_fwcmd_iodone(hw
);
1347 case FW_CMD_RA_ACTIVE
:
1348 RT_TRACE(rtlpriv
, COMP_CMD
, DBG_DMESG
, "FW_CMD_RA_ACTIVE\n");
1349 rtl_write_dword(rtlpriv
, WFM5
, FW_RA_ACTIVE
);
1350 rtl92s_phy_chk_fwcmd_iodone(hw
);
1352 case FW_CMD_RA_REFRESH_N
:
1353 RT_TRACE(rtlpriv
, COMP_CMD
, DBG_DMESG
, "FW_CMD_RA_REFRESH_N\n");
1354 input
= FW_RA_REFRESH
;
1355 rtl_write_dword(rtlpriv
, WFM5
, input
);
1356 rtl92s_phy_chk_fwcmd_iodone(hw
);
1357 rtl_write_dword(rtlpriv
, WFM5
, FW_RA_ENABLE_RSSI_MASK
);
1358 rtl92s_phy_chk_fwcmd_iodone(hw
);
1360 case FW_CMD_RA_REFRESH_BG
:
1361 RT_TRACE(rtlpriv
, COMP_CMD
, DBG_DMESG
,
1362 "FW_CMD_RA_REFRESH_BG\n");
1363 rtl_write_dword(rtlpriv
, WFM5
, FW_RA_REFRESH
);
1364 rtl92s_phy_chk_fwcmd_iodone(hw
);
1365 rtl_write_dword(rtlpriv
, WFM5
, FW_RA_DISABLE_RSSI_MASK
);
1366 rtl92s_phy_chk_fwcmd_iodone(hw
);
1368 case FW_CMD_RA_REFRESH_N_COMB
:
1369 RT_TRACE(rtlpriv
, COMP_CMD
, DBG_DMESG
,
1370 "FW_CMD_RA_REFRESH_N_COMB\n");
1371 input
= FW_RA_IOT_N_COMB
;
1372 rtl_write_dword(rtlpriv
, WFM5
, input
);
1373 rtl92s_phy_chk_fwcmd_iodone(hw
);
1375 case FW_CMD_RA_REFRESH_BG_COMB
:
1376 RT_TRACE(rtlpriv
, COMP_CMD
, DBG_DMESG
,
1377 "FW_CMD_RA_REFRESH_BG_COMB\n");
1378 input
= FW_RA_IOT_BG_COMB
;
1379 rtl_write_dword(rtlpriv
, WFM5
, input
);
1380 rtl92s_phy_chk_fwcmd_iodone(hw
);
1382 case FW_CMD_IQK_ENABLE
:
1383 RT_TRACE(rtlpriv
, COMP_CMD
, DBG_DMESG
, "FW_CMD_IQK_ENABLE\n");
1384 rtl_write_dword(rtlpriv
, WFM5
, FW_IQK_ENABLE
);
1385 rtl92s_phy_chk_fwcmd_iodone(hw
);
1387 case FW_CMD_PAUSE_DM_BY_SCAN
:
1388 /* Lower initial gain */
1389 rtl_set_bbreg(hw
, ROFDM0_XAAGCCORE1
, MASKBYTE0
, 0x17);
1390 rtl_set_bbreg(hw
, ROFDM0_XBAGCCORE1
, MASKBYTE0
, 0x17);
1392 rtl_set_bbreg(hw
, RCCK0_CCA
, MASKBYTE2
, 0x40);
1394 case FW_CMD_RESUME_DM_BY_SCAN
:
1396 rtl_set_bbreg(hw
, RCCK0_CCA
, MASKBYTE2
, 0xcd);
1397 rtl92s_phy_set_txpower(hw
, rtlphy
->current_channel
);
1399 case FW_CMD_HIGH_PWR_DISABLE
:
1400 if (rtlpriv
->dm
.dm_flag
& HAL_DM_HIPWR_DISABLE
)
1403 /* Lower initial gain */
1404 rtl_set_bbreg(hw
, ROFDM0_XAAGCCORE1
, MASKBYTE0
, 0x17);
1405 rtl_set_bbreg(hw
, ROFDM0_XBAGCCORE1
, MASKBYTE0
, 0x17);
1407 rtl_set_bbreg(hw
, RCCK0_CCA
, MASKBYTE2
, 0x40);
1409 case FW_CMD_HIGH_PWR_ENABLE
:
1410 if ((rtlpriv
->dm
.dm_flag
& HAL_DM_HIPWR_DISABLE
) ||
1411 rtlpriv
->dm
.dynamic_txpower_enable
)
1415 rtl_set_bbreg(hw
, RCCK0_CCA
, MASKBYTE2
, 0xcd);
1417 case FW_CMD_LPS_ENTER
:
1418 RT_TRACE(rtlpriv
, COMP_CMD
, DBG_DMESG
, "FW_CMD_LPS_ENTER\n");
1419 current_aid
= rtlpriv
->mac80211
.assoc_id
;
1420 rtl_write_dword(rtlpriv
, WFM5
, (FW_LPS_ENTER
|
1421 ((current_aid
| 0xc000) << 8)));
1422 rtl92s_phy_chk_fwcmd_iodone(hw
);
1423 /* FW set TXOP disable here, so disable EDCA
1424 * turbo mode until driver leave LPS */
1426 case FW_CMD_LPS_LEAVE
:
1427 RT_TRACE(rtlpriv
, COMP_CMD
, DBG_DMESG
, "FW_CMD_LPS_LEAVE\n");
1428 rtl_write_dword(rtlpriv
, WFM5
, FW_LPS_LEAVE
);
1429 rtl92s_phy_chk_fwcmd_iodone(hw
);
1431 case FW_CMD_ADD_A2_ENTRY
:
1432 RT_TRACE(rtlpriv
, COMP_CMD
, DBG_DMESG
, "FW_CMD_ADD_A2_ENTRY\n");
1433 rtl_write_dword(rtlpriv
, WFM5
, FW_ADD_A2_ENTRY
);
1434 rtl92s_phy_chk_fwcmd_iodone(hw
);
1436 case FW_CMD_CTRL_DM_BY_DRIVER
:
1437 RT_TRACE(rtlpriv
, COMP_CMD
, DBG_LOUD
,
1438 "FW_CMD_CTRL_DM_BY_DRIVER\n");
1439 rtl_write_dword(rtlpriv
, WFM5
, FW_CTRL_DM_BY_DRIVER
);
1440 rtl92s_phy_chk_fwcmd_iodone(hw
);
1447 rtl92s_phy_chk_fwcmd_iodone(hw
);
1449 /* Clear FW CMD operation flag. */
1450 rtlhal
->set_fwcmd_inprogress
= false;
1453 bool rtl92s_phy_set_fw_cmd(struct ieee80211_hw
*hw
, enum fwcmd_iotype fw_cmdio
)
1455 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1456 struct rtl_hal
*rtlhal
= rtl_hal(rtl_priv(hw
));
1457 struct rtl_efuse
*rtlefuse
= rtl_efuse(rtl_priv(hw
));
1458 u32 fw_param
= FW_CMD_IO_PARA_QUERY(rtlpriv
);
1459 u16 fw_cmdmap
= FW_CMD_IO_QUERY(rtlpriv
);
1460 bool bPostProcessing
= false;
1462 RT_TRACE(rtlpriv
, COMP_CMD
, DBG_LOUD
,
1463 "Set FW Cmd(%#x), set_fwcmd_inprogress(%d)\n",
1464 fw_cmdio
, rtlhal
->set_fwcmd_inprogress
);
1467 /* We re-map to combined FW CMD ones if firmware version */
1468 /* is v.53 or later. */
1470 case FW_CMD_RA_REFRESH_N
:
1471 fw_cmdio
= FW_CMD_RA_REFRESH_N_COMB
;
1473 case FW_CMD_RA_REFRESH_BG
:
1474 fw_cmdio
= FW_CMD_RA_REFRESH_BG_COMB
;
1480 /* If firmware version is v.62 or later,
1481 * use FW_CMD_IO_SET for FW_CMD_CTRL_DM_BY_DRIVER */
1482 if (hal_get_firmwareversion(rtlpriv
) >= 0x3E) {
1483 if (fw_cmdio
== FW_CMD_CTRL_DM_BY_DRIVER
)
1484 fw_cmdio
= FW_CMD_CTRL_DM_BY_DRIVER_NEW
;
1488 /* We shall revise all FW Cmd IO into Reg0x364
1489 * DM map table in the future. */
1491 case FW_CMD_RA_INIT
:
1492 RT_TRACE(rtlpriv
, COMP_CMD
, DBG_LOUD
, "RA init!!\n");
1493 fw_cmdmap
|= FW_RA_INIT_CTL
;
1494 FW_CMD_IO_SET(rtlpriv
, fw_cmdmap
);
1495 /* Clear control flag to sync with FW. */
1496 FW_CMD_IO_CLR(rtlpriv
, FW_RA_INIT_CTL
);
1498 case FW_CMD_DIG_DISABLE
:
1499 RT_TRACE(rtlpriv
, COMP_CMD
, DBG_LOUD
,
1500 "Set DIG disable!!\n");
1501 fw_cmdmap
&= ~FW_DIG_ENABLE_CTL
;
1502 FW_CMD_IO_SET(rtlpriv
, fw_cmdmap
);
1504 case FW_CMD_DIG_ENABLE
:
1505 case FW_CMD_DIG_RESUME
:
1506 if (!(rtlpriv
->dm
.dm_flag
& HAL_DM_DIG_DISABLE
)) {
1507 RT_TRACE(rtlpriv
, COMP_CMD
, DBG_LOUD
,
1508 "Set DIG enable or resume!!\n");
1509 fw_cmdmap
|= (FW_DIG_ENABLE_CTL
| FW_SS_CTL
);
1510 FW_CMD_IO_SET(rtlpriv
, fw_cmdmap
);
1513 case FW_CMD_DIG_HALT
:
1514 RT_TRACE(rtlpriv
, COMP_CMD
, DBG_LOUD
,
1515 "Set DIG halt!!\n");
1516 fw_cmdmap
&= ~(FW_DIG_ENABLE_CTL
| FW_SS_CTL
);
1517 FW_CMD_IO_SET(rtlpriv
, fw_cmdmap
);
1519 case FW_CMD_TXPWR_TRACK_THERMAL
: {
1521 fw_cmdmap
|= FW_PWR_TRK_CTL
;
1523 /* Clear FW parameter in terms of thermal parts. */
1524 fw_param
&= FW_PWR_TRK_PARAM_CLR
;
1526 thermalval
= rtlpriv
->dm
.thermalvalue
;
1527 fw_param
|= ((thermalval
<< 24) |
1528 (rtlefuse
->thermalmeter
[0] << 16));
1530 RT_TRACE(rtlpriv
, COMP_CMD
, DBG_LOUD
,
1531 "Set TxPwr tracking!! FwCmdMap(%#x), FwParam(%#x)\n",
1532 fw_cmdmap
, fw_param
);
1534 FW_CMD_PARA_SET(rtlpriv
, fw_param
);
1535 FW_CMD_IO_SET(rtlpriv
, fw_cmdmap
);
1537 /* Clear control flag to sync with FW. */
1538 FW_CMD_IO_CLR(rtlpriv
, FW_PWR_TRK_CTL
);
1541 /* The following FW CMDs are only compatible to
1543 case FW_CMD_RA_REFRESH_N_COMB
:
1544 fw_cmdmap
|= FW_RA_N_CTL
;
1546 /* Clear RA BG mode control. */
1547 fw_cmdmap
&= ~(FW_RA_BG_CTL
| FW_RA_INIT_CTL
);
1549 /* Clear FW parameter in terms of RA parts. */
1550 fw_param
&= FW_RA_PARAM_CLR
;
1552 RT_TRACE(rtlpriv
, COMP_CMD
, DBG_LOUD
,
1553 "[FW CMD] [New Version] Set RA/IOT Comb in n mode!! FwCmdMap(%#x), FwParam(%#x)\n",
1554 fw_cmdmap
, fw_param
);
1556 FW_CMD_PARA_SET(rtlpriv
, fw_param
);
1557 FW_CMD_IO_SET(rtlpriv
, fw_cmdmap
);
1559 /* Clear control flag to sync with FW. */
1560 FW_CMD_IO_CLR(rtlpriv
, FW_RA_N_CTL
);
1562 case FW_CMD_RA_REFRESH_BG_COMB
:
1563 fw_cmdmap
|= FW_RA_BG_CTL
;
1565 /* Clear RA n-mode control. */
1566 fw_cmdmap
&= ~(FW_RA_N_CTL
| FW_RA_INIT_CTL
);
1567 /* Clear FW parameter in terms of RA parts. */
1568 fw_param
&= FW_RA_PARAM_CLR
;
1570 FW_CMD_PARA_SET(rtlpriv
, fw_param
);
1571 FW_CMD_IO_SET(rtlpriv
, fw_cmdmap
);
1573 /* Clear control flag to sync with FW. */
1574 FW_CMD_IO_CLR(rtlpriv
, FW_RA_BG_CTL
);
1576 case FW_CMD_IQK_ENABLE
:
1577 fw_cmdmap
|= FW_IQK_CTL
;
1578 FW_CMD_IO_SET(rtlpriv
, fw_cmdmap
);
1579 /* Clear control flag to sync with FW. */
1580 FW_CMD_IO_CLR(rtlpriv
, FW_IQK_CTL
);
1582 /* The following FW CMD is compatible to v.62 or later. */
1583 case FW_CMD_CTRL_DM_BY_DRIVER_NEW
:
1584 fw_cmdmap
|= FW_DRIVER_CTRL_DM_CTL
;
1585 FW_CMD_IO_SET(rtlpriv
, fw_cmdmap
);
1587 /* The followed FW Cmds needs post-processing later. */
1588 case FW_CMD_RESUME_DM_BY_SCAN
:
1589 fw_cmdmap
|= (FW_DIG_ENABLE_CTL
|
1590 FW_HIGH_PWR_ENABLE_CTL
|
1593 if (rtlpriv
->dm
.dm_flag
& HAL_DM_DIG_DISABLE
||
1594 !digtable
.dig_enable_flag
)
1595 fw_cmdmap
&= ~FW_DIG_ENABLE_CTL
;
1597 if ((rtlpriv
->dm
.dm_flag
& HAL_DM_HIPWR_DISABLE
) ||
1598 rtlpriv
->dm
.dynamic_txpower_enable
)
1599 fw_cmdmap
&= ~FW_HIGH_PWR_ENABLE_CTL
;
1601 if ((digtable
.dig_ext_port_stage
==
1602 DIG_EXT_PORT_STAGE_0
) ||
1603 (digtable
.dig_ext_port_stage
==
1604 DIG_EXT_PORT_STAGE_1
))
1605 fw_cmdmap
&= ~FW_DIG_ENABLE_CTL
;
1607 FW_CMD_IO_SET(rtlpriv
, fw_cmdmap
);
1608 bPostProcessing
= true;
1610 case FW_CMD_PAUSE_DM_BY_SCAN
:
1611 fw_cmdmap
&= ~(FW_DIG_ENABLE_CTL
|
1612 FW_HIGH_PWR_ENABLE_CTL
|
1614 FW_CMD_IO_SET(rtlpriv
, fw_cmdmap
);
1615 bPostProcessing
= true;
1617 case FW_CMD_HIGH_PWR_DISABLE
:
1618 fw_cmdmap
&= ~FW_HIGH_PWR_ENABLE_CTL
;
1619 FW_CMD_IO_SET(rtlpriv
, fw_cmdmap
);
1620 bPostProcessing
= true;
1622 case FW_CMD_HIGH_PWR_ENABLE
:
1623 if (!(rtlpriv
->dm
.dm_flag
& HAL_DM_HIPWR_DISABLE
) &&
1624 (rtlpriv
->dm
.dynamic_txpower_enable
!= true)) {
1625 fw_cmdmap
|= (FW_HIGH_PWR_ENABLE_CTL
|
1627 FW_CMD_IO_SET(rtlpriv
, fw_cmdmap
);
1628 bPostProcessing
= true;
1631 case FW_CMD_DIG_MODE_FA
:
1632 fw_cmdmap
|= FW_FA_CTL
;
1633 FW_CMD_IO_SET(rtlpriv
, fw_cmdmap
);
1635 case FW_CMD_DIG_MODE_SS
:
1636 fw_cmdmap
&= ~FW_FA_CTL
;
1637 FW_CMD_IO_SET(rtlpriv
, fw_cmdmap
);
1639 case FW_CMD_PAPE_CONTROL
:
1640 RT_TRACE(rtlpriv
, COMP_CMD
, DBG_LOUD
,
1641 "[FW CMD] Set PAPE Control\n");
1642 fw_cmdmap
&= ~FW_PAPE_CTL_BY_SW_HW
;
1644 FW_CMD_IO_SET(rtlpriv
, fw_cmdmap
);
1647 /* Pass to original FW CMD processing callback
1649 bPostProcessing
= true;
1654 /* We shall post processing these FW CMD if
1655 * variable bPostProcessing is set. */
1656 if (bPostProcessing
&& !rtlhal
->set_fwcmd_inprogress
) {
1657 rtlhal
->set_fwcmd_inprogress
= true;
1658 /* Update current FW Cmd for callback use. */
1659 rtlhal
->current_fwcmd_io
= fw_cmdio
;
1664 _rtl92s_phy_set_fwcmd_io(hw
);
1668 static void _rtl92s_phy_check_ephy_switchready(struct ieee80211_hw
*hw
)
1670 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1674 regu1
= rtl_read_byte(rtlpriv
, 0x554);
1675 while ((regu1
& BIT(5)) && (delay
> 0)) {
1676 regu1
= rtl_read_byte(rtlpriv
, 0x554);
1678 /* We delay only 50us to prevent
1679 * being scheduled out. */
1684 void rtl92s_phy_switch_ephy_parameter(struct ieee80211_hw
*hw
)
1686 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1687 struct rtl_ps_ctl
*ppsc
= rtl_psc(rtl_priv(hw
));
1689 /* The way to be capable to switch clock request
1690 * when the PG setting does not support clock request.
1691 * This is the backdoor solution to switch clock
1692 * request before ASPM or D3. */
1693 rtl_write_dword(rtlpriv
, 0x540, 0x73c11);
1694 rtl_write_dword(rtlpriv
, 0x548, 0x2407c);
1696 /* Switch EPHY parameter!!!! */
1697 rtl_write_word(rtlpriv
, 0x550, 0x1000);
1698 rtl_write_byte(rtlpriv
, 0x554, 0x20);
1699 _rtl92s_phy_check_ephy_switchready(hw
);
1701 rtl_write_word(rtlpriv
, 0x550, 0xa0eb);
1702 rtl_write_byte(rtlpriv
, 0x554, 0x3e);
1703 _rtl92s_phy_check_ephy_switchready(hw
);
1705 rtl_write_word(rtlpriv
, 0x550, 0xff80);
1706 rtl_write_byte(rtlpriv
, 0x554, 0x39);
1707 _rtl92s_phy_check_ephy_switchready(hw
);
1709 /* Delay L1 enter time */
1710 if (ppsc
->support_aspm
&& !ppsc
->support_backdoor
)
1711 rtl_write_byte(rtlpriv
, 0x560, 0x40);
1713 rtl_write_byte(rtlpriv
, 0x560, 0x00);
1717 void rtl92s_phy_set_beacon_hwreg(struct ieee80211_hw
*hw
, u16 BeaconInterval
)
1719 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1720 rtl_write_dword(rtlpriv
, WFM5
, 0xF1000000 | (BeaconInterval
<< 8));