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rtlwifi: rtl8192c-common: Convert driver to use common DM table initialization
[deliverable/linux.git] / drivers / net / wireless / rtlwifi / rtl8723ae / dm.c
1 /******************************************************************************
2 *
3 * Copyright(c) 2009-2012 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26 #include "../wifi.h"
27 #include "../base.h"
28 #include "../pci.h"
29 #include "../core.h"
30 #include "reg.h"
31 #include "def.h"
32 #include "phy.h"
33 #include "dm.h"
34 #include "../rtl8723com/dm_common.h"
35 #include "fw.h"
36 #include "hal_btc.h"
37
38 static const u32 ofdmswing_table[OFDM_TABLE_SIZE] = {
39 0x7f8001fe,
40 0x788001e2,
41 0x71c001c7,
42 0x6b8001ae,
43 0x65400195,
44 0x5fc0017f,
45 0x5a400169,
46 0x55400155,
47 0x50800142,
48 0x4c000130,
49 0x47c0011f,
50 0x43c0010f,
51 0x40000100,
52 0x3c8000f2,
53 0x390000e4,
54 0x35c000d7,
55 0x32c000cb,
56 0x300000c0,
57 0x2d4000b5,
58 0x2ac000ab,
59 0x288000a2,
60 0x26000098,
61 0x24000090,
62 0x22000088,
63 0x20000080,
64 0x1e400079,
65 0x1c800072,
66 0x1b00006c,
67 0x19800066,
68 0x18000060,
69 0x16c0005b,
70 0x15800056,
71 0x14400051,
72 0x1300004c,
73 0x12000048,
74 0x11000044,
75 0x10000040,
76 };
77
78 static const u8 cckswing_table_ch1ch13[CCK_TABLE_SIZE][8] = {
79 {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04},
80 {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04},
81 {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03},
82 {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03},
83 {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03},
84 {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03},
85 {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03},
86 {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03},
87 {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02},
88 {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02},
89 {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02},
90 {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02},
91 {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02},
92 {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02},
93 {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02},
94 {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02},
95 {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01},
96 {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02},
97 {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01},
98 {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},
99 {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},
100 {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01},
101 {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01},
102 {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01},
103 {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01},
104 {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01},
105 {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01},
106 {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01},
107 {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01},
108 {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01},
109 {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01},
110 {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},
111 {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}
112 };
113
114 static const u8 cckswing_table_ch14[CCK_TABLE_SIZE][8] = {
115 {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00},
116 {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00},
117 {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00},
118 {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00},
119 {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00},
120 {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00},
121 {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00},
122 {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00},
123 {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00},
124 {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00},
125 {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00},
126 {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00},
127 {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00},
128 {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00},
129 {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00},
130 {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00},
131 {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00},
132 {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00},
133 {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00},
134 {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},
135 {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},
136 {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00},
137 {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00},
138 {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},
139 {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},
140 {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00},
141 {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},
142 {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},
143 {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},
144 {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},
145 {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},
146 {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},
147 {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}
148 };
149
150 static void rtl8723e_dm_diginit(struct ieee80211_hw *hw)
151 {
152 struct rtl_priv *rtlpriv = rtl_priv(hw);
153 struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
154
155 dm_digtable->dig_enable_flag = true;
156 dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
157 dm_digtable->cur_igvalue = 0x20;
158 dm_digtable->pre_igvalue = 0x0;
159 dm_digtable->cursta_cstate = DIG_STA_DISCONNECT;
160 dm_digtable->presta_cstate = DIG_STA_DISCONNECT;
161 dm_digtable->curmultista_cstate = DIG_MULTISTA_DISCONNECT;
162 dm_digtable->rssi_lowthresh = DM_DIG_THRESH_LOW;
163 dm_digtable->rssi_highthresh = DM_DIG_THRESH_HIGH;
164 dm_digtable->fa_lowthresh = DM_FALSEALARM_THRESH_LOW;
165 dm_digtable->fa_highthresh = DM_FALSEALARM_THRESH_HIGH;
166 dm_digtable->rx_gain_max = DM_DIG_MAX;
167 dm_digtable->rx_gain_min = DM_DIG_MIN;
168 dm_digtable->back_val = DM_DIG_BACKOFF_DEFAULT;
169 dm_digtable->back_range_max = DM_DIG_BACKOFF_MAX;
170 dm_digtable->back_range_min = DM_DIG_BACKOFF_MIN;
171 dm_digtable->pre_cck_pd_state = CCK_PD_STAGE_MAX;
172 dm_digtable->cur_cck_pd_state = CCK_PD_STAGE_MAX;
173 }
174
175 static u8 rtl8723e_dm_initial_gain_min_pwdb(struct ieee80211_hw *hw)
176 {
177 struct rtl_priv *rtlpriv = rtl_priv(hw);
178 struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
179 long rssi_val_min = 0;
180
181 if ((dm_digtable->curmultista_cstate == DIG_MULTISTA_CONNECT) &&
182 (dm_digtable->cursta_cstate == DIG_STA_CONNECT)) {
183 if (rtlpriv->dm.entry_min_undec_sm_pwdb != 0)
184 rssi_val_min =
185 (rtlpriv->dm.entry_min_undec_sm_pwdb >
186 rtlpriv->dm.undec_sm_pwdb) ?
187 rtlpriv->dm.undec_sm_pwdb :
188 rtlpriv->dm.entry_min_undec_sm_pwdb;
189 else
190 rssi_val_min = rtlpriv->dm.undec_sm_pwdb;
191 } else if (dm_digtable->cursta_cstate == DIG_STA_CONNECT ||
192 dm_digtable->cursta_cstate == DIG_STA_BEFORE_CONNECT) {
193 rssi_val_min = rtlpriv->dm.undec_sm_pwdb;
194 } else if (dm_digtable->curmultista_cstate ==
195 DIG_MULTISTA_CONNECT) {
196 rssi_val_min = rtlpriv->dm.entry_min_undec_sm_pwdb;
197 }
198
199 return (u8) rssi_val_min;
200 }
201
202 static void rtl8723e_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw)
203 {
204 u32 ret_value;
205 struct rtl_priv *rtlpriv = rtl_priv(hw);
206 struct false_alarm_statistics *falsealm_cnt = &(rtlpriv->falsealm_cnt);
207
208 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER1, MASKDWORD);
209 falsealm_cnt->cnt_parity_fail = ((ret_value & 0xffff0000) >> 16);
210
211 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER2, MASKDWORD);
212 falsealm_cnt->cnt_rate_illegal = (ret_value & 0xffff);
213 falsealm_cnt->cnt_crc8_fail = ((ret_value & 0xffff0000) >> 16);
214
215 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER3, MASKDWORD);
216 falsealm_cnt->cnt_mcs_fail = (ret_value & 0xffff);
217 falsealm_cnt->cnt_ofdm_fail = falsealm_cnt->cnt_parity_fail +
218 falsealm_cnt->cnt_rate_illegal +
219 falsealm_cnt->cnt_crc8_fail + falsealm_cnt->cnt_mcs_fail;
220
221 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, BIT(14), 1);
222 ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERLOWER, MASKBYTE0);
223 falsealm_cnt->cnt_cck_fail = ret_value;
224
225 ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERUPPER, MASKBYTE3);
226 falsealm_cnt->cnt_cck_fail += (ret_value & 0xff) << 8;
227 falsealm_cnt->cnt_all = (falsealm_cnt->cnt_parity_fail +
228 falsealm_cnt->cnt_rate_illegal +
229 falsealm_cnt->cnt_crc8_fail +
230 falsealm_cnt->cnt_mcs_fail +
231 falsealm_cnt->cnt_cck_fail);
232
233 rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 1);
234 rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 0);
235 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 0);
236 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 2);
237
238 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
239 "cnt_parity_fail = %d, cnt_rate_illegal = %d, cnt_crc8_fail = %d, cnt_mcs_fail = %d\n",
240 falsealm_cnt->cnt_parity_fail,
241 falsealm_cnt->cnt_rate_illegal,
242 falsealm_cnt->cnt_crc8_fail, falsealm_cnt->cnt_mcs_fail);
243
244 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
245 "cnt_ofdm_fail = %x, cnt_cck_fail = %x, cnt_all = %x\n",
246 falsealm_cnt->cnt_ofdm_fail,
247 falsealm_cnt->cnt_cck_fail, falsealm_cnt->cnt_all);
248 }
249
250 static void rtl92c_dm_ctrl_initgain_by_fa(struct ieee80211_hw *hw)
251 {
252 struct rtl_priv *rtlpriv = rtl_priv(hw);
253 struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
254 u8 value_igi = dm_digtable->cur_igvalue;
255
256 if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH0)
257 value_igi--;
258 else if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH1)
259 value_igi += 0;
260 else if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH2)
261 value_igi++;
262 else if (rtlpriv->falsealm_cnt.cnt_all >= DM_DIG_FA_TH2)
263 value_igi += 2;
264 if (value_igi > DM_DIG_FA_UPPER)
265 value_igi = DM_DIG_FA_UPPER;
266 else if (value_igi < DM_DIG_FA_LOWER)
267 value_igi = DM_DIG_FA_LOWER;
268 if (rtlpriv->falsealm_cnt.cnt_all > 10000)
269 value_igi = 0x32;
270
271 dm_digtable->cur_igvalue = value_igi;
272 rtl8723e_dm_write_dig(hw);
273 }
274
275 static void rtl92c_dm_ctrl_initgain_by_rssi(struct ieee80211_hw *hw)
276 {
277 struct rtl_priv *rtlpriv = rtl_priv(hw);
278 struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
279
280 if (rtlpriv->falsealm_cnt.cnt_all > dm_digtable->fa_highthresh) {
281 if ((dm_digtable->back_val - 2) <
282 dm_digtable->back_range_min)
283 dm_digtable->back_val =
284 dm_digtable->back_range_min;
285 else
286 dm_digtable->back_val -= 2;
287 } else if (rtlpriv->falsealm_cnt.cnt_all < dm_digtable->fa_lowthresh) {
288 if ((dm_digtable->back_val + 2) >
289 dm_digtable->back_range_max)
290 dm_digtable->back_val =
291 dm_digtable->back_range_max;
292 else
293 dm_digtable->back_val += 2;
294 }
295
296 if ((dm_digtable->rssi_val_min + 10 - dm_digtable->back_val) >
297 dm_digtable->rx_gain_max)
298 dm_digtable->cur_igvalue = dm_digtable->rx_gain_max;
299 else if ((dm_digtable->rssi_val_min + 10 -
300 dm_digtable->back_val) < dm_digtable->rx_gain_min)
301 dm_digtable->cur_igvalue = dm_digtable->rx_gain_min;
302 else
303 dm_digtable->cur_igvalue = dm_digtable->rssi_val_min + 10 -
304 dm_digtable->back_val;
305
306 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
307 "rssi_val_min = %x back_val %x\n",
308 dm_digtable->rssi_val_min, dm_digtable->back_val);
309
310 rtl8723e_dm_write_dig(hw);
311 }
312
313 static void rtl8723e_dm_initial_gain_multi_sta(struct ieee80211_hw *hw)
314 {
315 static u8 binitialized;
316 struct rtl_priv *rtlpriv = rtl_priv(hw);
317 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
318 struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
319 long rssi_strength = rtlpriv->dm.entry_min_undec_sm_pwdb;
320 bool multi_sta = false;
321
322 if (mac->opmode == NL80211_IFTYPE_ADHOC)
323 multi_sta = true;
324
325 if (!multi_sta || (dm_digtable->cursta_cstate != DIG_STA_DISCONNECT)) {
326 binitialized = false;
327 dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
328 return;
329 } else if (!binitialized) {
330 binitialized = true;
331 dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_0;
332 dm_digtable->cur_igvalue = 0x20;
333 rtl8723e_dm_write_dig(hw);
334 }
335
336 if (dm_digtable->curmultista_cstate == DIG_MULTISTA_CONNECT) {
337 if ((rssi_strength < dm_digtable->rssi_lowthresh) &&
338 (dm_digtable->dig_ext_port_stage != DIG_EXT_PORT_STAGE_1)) {
339
340 if (dm_digtable->dig_ext_port_stage ==
341 DIG_EXT_PORT_STAGE_2) {
342 dm_digtable->cur_igvalue = 0x20;
343 rtl8723e_dm_write_dig(hw);
344 }
345
346 dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_1;
347 } else if (rssi_strength > dm_digtable->rssi_highthresh) {
348 dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_2;
349 rtl92c_dm_ctrl_initgain_by_fa(hw);
350 }
351 } else if (dm_digtable->dig_ext_port_stage != DIG_EXT_PORT_STAGE_0) {
352 dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_0;
353 dm_digtable->cur_igvalue = 0x20;
354 rtl8723e_dm_write_dig(hw);
355 }
356
357 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
358 "curmultista_cstate = %x dig_ext_port_stage %x\n",
359 dm_digtable->curmultista_cstate,
360 dm_digtable->dig_ext_port_stage);
361 }
362
363 static void rtl8723e_dm_initial_gain_sta(struct ieee80211_hw *hw)
364 {
365 struct rtl_priv *rtlpriv = rtl_priv(hw);
366 struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
367
368 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
369 "presta_cstate = %x, cursta_cstate = %x\n",
370 dm_digtable->presta_cstate,
371 dm_digtable->cursta_cstate);
372
373 if (dm_digtable->presta_cstate == dm_digtable->cursta_cstate ||
374 dm_digtable->cursta_cstate == DIG_STA_BEFORE_CONNECT ||
375 dm_digtable->cursta_cstate == DIG_STA_CONNECT) {
376 if (dm_digtable->cursta_cstate != DIG_STA_DISCONNECT) {
377 dm_digtable->rssi_val_min =
378 rtl8723e_dm_initial_gain_min_pwdb(hw);
379 rtl92c_dm_ctrl_initgain_by_rssi(hw);
380 }
381 } else {
382 dm_digtable->rssi_val_min = 0;
383 dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
384 dm_digtable->back_val = DM_DIG_BACKOFF_DEFAULT;
385 dm_digtable->cur_igvalue = 0x20;
386 dm_digtable->pre_igvalue = 0;
387 rtl8723e_dm_write_dig(hw);
388 }
389 }
390
391 static void rtl8723e_dm_cck_packet_detection_thresh(struct ieee80211_hw *hw)
392 {
393 struct rtl_priv *rtlpriv = rtl_priv(hw);
394 struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
395
396 if (dm_digtable->cursta_cstate == DIG_STA_CONNECT) {
397 dm_digtable->rssi_val_min = rtl8723e_dm_initial_gain_min_pwdb(hw);
398
399 if (dm_digtable->pre_cck_pd_state == CCK_PD_STAGE_LOWRSSI) {
400 if (dm_digtable->rssi_val_min <= 25)
401 dm_digtable->cur_cck_pd_state =
402 CCK_PD_STAGE_LOWRSSI;
403 else
404 dm_digtable->cur_cck_pd_state =
405 CCK_PD_STAGE_HIGHRSSI;
406 } else {
407 if (dm_digtable->rssi_val_min <= 20)
408 dm_digtable->cur_cck_pd_state =
409 CCK_PD_STAGE_LOWRSSI;
410 else
411 dm_digtable->cur_cck_pd_state =
412 CCK_PD_STAGE_HIGHRSSI;
413 }
414 } else {
415 dm_digtable->cur_cck_pd_state = CCK_PD_STAGE_MAX;
416 }
417
418 if (dm_digtable->pre_cck_pd_state != dm_digtable->cur_cck_pd_state) {
419 if (dm_digtable->cur_cck_pd_state == CCK_PD_STAGE_LOWRSSI) {
420 if (rtlpriv->falsealm_cnt.cnt_cck_fail > 800)
421 dm_digtable->cur_cck_fa_state =
422 CCK_FA_STAGE_HIGH;
423 else
424 dm_digtable->cur_cck_fa_state =
425 CCK_FA_STAGE_LOW;
426 if (dm_digtable->pre_cck_fa_state !=
427 dm_digtable->cur_cck_fa_state) {
428 if (dm_digtable->cur_cck_fa_state ==
429 CCK_FA_STAGE_LOW)
430 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2,
431 0x83);
432 else
433 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2,
434 0xcd);
435
436 dm_digtable->pre_cck_fa_state =
437 dm_digtable->cur_cck_fa_state;
438 }
439
440 rtl_set_bbreg(hw, RCCK0_SYSTEM, MASKBYTE1, 0x40);
441
442 } else {
443 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd);
444 rtl_set_bbreg(hw, RCCK0_SYSTEM, MASKBYTE1, 0x47);
445
446 }
447 dm_digtable->pre_cck_pd_state = dm_digtable->cur_cck_pd_state;
448 }
449
450 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
451 "CCKPDStage=%x\n", dm_digtable->cur_cck_pd_state);
452
453 }
454
455 static void rtl8723e_dm_ctrl_initgain_by_twoport(struct ieee80211_hw *hw)
456 {
457 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
458 struct rtl_priv *rtlpriv = rtl_priv(hw);
459 struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
460
461 if (mac->act_scanning)
462 return;
463
464 if (mac->link_state >= MAC80211_LINKED)
465 dm_digtable->cursta_cstate = DIG_STA_CONNECT;
466 else
467 dm_digtable->cursta_cstate = DIG_STA_DISCONNECT;
468
469 rtl8723e_dm_initial_gain_sta(hw);
470 rtl8723e_dm_initial_gain_multi_sta(hw);
471 rtl8723e_dm_cck_packet_detection_thresh(hw);
472
473 dm_digtable->presta_cstate = dm_digtable->cursta_cstate;
474
475 }
476
477 static void rtl8723e_dm_dig(struct ieee80211_hw *hw)
478 {
479 struct rtl_priv *rtlpriv = rtl_priv(hw);
480 struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
481
482 if (!rtlpriv->dm.dm_initialgain_enable)
483 return;
484 if (!dm_digtable->dig_enable_flag)
485 return;
486
487 rtl8723e_dm_ctrl_initgain_by_twoport(hw);
488
489 }
490
491 static void rtl8723e_dm_dynamic_txpower(struct ieee80211_hw *hw)
492 {
493 struct rtl_priv *rtlpriv = rtl_priv(hw);
494 struct rtl_phy *rtlphy = &(rtlpriv->phy);
495 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
496 long undec_sm_pwdb;
497
498 if (!rtlpriv->dm.dynamic_txpower_enable)
499 return;
500
501 if (rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) {
502 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
503 return;
504 }
505
506 if ((mac->link_state < MAC80211_LINKED) &&
507 (rtlpriv->dm.entry_min_undec_sm_pwdb == 0)) {
508 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
509 "Not connected to any\n");
510
511 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
512
513 rtlpriv->dm.last_dtp_lvl = TXHIGHPWRLEVEL_NORMAL;
514 return;
515 }
516
517 if (mac->link_state >= MAC80211_LINKED) {
518 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
519 undec_sm_pwdb =
520 rtlpriv->dm.entry_min_undec_sm_pwdb;
521 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
522 "AP Client PWDB = 0x%lx\n",
523 undec_sm_pwdb);
524 } else {
525 undec_sm_pwdb =
526 rtlpriv->dm.undec_sm_pwdb;
527 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
528 "STA Default Port PWDB = 0x%lx\n",
529 undec_sm_pwdb);
530 }
531 } else {
532 undec_sm_pwdb =
533 rtlpriv->dm.entry_min_undec_sm_pwdb;
534
535 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
536 "AP Ext Port PWDB = 0x%lx\n",
537 undec_sm_pwdb);
538 }
539
540 if (undec_sm_pwdb >= TX_POWER_NEAR_FIELD_THRESH_LVL2) {
541 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_LEVEL1;
542 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
543 "TXHIGHPWRLEVEL_LEVEL1 (TxPwr=0x0)\n");
544 } else if ((undec_sm_pwdb <
545 (TX_POWER_NEAR_FIELD_THRESH_LVL2 - 3)) &&
546 (undec_sm_pwdb >=
547 TX_POWER_NEAR_FIELD_THRESH_LVL1)) {
548 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_LEVEL1;
549 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
550 "TXHIGHPWRLEVEL_LEVEL1 (TxPwr=0x10)\n");
551 } else if (undec_sm_pwdb <
552 (TX_POWER_NEAR_FIELD_THRESH_LVL1 - 5)) {
553 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
554 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
555 "TXHIGHPWRLEVEL_NORMAL\n");
556 }
557
558 if (rtlpriv->dm.dynamic_txhighpower_lvl != rtlpriv->dm.last_dtp_lvl) {
559 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
560 "PHY_SetTxPowerLevel8192S() Channel = %d\n",
561 rtlphy->current_channel);
562 rtl8723e_phy_set_txpower_level(hw, rtlphy->current_channel);
563 }
564
565 rtlpriv->dm.last_dtp_lvl = rtlpriv->dm.dynamic_txhighpower_lvl;
566 }
567
568 void rtl8723e_dm_write_dig(struct ieee80211_hw *hw)
569 {
570 struct rtl_priv *rtlpriv = rtl_priv(hw);
571 struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
572
573 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
574 "cur_igvalue = 0x%x, pre_igvalue = 0x%x, back_val = %d\n",
575 dm_digtable->cur_igvalue, dm_digtable->pre_igvalue,
576 dm_digtable->back_val);
577
578 if (dm_digtable->pre_igvalue != dm_digtable->cur_igvalue) {
579 rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, 0x7f,
580 dm_digtable->cur_igvalue);
581 rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, 0x7f,
582 dm_digtable->cur_igvalue);
583
584 dm_digtable->pre_igvalue = dm_digtable->cur_igvalue;
585 }
586 }
587
588 static void rtl8723e_dm_pwdb_monitor(struct ieee80211_hw *hw)
589 {
590 }
591
592 static void rtl8723e_dm_check_edca_turbo(struct ieee80211_hw *hw)
593 {
594 struct rtl_priv *rtlpriv = rtl_priv(hw);
595 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
596
597 static u64 last_txok_cnt;
598 static u64 last_rxok_cnt;
599 static u32 last_bt_edca_ul;
600 static u32 last_bt_edca_dl;
601 u64 cur_txok_cnt = 0;
602 u64 cur_rxok_cnt = 0;
603 u32 edca_be_ul = 0x5ea42b;
604 u32 edca_be_dl = 0x5ea42b;
605 bool bt_change_edca = false;
606
607 if ((last_bt_edca_ul != rtlpriv->btcoexist.bt_edca_ul) ||
608 (last_bt_edca_dl != rtlpriv->btcoexist.bt_edca_dl)) {
609 rtlpriv->dm.current_turbo_edca = false;
610 last_bt_edca_ul = rtlpriv->btcoexist.bt_edca_ul;
611 last_bt_edca_dl = rtlpriv->btcoexist.bt_edca_dl;
612 }
613
614 if (rtlpriv->btcoexist.bt_edca_ul != 0) {
615 edca_be_ul = rtlpriv->btcoexist.bt_edca_ul;
616 bt_change_edca = true;
617 }
618
619 if (rtlpriv->btcoexist.bt_edca_dl != 0) {
620 edca_be_ul = rtlpriv->btcoexist.bt_edca_dl;
621 bt_change_edca = true;
622 }
623
624 if (mac->link_state != MAC80211_LINKED) {
625 rtlpriv->dm.current_turbo_edca = false;
626 return;
627 }
628 if ((bt_change_edca) || ((!rtlpriv->dm.is_any_nonbepkts) &&
629 (!rtlpriv->dm.disable_framebursting))) {
630
631 cur_txok_cnt = rtlpriv->stats.txbytesunicast - last_txok_cnt;
632 cur_rxok_cnt = rtlpriv->stats.rxbytesunicast - last_rxok_cnt;
633
634 if (cur_rxok_cnt > 4 * cur_txok_cnt) {
635 if (!rtlpriv->dm.is_cur_rdlstate ||
636 !rtlpriv->dm.current_turbo_edca) {
637 rtl_write_dword(rtlpriv,
638 REG_EDCA_BE_PARAM,
639 edca_be_dl);
640 rtlpriv->dm.is_cur_rdlstate = true;
641 }
642 } else {
643 if (rtlpriv->dm.is_cur_rdlstate ||
644 !rtlpriv->dm.current_turbo_edca) {
645 rtl_write_dword(rtlpriv,
646 REG_EDCA_BE_PARAM,
647 edca_be_ul);
648 rtlpriv->dm.is_cur_rdlstate = false;
649 }
650 }
651 rtlpriv->dm.current_turbo_edca = true;
652 } else {
653 if (rtlpriv->dm.current_turbo_edca) {
654 u8 tmp = AC0_BE;
655 rtlpriv->cfg->ops->set_hw_reg(hw,
656 HW_VAR_AC_PARAM,
657 (u8 *)(&tmp));
658 rtlpriv->dm.current_turbo_edca = false;
659 }
660 }
661
662 rtlpriv->dm.is_any_nonbepkts = false;
663 last_txok_cnt = rtlpriv->stats.txbytesunicast;
664 last_rxok_cnt = rtlpriv->stats.rxbytesunicast;
665 }
666
667 static void rtl8723e_dm_initialize_txpower_tracking_thermalmeter(
668 struct ieee80211_hw *hw)
669 {
670 struct rtl_priv *rtlpriv = rtl_priv(hw);
671
672 rtlpriv->dm.txpower_tracking = true;
673 rtlpriv->dm.txpower_trackinginit = false;
674
675 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
676 "pMgntInfo->txpower_tracking = %d\n",
677 rtlpriv->dm.txpower_tracking);
678 }
679
680 static void rtl8723e_dm_initialize_txpower_tracking(struct ieee80211_hw *hw)
681 {
682 rtl8723e_dm_initialize_txpower_tracking_thermalmeter(hw);
683 }
684
685 void rtl8723e_dm_check_txpower_tracking(struct ieee80211_hw *hw)
686 {
687 return;
688 }
689
690 void rtl8723e_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw)
691 {
692 struct rtl_priv *rtlpriv = rtl_priv(hw);
693 struct rate_adaptive *p_ra = &(rtlpriv->ra);
694
695 p_ra->ratr_state = DM_RATR_STA_INIT;
696 p_ra->pre_ratr_state = DM_RATR_STA_INIT;
697
698 if (rtlpriv->dm.dm_type == DM_TYPE_BYDRIVER)
699 rtlpriv->dm.useramask = true;
700 else
701 rtlpriv->dm.useramask = false;
702
703 }
704
705 void rtl8723e_dm_rf_saving(struct ieee80211_hw *hw, u8 bforce_in_normal)
706 {
707 struct rtl_priv *rtlpriv = rtl_priv(hw);
708 struct ps_t *dm_pstable = &rtlpriv->dm_pstable;
709 static u8 initialize;
710 static u32 reg_874, reg_c70, reg_85c, reg_a74;
711
712 if (initialize == 0) {
713 reg_874 = (rtl_get_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
714 MASKDWORD) & 0x1CC000) >> 14;
715
716 reg_c70 = (rtl_get_bbreg(hw, ROFDM0_AGCPARAMETER1,
717 MASKDWORD) & BIT(3)) >> 3;
718
719 reg_85c = (rtl_get_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL,
720 MASKDWORD) & 0xFF000000) >> 24;
721
722 reg_a74 = (rtl_get_bbreg(hw, 0xa74, MASKDWORD) & 0xF000) >> 12;
723
724 initialize = 1;
725 }
726
727 if (!bforce_in_normal) {
728 if (dm_pstable->rssi_val_min != 0) {
729 if (dm_pstable->pre_rfstate == RF_NORMAL) {
730 if (dm_pstable->rssi_val_min >= 30)
731 dm_pstable->cur_rfstate = RF_SAVE;
732 else
733 dm_pstable->cur_rfstate = RF_NORMAL;
734 } else {
735 if (dm_pstable->rssi_val_min <= 25)
736 dm_pstable->cur_rfstate = RF_NORMAL;
737 else
738 dm_pstable->cur_rfstate = RF_SAVE;
739 }
740 } else {
741 dm_pstable->cur_rfstate = RF_MAX;
742 }
743 } else {
744 dm_pstable->cur_rfstate = RF_NORMAL;
745 }
746
747 if (dm_pstable->pre_rfstate != dm_pstable->cur_rfstate) {
748 if (dm_pstable->cur_rfstate == RF_SAVE) {
749 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
750 BIT(5), 0x1);
751 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
752 0x1C0000, 0x2);
753 rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, BIT(3), 0);
754 rtl_set_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL,
755 0xFF000000, 0x63);
756 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
757 0xC000, 0x2);
758 rtl_set_bbreg(hw, 0xa74, 0xF000, 0x3);
759 rtl_set_bbreg(hw, 0x818, BIT(28), 0x0);
760 rtl_set_bbreg(hw, 0x818, BIT(28), 0x1);
761 } else {
762 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
763 0x1CC000, reg_874);
764 rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, BIT(3),
765 reg_c70);
766 rtl_set_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL, 0xFF000000,
767 reg_85c);
768 rtl_set_bbreg(hw, 0xa74, 0xF000, reg_a74);
769 rtl_set_bbreg(hw, 0x818, BIT(28), 0x0);
770 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
771 BIT(5), 0x0);
772 }
773
774 dm_pstable->pre_rfstate = dm_pstable->cur_rfstate;
775 }
776 }
777
778 static void rtl8723e_dm_dynamic_bb_powersaving(struct ieee80211_hw *hw)
779 {
780 struct rtl_priv *rtlpriv = rtl_priv(hw);
781 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
782 struct ps_t *dm_pstable = &rtlpriv->dm_pstable;
783
784 if (((mac->link_state == MAC80211_NOLINK)) &&
785 (rtlpriv->dm.entry_min_undec_sm_pwdb == 0)) {
786 dm_pstable->rssi_val_min = 0;
787 RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
788 "Not connected to any\n");
789 }
790
791 if (mac->link_state == MAC80211_LINKED) {
792 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
793 dm_pstable->rssi_val_min =
794 rtlpriv->dm.entry_min_undec_sm_pwdb;
795 RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
796 "AP Client PWDB = 0x%lx\n",
797 dm_pstable->rssi_val_min);
798 } else {
799 dm_pstable->rssi_val_min =
800 rtlpriv->dm.undec_sm_pwdb;
801 RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
802 "STA Default Port PWDB = 0x%lx\n",
803 dm_pstable->rssi_val_min);
804 }
805 } else {
806 dm_pstable->rssi_val_min =
807 rtlpriv->dm.entry_min_undec_sm_pwdb;
808
809 RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
810 "AP Ext Port PWDB = 0x%lx\n",
811 dm_pstable->rssi_val_min);
812 }
813
814 rtl8723e_dm_rf_saving(hw, false);
815 }
816
817 void rtl8723e_dm_init(struct ieee80211_hw *hw)
818 {
819 struct rtl_priv *rtlpriv = rtl_priv(hw);
820
821 rtlpriv->dm.dm_type = DM_TYPE_BYDRIVER;
822 rtl8723e_dm_diginit(hw);
823 rtl8723_dm_init_dynamic_txpower(hw);
824 rtl8723_dm_init_edca_turbo(hw);
825 rtl8723e_dm_init_rate_adaptive_mask(hw);
826 rtl8723e_dm_initialize_txpower_tracking(hw);
827 rtl8723_dm_init_dynamic_bb_powersaving(hw);
828 }
829
830 void rtl8723e_dm_watchdog(struct ieee80211_hw *hw)
831 {
832 struct rtl_priv *rtlpriv = rtl_priv(hw);
833 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
834 bool fw_current_inpsmode = false;
835 bool fw_ps_awake = true;
836 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
837 (u8 *)(&fw_current_inpsmode));
838 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FWLPS_RF_ON,
839 (u8 *)(&fw_ps_awake));
840
841 if (ppsc->p2p_ps_info.p2p_ps_mode)
842 fw_ps_awake = false;
843
844 if ((ppsc->rfpwr_state == ERFON) &&
845 ((!fw_current_inpsmode) && fw_ps_awake) &&
846 (!ppsc->rfchange_inprogress)) {
847 rtl8723e_dm_pwdb_monitor(hw);
848 rtl8723e_dm_dig(hw);
849 rtl8723e_dm_false_alarm_counter_statistics(hw);
850 rtl8723e_dm_dynamic_bb_powersaving(hw);
851 rtl8723e_dm_dynamic_txpower(hw);
852 rtl8723e_dm_check_txpower_tracking(hw);
853 /* rtl92c_dm_refresh_rate_adaptive_mask(hw); */
854 rtl8723e_dm_bt_coexist(hw);
855 rtl8723e_dm_check_edca_turbo(hw);
856 }
857 if (rtlpriv->btcoexist.init_set)
858 rtl_write_byte(rtlpriv, 0x76e, 0xc);
859 }
860
861 static void rtl8723e_dm_init_bt_coexist(struct ieee80211_hw *hw)
862 {
863 struct rtl_priv *rtlpriv = rtl_priv(hw);
864
865 rtlpriv->btcoexist.bt_rfreg_origin_1e
866 = rtl_get_rfreg(hw, (enum radio_path)0, RF_RCK1, 0xfffff);
867 rtlpriv->btcoexist.bt_rfreg_origin_1f
868 = rtl_get_rfreg(hw, (enum radio_path)0, RF_RCK2, 0xf0);
869
870 rtlpriv->btcoexist.cstate = 0;
871 rtlpriv->btcoexist.previous_state = 0;
872 rtlpriv->btcoexist.cstate_h = 0;
873 rtlpriv->btcoexist.previous_state_h = 0;
874 rtlpriv->btcoexist.lps_counter = 0;
875
876 /* Enable counter statistics */
877 rtl_write_byte(rtlpriv, 0x76e, 0x4);
878 rtl_write_byte(rtlpriv, 0x778, 0x3);
879 rtl_write_byte(rtlpriv, 0x40, 0x20);
880
881 rtlpriv->btcoexist.init_set = true;
882 }
883
884 void rtl8723e_dm_bt_coexist(struct ieee80211_hw *hw)
885 {
886 struct rtl_priv *rtlpriv = rtl_priv(hw);
887 u8 tmp_byte = 0;
888 if (!rtlpriv->btcoexist.bt_coexistence) {
889 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
890 "[DM]{BT], BT not exist!!\n");
891 return;
892 }
893
894 if (!rtlpriv->btcoexist.init_set) {
895 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
896 "[DM][BT], rtl8723e_dm_bt_coexist()\n");
897 rtl8723e_dm_init_bt_coexist(hw);
898 }
899
900 tmp_byte = rtl_read_byte(rtlpriv, 0x40);
901 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
902 "[DM][BT], 0x40 is 0x%x", tmp_byte);
903 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
904 "[DM][BT], bt_dm_coexist start");
905 rtl8723e_dm_bt_coexist_8723(hw);
906 }
Linux kernel - Deliverables
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