drivers/net/wireless/rtlwifi/rtl8723ae/dm.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2012  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * The full GNU General Public License is included in this distribution in the
  15  * file called LICENSE.
  16  *
  17  * Contact Information:
  18  * wlanfae <wlanfae@realtek.com>
  19  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20  * Hsinchu 300, Taiwan.
  21  *
  22  * Larry Finger <Larry.Finger@lwfinger.net>
  23  *
  24  *****************************************************************************/
  25
  26 #include "../wifi.h"
  27 #include "../base.h"
  28 #include "../pci.h"
  29 #include "reg.h"
  30 #include "def.h"
  31 #include "phy.h"
  32 #include "dm.h"
  33 #include "../rtl8723com/dm_common.h"
  34 #include "fw.h"
  35 #include "hal_btc.h"
  36
  37 static const u32 ofdmswing_table[OFDM_TABLE_SIZE] = {
  38         0x7f8001fe,
  39         0x788001e2,
  40         0x71c001c7,
  41         0x6b8001ae,
  42         0x65400195,
  43         0x5fc0017f,
  44         0x5a400169,
  45         0x55400155,
  46         0x50800142,
  47         0x4c000130,
  48         0x47c0011f,
  49         0x43c0010f,
  50         0x40000100,
  51         0x3c8000f2,
  52         0x390000e4,
  53         0x35c000d7,
  54         0x32c000cb,
  55         0x300000c0,
  56         0x2d4000b5,
  57         0x2ac000ab,
  58         0x288000a2,
  59         0x26000098,
  60         0x24000090,
  61         0x22000088,
  62         0x20000080,
  63         0x1e400079,
  64         0x1c800072,
  65         0x1b00006c,
  66         0x19800066,
  67         0x18000060,
  68         0x16c0005b,
  69         0x15800056,
  70         0x14400051,
  71         0x1300004c,
  72         0x12000048,
  73         0x11000044,
  74         0x10000040,
  75 };
  76
  77 static const u8 cckswing_table_ch1ch13[CCK_TABLE_SIZE][8] = {
  78         {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04},
  79         {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04},
  80         {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03},
  81         {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03},
  82         {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03},
  83         {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03},
  84         {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03},
  85         {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03},
  86         {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02},
  87         {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02},
  88         {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02},
  89         {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02},
  90         {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02},
  91         {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02},
  92         {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02},
  93         {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02},
  94         {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01},
  95         {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02},
  96         {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01},
  97         {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},
  98         {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},
  99         {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01},
 100         {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01},
 101         {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01},
 102         {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01},
 103         {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01},
 104         {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01},
 105         {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01},
 106         {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01},
 107         {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01},
 108         {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01},
 109         {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},
 110         {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}
 111 };
 112
 113 static const u8 cckswing_table_ch14[CCK_TABLE_SIZE][8] = {
 114         {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00},
 115         {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00},
 116         {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00},
 117         {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00},
 118         {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00},
 119         {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00},
 120         {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00},
 121         {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00},
 122         {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00},
 123         {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00},
 124         {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00},
 125         {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00},
 126         {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00},
 127         {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00},
 128         {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00},
 129         {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00},
 130         {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00},
 131         {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00},
 132         {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00},
 133         {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},
 134         {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},
 135         {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00},
 136         {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00},
 137         {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},
 138         {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},
 139         {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00},
 140         {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},
 141         {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},
 142         {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},
 143         {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},
 144         {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},
 145         {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},
 146         {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}
 147 };
 148
 149 static void rtl8723e_dm_diginit(struct ieee80211_hw *hw)
 150 {
 151         struct rtl_priv *rtlpriv = rtl_priv(hw);
 152         struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
 153
 154         dm_digtable->dig_enable_flag = true;
 155         dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
 156         dm_digtable->cur_igvalue = 0x20;
 157         dm_digtable->pre_igvalue = 0x0;
 158         dm_digtable->cursta_cstate = DIG_STA_DISCONNECT;
 159         dm_digtable->presta_cstate = DIG_STA_DISCONNECT;
 160         dm_digtable->curmultista_cstate = DIG_MULTISTA_DISCONNECT;
 161         dm_digtable->rssi_lowthresh = DM_DIG_THRESH_LOW;
 162         dm_digtable->rssi_highthresh = DM_DIG_THRESH_HIGH;
 163         dm_digtable->fa_lowthresh = DM_FALSEALARM_THRESH_LOW;
 164         dm_digtable->fa_highthresh = DM_FALSEALARM_THRESH_HIGH;
 165         dm_digtable->rx_gain_max = DM_DIG_MAX;
 166         dm_digtable->rx_gain_min = DM_DIG_MIN;
 167         dm_digtable->back_val = DM_DIG_BACKOFF_DEFAULT;
 168         dm_digtable->back_range_max = DM_DIG_BACKOFF_MAX;
 169         dm_digtable->back_range_min = DM_DIG_BACKOFF_MIN;
 170         dm_digtable->pre_cck_pd_state = CCK_PD_STAGE_MAX;
 171         dm_digtable->cur_cck_pd_state = CCK_PD_STAGE_MAX;
 172 }
 173
 174 static u8 rtl8723e_dm_initial_gain_min_pwdb(struct ieee80211_hw *hw)
 175 {
 176         struct rtl_priv *rtlpriv = rtl_priv(hw);
 177         struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
 178         long rssi_val_min = 0;
 179
 180         if ((dm_digtable->curmultista_cstate == DIG_MULTISTA_CONNECT) &&
 181             (dm_digtable->cursta_cstate == DIG_STA_CONNECT)) {
 182                 if (rtlpriv->dm.entry_min_undec_sm_pwdb != 0)
 183                         rssi_val_min =
 184                             (rtlpriv->dm.entry_min_undec_sm_pwdb >
 185                              rtlpriv->dm.undec_sm_pwdb) ?
 186                             rtlpriv->dm.undec_sm_pwdb :
 187                             rtlpriv->dm.entry_min_undec_sm_pwdb;
 188                 else
 189                         rssi_val_min = rtlpriv->dm.undec_sm_pwdb;
 190         } else if (dm_digtable->cursta_cstate == DIG_STA_CONNECT ||
 191                    dm_digtable->cursta_cstate == DIG_STA_BEFORE_CONNECT) {
 192                 rssi_val_min = rtlpriv->dm.undec_sm_pwdb;
 193         } else if (dm_digtable->curmultista_cstate ==
 194                 DIG_MULTISTA_CONNECT) {
 195                 rssi_val_min = rtlpriv->dm.entry_min_undec_sm_pwdb;
 196         }
 197
 198         return (u8) rssi_val_min;
 199 }
 200
 201 static void rtl8723e_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw)
 202 {
 203         u32 ret_value;
 204         struct rtl_priv *rtlpriv = rtl_priv(hw);
 205         struct false_alarm_statistics *falsealm_cnt = &(rtlpriv->falsealm_cnt);
 206
 207         ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER1, MASKDWORD);
 208         falsealm_cnt->cnt_parity_fail = ((ret_value & 0xffff0000) >> 16);
 209
 210         ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER2, MASKDWORD);
 211         falsealm_cnt->cnt_rate_illegal = (ret_value & 0xffff);
 212         falsealm_cnt->cnt_crc8_fail = ((ret_value & 0xffff0000) >> 16);
 213
 214         ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER3, MASKDWORD);
 215         falsealm_cnt->cnt_mcs_fail = (ret_value & 0xffff);
 216         falsealm_cnt->cnt_ofdm_fail = falsealm_cnt->cnt_parity_fail +
 217             falsealm_cnt->cnt_rate_illegal +
 218             falsealm_cnt->cnt_crc8_fail + falsealm_cnt->cnt_mcs_fail;
 219
 220         rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, BIT(14), 1);
 221         ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERLOWER, MASKBYTE0);
 222         falsealm_cnt->cnt_cck_fail = ret_value;
 223
 224         ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERUPPER, MASKBYTE3);
 225         falsealm_cnt->cnt_cck_fail += (ret_value & 0xff) << 8;
 226         falsealm_cnt->cnt_all = (falsealm_cnt->cnt_parity_fail +
 227                                  falsealm_cnt->cnt_rate_illegal +
 228                                  falsealm_cnt->cnt_crc8_fail +
 229                                  falsealm_cnt->cnt_mcs_fail +
 230                                  falsealm_cnt->cnt_cck_fail);
 231
 232         rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 1);
 233         rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 0);
 234         rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 0);
 235         rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 2);
 236
 237         RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
 238                  "cnt_parity_fail = %d, cnt_rate_illegal = %d, cnt_crc8_fail = %d, cnt_mcs_fail = %d\n",
 239                  falsealm_cnt->cnt_parity_fail,
 240                  falsealm_cnt->cnt_rate_illegal,
 241                  falsealm_cnt->cnt_crc8_fail, falsealm_cnt->cnt_mcs_fail);
 242
 243         RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
 244                  "cnt_ofdm_fail = %x, cnt_cck_fail = %x, cnt_all = %x\n",
 245                  falsealm_cnt->cnt_ofdm_fail,
 246                  falsealm_cnt->cnt_cck_fail, falsealm_cnt->cnt_all);
 247 }
 248
 249 static void rtl92c_dm_ctrl_initgain_by_fa(struct ieee80211_hw *hw)
 250 {
 251         struct rtl_priv *rtlpriv = rtl_priv(hw);
 252         struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
 253         u8 value_igi = dm_digtable->cur_igvalue;
 254
 255         if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH0)
 256                 value_igi--;
 257         else if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH1)
 258                 value_igi += 0;
 259         else if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH2)
 260                 value_igi++;
 261         else if (rtlpriv->falsealm_cnt.cnt_all >= DM_DIG_FA_TH2)
 262                 value_igi += 2;
 263         if (value_igi > DM_DIG_FA_UPPER)
 264                 value_igi = DM_DIG_FA_UPPER;
 265         else if (value_igi < DM_DIG_FA_LOWER)
 266                 value_igi = DM_DIG_FA_LOWER;
 267         if (rtlpriv->falsealm_cnt.cnt_all > 10000)
 268                 value_igi = 0x32;
 269
 270         dm_digtable->cur_igvalue = value_igi;
 271         rtl8723e_dm_write_dig(hw);
 272 }
 273
 274 static void rtl92c_dm_ctrl_initgain_by_rssi(struct ieee80211_hw *hw)
 275 {
 276         struct rtl_priv *rtlpriv = rtl_priv(hw);
 277         struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
 278
 279         if (rtlpriv->falsealm_cnt.cnt_all > dm_digtable->fa_highthresh) {
 280                 if ((dm_digtable->back_val - 2) <
 281                     dm_digtable->back_range_min)
 282                         dm_digtable->back_val =
 283                             dm_digtable->back_range_min;
 284                 else
 285                         dm_digtable->back_val -= 2;
 286         } else if (rtlpriv->falsealm_cnt.cnt_all < dm_digtable->fa_lowthresh) {
 287                 if ((dm_digtable->back_val + 2) >
 288                     dm_digtable->back_range_max)
 289                         dm_digtable->back_val =
 290                             dm_digtable->back_range_max;
 291                 else
 292                         dm_digtable->back_val += 2;
 293         }
 294
 295         if ((dm_digtable->rssi_val_min + 10 - dm_digtable->back_val) >
 296             dm_digtable->rx_gain_max)
 297                 dm_digtable->cur_igvalue = dm_digtable->rx_gain_max;
 298         else if ((dm_digtable->rssi_val_min + 10 -
 299                   dm_digtable->back_val) < dm_digtable->rx_gain_min)
 300                 dm_digtable->cur_igvalue = dm_digtable->rx_gain_min;
 301         else
 302                 dm_digtable->cur_igvalue = dm_digtable->rssi_val_min + 10 -
 303                     dm_digtable->back_val;
 304
 305         RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
 306                  "rssi_val_min = %x back_val %x\n",
 307                   dm_digtable->rssi_val_min, dm_digtable->back_val);
 308
 309         rtl8723e_dm_write_dig(hw);
 310 }
 311
 312 static void rtl8723e_dm_initial_gain_multi_sta(struct ieee80211_hw *hw)
 313 {
 314         static u8 binitialized;
 315         struct rtl_priv *rtlpriv = rtl_priv(hw);
 316         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 317         struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
 318         long rssi_strength = rtlpriv->dm.entry_min_undec_sm_pwdb;
 319         bool multi_sta = false;
 320
 321         if (mac->opmode == NL80211_IFTYPE_ADHOC)
 322                 multi_sta = true;
 323
 324         if (!multi_sta || (dm_digtable->cursta_cstate != DIG_STA_DISCONNECT)) {
 325                 binitialized = false;
 326                 dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
 327                 return;
 328         } else if (!binitialized) {
 329                 binitialized = true;
 330                 dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_0;
 331                 dm_digtable->cur_igvalue = 0x20;
 332                 rtl8723e_dm_write_dig(hw);
 333         }
 334
 335         if (dm_digtable->curmultista_cstate == DIG_MULTISTA_CONNECT) {
 336                 if ((rssi_strength < dm_digtable->rssi_lowthresh) &&
 337                     (dm_digtable->dig_ext_port_stage != DIG_EXT_PORT_STAGE_1)) {
 338
 339                         if (dm_digtable->dig_ext_port_stage ==
 340                             DIG_EXT_PORT_STAGE_2) {
 341                                 dm_digtable->cur_igvalue = 0x20;
 342                                 rtl8723e_dm_write_dig(hw);
 343                         }
 344
 345                         dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_1;
 346                 } else if (rssi_strength > dm_digtable->rssi_highthresh) {
 347                         dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_2;
 348                         rtl92c_dm_ctrl_initgain_by_fa(hw);
 349                 }
 350         } else if (dm_digtable->dig_ext_port_stage != DIG_EXT_PORT_STAGE_0) {
 351                 dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_0;
 352                 dm_digtable->cur_igvalue = 0x20;
 353                 rtl8723e_dm_write_dig(hw);
 354         }
 355
 356         RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
 357                  "curmultista_cstate = %x dig_ext_port_stage %x\n",
 358                  dm_digtable->curmultista_cstate,
 359                  dm_digtable->dig_ext_port_stage);
 360 }
 361
 362 static void rtl8723e_dm_initial_gain_sta(struct ieee80211_hw *hw)
 363 {
 364         struct rtl_priv *rtlpriv = rtl_priv(hw);
 365         struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
 366
 367         RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
 368                  "presta_cstate = %x, cursta_cstate = %x\n",
 369                   dm_digtable->presta_cstate,
 370                   dm_digtable->cursta_cstate);
 371
 372         if (dm_digtable->presta_cstate == dm_digtable->cursta_cstate ||
 373             dm_digtable->cursta_cstate == DIG_STA_BEFORE_CONNECT ||
 374             dm_digtable->cursta_cstate == DIG_STA_CONNECT) {
 375                 if (dm_digtable->cursta_cstate != DIG_STA_DISCONNECT) {
 376                         dm_digtable->rssi_val_min =
 377                             rtl8723e_dm_initial_gain_min_pwdb(hw);
 378                         rtl92c_dm_ctrl_initgain_by_rssi(hw);
 379                 }
 380         } else {
 381                 dm_digtable->rssi_val_min = 0;
 382                 dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
 383                 dm_digtable->back_val = DM_DIG_BACKOFF_DEFAULT;
 384                 dm_digtable->cur_igvalue = 0x20;
 385                 dm_digtable->pre_igvalue = 0;
 386                 rtl8723e_dm_write_dig(hw);
 387         }
 388 }
 389
 390 static void rtl8723e_dm_cck_packet_detection_thresh(struct ieee80211_hw *hw)
 391 {
 392         struct rtl_priv *rtlpriv = rtl_priv(hw);
 393         struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
 394
 395         if (dm_digtable->cursta_cstate == DIG_STA_CONNECT) {
 396                 dm_digtable->rssi_val_min = rtl8723e_dm_initial_gain_min_pwdb(hw);
 397
 398                 if (dm_digtable->pre_cck_pd_state == CCK_PD_STAGE_LowRssi) {
 399                         if (dm_digtable->rssi_val_min <= 25)
 400                                 dm_digtable->cur_cck_pd_state =
 401                                     CCK_PD_STAGE_LowRssi;
 402                         else
 403                                 dm_digtable->cur_cck_pd_state =
 404                                     CCK_PD_STAGE_HighRssi;
 405                 } else {
 406                         if (dm_digtable->rssi_val_min <= 20)
 407                                 dm_digtable->cur_cck_pd_state =
 408                                     CCK_PD_STAGE_LowRssi;
 409                         else
 410                                 dm_digtable->cur_cck_pd_state =
 411                                     CCK_PD_STAGE_HighRssi;
 412                 }
 413         } else {
 414                 dm_digtable->cur_cck_pd_state = CCK_PD_STAGE_MAX;
 415         }
 416
 417         if (dm_digtable->pre_cck_pd_state != dm_digtable->cur_cck_pd_state) {
 418                 if (dm_digtable->cur_cck_pd_state == CCK_PD_STAGE_LowRssi) {
 419                         if (rtlpriv->falsealm_cnt.cnt_cck_fail > 800)
 420                                 dm_digtable->cur_cck_fa_state =
 421                                     CCK_FA_STAGE_High;
 422                         else
 423                                 dm_digtable->cur_cck_fa_state =
 424                                     CCK_FA_STAGE_LOW;
 425                         if (dm_digtable->pre_cck_fa_state !=
 426                             dm_digtable->cur_cck_fa_state) {
 427                                 if (dm_digtable->cur_cck_fa_state ==
 428                                     CCK_FA_STAGE_LOW)
 429                                         rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2,
 430                                                       0x83);
 431                                 else
 432                                         rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2,
 433                                                       0xcd);
 434
 435                                 dm_digtable->pre_cck_fa_state =
 436                                     dm_digtable->cur_cck_fa_state;
 437                         }
 438
 439                         rtl_set_bbreg(hw, RCCK0_SYSTEM, MASKBYTE1, 0x40);
 440
 441                 } else {
 442                         rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd);
 443                         rtl_set_bbreg(hw, RCCK0_SYSTEM, MASKBYTE1, 0x47);
 444
 445                 }
 446                 dm_digtable->pre_cck_pd_state = dm_digtable->cur_cck_pd_state;
 447         }
 448
 449         RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
 450                  "CCKPDStage=%x\n", dm_digtable->cur_cck_pd_state);
 451
 452 }
 453
 454 static void rtl8723e_dm_ctrl_initgain_by_twoport(struct ieee80211_hw *hw)
 455 {
 456         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 457         struct rtl_priv *rtlpriv = rtl_priv(hw);
 458         struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
 459
 460         if (mac->act_scanning)
 461                 return;
 462
 463         if (mac->link_state >= MAC80211_LINKED)
 464                 dm_digtable->cursta_cstate = DIG_STA_CONNECT;
 465         else
 466                 dm_digtable->cursta_cstate = DIG_STA_DISCONNECT;
 467
 468         rtl8723e_dm_initial_gain_sta(hw);
 469         rtl8723e_dm_initial_gain_multi_sta(hw);
 470         rtl8723e_dm_cck_packet_detection_thresh(hw);
 471
 472         dm_digtable->presta_cstate = dm_digtable->cursta_cstate;
 473
 474 }
 475
 476 static void rtl8723e_dm_dig(struct ieee80211_hw *hw)
 477 {
 478         struct rtl_priv *rtlpriv = rtl_priv(hw);
 479         struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
 480
 481         if (!rtlpriv->dm.dm_initialgain_enable)
 482                 return;
 483         if (!dm_digtable->dig_enable_flag)
 484                 return;
 485
 486         rtl8723e_dm_ctrl_initgain_by_twoport(hw);
 487
 488 }
 489
 490 static void rtl8723e_dm_dynamic_txpower(struct ieee80211_hw *hw)
 491 {
 492         struct rtl_priv *rtlpriv = rtl_priv(hw);
 493         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 494         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 495         long undec_sm_pwdb;
 496
 497         if (!rtlpriv->dm.dynamic_txpower_enable)
 498                 return;
 499
 500         if (rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) {
 501                 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
 502                 return;
 503         }
 504
 505         if ((mac->link_state < MAC80211_LINKED) &&
 506             (rtlpriv->dm.entry_min_undec_sm_pwdb == 0)) {
 507                 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
 508                          "Not connected to any\n");
 509
 510                 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
 511
 512                 rtlpriv->dm.last_dtp_lvl = TXHIGHPWRLEVEL_NORMAL;
 513                 return;
 514         }
 515
 516         if (mac->link_state >= MAC80211_LINKED) {
 517                 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
 518                         undec_sm_pwdb =
 519                             rtlpriv->dm.entry_min_undec_sm_pwdb;
 520                         RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
 521                                  "AP Client PWDB = 0x%lx\n",
 522                                   undec_sm_pwdb);
 523                 } else {
 524                         undec_sm_pwdb =
 525                             rtlpriv->dm.undec_sm_pwdb;
 526                         RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
 527                                  "STA Default Port PWDB = 0x%lx\n",
 528                                   undec_sm_pwdb);
 529                 }
 530         } else {
 531                 undec_sm_pwdb =
 532                     rtlpriv->dm.entry_min_undec_sm_pwdb;
 533
 534                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
 535                          "AP Ext Port PWDB = 0x%lx\n",
 536                           undec_sm_pwdb);
 537         }
 538
 539         if (undec_sm_pwdb >= TX_POWER_NEAR_FIELD_THRESH_LVL2) {
 540                 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_LEVEL1;
 541                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
 542                          "TXHIGHPWRLEVEL_LEVEL1 (TxPwr=0x0)\n");
 543         } else if ((undec_sm_pwdb <
 544                     (TX_POWER_NEAR_FIELD_THRESH_LVL2 - 3)) &&
 545                    (undec_sm_pwdb >=
 546                     TX_POWER_NEAR_FIELD_THRESH_LVL1)) {
 547                 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_LEVEL1;
 548                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
 549                          "TXHIGHPWRLEVEL_LEVEL1 (TxPwr=0x10)\n");
 550         } else if (undec_sm_pwdb <
 551                    (TX_POWER_NEAR_FIELD_THRESH_LVL1 - 5)) {
 552                 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
 553                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
 554                          "TXHIGHPWRLEVEL_NORMAL\n");
 555         }
 556
 557         if (rtlpriv->dm.dynamic_txhighpower_lvl != rtlpriv->dm.last_dtp_lvl) {
 558                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
 559                          "PHY_SetTxPowerLevel8192S() Channel = %d\n",
 560                           rtlphy->current_channel);
 561                 rtl8723e_phy_set_txpower_level(hw, rtlphy->current_channel);
 562         }
 563
 564         rtlpriv->dm.last_dtp_lvl = rtlpriv->dm.dynamic_txhighpower_lvl;
 565 }
 566
 567 void rtl8723e_dm_write_dig(struct ieee80211_hw *hw)
 568 {
 569         struct rtl_priv *rtlpriv = rtl_priv(hw);
 570         struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
 571
 572         RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
 573                  "cur_igvalue = 0x%x, pre_igvalue = 0x%x, back_val = %d\n",
 574                   dm_digtable->cur_igvalue, dm_digtable->pre_igvalue,
 575                   dm_digtable->back_val);
 576
 577         if (dm_digtable->pre_igvalue != dm_digtable->cur_igvalue) {
 578                 rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, 0x7f,
 579                               dm_digtable->cur_igvalue);
 580                 rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, 0x7f,
 581                               dm_digtable->cur_igvalue);
 582
 583                 dm_digtable->pre_igvalue = dm_digtable->cur_igvalue;
 584         }
 585 }
 586
 587 static void rtl8723e_dm_pwdb_monitor(struct ieee80211_hw *hw)
 588 {
 589 }
 590
 591 static void rtl8723e_dm_check_edca_turbo(struct ieee80211_hw *hw)
 592 {
 593         struct rtl_priv *rtlpriv = rtl_priv(hw);
 594         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 595
 596         static u64 last_txok_cnt;
 597         static u64 last_rxok_cnt;
 598         static u32 last_bt_edca_ul;
 599         static u32 last_bt_edca_dl;
 600         u64 cur_txok_cnt = 0;
 601         u64 cur_rxok_cnt = 0;
 602         u32 edca_be_ul = 0x5ea42b;
 603         u32 edca_be_dl = 0x5ea42b;
 604         bool bt_change_edca = false;
 605
 606         if ((last_bt_edca_ul != rtlpriv->btcoexist.bt_edca_ul) ||
 607             (last_bt_edca_dl != rtlpriv->btcoexist.bt_edca_dl)) {
 608                 rtlpriv->dm.current_turbo_edca = false;
 609                 last_bt_edca_ul = rtlpriv->btcoexist.bt_edca_ul;
 610                 last_bt_edca_dl = rtlpriv->btcoexist.bt_edca_dl;
 611         }
 612
 613         if (rtlpriv->btcoexist.bt_edca_ul != 0) {
 614                 edca_be_ul = rtlpriv->btcoexist.bt_edca_ul;
 615                 bt_change_edca = true;
 616         }
 617
 618         if (rtlpriv->btcoexist.bt_edca_dl != 0) {
 619                 edca_be_ul = rtlpriv->btcoexist.bt_edca_dl;
 620                 bt_change_edca = true;
 621         }
 622
 623         if (mac->link_state != MAC80211_LINKED) {
 624                 rtlpriv->dm.current_turbo_edca = false;
 625                 return;
 626         }
 627         if ((bt_change_edca) || ((!rtlpriv->dm.is_any_nonbepkts) &&
 628              (!rtlpriv->dm.disable_framebursting))) {
 629
 630                 cur_txok_cnt = rtlpriv->stats.txbytesunicast - last_txok_cnt;
 631                 cur_rxok_cnt = rtlpriv->stats.rxbytesunicast - last_rxok_cnt;
 632
 633                 if (cur_rxok_cnt > 4 * cur_txok_cnt) {
 634                         if (!rtlpriv->dm.is_cur_rdlstate ||
 635                             !rtlpriv->dm.current_turbo_edca) {
 636                                 rtl_write_dword(rtlpriv,
 637                                                 REG_EDCA_BE_PARAM,
 638                                                 edca_be_dl);
 639                                 rtlpriv->dm.is_cur_rdlstate = true;
 640                         }
 641                 } else {
 642                         if (rtlpriv->dm.is_cur_rdlstate ||
 643                             !rtlpriv->dm.current_turbo_edca) {
 644                                 rtl_write_dword(rtlpriv,
 645                                                 REG_EDCA_BE_PARAM,
 646                                                 edca_be_ul);
 647                                 rtlpriv->dm.is_cur_rdlstate = false;
 648                         }
 649                 }
 650                 rtlpriv->dm.current_turbo_edca = true;
 651         } else {
 652                 if (rtlpriv->dm.current_turbo_edca) {
 653                         u8 tmp = AC0_BE;
 654                         rtlpriv->cfg->ops->set_hw_reg(hw,
 655                                                       HW_VAR_AC_PARAM,
 656                                                       (u8 *)(&tmp));
 657                         rtlpriv->dm.current_turbo_edca = false;
 658                 }
 659         }
 660
 661         rtlpriv->dm.is_any_nonbepkts = false;
 662         last_txok_cnt = rtlpriv->stats.txbytesunicast;
 663         last_rxok_cnt = rtlpriv->stats.rxbytesunicast;
 664 }
 665
 666 static void rtl8723e_dm_initialize_txpower_tracking_thermalmeter(
 667                                 struct ieee80211_hw *hw)
 668 {
 669         struct rtl_priv *rtlpriv = rtl_priv(hw);
 670
 671         rtlpriv->dm.txpower_tracking = true;
 672         rtlpriv->dm.txpower_trackinginit = false;
 673
 674         RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
 675                  "pMgntInfo->txpower_tracking = %d\n",
 676                   rtlpriv->dm.txpower_tracking);
 677 }
 678
 679 static void rtl8723e_dm_initialize_txpower_tracking(struct ieee80211_hw *hw)
 680 {
 681         rtl8723e_dm_initialize_txpower_tracking_thermalmeter(hw);
 682 }
 683
 684 void rtl8723e_dm_check_txpower_tracking(struct ieee80211_hw *hw)
 685 {
 686         return;
 687 }
 688
 689 void rtl8723e_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw)
 690 {
 691         struct rtl_priv *rtlpriv = rtl_priv(hw);
 692         struct rate_adaptive *p_ra = &(rtlpriv->ra);
 693
 694         p_ra->ratr_state = DM_RATR_STA_INIT;
 695         p_ra->pre_ratr_state = DM_RATR_STA_INIT;
 696
 697         if (rtlpriv->dm.dm_type == DM_TYPE_BYDRIVER)
 698                 rtlpriv->dm.useramask = true;
 699         else
 700                 rtlpriv->dm.useramask = false;
 701
 702 }
 703
 704 void rtl8723e_dm_rf_saving(struct ieee80211_hw *hw, u8 bforce_in_normal)
 705 {
 706         struct rtl_priv *rtlpriv = rtl_priv(hw);
 707         struct ps_t *dm_pstable = &rtlpriv->dm_pstable;
 708         static u8 initialize;
 709         static u32 reg_874, reg_c70, reg_85c, reg_a74;
 710
 711         if (initialize == 0) {
 712                 reg_874 = (rtl_get_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
 713                                          MASKDWORD) & 0x1CC000) >> 14;
 714
 715                 reg_c70 = (rtl_get_bbreg(hw, ROFDM0_AGCPARAMETER1,
 716                                          MASKDWORD) & BIT(3)) >> 3;
 717
 718                 reg_85c = (rtl_get_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL,
 719                                          MASKDWORD) & 0xFF000000) >> 24;
 720
 721                 reg_a74 = (rtl_get_bbreg(hw, 0xa74, MASKDWORD) & 0xF000) >> 12;
 722
 723                 initialize = 1;
 724         }
 725
 726         if (!bforce_in_normal) {
 727                 if (dm_pstable->rssi_val_min != 0) {
 728                         if (dm_pstable->pre_rfstate == RF_NORMAL) {
 729                                 if (dm_pstable->rssi_val_min >= 30)
 730                                         dm_pstable->cur_rfstate = RF_SAVE;
 731                                 else
 732                                         dm_pstable->cur_rfstate = RF_NORMAL;
 733                         } else {
 734                                 if (dm_pstable->rssi_val_min <= 25)
 735                                         dm_pstable->cur_rfstate = RF_NORMAL;
 736                                 else
 737                                         dm_pstable->cur_rfstate = RF_SAVE;
 738                         }
 739                 } else {
 740                         dm_pstable->cur_rfstate = RF_MAX;
 741                 }
 742         } else {
 743                 dm_pstable->cur_rfstate = RF_NORMAL;
 744         }
 745
 746         if (dm_pstable->pre_rfstate != dm_pstable->cur_rfstate) {
 747                 if (dm_pstable->cur_rfstate == RF_SAVE) {
 748                         rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
 749                                       BIT(5), 0x1);
 750                         rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
 751                                       0x1C0000, 0x2);
 752                         rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, BIT(3), 0);
 753                         rtl_set_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL,
 754                                       0xFF000000, 0x63);
 755                         rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
 756                                       0xC000, 0x2);
 757                         rtl_set_bbreg(hw, 0xa74, 0xF000, 0x3);
 758                         rtl_set_bbreg(hw, 0x818, BIT(28), 0x0);
 759                         rtl_set_bbreg(hw, 0x818, BIT(28), 0x1);
 760                 } else {
 761                         rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
 762                                       0x1CC000, reg_874);
 763                         rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, BIT(3),
 764                                       reg_c70);
 765                         rtl_set_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL, 0xFF000000,
 766                                       reg_85c);
 767                         rtl_set_bbreg(hw, 0xa74, 0xF000, reg_a74);
 768                         rtl_set_bbreg(hw, 0x818, BIT(28), 0x0);
 769                         rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
 770                                       BIT(5), 0x0);
 771                 }
 772
 773                 dm_pstable->pre_rfstate = dm_pstable->cur_rfstate;
 774         }
 775 }
 776
 777 static void rtl8723e_dm_dynamic_bb_powersaving(struct ieee80211_hw *hw)
 778 {
 779         struct rtl_priv *rtlpriv = rtl_priv(hw);
 780         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 781         struct ps_t *dm_pstable = &rtlpriv->dm_pstable;
 782
 783         if (((mac->link_state == MAC80211_NOLINK)) &&
 784             (rtlpriv->dm.entry_min_undec_sm_pwdb == 0)) {
 785                 dm_pstable->rssi_val_min = 0;
 786                 RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
 787                          "Not connected to any\n");
 788         }
 789
 790         if (mac->link_state == MAC80211_LINKED) {
 791                 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
 792                         dm_pstable->rssi_val_min =
 793                             rtlpriv->dm.entry_min_undec_sm_pwdb;
 794                         RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
 795                                  "AP Client PWDB = 0x%lx\n",
 796                                   dm_pstable->rssi_val_min);
 797                 } else {
 798                         dm_pstable->rssi_val_min =
 799                             rtlpriv->dm.undec_sm_pwdb;
 800                         RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
 801                                  "STA Default Port PWDB = 0x%lx\n",
 802                                   dm_pstable->rssi_val_min);
 803                 }
 804         } else {
 805                 dm_pstable->rssi_val_min =
 806                     rtlpriv->dm.entry_min_undec_sm_pwdb;
 807
 808                 RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
 809                          "AP Ext Port PWDB = 0x%lx\n",
 810                           dm_pstable->rssi_val_min);
 811         }
 812
 813         rtl8723e_dm_rf_saving(hw, false);
 814 }
 815
 816 void rtl8723e_dm_init(struct ieee80211_hw *hw)
 817 {
 818         struct rtl_priv *rtlpriv = rtl_priv(hw);
 819
 820         rtlpriv->dm.dm_type = DM_TYPE_BYDRIVER;
 821         rtl8723e_dm_diginit(hw);
 822         rtl8723_dm_init_dynamic_txpower(hw);
 823         rtl8723_dm_init_edca_turbo(hw);
 824         rtl8723e_dm_init_rate_adaptive_mask(hw);
 825         rtl8723e_dm_initialize_txpower_tracking(hw);
 826         rtl8723_dm_init_dynamic_bb_powersaving(hw);
 827 }
 828
 829 void rtl8723e_dm_watchdog(struct ieee80211_hw *hw)
 830 {
 831         struct rtl_priv *rtlpriv = rtl_priv(hw);
 832         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 833         bool fw_current_inpsmode = false;
 834         bool fw_ps_awake = true;
 835         rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 836                                       (u8 *)(&fw_current_inpsmode));
 837         rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FWLPS_RF_ON,
 838                                       (u8 *)(&fw_ps_awake));
 839
 840         if (ppsc->p2p_ps_info.p2p_ps_mode)
 841                 fw_ps_awake = false;
 842
 843         if ((ppsc->rfpwr_state == ERFON) &&
 844             ((!fw_current_inpsmode) && fw_ps_awake) &&
 845             (!ppsc->rfchange_inprogress)) {
 846                 rtl8723e_dm_pwdb_monitor(hw);
 847                 rtl8723e_dm_dig(hw);
 848                 rtl8723e_dm_false_alarm_counter_statistics(hw);
 849                 rtl8723e_dm_dynamic_bb_powersaving(hw);
 850                 rtl8723e_dm_dynamic_txpower(hw);
 851                 rtl8723e_dm_check_txpower_tracking(hw);
 852                 /* rtl92c_dm_refresh_rate_adaptive_mask(hw); */
 853                 rtl8723e_dm_bt_coexist(hw);
 854                 rtl8723e_dm_check_edca_turbo(hw);
 855         }
 856         if (rtlpriv->btcoexist.init_set)
 857                 rtl_write_byte(rtlpriv, 0x76e, 0xc);
 858 }
 859
 860 static void rtl8723e_dm_init_bt_coexist(struct ieee80211_hw *hw)
 861 {
 862         struct rtl_priv *rtlpriv = rtl_priv(hw);
 863
 864         rtlpriv->btcoexist.bt_rfreg_origin_1e
 865                 = rtl_get_rfreg(hw, (enum radio_path)0, RF_RCK1, 0xfffff);
 866         rtlpriv->btcoexist.bt_rfreg_origin_1f
 867                 = rtl_get_rfreg(hw, (enum radio_path)0, RF_RCK2, 0xf0);
 868
 869         rtlpriv->btcoexist.cstate = 0;
 870         rtlpriv->btcoexist.previous_state = 0;
 871         rtlpriv->btcoexist.cstate_h = 0;
 872         rtlpriv->btcoexist.previous_state_h = 0;
 873         rtlpriv->btcoexist.lps_counter = 0;
 874
 875         /*  Enable counter statistics */
 876         rtl_write_byte(rtlpriv, 0x76e, 0x4);
 877         rtl_write_byte(rtlpriv, 0x778, 0x3);
 878         rtl_write_byte(rtlpriv, 0x40, 0x20);
 879
 880         rtlpriv->btcoexist.init_set = true;
 881 }
 882
 883 void rtl8723e_dm_bt_coexist(struct ieee80211_hw *hw)
 884 {
 885         struct rtl_priv *rtlpriv = rtl_priv(hw);
 886         u8 tmp_byte = 0;
 887         if (!rtlpriv->btcoexist.bt_coexistence) {
 888                 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
 889                          "[DM]{BT], BT not exist!!\n");
 890                 return;
 891         }
 892
 893         if (!rtlpriv->btcoexist.init_set) {
 894                 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
 895                          "[DM][BT], rtl8723e_dm_bt_coexist()\n");
 896                 rtl8723e_dm_init_bt_coexist(hw);
 897         }
 898
 899         tmp_byte = rtl_read_byte(rtlpriv, 0x40);
 900         RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
 901                  "[DM][BT], 0x40 is 0x%x", tmp_byte);
 902         RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
 903                  "[DM][BT], bt_dm_coexist start");
 904         rtl8723e_dm_bt_coexist_8723(hw);
 905 }