drivers/net/wireless/rtlwifi/rtl8723be/def.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2014  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * The full GNU General Public License is included in this distribution in the
  15  * file called LICENSE.
  16  *
  17  * Contact Information:
  18  * wlanfae <wlanfae@realtek.com>
  19  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20  * Hsinchu 300, Taiwan.
  21  *
  22  * Larry Finger <Larry.Finger@lwfinger.net>
  23  *
  24  *****************************************************************************/
  25
  26 #ifndef __RTL8723BE_DEF_H__
  27 #define __RTL8723BE_DEF_H__
  28
  29 #define HAL_RETRY_LIMIT_INFRA                           48
  30 #define HAL_RETRY_LIMIT_AP_ADHOC                        7
  31
  32 #define RESET_DELAY_8185                                20
  33
  34 #define RT_IBSS_INT_MASKS       (IMR_BCNINT | IMR_TBDOK | IMR_TBDER)
  35 #define RT_AC_INT_MASKS         (IMR_VIDOK | IMR_VODOK | IMR_BEDOK|IMR_BKDOK)
  36
  37 #define NUM_OF_FIRMWARE_QUEUE                   10
  38 #define NUM_OF_PAGES_IN_FW                      0x100
  39 #define NUM_OF_PAGE_IN_FW_QUEUE_BK              0x07
  40 #define NUM_OF_PAGE_IN_FW_QUEUE_BE              0x07
  41 #define NUM_OF_PAGE_IN_FW_QUEUE_VI              0x07
  42 #define NUM_OF_PAGE_IN_FW_QUEUE_VO              0x07
  43 #define NUM_OF_PAGE_IN_FW_QUEUE_HCCA            0x0
  44 #define NUM_OF_PAGE_IN_FW_QUEUE_CMD             0x0
  45 #define NUM_OF_PAGE_IN_FW_QUEUE_MGNT            0x02
  46 #define NUM_OF_PAGE_IN_FW_QUEUE_HIGH            0x02
  47 #define NUM_OF_PAGE_IN_FW_QUEUE_BCN             0x2
  48 #define NUM_OF_PAGE_IN_FW_QUEUE_PUB             0xA1
  49
  50 #define NUM_OF_PAGE_IN_FW_QUEUE_BK_DTM          0x026
  51 #define NUM_OF_PAGE_IN_FW_QUEUE_BE_DTM          0x048
  52 #define NUM_OF_PAGE_IN_FW_QUEUE_VI_DTM          0x048
  53 #define NUM_OF_PAGE_IN_FW_QUEUE_VO_DTM          0x026
  54 #define NUM_OF_PAGE_IN_FW_QUEUE_PUB_DTM         0x00
  55
  56 #define MAX_LINES_HWCONFIG_TXT                  1000
  57 #define MAX_BYTES_LINE_HWCONFIG_TXT             256
  58
  59 #define SW_THREE_WIRE                           0
  60 #define HW_THREE_WIRE                           2
  61
  62 #define BT_DEMO_BOARD                           0
  63 #define BT_QA_BOARD                             1
  64 #define BT_FPGA                                 2
  65
  66 #define HAL_PRIME_CHNL_OFFSET_DONT_CARE         0
  67 #define HAL_PRIME_CHNL_OFFSET_LOWER             1
  68 #define HAL_PRIME_CHNL_OFFSET_UPPER             2
  69
  70 #define MAX_H2C_QUEUE_NUM                       10
  71
  72 #define RX_MPDU_QUEUE                           0
  73 #define RX_CMD_QUEUE                            1
  74 #define RX_MAX_QUEUE                            2
  75 #define AC2QUEUEID(_AC)                         (_AC)
  76
  77 #define C2H_RX_CMD_HDR_LEN                      8
  78 #define GET_C2H_CMD_CMD_LEN(__prxhdr)           \
  79         LE_BITS_TO_4BYTE((__prxhdr), 0, 16)
  80 #define GET_C2H_CMD_ELEMENT_ID(__prxhdr)        \
  81         LE_BITS_TO_4BYTE((__prxhdr), 16, 8)
  82 #define GET_C2H_CMD_CMD_SEQ(__prxhdr)           \
  83         LE_BITS_TO_4BYTE((__prxhdr), 24, 7)
  84 #define GET_C2H_CMD_CONTINUE(__prxhdr)          \
  85         LE_BITS_TO_4BYTE((__prxhdr), 31, 1)
  86 #define GET_C2H_CMD_CONTENT(__prxhdr)           \
  87         ((u8 *)(__prxhdr) + C2H_RX_CMD_HDR_LEN)
  88
  89 #define GET_C2H_CMD_FEEDBACK_ELEMENT_ID(__pcmdfbhdr)    \
  90         LE_BITS_TO_4BYTE((__pcmdfbhdr), 0, 8)
  91 #define GET_C2H_CMD_FEEDBACK_CCX_LEN(__pcmdfbhdr)       \
  92         LE_BITS_TO_4BYTE((__pcmdfbhdr), 8, 8)
  93 #define GET_C2H_CMD_FEEDBACK_CCX_CMD_CNT(__pcmdfbhdr)   \
  94         LE_BITS_TO_4BYTE((__pcmdfbhdr), 16, 16)
  95 #define GET_C2H_CMD_FEEDBACK_CCX_MAC_ID(__pcmdfbhdr)    \
  96         LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 0, 5)
  97 #define GET_C2H_CMD_FEEDBACK_CCX_VALID(__pcmdfbhdr)     \
  98         LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 7, 1)
  99 #define GET_C2H_CMD_FEEDBACK_CCX_RETRY_CNT(__pcmdfbhdr) \
 100         LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 8, 5)
 101 #define GET_C2H_CMD_FEEDBACK_CCX_TOK(__pcmdfbhdr)       \
 102         LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 15, 1)
 103 #define GET_C2H_CMD_FEEDBACK_CCX_QSEL(__pcmdfbhdr)      \
 104         LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 16, 4)
 105 #define GET_C2H_CMD_FEEDBACK_CCX_SEQ(__pcmdfbhdr)       \
 106         LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 20, 12)
 107
 108 #define CHIP_BONDING_IDENTIFIER(_value) (((_value)>>22)&0x3)
 109 #define CHIP_BONDING_92C_1T2R           0x1
 110
 111 #define CHIP_8723                       BIT(0)
 112 #define CHIP_8723B                      (BIT(1) | BIT(2))
 113 #define NORMAL_CHIP                     BIT(3)
 114 #define RF_TYPE_1T1R                    (~(BIT(4) | BIT(5) | BIT(6)))
 115 #define RF_TYPE_1T2R                    BIT(4)
 116 #define RF_TYPE_2T2R                    BIT(5)
 117 #define CHIP_VENDOR_UMC                 BIT(7)
 118 #define B_CUT_VERSION                   BIT(12)
 119 #define C_CUT_VERSION                   BIT(13)
 120 #define D_CUT_VERSION                   ((BIT(12) | BIT(13)))
 121 #define E_CUT_VERSION                   BIT(14)
 122 #define RF_RL_ID                        (BIT(31) | BIT(30) | BIT(29) | BIT(28))
 123
 124 /* MASK */
 125 #define IC_TYPE_MASK                    (BIT(0) | BIT(1) | BIT(2))
 126 #define CHIP_TYPE_MASK                  BIT(3)
 127 #define RF_TYPE_MASK                    (BIT(4) | BIT(5) | BIT(6))
 128 #define MANUFACTUER_MASK                BIT(7)
 129 #define ROM_VERSION_MASK                (BIT(11) | BIT(10) | BIT(9) | BIT(8))
 130 #define CUT_VERSION_MASK                (BIT(15) | BIT(14) | BIT(13) | BIT(12))
 131
 132 /* Get element */
 133 #define GET_CVID_IC_TYPE(version)       ((version) & IC_TYPE_MASK)
 134 #define GET_CVID_CHIP_TYPE(version)     ((version) & CHIP_TYPE_MASK)
 135 #define GET_CVID_RF_TYPE(version)       ((version) & RF_TYPE_MASK)
 136 #define GET_CVID_MANUFACTUER(version)   ((version) & MANUFACTUER_MASK)
 137 #define GET_CVID_ROM_VERSION(version)   ((version) & ROM_VERSION_MASK)
 138 #define GET_CVID_CUT_VERSION(version)   ((version) & CUT_VERSION_MASK)
 139
 140 #define IS_92C_SERIAL(version)   ((IS_81XXC(version) && IS_2T2R(version)) ?\
 141                                                                 true : false)
 142 #define IS_81XXC(version)       ((GET_CVID_IC_TYPE(version) == 0) ?\
 143                                                         true : false)
 144 #define IS_8723_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8723) ?\
 145                                                         true : false)
 146 #define IS_1T1R(version)        ((GET_CVID_RF_TYPE(version)) ? false : true)
 147 #define IS_1T2R(version)        ((GET_CVID_RF_TYPE(version) == RF_TYPE_1T2R)\
 148                                                         ? true : false)
 149 #define IS_2T2R(version)        ((GET_CVID_RF_TYPE(version) == RF_TYPE_2T2R)\
 150                                                         ? true : false)
 151 enum rf_optype {
 152         RF_OP_BY_SW_3WIRE = 0,
 153         RF_OP_BY_FW,
 154         RF_OP_MAX
 155 };
 156
 157 enum rf_power_state {
 158         RF_ON,
 159         RF_OFF,
 160         RF_SLEEP,
 161         RF_SHUT_DOWN,
 162 };
 163
 164 enum power_save_mode {
 165         POWER_SAVE_MODE_ACTIVE,
 166         POWER_SAVE_MODE_SAVE,
 167 };
 168
 169 enum power_polocy_config {
 170         POWERCFG_MAX_POWER_SAVINGS,
 171         POWERCFG_GLOBAL_POWER_SAVINGS,
 172         POWERCFG_LOCAL_POWER_SAVINGS,
 173         POWERCFG_LENOVO,
 174 };
 175
 176 enum interface_select_pci {
 177         INTF_SEL1_MINICARD = 0,
 178         INTF_SEL0_PCIE = 1,
 179         INTF_SEL2_RSV = 2,
 180         INTF_SEL3_RSV = 3,
 181 };
 182
 183 enum rtl_desc_qsel {
 184         QSLT_BK = 0x2,
 185         QSLT_BE = 0x0,
 186         QSLT_VI = 0x5,
 187         QSLT_VO = 0x7,
 188         QSLT_BEACON = 0x10,
 189         QSLT_HIGH = 0x11,
 190         QSLT_MGNT = 0x12,
 191         QSLT_CMD = 0x13,
 192 };
 193
 194 enum rtl_desc8723e_rate {
 195         DESC92C_RATE1M = 0x00,
 196         DESC92C_RATE2M = 0x01,
 197         DESC92C_RATE5_5M = 0x02,
 198         DESC92C_RATE11M = 0x03,
 199
 200         DESC92C_RATE6M = 0x04,
 201         DESC92C_RATE9M = 0x05,
 202         DESC92C_RATE12M = 0x06,
 203         DESC92C_RATE18M = 0x07,
 204         DESC92C_RATE24M = 0x08,
 205         DESC92C_RATE36M = 0x09,
 206         DESC92C_RATE48M = 0x0a,
 207         DESC92C_RATE54M = 0x0b,
 208
 209         DESC92C_RATEMCS0 = 0x0c,
 210         DESC92C_RATEMCS1 = 0x0d,
 211         DESC92C_RATEMCS2 = 0x0e,
 212         DESC92C_RATEMCS3 = 0x0f,
 213         DESC92C_RATEMCS4 = 0x10,
 214         DESC92C_RATEMCS5 = 0x11,
 215         DESC92C_RATEMCS6 = 0x12,
 216         DESC92C_RATEMCS7 = 0x13,
 217         DESC92C_RATEMCS8 = 0x14,
 218         DESC92C_RATEMCS9 = 0x15,
 219         DESC92C_RATEMCS10 = 0x16,
 220         DESC92C_RATEMCS11 = 0x17,
 221         DESC92C_RATEMCS12 = 0x18,
 222         DESC92C_RATEMCS13 = 0x19,
 223         DESC92C_RATEMCS14 = 0x1a,
 224         DESC92C_RATEMCS15 = 0x1b,
 225         DESC92C_RATEMCS15_SG = 0x1c,
 226         DESC92C_RATEMCS32 = 0x20,
 227 };
 228
 229 enum rx_packet_type {
 230         NORMAL_RX,
 231         TX_REPORT1,
 232         TX_REPORT2,
 233         HIS_REPORT,
 234 };
 235
 236 struct phy_sts_cck_8723e_t {
 237         u8 adc_pwdb_X[4];
 238         u8 sq_rpt;
 239         u8 cck_agc_rpt;
 240 };
 241
 242 struct h2c_cmd_8723e {
 243         u8 element_id;
 244         u32 cmd_len;
 245         u8 *p_cmdbuffer;
 246 };
 247
 248 #endif