drivers/net/wireless/rtlwifi/wifi.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2012  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * wlanfae <wlanfae@realtek.com>
  23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24  * Hsinchu 300, Taiwan.
  25  *
  26  * Larry Finger <Larry.Finger@lwfinger.net>
  27  *
  28  *****************************************************************************/
  29
  30 #ifndef __RTL_WIFI_H__
  31 #define __RTL_WIFI_H__
  32
  33 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  34
  35 #include <linux/sched.h>
  36 #include <linux/firmware.h>
  37 #include <linux/etherdevice.h>
  38 #include <linux/vmalloc.h>
  39 #include <linux/usb.h>
  40 #include <net/mac80211.h>
  41 #include "debug.h"
  42
  43 #define RF_CHANGE_BY_INIT                       0
  44 #define RF_CHANGE_BY_IPS                        BIT(28)
  45 #define RF_CHANGE_BY_PS                         BIT(29)
  46 #define RF_CHANGE_BY_HW                         BIT(30)
  47 #define RF_CHANGE_BY_SW                         BIT(31)
  48
  49 #define IQK_ADDA_REG_NUM                        16
  50 #define IQK_MAC_REG_NUM                         4
  51
  52 #define MAX_KEY_LEN                             61
  53 #define KEY_BUF_SIZE                            5
  54
  55 /* QoS related. */
  56 /*aci: 0x00     Best Effort*/
  57 /*aci: 0x01     Background*/
  58 /*aci: 0x10     Video*/
  59 /*aci: 0x11     Voice*/
  60 /*Max: define total number.*/
  61 #define AC0_BE                                  0
  62 #define AC1_BK                                  1
  63 #define AC2_VI                                  2
  64 #define AC3_VO                                  3
  65 #define AC_MAX                                  4
  66 #define QOS_QUEUE_NUM                           4
  67 #define RTL_MAC80211_NUM_QUEUE                  5
  68 #define REALTEK_USB_VENQT_MAX_BUF_SIZE          254
  69
  70 #define QBSS_LOAD_SIZE                          5
  71 #define MAX_WMMELE_LENGTH                       64
  72
  73 #define TOTAL_CAM_ENTRY                         32
  74
  75 /*slot time for 11g. */
  76 #define RTL_SLOT_TIME_9                         9
  77 #define RTL_SLOT_TIME_20                        20
  78
  79 /*related with tcp/ip. */
  80 /*if_ehther.h*/
  81 #define ETH_P_PAE               0x888E  /*Port Access Entity (IEEE 802.1X) */
  82 #define ETH_P_IP                0x0800  /*Internet Protocol packet */
  83 #define ETH_P_ARP               0x0806  /*Address Resolution packet */
  84 #define SNAP_SIZE               6
  85 #define PROTOC_TYPE_SIZE        2
  86
  87 /*related with 802.11 frame*/
  88 #define MAC80211_3ADDR_LEN                      24
  89 #define MAC80211_4ADDR_LEN                      30
  90
  91 #define CHANNEL_MAX_NUMBER      (14 + 24 + 21)  /* 14 is the max channel no */
  92 #define CHANNEL_GROUP_MAX       (3 + 9) /*  ch1~3, 4~9, 10~14 = three groups */
  93 #define MAX_PG_GROUP                    13
  94 #define CHANNEL_GROUP_MAX_2G            3
  95 #define CHANNEL_GROUP_IDX_5GL           3
  96 #define CHANNEL_GROUP_IDX_5GM           6
  97 #define CHANNEL_GROUP_IDX_5GH           9
  98 #define CHANNEL_GROUP_MAX_5G            9
  99 #define CHANNEL_MAX_NUMBER_2G           14
 100 #define AVG_THERMAL_NUM                 8
 101 #define MAX_TID_COUNT                   9
 102
 103 /* for early mode */
 104 #define FCS_LEN                         4
 105 #define EM_HDR_LEN                      8
 106 enum intf_type {
 107         INTF_PCI = 0,
 108         INTF_USB = 1,
 109 };
 110
 111 enum radio_path {
 112         RF90_PATH_A = 0,
 113         RF90_PATH_B = 1,
 114         RF90_PATH_C = 2,
 115         RF90_PATH_D = 3,
 116 };
 117
 118 enum rt_eeprom_type {
 119         EEPROM_93C46,
 120         EEPROM_93C56,
 121         EEPROM_BOOT_EFUSE,
 122 };
 123
 124 enum rtl_status {
 125         RTL_STATUS_INTERFACE_START = 0,
 126 };
 127
 128 enum hardware_type {
 129         HARDWARE_TYPE_RTL8192E,
 130         HARDWARE_TYPE_RTL8192U,
 131         HARDWARE_TYPE_RTL8192SE,
 132         HARDWARE_TYPE_RTL8192SU,
 133         HARDWARE_TYPE_RTL8192CE,
 134         HARDWARE_TYPE_RTL8192CU,
 135         HARDWARE_TYPE_RTL8192DE,
 136         HARDWARE_TYPE_RTL8192DU,
 137         HARDWARE_TYPE_RTL8723E,
 138         HARDWARE_TYPE_RTL8723U,
 139
 140         /* keep it last */
 141         HARDWARE_TYPE_NUM
 142 };
 143
 144 #define IS_HARDWARE_TYPE_8192SU(rtlhal)                 \
 145         (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SU)
 146 #define IS_HARDWARE_TYPE_8192SE(rtlhal)                 \
 147         (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
 148 #define IS_HARDWARE_TYPE_8192CE(rtlhal)                 \
 149         (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CE)
 150 #define IS_HARDWARE_TYPE_8192CU(rtlhal)                 \
 151         (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CU)
 152 #define IS_HARDWARE_TYPE_8192DE(rtlhal)                 \
 153         (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE)
 154 #define IS_HARDWARE_TYPE_8192DU(rtlhal)                 \
 155         (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DU)
 156 #define IS_HARDWARE_TYPE_8723E(rtlhal)                  \
 157         (rtlhal->hw_type == HARDWARE_TYPE_RTL8723E)
 158 #define IS_HARDWARE_TYPE_8723U(rtlhal)                  \
 159         (rtlhal->hw_type == HARDWARE_TYPE_RTL8723U)
 160 #define IS_HARDWARE_TYPE_8192S(rtlhal)                  \
 161 (IS_HARDWARE_TYPE_8192SE(rtlhal) || IS_HARDWARE_TYPE_8192SU(rtlhal))
 162 #define IS_HARDWARE_TYPE_8192C(rtlhal)                  \
 163 (IS_HARDWARE_TYPE_8192CE(rtlhal) || IS_HARDWARE_TYPE_8192CU(rtlhal))
 164 #define IS_HARDWARE_TYPE_8192D(rtlhal)                  \
 165 (IS_HARDWARE_TYPE_8192DE(rtlhal) || IS_HARDWARE_TYPE_8192DU(rtlhal))
 166 #define IS_HARDWARE_TYPE_8723(rtlhal)                   \
 167 (IS_HARDWARE_TYPE_8723E(rtlhal) || IS_HARDWARE_TYPE_8723U(rtlhal))
 168 #define IS_HARDWARE_TYPE_8723U(rtlhal)                  \
 169         (rtlhal->hw_type == HARDWARE_TYPE_RTL8723U)
 170
 171 #define RX_HAL_IS_CCK_RATE(_pdesc)\
 172         (_pdesc->rxmcs == DESC92_RATE1M ||              \
 173          _pdesc->rxmcs == DESC92_RATE2M ||              \
 174          _pdesc->rxmcs == DESC92_RATE5_5M ||            \
 175          _pdesc->rxmcs == DESC92_RATE11M)
 176
 177 enum scan_operation_backup_opt {
 178         SCAN_OPT_BACKUP = 0,
 179         SCAN_OPT_RESTORE,
 180         SCAN_OPT_MAX
 181 };
 182
 183 /*RF state.*/
 184 enum rf_pwrstate {
 185         ERFON,
 186         ERFSLEEP,
 187         ERFOFF
 188 };
 189
 190 struct bb_reg_def {
 191         u32 rfintfs;
 192         u32 rfintfi;
 193         u32 rfintfo;
 194         u32 rfintfe;
 195         u32 rf3wire_offset;
 196         u32 rflssi_select;
 197         u32 rftxgain_stage;
 198         u32 rfhssi_para1;
 199         u32 rfhssi_para2;
 200         u32 rfswitch_control;
 201         u32 rfagc_control1;
 202         u32 rfagc_control2;
 203         u32 rfrxiq_imbalance;
 204         u32 rfrx_afe;
 205         u32 rftxiq_imbalance;
 206         u32 rftx_afe;
 207         u32 rflssi_readback;
 208         u32 rflssi_readbackpi;
 209 };
 210
 211 enum io_type {
 212         IO_CMD_PAUSE_DM_BY_SCAN = 0,
 213         IO_CMD_RESUME_DM_BY_SCAN = 1,
 214 };
 215
 216 enum hw_variables {
 217         HW_VAR_ETHER_ADDR,
 218         HW_VAR_MULTICAST_REG,
 219         HW_VAR_BASIC_RATE,
 220         HW_VAR_BSSID,
 221         HW_VAR_MEDIA_STATUS,
 222         HW_VAR_SECURITY_CONF,
 223         HW_VAR_BEACON_INTERVAL,
 224         HW_VAR_ATIM_WINDOW,
 225         HW_VAR_LISTEN_INTERVAL,
 226         HW_VAR_CS_COUNTER,
 227         HW_VAR_DEFAULTKEY0,
 228         HW_VAR_DEFAULTKEY1,
 229         HW_VAR_DEFAULTKEY2,
 230         HW_VAR_DEFAULTKEY3,
 231         HW_VAR_SIFS,
 232         HW_VAR_DIFS,
 233         HW_VAR_EIFS,
 234         HW_VAR_SLOT_TIME,
 235         HW_VAR_ACK_PREAMBLE,
 236         HW_VAR_CW_CONFIG,
 237         HW_VAR_CW_VALUES,
 238         HW_VAR_RATE_FALLBACK_CONTROL,
 239         HW_VAR_CONTENTION_WINDOW,
 240         HW_VAR_RETRY_COUNT,
 241         HW_VAR_TR_SWITCH,
 242         HW_VAR_COMMAND,
 243         HW_VAR_WPA_CONFIG,
 244         HW_VAR_AMPDU_MIN_SPACE,
 245         HW_VAR_SHORTGI_DENSITY,
 246         HW_VAR_AMPDU_FACTOR,
 247         HW_VAR_MCS_RATE_AVAILABLE,
 248         HW_VAR_AC_PARAM,
 249         HW_VAR_ACM_CTRL,
 250         HW_VAR_DIS_Req_Qsize,
 251         HW_VAR_CCX_CHNL_LOAD,
 252         HW_VAR_CCX_NOISE_HISTOGRAM,
 253         HW_VAR_CCX_CLM_NHM,
 254         HW_VAR_TxOPLimit,
 255         HW_VAR_TURBO_MODE,
 256         HW_VAR_RF_STATE,
 257         HW_VAR_RF_OFF_BY_HW,
 258         HW_VAR_BUS_SPEED,
 259         HW_VAR_SET_DEV_POWER,
 260
 261         HW_VAR_RCR,
 262         HW_VAR_RATR_0,
 263         HW_VAR_RRSR,
 264         HW_VAR_CPU_RST,
 265         HW_VAR_CECHK_BSSID,
 266         HW_VAR_LBK_MODE,
 267         HW_VAR_AES_11N_FIX,
 268         HW_VAR_USB_RX_AGGR,
 269         HW_VAR_USER_CONTROL_TURBO_MODE,
 270         HW_VAR_RETRY_LIMIT,
 271         HW_VAR_INIT_TX_RATE,
 272         HW_VAR_TX_RATE_REG,
 273         HW_VAR_EFUSE_USAGE,
 274         HW_VAR_EFUSE_BYTES,
 275         HW_VAR_AUTOLOAD_STATUS,
 276         HW_VAR_RF_2R_DISABLE,
 277         HW_VAR_SET_RPWM,
 278         HW_VAR_H2C_FW_PWRMODE,
 279         HW_VAR_H2C_FW_JOINBSSRPT,
 280         HW_VAR_FW_PSMODE_STATUS,
 281         HW_VAR_1X1_RECV_COMBINE,
 282         HW_VAR_STOP_SEND_BEACON,
 283         HW_VAR_TSF_TIMER,
 284         HW_VAR_IO_CMD,
 285
 286         HW_VAR_RF_RECOVERY,
 287         HW_VAR_H2C_FW_UPDATE_GTK,
 288         HW_VAR_WF_MASK,
 289         HW_VAR_WF_CRC,
 290         HW_VAR_WF_IS_MAC_ADDR,
 291         HW_VAR_H2C_FW_OFFLOAD,
 292         HW_VAR_RESET_WFCRC,
 293
 294         HW_VAR_HANDLE_FW_C2H,
 295         HW_VAR_DL_FW_RSVD_PAGE,
 296         HW_VAR_AID,
 297         HW_VAR_HW_SEQ_ENABLE,
 298         HW_VAR_CORRECT_TSF,
 299         HW_VAR_BCN_VALID,
 300         HW_VAR_FWLPS_RF_ON,
 301         HW_VAR_DUAL_TSF_RST,
 302         HW_VAR_SWITCH_EPHY_WoWLAN,
 303         HW_VAR_INT_MIGRATION,
 304         HW_VAR_INT_AC,
 305         HW_VAR_RF_TIMING,
 306
 307         HW_VAR_MRC,
 308
 309         HW_VAR_MGT_FILTER,
 310         HW_VAR_CTRL_FILTER,
 311         HW_VAR_DATA_FILTER,
 312 };
 313
 314 enum _RT_MEDIA_STATUS {
 315         RT_MEDIA_DISCONNECT = 0,
 316         RT_MEDIA_CONNECT = 1
 317 };
 318
 319 enum rt_oem_id {
 320         RT_CID_DEFAULT = 0,
 321         RT_CID_8187_ALPHA0 = 1,
 322         RT_CID_8187_SERCOMM_PS = 2,
 323         RT_CID_8187_HW_LED = 3,
 324         RT_CID_8187_NETGEAR = 4,
 325         RT_CID_WHQL = 5,
 326         RT_CID_819x_CAMEO = 6,
 327         RT_CID_819x_RUNTOP = 7,
 328         RT_CID_819x_Senao = 8,
 329         RT_CID_TOSHIBA = 9,
 330         RT_CID_819x_Netcore = 10,
 331         RT_CID_Nettronix = 11,
 332         RT_CID_DLINK = 12,
 333         RT_CID_PRONET = 13,
 334         RT_CID_COREGA = 14,
 335         RT_CID_819x_ALPHA = 15,
 336         RT_CID_819x_Sitecom = 16,
 337         RT_CID_CCX = 17,
 338         RT_CID_819x_Lenovo = 18,
 339         RT_CID_819x_QMI = 19,
 340         RT_CID_819x_Edimax_Belkin = 20,
 341         RT_CID_819x_Sercomm_Belkin = 21,
 342         RT_CID_819x_CAMEO1 = 22,
 343         RT_CID_819x_MSI = 23,
 344         RT_CID_819x_Acer = 24,
 345         RT_CID_819x_HP = 27,
 346         RT_CID_819x_CLEVO = 28,
 347         RT_CID_819x_Arcadyan_Belkin = 29,
 348         RT_CID_819x_SAMSUNG = 30,
 349         RT_CID_819x_WNC_COREGA = 31,
 350         RT_CID_819x_Foxcoon = 32,
 351         RT_CID_819x_DELL = 33,
 352 };
 353
 354 enum hw_descs {
 355         HW_DESC_OWN,
 356         HW_DESC_RXOWN,
 357         HW_DESC_TX_NEXTDESC_ADDR,
 358         HW_DESC_TXBUFF_ADDR,
 359         HW_DESC_RXBUFF_ADDR,
 360         HW_DESC_RXPKT_LEN,
 361         HW_DESC_RXERO,
 362 };
 363
 364 enum prime_sc {
 365         PRIME_CHNL_OFFSET_DONT_CARE = 0,
 366         PRIME_CHNL_OFFSET_LOWER = 1,
 367         PRIME_CHNL_OFFSET_UPPER = 2,
 368 };
 369
 370 enum rf_type {
 371         RF_1T1R = 0,
 372         RF_1T2R = 1,
 373         RF_2T2R = 2,
 374         RF_2T2R_GREEN = 3,
 375 };
 376
 377 enum ht_channel_width {
 378         HT_CHANNEL_WIDTH_20 = 0,
 379         HT_CHANNEL_WIDTH_20_40 = 1,
 380 };
 381
 382 /* Ref: 802.11i sepc D10.0 7.3.2.25.1
 383 Cipher Suites Encryption Algorithms */
 384 enum rt_enc_alg {
 385         NO_ENCRYPTION = 0,
 386         WEP40_ENCRYPTION = 1,
 387         TKIP_ENCRYPTION = 2,
 388         RSERVED_ENCRYPTION = 3,
 389         AESCCMP_ENCRYPTION = 4,
 390         WEP104_ENCRYPTION = 5,
 391 };
 392
 393 enum rtl_hal_state {
 394         _HAL_STATE_STOP = 0,
 395         _HAL_STATE_START = 1,
 396 };
 397
 398 enum rtl_desc92_rate {
 399         DESC92_RATE1M = 0x00,
 400         DESC92_RATE2M = 0x01,
 401         DESC92_RATE5_5M = 0x02,
 402         DESC92_RATE11M = 0x03,
 403
 404         DESC92_RATE6M = 0x04,
 405         DESC92_RATE9M = 0x05,
 406         DESC92_RATE12M = 0x06,
 407         DESC92_RATE18M = 0x07,
 408         DESC92_RATE24M = 0x08,
 409         DESC92_RATE36M = 0x09,
 410         DESC92_RATE48M = 0x0a,
 411         DESC92_RATE54M = 0x0b,
 412
 413         DESC92_RATEMCS0 = 0x0c,
 414         DESC92_RATEMCS1 = 0x0d,
 415         DESC92_RATEMCS2 = 0x0e,
 416         DESC92_RATEMCS3 = 0x0f,
 417         DESC92_RATEMCS4 = 0x10,
 418         DESC92_RATEMCS5 = 0x11,
 419         DESC92_RATEMCS6 = 0x12,
 420         DESC92_RATEMCS7 = 0x13,
 421         DESC92_RATEMCS8 = 0x14,
 422         DESC92_RATEMCS9 = 0x15,
 423         DESC92_RATEMCS10 = 0x16,
 424         DESC92_RATEMCS11 = 0x17,
 425         DESC92_RATEMCS12 = 0x18,
 426         DESC92_RATEMCS13 = 0x19,
 427         DESC92_RATEMCS14 = 0x1a,
 428         DESC92_RATEMCS15 = 0x1b,
 429         DESC92_RATEMCS15_SG = 0x1c,
 430         DESC92_RATEMCS32 = 0x20,
 431 };
 432
 433 enum rtl_var_map {
 434         /*reg map */
 435         SYS_ISO_CTRL = 0,
 436         SYS_FUNC_EN,
 437         SYS_CLK,
 438         MAC_RCR_AM,
 439         MAC_RCR_AB,
 440         MAC_RCR_ACRC32,
 441         MAC_RCR_ACF,
 442         MAC_RCR_AAP,
 443
 444         /*efuse map */
 445         EFUSE_TEST,
 446         EFUSE_CTRL,
 447         EFUSE_CLK,
 448         EFUSE_CLK_CTRL,
 449         EFUSE_PWC_EV12V,
 450         EFUSE_FEN_ELDR,
 451         EFUSE_LOADER_CLK_EN,
 452         EFUSE_ANA8M,
 453         EFUSE_HWSET_MAX_SIZE,
 454         EFUSE_MAX_SECTION_MAP,
 455         EFUSE_REAL_CONTENT_SIZE,
 456         EFUSE_OOB_PROTECT_BYTES_LEN,
 457
 458         /*CAM map */
 459         RWCAM,
 460         WCAMI,
 461         RCAMO,
 462         CAMDBG,
 463         SECR,
 464         SEC_CAM_NONE,
 465         SEC_CAM_WEP40,
 466         SEC_CAM_TKIP,
 467         SEC_CAM_AES,
 468         SEC_CAM_WEP104,
 469
 470         /*IMR map */
 471         RTL_IMR_BCNDMAINT6,     /*Beacon DMA Interrupt 6 */
 472         RTL_IMR_BCNDMAINT5,     /*Beacon DMA Interrupt 5 */
 473         RTL_IMR_BCNDMAINT4,     /*Beacon DMA Interrupt 4 */
 474         RTL_IMR_BCNDMAINT3,     /*Beacon DMA Interrupt 3 */
 475         RTL_IMR_BCNDMAINT2,     /*Beacon DMA Interrupt 2 */
 476         RTL_IMR_BCNDMAINT1,     /*Beacon DMA Interrupt 1 */
 477         RTL_IMR_BCNDOK8,        /*Beacon Queue DMA OK Interrup 8 */
 478         RTL_IMR_BCNDOK7,        /*Beacon Queue DMA OK Interrup 7 */
 479         RTL_IMR_BCNDOK6,        /*Beacon Queue DMA OK Interrup 6 */
 480         RTL_IMR_BCNDOK5,        /*Beacon Queue DMA OK Interrup 5 */
 481         RTL_IMR_BCNDOK4,        /*Beacon Queue DMA OK Interrup 4 */
 482         RTL_IMR_BCNDOK3,        /*Beacon Queue DMA OK Interrup 3 */
 483         RTL_IMR_BCNDOK2,        /*Beacon Queue DMA OK Interrup 2 */
 484         RTL_IMR_BCNDOK1,        /*Beacon Queue DMA OK Interrup 1 */
 485         RTL_IMR_TIMEOUT2,       /*Timeout interrupt 2 */
 486         RTL_IMR_TIMEOUT1,       /*Timeout interrupt 1 */
 487         RTL_IMR_TXFOVW,         /*Transmit FIFO Overflow */
 488         RTL_IMR_PSTIMEOUT,      /*Power save time out interrupt */
 489         RTL_IMR_BcnInt,         /*Beacon DMA Interrupt 0 */
 490         RTL_IMR_RXFOVW,         /*Receive FIFO Overflow */
 491         RTL_IMR_RDU,            /*Receive Descriptor Unavailable */
 492         RTL_IMR_ATIMEND,        /*For 92C,ATIM Window End Interrupt */
 493         RTL_IMR_BDOK,           /*Beacon Queue DMA OK Interrup */
 494         RTL_IMR_HIGHDOK,        /*High Queue DMA OK Interrupt */
 495         RTL_IMR_COMDOK,         /*Command Queue DMA OK Interrupt*/
 496         RTL_IMR_TBDOK,          /*Transmit Beacon OK interrup */
 497         RTL_IMR_MGNTDOK,        /*Management Queue DMA OK Interrupt */
 498         RTL_IMR_TBDER,          /*For 92C,Transmit Beacon Error Interrupt */
 499         RTL_IMR_BKDOK,          /*AC_BK DMA OK Interrupt */
 500         RTL_IMR_BEDOK,          /*AC_BE DMA OK Interrupt */
 501         RTL_IMR_VIDOK,          /*AC_VI DMA OK Interrupt */
 502         RTL_IMR_VODOK,          /*AC_VO DMA Interrupt */
 503         RTL_IMR_ROK,            /*Receive DMA OK Interrupt */
 504         RTL_IBSS_INT_MASKS,     /*(RTL_IMR_BcnInt | RTL_IMR_TBDOK |
 505                                  * RTL_IMR_TBDER) */
 506
 507         /*CCK Rates, TxHT = 0 */
 508         RTL_RC_CCK_RATE1M,
 509         RTL_RC_CCK_RATE2M,
 510         RTL_RC_CCK_RATE5_5M,
 511         RTL_RC_CCK_RATE11M,
 512
 513         /*OFDM Rates, TxHT = 0 */
 514         RTL_RC_OFDM_RATE6M,
 515         RTL_RC_OFDM_RATE9M,
 516         RTL_RC_OFDM_RATE12M,
 517         RTL_RC_OFDM_RATE18M,
 518         RTL_RC_OFDM_RATE24M,
 519         RTL_RC_OFDM_RATE36M,
 520         RTL_RC_OFDM_RATE48M,
 521         RTL_RC_OFDM_RATE54M,
 522
 523         RTL_RC_HT_RATEMCS7,
 524         RTL_RC_HT_RATEMCS15,
 525
 526         /*keep it last */
 527         RTL_VAR_MAP_MAX,
 528 };
 529
 530 /*Firmware PS mode for control LPS.*/
 531 enum _fw_ps_mode {
 532         FW_PS_ACTIVE_MODE = 0,
 533         FW_PS_MIN_MODE = 1,
 534         FW_PS_MAX_MODE = 2,
 535         FW_PS_DTIM_MODE = 3,
 536         FW_PS_VOIP_MODE = 4,
 537         FW_PS_UAPSD_WMM_MODE = 5,
 538         FW_PS_UAPSD_MODE = 6,
 539         FW_PS_IBSS_MODE = 7,
 540         FW_PS_WWLAN_MODE = 8,
 541         FW_PS_PM_Radio_Off = 9,
 542         FW_PS_PM_Card_Disable = 10,
 543 };
 544
 545 enum rt_psmode {
 546         EACTIVE,                /*Active/Continuous access. */
 547         EMAXPS,                 /*Max power save mode. */
 548         EFASTPS,                /*Fast power save mode. */
 549         EAUTOPS,                /*Auto power save mode. */
 550 };
 551
 552 /*LED related.*/
 553 enum led_ctl_mode {
 554         LED_CTL_POWER_ON = 1,
 555         LED_CTL_LINK = 2,
 556         LED_CTL_NO_LINK = 3,
 557         LED_CTL_TX = 4,
 558         LED_CTL_RX = 5,
 559         LED_CTL_SITE_SURVEY = 6,
 560         LED_CTL_POWER_OFF = 7,
 561         LED_CTL_START_TO_LINK = 8,
 562         LED_CTL_START_WPS = 9,
 563         LED_CTL_STOP_WPS = 10,
 564 };
 565
 566 enum rtl_led_pin {
 567         LED_PIN_GPIO0,
 568         LED_PIN_LED0,
 569         LED_PIN_LED1,
 570         LED_PIN_LED2
 571 };
 572
 573 /*QoS related.*/
 574 /*acm implementation method.*/
 575 enum acm_method {
 576         eAcmWay0_SwAndHw = 0,
 577         eAcmWay1_HW = 1,
 578         eAcmWay2_SW = 2,
 579 };
 580
 581 enum macphy_mode {
 582         SINGLEMAC_SINGLEPHY = 0,
 583         DUALMAC_DUALPHY,
 584         DUALMAC_SINGLEPHY,
 585 };
 586
 587 enum band_type {
 588         BAND_ON_2_4G = 0,
 589         BAND_ON_5G,
 590         BAND_ON_BOTH,
 591         BANDMAX
 592 };
 593
 594 /*aci/aifsn Field.
 595 Ref: WMM spec 2.2.2: WME Parameter Element, p.12.*/
 596 union aci_aifsn {
 597         u8 char_data;
 598
 599         struct {
 600                 u8 aifsn:4;
 601                 u8 acm:1;
 602                 u8 aci:2;
 603                 u8 reserved:1;
 604         } f;                    /* Field */
 605 };
 606
 607 /*mlme related.*/
 608 enum wireless_mode {
 609         WIRELESS_MODE_UNKNOWN = 0x00,
 610         WIRELESS_MODE_A = 0x01,
 611         WIRELESS_MODE_B = 0x02,
 612         WIRELESS_MODE_G = 0x04,
 613         WIRELESS_MODE_AUTO = 0x08,
 614         WIRELESS_MODE_N_24G = 0x10,
 615         WIRELESS_MODE_N_5G = 0x20
 616 };
 617
 618 #define IS_WIRELESS_MODE_A(wirelessmode)        \
 619         (wirelessmode == WIRELESS_MODE_A)
 620 #define IS_WIRELESS_MODE_B(wirelessmode)        \
 621         (wirelessmode == WIRELESS_MODE_B)
 622 #define IS_WIRELESS_MODE_G(wirelessmode)        \
 623         (wirelessmode == WIRELESS_MODE_G)
 624 #define IS_WIRELESS_MODE_N_24G(wirelessmode)    \
 625         (wirelessmode == WIRELESS_MODE_N_24G)
 626 #define IS_WIRELESS_MODE_N_5G(wirelessmode)     \
 627         (wirelessmode == WIRELESS_MODE_N_5G)
 628
 629 enum ratr_table_mode {
 630         RATR_INX_WIRELESS_NGB = 0,
 631         RATR_INX_WIRELESS_NG = 1,
 632         RATR_INX_WIRELESS_NB = 2,
 633         RATR_INX_WIRELESS_N = 3,
 634         RATR_INX_WIRELESS_GB = 4,
 635         RATR_INX_WIRELESS_G = 5,
 636         RATR_INX_WIRELESS_B = 6,
 637         RATR_INX_WIRELESS_MC = 7,
 638         RATR_INX_WIRELESS_A = 8,
 639 };
 640
 641 enum rtl_link_state {
 642         MAC80211_NOLINK = 0,
 643         MAC80211_LINKING = 1,
 644         MAC80211_LINKED = 2,
 645         MAC80211_LINKED_SCANNING = 3,
 646 };
 647
 648 enum act_category {
 649         ACT_CAT_QOS = 1,
 650         ACT_CAT_DLS = 2,
 651         ACT_CAT_BA = 3,
 652         ACT_CAT_HT = 7,
 653         ACT_CAT_WMM = 17,
 654 };
 655
 656 enum ba_action {
 657         ACT_ADDBAREQ = 0,
 658         ACT_ADDBARSP = 1,
 659         ACT_DELBA = 2,
 660 };
 661
 662 struct octet_string {
 663         u8 *octet;
 664         u16 length;
 665 };
 666
 667 struct rtl_hdr_3addr {
 668         __le16 frame_ctl;
 669         __le16 duration_id;
 670         u8 addr1[ETH_ALEN];
 671         u8 addr2[ETH_ALEN];
 672         u8 addr3[ETH_ALEN];
 673         __le16 seq_ctl;
 674         u8 payload[0];
 675 } __packed;
 676
 677 struct rtl_info_element {
 678         u8 id;
 679         u8 len;
 680         u8 data[0];
 681 } __packed;
 682
 683 struct rtl_probe_rsp {
 684         struct rtl_hdr_3addr header;
 685         u32 time_stamp[2];
 686         __le16 beacon_interval;
 687         __le16 capability;
 688         /*SSID, supported rates, FH params, DS params,
 689            CF params, IBSS params, TIM (if beacon), RSN */
 690         struct rtl_info_element info_element[0];
 691 } __packed;
 692
 693 /*LED related.*/
 694 /*ledpin Identify how to implement this SW led.*/
 695 struct rtl_led {
 696         void *hw;
 697         enum rtl_led_pin ledpin;
 698         bool ledon;
 699 };
 700
 701 struct rtl_led_ctl {
 702         bool led_opendrain;
 703         struct rtl_led sw_led0;
 704         struct rtl_led sw_led1;
 705 };
 706
 707 struct rtl_qos_parameters {
 708         __le16 cw_min;
 709         __le16 cw_max;
 710         u8 aifs;
 711         u8 flag;
 712         __le16 tx_op;
 713 } __packed;
 714
 715 struct rt_smooth_data {
 716         u32 elements[100];      /*array to store values */
 717         u32 index;              /*index to current array to store */
 718         u32 total_num;          /*num of valid elements */
 719         u32 total_val;          /*sum of valid elements */
 720 };
 721
 722 struct false_alarm_statistics {
 723         u32 cnt_parity_fail;
 724         u32 cnt_rate_illegal;
 725         u32 cnt_crc8_fail;
 726         u32 cnt_mcs_fail;
 727         u32 cnt_fast_fsync_fail;
 728         u32 cnt_sb_search_fail;
 729         u32 cnt_ofdm_fail;
 730         u32 cnt_cck_fail;
 731         u32 cnt_all;
 732 };
 733
 734 struct init_gain {
 735         u8 xaagccore1;
 736         u8 xbagccore1;
 737         u8 xcagccore1;
 738         u8 xdagccore1;
 739         u8 cca;
 740
 741 };
 742
 743 struct wireless_stats {
 744         unsigned long txbytesunicast;
 745         unsigned long txbytesmulticast;
 746         unsigned long txbytesbroadcast;
 747         unsigned long rxbytesunicast;
 748
 749         long rx_snr_db[4];
 750         /*Correct smoothed ss in Dbm, only used
 751            in driver to report real power now. */
 752         long recv_signal_power;
 753         long signal_quality;
 754         long last_sigstrength_inpercent;
 755
 756         u32 rssi_calculate_cnt;
 757
 758         /*Transformed, in dbm. Beautified signal
 759            strength for UI, not correct. */
 760         long signal_strength;
 761
 762         u8 rx_rssi_percentage[4];
 763         u8 rx_evm_percentage[2];
 764
 765         struct rt_smooth_data ui_rssi;
 766         struct rt_smooth_data ui_link_quality;
 767 };
 768
 769 struct rate_adaptive {
 770         u8 rate_adaptive_disabled;
 771         u8 ratr_state;
 772         u16 reserve;
 773
 774         u32 high_rssi_thresh_for_ra;
 775         u32 high2low_rssi_thresh_for_ra;
 776         u8 low2high_rssi_thresh_for_ra40m;
 777         u32 low_rssi_thresh_for_ra40M;
 778         u8 low2high_rssi_thresh_for_ra20m;
 779         u32 low_rssi_thresh_for_ra20M;
 780         u32 upper_rssi_threshold_ratr;
 781         u32 middleupper_rssi_threshold_ratr;
 782         u32 middle_rssi_threshold_ratr;
 783         u32 middlelow_rssi_threshold_ratr;
 784         u32 low_rssi_threshold_ratr;
 785         u32 ultralow_rssi_threshold_ratr;
 786         u32 low_rssi_threshold_ratr_40m;
 787         u32 low_rssi_threshold_ratr_20m;
 788         u8 ping_rssi_enable;
 789         u32 ping_rssi_ratr;
 790         u32 ping_rssi_thresh_for_ra;
 791         u32 last_ratr;
 792         u8 pre_ratr_state;
 793 };
 794
 795 struct regd_pair_mapping {
 796         u16 reg_dmnenum;
 797         u16 reg_5ghz_ctl;
 798         u16 reg_2ghz_ctl;
 799 };
 800
 801 struct rtl_regulatory {
 802         char alpha2[2];
 803         u16 country_code;
 804         u16 max_power_level;
 805         u32 tp_scale;
 806         u16 current_rd;
 807         u16 current_rd_ext;
 808         int16_t power_limit;
 809         struct regd_pair_mapping *regpair;
 810 };
 811
 812 struct rtl_rfkill {
 813         bool rfkill_state;      /*0 is off, 1 is on */
 814 };
 815
 816 #define IQK_MATRIX_REG_NUM      8
 817 #define IQK_MATRIX_SETTINGS_NUM (1 + 24 + 21)
 818 struct iqk_matrix_regs {
 819         bool iqk_done;
 820         long value[1][IQK_MATRIX_REG_NUM];
 821 };
 822
 823 struct phy_parameters {
 824         u16 length;
 825         u32 *pdata;
 826 };
 827
 828 enum hw_param_tab_index {
 829         PHY_REG_2T,
 830         PHY_REG_1T,
 831         PHY_REG_PG,
 832         RADIOA_2T,
 833         RADIOB_2T,
 834         RADIOA_1T,
 835         RADIOB_1T,
 836         MAC_REG,
 837         AGCTAB_2T,
 838         AGCTAB_1T,
 839         MAX_TAB
 840 };
 841
 842 struct rtl_phy {
 843         struct bb_reg_def phyreg_def[4];        /*Radio A/B/C/D */
 844         struct init_gain initgain_backup;
 845         enum io_type current_io_type;
 846
 847         u8 rf_mode;
 848         u8 rf_type;
 849         u8 current_chan_bw;
 850         u8 set_bwmode_inprogress;
 851         u8 sw_chnl_inprogress;
 852         u8 sw_chnl_stage;
 853         u8 sw_chnl_step;
 854         u8 current_channel;
 855         u8 h2c_box_num;
 856         u8 set_io_inprogress;
 857         u8 lck_inprogress;
 858
 859         /* record for power tracking */
 860         s32 reg_e94;
 861         s32 reg_e9c;
 862         s32 reg_ea4;
 863         s32 reg_eac;
 864         s32 reg_eb4;
 865         s32 reg_ebc;
 866         s32 reg_ec4;
 867         s32 reg_ecc;
 868         u8 rfpienable;
 869         u8 reserve_0;
 870         u16 reserve_1;
 871         u32 reg_c04, reg_c08, reg_874;
 872         u32 adda_backup[16];
 873         u32 iqk_mac_backup[IQK_MAC_REG_NUM];
 874         u32 iqk_bb_backup[10];
 875
 876         /* Dual mac */
 877         bool need_iqk;
 878         struct iqk_matrix_regs iqk_matrix_regsetting[IQK_MATRIX_SETTINGS_NUM];
 879
 880         bool rfpi_enable;
 881
 882         u8 pwrgroup_cnt;
 883         u8 cck_high_power;
 884         /* MAX_PG_GROUP groups of pwr diff by rates */
 885         u32 mcs_txpwrlevel_origoffset[MAX_PG_GROUP][16];
 886         u8 default_initialgain[4];
 887
 888         /* the current Tx power level */
 889         u8 cur_cck_txpwridx;
 890         u8 cur_ofdm24g_txpwridx;
 891
 892         u32 rfreg_chnlval[2];
 893         bool apk_done;
 894         u32 reg_rf3c[2];        /* pathA / pathB  */
 895
 896         /* bfsync */
 897         u8 framesync;
 898         u32 framesync_c34;
 899
 900         u8 num_total_rfpath;
 901         struct phy_parameters hwparam_tables[MAX_TAB];
 902         u16 rf_pathmap;
 903 };
 904
 905 #define MAX_TID_COUNT                           9
 906 #define RTL_AGG_STOP                            0
 907 #define RTL_AGG_PROGRESS                        1
 908 #define RTL_AGG_START                           2
 909 #define RTL_AGG_OPERATIONAL                     3
 910 #define RTL_AGG_OFF                             0
 911 #define RTL_AGG_ON                              1
 912 #define RTL_AGG_EMPTYING_HW_QUEUE_ADDBA         2
 913 #define RTL_AGG_EMPTYING_HW_QUEUE_DELBA         3
 914
 915 struct rtl_ht_agg {
 916         u16 txq_id;
 917         u16 wait_for_ba;
 918         u16 start_idx;
 919         u64 bitmap;
 920         u32 rate_n_flags;
 921         u8 agg_state;
 922 };
 923
 924 struct rtl_tid_data {
 925         u16 seq_number;
 926         struct rtl_ht_agg agg;
 927 };
 928
 929 struct rtl_sta_info {
 930         u8 ratr_index;
 931         u8 wireless_mode;
 932         u8 mimo_ps;
 933         struct rtl_tid_data tids[MAX_TID_COUNT];
 934 } __packed;
 935
 936 struct rtl_priv;
 937 struct rtl_io {
 938         struct device *dev;
 939         struct mutex bb_mutex;
 940
 941         /*PCI MEM map */
 942         unsigned long pci_mem_end;      /*shared mem end        */
 943         unsigned long pci_mem_start;    /*shared mem start */
 944
 945         /*PCI IO map */
 946         unsigned long pci_base_addr;    /*device I/O address */
 947
 948         void (*write8_async) (struct rtl_priv *rtlpriv, u32 addr, u8 val);
 949         void (*write16_async) (struct rtl_priv *rtlpriv, u32 addr, u16 val);
 950         void (*write32_async) (struct rtl_priv *rtlpriv, u32 addr, u32 val);
 951         void (*writeN_sync) (struct rtl_priv *rtlpriv, u32 addr, void *buf,
 952                              u16 len);
 953
 954         u8(*read8_sync) (struct rtl_priv *rtlpriv, u32 addr);
 955         u16(*read16_sync) (struct rtl_priv *rtlpriv, u32 addr);
 956         u32(*read32_sync) (struct rtl_priv *rtlpriv, u32 addr);
 957
 958 };
 959
 960 struct rtl_mac {
 961         u8 mac_addr[ETH_ALEN];
 962         u8 mac80211_registered;
 963         u8 beacon_enabled;
 964
 965         u32 tx_ss_num;
 966         u32 rx_ss_num;
 967
 968         struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];
 969         struct ieee80211_hw *hw;
 970         struct ieee80211_vif *vif;
 971         enum nl80211_iftype opmode;
 972
 973         /*Probe Beacon management */
 974         struct rtl_tid_data tids[MAX_TID_COUNT];
 975         enum rtl_link_state link_state;
 976
 977         int n_channels;
 978         int n_bitrates;
 979
 980         bool offchan_delay;
 981
 982         /*filters */
 983         u32 rx_conf;
 984         u16 rx_mgt_filter;
 985         u16 rx_ctrl_filter;
 986         u16 rx_data_filter;
 987
 988         bool act_scanning;
 989         u8 cnt_after_linked;
 990
 991         /* early mode */
 992         /* skb wait queue */
 993         struct sk_buff_head skb_waitq[MAX_TID_COUNT];
 994         u8 earlymode_threshold;
 995
 996         /*RDG*/
 997         bool rdg_en;
 998
 999         /*AP*/
1000         u8 bssid[6];
1001         u32 vendor;
1002         u8 mcs[16];     /* 16 bytes mcs for HT rates. */
1003         u32 basic_rates; /* b/g rates */
1004         u8 ht_enable;
1005         u8 sgi_40;
1006         u8 sgi_20;
1007         u8 bw_40;
1008         u8 mode;                /* wireless mode */
1009         u8 slot_time;
1010         u8 short_preamble;
1011         u8 use_cts_protect;
1012         u8 cur_40_prime_sc;
1013         u8 cur_40_prime_sc_bk;
1014         u64 tsf;
1015         u8 retry_short;
1016         u8 retry_long;
1017         u16 assoc_id;
1018
1019         /*IBSS*/
1020         int beacon_interval;
1021
1022         /*AMPDU*/
1023         u8 min_space_cfg;       /*For Min spacing configurations */
1024         u8 max_mss_density;
1025         u8 current_ampdu_factor;
1026         u8 current_ampdu_density;
1027
1028         /*QOS & EDCA */
1029         struct ieee80211_tx_queue_params edca_param[RTL_MAC80211_NUM_QUEUE];
1030         struct rtl_qos_parameters ac[AC_MAX];
1031 };
1032
1033 struct rtl_hal {
1034         struct ieee80211_hw *hw;
1035
1036         enum intf_type interface;
1037         u16 hw_type;            /*92c or 92d or 92s and so on */
1038         u8 ic_class;
1039         u8 oem_id;
1040         u32 version;            /*version of chip */
1041         u8 state;               /*stop 0, start 1 */
1042
1043         /*firmware */
1044         u32 fwsize;
1045         u8 *pfirmware;
1046         u16 fw_version;
1047         u16 fw_subversion;
1048         bool h2c_setinprogress;
1049         u8 last_hmeboxnum;
1050         bool fw_ready;
1051         /*Reserve page start offset except beacon in TxQ. */
1052         u8 fw_rsvdpage_startoffset;
1053         u8 h2c_txcmd_seq;
1054
1055         /* FW Cmd IO related */
1056         u16 fwcmd_iomap;
1057         u32 fwcmd_ioparam;
1058         bool set_fwcmd_inprogress;
1059         u8 current_fwcmd_io;
1060
1061         /**/
1062         bool driver_going2unload;
1063
1064         /*AMPDU init min space*/
1065         u8 minspace_cfg;        /*For Min spacing configurations */
1066
1067         /* Dual mac */
1068         enum macphy_mode macphymode;
1069         enum band_type current_bandtype;        /* 0:2.4G, 1:5G */
1070         enum band_type current_bandtypebackup;
1071         enum band_type bandset;
1072         /* dual MAC 0--Mac0 1--Mac1 */
1073         u32 interfaceindex;
1074         /* just for DualMac S3S4 */
1075         u8 macphyctl_reg;
1076         bool earlymode_enable;
1077         /* Dual mac*/
1078         bool during_mac0init_radiob;
1079         bool during_mac1init_radioa;
1080         bool reloadtxpowerindex;
1081         /* True if IMR or IQK  have done
1082         for 2.4G in scan progress */
1083         bool load_imrandiqk_setting_for2g;
1084
1085         bool disable_amsdu_8k;
1086 };
1087
1088 struct rtl_security {
1089         /*default 0 */
1090         bool use_sw_sec;
1091
1092         bool being_setkey;
1093         bool use_defaultkey;
1094         /*Encryption Algorithm for Unicast Packet */
1095         enum rt_enc_alg pairwise_enc_algorithm;
1096         /*Encryption Algorithm for Brocast/Multicast */
1097         enum rt_enc_alg group_enc_algorithm;
1098         /*Cam Entry Bitmap */
1099         u32 hwsec_cam_bitmap;
1100         u8 hwsec_cam_sta_addr[TOTAL_CAM_ENTRY][ETH_ALEN];
1101         /*local Key buffer, indx 0 is for
1102            pairwise key 1-4 is for agoup key. */
1103         u8 key_buf[KEY_BUF_SIZE][MAX_KEY_LEN];
1104         u8 key_len[KEY_BUF_SIZE];
1105
1106         /*The pointer of Pairwise Key,
1107            it always points to KeyBuf[4] */
1108         u8 *pairwise_key;
1109 };
1110
1111 struct rtl_dm {
1112         /*PHY status for Dynamic Management */
1113         long entry_min_undecoratedsmoothed_pwdb;
1114         long undecorated_smoothed_pwdb; /*out dm */
1115         long entry_max_undecoratedsmoothed_pwdb;
1116         bool dm_initialgain_enable;
1117         bool dynamic_txpower_enable;
1118         bool current_turbo_edca;
1119         bool is_any_nonbepkts;  /*out dm */
1120         bool is_cur_rdlstate;
1121         bool txpower_trackinginit;
1122         bool disable_framebursting;
1123         bool cck_inch14;
1124         bool txpower_tracking;
1125         bool useramask;
1126         bool rfpath_rxenable[4];
1127         bool inform_fw_driverctrldm;
1128         bool current_mrc_switch;
1129         u8 txpowercount;
1130
1131         u8 thermalvalue_rxgain;
1132         u8 thermalvalue_iqk;
1133         u8 thermalvalue_lck;
1134         u8 thermalvalue;
1135         u8 last_dtp_lvl;
1136         u8 thermalvalue_avg[AVG_THERMAL_NUM];
1137         u8 thermalvalue_avg_index;
1138         bool done_txpower;
1139         u8 dynamic_txhighpower_lvl;     /*Tx high power level */
1140         u8 dm_flag;             /*Indicate each dynamic mechanism's status. */
1141         u8 dm_type;
1142         u8 txpower_track_control;
1143         bool interrupt_migration;
1144         bool disable_tx_int;
1145         char ofdm_index[2];
1146         char cck_index;
1147 };
1148
1149 #define EFUSE_MAX_LOGICAL_SIZE                  256
1150
1151 struct rtl_efuse {
1152         bool autoLoad_ok;
1153         bool bootfromefuse;
1154         u16 max_physical_size;
1155
1156         u8 efuse_map[2][EFUSE_MAX_LOGICAL_SIZE];
1157         u16 efuse_usedbytes;
1158         u8 efuse_usedpercentage;
1159 #ifdef EFUSE_REPG_WORKAROUND
1160         bool efuse_re_pg_sec1flag;
1161         u8 efuse_re_pg_data[8];
1162 #endif
1163
1164         u8 autoload_failflag;
1165         u8 autoload_status;
1166
1167         short epromtype;
1168         u16 eeprom_vid;
1169         u16 eeprom_did;
1170         u16 eeprom_svid;
1171         u16 eeprom_smid;
1172         u8 eeprom_oemid;
1173         u16 eeprom_channelplan;
1174         u8 eeprom_version;
1175         u8 board_type;
1176         u8 external_pa;
1177
1178         u8 dev_addr[6];
1179
1180         bool txpwr_fromeprom;
1181         u8 eeprom_crystalcap;
1182         u8 eeprom_tssi[2];
1183         u8 eeprom_tssi_5g[3][2]; /* for 5GL/5GM/5GH band. */
1184         u8 eeprom_pwrlimit_ht20[CHANNEL_GROUP_MAX];
1185         u8 eeprom_pwrlimit_ht40[CHANNEL_GROUP_MAX];
1186         u8 eeprom_chnlarea_txpwr_cck[2][CHANNEL_GROUP_MAX_2G];
1187         u8 eeprom_chnlarea_txpwr_ht40_1s[2][CHANNEL_GROUP_MAX];
1188         u8 eeprom_chnlarea_txpwr_ht40_2sdiif[2][CHANNEL_GROUP_MAX];
1189         u8 txpwrlevel_cck[2][CHANNEL_MAX_NUMBER_2G];
1190         u8 txpwrlevel_ht40_1s[2][CHANNEL_MAX_NUMBER];   /*For HT 40MHZ pwr */
1191         u8 txpwrlevel_ht40_2s[2][CHANNEL_MAX_NUMBER];   /*For HT 40MHZ pwr */
1192
1193         u8 internal_pa_5g[2];   /* pathA / pathB */
1194         u8 eeprom_c9;
1195         u8 eeprom_cc;
1196
1197         /*For power group */
1198         u8 eeprom_pwrgroup[2][3];
1199         u8 pwrgroup_ht20[2][CHANNEL_MAX_NUMBER];
1200         u8 pwrgroup_ht40[2][CHANNEL_MAX_NUMBER];
1201
1202         char txpwr_ht20diff[2][CHANNEL_MAX_NUMBER]; /*HT 20<->40 Pwr diff */
1203         /*For HT<->legacy pwr diff*/
1204         u8 txpwr_legacyhtdiff[2][CHANNEL_MAX_NUMBER];
1205         u8 txpwr_safetyflag;                    /* Band edge enable flag */
1206         u16 eeprom_txpowerdiff;
1207         u8 legacy_httxpowerdiff;        /* Legacy to HT rate power diff */
1208         u8 antenna_txpwdiff[3];
1209
1210         u8 eeprom_regulatory;
1211         u8 eeprom_thermalmeter;
1212         u8 thermalmeter[2]; /*ThermalMeter, index 0 for RFIC0, 1 for RFIC1 */
1213         u16 tssi_13dbm;
1214         u8 crystalcap;          /* CrystalCap. */
1215         u8 delta_iqk;
1216         u8 delta_lck;
1217
1218         u8 legacy_ht_txpowerdiff;       /*Legacy to HT rate power diff */
1219         bool apk_thermalmeterignore;
1220
1221         bool b1x1_recvcombine;
1222         bool b1ss_support;
1223
1224         /*channel plan */
1225         u8 channel_plan;
1226 };
1227
1228 struct rtl_ps_ctl {
1229         bool pwrdomain_protect;
1230         bool in_powersavemode;
1231         bool rfchange_inprogress;
1232         bool swrf_processing;
1233         bool hwradiooff;
1234
1235         /*
1236          * just for PCIE ASPM
1237          * If it supports ASPM, Offset[560h] = 0x40,
1238          * otherwise Offset[560h] = 0x00.
1239          * */
1240         bool support_aspm;
1241
1242         bool support_backdoor;
1243
1244         /*for LPS */
1245         enum rt_psmode dot11_psmode;    /*Power save mode configured. */
1246         bool swctrl_lps;
1247         bool leisure_ps;
1248         bool fwctrl_lps;
1249         u8 fwctrl_psmode;
1250         /*For Fw control LPS mode */
1251         u8 reg_fwctrl_lps;
1252         /*Record Fw PS mode status. */
1253         bool fw_current_inpsmode;
1254         u8 reg_max_lps_awakeintvl;
1255         bool report_linked;
1256
1257         /*for IPS */
1258         bool inactiveps;
1259
1260         u32 rfoff_reason;
1261
1262         /*RF OFF Level */
1263         u32 cur_ps_level;
1264         u32 reg_rfps_level;
1265
1266         /*just for PCIE ASPM */
1267         u8 const_amdpci_aspm;
1268         bool pwrdown_mode;
1269
1270         enum rf_pwrstate inactive_pwrstate;
1271         enum rf_pwrstate rfpwr_state;   /*cur power state */
1272
1273         /* for SW LPS*/
1274         bool sw_ps_enabled;
1275         bool state;
1276         bool state_inap;
1277         bool multi_buffered;
1278         u16 nullfunc_seq;
1279         unsigned int dtim_counter;
1280         unsigned int sleep_ms;
1281         unsigned long last_sleep_jiffies;
1282         unsigned long last_awake_jiffies;
1283         unsigned long last_delaylps_stamp_jiffies;
1284         unsigned long last_dtim;
1285         unsigned long last_beacon;
1286         unsigned long last_action;
1287         unsigned long last_slept;
1288 };
1289
1290 struct rtl_stats {
1291         u32 mac_time[2];
1292         s8 rssi;
1293         u8 signal;
1294         u8 noise;
1295         u16 rate;               /*in 100 kbps */
1296         u8 received_channel;
1297         u8 control;
1298         u8 mask;
1299         u8 freq;
1300         u16 len;
1301         u64 tsf;
1302         u32 beacon_time;
1303         u8 nic_type;
1304         u16 length;
1305         u8 signalquality;       /*in 0-100 index. */
1306         /*
1307          * Real power in dBm for this packet,
1308          * no beautification and aggregation.
1309          * */
1310         s32 recvsignalpower;
1311         s8 rxpower;             /*in dBm Translate from PWdB */
1312         u8 signalstrength;      /*in 0-100 index. */
1313         u16 hwerror:1;
1314         u16 crc:1;
1315         u16 icv:1;
1316         u16 shortpreamble:1;
1317         u16 antenna:1;
1318         u16 decrypted:1;
1319         u16 wakeup:1;
1320         u32 timestamp_low;
1321         u32 timestamp_high;
1322
1323         u8 rx_drvinfo_size;
1324         u8 rx_bufshift;
1325         bool isampdu;
1326         bool isfirst_ampdu;
1327         bool rx_is40Mhzpacket;
1328         u32 rx_pwdb_all;
1329         u8 rx_mimo_signalstrength[4];   /*in 0~100 index */
1330         s8 rx_mimo_signalquality[2];
1331         bool packet_matchbssid;
1332         bool is_cck;
1333         bool is_ht;
1334         bool packet_toself;
1335         bool packet_beacon;     /*for rssi */
1336         char cck_adc_pwdb[4];   /*for rx path selection */
1337 };
1338
1339 struct rt_link_detect {
1340         u32 num_tx_in4period[4];
1341         u32 num_rx_in4period[4];
1342
1343         u32 num_tx_inperiod;
1344         u32 num_rx_inperiod;
1345
1346         bool busytraffic;
1347         bool higher_busytraffic;
1348         bool higher_busyrxtraffic;
1349
1350         u32 tidtx_in4period[MAX_TID_COUNT][4];
1351         u32 tidtx_inperiod[MAX_TID_COUNT];
1352         bool higher_busytxtraffic[MAX_TID_COUNT];
1353 };
1354
1355 struct rtl_tcb_desc {
1356         u8 packet_bw:1;
1357         u8 multicast:1;
1358         u8 broadcast:1;
1359
1360         u8 rts_stbc:1;
1361         u8 rts_enable:1;
1362         u8 cts_enable:1;
1363         u8 rts_use_shortpreamble:1;
1364         u8 rts_use_shortgi:1;
1365         u8 rts_sc:1;
1366         u8 rts_bw:1;
1367         u8 rts_rate;
1368
1369         u8 use_shortgi:1;
1370         u8 use_shortpreamble:1;
1371         u8 use_driver_rate:1;
1372         u8 disable_ratefallback:1;
1373
1374         u8 ratr_index;
1375         u8 mac_id;
1376         u8 hw_rate;
1377
1378         u8 last_inipkt:1;
1379         u8 cmd_or_init:1;
1380         u8 queue_index;
1381
1382         /* early mode */
1383         u8 empkt_num;
1384         /* The max value by HW */
1385         u32 empkt_len[5];
1386 };
1387
1388 struct rtl_hal_ops {
1389         int (*init_sw_vars) (struct ieee80211_hw *hw);
1390         void (*deinit_sw_vars) (struct ieee80211_hw *hw);
1391         void (*read_chip_version)(struct ieee80211_hw *hw);
1392         void (*read_eeprom_info) (struct ieee80211_hw *hw);
1393         void (*interrupt_recognized) (struct ieee80211_hw *hw,
1394                                       u32 *p_inta, u32 *p_intb);
1395         int (*hw_init) (struct ieee80211_hw *hw);
1396         void (*hw_disable) (struct ieee80211_hw *hw);
1397         void (*hw_suspend) (struct ieee80211_hw *hw);
1398         void (*hw_resume) (struct ieee80211_hw *hw);
1399         void (*enable_interrupt) (struct ieee80211_hw *hw);
1400         void (*disable_interrupt) (struct ieee80211_hw *hw);
1401         int (*set_network_type) (struct ieee80211_hw *hw,
1402                                  enum nl80211_iftype type);
1403         void (*set_chk_bssid)(struct ieee80211_hw *hw,
1404                                 bool check_bssid);
1405         void (*set_bw_mode) (struct ieee80211_hw *hw,
1406                              enum nl80211_channel_type ch_type);
1407          u8(*switch_channel) (struct ieee80211_hw *hw);
1408         void (*set_qos) (struct ieee80211_hw *hw, int aci);
1409         void (*set_bcn_reg) (struct ieee80211_hw *hw);
1410         void (*set_bcn_intv) (struct ieee80211_hw *hw);
1411         void (*update_interrupt_mask) (struct ieee80211_hw *hw,
1412                                        u32 add_msr, u32 rm_msr);
1413         void (*get_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val);
1414         void (*set_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val);
1415         void (*update_rate_tbl) (struct ieee80211_hw *hw,
1416                               struct ieee80211_sta *sta, u8 rssi_level);
1417         void (*update_rate_mask) (struct ieee80211_hw *hw, u8 rssi_level);
1418         void (*fill_tx_desc) (struct ieee80211_hw *hw,
1419                               struct ieee80211_hdr *hdr, u8 *pdesc_tx,
1420                               struct ieee80211_tx_info *info,
1421                               struct sk_buff *skb, u8 hw_queue,
1422                               struct rtl_tcb_desc *ptcb_desc);
1423         void (*fill_fake_txdesc) (struct ieee80211_hw *hw, u8 *pDesc,
1424                                   u32 buffer_len, bool bIsPsPoll);
1425         void (*fill_tx_cmddesc) (struct ieee80211_hw *hw, u8 *pdesc,
1426                                  bool firstseg, bool lastseg,
1427                                  struct sk_buff *skb);
1428         bool (*cmd_send_packet)(struct ieee80211_hw *hw, struct sk_buff *skb);
1429         bool (*query_rx_desc) (struct ieee80211_hw *hw,
1430                                struct rtl_stats *stats,
1431                                struct ieee80211_rx_status *rx_status,
1432                                u8 *pdesc, struct sk_buff *skb);
1433         void (*set_channel_access) (struct ieee80211_hw *hw);
1434         bool (*radio_onoff_checking) (struct ieee80211_hw *hw, u8 *valid);
1435         void (*dm_watchdog) (struct ieee80211_hw *hw);
1436         void (*scan_operation_backup) (struct ieee80211_hw *hw, u8 operation);
1437         bool (*set_rf_power_state) (struct ieee80211_hw *hw,
1438                                     enum rf_pwrstate rfpwr_state);
1439         void (*led_control) (struct ieee80211_hw *hw,
1440                              enum led_ctl_mode ledaction);
1441         void (*set_desc) (u8 *pdesc, bool istx, u8 desc_name, u8 *val);
1442         u32 (*get_desc) (u8 *pdesc, bool istx, u8 desc_name);
1443         void (*tx_polling) (struct ieee80211_hw *hw, u8 hw_queue);
1444         void (*enable_hw_sec) (struct ieee80211_hw *hw);
1445         void (*set_key) (struct ieee80211_hw *hw, u32 key_index,
1446                          u8 *macaddr, bool is_group, u8 enc_algo,
1447                          bool is_wepkey, bool clear_all);
1448         void (*init_sw_leds) (struct ieee80211_hw *hw);
1449         void (*deinit_sw_leds) (struct ieee80211_hw *hw);
1450         u32 (*get_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask);
1451         void (*set_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask,
1452                            u32 data);
1453         u32 (*get_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath,
1454                           u32 regaddr, u32 bitmask);
1455         void (*set_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath,
1456                            u32 regaddr, u32 bitmask, u32 data);
1457         void (*linked_set_reg) (struct ieee80211_hw *hw);
1458         bool (*phy_rf6052_config) (struct ieee80211_hw *hw);
1459         void (*phy_rf6052_set_cck_txpower) (struct ieee80211_hw *hw,
1460                                             u8 *powerlevel);
1461         void (*phy_rf6052_set_ofdm_txpower) (struct ieee80211_hw *hw,
1462                                              u8 *ppowerlevel, u8 channel);
1463         bool (*config_bb_with_headerfile) (struct ieee80211_hw *hw,
1464                                            u8 configtype);
1465         bool (*config_bb_with_pgheaderfile) (struct ieee80211_hw *hw,
1466                                              u8 configtype);
1467         void (*phy_lc_calibrate) (struct ieee80211_hw *hw, bool is2t);
1468         void (*phy_set_bw_mode_callback) (struct ieee80211_hw *hw);
1469         void (*dm_dynamic_txpower) (struct ieee80211_hw *hw);
1470 };
1471
1472 struct rtl_intf_ops {
1473         /*com */
1474         void (*read_efuse_byte)(struct ieee80211_hw *hw, u16 _offset, u8 *pbuf);
1475         int (*adapter_start) (struct ieee80211_hw *hw);
1476         void (*adapter_stop) (struct ieee80211_hw *hw);
1477
1478         int (*adapter_tx) (struct ieee80211_hw *hw, struct sk_buff *skb,
1479                         struct rtl_tcb_desc *ptcb_desc);
1480         void (*flush)(struct ieee80211_hw *hw, bool drop);
1481         int (*reset_trx_ring) (struct ieee80211_hw *hw);
1482         bool (*waitq_insert) (struct ieee80211_hw *hw, struct sk_buff *skb);
1483
1484         /*pci */
1485         void (*disable_aspm) (struct ieee80211_hw *hw);
1486         void (*enable_aspm) (struct ieee80211_hw *hw);
1487
1488         /*usb */
1489 };
1490
1491 struct rtl_mod_params {
1492         /* default: 0 = using hardware encryption */
1493         bool sw_crypto;
1494
1495         /* default: 0 = DBG_EMERG (0)*/
1496         int debug;
1497
1498         /* default: 1 = using no linked power save */
1499         bool inactiveps;
1500
1501         /* default: 1 = using linked sw power save */
1502         bool swctrl_lps;
1503
1504         /* default: 1 = using linked fw power save */
1505         bool fwctrl_lps;
1506 };
1507
1508 struct rtl_hal_usbint_cfg {
1509         /* data - rx */
1510         u32 in_ep_num;
1511         u32 rx_urb_num;
1512         u32 rx_max_size;
1513
1514         /* op - rx */
1515         void (*usb_rx_hdl)(struct ieee80211_hw *, struct sk_buff *);
1516         void (*usb_rx_segregate_hdl)(struct ieee80211_hw *, struct sk_buff *,
1517                                      struct sk_buff_head *);
1518
1519         /* tx */
1520         void (*usb_tx_cleanup)(struct ieee80211_hw *, struct sk_buff *);
1521         int (*usb_tx_post_hdl)(struct ieee80211_hw *, struct urb *,
1522                                struct sk_buff *);
1523         struct sk_buff *(*usb_tx_aggregate_hdl)(struct ieee80211_hw *,
1524                                                 struct sk_buff_head *);
1525
1526         /* endpoint mapping */
1527         int (*usb_endpoint_mapping)(struct ieee80211_hw *hw);
1528         u16 (*usb_mq_to_hwq)(__le16 fc, u16 mac80211_queue_index);
1529 };
1530
1531 struct rtl_hal_cfg {
1532         u8 bar_id;
1533         bool write_readback;
1534         char *name;
1535         char *fw_name;
1536         struct rtl_hal_ops *ops;
1537         struct rtl_mod_params *mod_params;
1538         struct rtl_hal_usbint_cfg *usb_interface_cfg;
1539
1540         /*this map used for some registers or vars
1541            defined int HAL but used in MAIN */
1542         u32 maps[RTL_VAR_MAP_MAX];
1543
1544 };
1545
1546 struct rtl_locks {
1547         /* mutex */
1548         struct mutex conf_mutex;
1549         struct mutex ps_mutex;
1550
1551         /*spin lock */
1552         spinlock_t ips_lock;
1553         spinlock_t irq_th_lock;
1554         spinlock_t h2c_lock;
1555         spinlock_t rf_ps_lock;
1556         spinlock_t rf_lock;
1557         spinlock_t waitq_lock;
1558
1559         /*Dual mac*/
1560         spinlock_t cck_and_rw_pagea_lock;
1561 };
1562
1563 struct rtl_works {
1564         struct ieee80211_hw *hw;
1565
1566         /*timer */
1567         struct timer_list watchdog_timer;
1568
1569         /*task */
1570         struct tasklet_struct irq_tasklet;
1571         struct tasklet_struct irq_prepare_bcn_tasklet;
1572
1573         /*work queue */
1574         struct workqueue_struct *rtl_wq;
1575         struct delayed_work watchdog_wq;
1576         struct delayed_work ips_nic_off_wq;
1577
1578         /* For SW LPS */
1579         struct delayed_work ps_work;
1580         struct delayed_work ps_rfon_wq;
1581
1582         struct work_struct lps_leave_work;
1583 };
1584
1585 struct rtl_debug {
1586         u32 dbgp_type[DBGP_TYPE_MAX];
1587         u32 global_debuglevel;
1588         u64 global_debugcomponents;
1589
1590         /* add for proc debug */
1591         struct proc_dir_entry *proc_dir;
1592         char proc_name[20];
1593 };
1594
1595 struct rtl_priv {
1596         struct rtl_locks locks;
1597         struct rtl_works works;
1598         struct rtl_mac mac80211;
1599         struct rtl_hal rtlhal;
1600         struct rtl_regulatory regd;
1601         struct rtl_rfkill rfkill;
1602         struct rtl_io io;
1603         struct rtl_phy phy;
1604         struct rtl_dm dm;
1605         struct rtl_security sec;
1606         struct rtl_efuse efuse;
1607
1608         struct rtl_ps_ctl psc;
1609         struct rate_adaptive ra;
1610         struct wireless_stats stats;
1611         struct rt_link_detect link_info;
1612         struct false_alarm_statistics falsealm_cnt;
1613
1614         struct rtl_rate_priv *rate_priv;
1615
1616         struct rtl_debug dbg;
1617
1618         /*
1619          *hal_cfg : for diff cards
1620          *intf_ops : for diff interrface usb/pcie
1621          */
1622         struct rtl_hal_cfg *cfg;
1623         struct rtl_intf_ops *intf_ops;
1624
1625         /*this var will be set by set_bit,
1626            and was used to indicate status of
1627            interface or hardware */
1628         unsigned long status;
1629
1630         /*This must be the last item so
1631            that it points to the data allocated
1632            beyond  this structure like:
1633            rtl_pci_priv or rtl_usb_priv */
1634         u8 priv[0];
1635 };
1636
1637 #define rtl_priv(hw)            (((struct rtl_priv *)(hw)->priv))
1638 #define rtl_mac(rtlpriv)        (&((rtlpriv)->mac80211))
1639 #define rtl_hal(rtlpriv)        (&((rtlpriv)->rtlhal))
1640 #define rtl_efuse(rtlpriv)      (&((rtlpriv)->efuse))
1641 #define rtl_psc(rtlpriv)        (&((rtlpriv)->psc))
1642
1643
1644 /***************************************
1645     Bluetooth Co-existence Related
1646 ****************************************/
1647
1648 enum bt_ant_num {
1649         ANT_X2 = 0,
1650         ANT_X1 = 1,
1651 };
1652
1653 enum bt_co_type {
1654         BT_2WIRE = 0,
1655         BT_ISSC_3WIRE = 1,
1656         BT_ACCEL = 2,
1657         BT_CSR_BC4 = 3,
1658         BT_CSR_BC8 = 4,
1659         BT_RTL8756 = 5,
1660 };
1661
1662 enum bt_cur_state {
1663         BT_OFF = 0,
1664         BT_ON = 1,
1665 };
1666
1667 enum bt_service_type {
1668         BT_SCO = 0,
1669         BT_A2DP = 1,
1670         BT_HID = 2,
1671         BT_HID_IDLE = 3,
1672         BT_SCAN = 4,
1673         BT_IDLE = 5,
1674         BT_OTHER_ACTION = 6,
1675         BT_BUSY = 7,
1676         BT_OTHERBUSY = 8,
1677         BT_PAN = 9,
1678 };
1679
1680 enum bt_radio_shared {
1681         BT_RADIO_SHARED = 0,
1682         BT_RADIO_INDIVIDUAL = 1,
1683 };
1684
1685 struct bt_coexist_info {
1686
1687         /* EEPROM BT info. */
1688         u8 eeprom_bt_coexist;
1689         u8 eeprom_bt_type;
1690         u8 eeprom_bt_ant_num;
1691         u8 eeprom_bt_ant_isolation;
1692         u8 eeprom_bt_radio_shared;
1693
1694         u8 bt_coexistence;
1695         u8 bt_ant_num;
1696         u8 bt_coexist_type;
1697         u8 bt_state;
1698         u8 bt_cur_state;        /* 0:on, 1:off */
1699         u8 bt_ant_isolation;    /* 0:good, 1:bad */
1700         u8 bt_pape_ctrl;        /* 0:SW, 1:SW/HW dynamic */
1701         u8 bt_service;
1702         u8 bt_radio_shared_type;
1703         u8 bt_rfreg_origin_1e;
1704         u8 bt_rfreg_origin_1f;
1705         u8 bt_rssi_state;
1706         u32 ratio_tx;
1707         u32 ratio_pri;
1708         u32 bt_edca_ul;
1709         u32 bt_edca_dl;
1710
1711         bool init_set;
1712         bool bt_busy_traffic;
1713         bool bt_traffic_mode_set;
1714         bool bt_non_traffic_mode_set;
1715
1716         bool fw_coexist_all_off;
1717         bool sw_coexist_all_off;
1718         u32 current_state;
1719         u32 previous_state;
1720         u8 bt_pre_rssi_state;
1721
1722         u8 reg_bt_iso;
1723         u8 reg_bt_sco;
1724
1725 };
1726
1727
1728 /****************************************
1729         mem access macro define start
1730         Call endian free function when
1731         1. Read/write packet content.
1732         2. Before write integer to IO.
1733         3. After read integer from IO.
1734 ****************************************/
1735 /* Convert little data endian to host ordering */
1736 #define EF1BYTE(_val)           \
1737         ((u8)(_val))
1738 #define EF2BYTE(_val)           \
1739         (le16_to_cpu(_val))
1740 #define EF4BYTE(_val)           \
1741         (le32_to_cpu(_val))
1742
1743 /* Read data from memory */
1744 #define READEF1BYTE(_ptr)       \
1745         EF1BYTE(*((u8 *)(_ptr)))
1746 /* Read le16 data from memory and convert to host ordering */
1747 #define READEF2BYTE(_ptr)       \
1748         EF2BYTE(*((u16 *)(_ptr)))
1749 #define READEF4BYTE(_ptr)       \
1750         EF4BYTE(*((u32 *)(_ptr)))
1751
1752 /* Write data to memory */
1753 #define WRITEEF1BYTE(_ptr, _val)        \
1754         (*((u8 *)(_ptr))) = EF1BYTE(_val)
1755 /* Write le16 data to memory in host ordering */
1756 #define WRITEEF2BYTE(_ptr, _val)        \
1757         (*((u16 *)(_ptr))) = EF2BYTE(_val)
1758 #define WRITEEF4BYTE(_ptr, _val)        \
1759         (*((u16 *)(_ptr))) = EF2BYTE(_val)
1760
1761 /* Create a bit mask
1762  * Examples:
1763  * BIT_LEN_MASK_32(0) => 0x00000000
1764  * BIT_LEN_MASK_32(1) => 0x00000001
1765  * BIT_LEN_MASK_32(2) => 0x00000003
1766  * BIT_LEN_MASK_32(32) => 0xFFFFFFFF
1767  */
1768 #define BIT_LEN_MASK_32(__bitlen)        \
1769         (0xFFFFFFFF >> (32 - (__bitlen)))
1770 #define BIT_LEN_MASK_16(__bitlen)        \
1771         (0xFFFF >> (16 - (__bitlen)))
1772 #define BIT_LEN_MASK_8(__bitlen) \
1773         (0xFF >> (8 - (__bitlen)))
1774
1775 /* Create an offset bit mask
1776  * Examples:
1777  * BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003
1778  * BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000
1779  */
1780 #define BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen) \
1781         (BIT_LEN_MASK_32(__bitlen) << (__bitoffset))
1782 #define BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen) \
1783         (BIT_LEN_MASK_16(__bitlen) << (__bitoffset))
1784 #define BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen) \
1785         (BIT_LEN_MASK_8(__bitlen) << (__bitoffset))
1786
1787 /*Description:
1788  * Return 4-byte value in host byte ordering from
1789  * 4-byte pointer in little-endian system.
1790  */
1791 #define LE_P4BYTE_TO_HOST_4BYTE(__pstart) \
1792         (EF4BYTE(*((u32 *)(__pstart))))
1793 #define LE_P2BYTE_TO_HOST_2BYTE(__pstart) \
1794         (EF2BYTE(*((u16 *)(__pstart))))
1795 #define LE_P1BYTE_TO_HOST_1BYTE(__pstart) \
1796         (EF1BYTE(*((u8 *)(__pstart))))
1797
1798 /*Description:
1799 Translate subfield (continuous bits in little-endian) of 4-byte
1800 value to host byte ordering.*/
1801 #define LE_BITS_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
1802         ( \
1803                 (LE_P4BYTE_TO_HOST_4BYTE(__pstart) >> (__bitoffset))  & \
1804                 BIT_LEN_MASK_32(__bitlen) \
1805         )
1806 #define LE_BITS_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
1807         ( \
1808                 (LE_P2BYTE_TO_HOST_2BYTE(__pstart) >> (__bitoffset)) & \
1809                 BIT_LEN_MASK_16(__bitlen) \
1810         )
1811 #define LE_BITS_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
1812         ( \
1813                 (LE_P1BYTE_TO_HOST_1BYTE(__pstart) >> (__bitoffset)) & \
1814                 BIT_LEN_MASK_8(__bitlen) \
1815         )
1816
1817 /* Description:
1818  * Mask subfield (continuous bits in little-endian) of 4-byte value
1819  * and return the result in 4-byte value in host byte ordering.
1820  */
1821 #define LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
1822         ( \
1823                 LE_P4BYTE_TO_HOST_4BYTE(__pstart)  & \
1824                 (~BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen)) \
1825         )
1826 #define LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
1827         ( \
1828                 LE_P2BYTE_TO_HOST_2BYTE(__pstart) & \
1829                 (~BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen)) \
1830         )
1831 #define LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
1832         ( \
1833                 LE_P1BYTE_TO_HOST_1BYTE(__pstart) & \
1834                 (~BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen)) \
1835         )
1836
1837 /* Description:
1838  * Set subfield of little-endian 4-byte value to specified value.
1839  */
1840 #define SET_BITS_TO_LE_4BYTE(__pstart, __bitoffset, __bitlen, __val) \
1841         *((u32 *)(__pstart)) = EF4BYTE \
1842         ( \
1843                 LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) | \
1844                 ((((u32)__val) & BIT_LEN_MASK_32(__bitlen)) << (__bitoffset)) \
1845         );
1846 #define SET_BITS_TO_LE_2BYTE(__pstart, __bitoffset, __bitlen, __val) \
1847         *((u16 *)(__pstart)) = EF2BYTE \
1848         ( \
1849                 LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) | \
1850                 ((((u16)__val) & BIT_LEN_MASK_16(__bitlen)) << (__bitoffset)) \
1851         );
1852 #define SET_BITS_TO_LE_1BYTE(__pstart, __bitoffset, __bitlen, __val) \
1853         *((u8 *)(__pstart)) = EF1BYTE \
1854         ( \
1855                 LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) | \
1856                 ((((u8)__val) & BIT_LEN_MASK_8(__bitlen)) << (__bitoffset)) \
1857         );
1858
1859 #define N_BYTE_ALIGMENT(__value, __aligment) ((__aligment == 1) ? \
1860         (__value) : (((__value + __aligment - 1) / __aligment) * __aligment))
1861
1862 /****************************************
1863         mem access macro define end
1864 ****************************************/
1865
1866 #define byte(x, n) ((x >> (8 * n)) & 0xff)
1867
1868 #define packet_get_type(_packet) (EF1BYTE((_packet).octet[0]) & 0xFC)
1869 #define RTL_WATCH_DOG_TIME      2000
1870 #define MSECS(t)                msecs_to_jiffies(t)
1871 #define WLAN_FC_GET_VERS(fc)    (le16_to_cpu(fc) & IEEE80211_FCTL_VERS)
1872 #define WLAN_FC_GET_TYPE(fc)    (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE)
1873 #define WLAN_FC_GET_STYPE(fc)   (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE)
1874 #define WLAN_FC_MORE_DATA(fc)   (le16_to_cpu(fc) & IEEE80211_FCTL_MOREDATA)
1875 #define SEQ_TO_SN(seq)          (((seq) & IEEE80211_SCTL_SEQ) >> 4)
1876 #define SN_TO_SEQ(ssn)          (((ssn) << 4) & IEEE80211_SCTL_SEQ)
1877 #define MAX_SN                  ((IEEE80211_SCTL_SEQ) >> 4)
1878
1879 #define RT_RF_OFF_LEVL_ASPM             BIT(0)  /*PCI ASPM */
1880 #define RT_RF_OFF_LEVL_CLK_REQ          BIT(1)  /*PCI clock request */
1881 #define RT_RF_OFF_LEVL_PCI_D3           BIT(2)  /*PCI D3 mode */
1882 /*NIC halt, re-initialize hw parameters*/
1883 #define RT_RF_OFF_LEVL_HALT_NIC         BIT(3)
1884 #define RT_RF_OFF_LEVL_FREE_FW          BIT(4)  /*FW free, re-download the FW */
1885 #define RT_RF_OFF_LEVL_FW_32K           BIT(5)  /*FW in 32k */
1886 /*Always enable ASPM and Clock Req in initialization.*/
1887 #define RT_RF_PS_LEVEL_ALWAYS_ASPM      BIT(6)
1888 /* no matter RFOFF or SLEEP we set PS_ASPM_LEVL*/
1889 #define RT_PS_LEVEL_ASPM                BIT(7)
1890 /*When LPS is on, disable 2R if no packet is received or transmittd.*/
1891 #define RT_RF_LPS_DISALBE_2R            BIT(30)
1892 #define RT_RF_LPS_LEVEL_ASPM            BIT(31) /*LPS with ASPM */
1893 #define RT_IN_PS_LEVEL(ppsc, _ps_flg)           \
1894         ((ppsc->cur_ps_level & _ps_flg) ? true : false)
1895 #define RT_CLEAR_PS_LEVEL(ppsc, _ps_flg)        \
1896         (ppsc->cur_ps_level &= (~(_ps_flg)))
1897 #define RT_SET_PS_LEVEL(ppsc, _ps_flg)          \
1898         (ppsc->cur_ps_level |= _ps_flg)
1899
1900 #define container_of_dwork_rtl(x, y, z) \
1901         container_of(container_of(x, struct delayed_work, work), y, z)
1902
1903 #define FILL_OCTET_STRING(_os, _octet, _len)    \
1904                 (_os).octet = (u8 *)(_octet);           \
1905                 (_os).length = (_len);
1906
1907 #define CP_MACADDR(des, src)    \
1908         ((des)[0] = (src)[0], (des)[1] = (src)[1],\
1909         (des)[2] = (src)[2], (des)[3] = (src)[3],\
1910         (des)[4] = (src)[4], (des)[5] = (src)[5])
1911
1912 static inline u8 rtl_read_byte(struct rtl_priv *rtlpriv, u32 addr)
1913 {
1914         return rtlpriv->io.read8_sync(rtlpriv, addr);
1915 }
1916
1917 static inline u16 rtl_read_word(struct rtl_priv *rtlpriv, u32 addr)
1918 {
1919         return rtlpriv->io.read16_sync(rtlpriv, addr);
1920 }
1921
1922 static inline u32 rtl_read_dword(struct rtl_priv *rtlpriv, u32 addr)
1923 {
1924         return rtlpriv->io.read32_sync(rtlpriv, addr);
1925 }
1926
1927 static inline void rtl_write_byte(struct rtl_priv *rtlpriv, u32 addr, u8 val8)
1928 {
1929         rtlpriv->io.write8_async(rtlpriv, addr, val8);
1930
1931         if (rtlpriv->cfg->write_readback)
1932                 rtlpriv->io.read8_sync(rtlpriv, addr);
1933 }
1934
1935 static inline void rtl_write_word(struct rtl_priv *rtlpriv, u32 addr, u16 val16)
1936 {
1937         rtlpriv->io.write16_async(rtlpriv, addr, val16);
1938
1939         if (rtlpriv->cfg->write_readback)
1940                 rtlpriv->io.read16_sync(rtlpriv, addr);
1941 }
1942
1943 static inline void rtl_write_dword(struct rtl_priv *rtlpriv,
1944                                    u32 addr, u32 val32)
1945 {
1946         rtlpriv->io.write32_async(rtlpriv, addr, val32);
1947
1948         if (rtlpriv->cfg->write_readback)
1949                 rtlpriv->io.read32_sync(rtlpriv, addr);
1950 }
1951
1952 static inline u32 rtl_get_bbreg(struct ieee80211_hw *hw,
1953                                 u32 regaddr, u32 bitmask)
1954 {
1955         return ((struct rtl_priv *)(hw)->priv)->cfg->ops->get_bbreg(hw,
1956                                                                     regaddr,
1957                                                                     bitmask);
1958 }
1959
1960 static inline void rtl_set_bbreg(struct ieee80211_hw *hw, u32 regaddr,
1961                                  u32 bitmask, u32 data)
1962 {
1963         ((struct rtl_priv *)(hw)->priv)->cfg->ops->set_bbreg(hw,
1964                                                              regaddr, bitmask,
1965                                                              data);
1966
1967 }
1968
1969 static inline u32 rtl_get_rfreg(struct ieee80211_hw *hw,
1970                                 enum radio_path rfpath, u32 regaddr,
1971                                 u32 bitmask)
1972 {
1973         return ((struct rtl_priv *)(hw)->priv)->cfg->ops->get_rfreg(hw,
1974                                                                     rfpath,
1975                                                                     regaddr,
1976                                                                     bitmask);
1977 }
1978
1979 static inline void rtl_set_rfreg(struct ieee80211_hw *hw,
1980                                  enum radio_path rfpath, u32 regaddr,
1981                                  u32 bitmask, u32 data)
1982 {
1983         ((struct rtl_priv *)(hw)->priv)->cfg->ops->set_rfreg(hw,
1984                                                              rfpath, regaddr,
1985                                                              bitmask, data);
1986 }
1987
1988 static inline bool is_hal_stop(struct rtl_hal *rtlhal)
1989 {
1990         return (_HAL_STATE_STOP == rtlhal->state);
1991 }
1992
1993 static inline void set_hal_start(struct rtl_hal *rtlhal)
1994 {
1995         rtlhal->state = _HAL_STATE_START;
1996 }
1997
1998 static inline void set_hal_stop(struct rtl_hal *rtlhal)
1999 {
2000         rtlhal->state = _HAL_STATE_STOP;
2001 }
2002
2003 static inline u8 get_rf_type(struct rtl_phy *rtlphy)
2004 {
2005         return rtlphy->rf_type;
2006 }
2007
2008 static inline struct ieee80211_hdr *rtl_get_hdr(struct sk_buff *skb)
2009 {
2010         return (struct ieee80211_hdr *)(skb->data);
2011 }
2012
2013 static inline __le16 rtl_get_fc(struct sk_buff *skb)
2014 {
2015         return rtl_get_hdr(skb)->frame_control;
2016 }
2017
2018 static inline u16 rtl_get_tid_h(struct ieee80211_hdr *hdr)
2019 {
2020         return (ieee80211_get_qos_ctl(hdr))[0] & IEEE80211_QOS_CTL_TID_MASK;
2021 }
2022
2023 static inline u16 rtl_get_tid(struct sk_buff *skb)
2024 {
2025         return rtl_get_tid_h(rtl_get_hdr(skb));
2026 }
2027
2028 static inline struct ieee80211_sta *get_sta(struct ieee80211_hw *hw,
2029                                             struct ieee80211_vif *vif,
2030                                             const u8 *bssid)
2031 {
2032         return ieee80211_find_sta(vif, bssid);
2033 }
2034
2035 #endif