drivers/net/wireless/rtlwifi/wifi.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2012  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * wlanfae <wlanfae@realtek.com>
  23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24  * Hsinchu 300, Taiwan.
  25  *
  26  * Larry Finger <Larry.Finger@lwfinger.net>
  27  *
  28  *****************************************************************************/
  29
  30 #ifndef __RTL_WIFI_H__
  31 #define __RTL_WIFI_H__
  32
  33 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  34
  35 #include <linux/sched.h>
  36 #include <linux/firmware.h>
  37 #include <linux/etherdevice.h>
  38 #include <linux/vmalloc.h>
  39 #include <linux/usb.h>
  40 #include <net/mac80211.h>
  41 #include <linux/completion.h>
  42 #include "debug.h"
  43
  44 #define RF_CHANGE_BY_INIT                       0
  45 #define RF_CHANGE_BY_IPS                        BIT(28)
  46 #define RF_CHANGE_BY_PS                         BIT(29)
  47 #define RF_CHANGE_BY_HW                         BIT(30)
  48 #define RF_CHANGE_BY_SW                         BIT(31)
  49
  50 #define IQK_ADDA_REG_NUM                        16
  51 #define IQK_MAC_REG_NUM                         4
  52
  53 #define MAX_KEY_LEN                             61
  54 #define KEY_BUF_SIZE                            5
  55
  56 /* QoS related. */
  57 /*aci: 0x00     Best Effort*/
  58 /*aci: 0x01     Background*/
  59 /*aci: 0x10     Video*/
  60 /*aci: 0x11     Voice*/
  61 /*Max: define total number.*/
  62 #define AC0_BE                                  0
  63 #define AC1_BK                                  1
  64 #define AC2_VI                                  2
  65 #define AC3_VO                                  3
  66 #define AC_MAX                                  4
  67 #define QOS_QUEUE_NUM                           4
  68 #define RTL_MAC80211_NUM_QUEUE                  5
  69 #define REALTEK_USB_VENQT_MAX_BUF_SIZE          254
  70 #define RTL_USB_MAX_RX_COUNT                    100
  71 #define QBSS_LOAD_SIZE                          5
  72 #define MAX_WMMELE_LENGTH                       64
  73
  74 #define TOTAL_CAM_ENTRY                         32
  75
  76 /*slot time for 11g. */
  77 #define RTL_SLOT_TIME_9                         9
  78 #define RTL_SLOT_TIME_20                        20
  79
  80 /*related with tcp/ip. */
  81 /*if_ehther.h*/
  82 #define ETH_P_PAE               0x888E  /*Port Access Entity (IEEE 802.1X) */
  83 #define ETH_P_IP                0x0800  /*Internet Protocol packet */
  84 #define ETH_P_ARP               0x0806  /*Address Resolution packet */
  85 #define SNAP_SIZE               6
  86 #define PROTOC_TYPE_SIZE        2
  87
  88 /*related with 802.11 frame*/
  89 #define MAC80211_3ADDR_LEN                      24
  90 #define MAC80211_4ADDR_LEN                      30
  91
  92 #define CHANNEL_MAX_NUMBER      (14 + 24 + 21)  /* 14 is the max channel no */
  93 #define CHANNEL_GROUP_MAX       (3 + 9) /*  ch1~3, 4~9, 10~14 = three groups */
  94 #define MAX_PG_GROUP                    13
  95 #define CHANNEL_GROUP_MAX_2G            3
  96 #define CHANNEL_GROUP_IDX_5GL           3
  97 #define CHANNEL_GROUP_IDX_5GM           6
  98 #define CHANNEL_GROUP_IDX_5GH           9
  99 #define CHANNEL_GROUP_MAX_5G            9
 100 #define CHANNEL_MAX_NUMBER_2G           14
 101 #define AVG_THERMAL_NUM                 8
 102 #define AVG_THERMAL_NUM_88E             4
 103 #define MAX_TID_COUNT                   9
 104
 105 /* for early mode */
 106 #define FCS_LEN                         4
 107 #define EM_HDR_LEN                      8
 108
 109 #define MAX_TX_COUNT                    4
 110 #define MAX_RF_PATH                     4
 111 #define MAX_CHNL_GROUP_24G              6
 112 #define MAX_CHNL_GROUP_5G               14
 113
 114 struct txpower_info_2g {
 115         u8 index_cck_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
 116         u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
 117         /*If only one tx, only BW20 and OFDM are used.*/
 118         u8 cck_diff[MAX_RF_PATH][MAX_TX_COUNT];
 119         u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT];
 120         u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT];
 121         u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT];
 122 };
 123
 124 struct txpower_info_5g {
 125         u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_5G];
 126         /*If only one tx, only BW20, OFDM, BW80 and BW160 are used.*/
 127         u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT];
 128         u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT];
 129         u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT];
 130 };
 131
 132 enum intf_type {
 133         INTF_PCI = 0,
 134         INTF_USB = 1,
 135 };
 136
 137 enum radio_path {
 138         RF90_PATH_A = 0,
 139         RF90_PATH_B = 1,
 140         RF90_PATH_C = 2,
 141         RF90_PATH_D = 3,
 142 };
 143
 144 enum rt_eeprom_type {
 145         EEPROM_93C46,
 146         EEPROM_93C56,
 147         EEPROM_BOOT_EFUSE,
 148 };
 149
 150 enum ttl_status {
 151         RTL_STATUS_INTERFACE_START = 0,
 152 };
 153
 154 enum hardware_type {
 155         HARDWARE_TYPE_RTL8192E,
 156         HARDWARE_TYPE_RTL8192U,
 157         HARDWARE_TYPE_RTL8192SE,
 158         HARDWARE_TYPE_RTL8192SU,
 159         HARDWARE_TYPE_RTL8192CE,
 160         HARDWARE_TYPE_RTL8192CU,
 161         HARDWARE_TYPE_RTL8192DE,
 162         HARDWARE_TYPE_RTL8192DU,
 163         HARDWARE_TYPE_RTL8723AE,
 164         HARDWARE_TYPE_RTL8723U,
 165
 166         /* keep it last */
 167         HARDWARE_TYPE_NUM
 168 };
 169
 170 #define IS_HARDWARE_TYPE_8192SU(rtlhal)                 \
 171         (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SU)
 172 #define IS_HARDWARE_TYPE_8192SE(rtlhal)                 \
 173         (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
 174 #define IS_HARDWARE_TYPE_8192CE(rtlhal)                 \
 175         (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CE)
 176 #define IS_HARDWARE_TYPE_8192CU(rtlhal)                 \
 177         (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CU)
 178 #define IS_HARDWARE_TYPE_8192DE(rtlhal)                 \
 179         (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE)
 180 #define IS_HARDWARE_TYPE_8192DU(rtlhal)                 \
 181         (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DU)
 182 #define IS_HARDWARE_TYPE_8723E(rtlhal)                  \
 183         (rtlhal->hw_type == HARDWARE_TYPE_RTL8723E)
 184 #define IS_HARDWARE_TYPE_8723U(rtlhal)                  \
 185         (rtlhal->hw_type == HARDWARE_TYPE_RTL8723U)
 186 #define IS_HARDWARE_TYPE_8192S(rtlhal)                  \
 187 (IS_HARDWARE_TYPE_8192SE(rtlhal) || IS_HARDWARE_TYPE_8192SU(rtlhal))
 188 #define IS_HARDWARE_TYPE_8192C(rtlhal)                  \
 189 (IS_HARDWARE_TYPE_8192CE(rtlhal) || IS_HARDWARE_TYPE_8192CU(rtlhal))
 190 #define IS_HARDWARE_TYPE_8192D(rtlhal)                  \
 191 (IS_HARDWARE_TYPE_8192DE(rtlhal) || IS_HARDWARE_TYPE_8192DU(rtlhal))
 192 #define IS_HARDWARE_TYPE_8723(rtlhal)                   \
 193 (IS_HARDWARE_TYPE_8723E(rtlhal) || IS_HARDWARE_TYPE_8723U(rtlhal))
 194 #define IS_HARDWARE_TYPE_8723U(rtlhal)                  \
 195         (rtlhal->hw_type == HARDWARE_TYPE_RTL8723U)
 196
 197 #define RX_HAL_IS_CCK_RATE(_pdesc)\
 198         (_pdesc->rxmcs == DESC92_RATE1M ||              \
 199          _pdesc->rxmcs == DESC92_RATE2M ||              \
 200          _pdesc->rxmcs == DESC92_RATE5_5M ||            \
 201          _pdesc->rxmcs == DESC92_RATE11M)
 202
 203 enum scan_operation_backup_opt {
 204         SCAN_OPT_BACKUP = 0,
 205         SCAN_OPT_RESTORE,
 206         SCAN_OPT_MAX
 207 };
 208
 209 /*RF state.*/
 210 enum rf_pwrstate {
 211         ERFON,
 212         ERFSLEEP,
 213         ERFOFF
 214 };
 215
 216 struct bb_reg_def {
 217         u32 rfintfs;
 218         u32 rfintfi;
 219         u32 rfintfo;
 220         u32 rfintfe;
 221         u32 rf3wire_offset;
 222         u32 rflssi_select;
 223         u32 rftxgain_stage;
 224         u32 rfhssi_para1;
 225         u32 rfhssi_para2;
 226         u32 rfsw_ctrl;
 227         u32 rfagc_control1;
 228         u32 rfagc_control2;
 229         u32 rfrxiq_imbal;
 230         u32 rfrx_afe;
 231         u32 rftxiq_imbal;
 232         u32 rftx_afe;
 233         u32 rf_rb;              /* rflssi_readback */
 234         u32 rf_rbpi;            /* rflssi_readbackpi */
 235 };
 236
 237 enum io_type {
 238         IO_CMD_PAUSE_DM_BY_SCAN = 0,
 239         IO_CMD_RESUME_DM_BY_SCAN = 1,
 240 };
 241
 242 enum hw_variables {
 243         HW_VAR_ETHER_ADDR,
 244         HW_VAR_MULTICAST_REG,
 245         HW_VAR_BASIC_RATE,
 246         HW_VAR_BSSID,
 247         HW_VAR_MEDIA_STATUS,
 248         HW_VAR_SECURITY_CONF,
 249         HW_VAR_BEACON_INTERVAL,
 250         HW_VAR_ATIM_WINDOW,
 251         HW_VAR_LISTEN_INTERVAL,
 252         HW_VAR_CS_COUNTER,
 253         HW_VAR_DEFAULTKEY0,
 254         HW_VAR_DEFAULTKEY1,
 255         HW_VAR_DEFAULTKEY2,
 256         HW_VAR_DEFAULTKEY3,
 257         HW_VAR_SIFS,
 258         HW_VAR_DIFS,
 259         HW_VAR_EIFS,
 260         HW_VAR_SLOT_TIME,
 261         HW_VAR_ACK_PREAMBLE,
 262         HW_VAR_CW_CONFIG,
 263         HW_VAR_CW_VALUES,
 264         HW_VAR_RATE_FALLBACK_CONTROL,
 265         HW_VAR_CONTENTION_WINDOW,
 266         HW_VAR_RETRY_COUNT,
 267         HW_VAR_TR_SWITCH,
 268         HW_VAR_COMMAND,
 269         HW_VAR_WPA_CONFIG,
 270         HW_VAR_AMPDU_MIN_SPACE,
 271         HW_VAR_SHORTGI_DENSITY,
 272         HW_VAR_AMPDU_FACTOR,
 273         HW_VAR_MCS_RATE_AVAILABLE,
 274         HW_VAR_AC_PARAM,
 275         HW_VAR_ACM_CTRL,
 276         HW_VAR_DIS_Req_Qsize,
 277         HW_VAR_CCX_CHNL_LOAD,
 278         HW_VAR_CCX_NOISE_HISTOGRAM,
 279         HW_VAR_CCX_CLM_NHM,
 280         HW_VAR_TxOPLimit,
 281         HW_VAR_TURBO_MODE,
 282         HW_VAR_RF_STATE,
 283         HW_VAR_RF_OFF_BY_HW,
 284         HW_VAR_BUS_SPEED,
 285         HW_VAR_SET_DEV_POWER,
 286
 287         HW_VAR_RCR,
 288         HW_VAR_RATR_0,
 289         HW_VAR_RRSR,
 290         HW_VAR_CPU_RST,
 291         HW_VAR_CHECK_BSSID,
 292         HW_VAR_LBK_MODE,
 293         HW_VAR_AES_11N_FIX,
 294         HW_VAR_USB_RX_AGGR,
 295         HW_VAR_USER_CONTROL_TURBO_MODE,
 296         HW_VAR_RETRY_LIMIT,
 297         HW_VAR_INIT_TX_RATE,
 298         HW_VAR_TX_RATE_REG,
 299         HW_VAR_EFUSE_USAGE,
 300         HW_VAR_EFUSE_BYTES,
 301         HW_VAR_AUTOLOAD_STATUS,
 302         HW_VAR_RF_2R_DISABLE,
 303         HW_VAR_SET_RPWM,
 304         HW_VAR_H2C_FW_PWRMODE,
 305         HW_VAR_H2C_FW_JOINBSSRPT,
 306         HW_VAR_H2C_FW_P2P_PS_OFFLOAD,
 307         HW_VAR_FW_PSMODE_STATUS,
 308         HW_VAR_RESUME_CLK_ON,
 309         HW_VAR_FW_LPS_ACTION,
 310         HW_VAR_1X1_RECV_COMBINE,
 311         HW_VAR_STOP_SEND_BEACON,
 312         HW_VAR_TSF_TIMER,
 313         HW_VAR_IO_CMD,
 314
 315         HW_VAR_RF_RECOVERY,
 316         HW_VAR_H2C_FW_UPDATE_GTK,
 317         HW_VAR_WF_MASK,
 318         HW_VAR_WF_CRC,
 319         HW_VAR_WF_IS_MAC_ADDR,
 320         HW_VAR_H2C_FW_OFFLOAD,
 321         HW_VAR_RESET_WFCRC,
 322
 323         HW_VAR_HANDLE_FW_C2H,
 324         HW_VAR_DL_FW_RSVD_PAGE,
 325         HW_VAR_AID,
 326         HW_VAR_HW_SEQ_ENABLE,
 327         HW_VAR_CORRECT_TSF,
 328         HW_VAR_BCN_VALID,
 329         HW_VAR_FWLPS_RF_ON,
 330         HW_VAR_DUAL_TSF_RST,
 331         HW_VAR_SWITCH_EPHY_WoWLAN,
 332         HW_VAR_INT_MIGRATION,
 333         HW_VAR_INT_AC,
 334         HW_VAR_RF_TIMING,
 335
 336         HAL_DEF_WOWLAN,
 337         HW_VAR_MRC,
 338
 339         HW_VAR_MGT_FILTER,
 340         HW_VAR_CTRL_FILTER,
 341         HW_VAR_DATA_FILTER,
 342 };
 343
 344 enum _RT_MEDIA_STATUS {
 345         RT_MEDIA_DISCONNECT = 0,
 346         RT_MEDIA_CONNECT = 1
 347 };
 348
 349 enum rt_oem_id {
 350         RT_CID_DEFAULT = 0,
 351         RT_CID_8187_ALPHA0 = 1,
 352         RT_CID_8187_SERCOMM_PS = 2,
 353         RT_CID_8187_HW_LED = 3,
 354         RT_CID_8187_NETGEAR = 4,
 355         RT_CID_WHQL = 5,
 356         RT_CID_819x_CAMEO = 6,
 357         RT_CID_819x_RUNTOP = 7,
 358         RT_CID_819x_Senao = 8,
 359         RT_CID_TOSHIBA = 9,
 360         RT_CID_819x_Netcore = 10,
 361         RT_CID_Nettronix = 11,
 362         RT_CID_DLINK = 12,
 363         RT_CID_PRONET = 13,
 364         RT_CID_COREGA = 14,
 365         RT_CID_819x_ALPHA = 15,
 366         RT_CID_819x_Sitecom = 16,
 367         RT_CID_CCX = 17,
 368         RT_CID_819x_Lenovo = 18,
 369         RT_CID_819x_QMI = 19,
 370         RT_CID_819x_Edimax_Belkin = 20,
 371         RT_CID_819x_Sercomm_Belkin = 21,
 372         RT_CID_819x_CAMEO1 = 22,
 373         RT_CID_819x_MSI = 23,
 374         RT_CID_819x_Acer = 24,
 375         RT_CID_819x_HP = 27,
 376         RT_CID_819x_CLEVO = 28,
 377         RT_CID_819x_Arcadyan_Belkin = 29,
 378         RT_CID_819x_SAMSUNG = 30,
 379         RT_CID_819x_WNC_COREGA = 31,
 380         RT_CID_819x_Foxcoon = 32,
 381         RT_CID_819x_DELL = 33,
 382         RT_CID_819x_PRONETS = 34,
 383         RT_CID_819x_Edimax_ASUS = 35,
 384         RT_CID_NETGEAR = 36,
 385         RT_CID_PLANEX = 37,
 386         RT_CID_CC_C = 38,
 387 };
 388
 389 enum hw_descs {
 390         HW_DESC_OWN,
 391         HW_DESC_RXOWN,
 392         HW_DESC_TX_NEXTDESC_ADDR,
 393         HW_DESC_TXBUFF_ADDR,
 394         HW_DESC_RXBUFF_ADDR,
 395         HW_DESC_RXPKT_LEN,
 396         HW_DESC_RXERO,
 397 };
 398
 399 enum prime_sc {
 400         PRIME_CHNL_OFFSET_DONT_CARE = 0,
 401         PRIME_CHNL_OFFSET_LOWER = 1,
 402         PRIME_CHNL_OFFSET_UPPER = 2,
 403 };
 404
 405 enum rf_type {
 406         RF_1T1R = 0,
 407         RF_1T2R = 1,
 408         RF_2T2R = 2,
 409         RF_2T2R_GREEN = 3,
 410 };
 411
 412 enum ht_channel_width {
 413         HT_CHANNEL_WIDTH_20 = 0,
 414         HT_CHANNEL_WIDTH_20_40 = 1,
 415 };
 416
 417 /* Ref: 802.11i sepc D10.0 7.3.2.25.1
 418 Cipher Suites Encryption Algorithms */
 419 enum rt_enc_alg {
 420         NO_ENCRYPTION = 0,
 421         WEP40_ENCRYPTION = 1,
 422         TKIP_ENCRYPTION = 2,
 423         RSERVED_ENCRYPTION = 3,
 424         AESCCMP_ENCRYPTION = 4,
 425         WEP104_ENCRYPTION = 5,
 426         AESCMAC_ENCRYPTION = 6, /*IEEE802.11w */
 427 };
 428
 429 enum rtl_hal_state {
 430         _HAL_STATE_STOP = 0,
 431         _HAL_STATE_START = 1,
 432 };
 433
 434 enum rtl_desc92_rate {
 435         DESC92_RATE1M = 0x00,
 436         DESC92_RATE2M = 0x01,
 437         DESC92_RATE5_5M = 0x02,
 438         DESC92_RATE11M = 0x03,
 439
 440         DESC92_RATE6M = 0x04,
 441         DESC92_RATE9M = 0x05,
 442         DESC92_RATE12M = 0x06,
 443         DESC92_RATE18M = 0x07,
 444         DESC92_RATE24M = 0x08,
 445         DESC92_RATE36M = 0x09,
 446         DESC92_RATE48M = 0x0a,
 447         DESC92_RATE54M = 0x0b,
 448
 449         DESC92_RATEMCS0 = 0x0c,
 450         DESC92_RATEMCS1 = 0x0d,
 451         DESC92_RATEMCS2 = 0x0e,
 452         DESC92_RATEMCS3 = 0x0f,
 453         DESC92_RATEMCS4 = 0x10,
 454         DESC92_RATEMCS5 = 0x11,
 455         DESC92_RATEMCS6 = 0x12,
 456         DESC92_RATEMCS7 = 0x13,
 457         DESC92_RATEMCS8 = 0x14,
 458         DESC92_RATEMCS9 = 0x15,
 459         DESC92_RATEMCS10 = 0x16,
 460         DESC92_RATEMCS11 = 0x17,
 461         DESC92_RATEMCS12 = 0x18,
 462         DESC92_RATEMCS13 = 0x19,
 463         DESC92_RATEMCS14 = 0x1a,
 464         DESC92_RATEMCS15 = 0x1b,
 465         DESC92_RATEMCS15_SG = 0x1c,
 466         DESC92_RATEMCS32 = 0x20,
 467 };
 468
 469 enum rtl_var_map {
 470         /*reg map */
 471         SYS_ISO_CTRL = 0,
 472         SYS_FUNC_EN,
 473         SYS_CLK,
 474         MAC_RCR_AM,
 475         MAC_RCR_AB,
 476         MAC_RCR_ACRC32,
 477         MAC_RCR_ACF,
 478         MAC_RCR_AAP,
 479
 480         /*efuse map */
 481         EFUSE_TEST,
 482         EFUSE_CTRL,
 483         EFUSE_CLK,
 484         EFUSE_CLK_CTRL,
 485         EFUSE_PWC_EV12V,
 486         EFUSE_FEN_ELDR,
 487         EFUSE_LOADER_CLK_EN,
 488         EFUSE_ANA8M,
 489         EFUSE_HWSET_MAX_SIZE,
 490         EFUSE_MAX_SECTION_MAP,
 491         EFUSE_REAL_CONTENT_SIZE,
 492         EFUSE_OOB_PROTECT_BYTES_LEN,
 493         EFUSE_ACCESS,
 494
 495         /*CAM map */
 496         RWCAM,
 497         WCAMI,
 498         RCAMO,
 499         CAMDBG,
 500         SECR,
 501         SEC_CAM_NONE,
 502         SEC_CAM_WEP40,
 503         SEC_CAM_TKIP,
 504         SEC_CAM_AES,
 505         SEC_CAM_WEP104,
 506
 507         /*IMR map */
 508         RTL_IMR_BCNDMAINT6,     /*Beacon DMA Interrupt 6 */
 509         RTL_IMR_BCNDMAINT5,     /*Beacon DMA Interrupt 5 */
 510         RTL_IMR_BCNDMAINT4,     /*Beacon DMA Interrupt 4 */
 511         RTL_IMR_BCNDMAINT3,     /*Beacon DMA Interrupt 3 */
 512         RTL_IMR_BCNDMAINT2,     /*Beacon DMA Interrupt 2 */
 513         RTL_IMR_BCNDMAINT1,     /*Beacon DMA Interrupt 1 */
 514         RTL_IMR_BCNDOK8,        /*Beacon Queue DMA OK Interrup 8 */
 515         RTL_IMR_BCNDOK7,        /*Beacon Queue DMA OK Interrup 7 */
 516         RTL_IMR_BCNDOK6,        /*Beacon Queue DMA OK Interrup 6 */
 517         RTL_IMR_BCNDOK5,        /*Beacon Queue DMA OK Interrup 5 */
 518         RTL_IMR_BCNDOK4,        /*Beacon Queue DMA OK Interrup 4 */
 519         RTL_IMR_BCNDOK3,        /*Beacon Queue DMA OK Interrup 3 */
 520         RTL_IMR_BCNDOK2,        /*Beacon Queue DMA OK Interrup 2 */
 521         RTL_IMR_BCNDOK1,        /*Beacon Queue DMA OK Interrup 1 */
 522         RTL_IMR_TIMEOUT2,       /*Timeout interrupt 2 */
 523         RTL_IMR_TIMEOUT1,       /*Timeout interrupt 1 */
 524         RTL_IMR_TXFOVW,         /*Transmit FIFO Overflow */
 525         RTL_IMR_PSTIMEOUT,      /*Power save time out interrupt */
 526         RTL_IMR_BCNINT,         /*Beacon DMA Interrupt 0 */
 527         RTL_IMR_RXFOVW,         /*Receive FIFO Overflow */
 528         RTL_IMR_RDU,            /*Receive Descriptor Unavailable */
 529         RTL_IMR_ATIMEND,        /*For 92C,ATIM Window End Interrupt */
 530         RTL_IMR_BDOK,           /*Beacon Queue DMA OK Interrup */
 531         RTL_IMR_HIGHDOK,        /*High Queue DMA OK Interrupt */
 532         RTL_IMR_COMDOK,         /*Command Queue DMA OK Interrupt*/
 533         RTL_IMR_TBDOK,          /*Transmit Beacon OK interrup */
 534         RTL_IMR_MGNTDOK,        /*Management Queue DMA OK Interrupt */
 535         RTL_IMR_TBDER,          /*For 92C,Transmit Beacon Error Interrupt */
 536         RTL_IMR_BKDOK,          /*AC_BK DMA OK Interrupt */
 537         RTL_IMR_BEDOK,          /*AC_BE DMA OK Interrupt */
 538         RTL_IMR_VIDOK,          /*AC_VI DMA OK Interrupt */
 539         RTL_IMR_VODOK,          /*AC_VO DMA Interrupt */
 540         RTL_IMR_ROK,            /*Receive DMA OK Interrupt */
 541         RTL_IBSS_INT_MASKS,     /*(RTL_IMR_BCNINT | RTL_IMR_TBDOK |
 542                                  * RTL_IMR_TBDER) */
 543         RTL_IMR_C2HCMD,         /*fw interrupt*/
 544
 545         /*CCK Rates, TxHT = 0 */
 546         RTL_RC_CCK_RATE1M,
 547         RTL_RC_CCK_RATE2M,
 548         RTL_RC_CCK_RATE5_5M,
 549         RTL_RC_CCK_RATE11M,
 550
 551         /*OFDM Rates, TxHT = 0 */
 552         RTL_RC_OFDM_RATE6M,
 553         RTL_RC_OFDM_RATE9M,
 554         RTL_RC_OFDM_RATE12M,
 555         RTL_RC_OFDM_RATE18M,
 556         RTL_RC_OFDM_RATE24M,
 557         RTL_RC_OFDM_RATE36M,
 558         RTL_RC_OFDM_RATE48M,
 559         RTL_RC_OFDM_RATE54M,
 560
 561         RTL_RC_HT_RATEMCS7,
 562         RTL_RC_HT_RATEMCS15,
 563
 564         /*keep it last */
 565         RTL_VAR_MAP_MAX,
 566 };
 567
 568 /*Firmware PS mode for control LPS.*/
 569 enum _fw_ps_mode {
 570         FW_PS_ACTIVE_MODE = 0,
 571         FW_PS_MIN_MODE = 1,
 572         FW_PS_MAX_MODE = 2,
 573         FW_PS_DTIM_MODE = 3,
 574         FW_PS_VOIP_MODE = 4,
 575         FW_PS_UAPSD_WMM_MODE = 5,
 576         FW_PS_UAPSD_MODE = 6,
 577         FW_PS_IBSS_MODE = 7,
 578         FW_PS_WWLAN_MODE = 8,
 579         FW_PS_PM_Radio_Off = 9,
 580         FW_PS_PM_Card_Disable = 10,
 581 };
 582
 583 enum rt_psmode {
 584         EACTIVE,                /*Active/Continuous access. */
 585         EMAXPS,                 /*Max power save mode. */
 586         EFASTPS,                /*Fast power save mode. */
 587         EAUTOPS,                /*Auto power save mode. */
 588 };
 589
 590 /*LED related.*/
 591 enum led_ctl_mode {
 592         LED_CTL_POWER_ON = 1,
 593         LED_CTL_LINK = 2,
 594         LED_CTL_NO_LINK = 3,
 595         LED_CTL_TX = 4,
 596         LED_CTL_RX = 5,
 597         LED_CTL_SITE_SURVEY = 6,
 598         LED_CTL_POWER_OFF = 7,
 599         LED_CTL_START_TO_LINK = 8,
 600         LED_CTL_START_WPS = 9,
 601         LED_CTL_STOP_WPS = 10,
 602 };
 603
 604 enum rtl_led_pin {
 605         LED_PIN_GPIO0,
 606         LED_PIN_LED0,
 607         LED_PIN_LED1,
 608         LED_PIN_LED2
 609 };
 610
 611 /*QoS related.*/
 612 /*acm implementation method.*/
 613 enum acm_method {
 614         eAcmWay0_SwAndHw = 0,
 615         eAcmWay1_HW = 1,
 616         eAcmWay2_SW = 2,
 617 };
 618
 619 enum macphy_mode {
 620         SINGLEMAC_SINGLEPHY = 0,
 621         DUALMAC_DUALPHY,
 622         DUALMAC_SINGLEPHY,
 623 };
 624
 625 enum band_type {
 626         BAND_ON_2_4G = 0,
 627         BAND_ON_5G,
 628         BAND_ON_BOTH,
 629         BANDMAX
 630 };
 631
 632 /*aci/aifsn Field.
 633 Ref: WMM spec 2.2.2: WME Parameter Element, p.12.*/
 634 union aci_aifsn {
 635         u8 char_data;
 636
 637         struct {
 638                 u8 aifsn:4;
 639                 u8 acm:1;
 640                 u8 aci:2;
 641                 u8 reserved:1;
 642         } f;                    /* Field */
 643 };
 644
 645 /*mlme related.*/
 646 enum wireless_mode {
 647         WIRELESS_MODE_UNKNOWN = 0x00,
 648         WIRELESS_MODE_A = 0x01,
 649         WIRELESS_MODE_B = 0x02,
 650         WIRELESS_MODE_G = 0x04,
 651         WIRELESS_MODE_AUTO = 0x08,
 652         WIRELESS_MODE_N_24G = 0x10,
 653         WIRELESS_MODE_N_5G = 0x20
 654 };
 655
 656 #define IS_WIRELESS_MODE_A(wirelessmode)        \
 657         (wirelessmode == WIRELESS_MODE_A)
 658 #define IS_WIRELESS_MODE_B(wirelessmode)        \
 659         (wirelessmode == WIRELESS_MODE_B)
 660 #define IS_WIRELESS_MODE_G(wirelessmode)        \
 661         (wirelessmode == WIRELESS_MODE_G)
 662 #define IS_WIRELESS_MODE_N_24G(wirelessmode)    \
 663         (wirelessmode == WIRELESS_MODE_N_24G)
 664 #define IS_WIRELESS_MODE_N_5G(wirelessmode)     \
 665         (wirelessmode == WIRELESS_MODE_N_5G)
 666
 667 enum ratr_table_mode {
 668         RATR_INX_WIRELESS_NGB = 0,
 669         RATR_INX_WIRELESS_NG = 1,
 670         RATR_INX_WIRELESS_NB = 2,
 671         RATR_INX_WIRELESS_N = 3,
 672         RATR_INX_WIRELESS_GB = 4,
 673         RATR_INX_WIRELESS_G = 5,
 674         RATR_INX_WIRELESS_B = 6,
 675         RATR_INX_WIRELESS_MC = 7,
 676         RATR_INX_WIRELESS_A = 8,
 677 };
 678
 679 enum rtl_link_state {
 680         MAC80211_NOLINK = 0,
 681         MAC80211_LINKING = 1,
 682         MAC80211_LINKED = 2,
 683         MAC80211_LINKED_SCANNING = 3,
 684 };
 685
 686 enum act_category {
 687         ACT_CAT_QOS = 1,
 688         ACT_CAT_DLS = 2,
 689         ACT_CAT_BA = 3,
 690         ACT_CAT_HT = 7,
 691         ACT_CAT_WMM = 17,
 692 };
 693
 694 enum ba_action {
 695         ACT_ADDBAREQ = 0,
 696         ACT_ADDBARSP = 1,
 697         ACT_DELBA = 2,
 698 };
 699
 700 enum rt_polarity_ctl {
 701         RT_POLARITY_LOW_ACT = 0,
 702         RT_POLARITY_HIGH_ACT = 1,
 703 };
 704
 705 struct octet_string {
 706         u8 *octet;
 707         u16 length;
 708 };
 709
 710 struct rtl_hdr_3addr {
 711         __le16 frame_ctl;
 712         __le16 duration_id;
 713         u8 addr1[ETH_ALEN];
 714         u8 addr2[ETH_ALEN];
 715         u8 addr3[ETH_ALEN];
 716         __le16 seq_ctl;
 717         u8 payload[0];
 718 } __packed;
 719
 720 struct rtl_info_element {
 721         u8 id;
 722         u8 len;
 723         u8 data[0];
 724 } __packed;
 725
 726 struct rtl_probe_rsp {
 727         struct rtl_hdr_3addr header;
 728         u32 time_stamp[2];
 729         __le16 beacon_interval;
 730         __le16 capability;
 731         /*SSID, supported rates, FH params, DS params,
 732            CF params, IBSS params, TIM (if beacon), RSN */
 733         struct rtl_info_element info_element[0];
 734 } __packed;
 735
 736 /*LED related.*/
 737 /*ledpin Identify how to implement this SW led.*/
 738 struct rtl_led {
 739         void *hw;
 740         enum rtl_led_pin ledpin;
 741         bool ledon;
 742 };
 743
 744 struct rtl_led_ctl {
 745         bool led_opendrain;
 746         struct rtl_led sw_led0;
 747         struct rtl_led sw_led1;
 748 };
 749
 750 struct rtl_qos_parameters {
 751         __le16 cw_min;
 752         __le16 cw_max;
 753         u8 aifs;
 754         u8 flag;
 755         __le16 tx_op;
 756 } __packed;
 757
 758 struct rt_smooth_data {
 759         u32 elements[100];      /*array to store values */
 760         u32 index;              /*index to current array to store */
 761         u32 total_num;          /*num of valid elements */
 762         u32 total_val;          /*sum of valid elements */
 763 };
 764
 765 struct false_alarm_statistics {
 766         u32 cnt_parity_fail;
 767         u32 cnt_rate_illegal;
 768         u32 cnt_crc8_fail;
 769         u32 cnt_mcs_fail;
 770         u32 cnt_fast_fsync_fail;
 771         u32 cnt_sb_search_fail;
 772         u32 cnt_ofdm_fail;
 773         u32 cnt_cck_fail;
 774         u32 cnt_all;
 775         u32 cnt_ofdm_cca;
 776         u32 cnt_cck_cca;
 777         u32 cnt_cca_all;
 778         u32 cnt_bw_usc;
 779         u32 cnt_bw_lsc;
 780 };
 781
 782 struct init_gain {
 783         u8 xaagccore1;
 784         u8 xbagccore1;
 785         u8 xcagccore1;
 786         u8 xdagccore1;
 787         u8 cca;
 788
 789 };
 790
 791 struct wireless_stats {
 792         unsigned long txbytesunicast;
 793         unsigned long txbytesmulticast;
 794         unsigned long txbytesbroadcast;
 795         unsigned long rxbytesunicast;
 796
 797         long rx_snr_db[4];
 798         /*Correct smoothed ss in Dbm, only used
 799            in driver to report real power now. */
 800         long recv_signal_power;
 801         long signal_quality;
 802         long last_sigstrength_inpercent;
 803
 804         u32 rssi_calculate_cnt;
 805
 806         /*Transformed, in dbm. Beautified signal
 807            strength for UI, not correct. */
 808         long signal_strength;
 809
 810         u8 rx_rssi_percentage[4];
 811         u8 rx_evm_percentage[2];
 812
 813         struct rt_smooth_data ui_rssi;
 814         struct rt_smooth_data ui_link_quality;
 815 };
 816
 817 struct rate_adaptive {
 818         u8 rate_adaptive_disabled;
 819         u8 ratr_state;
 820         u16 reserve;
 821
 822         u32 high_rssi_thresh_for_ra;
 823         u32 high2low_rssi_thresh_for_ra;
 824         u8 low2high_rssi_thresh_for_ra40m;
 825         u32 low_rssi_thresh_for_ra40M;
 826         u8 low2high_rssi_thresh_for_ra20m;
 827         u32 low_rssi_thresh_for_ra20M;
 828         u32 upper_rssi_threshold_ratr;
 829         u32 middleupper_rssi_threshold_ratr;
 830         u32 middle_rssi_threshold_ratr;
 831         u32 middlelow_rssi_threshold_ratr;
 832         u32 low_rssi_threshold_ratr;
 833         u32 ultralow_rssi_threshold_ratr;
 834         u32 low_rssi_threshold_ratr_40m;
 835         u32 low_rssi_threshold_ratr_20m;
 836         u8 ping_rssi_enable;
 837         u32 ping_rssi_ratr;
 838         u32 ping_rssi_thresh_for_ra;
 839         u32 last_ratr;
 840         u8 pre_ratr_state;
 841 };
 842
 843 struct regd_pair_mapping {
 844         u16 reg_dmnenum;
 845         u16 reg_5ghz_ctl;
 846         u16 reg_2ghz_ctl;
 847 };
 848
 849 struct rtl_regulatory {
 850         char alpha2[2];
 851         u16 country_code;
 852         u16 max_power_level;
 853         u32 tp_scale;
 854         u16 current_rd;
 855         u16 current_rd_ext;
 856         int16_t power_limit;
 857         struct regd_pair_mapping *regpair;
 858 };
 859
 860 struct rtl_rfkill {
 861         bool rfkill_state;      /*0 is off, 1 is on */
 862 };
 863
 864 /*for P2P PS**/
 865 #define P2P_MAX_NOA_NUM         2
 866
 867 enum p2p_role {
 868         P2P_ROLE_DISABLE = 0,
 869         P2P_ROLE_DEVICE = 1,
 870         P2P_ROLE_CLIENT = 2,
 871         P2P_ROLE_GO = 3
 872 };
 873
 874 enum p2p_ps_state {
 875         P2P_PS_DISABLE = 0,
 876         P2P_PS_ENABLE = 1,
 877         P2P_PS_SCAN = 2,
 878         P2P_PS_SCAN_DONE = 3,
 879         P2P_PS_ALLSTASLEEP = 4, /* for P2P GO */
 880 };
 881
 882 enum p2p_ps_mode {
 883         P2P_PS_NONE = 0,
 884         P2P_PS_CTWINDOW = 1,
 885         P2P_PS_NOA       = 2,
 886         P2P_PS_MIX = 3, /* CTWindow and NoA */
 887 };
 888
 889 struct rtl_p2p_ps_info {
 890         enum p2p_ps_mode p2p_ps_mode; /* indicate p2p ps mode */
 891         enum p2p_ps_state p2p_ps_state; /*  indicate p2p ps state */
 892         u8 noa_index; /*  Identifies instance of Notice of Absence timing. */
 893         /*  Client traffic window. A period of time in TU after TBTT. */
 894         u8 ctwindow;
 895         u8 opp_ps; /*  opportunistic power save. */
 896         u8 noa_num; /*  number of NoA descriptor in P2P IE. */
 897         /*  Count for owner, Type of client. */
 898         u8 noa_count_type[P2P_MAX_NOA_NUM];
 899         /*  Max duration for owner, preferred or min acceptable duration
 900          * for client.
 901          */
 902         u32 noa_duration[P2P_MAX_NOA_NUM];
 903         /*  Length of interval for owner, preferred or max acceptable intervali
 904          * of client.
 905          */
 906         u32 noa_interval[P2P_MAX_NOA_NUM];
 907         /*  schedule in terms of the lower 4 bytes of the TSF timer. */
 908         u32 noa_start_time[P2P_MAX_NOA_NUM];
 909 };
 910
 911 struct p2p_ps_offload_t {
 912         u8 offload_en:1;
 913         u8 role:1; /* 1: Owner, 0: Client */
 914         u8 ctwindow_en:1;
 915         u8 noa0_en:1;
 916         u8 noa1_en:1;
 917         u8 allstasleep:1;
 918         u8 discovery:1;
 919         u8 reserved:1;
 920 };
 921
 922 #define IQK_MATRIX_REG_NUM      8
 923 #define IQK_MATRIX_SETTINGS_NUM (1 + 24 + 21)
 924
 925 struct iqk_matrix_regs {
 926         bool iqk_done;
 927         long value[1][IQK_MATRIX_REG_NUM];
 928 };
 929
 930 struct phy_parameters {
 931         u16 length;
 932         u32 *pdata;
 933 };
 934
 935 enum hw_param_tab_index {
 936         PHY_REG_2T,
 937         PHY_REG_1T,
 938         PHY_REG_PG,
 939         RADIOA_2T,
 940         RADIOB_2T,
 941         RADIOA_1T,
 942         RADIOB_1T,
 943         MAC_REG,
 944         AGCTAB_2T,
 945         AGCTAB_1T,
 946         MAX_TAB
 947 };
 948
 949 struct rtl_phy {
 950         struct bb_reg_def phyreg_def[4];        /*Radio A/B/C/D */
 951         struct init_gain initgain_backup;
 952         enum io_type current_io_type;
 953
 954         u8 rf_mode;
 955         u8 rf_type;
 956         u8 current_chan_bw;
 957         u8 set_bwmode_inprogress;
 958         u8 sw_chnl_inprogress;
 959         u8 sw_chnl_stage;
 960         u8 sw_chnl_step;
 961         u8 current_channel;
 962         u8 h2c_box_num;
 963         u8 set_io_inprogress;
 964         u8 lck_inprogress;
 965
 966         /* record for power tracking */
 967         s32 reg_e94;
 968         s32 reg_e9c;
 969         s32 reg_ea4;
 970         s32 reg_eac;
 971         s32 reg_eb4;
 972         s32 reg_ebc;
 973         s32 reg_ec4;
 974         s32 reg_ecc;
 975         u8 rfpienable;
 976         u8 reserve_0;
 977         u16 reserve_1;
 978         u32 reg_c04, reg_c08, reg_874;
 979         u32 adda_backup[16];
 980         u32 iqk_mac_backup[IQK_MAC_REG_NUM];
 981         u32 iqk_bb_backup[10];
 982         bool iqk_initialized;
 983
 984         /* Dual mac */
 985         bool need_iqk;
 986         struct iqk_matrix_regs iqk_matrix[IQK_MATRIX_SETTINGS_NUM];
 987
 988         bool rfpi_enable;
 989
 990         u8 pwrgroup_cnt;
 991         u8 cck_high_power;
 992         /* MAX_PG_GROUP groups of pwr diff by rates */
 993         u32 mcs_offset[MAX_PG_GROUP][16];
 994         u8 default_initialgain[4];
 995
 996         /* the current Tx power level */
 997         u8 cur_cck_txpwridx;
 998         u8 cur_ofdm24g_txpwridx;
 999         u8 cur_bw20_txpwridx;
1000         u8 cur_bw40_txpwridx;
1001
1002         u32 rfreg_chnlval[2];
1003         bool apk_done;
1004         u32 reg_rf3c[2];        /* pathA / pathB  */
1005
1006         /* bfsync */
1007         u8 framesync;
1008         u32 framesync_c34;
1009
1010         u8 num_total_rfpath;
1011         struct phy_parameters hwparam_tables[MAX_TAB];
1012         u16 rf_pathmap;
1013
1014         enum rt_polarity_ctl polarity_ctl;
1015 };
1016
1017 #define MAX_TID_COUNT                           9
1018 #define RTL_AGG_STOP                            0
1019 #define RTL_AGG_PROGRESS                        1
1020 #define RTL_AGG_START                           2
1021 #define RTL_AGG_OPERATIONAL                     3
1022 #define RTL_AGG_OFF                             0
1023 #define RTL_AGG_ON                              1
1024 #define RTL_RX_AGG_START                        1
1025 #define RTL_RX_AGG_STOP                         0
1026 #define RTL_AGG_EMPTYING_HW_QUEUE_ADDBA         2
1027 #define RTL_AGG_EMPTYING_HW_QUEUE_DELBA         3
1028
1029 struct rtl_ht_agg {
1030         u16 txq_id;
1031         u16 wait_for_ba;
1032         u16 start_idx;
1033         u64 bitmap;
1034         u32 rate_n_flags;
1035         u8 agg_state;
1036         u8 rx_agg_state;
1037 };
1038
1039 struct rssi_sta {
1040         long undec_sm_pwdb;
1041 };
1042
1043 struct rtl_tid_data {
1044         u16 seq_number;
1045         struct rtl_ht_agg agg;
1046 };
1047
1048 struct rtl_sta_info {
1049         struct list_head list;
1050         u8 ratr_index;
1051         u8 wireless_mode;
1052         u8 mimo_ps;
1053         u8 mac_addr[ETH_ALEN];
1054         struct rtl_tid_data tids[MAX_TID_COUNT];
1055
1056         /* just used for ap adhoc or mesh*/
1057         struct rssi_sta rssi_stat;
1058 } __packed;
1059
1060 struct rtl_priv;
1061 struct rtl_io {
1062         struct device *dev;
1063         struct mutex bb_mutex;
1064
1065         /*PCI MEM map */
1066         unsigned long pci_mem_end;      /*shared mem end        */
1067         unsigned long pci_mem_start;    /*shared mem start */
1068
1069         /*PCI IO map */
1070         unsigned long pci_base_addr;    /*device I/O address */
1071
1072         void (*write8_async) (struct rtl_priv *rtlpriv, u32 addr, u8 val);
1073         void (*write16_async) (struct rtl_priv *rtlpriv, u32 addr, u16 val);
1074         void (*write32_async) (struct rtl_priv *rtlpriv, u32 addr, u32 val);
1075         void (*writeN_sync) (struct rtl_priv *rtlpriv, u32 addr, void *buf,
1076                              u16 len);
1077
1078         u8(*read8_sync) (struct rtl_priv *rtlpriv, u32 addr);
1079         u16(*read16_sync) (struct rtl_priv *rtlpriv, u32 addr);
1080         u32(*read32_sync) (struct rtl_priv *rtlpriv, u32 addr);
1081
1082 };
1083
1084 struct rtl_mac {
1085         u8 mac_addr[ETH_ALEN];
1086         u8 mac80211_registered;
1087         u8 beacon_enabled;
1088
1089         u32 tx_ss_num;
1090         u32 rx_ss_num;
1091
1092         struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];
1093         struct ieee80211_hw *hw;
1094         struct ieee80211_vif *vif;
1095         enum nl80211_iftype opmode;
1096
1097         /*Probe Beacon management */
1098         struct rtl_tid_data tids[MAX_TID_COUNT];
1099         enum rtl_link_state link_state;
1100
1101         int n_channels;
1102         int n_bitrates;
1103
1104         bool offchan_delay;
1105         u8 p2p; /*using p2p role*/
1106         bool p2p_in_use;
1107
1108         /*filters */
1109         u32 rx_conf;
1110         u16 rx_mgt_filter;
1111         u16 rx_ctrl_filter;
1112         u16 rx_data_filter;
1113
1114         bool act_scanning;
1115         u8 cnt_after_linked;
1116         bool skip_scan;
1117
1118         /* early mode */
1119         /* skb wait queue */
1120         struct sk_buff_head skb_waitq[MAX_TID_COUNT];
1121
1122         /*RDG*/
1123         bool rdg_en;
1124
1125         /*AP*/
1126         u8 bssid[6];
1127         u32 vendor;
1128         u8 mcs[16];     /* 16 bytes mcs for HT rates. */
1129         u32 basic_rates; /* b/g rates */
1130         u8 ht_enable;
1131         u8 sgi_40;
1132         u8 sgi_20;
1133         u8 bw_40;
1134         u8 mode;                /* wireless mode */
1135         u8 slot_time;
1136         u8 short_preamble;
1137         u8 use_cts_protect;
1138         u8 cur_40_prime_sc;
1139         u8 cur_40_prime_sc_bk;
1140         u64 tsf;
1141         u8 retry_short;
1142         u8 retry_long;
1143         u16 assoc_id;
1144         bool hiddenssid;
1145
1146         /*IBSS*/
1147         int beacon_interval;
1148
1149         /*AMPDU*/
1150         u8 min_space_cfg;       /*For Min spacing configurations */
1151         u8 max_mss_density;
1152         u8 current_ampdu_factor;
1153         u8 current_ampdu_density;
1154
1155         /*QOS & EDCA */
1156         struct ieee80211_tx_queue_params edca_param[RTL_MAC80211_NUM_QUEUE];
1157         struct rtl_qos_parameters ac[AC_MAX];
1158
1159         /* counters */
1160         u64 last_txok_cnt;
1161         u64 last_rxok_cnt;
1162         u32 last_bt_edca_ul;
1163         u32 last_bt_edca_dl;
1164 };
1165
1166 struct btdm_8723 {
1167         bool all_off;
1168         bool agc_table_en;
1169         bool adc_back_off_on;
1170         bool b2_ant_hid_en;
1171         bool low_penalty_rate_adaptive;
1172         bool rf_rx_lpf_shrink;
1173         bool reject_aggre_pkt;
1174         bool tra_tdma_on;
1175         u8 tra_tdma_nav;
1176         u8 tra_tdma_ant;
1177         bool tdma_on;
1178         u8 tdma_ant;
1179         u8 tdma_nav;
1180         u8 tdma_dac_swing;
1181         u8 fw_dac_swing_lvl;
1182         bool ps_tdma_on;
1183         u8 ps_tdma_byte[5];
1184         bool pta_on;
1185         u32 val_0x6c0;
1186         u32 val_0x6c8;
1187         u32 val_0x6cc;
1188         bool sw_dac_swing_on;
1189         u32 sw_dac_swing_lvl;
1190         u32 wlan_act_hi;
1191         u32 wlan_act_lo;
1192         u32 bt_retry_index;
1193         bool dec_bt_pwr;
1194         bool ignore_wlan_act;
1195 };
1196
1197 struct bt_coexist_8723 {
1198         u32 high_priority_tx;
1199         u32 high_priority_rx;
1200         u32 low_priority_tx;
1201         u32 low_priority_rx;
1202         u8 c2h_bt_info;
1203         bool c2h_bt_info_req_sent;
1204         bool c2h_bt_inquiry_page;
1205         u32 bt_inq_page_start_time;
1206         u8 bt_retry_cnt;
1207         u8 c2h_bt_info_original;
1208         u8 bt_inquiry_page_cnt;
1209         struct btdm_8723 btdm;
1210 };
1211
1212 struct rtl_hal {
1213         struct ieee80211_hw *hw;
1214         bool driver_is_goingto_unload;
1215         bool up_first_time;
1216         bool first_init;
1217         bool being_init_adapter;
1218         bool bbrf_ready;
1219         bool mac_func_enable;
1220         struct bt_coexist_8723 hal_coex_8723;
1221
1222         enum intf_type interface;
1223         u16 hw_type;            /*92c or 92d or 92s and so on */
1224         u8 ic_class;
1225         u8 oem_id;
1226         u32 version;            /*version of chip */
1227         u8 state;               /*stop 0, start 1 */
1228         u8 board_type;
1229
1230         /*firmware */
1231         u32 fwsize;
1232         u8 *pfirmware;
1233         u16 fw_version;
1234         u16 fw_subversion;
1235         bool h2c_setinprogress;
1236         u8 last_hmeboxnum;
1237         bool fw_ready;
1238         /*Reserve page start offset except beacon in TxQ. */
1239         u8 fw_rsvdpage_startoffset;
1240         u8 h2c_txcmd_seq;
1241
1242         /* FW Cmd IO related */
1243         u16 fwcmd_iomap;
1244         u32 fwcmd_ioparam;
1245         bool set_fwcmd_inprogress;
1246         u8 current_fwcmd_io;
1247
1248         struct p2p_ps_offload_t p2p_ps_offload;
1249         bool fw_clk_change_in_progress;
1250         bool allow_sw_to_change_hwclc;
1251         u8 fw_ps_state;
1252         /**/
1253         bool driver_going2unload;
1254
1255         /*AMPDU init min space*/
1256         u8 minspace_cfg;        /*For Min spacing configurations */
1257
1258         /* Dual mac */
1259         enum macphy_mode macphymode;
1260         enum band_type current_bandtype;        /* 0:2.4G, 1:5G */
1261         enum band_type current_bandtypebackup;
1262         enum band_type bandset;
1263         /* dual MAC 0--Mac0 1--Mac1 */
1264         u32 interfaceindex;
1265         /* just for DualMac S3S4 */
1266         u8 macphyctl_reg;
1267         bool earlymode_enable;
1268         u8 max_earlymode_num;
1269         /* Dual mac*/
1270         bool during_mac0init_radiob;
1271         bool during_mac1init_radioa;
1272         bool reloadtxpowerindex;
1273         /* True if IMR or IQK  have done
1274         for 2.4G in scan progress */
1275         bool load_imrandiqk_setting_for2g;
1276
1277         bool disable_amsdu_8k;
1278         bool master_of_dmsp;
1279         bool slave_of_dmsp;
1280 };
1281
1282 struct rtl_security {
1283         /*default 0 */
1284         bool use_sw_sec;
1285
1286         bool being_setkey;
1287         bool use_defaultkey;
1288         /*Encryption Algorithm for Unicast Packet */
1289         enum rt_enc_alg pairwise_enc_algorithm;
1290         /*Encryption Algorithm for Brocast/Multicast */
1291         enum rt_enc_alg group_enc_algorithm;
1292         /*Cam Entry Bitmap */
1293         u32 hwsec_cam_bitmap;
1294         u8 hwsec_cam_sta_addr[TOTAL_CAM_ENTRY][ETH_ALEN];
1295         /*local Key buffer, indx 0 is for
1296            pairwise key 1-4 is for agoup key. */
1297         u8 key_buf[KEY_BUF_SIZE][MAX_KEY_LEN];
1298         u8 key_len[KEY_BUF_SIZE];
1299
1300         /*The pointer of Pairwise Key,
1301            it always points to KeyBuf[4] */
1302         u8 *pairwise_key;
1303 };
1304
1305 #define ASSOCIATE_ENTRY_NUM     33
1306
1307 struct fast_ant_training {
1308         u8      bssid[6];
1309         u8      antsel_rx_keep_0;
1310         u8      antsel_rx_keep_1;
1311         u8      antsel_rx_keep_2;
1312         u32     ant_sum[7];
1313         u32     ant_cnt[7];
1314         u32     ant_ave[7];
1315         u8      fat_state;
1316         u32     train_idx;
1317         u8      antsel_a[ASSOCIATE_ENTRY_NUM];
1318         u8      antsel_b[ASSOCIATE_ENTRY_NUM];
1319         u8      antsel_c[ASSOCIATE_ENTRY_NUM];
1320         u32     main_ant_sum[ASSOCIATE_ENTRY_NUM];
1321         u32     aux_ant_sum[ASSOCIATE_ENTRY_NUM];
1322         u32     main_ant_cnt[ASSOCIATE_ENTRY_NUM];
1323         u32     aux_ant_cnt[ASSOCIATE_ENTRY_NUM];
1324         u8      rx_idle_ant;
1325         bool    becomelinked;
1326 };
1327
1328 struct rtl_dm {
1329         /*PHY status for Dynamic Management */
1330         long entry_min_undec_sm_pwdb;
1331         long undec_sm_pwdb;     /*out dm */
1332         long entry_max_undec_sm_pwdb;
1333         bool dm_initialgain_enable;
1334         bool dynamic_txpower_enable;
1335         bool current_turbo_edca;
1336         bool is_any_nonbepkts;  /*out dm */
1337         bool is_cur_rdlstate;
1338         bool txpower_trackinginit;
1339         bool disable_framebursting;
1340         bool cck_inch14;
1341         bool txpower_tracking;
1342         bool useramask;
1343         bool rfpath_rxenable[4];
1344         bool inform_fw_driverctrldm;
1345         bool current_mrc_switch;
1346         u8 txpowercount;
1347
1348         u8 thermalvalue_rxgain;
1349         u8 thermalvalue_iqk;
1350         u8 thermalvalue_lck;
1351         u8 thermalvalue;
1352         u8 last_dtp_lvl;
1353         u8 thermalvalue_avg[AVG_THERMAL_NUM];
1354         u8 thermalvalue_avg_index;
1355         bool done_txpower;
1356         u8 dynamic_txhighpower_lvl;     /*Tx high power level */
1357         u8 dm_flag;             /*Indicate each dynamic mechanism's status. */
1358         u8 dm_type;
1359         u8 txpower_track_control;
1360         bool interrupt_migration;
1361         bool disable_tx_int;
1362         char ofdm_index[2];
1363         char cck_index;
1364         char delta_power_index;
1365         char delta_power_index_last;
1366         char power_index_offset;
1367
1368         /*88e tx power tracking*/
1369         u8      swing_idx_ofdm[2];
1370         u8      swing_idx_ofdm_cur;
1371         u8      swing_idx_ofdm_base;
1372         bool    swing_flag_ofdm;
1373         u8      swing_idx_cck;
1374         u8      swing_idx_cck_cur;
1375         u8      swing_idx_cck_base;
1376         bool    swing_flag_cck;
1377
1378         /* DMSP */
1379         bool supp_phymode_switch;
1380
1381         struct fast_ant_training fat_table;
1382 };
1383
1384 #define EFUSE_MAX_LOGICAL_SIZE                  256
1385
1386 struct rtl_efuse {
1387         bool autoLoad_ok;
1388         bool bootfromefuse;
1389         u16 max_physical_size;
1390
1391         u8 efuse_map[2][EFUSE_MAX_LOGICAL_SIZE];
1392         u16 efuse_usedbytes;
1393         u8 efuse_usedpercentage;
1394 #ifdef EFUSE_REPG_WORKAROUND
1395         bool efuse_re_pg_sec1flag;
1396         u8 efuse_re_pg_data[8];
1397 #endif
1398
1399         u8 autoload_failflag;
1400         u8 autoload_status;
1401
1402         short epromtype;
1403         u16 eeprom_vid;
1404         u16 eeprom_did;
1405         u16 eeprom_svid;
1406         u16 eeprom_smid;
1407         u8 eeprom_oemid;
1408         u16 eeprom_channelplan;
1409         u8 eeprom_version;
1410         u8 board_type;
1411         u8 external_pa;
1412
1413         u8 dev_addr[6];
1414         u8 wowlan_enable;
1415         u8 antenna_div_cfg;
1416         u8 antenna_div_type;
1417
1418         bool txpwr_fromeprom;
1419         u8 eeprom_crystalcap;
1420         u8 eeprom_tssi[2];
1421         u8 eeprom_tssi_5g[3][2]; /* for 5GL/5GM/5GH band. */
1422         u8 eeprom_pwrlimit_ht20[CHANNEL_GROUP_MAX];
1423         u8 eeprom_pwrlimit_ht40[CHANNEL_GROUP_MAX];
1424         u8 eeprom_chnlarea_txpwr_cck[2][CHANNEL_GROUP_MAX_2G];
1425         u8 eeprom_chnlarea_txpwr_ht40_1s[2][CHANNEL_GROUP_MAX];
1426         u8 eprom_chnl_txpwr_ht40_2sdf[2][CHANNEL_GROUP_MAX];
1427         u8 txpwrlevel_cck[2][CHANNEL_MAX_NUMBER_2G];
1428         u8 txpwrlevel_ht40_1s[2][CHANNEL_MAX_NUMBER];   /*For HT 40MHZ pwr */
1429         u8 txpwrlevel_ht40_2s[2][CHANNEL_MAX_NUMBER];   /*For HT 40MHZ pwr */
1430
1431         u8 internal_pa_5g[2];   /* pathA / pathB */
1432         u8 eeprom_c9;
1433         u8 eeprom_cc;
1434
1435         /*For power group */
1436         u8 eeprom_pwrgroup[2][3];
1437         u8 pwrgroup_ht20[2][CHANNEL_MAX_NUMBER];
1438         u8 pwrgroup_ht40[2][CHANNEL_MAX_NUMBER];
1439
1440         char txpwr_ht20diff[2][CHANNEL_MAX_NUMBER]; /*HT 20<->40 Pwr diff */
1441         /*For HT<->legacy pwr diff*/
1442         u8 txpwr_legacyhtdiff[2][CHANNEL_MAX_NUMBER];
1443         u8 txpwr_safetyflag;                    /* Band edge enable flag */
1444         u16 eeprom_txpowerdiff;
1445         u8 legacy_httxpowerdiff;        /* Legacy to HT rate power diff */
1446         u8 antenna_txpwdiff[3];
1447
1448         u8 eeprom_regulatory;
1449         u8 eeprom_thermalmeter;
1450         u8 thermalmeter[2]; /*ThermalMeter, index 0 for RFIC0, 1 for RFIC1 */
1451         u16 tssi_13dbm;
1452         u8 crystalcap;          /* CrystalCap. */
1453         u8 delta_iqk;
1454         u8 delta_lck;
1455
1456         u8 legacy_ht_txpowerdiff;       /*Legacy to HT rate power diff */
1457         bool apk_thermalmeterignore;
1458
1459         bool b1x1_recvcombine;
1460         bool b1ss_support;
1461
1462         /*channel plan */
1463         u8 channel_plan;
1464 };
1465
1466 struct rtl_ps_ctl {
1467         bool pwrdomain_protect;
1468         bool in_powersavemode;
1469         bool rfchange_inprogress;
1470         bool swrf_processing;
1471         bool hwradiooff;
1472         /*
1473          * just for PCIE ASPM
1474          * If it supports ASPM, Offset[560h] = 0x40,
1475          * otherwise Offset[560h] = 0x00.
1476          * */
1477         bool support_aspm;
1478         bool support_backdoor;
1479
1480         /*for LPS */
1481         enum rt_psmode dot11_psmode;    /*Power save mode configured. */
1482         bool swctrl_lps;
1483         bool leisure_ps;
1484         bool fwctrl_lps;
1485         u8 fwctrl_psmode;
1486         /*For Fw control LPS mode */
1487         u8 reg_fwctrl_lps;
1488         /*Record Fw PS mode status. */
1489         bool fw_current_inpsmode;
1490         u8 reg_max_lps_awakeintvl;
1491         bool report_linked;
1492         bool low_power_enable;/*for 32k*/
1493
1494         /*for IPS */
1495         bool inactiveps;
1496
1497         u32 rfoff_reason;
1498
1499         /*RF OFF Level */
1500         u32 cur_ps_level;
1501         u32 reg_rfps_level;
1502
1503         /*just for PCIE ASPM */
1504         u8 const_amdpci_aspm;
1505         bool pwrdown_mode;
1506
1507         enum rf_pwrstate inactive_pwrstate;
1508         enum rf_pwrstate rfpwr_state;   /*cur power state */
1509
1510         /* for SW LPS*/
1511         bool sw_ps_enabled;
1512         bool state;
1513         bool state_inap;
1514         bool multi_buffered;
1515         u16 nullfunc_seq;
1516         unsigned int dtim_counter;
1517         unsigned int sleep_ms;
1518         unsigned long last_sleep_jiffies;
1519         unsigned long last_awake_jiffies;
1520         unsigned long last_delaylps_stamp_jiffies;
1521         unsigned long last_dtim;
1522         unsigned long last_beacon;
1523         unsigned long last_action;
1524         unsigned long last_slept;
1525
1526         /*For P2P PS */
1527         struct rtl_p2p_ps_info p2p_ps_info;
1528         u8 pwr_mode;
1529         u8 smart_ps;
1530 };
1531
1532 struct rtl_stats {
1533         u8 psaddr[ETH_ALEN];
1534         u32 mac_time[2];
1535         s8 rssi;
1536         u8 signal;
1537         u8 noise;
1538         u8 rate;                /* hw desc rate */
1539         u8 received_channel;
1540         u8 control;
1541         u8 mask;
1542         u8 freq;
1543         u16 len;
1544         u64 tsf;
1545         u32 beacon_time;
1546         u8 nic_type;
1547         u16 length;
1548         u8 signalquality;       /*in 0-100 index. */
1549         /*
1550          * Real power in dBm for this packet,
1551          * no beautification and aggregation.
1552          * */
1553         s32 recvsignalpower;
1554         s8 rxpower;             /*in dBm Translate from PWdB */
1555         u8 signalstrength;      /*in 0-100 index. */
1556         u16 hwerror:1;
1557         u16 crc:1;
1558         u16 icv:1;
1559         u16 shortpreamble:1;
1560         u16 antenna:1;
1561         u16 decrypted:1;
1562         u16 wakeup:1;
1563         u32 timestamp_low;
1564         u32 timestamp_high;
1565
1566         u8 rx_drvinfo_size;
1567         u8 rx_bufshift;
1568         bool isampdu;
1569         bool isfirst_ampdu;
1570         bool rx_is40Mhzpacket;
1571         u32 rx_pwdb_all;
1572         u8 rx_mimo_signalstrength[4];   /*in 0~100 index */
1573         s8 rx_mimo_sig_qual[2];
1574         bool packet_matchbssid;
1575         bool is_cck;
1576         bool is_ht;
1577         bool packet_toself;
1578         bool packet_beacon;     /*for rssi */
1579         char cck_adc_pwdb[4];   /*for rx path selection */
1580
1581         u8 packet_report_type;
1582
1583         u32 macid;
1584         u8 wake_match;
1585         u32 bt_rx_rssi_percentage;
1586         u32 macid_valid_entry[2];
1587 };
1588
1589
1590 struct rt_link_detect {
1591         /* count for roaming */
1592         u32 bcn_rx_inperiod;
1593         u32 roam_times;
1594
1595         u32 num_tx_in4period[4];
1596         u32 num_rx_in4period[4];
1597
1598         u32 num_tx_inperiod;
1599         u32 num_rx_inperiod;
1600
1601         bool busytraffic;
1602         bool tx_busy_traffic;
1603         bool rx_busy_traffic;
1604         bool higher_busytraffic;
1605         bool higher_busyrxtraffic;
1606
1607         u32 tidtx_in4period[MAX_TID_COUNT][4];
1608         u32 tidtx_inperiod[MAX_TID_COUNT];
1609         bool higher_busytxtraffic[MAX_TID_COUNT];
1610 };
1611
1612 struct rtl_tcb_desc {
1613         u8 packet_bw:1;
1614         u8 multicast:1;
1615         u8 broadcast:1;
1616
1617         u8 rts_stbc:1;
1618         u8 rts_enable:1;
1619         u8 cts_enable:1;
1620         u8 rts_use_shortpreamble:1;
1621         u8 rts_use_shortgi:1;
1622         u8 rts_sc:1;
1623         u8 rts_bw:1;
1624         u8 rts_rate;
1625
1626         u8 use_shortgi:1;
1627         u8 use_shortpreamble:1;
1628         u8 use_driver_rate:1;
1629         u8 disable_ratefallback:1;
1630
1631         u8 ratr_index;
1632         u8 mac_id;
1633         u8 hw_rate;
1634
1635         u8 last_inipkt:1;
1636         u8 cmd_or_init:1;
1637         u8 queue_index;
1638
1639         /* early mode */
1640         u8 empkt_num;
1641         /* The max value by HW */
1642         u32 empkt_len[10];
1643         bool btx_enable_sw_calc_duration;
1644 };
1645
1646 struct rtl_hal_ops {
1647         int (*init_sw_vars) (struct ieee80211_hw *hw);
1648         void (*deinit_sw_vars) (struct ieee80211_hw *hw);
1649         void (*read_chip_version)(struct ieee80211_hw *hw);
1650         void (*read_eeprom_info) (struct ieee80211_hw *hw);
1651         void (*interrupt_recognized) (struct ieee80211_hw *hw,
1652                                       u32 *p_inta, u32 *p_intb);
1653         int (*hw_init) (struct ieee80211_hw *hw);
1654         void (*hw_disable) (struct ieee80211_hw *hw);
1655         void (*hw_suspend) (struct ieee80211_hw *hw);
1656         void (*hw_resume) (struct ieee80211_hw *hw);
1657         void (*enable_interrupt) (struct ieee80211_hw *hw);
1658         void (*disable_interrupt) (struct ieee80211_hw *hw);
1659         int (*set_network_type) (struct ieee80211_hw *hw,
1660                                  enum nl80211_iftype type);
1661         void (*set_chk_bssid)(struct ieee80211_hw *hw,
1662                                 bool check_bssid);
1663         void (*set_bw_mode) (struct ieee80211_hw *hw,
1664                              enum nl80211_channel_type ch_type);
1665          u8(*switch_channel) (struct ieee80211_hw *hw);
1666         void (*set_qos) (struct ieee80211_hw *hw, int aci);
1667         void (*set_bcn_reg) (struct ieee80211_hw *hw);
1668         void (*set_bcn_intv) (struct ieee80211_hw *hw);
1669         void (*update_interrupt_mask) (struct ieee80211_hw *hw,
1670                                        u32 add_msr, u32 rm_msr);
1671         void (*get_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val);
1672         void (*set_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val);
1673         void (*update_rate_tbl) (struct ieee80211_hw *hw,
1674                               struct ieee80211_sta *sta, u8 rssi_level);
1675         void (*update_rate_mask) (struct ieee80211_hw *hw, u8 rssi_level);
1676         void (*fill_tx_desc) (struct ieee80211_hw *hw,
1677                               struct ieee80211_hdr *hdr, u8 *pdesc_tx,
1678                               struct ieee80211_tx_info *info,
1679                               struct ieee80211_sta *sta,
1680                               struct sk_buff *skb, u8 hw_queue,
1681                               struct rtl_tcb_desc *ptcb_desc);
1682         void (*fill_fake_txdesc) (struct ieee80211_hw *hw, u8 *pDesc,
1683                                   u32 buffer_len, bool bIsPsPoll);
1684         void (*fill_tx_cmddesc) (struct ieee80211_hw *hw, u8 *pdesc,
1685                                  bool firstseg, bool lastseg,
1686                                  struct sk_buff *skb);
1687         bool (*cmd_send_packet)(struct ieee80211_hw *hw, struct sk_buff *skb);
1688         bool (*query_rx_desc) (struct ieee80211_hw *hw,
1689                                struct rtl_stats *stats,
1690                                struct ieee80211_rx_status *rx_status,
1691                                u8 *pdesc, struct sk_buff *skb);
1692         void (*set_channel_access) (struct ieee80211_hw *hw);
1693         bool (*radio_onoff_checking) (struct ieee80211_hw *hw, u8 *valid);
1694         void (*dm_watchdog) (struct ieee80211_hw *hw);
1695         void (*scan_operation_backup) (struct ieee80211_hw *hw, u8 operation);
1696         bool (*set_rf_power_state) (struct ieee80211_hw *hw,
1697                                     enum rf_pwrstate rfpwr_state);
1698         void (*led_control) (struct ieee80211_hw *hw,
1699                              enum led_ctl_mode ledaction);
1700         void (*set_desc) (u8 *pdesc, bool istx, u8 desc_name, u8 *val);
1701         u32 (*get_desc) (u8 *pdesc, bool istx, u8 desc_name);
1702         void (*tx_polling) (struct ieee80211_hw *hw, u8 hw_queue);
1703         void (*enable_hw_sec) (struct ieee80211_hw *hw);
1704         void (*set_key) (struct ieee80211_hw *hw, u32 key_index,
1705                          u8 *macaddr, bool is_group, u8 enc_algo,
1706                          bool is_wepkey, bool clear_all);
1707         void (*init_sw_leds) (struct ieee80211_hw *hw);
1708         void (*deinit_sw_leds) (struct ieee80211_hw *hw);
1709         u32 (*get_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask);
1710         void (*set_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask,
1711                            u32 data);
1712         u32 (*get_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath,
1713                           u32 regaddr, u32 bitmask);
1714         void (*set_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath,
1715                            u32 regaddr, u32 bitmask, u32 data);
1716         void (*allow_all_destaddr)(struct ieee80211_hw *hw,
1717                 bool allow_all_da, bool write_into_reg);
1718         void (*linked_set_reg) (struct ieee80211_hw *hw);
1719         void (*chk_switch_dmdp) (struct ieee80211_hw *hw);
1720         void (*dualmac_easy_concurrent) (struct ieee80211_hw *hw);
1721         void (*dualmac_switch_to_dmdp) (struct ieee80211_hw *hw);
1722         bool (*phy_rf6052_config) (struct ieee80211_hw *hw);
1723         void (*phy_rf6052_set_cck_txpower) (struct ieee80211_hw *hw,
1724                                             u8 *powerlevel);
1725         void (*phy_rf6052_set_ofdm_txpower) (struct ieee80211_hw *hw,
1726                                              u8 *ppowerlevel, u8 channel);
1727         bool (*config_bb_with_headerfile) (struct ieee80211_hw *hw,
1728                                            u8 configtype);
1729         bool (*config_bb_with_pgheaderfile) (struct ieee80211_hw *hw,
1730                                              u8 configtype);
1731         void (*phy_lc_calibrate) (struct ieee80211_hw *hw, bool is2t);
1732         void (*phy_set_bw_mode_callback) (struct ieee80211_hw *hw);
1733         void (*dm_dynamic_txpower) (struct ieee80211_hw *hw);
1734         void (*c2h_command_handle) (struct ieee80211_hw *hw);
1735         void (*bt_wifi_media_status_notify) (struct ieee80211_hw *hw,
1736                                              bool mstate);
1737         void (*bt_coex_off_before_lps) (struct ieee80211_hw *hw);
1738 };
1739
1740 struct rtl_intf_ops {
1741         /*com */
1742         void (*read_efuse_byte)(struct ieee80211_hw *hw, u16 _offset, u8 *pbuf);
1743         int (*adapter_start) (struct ieee80211_hw *hw);
1744         void (*adapter_stop) (struct ieee80211_hw *hw);
1745         bool (*check_buddy_priv)(struct ieee80211_hw *hw,
1746                                  struct rtl_priv **buddy_priv);
1747
1748         int (*adapter_tx) (struct ieee80211_hw *hw,
1749                            struct ieee80211_sta *sta,
1750                            struct sk_buff *skb,
1751                            struct rtl_tcb_desc *ptcb_desc);
1752         void (*flush)(struct ieee80211_hw *hw, bool drop);
1753         int (*reset_trx_ring) (struct ieee80211_hw *hw);
1754         bool (*waitq_insert) (struct ieee80211_hw *hw,
1755                               struct ieee80211_sta *sta,
1756                               struct sk_buff *skb);
1757
1758         /*pci */
1759         void (*disable_aspm) (struct ieee80211_hw *hw);
1760         void (*enable_aspm) (struct ieee80211_hw *hw);
1761
1762         /*usb */
1763 };
1764
1765 struct rtl_mod_params {
1766         /* default: 0 = using hardware encryption */
1767         bool sw_crypto;
1768
1769         /* default: 0 = DBG_EMERG (0)*/
1770         int debug;
1771
1772         /* default: 1 = using no linked power save */
1773         bool inactiveps;
1774
1775         /* default: 1 = using linked sw power save */
1776         bool swctrl_lps;
1777
1778         /* default: 1 = using linked fw power save */
1779         bool fwctrl_lps;
1780 };
1781
1782 struct rtl_hal_usbint_cfg {
1783         /* data - rx */
1784         u32 in_ep_num;
1785         u32 rx_urb_num;
1786         u32 rx_max_size;
1787
1788         /* op - rx */
1789         void (*usb_rx_hdl)(struct ieee80211_hw *, struct sk_buff *);
1790         void (*usb_rx_segregate_hdl)(struct ieee80211_hw *, struct sk_buff *,
1791                                      struct sk_buff_head *);
1792
1793         /* tx */
1794         void (*usb_tx_cleanup)(struct ieee80211_hw *, struct sk_buff *);
1795         int (*usb_tx_post_hdl)(struct ieee80211_hw *, struct urb *,
1796                                struct sk_buff *);
1797         struct sk_buff *(*usb_tx_aggregate_hdl)(struct ieee80211_hw *,
1798                                                 struct sk_buff_head *);
1799
1800         /* endpoint mapping */
1801         int (*usb_endpoint_mapping)(struct ieee80211_hw *hw);
1802         u16 (*usb_mq_to_hwq)(__le16 fc, u16 mac80211_queue_index);
1803 };
1804
1805 struct rtl_hal_cfg {
1806         u8 bar_id;
1807         bool write_readback;
1808         char *name;
1809         char *fw_name;
1810         struct rtl_hal_ops *ops;
1811         struct rtl_mod_params *mod_params;
1812         struct rtl_hal_usbint_cfg *usb_interface_cfg;
1813
1814         /*this map used for some registers or vars
1815            defined int HAL but used in MAIN */
1816         u32 maps[RTL_VAR_MAP_MAX];
1817
1818 };
1819
1820 struct rtl_locks {
1821         /* mutex */
1822         struct mutex conf_mutex;
1823         struct mutex ps_mutex;
1824
1825         /*spin lock */
1826         spinlock_t ips_lock;
1827         spinlock_t irq_th_lock;
1828         spinlock_t irq_pci_lock;
1829         spinlock_t tx_lock;
1830         spinlock_t h2c_lock;
1831         spinlock_t rf_ps_lock;
1832         spinlock_t rf_lock;
1833         spinlock_t lps_lock;
1834         spinlock_t waitq_lock;
1835         spinlock_t entry_list_lock;
1836         spinlock_t usb_lock;
1837
1838         /*FW clock change */
1839         spinlock_t fw_ps_lock;
1840
1841         /*Dual mac*/
1842         spinlock_t cck_and_rw_pagea_lock;
1843
1844         /*Easy concurrent*/
1845         spinlock_t check_sendpkt_lock;
1846 };
1847
1848 struct rtl_works {
1849         struct ieee80211_hw *hw;
1850
1851         /*timer */
1852         struct timer_list watchdog_timer;
1853         struct timer_list dualmac_easyconcurrent_retrytimer;
1854         struct timer_list fw_clockoff_timer;
1855         struct timer_list fast_antenna_training_timer;
1856         /*task */
1857         struct tasklet_struct irq_tasklet;
1858         struct tasklet_struct irq_prepare_bcn_tasklet;
1859
1860         /*work queue */
1861         struct workqueue_struct *rtl_wq;
1862         struct delayed_work watchdog_wq;
1863         struct delayed_work ips_nic_off_wq;
1864
1865         /* For SW LPS */
1866         struct delayed_work ps_work;
1867         struct delayed_work ps_rfon_wq;
1868         struct delayed_work fwevt_wq;
1869
1870         struct work_struct lps_change_work;
1871 };
1872
1873 struct rtl_debug {
1874         u32 dbgp_type[DBGP_TYPE_MAX];
1875         int global_debuglevel;
1876         u64 global_debugcomponents;
1877
1878         /* add for proc debug */
1879         struct proc_dir_entry *proc_dir;
1880         char proc_name[20];
1881 };
1882
1883 #define MIMO_PS_STATIC                  0
1884 #define MIMO_PS_DYNAMIC                 1
1885 #define MIMO_PS_NOLIMIT                 3
1886
1887 struct rtl_dualmac_easy_concurrent_ctl {
1888         enum band_type currentbandtype_backfordmdp;
1889         bool close_bbandrf_for_dmsp;
1890         bool change_to_dmdp;
1891         bool change_to_dmsp;
1892         bool switch_in_process;
1893 };
1894
1895 struct rtl_dmsp_ctl {
1896         bool activescan_for_slaveofdmsp;
1897         bool scan_for_anothermac_fordmsp;
1898         bool scan_for_itself_fordmsp;
1899         bool writedig_for_anothermacofdmsp;
1900         u32 curdigvalue_for_anothermacofdmsp;
1901         bool changecckpdstate_for_anothermacofdmsp;
1902         u8 curcckpdstate_for_anothermacofdmsp;
1903         bool changetxhighpowerlvl_for_anothermacofdmsp;
1904         u8 curtxhighlvl_for_anothermacofdmsp;
1905         long rssivalmin_for_anothermacofdmsp;
1906 };
1907
1908 struct ps_t {
1909         u8 pre_ccastate;
1910         u8 cur_ccasate;
1911         u8 pre_rfstate;
1912         u8 cur_rfstate;
1913         long rssi_val_min;
1914 };
1915
1916 struct dig_t {
1917         u32 rssi_lowthresh;
1918         u32 rssi_highthresh;
1919         u32 fa_lowthresh;
1920         u32 fa_highthresh;
1921         long last_min_undec_pwdb_for_dm;
1922         long rssi_highpower_lowthresh;
1923         long rssi_highpower_highthresh;
1924         u32 recover_cnt;
1925         u32 pre_igvalue;
1926         u32 cur_igvalue;
1927         long rssi_val;
1928         u8 dig_enable_flag;
1929         u8 dig_ext_port_stage;
1930         u8 dig_algorithm;
1931         u8 dig_twoport_algorithm;
1932         u8 dig_dbgmode;
1933         u8 dig_slgorithm_switch;
1934         u8 cursta_cstate;
1935         u8 presta_cstate;
1936         u8 curmultista_cstate;
1937         char back_val;
1938         char back_range_max;
1939         char back_range_min;
1940         u8 rx_gain_max;
1941         u8 rx_gain_min;
1942         u8 min_undec_pwdb_for_dm;
1943         u8 rssi_val_min;
1944         u8 pre_cck_cca_thres;
1945         u8 cur_cck_cca_thres;
1946         u8 pre_cck_pd_state;
1947         u8 cur_cck_pd_state;
1948         u8 pre_cck_fa_state;
1949         u8 cur_cck_fa_state;
1950         u8 pre_ccastate;
1951         u8 cur_ccasate;
1952         u8 large_fa_hit;
1953         u8 forbidden_igi;
1954         u8 dig_state;
1955         u8 dig_highpwrstate;
1956         u8 cur_sta_cstate;
1957         u8 pre_sta_cstate;
1958         u8 cur_ap_cstate;
1959         u8 pre_ap_cstate;
1960         u8 cur_pd_thstate;
1961         u8 pre_pd_thstate;
1962         u8 cur_cs_ratiostate;
1963         u8 pre_cs_ratiostate;
1964         u8 backoff_enable_flag;
1965         char backoffval_range_max;
1966         char backoffval_range_min;
1967         u8 dig_min_0;
1968         u8 dig_min_1;
1969         bool media_connect_0;
1970         bool media_connect_1;
1971
1972         u32 antdiv_rssi_max;
1973         u32 rssi_max;
1974 };
1975
1976 struct rtl_global_var {
1977         /* from this list we can get
1978          * other adapter's rtl_priv */
1979         struct list_head glb_priv_list;
1980         spinlock_t glb_list_lock;
1981 };
1982
1983 struct rtl_priv {
1984         struct ieee80211_hw *hw;
1985         struct completion firmware_loading_complete;
1986         struct list_head list;
1987         struct rtl_priv *buddy_priv;
1988         struct rtl_global_var *glb_var;
1989         struct rtl_dualmac_easy_concurrent_ctl easy_concurrent_ctl;
1990         struct rtl_dmsp_ctl dmsp_ctl;
1991         struct rtl_locks locks;
1992         struct rtl_works works;
1993         struct rtl_mac mac80211;
1994         struct rtl_hal rtlhal;
1995         struct rtl_regulatory regd;
1996         struct rtl_rfkill rfkill;
1997         struct rtl_io io;
1998         struct rtl_phy phy;
1999         struct rtl_dm dm;
2000         struct rtl_security sec;
2001         struct rtl_efuse efuse;
2002
2003         struct rtl_ps_ctl psc;
2004         struct rate_adaptive ra;
2005         struct wireless_stats stats;
2006         struct rt_link_detect link_info;
2007         struct false_alarm_statistics falsealm_cnt;
2008
2009         struct rtl_rate_priv *rate_priv;
2010
2011         /* sta entry list for ap adhoc or mesh */
2012         struct list_head entry_list;
2013
2014         struct rtl_debug dbg;
2015         int max_fw_size;
2016
2017         /*
2018          *hal_cfg : for diff cards
2019          *intf_ops : for diff interrface usb/pcie
2020          */
2021         struct rtl_hal_cfg *cfg;
2022         struct rtl_intf_ops *intf_ops;
2023
2024         /*this var will be set by set_bit,
2025            and was used to indicate status of
2026            interface or hardware */
2027         unsigned long status;
2028
2029         /* tables for dm */
2030         struct dig_t dm_digtable;
2031         struct ps_t dm_pstable;
2032
2033         /* section shared by individual drivers */
2034         union {
2035                 struct {        /* data buffer pointer for USB reads */
2036                         __le32 *usb_data;
2037                         int usb_data_index;
2038                         bool initialized;
2039                 };
2040                 struct {        /* section for 8723ae */
2041                         bool reg_init;  /* true if regs saved */
2042                         u32 reg_874;
2043                         u32 reg_c70;
2044                         u32 reg_85c;
2045                         u32 reg_a74;
2046                         bool bt_operation_on;
2047                 };
2048         };
2049         bool enter_ps;  /* true when entering PS */
2050
2051         /*This must be the last item so
2052            that it points to the data allocated
2053            beyond  this structure like:
2054            rtl_pci_priv or rtl_usb_priv */
2055         u8 priv[0];
2056 };
2057
2058 #define rtl_priv(hw)            (((struct rtl_priv *)(hw)->priv))
2059 #define rtl_mac(rtlpriv)        (&((rtlpriv)->mac80211))
2060 #define rtl_hal(rtlpriv)        (&((rtlpriv)->rtlhal))
2061 #define rtl_efuse(rtlpriv)      (&((rtlpriv)->efuse))
2062 #define rtl_psc(rtlpriv)        (&((rtlpriv)->psc))
2063
2064
2065 /***************************************
2066     Bluetooth Co-existence Related
2067 ****************************************/
2068
2069 enum bt_ant_num {
2070         ANT_X2 = 0,
2071         ANT_X1 = 1,
2072 };
2073
2074 enum bt_co_type {
2075         BT_2WIRE = 0,
2076         BT_ISSC_3WIRE = 1,
2077         BT_ACCEL = 2,
2078         BT_CSR_BC4 = 3,
2079         BT_CSR_BC8 = 4,
2080         BT_RTL8756 = 5,
2081         BT_RTL8723A = 6,
2082 };
2083
2084 enum bt_cur_state {
2085         BT_OFF = 0,
2086         BT_ON = 1,
2087 };
2088
2089 enum bt_service_type {
2090         BT_SCO = 0,
2091         BT_A2DP = 1,
2092         BT_HID = 2,
2093         BT_HID_IDLE = 3,
2094         BT_SCAN = 4,
2095         BT_IDLE = 5,
2096         BT_OTHER_ACTION = 6,
2097         BT_BUSY = 7,
2098         BT_OTHERBUSY = 8,
2099         BT_PAN = 9,
2100 };
2101
2102 enum bt_radio_shared {
2103         BT_RADIO_SHARED = 0,
2104         BT_RADIO_INDIVIDUAL = 1,
2105 };
2106
2107 struct bt_coexist_info {
2108
2109         /* EEPROM BT info. */
2110         u8 eeprom_bt_coexist;
2111         u8 eeprom_bt_type;
2112         u8 eeprom_bt_ant_num;
2113         u8 eeprom_bt_ant_isol;
2114         u8 eeprom_bt_radio_shared;
2115
2116         u8 bt_coexistence;
2117         u8 bt_ant_num;
2118         u8 bt_coexist_type;
2119         u8 bt_state;
2120         u8 bt_cur_state;        /* 0:on, 1:off */
2121         u8 bt_ant_isolation;    /* 0:good, 1:bad */
2122         u8 bt_pape_ctrl;        /* 0:SW, 1:SW/HW dynamic */
2123         u8 bt_service;
2124         u8 bt_radio_shared_type;
2125         u8 bt_rfreg_origin_1e;
2126         u8 bt_rfreg_origin_1f;
2127         u8 bt_rssi_state;
2128         u32 ratio_tx;
2129         u32 ratio_pri;
2130         u32 bt_edca_ul;
2131         u32 bt_edca_dl;
2132
2133         bool init_set;
2134         bool bt_busy_traffic;
2135         bool bt_traffic_mode_set;
2136         bool bt_non_traffic_mode_set;
2137
2138         bool fw_coexist_all_off;
2139         bool sw_coexist_all_off;
2140         bool hw_coexist_all_off;
2141         u32 cstate;
2142         u32 previous_state;
2143         u32 cstate_h;
2144         u32 previous_state_h;
2145
2146         u8 bt_pre_rssi_state;
2147         u8 bt_pre_rssi_state1;
2148
2149         u8 reg_bt_iso;
2150         u8 reg_bt_sco;
2151         bool balance_on;
2152         u8 bt_active_zero_cnt;
2153         bool cur_bt_disabled;
2154         bool pre_bt_disabled;
2155
2156         u8 bt_profile_case;
2157         u8 bt_profile_action;
2158         bool bt_busy;
2159         bool hold_for_bt_operation;
2160         u8 lps_counter;
2161 };
2162
2163
2164 /****************************************
2165         mem access macro define start
2166         Call endian free function when
2167         1. Read/write packet content.
2168         2. Before write integer to IO.
2169         3. After read integer from IO.
2170 ****************************************/
2171 /* Convert little data endian to host ordering */
2172 #define EF1BYTE(_val)           \
2173         ((u8)(_val))
2174 #define EF2BYTE(_val)           \
2175         (le16_to_cpu(_val))
2176 #define EF4BYTE(_val)           \
2177         (le32_to_cpu(_val))
2178
2179 /* Read data from memory */
2180 #define READEF1BYTE(_ptr)       \
2181         EF1BYTE(*((u8 *)(_ptr)))
2182 /* Read le16 data from memory and convert to host ordering */
2183 #define READEF2BYTE(_ptr)       \
2184         EF2BYTE(*(_ptr))
2185 #define READEF4BYTE(_ptr)       \
2186         EF4BYTE(*(_ptr))
2187
2188 /* Write data to memory */
2189 #define WRITEEF1BYTE(_ptr, _val)        \
2190         (*((u8 *)(_ptr))) = EF1BYTE(_val)
2191 /* Write le16 data to memory in host ordering */
2192 #define WRITEEF2BYTE(_ptr, _val)        \
2193         (*((u16 *)(_ptr))) = EF2BYTE(_val)
2194 #define WRITEEF4BYTE(_ptr, _val)        \
2195         (*((u32 *)(_ptr))) = EF2BYTE(_val)
2196
2197 /* Create a bit mask
2198  * Examples:
2199  * BIT_LEN_MASK_32(0) => 0x00000000
2200  * BIT_LEN_MASK_32(1) => 0x00000001
2201  * BIT_LEN_MASK_32(2) => 0x00000003
2202  * BIT_LEN_MASK_32(32) => 0xFFFFFFFF
2203  */
2204 #define BIT_LEN_MASK_32(__bitlen)        \
2205         (0xFFFFFFFF >> (32 - (__bitlen)))
2206 #define BIT_LEN_MASK_16(__bitlen)        \
2207         (0xFFFF >> (16 - (__bitlen)))
2208 #define BIT_LEN_MASK_8(__bitlen) \
2209         (0xFF >> (8 - (__bitlen)))
2210
2211 /* Create an offset bit mask
2212  * Examples:
2213  * BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003
2214  * BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000
2215  */
2216 #define BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen) \
2217         (BIT_LEN_MASK_32(__bitlen) << (__bitoffset))
2218 #define BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen) \
2219         (BIT_LEN_MASK_16(__bitlen) << (__bitoffset))
2220 #define BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen) \
2221         (BIT_LEN_MASK_8(__bitlen) << (__bitoffset))
2222
2223 /*Description:
2224  * Return 4-byte value in host byte ordering from
2225  * 4-byte pointer in little-endian system.
2226  */
2227 #define LE_P4BYTE_TO_HOST_4BYTE(__pstart) \
2228         (EF4BYTE(*((__le32 *)(__pstart))))
2229 #define LE_P2BYTE_TO_HOST_2BYTE(__pstart) \
2230         (EF2BYTE(*((__le16 *)(__pstart))))
2231 #define LE_P1BYTE_TO_HOST_1BYTE(__pstart) \
2232         (EF1BYTE(*((u8 *)(__pstart))))
2233
2234 /*Description:
2235 Translate subfield (continuous bits in little-endian) of 4-byte
2236 value to host byte ordering.*/
2237 #define LE_BITS_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
2238         ( \
2239                 (LE_P4BYTE_TO_HOST_4BYTE(__pstart) >> (__bitoffset))  & \
2240                 BIT_LEN_MASK_32(__bitlen) \
2241         )
2242 #define LE_BITS_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
2243         ( \
2244                 (LE_P2BYTE_TO_HOST_2BYTE(__pstart) >> (__bitoffset)) & \
2245                 BIT_LEN_MASK_16(__bitlen) \
2246         )
2247 #define LE_BITS_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
2248         ( \
2249                 (LE_P1BYTE_TO_HOST_1BYTE(__pstart) >> (__bitoffset)) & \
2250                 BIT_LEN_MASK_8(__bitlen) \
2251         )
2252
2253 /* Description:
2254  * Mask subfield (continuous bits in little-endian) of 4-byte value
2255  * and return the result in 4-byte value in host byte ordering.
2256  */
2257 #define LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
2258         ( \
2259                 LE_P4BYTE_TO_HOST_4BYTE(__pstart)  & \
2260                 (~BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen)) \
2261         )
2262 #define LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
2263         ( \
2264                 LE_P2BYTE_TO_HOST_2BYTE(__pstart) & \
2265                 (~BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen)) \
2266         )
2267 #define LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
2268         ( \
2269                 LE_P1BYTE_TO_HOST_1BYTE(__pstart) & \
2270                 (~BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen)) \
2271         )
2272
2273 /* Description:
2274  * Set subfield of little-endian 4-byte value to specified value.
2275  */
2276 #define SET_BITS_TO_LE_4BYTE(__pstart, __bitoffset, __bitlen, __val) \
2277         *((u32 *)(__pstart)) = \
2278         ( \
2279                 LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) | \
2280                 ((((u32)__val) & BIT_LEN_MASK_32(__bitlen)) << (__bitoffset)) \
2281         );
2282 #define SET_BITS_TO_LE_2BYTE(__pstart, __bitoffset, __bitlen, __val) \
2283         *((u16 *)(__pstart)) = \
2284         ( \
2285                 LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) | \
2286                 ((((u16)__val) & BIT_LEN_MASK_16(__bitlen)) << (__bitoffset)) \
2287         );
2288 #define SET_BITS_TO_LE_1BYTE(__pstart, __bitoffset, __bitlen, __val) \
2289         *((u8 *)(__pstart)) = EF1BYTE \
2290         ( \
2291                 LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) | \
2292                 ((((u8)__val) & BIT_LEN_MASK_8(__bitlen)) << (__bitoffset)) \
2293         );
2294
2295 #define N_BYTE_ALIGMENT(__value, __aligment) ((__aligment == 1) ? \
2296         (__value) : (((__value + __aligment - 1) / __aligment) * __aligment))
2297
2298 /****************************************
2299         mem access macro define end
2300 ****************************************/
2301
2302 #define byte(x, n) ((x >> (8 * n)) & 0xff)
2303
2304 #define packet_get_type(_packet) (EF1BYTE((_packet).octet[0]) & 0xFC)
2305 #define RTL_WATCH_DOG_TIME      2000
2306 #define MSECS(t)                msecs_to_jiffies(t)
2307 #define WLAN_FC_GET_VERS(fc)    (le16_to_cpu(fc) & IEEE80211_FCTL_VERS)
2308 #define WLAN_FC_GET_TYPE(fc)    (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE)
2309 #define WLAN_FC_GET_STYPE(fc)   (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE)
2310 #define WLAN_FC_MORE_DATA(fc)   (le16_to_cpu(fc) & IEEE80211_FCTL_MOREDATA)
2311 #define rtl_dm(rtlpriv)         (&((rtlpriv)->dm))
2312
2313 #define RT_RF_OFF_LEVL_ASPM             BIT(0)  /*PCI ASPM */
2314 #define RT_RF_OFF_LEVL_CLK_REQ          BIT(1)  /*PCI clock request */
2315 #define RT_RF_OFF_LEVL_PCI_D3           BIT(2)  /*PCI D3 mode */
2316 /*NIC halt, re-initialize hw parameters*/
2317 #define RT_RF_OFF_LEVL_HALT_NIC         BIT(3)
2318 #define RT_RF_OFF_LEVL_FREE_FW          BIT(4)  /*FW free, re-download the FW */
2319 #define RT_RF_OFF_LEVL_FW_32K           BIT(5)  /*FW in 32k */
2320 /*Always enable ASPM and Clock Req in initialization.*/
2321 #define RT_RF_PS_LEVEL_ALWAYS_ASPM      BIT(6)
2322 /* no matter RFOFF or SLEEP we set PS_ASPM_LEVL*/
2323 #define RT_PS_LEVEL_ASPM                BIT(7)
2324 /*When LPS is on, disable 2R if no packet is received or transmittd.*/
2325 #define RT_RF_LPS_DISALBE_2R            BIT(30)
2326 #define RT_RF_LPS_LEVEL_ASPM            BIT(31) /*LPS with ASPM */
2327 #define RT_IN_PS_LEVEL(ppsc, _ps_flg)           \
2328         ((ppsc->cur_ps_level & _ps_flg) ? true : false)
2329 #define RT_CLEAR_PS_LEVEL(ppsc, _ps_flg)        \
2330         (ppsc->cur_ps_level &= (~(_ps_flg)))
2331 #define RT_SET_PS_LEVEL(ppsc, _ps_flg)          \
2332         (ppsc->cur_ps_level |= _ps_flg)
2333
2334 #define container_of_dwork_rtl(x, y, z) \
2335         container_of(container_of(x, struct delayed_work, work), y, z)
2336
2337 #define FILL_OCTET_STRING(_os, _octet, _len)    \
2338                 (_os).octet = (u8 *)(_octet);           \
2339                 (_os).length = (_len);
2340
2341 #define CP_MACADDR(des, src)    \
2342         ((des)[0] = (src)[0], (des)[1] = (src)[1],\
2343         (des)[2] = (src)[2], (des)[3] = (src)[3],\
2344         (des)[4] = (src)[4], (des)[5] = (src)[5])
2345
2346 static inline u8 rtl_read_byte(struct rtl_priv *rtlpriv, u32 addr)
2347 {
2348         return rtlpriv->io.read8_sync(rtlpriv, addr);
2349 }
2350
2351 static inline u16 rtl_read_word(struct rtl_priv *rtlpriv, u32 addr)
2352 {
2353         return rtlpriv->io.read16_sync(rtlpriv, addr);
2354 }
2355
2356 static inline u32 rtl_read_dword(struct rtl_priv *rtlpriv, u32 addr)
2357 {
2358         return rtlpriv->io.read32_sync(rtlpriv, addr);
2359 }
2360
2361 static inline void rtl_write_byte(struct rtl_priv *rtlpriv, u32 addr, u8 val8)
2362 {
2363         rtlpriv->io.write8_async(rtlpriv, addr, val8);
2364
2365         if (rtlpriv->cfg->write_readback)
2366                 rtlpriv->io.read8_sync(rtlpriv, addr);
2367 }
2368
2369 static inline void rtl_write_word(struct rtl_priv *rtlpriv, u32 addr, u16 val16)
2370 {
2371         rtlpriv->io.write16_async(rtlpriv, addr, val16);
2372
2373         if (rtlpriv->cfg->write_readback)
2374                 rtlpriv->io.read16_sync(rtlpriv, addr);
2375 }
2376
2377 static inline void rtl_write_dword(struct rtl_priv *rtlpriv,
2378                                    u32 addr, u32 val32)
2379 {
2380         rtlpriv->io.write32_async(rtlpriv, addr, val32);
2381
2382         if (rtlpriv->cfg->write_readback)
2383                 rtlpriv->io.read32_sync(rtlpriv, addr);
2384 }
2385
2386 static inline u32 rtl_get_bbreg(struct ieee80211_hw *hw,
2387                                 u32 regaddr, u32 bitmask)
2388 {
2389         struct rtl_priv *rtlpriv = hw->priv;
2390
2391         return rtlpriv->cfg->ops->get_bbreg(hw, regaddr, bitmask);
2392 }
2393
2394 static inline void rtl_set_bbreg(struct ieee80211_hw *hw, u32 regaddr,
2395                                  u32 bitmask, u32 data)
2396 {
2397         struct rtl_priv *rtlpriv = hw->priv;
2398
2399         rtlpriv->cfg->ops->set_bbreg(hw, regaddr, bitmask, data);
2400 }
2401
2402 static inline u32 rtl_get_rfreg(struct ieee80211_hw *hw,
2403                                 enum radio_path rfpath, u32 regaddr,
2404                                 u32 bitmask)
2405 {
2406         struct rtl_priv *rtlpriv = hw->priv;
2407
2408         return rtlpriv->cfg->ops->get_rfreg(hw, rfpath, regaddr, bitmask);
2409 }
2410
2411 static inline void rtl_set_rfreg(struct ieee80211_hw *hw,
2412                                  enum radio_path rfpath, u32 regaddr,
2413                                  u32 bitmask, u32 data)
2414 {
2415         struct rtl_priv *rtlpriv = hw->priv;
2416
2417         rtlpriv->cfg->ops->set_rfreg(hw, rfpath, regaddr, bitmask, data);
2418 }
2419
2420 static inline bool is_hal_stop(struct rtl_hal *rtlhal)
2421 {
2422         return (_HAL_STATE_STOP == rtlhal->state);
2423 }
2424
2425 static inline void set_hal_start(struct rtl_hal *rtlhal)
2426 {
2427         rtlhal->state = _HAL_STATE_START;
2428 }
2429
2430 static inline void set_hal_stop(struct rtl_hal *rtlhal)
2431 {
2432         rtlhal->state = _HAL_STATE_STOP;
2433 }
2434
2435 static inline u8 get_rf_type(struct rtl_phy *rtlphy)
2436 {
2437         return rtlphy->rf_type;
2438 }
2439
2440 static inline struct ieee80211_hdr *rtl_get_hdr(struct sk_buff *skb)
2441 {
2442         return (struct ieee80211_hdr *)(skb->data);
2443 }
2444
2445 static inline __le16 rtl_get_fc(struct sk_buff *skb)
2446 {
2447         return rtl_get_hdr(skb)->frame_control;
2448 }
2449
2450 static inline u16 rtl_get_tid_h(struct ieee80211_hdr *hdr)
2451 {
2452         return (ieee80211_get_qos_ctl(hdr))[0] & IEEE80211_QOS_CTL_TID_MASK;
2453 }
2454
2455 static inline u16 rtl_get_tid(struct sk_buff *skb)
2456 {
2457         return rtl_get_tid_h(rtl_get_hdr(skb));
2458 }
2459
2460 static inline struct ieee80211_sta *get_sta(struct ieee80211_hw *hw,
2461                                             struct ieee80211_vif *vif,
2462                                             const u8 *bssid)
2463 {
2464         return ieee80211_find_sta(vif, bssid);
2465 }
2466
2467 static inline struct ieee80211_sta *rtl_find_sta(struct ieee80211_hw *hw,
2468                 u8 *mac_addr)
2469 {
2470         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2471         return ieee80211_find_sta(mac->vif, mac_addr);
2472 }
2473
2474 #endif