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Merge git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6
[deliverable/linux.git] / drivers / net / wireless / rtlwifi / wifi.h
1 /******************************************************************************
2 *
3 * Copyright(c) 2009-2012 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30 #ifndef __RTL_WIFI_H__
31 #define __RTL_WIFI_H__
32
33 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
34
35 #include <linux/sched.h>
36 #include <linux/firmware.h>
37 #include <linux/etherdevice.h>
38 #include <linux/vmalloc.h>
39 #include <linux/usb.h>
40 #include <net/mac80211.h>
41 #include <linux/completion.h>
42 #include "debug.h"
43
44 #define RF_CHANGE_BY_INIT 0
45 #define RF_CHANGE_BY_IPS BIT(28)
46 #define RF_CHANGE_BY_PS BIT(29)
47 #define RF_CHANGE_BY_HW BIT(30)
48 #define RF_CHANGE_BY_SW BIT(31)
49
50 #define IQK_ADDA_REG_NUM 16
51 #define IQK_MAC_REG_NUM 4
52
53 #define MAX_KEY_LEN 61
54 #define KEY_BUF_SIZE 5
55
56 /* QoS related. */
57 /*aci: 0x00 Best Effort*/
58 /*aci: 0x01 Background*/
59 /*aci: 0x10 Video*/
60 /*aci: 0x11 Voice*/
61 /*Max: define total number.*/
62 #define AC0_BE 0
63 #define AC1_BK 1
64 #define AC2_VI 2
65 #define AC3_VO 3
66 #define AC_MAX 4
67 #define QOS_QUEUE_NUM 4
68 #define RTL_MAC80211_NUM_QUEUE 5
69 #define REALTEK_USB_VENQT_MAX_BUF_SIZE 254
70 #define RTL_USB_MAX_RX_COUNT 100
71 #define QBSS_LOAD_SIZE 5
72 #define MAX_WMMELE_LENGTH 64
73
74 #define TOTAL_CAM_ENTRY 32
75
76 /*slot time for 11g. */
77 #define RTL_SLOT_TIME_9 9
78 #define RTL_SLOT_TIME_20 20
79
80 /*related with tcp/ip. */
81 /*if_ehther.h*/
82 #define ETH_P_PAE 0x888E /*Port Access Entity (IEEE 802.1X) */
83 #define ETH_P_IP 0x0800 /*Internet Protocol packet */
84 #define ETH_P_ARP 0x0806 /*Address Resolution packet */
85 #define SNAP_SIZE 6
86 #define PROTOC_TYPE_SIZE 2
87
88 /*related with 802.11 frame*/
89 #define MAC80211_3ADDR_LEN 24
90 #define MAC80211_4ADDR_LEN 30
91
92 #define CHANNEL_MAX_NUMBER (14 + 24 + 21) /* 14 is the max channel no */
93 #define CHANNEL_GROUP_MAX (3 + 9) /* ch1~3, 4~9, 10~14 = three groups */
94 #define MAX_PG_GROUP 13
95 #define CHANNEL_GROUP_MAX_2G 3
96 #define CHANNEL_GROUP_IDX_5GL 3
97 #define CHANNEL_GROUP_IDX_5GM 6
98 #define CHANNEL_GROUP_IDX_5GH 9
99 #define CHANNEL_GROUP_MAX_5G 9
100 #define CHANNEL_MAX_NUMBER_2G 14
101 #define AVG_THERMAL_NUM 8
102 #define AVG_THERMAL_NUM_88E 4
103 #define MAX_TID_COUNT 9
104
105 /* for early mode */
106 #define FCS_LEN 4
107 #define EM_HDR_LEN 8
108
109 #define MAX_TX_COUNT 4
110 #define MAX_RF_PATH 4
111 #define MAX_CHNL_GROUP_24G 6
112 #define MAX_CHNL_GROUP_5G 14
113
114 struct txpower_info_2g {
115 u8 index_cck_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
116 u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
117 /*If only one tx, only BW20 and OFDM are used.*/
118 u8 cck_diff[MAX_RF_PATH][MAX_TX_COUNT];
119 u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT];
120 u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT];
121 u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT];
122 };
123
124 struct txpower_info_5g {
125 u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_5G];
126 /*If only one tx, only BW20, OFDM, BW80 and BW160 are used.*/
127 u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT];
128 u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT];
129 u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT];
130 };
131
132 enum intf_type {
133 INTF_PCI = 0,
134 INTF_USB = 1,
135 };
136
137 enum radio_path {
138 RF90_PATH_A = 0,
139 RF90_PATH_B = 1,
140 RF90_PATH_C = 2,
141 RF90_PATH_D = 3,
142 };
143
144 enum rt_eeprom_type {
145 EEPROM_93C46,
146 EEPROM_93C56,
147 EEPROM_BOOT_EFUSE,
148 };
149
150 enum ttl_status {
151 RTL_STATUS_INTERFACE_START = 0,
152 };
153
154 enum hardware_type {
155 HARDWARE_TYPE_RTL8192E,
156 HARDWARE_TYPE_RTL8192U,
157 HARDWARE_TYPE_RTL8192SE,
158 HARDWARE_TYPE_RTL8192SU,
159 HARDWARE_TYPE_RTL8192CE,
160 HARDWARE_TYPE_RTL8192CU,
161 HARDWARE_TYPE_RTL8192DE,
162 HARDWARE_TYPE_RTL8192DU,
163 HARDWARE_TYPE_RTL8723AE,
164 HARDWARE_TYPE_RTL8723U,
165 HARDWARE_TYPE_RTL8188EE,
166
167 /* keep it last */
168 HARDWARE_TYPE_NUM
169 };
170
171 #define IS_HARDWARE_TYPE_8192SU(rtlhal) \
172 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SU)
173 #define IS_HARDWARE_TYPE_8192SE(rtlhal) \
174 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
175 #define IS_HARDWARE_TYPE_8192CE(rtlhal) \
176 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CE)
177 #define IS_HARDWARE_TYPE_8192CU(rtlhal) \
178 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CU)
179 #define IS_HARDWARE_TYPE_8192DE(rtlhal) \
180 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE)
181 #define IS_HARDWARE_TYPE_8192DU(rtlhal) \
182 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DU)
183 #define IS_HARDWARE_TYPE_8723E(rtlhal) \
184 (rtlhal->hw_type == HARDWARE_TYPE_RTL8723E)
185 #define IS_HARDWARE_TYPE_8723U(rtlhal) \
186 (rtlhal->hw_type == HARDWARE_TYPE_RTL8723U)
187 #define IS_HARDWARE_TYPE_8192S(rtlhal) \
188 (IS_HARDWARE_TYPE_8192SE(rtlhal) || IS_HARDWARE_TYPE_8192SU(rtlhal))
189 #define IS_HARDWARE_TYPE_8192C(rtlhal) \
190 (IS_HARDWARE_TYPE_8192CE(rtlhal) || IS_HARDWARE_TYPE_8192CU(rtlhal))
191 #define IS_HARDWARE_TYPE_8192D(rtlhal) \
192 (IS_HARDWARE_TYPE_8192DE(rtlhal) || IS_HARDWARE_TYPE_8192DU(rtlhal))
193 #define IS_HARDWARE_TYPE_8723(rtlhal) \
194 (IS_HARDWARE_TYPE_8723E(rtlhal) || IS_HARDWARE_TYPE_8723U(rtlhal))
195 #define IS_HARDWARE_TYPE_8723U(rtlhal) \
196 (rtlhal->hw_type == HARDWARE_TYPE_RTL8723U)
197
198 #define RX_HAL_IS_CCK_RATE(_pdesc)\
199 (_pdesc->rxmcs == DESC92_RATE1M || \
200 _pdesc->rxmcs == DESC92_RATE2M || \
201 _pdesc->rxmcs == DESC92_RATE5_5M || \
202 _pdesc->rxmcs == DESC92_RATE11M)
203
204 enum scan_operation_backup_opt {
205 SCAN_OPT_BACKUP = 0,
206 SCAN_OPT_RESTORE,
207 SCAN_OPT_MAX
208 };
209
210 /*RF state.*/
211 enum rf_pwrstate {
212 ERFON,
213 ERFSLEEP,
214 ERFOFF
215 };
216
217 struct bb_reg_def {
218 u32 rfintfs;
219 u32 rfintfi;
220 u32 rfintfo;
221 u32 rfintfe;
222 u32 rf3wire_offset;
223 u32 rflssi_select;
224 u32 rftxgain_stage;
225 u32 rfhssi_para1;
226 u32 rfhssi_para2;
227 u32 rfsw_ctrl;
228 u32 rfagc_control1;
229 u32 rfagc_control2;
230 u32 rfrxiq_imbal;
231 u32 rfrx_afe;
232 u32 rftxiq_imbal;
233 u32 rftx_afe;
234 u32 rf_rb; /* rflssi_readback */
235 u32 rf_rbpi; /* rflssi_readbackpi */
236 };
237
238 enum io_type {
239 IO_CMD_PAUSE_DM_BY_SCAN = 0,
240 IO_CMD_RESUME_DM_BY_SCAN = 1,
241 };
242
243 enum hw_variables {
244 HW_VAR_ETHER_ADDR,
245 HW_VAR_MULTICAST_REG,
246 HW_VAR_BASIC_RATE,
247 HW_VAR_BSSID,
248 HW_VAR_MEDIA_STATUS,
249 HW_VAR_SECURITY_CONF,
250 HW_VAR_BEACON_INTERVAL,
251 HW_VAR_ATIM_WINDOW,
252 HW_VAR_LISTEN_INTERVAL,
253 HW_VAR_CS_COUNTER,
254 HW_VAR_DEFAULTKEY0,
255 HW_VAR_DEFAULTKEY1,
256 HW_VAR_DEFAULTKEY2,
257 HW_VAR_DEFAULTKEY3,
258 HW_VAR_SIFS,
259 HW_VAR_DIFS,
260 HW_VAR_EIFS,
261 HW_VAR_SLOT_TIME,
262 HW_VAR_ACK_PREAMBLE,
263 HW_VAR_CW_CONFIG,
264 HW_VAR_CW_VALUES,
265 HW_VAR_RATE_FALLBACK_CONTROL,
266 HW_VAR_CONTENTION_WINDOW,
267 HW_VAR_RETRY_COUNT,
268 HW_VAR_TR_SWITCH,
269 HW_VAR_COMMAND,
270 HW_VAR_WPA_CONFIG,
271 HW_VAR_AMPDU_MIN_SPACE,
272 HW_VAR_SHORTGI_DENSITY,
273 HW_VAR_AMPDU_FACTOR,
274 HW_VAR_MCS_RATE_AVAILABLE,
275 HW_VAR_AC_PARAM,
276 HW_VAR_ACM_CTRL,
277 HW_VAR_DIS_Req_Qsize,
278 HW_VAR_CCX_CHNL_LOAD,
279 HW_VAR_CCX_NOISE_HISTOGRAM,
280 HW_VAR_CCX_CLM_NHM,
281 HW_VAR_TxOPLimit,
282 HW_VAR_TURBO_MODE,
283 HW_VAR_RF_STATE,
284 HW_VAR_RF_OFF_BY_HW,
285 HW_VAR_BUS_SPEED,
286 HW_VAR_SET_DEV_POWER,
287
288 HW_VAR_RCR,
289 HW_VAR_RATR_0,
290 HW_VAR_RRSR,
291 HW_VAR_CPU_RST,
292 HW_VAR_CHECK_BSSID,
293 HW_VAR_LBK_MODE,
294 HW_VAR_AES_11N_FIX,
295 HW_VAR_USB_RX_AGGR,
296 HW_VAR_USER_CONTROL_TURBO_MODE,
297 HW_VAR_RETRY_LIMIT,
298 HW_VAR_INIT_TX_RATE,
299 HW_VAR_TX_RATE_REG,
300 HW_VAR_EFUSE_USAGE,
301 HW_VAR_EFUSE_BYTES,
302 HW_VAR_AUTOLOAD_STATUS,
303 HW_VAR_RF_2R_DISABLE,
304 HW_VAR_SET_RPWM,
305 HW_VAR_H2C_FW_PWRMODE,
306 HW_VAR_H2C_FW_JOINBSSRPT,
307 HW_VAR_H2C_FW_P2P_PS_OFFLOAD,
308 HW_VAR_FW_PSMODE_STATUS,
309 HW_VAR_RESUME_CLK_ON,
310 HW_VAR_FW_LPS_ACTION,
311 HW_VAR_1X1_RECV_COMBINE,
312 HW_VAR_STOP_SEND_BEACON,
313 HW_VAR_TSF_TIMER,
314 HW_VAR_IO_CMD,
315
316 HW_VAR_RF_RECOVERY,
317 HW_VAR_H2C_FW_UPDATE_GTK,
318 HW_VAR_WF_MASK,
319 HW_VAR_WF_CRC,
320 HW_VAR_WF_IS_MAC_ADDR,
321 HW_VAR_H2C_FW_OFFLOAD,
322 HW_VAR_RESET_WFCRC,
323
324 HW_VAR_HANDLE_FW_C2H,
325 HW_VAR_DL_FW_RSVD_PAGE,
326 HW_VAR_AID,
327 HW_VAR_HW_SEQ_ENABLE,
328 HW_VAR_CORRECT_TSF,
329 HW_VAR_BCN_VALID,
330 HW_VAR_FWLPS_RF_ON,
331 HW_VAR_DUAL_TSF_RST,
332 HW_VAR_SWITCH_EPHY_WoWLAN,
333 HW_VAR_INT_MIGRATION,
334 HW_VAR_INT_AC,
335 HW_VAR_RF_TIMING,
336
337 HAL_DEF_WOWLAN,
338 HW_VAR_MRC,
339
340 HW_VAR_MGT_FILTER,
341 HW_VAR_CTRL_FILTER,
342 HW_VAR_DATA_FILTER,
343 };
344
345 enum _RT_MEDIA_STATUS {
346 RT_MEDIA_DISCONNECT = 0,
347 RT_MEDIA_CONNECT = 1
348 };
349
350 enum rt_oem_id {
351 RT_CID_DEFAULT = 0,
352 RT_CID_8187_ALPHA0 = 1,
353 RT_CID_8187_SERCOMM_PS = 2,
354 RT_CID_8187_HW_LED = 3,
355 RT_CID_8187_NETGEAR = 4,
356 RT_CID_WHQL = 5,
357 RT_CID_819x_CAMEO = 6,
358 RT_CID_819x_RUNTOP = 7,
359 RT_CID_819x_Senao = 8,
360 RT_CID_TOSHIBA = 9,
361 RT_CID_819x_Netcore = 10,
362 RT_CID_Nettronix = 11,
363 RT_CID_DLINK = 12,
364 RT_CID_PRONET = 13,
365 RT_CID_COREGA = 14,
366 RT_CID_819x_ALPHA = 15,
367 RT_CID_819x_Sitecom = 16,
368 RT_CID_CCX = 17,
369 RT_CID_819x_Lenovo = 18,
370 RT_CID_819x_QMI = 19,
371 RT_CID_819x_Edimax_Belkin = 20,
372 RT_CID_819x_Sercomm_Belkin = 21,
373 RT_CID_819x_CAMEO1 = 22,
374 RT_CID_819x_MSI = 23,
375 RT_CID_819x_Acer = 24,
376 RT_CID_819x_HP = 27,
377 RT_CID_819x_CLEVO = 28,
378 RT_CID_819x_Arcadyan_Belkin = 29,
379 RT_CID_819x_SAMSUNG = 30,
380 RT_CID_819x_WNC_COREGA = 31,
381 RT_CID_819x_Foxcoon = 32,
382 RT_CID_819x_DELL = 33,
383 RT_CID_819x_PRONETS = 34,
384 RT_CID_819x_Edimax_ASUS = 35,
385 RT_CID_NETGEAR = 36,
386 RT_CID_PLANEX = 37,
387 RT_CID_CC_C = 38,
388 };
389
390 enum hw_descs {
391 HW_DESC_OWN,
392 HW_DESC_RXOWN,
393 HW_DESC_TX_NEXTDESC_ADDR,
394 HW_DESC_TXBUFF_ADDR,
395 HW_DESC_RXBUFF_ADDR,
396 HW_DESC_RXPKT_LEN,
397 HW_DESC_RXERO,
398 };
399
400 enum prime_sc {
401 PRIME_CHNL_OFFSET_DONT_CARE = 0,
402 PRIME_CHNL_OFFSET_LOWER = 1,
403 PRIME_CHNL_OFFSET_UPPER = 2,
404 };
405
406 enum rf_type {
407 RF_1T1R = 0,
408 RF_1T2R = 1,
409 RF_2T2R = 2,
410 RF_2T2R_GREEN = 3,
411 };
412
413 enum ht_channel_width {
414 HT_CHANNEL_WIDTH_20 = 0,
415 HT_CHANNEL_WIDTH_20_40 = 1,
416 };
417
418 /* Ref: 802.11i sepc D10.0 7.3.2.25.1
419 Cipher Suites Encryption Algorithms */
420 enum rt_enc_alg {
421 NO_ENCRYPTION = 0,
422 WEP40_ENCRYPTION = 1,
423 TKIP_ENCRYPTION = 2,
424 RSERVED_ENCRYPTION = 3,
425 AESCCMP_ENCRYPTION = 4,
426 WEP104_ENCRYPTION = 5,
427 AESCMAC_ENCRYPTION = 6, /*IEEE802.11w */
428 };
429
430 enum rtl_hal_state {
431 _HAL_STATE_STOP = 0,
432 _HAL_STATE_START = 1,
433 };
434
435 enum rtl_desc92_rate {
436 DESC92_RATE1M = 0x00,
437 DESC92_RATE2M = 0x01,
438 DESC92_RATE5_5M = 0x02,
439 DESC92_RATE11M = 0x03,
440
441 DESC92_RATE6M = 0x04,
442 DESC92_RATE9M = 0x05,
443 DESC92_RATE12M = 0x06,
444 DESC92_RATE18M = 0x07,
445 DESC92_RATE24M = 0x08,
446 DESC92_RATE36M = 0x09,
447 DESC92_RATE48M = 0x0a,
448 DESC92_RATE54M = 0x0b,
449
450 DESC92_RATEMCS0 = 0x0c,
451 DESC92_RATEMCS1 = 0x0d,
452 DESC92_RATEMCS2 = 0x0e,
453 DESC92_RATEMCS3 = 0x0f,
454 DESC92_RATEMCS4 = 0x10,
455 DESC92_RATEMCS5 = 0x11,
456 DESC92_RATEMCS6 = 0x12,
457 DESC92_RATEMCS7 = 0x13,
458 DESC92_RATEMCS8 = 0x14,
459 DESC92_RATEMCS9 = 0x15,
460 DESC92_RATEMCS10 = 0x16,
461 DESC92_RATEMCS11 = 0x17,
462 DESC92_RATEMCS12 = 0x18,
463 DESC92_RATEMCS13 = 0x19,
464 DESC92_RATEMCS14 = 0x1a,
465 DESC92_RATEMCS15 = 0x1b,
466 DESC92_RATEMCS15_SG = 0x1c,
467 DESC92_RATEMCS32 = 0x20,
468 };
469
470 enum rtl_var_map {
471 /*reg map */
472 SYS_ISO_CTRL = 0,
473 SYS_FUNC_EN,
474 SYS_CLK,
475 MAC_RCR_AM,
476 MAC_RCR_AB,
477 MAC_RCR_ACRC32,
478 MAC_RCR_ACF,
479 MAC_RCR_AAP,
480
481 /*efuse map */
482 EFUSE_TEST,
483 EFUSE_CTRL,
484 EFUSE_CLK,
485 EFUSE_CLK_CTRL,
486 EFUSE_PWC_EV12V,
487 EFUSE_FEN_ELDR,
488 EFUSE_LOADER_CLK_EN,
489 EFUSE_ANA8M,
490 EFUSE_HWSET_MAX_SIZE,
491 EFUSE_MAX_SECTION_MAP,
492 EFUSE_REAL_CONTENT_SIZE,
493 EFUSE_OOB_PROTECT_BYTES_LEN,
494 EFUSE_ACCESS,
495
496 /*CAM map */
497 RWCAM,
498 WCAMI,
499 RCAMO,
500 CAMDBG,
501 SECR,
502 SEC_CAM_NONE,
503 SEC_CAM_WEP40,
504 SEC_CAM_TKIP,
505 SEC_CAM_AES,
506 SEC_CAM_WEP104,
507
508 /*IMR map */
509 RTL_IMR_BCNDMAINT6, /*Beacon DMA Interrupt 6 */
510 RTL_IMR_BCNDMAINT5, /*Beacon DMA Interrupt 5 */
511 RTL_IMR_BCNDMAINT4, /*Beacon DMA Interrupt 4 */
512 RTL_IMR_BCNDMAINT3, /*Beacon DMA Interrupt 3 */
513 RTL_IMR_BCNDMAINT2, /*Beacon DMA Interrupt 2 */
514 RTL_IMR_BCNDMAINT1, /*Beacon DMA Interrupt 1 */
515 RTL_IMR_BCNDOK8, /*Beacon Queue DMA OK Interrup 8 */
516 RTL_IMR_BCNDOK7, /*Beacon Queue DMA OK Interrup 7 */
517 RTL_IMR_BCNDOK6, /*Beacon Queue DMA OK Interrup 6 */
518 RTL_IMR_BCNDOK5, /*Beacon Queue DMA OK Interrup 5 */
519 RTL_IMR_BCNDOK4, /*Beacon Queue DMA OK Interrup 4 */
520 RTL_IMR_BCNDOK3, /*Beacon Queue DMA OK Interrup 3 */
521 RTL_IMR_BCNDOK2, /*Beacon Queue DMA OK Interrup 2 */
522 RTL_IMR_BCNDOK1, /*Beacon Queue DMA OK Interrup 1 */
523 RTL_IMR_TIMEOUT2, /*Timeout interrupt 2 */
524 RTL_IMR_TIMEOUT1, /*Timeout interrupt 1 */
525 RTL_IMR_TXFOVW, /*Transmit FIFO Overflow */
526 RTL_IMR_PSTIMEOUT, /*Power save time out interrupt */
527 RTL_IMR_BCNINT, /*Beacon DMA Interrupt 0 */
528 RTL_IMR_RXFOVW, /*Receive FIFO Overflow */
529 RTL_IMR_RDU, /*Receive Descriptor Unavailable */
530 RTL_IMR_ATIMEND, /*For 92C,ATIM Window End Interrupt */
531 RTL_IMR_BDOK, /*Beacon Queue DMA OK Interrup */
532 RTL_IMR_HIGHDOK, /*High Queue DMA OK Interrupt */
533 RTL_IMR_COMDOK, /*Command Queue DMA OK Interrupt*/
534 RTL_IMR_TBDOK, /*Transmit Beacon OK interrup */
535 RTL_IMR_MGNTDOK, /*Management Queue DMA OK Interrupt */
536 RTL_IMR_TBDER, /*For 92C,Transmit Beacon Error Interrupt */
537 RTL_IMR_BKDOK, /*AC_BK DMA OK Interrupt */
538 RTL_IMR_BEDOK, /*AC_BE DMA OK Interrupt */
539 RTL_IMR_VIDOK, /*AC_VI DMA OK Interrupt */
540 RTL_IMR_VODOK, /*AC_VO DMA Interrupt */
541 RTL_IMR_ROK, /*Receive DMA OK Interrupt */
542 RTL_IBSS_INT_MASKS, /*(RTL_IMR_BCNINT | RTL_IMR_TBDOK |
543 * RTL_IMR_TBDER) */
544 RTL_IMR_C2HCMD, /*fw interrupt*/
545
546 /*CCK Rates, TxHT = 0 */
547 RTL_RC_CCK_RATE1M,
548 RTL_RC_CCK_RATE2M,
549 RTL_RC_CCK_RATE5_5M,
550 RTL_RC_CCK_RATE11M,
551
552 /*OFDM Rates, TxHT = 0 */
553 RTL_RC_OFDM_RATE6M,
554 RTL_RC_OFDM_RATE9M,
555 RTL_RC_OFDM_RATE12M,
556 RTL_RC_OFDM_RATE18M,
557 RTL_RC_OFDM_RATE24M,
558 RTL_RC_OFDM_RATE36M,
559 RTL_RC_OFDM_RATE48M,
560 RTL_RC_OFDM_RATE54M,
561
562 RTL_RC_HT_RATEMCS7,
563 RTL_RC_HT_RATEMCS15,
564
565 /*keep it last */
566 RTL_VAR_MAP_MAX,
567 };
568
569 /*Firmware PS mode for control LPS.*/
570 enum _fw_ps_mode {
571 FW_PS_ACTIVE_MODE = 0,
572 FW_PS_MIN_MODE = 1,
573 FW_PS_MAX_MODE = 2,
574 FW_PS_DTIM_MODE = 3,
575 FW_PS_VOIP_MODE = 4,
576 FW_PS_UAPSD_WMM_MODE = 5,
577 FW_PS_UAPSD_MODE = 6,
578 FW_PS_IBSS_MODE = 7,
579 FW_PS_WWLAN_MODE = 8,
580 FW_PS_PM_Radio_Off = 9,
581 FW_PS_PM_Card_Disable = 10,
582 };
583
584 enum rt_psmode {
585 EACTIVE, /*Active/Continuous access. */
586 EMAXPS, /*Max power save mode. */
587 EFASTPS, /*Fast power save mode. */
588 EAUTOPS, /*Auto power save mode. */
589 };
590
591 /*LED related.*/
592 enum led_ctl_mode {
593 LED_CTL_POWER_ON = 1,
594 LED_CTL_LINK = 2,
595 LED_CTL_NO_LINK = 3,
596 LED_CTL_TX = 4,
597 LED_CTL_RX = 5,
598 LED_CTL_SITE_SURVEY = 6,
599 LED_CTL_POWER_OFF = 7,
600 LED_CTL_START_TO_LINK = 8,
601 LED_CTL_START_WPS = 9,
602 LED_CTL_STOP_WPS = 10,
603 };
604
605 enum rtl_led_pin {
606 LED_PIN_GPIO0,
607 LED_PIN_LED0,
608 LED_PIN_LED1,
609 LED_PIN_LED2
610 };
611
612 /*QoS related.*/
613 /*acm implementation method.*/
614 enum acm_method {
615 eAcmWay0_SwAndHw = 0,
616 eAcmWay1_HW = 1,
617 eAcmWay2_SW = 2,
618 };
619
620 enum macphy_mode {
621 SINGLEMAC_SINGLEPHY = 0,
622 DUALMAC_DUALPHY,
623 DUALMAC_SINGLEPHY,
624 };
625
626 enum band_type {
627 BAND_ON_2_4G = 0,
628 BAND_ON_5G,
629 BAND_ON_BOTH,
630 BANDMAX
631 };
632
633 /*aci/aifsn Field.
634 Ref: WMM spec 2.2.2: WME Parameter Element, p.12.*/
635 union aci_aifsn {
636 u8 char_data;
637
638 struct {
639 u8 aifsn:4;
640 u8 acm:1;
641 u8 aci:2;
642 u8 reserved:1;
643 } f; /* Field */
644 };
645
646 /*mlme related.*/
647 enum wireless_mode {
648 WIRELESS_MODE_UNKNOWN = 0x00,
649 WIRELESS_MODE_A = 0x01,
650 WIRELESS_MODE_B = 0x02,
651 WIRELESS_MODE_G = 0x04,
652 WIRELESS_MODE_AUTO = 0x08,
653 WIRELESS_MODE_N_24G = 0x10,
654 WIRELESS_MODE_N_5G = 0x20
655 };
656
657 #define IS_WIRELESS_MODE_A(wirelessmode) \
658 (wirelessmode == WIRELESS_MODE_A)
659 #define IS_WIRELESS_MODE_B(wirelessmode) \
660 (wirelessmode == WIRELESS_MODE_B)
661 #define IS_WIRELESS_MODE_G(wirelessmode) \
662 (wirelessmode == WIRELESS_MODE_G)
663 #define IS_WIRELESS_MODE_N_24G(wirelessmode) \
664 (wirelessmode == WIRELESS_MODE_N_24G)
665 #define IS_WIRELESS_MODE_N_5G(wirelessmode) \
666 (wirelessmode == WIRELESS_MODE_N_5G)
667
668 enum ratr_table_mode {
669 RATR_INX_WIRELESS_NGB = 0,
670 RATR_INX_WIRELESS_NG = 1,
671 RATR_INX_WIRELESS_NB = 2,
672 RATR_INX_WIRELESS_N = 3,
673 RATR_INX_WIRELESS_GB = 4,
674 RATR_INX_WIRELESS_G = 5,
675 RATR_INX_WIRELESS_B = 6,
676 RATR_INX_WIRELESS_MC = 7,
677 RATR_INX_WIRELESS_A = 8,
678 };
679
680 enum rtl_link_state {
681 MAC80211_NOLINK = 0,
682 MAC80211_LINKING = 1,
683 MAC80211_LINKED = 2,
684 MAC80211_LINKED_SCANNING = 3,
685 };
686
687 enum act_category {
688 ACT_CAT_QOS = 1,
689 ACT_CAT_DLS = 2,
690 ACT_CAT_BA = 3,
691 ACT_CAT_HT = 7,
692 ACT_CAT_WMM = 17,
693 };
694
695 enum ba_action {
696 ACT_ADDBAREQ = 0,
697 ACT_ADDBARSP = 1,
698 ACT_DELBA = 2,
699 };
700
701 enum rt_polarity_ctl {
702 RT_POLARITY_LOW_ACT = 0,
703 RT_POLARITY_HIGH_ACT = 1,
704 };
705
706 struct octet_string {
707 u8 *octet;
708 u16 length;
709 };
710
711 struct rtl_hdr_3addr {
712 __le16 frame_ctl;
713 __le16 duration_id;
714 u8 addr1[ETH_ALEN];
715 u8 addr2[ETH_ALEN];
716 u8 addr3[ETH_ALEN];
717 __le16 seq_ctl;
718 u8 payload[0];
719 } __packed;
720
721 struct rtl_info_element {
722 u8 id;
723 u8 len;
724 u8 data[0];
725 } __packed;
726
727 struct rtl_probe_rsp {
728 struct rtl_hdr_3addr header;
729 u32 time_stamp[2];
730 __le16 beacon_interval;
731 __le16 capability;
732 /*SSID, supported rates, FH params, DS params,
733 CF params, IBSS params, TIM (if beacon), RSN */
734 struct rtl_info_element info_element[0];
735 } __packed;
736
737 /*LED related.*/
738 /*ledpin Identify how to implement this SW led.*/
739 struct rtl_led {
740 void *hw;
741 enum rtl_led_pin ledpin;
742 bool ledon;
743 };
744
745 struct rtl_led_ctl {
746 bool led_opendrain;
747 struct rtl_led sw_led0;
748 struct rtl_led sw_led1;
749 };
750
751 struct rtl_qos_parameters {
752 __le16 cw_min;
753 __le16 cw_max;
754 u8 aifs;
755 u8 flag;
756 __le16 tx_op;
757 } __packed;
758
759 struct rt_smooth_data {
760 u32 elements[100]; /*array to store values */
761 u32 index; /*index to current array to store */
762 u32 total_num; /*num of valid elements */
763 u32 total_val; /*sum of valid elements */
764 };
765
766 struct false_alarm_statistics {
767 u32 cnt_parity_fail;
768 u32 cnt_rate_illegal;
769 u32 cnt_crc8_fail;
770 u32 cnt_mcs_fail;
771 u32 cnt_fast_fsync_fail;
772 u32 cnt_sb_search_fail;
773 u32 cnt_ofdm_fail;
774 u32 cnt_cck_fail;
775 u32 cnt_all;
776 u32 cnt_ofdm_cca;
777 u32 cnt_cck_cca;
778 u32 cnt_cca_all;
779 u32 cnt_bw_usc;
780 u32 cnt_bw_lsc;
781 };
782
783 struct init_gain {
784 u8 xaagccore1;
785 u8 xbagccore1;
786 u8 xcagccore1;
787 u8 xdagccore1;
788 u8 cca;
789
790 };
791
792 struct wireless_stats {
793 unsigned long txbytesunicast;
794 unsigned long txbytesmulticast;
795 unsigned long txbytesbroadcast;
796 unsigned long rxbytesunicast;
797
798 long rx_snr_db[4];
799 /*Correct smoothed ss in Dbm, only used
800 in driver to report real power now. */
801 long recv_signal_power;
802 long signal_quality;
803 long last_sigstrength_inpercent;
804
805 u32 rssi_calculate_cnt;
806
807 /*Transformed, in dbm. Beautified signal
808 strength for UI, not correct. */
809 long signal_strength;
810
811 u8 rx_rssi_percentage[4];
812 u8 rx_evm_percentage[2];
813
814 struct rt_smooth_data ui_rssi;
815 struct rt_smooth_data ui_link_quality;
816 };
817
818 struct rate_adaptive {
819 u8 rate_adaptive_disabled;
820 u8 ratr_state;
821 u16 reserve;
822
823 u32 high_rssi_thresh_for_ra;
824 u32 high2low_rssi_thresh_for_ra;
825 u8 low2high_rssi_thresh_for_ra40m;
826 u32 low_rssi_thresh_for_ra40M;
827 u8 low2high_rssi_thresh_for_ra20m;
828 u32 low_rssi_thresh_for_ra20M;
829 u32 upper_rssi_threshold_ratr;
830 u32 middleupper_rssi_threshold_ratr;
831 u32 middle_rssi_threshold_ratr;
832 u32 middlelow_rssi_threshold_ratr;
833 u32 low_rssi_threshold_ratr;
834 u32 ultralow_rssi_threshold_ratr;
835 u32 low_rssi_threshold_ratr_40m;
836 u32 low_rssi_threshold_ratr_20m;
837 u8 ping_rssi_enable;
838 u32 ping_rssi_ratr;
839 u32 ping_rssi_thresh_for_ra;
840 u32 last_ratr;
841 u8 pre_ratr_state;
842 };
843
844 struct regd_pair_mapping {
845 u16 reg_dmnenum;
846 u16 reg_5ghz_ctl;
847 u16 reg_2ghz_ctl;
848 };
849
850 struct rtl_regulatory {
851 char alpha2[2];
852 u16 country_code;
853 u16 max_power_level;
854 u32 tp_scale;
855 u16 current_rd;
856 u16 current_rd_ext;
857 int16_t power_limit;
858 struct regd_pair_mapping *regpair;
859 };
860
861 struct rtl_rfkill {
862 bool rfkill_state; /*0 is off, 1 is on */
863 };
864
865 /*for P2P PS**/
866 #define P2P_MAX_NOA_NUM 2
867
868 enum p2p_role {
869 P2P_ROLE_DISABLE = 0,
870 P2P_ROLE_DEVICE = 1,
871 P2P_ROLE_CLIENT = 2,
872 P2P_ROLE_GO = 3
873 };
874
875 enum p2p_ps_state {
876 P2P_PS_DISABLE = 0,
877 P2P_PS_ENABLE = 1,
878 P2P_PS_SCAN = 2,
879 P2P_PS_SCAN_DONE = 3,
880 P2P_PS_ALLSTASLEEP = 4, /* for P2P GO */
881 };
882
883 enum p2p_ps_mode {
884 P2P_PS_NONE = 0,
885 P2P_PS_CTWINDOW = 1,
886 P2P_PS_NOA = 2,
887 P2P_PS_MIX = 3, /* CTWindow and NoA */
888 };
889
890 struct rtl_p2p_ps_info {
891 enum p2p_ps_mode p2p_ps_mode; /* indicate p2p ps mode */
892 enum p2p_ps_state p2p_ps_state; /* indicate p2p ps state */
893 u8 noa_index; /* Identifies instance of Notice of Absence timing. */
894 /* Client traffic window. A period of time in TU after TBTT. */
895 u8 ctwindow;
896 u8 opp_ps; /* opportunistic power save. */
897 u8 noa_num; /* number of NoA descriptor in P2P IE. */
898 /* Count for owner, Type of client. */
899 u8 noa_count_type[P2P_MAX_NOA_NUM];
900 /* Max duration for owner, preferred or min acceptable duration
901 * for client.
902 */
903 u32 noa_duration[P2P_MAX_NOA_NUM];
904 /* Length of interval for owner, preferred or max acceptable intervali
905 * of client.
906 */
907 u32 noa_interval[P2P_MAX_NOA_NUM];
908 /* schedule in terms of the lower 4 bytes of the TSF timer. */
909 u32 noa_start_time[P2P_MAX_NOA_NUM];
910 };
911
912 struct p2p_ps_offload_t {
913 u8 offload_en:1;
914 u8 role:1; /* 1: Owner, 0: Client */
915 u8 ctwindow_en:1;
916 u8 noa0_en:1;
917 u8 noa1_en:1;
918 u8 allstasleep:1;
919 u8 discovery:1;
920 u8 reserved:1;
921 };
922
923 #define IQK_MATRIX_REG_NUM 8
924 #define IQK_MATRIX_SETTINGS_NUM (1 + 24 + 21)
925
926 struct iqk_matrix_regs {
927 bool iqk_done;
928 long value[1][IQK_MATRIX_REG_NUM];
929 };
930
931 struct phy_parameters {
932 u16 length;
933 u32 *pdata;
934 };
935
936 enum hw_param_tab_index {
937 PHY_REG_2T,
938 PHY_REG_1T,
939 PHY_REG_PG,
940 RADIOA_2T,
941 RADIOB_2T,
942 RADIOA_1T,
943 RADIOB_1T,
944 MAC_REG,
945 AGCTAB_2T,
946 AGCTAB_1T,
947 MAX_TAB
948 };
949
950 struct rtl_phy {
951 struct bb_reg_def phyreg_def[4]; /*Radio A/B/C/D */
952 struct init_gain initgain_backup;
953 enum io_type current_io_type;
954
955 u8 rf_mode;
956 u8 rf_type;
957 u8 current_chan_bw;
958 u8 set_bwmode_inprogress;
959 u8 sw_chnl_inprogress;
960 u8 sw_chnl_stage;
961 u8 sw_chnl_step;
962 u8 current_channel;
963 u8 h2c_box_num;
964 u8 set_io_inprogress;
965 u8 lck_inprogress;
966
967 /* record for power tracking */
968 s32 reg_e94;
969 s32 reg_e9c;
970 s32 reg_ea4;
971 s32 reg_eac;
972 s32 reg_eb4;
973 s32 reg_ebc;
974 s32 reg_ec4;
975 s32 reg_ecc;
976 u8 rfpienable;
977 u8 reserve_0;
978 u16 reserve_1;
979 u32 reg_c04, reg_c08, reg_874;
980 u32 adda_backup[16];
981 u32 iqk_mac_backup[IQK_MAC_REG_NUM];
982 u32 iqk_bb_backup[10];
983 bool iqk_initialized;
984
985 /* Dual mac */
986 bool need_iqk;
987 struct iqk_matrix_regs iqk_matrix[IQK_MATRIX_SETTINGS_NUM];
988
989 bool rfpi_enable;
990
991 u8 pwrgroup_cnt;
992 u8 cck_high_power;
993 /* MAX_PG_GROUP groups of pwr diff by rates */
994 u32 mcs_offset[MAX_PG_GROUP][16];
995 u8 default_initialgain[4];
996
997 /* the current Tx power level */
998 u8 cur_cck_txpwridx;
999 u8 cur_ofdm24g_txpwridx;
1000 u8 cur_bw20_txpwridx;
1001 u8 cur_bw40_txpwridx;
1002
1003 u32 rfreg_chnlval[2];
1004 bool apk_done;
1005 u32 reg_rf3c[2]; /* pathA / pathB */
1006
1007 /* bfsync */
1008 u8 framesync;
1009 u32 framesync_c34;
1010
1011 u8 num_total_rfpath;
1012 struct phy_parameters hwparam_tables[MAX_TAB];
1013 u16 rf_pathmap;
1014
1015 enum rt_polarity_ctl polarity_ctl;
1016 };
1017
1018 #define MAX_TID_COUNT 9
1019 #define RTL_AGG_STOP 0
1020 #define RTL_AGG_PROGRESS 1
1021 #define RTL_AGG_START 2
1022 #define RTL_AGG_OPERATIONAL 3
1023 #define RTL_AGG_OFF 0
1024 #define RTL_AGG_ON 1
1025 #define RTL_RX_AGG_START 1
1026 #define RTL_RX_AGG_STOP 0
1027 #define RTL_AGG_EMPTYING_HW_QUEUE_ADDBA 2
1028 #define RTL_AGG_EMPTYING_HW_QUEUE_DELBA 3
1029
1030 struct rtl_ht_agg {
1031 u16 txq_id;
1032 u16 wait_for_ba;
1033 u16 start_idx;
1034 u64 bitmap;
1035 u32 rate_n_flags;
1036 u8 agg_state;
1037 u8 rx_agg_state;
1038 };
1039
1040 struct rssi_sta {
1041 long undec_sm_pwdb;
1042 };
1043
1044 struct rtl_tid_data {
1045 u16 seq_number;
1046 struct rtl_ht_agg agg;
1047 };
1048
1049 struct rtl_sta_info {
1050 struct list_head list;
1051 u8 ratr_index;
1052 u8 wireless_mode;
1053 u8 mimo_ps;
1054 u8 mac_addr[ETH_ALEN];
1055 struct rtl_tid_data tids[MAX_TID_COUNT];
1056
1057 /* just used for ap adhoc or mesh*/
1058 struct rssi_sta rssi_stat;
1059 } __packed;
1060
1061 struct rtl_priv;
1062 struct rtl_io {
1063 struct device *dev;
1064 struct mutex bb_mutex;
1065
1066 /*PCI MEM map */
1067 unsigned long pci_mem_end; /*shared mem end */
1068 unsigned long pci_mem_start; /*shared mem start */
1069
1070 /*PCI IO map */
1071 unsigned long pci_base_addr; /*device I/O address */
1072
1073 void (*write8_async) (struct rtl_priv *rtlpriv, u32 addr, u8 val);
1074 void (*write16_async) (struct rtl_priv *rtlpriv, u32 addr, u16 val);
1075 void (*write32_async) (struct rtl_priv *rtlpriv, u32 addr, u32 val);
1076 void (*writeN_sync) (struct rtl_priv *rtlpriv, u32 addr, void *buf,
1077 u16 len);
1078
1079 u8(*read8_sync) (struct rtl_priv *rtlpriv, u32 addr);
1080 u16(*read16_sync) (struct rtl_priv *rtlpriv, u32 addr);
1081 u32(*read32_sync) (struct rtl_priv *rtlpriv, u32 addr);
1082
1083 };
1084
1085 struct rtl_mac {
1086 u8 mac_addr[ETH_ALEN];
1087 u8 mac80211_registered;
1088 u8 beacon_enabled;
1089
1090 u32 tx_ss_num;
1091 u32 rx_ss_num;
1092
1093 struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];
1094 struct ieee80211_hw *hw;
1095 struct ieee80211_vif *vif;
1096 enum nl80211_iftype opmode;
1097
1098 /*Probe Beacon management */
1099 struct rtl_tid_data tids[MAX_TID_COUNT];
1100 enum rtl_link_state link_state;
1101
1102 int n_channels;
1103 int n_bitrates;
1104
1105 bool offchan_delay;
1106 u8 p2p; /*using p2p role*/
1107 bool p2p_in_use;
1108
1109 /*filters */
1110 u32 rx_conf;
1111 u16 rx_mgt_filter;
1112 u16 rx_ctrl_filter;
1113 u16 rx_data_filter;
1114
1115 bool act_scanning;
1116 u8 cnt_after_linked;
1117 bool skip_scan;
1118
1119 /* early mode */
1120 /* skb wait queue */
1121 struct sk_buff_head skb_waitq[MAX_TID_COUNT];
1122
1123 /*RDG*/
1124 bool rdg_en;
1125
1126 /*AP*/
1127 u8 bssid[6];
1128 u32 vendor;
1129 u8 mcs[16]; /* 16 bytes mcs for HT rates. */
1130 u32 basic_rates; /* b/g rates */
1131 u8 ht_enable;
1132 u8 sgi_40;
1133 u8 sgi_20;
1134 u8 bw_40;
1135 u8 mode; /* wireless mode */
1136 u8 slot_time;
1137 u8 short_preamble;
1138 u8 use_cts_protect;
1139 u8 cur_40_prime_sc;
1140 u8 cur_40_prime_sc_bk;
1141 u64 tsf;
1142 u8 retry_short;
1143 u8 retry_long;
1144 u16 assoc_id;
1145 bool hiddenssid;
1146
1147 /*IBSS*/
1148 int beacon_interval;
1149
1150 /*AMPDU*/
1151 u8 min_space_cfg; /*For Min spacing configurations */
1152 u8 max_mss_density;
1153 u8 current_ampdu_factor;
1154 u8 current_ampdu_density;
1155
1156 /*QOS & EDCA */
1157 struct ieee80211_tx_queue_params edca_param[RTL_MAC80211_NUM_QUEUE];
1158 struct rtl_qos_parameters ac[AC_MAX];
1159
1160 /* counters */
1161 u64 last_txok_cnt;
1162 u64 last_rxok_cnt;
1163 u32 last_bt_edca_ul;
1164 u32 last_bt_edca_dl;
1165 };
1166
1167 struct btdm_8723 {
1168 bool all_off;
1169 bool agc_table_en;
1170 bool adc_back_off_on;
1171 bool b2_ant_hid_en;
1172 bool low_penalty_rate_adaptive;
1173 bool rf_rx_lpf_shrink;
1174 bool reject_aggre_pkt;
1175 bool tra_tdma_on;
1176 u8 tra_tdma_nav;
1177 u8 tra_tdma_ant;
1178 bool tdma_on;
1179 u8 tdma_ant;
1180 u8 tdma_nav;
1181 u8 tdma_dac_swing;
1182 u8 fw_dac_swing_lvl;
1183 bool ps_tdma_on;
1184 u8 ps_tdma_byte[5];
1185 bool pta_on;
1186 u32 val_0x6c0;
1187 u32 val_0x6c8;
1188 u32 val_0x6cc;
1189 bool sw_dac_swing_on;
1190 u32 sw_dac_swing_lvl;
1191 u32 wlan_act_hi;
1192 u32 wlan_act_lo;
1193 u32 bt_retry_index;
1194 bool dec_bt_pwr;
1195 bool ignore_wlan_act;
1196 };
1197
1198 struct bt_coexist_8723 {
1199 u32 high_priority_tx;
1200 u32 high_priority_rx;
1201 u32 low_priority_tx;
1202 u32 low_priority_rx;
1203 u8 c2h_bt_info;
1204 bool c2h_bt_info_req_sent;
1205 bool c2h_bt_inquiry_page;
1206 u32 bt_inq_page_start_time;
1207 u8 bt_retry_cnt;
1208 u8 c2h_bt_info_original;
1209 u8 bt_inquiry_page_cnt;
1210 struct btdm_8723 btdm;
1211 };
1212
1213 struct rtl_hal {
1214 struct ieee80211_hw *hw;
1215 bool driver_is_goingto_unload;
1216 bool up_first_time;
1217 bool first_init;
1218 bool being_init_adapter;
1219 bool bbrf_ready;
1220 bool mac_func_enable;
1221 struct bt_coexist_8723 hal_coex_8723;
1222
1223 enum intf_type interface;
1224 u16 hw_type; /*92c or 92d or 92s and so on */
1225 u8 ic_class;
1226 u8 oem_id;
1227 u32 version; /*version of chip */
1228 u8 state; /*stop 0, start 1 */
1229 u8 board_type;
1230
1231 /*firmware */
1232 u32 fwsize;
1233 u8 *pfirmware;
1234 u16 fw_version;
1235 u16 fw_subversion;
1236 bool h2c_setinprogress;
1237 u8 last_hmeboxnum;
1238 bool fw_ready;
1239 /*Reserve page start offset except beacon in TxQ. */
1240 u8 fw_rsvdpage_startoffset;
1241 u8 h2c_txcmd_seq;
1242
1243 /* FW Cmd IO related */
1244 u16 fwcmd_iomap;
1245 u32 fwcmd_ioparam;
1246 bool set_fwcmd_inprogress;
1247 u8 current_fwcmd_io;
1248
1249 struct p2p_ps_offload_t p2p_ps_offload;
1250 bool fw_clk_change_in_progress;
1251 bool allow_sw_to_change_hwclc;
1252 u8 fw_ps_state;
1253 /**/
1254 bool driver_going2unload;
1255
1256 /*AMPDU init min space*/
1257 u8 minspace_cfg; /*For Min spacing configurations */
1258
1259 /* Dual mac */
1260 enum macphy_mode macphymode;
1261 enum band_type current_bandtype; /* 0:2.4G, 1:5G */
1262 enum band_type current_bandtypebackup;
1263 enum band_type bandset;
1264 /* dual MAC 0--Mac0 1--Mac1 */
1265 u32 interfaceindex;
1266 /* just for DualMac S3S4 */
1267 u8 macphyctl_reg;
1268 bool earlymode_enable;
1269 u8 max_earlymode_num;
1270 /* Dual mac*/
1271 bool during_mac0init_radiob;
1272 bool during_mac1init_radioa;
1273 bool reloadtxpowerindex;
1274 /* True if IMR or IQK have done
1275 for 2.4G in scan progress */
1276 bool load_imrandiqk_setting_for2g;
1277
1278 bool disable_amsdu_8k;
1279 bool master_of_dmsp;
1280 bool slave_of_dmsp;
1281 };
1282
1283 struct rtl_security {
1284 /*default 0 */
1285 bool use_sw_sec;
1286
1287 bool being_setkey;
1288 bool use_defaultkey;
1289 /*Encryption Algorithm for Unicast Packet */
1290 enum rt_enc_alg pairwise_enc_algorithm;
1291 /*Encryption Algorithm for Brocast/Multicast */
1292 enum rt_enc_alg group_enc_algorithm;
1293 /*Cam Entry Bitmap */
1294 u32 hwsec_cam_bitmap;
1295 u8 hwsec_cam_sta_addr[TOTAL_CAM_ENTRY][ETH_ALEN];
1296 /*local Key buffer, indx 0 is for
1297 pairwise key 1-4 is for agoup key. */
1298 u8 key_buf[KEY_BUF_SIZE][MAX_KEY_LEN];
1299 u8 key_len[KEY_BUF_SIZE];
1300
1301 /*The pointer of Pairwise Key,
1302 it always points to KeyBuf[4] */
1303 u8 *pairwise_key;
1304 };
1305
1306 #define ASSOCIATE_ENTRY_NUM 33
1307
1308 struct fast_ant_training {
1309 u8 bssid[6];
1310 u8 antsel_rx_keep_0;
1311 u8 antsel_rx_keep_1;
1312 u8 antsel_rx_keep_2;
1313 u32 ant_sum[7];
1314 u32 ant_cnt[7];
1315 u32 ant_ave[7];
1316 u8 fat_state;
1317 u32 train_idx;
1318 u8 antsel_a[ASSOCIATE_ENTRY_NUM];
1319 u8 antsel_b[ASSOCIATE_ENTRY_NUM];
1320 u8 antsel_c[ASSOCIATE_ENTRY_NUM];
1321 u32 main_ant_sum[ASSOCIATE_ENTRY_NUM];
1322 u32 aux_ant_sum[ASSOCIATE_ENTRY_NUM];
1323 u32 main_ant_cnt[ASSOCIATE_ENTRY_NUM];
1324 u32 aux_ant_cnt[ASSOCIATE_ENTRY_NUM];
1325 u8 rx_idle_ant;
1326 bool becomelinked;
1327 };
1328
1329 struct rtl_dm {
1330 /*PHY status for Dynamic Management */
1331 long entry_min_undec_sm_pwdb;
1332 long undec_sm_pwdb; /*out dm */
1333 long entry_max_undec_sm_pwdb;
1334 bool dm_initialgain_enable;
1335 bool dynamic_txpower_enable;
1336 bool current_turbo_edca;
1337 bool is_any_nonbepkts; /*out dm */
1338 bool is_cur_rdlstate;
1339 bool txpower_trackinginit;
1340 bool disable_framebursting;
1341 bool cck_inch14;
1342 bool txpower_tracking;
1343 bool useramask;
1344 bool rfpath_rxenable[4];
1345 bool inform_fw_driverctrldm;
1346 bool current_mrc_switch;
1347 u8 txpowercount;
1348
1349 u8 thermalvalue_rxgain;
1350 u8 thermalvalue_iqk;
1351 u8 thermalvalue_lck;
1352 u8 thermalvalue;
1353 u8 last_dtp_lvl;
1354 u8 thermalvalue_avg[AVG_THERMAL_NUM];
1355 u8 thermalvalue_avg_index;
1356 bool done_txpower;
1357 u8 dynamic_txhighpower_lvl; /*Tx high power level */
1358 u8 dm_flag; /*Indicate each dynamic mechanism's status. */
1359 u8 dm_type;
1360 u8 txpower_track_control;
1361 bool interrupt_migration;
1362 bool disable_tx_int;
1363 char ofdm_index[2];
1364 char cck_index;
1365 char delta_power_index;
1366 char delta_power_index_last;
1367 char power_index_offset;
1368
1369 /*88e tx power tracking*/
1370 u8 swing_idx_ofdm[2];
1371 u8 swing_idx_ofdm_cur;
1372 u8 swing_idx_ofdm_base;
1373 bool swing_flag_ofdm;
1374 u8 swing_idx_cck;
1375 u8 swing_idx_cck_cur;
1376 u8 swing_idx_cck_base;
1377 bool swing_flag_cck;
1378
1379 /* DMSP */
1380 bool supp_phymode_switch;
1381
1382 struct fast_ant_training fat_table;
1383 };
1384
1385 #define EFUSE_MAX_LOGICAL_SIZE 256
1386
1387 struct rtl_efuse {
1388 bool autoLoad_ok;
1389 bool bootfromefuse;
1390 u16 max_physical_size;
1391
1392 u8 efuse_map[2][EFUSE_MAX_LOGICAL_SIZE];
1393 u16 efuse_usedbytes;
1394 u8 efuse_usedpercentage;
1395 #ifdef EFUSE_REPG_WORKAROUND
1396 bool efuse_re_pg_sec1flag;
1397 u8 efuse_re_pg_data[8];
1398 #endif
1399
1400 u8 autoload_failflag;
1401 u8 autoload_status;
1402
1403 short epromtype;
1404 u16 eeprom_vid;
1405 u16 eeprom_did;
1406 u16 eeprom_svid;
1407 u16 eeprom_smid;
1408 u8 eeprom_oemid;
1409 u16 eeprom_channelplan;
1410 u8 eeprom_version;
1411 u8 board_type;
1412 u8 external_pa;
1413
1414 u8 dev_addr[6];
1415 u8 wowlan_enable;
1416 u8 antenna_div_cfg;
1417 u8 antenna_div_type;
1418
1419 bool txpwr_fromeprom;
1420 u8 eeprom_crystalcap;
1421 u8 eeprom_tssi[2];
1422 u8 eeprom_tssi_5g[3][2]; /* for 5GL/5GM/5GH band. */
1423 u8 eeprom_pwrlimit_ht20[CHANNEL_GROUP_MAX];
1424 u8 eeprom_pwrlimit_ht40[CHANNEL_GROUP_MAX];
1425 u8 eeprom_chnlarea_txpwr_cck[2][CHANNEL_GROUP_MAX_2G];
1426 u8 eeprom_chnlarea_txpwr_ht40_1s[2][CHANNEL_GROUP_MAX];
1427 u8 eprom_chnl_txpwr_ht40_2sdf[2][CHANNEL_GROUP_MAX];
1428 u8 txpwrlevel_cck[2][CHANNEL_MAX_NUMBER_2G];
1429 u8 txpwrlevel_ht40_1s[2][CHANNEL_MAX_NUMBER]; /*For HT 40MHZ pwr */
1430 u8 txpwrlevel_ht40_2s[2][CHANNEL_MAX_NUMBER]; /*For HT 40MHZ pwr */
1431
1432 u8 internal_pa_5g[2]; /* pathA / pathB */
1433 u8 eeprom_c9;
1434 u8 eeprom_cc;
1435
1436 /*For power group */
1437 u8 eeprom_pwrgroup[2][3];
1438 u8 pwrgroup_ht20[2][CHANNEL_MAX_NUMBER];
1439 u8 pwrgroup_ht40[2][CHANNEL_MAX_NUMBER];
1440
1441 char txpwr_ht20diff[2][CHANNEL_MAX_NUMBER]; /*HT 20<->40 Pwr diff */
1442 /*For HT<->legacy pwr diff*/
1443 u8 txpwr_legacyhtdiff[2][CHANNEL_MAX_NUMBER];
1444 u8 txpwr_safetyflag; /* Band edge enable flag */
1445 u16 eeprom_txpowerdiff;
1446 u8 legacy_httxpowerdiff; /* Legacy to HT rate power diff */
1447 u8 antenna_txpwdiff[3];
1448
1449 u8 eeprom_regulatory;
1450 u8 eeprom_thermalmeter;
1451 u8 thermalmeter[2]; /*ThermalMeter, index 0 for RFIC0, 1 for RFIC1 */
1452 u16 tssi_13dbm;
1453 u8 crystalcap; /* CrystalCap. */
1454 u8 delta_iqk;
1455 u8 delta_lck;
1456
1457 u8 legacy_ht_txpowerdiff; /*Legacy to HT rate power diff */
1458 bool apk_thermalmeterignore;
1459
1460 bool b1x1_recvcombine;
1461 bool b1ss_support;
1462
1463 /*channel plan */
1464 u8 channel_plan;
1465 };
1466
1467 struct rtl_ps_ctl {
1468 bool pwrdomain_protect;
1469 bool in_powersavemode;
1470 bool rfchange_inprogress;
1471 bool swrf_processing;
1472 bool hwradiooff;
1473 /*
1474 * just for PCIE ASPM
1475 * If it supports ASPM, Offset[560h] = 0x40,
1476 * otherwise Offset[560h] = 0x00.
1477 * */
1478 bool support_aspm;
1479 bool support_backdoor;
1480
1481 /*for LPS */
1482 enum rt_psmode dot11_psmode; /*Power save mode configured. */
1483 bool swctrl_lps;
1484 bool leisure_ps;
1485 bool fwctrl_lps;
1486 u8 fwctrl_psmode;
1487 /*For Fw control LPS mode */
1488 u8 reg_fwctrl_lps;
1489 /*Record Fw PS mode status. */
1490 bool fw_current_inpsmode;
1491 u8 reg_max_lps_awakeintvl;
1492 bool report_linked;
1493 bool low_power_enable;/*for 32k*/
1494
1495 /*for IPS */
1496 bool inactiveps;
1497
1498 u32 rfoff_reason;
1499
1500 /*RF OFF Level */
1501 u32 cur_ps_level;
1502 u32 reg_rfps_level;
1503
1504 /*just for PCIE ASPM */
1505 u8 const_amdpci_aspm;
1506 bool pwrdown_mode;
1507
1508 enum rf_pwrstate inactive_pwrstate;
1509 enum rf_pwrstate rfpwr_state; /*cur power state */
1510
1511 /* for SW LPS*/
1512 bool sw_ps_enabled;
1513 bool state;
1514 bool state_inap;
1515 bool multi_buffered;
1516 u16 nullfunc_seq;
1517 unsigned int dtim_counter;
1518 unsigned int sleep_ms;
1519 unsigned long last_sleep_jiffies;
1520 unsigned long last_awake_jiffies;
1521 unsigned long last_delaylps_stamp_jiffies;
1522 unsigned long last_dtim;
1523 unsigned long last_beacon;
1524 unsigned long last_action;
1525 unsigned long last_slept;
1526
1527 /*For P2P PS */
1528 struct rtl_p2p_ps_info p2p_ps_info;
1529 u8 pwr_mode;
1530 u8 smart_ps;
1531 };
1532
1533 struct rtl_stats {
1534 u8 psaddr[ETH_ALEN];
1535 u32 mac_time[2];
1536 s8 rssi;
1537 u8 signal;
1538 u8 noise;
1539 u8 rate; /* hw desc rate */
1540 u8 received_channel;
1541 u8 control;
1542 u8 mask;
1543 u8 freq;
1544 u16 len;
1545 u64 tsf;
1546 u32 beacon_time;
1547 u8 nic_type;
1548 u16 length;
1549 u8 signalquality; /*in 0-100 index. */
1550 /*
1551 * Real power in dBm for this packet,
1552 * no beautification and aggregation.
1553 * */
1554 s32 recvsignalpower;
1555 s8 rxpower; /*in dBm Translate from PWdB */
1556 u8 signalstrength; /*in 0-100 index. */
1557 u16 hwerror:1;
1558 u16 crc:1;
1559 u16 icv:1;
1560 u16 shortpreamble:1;
1561 u16 antenna:1;
1562 u16 decrypted:1;
1563 u16 wakeup:1;
1564 u32 timestamp_low;
1565 u32 timestamp_high;
1566
1567 u8 rx_drvinfo_size;
1568 u8 rx_bufshift;
1569 bool isampdu;
1570 bool isfirst_ampdu;
1571 bool rx_is40Mhzpacket;
1572 u32 rx_pwdb_all;
1573 u8 rx_mimo_signalstrength[4]; /*in 0~100 index */
1574 s8 rx_mimo_sig_qual[2];
1575 bool packet_matchbssid;
1576 bool is_cck;
1577 bool is_ht;
1578 bool packet_toself;
1579 bool packet_beacon; /*for rssi */
1580 char cck_adc_pwdb[4]; /*for rx path selection */
1581
1582 u8 packet_report_type;
1583
1584 u32 macid;
1585 u8 wake_match;
1586 u32 bt_rx_rssi_percentage;
1587 u32 macid_valid_entry[2];
1588 };
1589
1590
1591 struct rt_link_detect {
1592 /* count for roaming */
1593 u32 bcn_rx_inperiod;
1594 u32 roam_times;
1595
1596 u32 num_tx_in4period[4];
1597 u32 num_rx_in4period[4];
1598
1599 u32 num_tx_inperiod;
1600 u32 num_rx_inperiod;
1601
1602 bool busytraffic;
1603 bool tx_busy_traffic;
1604 bool rx_busy_traffic;
1605 bool higher_busytraffic;
1606 bool higher_busyrxtraffic;
1607
1608 u32 tidtx_in4period[MAX_TID_COUNT][4];
1609 u32 tidtx_inperiod[MAX_TID_COUNT];
1610 bool higher_busytxtraffic[MAX_TID_COUNT];
1611 };
1612
1613 struct rtl_tcb_desc {
1614 u8 packet_bw:1;
1615 u8 multicast:1;
1616 u8 broadcast:1;
1617
1618 u8 rts_stbc:1;
1619 u8 rts_enable:1;
1620 u8 cts_enable:1;
1621 u8 rts_use_shortpreamble:1;
1622 u8 rts_use_shortgi:1;
1623 u8 rts_sc:1;
1624 u8 rts_bw:1;
1625 u8 rts_rate;
1626
1627 u8 use_shortgi:1;
1628 u8 use_shortpreamble:1;
1629 u8 use_driver_rate:1;
1630 u8 disable_ratefallback:1;
1631
1632 u8 ratr_index;
1633 u8 mac_id;
1634 u8 hw_rate;
1635
1636 u8 last_inipkt:1;
1637 u8 cmd_or_init:1;
1638 u8 queue_index;
1639
1640 /* early mode */
1641 u8 empkt_num;
1642 /* The max value by HW */
1643 u32 empkt_len[10];
1644 bool btx_enable_sw_calc_duration;
1645 };
1646
1647 struct rtl_hal_ops {
1648 int (*init_sw_vars) (struct ieee80211_hw *hw);
1649 void (*deinit_sw_vars) (struct ieee80211_hw *hw);
1650 void (*read_chip_version)(struct ieee80211_hw *hw);
1651 void (*read_eeprom_info) (struct ieee80211_hw *hw);
1652 void (*interrupt_recognized) (struct ieee80211_hw *hw,
1653 u32 *p_inta, u32 *p_intb);
1654 int (*hw_init) (struct ieee80211_hw *hw);
1655 void (*hw_disable) (struct ieee80211_hw *hw);
1656 void (*hw_suspend) (struct ieee80211_hw *hw);
1657 void (*hw_resume) (struct ieee80211_hw *hw);
1658 void (*enable_interrupt) (struct ieee80211_hw *hw);
1659 void (*disable_interrupt) (struct ieee80211_hw *hw);
1660 int (*set_network_type) (struct ieee80211_hw *hw,
1661 enum nl80211_iftype type);
1662 void (*set_chk_bssid)(struct ieee80211_hw *hw,
1663 bool check_bssid);
1664 void (*set_bw_mode) (struct ieee80211_hw *hw,
1665 enum nl80211_channel_type ch_type);
1666 u8(*switch_channel) (struct ieee80211_hw *hw);
1667 void (*set_qos) (struct ieee80211_hw *hw, int aci);
1668 void (*set_bcn_reg) (struct ieee80211_hw *hw);
1669 void (*set_bcn_intv) (struct ieee80211_hw *hw);
1670 void (*update_interrupt_mask) (struct ieee80211_hw *hw,
1671 u32 add_msr, u32 rm_msr);
1672 void (*get_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val);
1673 void (*set_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val);
1674 void (*update_rate_tbl) (struct ieee80211_hw *hw,
1675 struct ieee80211_sta *sta, u8 rssi_level);
1676 void (*update_rate_mask) (struct ieee80211_hw *hw, u8 rssi_level);
1677 void (*fill_tx_desc) (struct ieee80211_hw *hw,
1678 struct ieee80211_hdr *hdr, u8 *pdesc_tx,
1679 struct ieee80211_tx_info *info,
1680 struct ieee80211_sta *sta,
1681 struct sk_buff *skb, u8 hw_queue,
1682 struct rtl_tcb_desc *ptcb_desc);
1683 void (*fill_fake_txdesc) (struct ieee80211_hw *hw, u8 *pDesc,
1684 u32 buffer_len, bool bIsPsPoll);
1685 void (*fill_tx_cmddesc) (struct ieee80211_hw *hw, u8 *pdesc,
1686 bool firstseg, bool lastseg,
1687 struct sk_buff *skb);
1688 bool (*cmd_send_packet)(struct ieee80211_hw *hw, struct sk_buff *skb);
1689 bool (*query_rx_desc) (struct ieee80211_hw *hw,
1690 struct rtl_stats *stats,
1691 struct ieee80211_rx_status *rx_status,
1692 u8 *pdesc, struct sk_buff *skb);
1693 void (*set_channel_access) (struct ieee80211_hw *hw);
1694 bool (*radio_onoff_checking) (struct ieee80211_hw *hw, u8 *valid);
1695 void (*dm_watchdog) (struct ieee80211_hw *hw);
1696 void (*scan_operation_backup) (struct ieee80211_hw *hw, u8 operation);
1697 bool (*set_rf_power_state) (struct ieee80211_hw *hw,
1698 enum rf_pwrstate rfpwr_state);
1699 void (*led_control) (struct ieee80211_hw *hw,
1700 enum led_ctl_mode ledaction);
1701 void (*set_desc) (u8 *pdesc, bool istx, u8 desc_name, u8 *val);
1702 u32 (*get_desc) (u8 *pdesc, bool istx, u8 desc_name);
1703 void (*tx_polling) (struct ieee80211_hw *hw, u8 hw_queue);
1704 void (*enable_hw_sec) (struct ieee80211_hw *hw);
1705 void (*set_key) (struct ieee80211_hw *hw, u32 key_index,
1706 u8 *macaddr, bool is_group, u8 enc_algo,
1707 bool is_wepkey, bool clear_all);
1708 void (*init_sw_leds) (struct ieee80211_hw *hw);
1709 void (*deinit_sw_leds) (struct ieee80211_hw *hw);
1710 u32 (*get_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask);
1711 void (*set_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask,
1712 u32 data);
1713 u32 (*get_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath,
1714 u32 regaddr, u32 bitmask);
1715 void (*set_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath,
1716 u32 regaddr, u32 bitmask, u32 data);
1717 void (*allow_all_destaddr)(struct ieee80211_hw *hw,
1718 bool allow_all_da, bool write_into_reg);
1719 void (*linked_set_reg) (struct ieee80211_hw *hw);
1720 void (*chk_switch_dmdp) (struct ieee80211_hw *hw);
1721 void (*dualmac_easy_concurrent) (struct ieee80211_hw *hw);
1722 void (*dualmac_switch_to_dmdp) (struct ieee80211_hw *hw);
1723 bool (*phy_rf6052_config) (struct ieee80211_hw *hw);
1724 void (*phy_rf6052_set_cck_txpower) (struct ieee80211_hw *hw,
1725 u8 *powerlevel);
1726 void (*phy_rf6052_set_ofdm_txpower) (struct ieee80211_hw *hw,
1727 u8 *ppowerlevel, u8 channel);
1728 bool (*config_bb_with_headerfile) (struct ieee80211_hw *hw,
1729 u8 configtype);
1730 bool (*config_bb_with_pgheaderfile) (struct ieee80211_hw *hw,
1731 u8 configtype);
1732 void (*phy_lc_calibrate) (struct ieee80211_hw *hw, bool is2t);
1733 void (*phy_set_bw_mode_callback) (struct ieee80211_hw *hw);
1734 void (*dm_dynamic_txpower) (struct ieee80211_hw *hw);
1735 void (*c2h_command_handle) (struct ieee80211_hw *hw);
1736 void (*bt_wifi_media_status_notify) (struct ieee80211_hw *hw,
1737 bool mstate);
1738 void (*bt_coex_off_before_lps) (struct ieee80211_hw *hw);
1739 void (*fill_h2c_cmd) (struct ieee80211_hw *hw, u8 element_id,
1740 u32 cmd_len, u8 *p_cmdbuffer);
1741 };
1742
1743 struct rtl_intf_ops {
1744 /*com */
1745 void (*read_efuse_byte)(struct ieee80211_hw *hw, u16 _offset, u8 *pbuf);
1746 int (*adapter_start) (struct ieee80211_hw *hw);
1747 void (*adapter_stop) (struct ieee80211_hw *hw);
1748 bool (*check_buddy_priv)(struct ieee80211_hw *hw,
1749 struct rtl_priv **buddy_priv);
1750
1751 int (*adapter_tx) (struct ieee80211_hw *hw,
1752 struct ieee80211_sta *sta,
1753 struct sk_buff *skb,
1754 struct rtl_tcb_desc *ptcb_desc);
1755 void (*flush)(struct ieee80211_hw *hw, bool drop);
1756 int (*reset_trx_ring) (struct ieee80211_hw *hw);
1757 bool (*waitq_insert) (struct ieee80211_hw *hw,
1758 struct ieee80211_sta *sta,
1759 struct sk_buff *skb);
1760
1761 /*pci */
1762 void (*disable_aspm) (struct ieee80211_hw *hw);
1763 void (*enable_aspm) (struct ieee80211_hw *hw);
1764
1765 /*usb */
1766 };
1767
1768 struct rtl_mod_params {
1769 /* default: 0 = using hardware encryption */
1770 bool sw_crypto;
1771
1772 /* default: 0 = DBG_EMERG (0)*/
1773 int debug;
1774
1775 /* default: 1 = using no linked power save */
1776 bool inactiveps;
1777
1778 /* default: 1 = using linked sw power save */
1779 bool swctrl_lps;
1780
1781 /* default: 1 = using linked fw power save */
1782 bool fwctrl_lps;
1783 };
1784
1785 struct rtl_hal_usbint_cfg {
1786 /* data - rx */
1787 u32 in_ep_num;
1788 u32 rx_urb_num;
1789 u32 rx_max_size;
1790
1791 /* op - rx */
1792 void (*usb_rx_hdl)(struct ieee80211_hw *, struct sk_buff *);
1793 void (*usb_rx_segregate_hdl)(struct ieee80211_hw *, struct sk_buff *,
1794 struct sk_buff_head *);
1795
1796 /* tx */
1797 void (*usb_tx_cleanup)(struct ieee80211_hw *, struct sk_buff *);
1798 int (*usb_tx_post_hdl)(struct ieee80211_hw *, struct urb *,
1799 struct sk_buff *);
1800 struct sk_buff *(*usb_tx_aggregate_hdl)(struct ieee80211_hw *,
1801 struct sk_buff_head *);
1802
1803 /* endpoint mapping */
1804 int (*usb_endpoint_mapping)(struct ieee80211_hw *hw);
1805 u16 (*usb_mq_to_hwq)(__le16 fc, u16 mac80211_queue_index);
1806 };
1807
1808 struct rtl_hal_cfg {
1809 u8 bar_id;
1810 bool write_readback;
1811 char *name;
1812 char *fw_name;
1813 struct rtl_hal_ops *ops;
1814 struct rtl_mod_params *mod_params;
1815 struct rtl_hal_usbint_cfg *usb_interface_cfg;
1816
1817 /*this map used for some registers or vars
1818 defined int HAL but used in MAIN */
1819 u32 maps[RTL_VAR_MAP_MAX];
1820
1821 };
1822
1823 struct rtl_locks {
1824 /* mutex */
1825 struct mutex conf_mutex;
1826 struct mutex ps_mutex;
1827
1828 /*spin lock */
1829 spinlock_t ips_lock;
1830 spinlock_t irq_th_lock;
1831 spinlock_t irq_pci_lock;
1832 spinlock_t tx_lock;
1833 spinlock_t h2c_lock;
1834 spinlock_t rf_ps_lock;
1835 spinlock_t rf_lock;
1836 spinlock_t lps_lock;
1837 spinlock_t waitq_lock;
1838 spinlock_t entry_list_lock;
1839 spinlock_t usb_lock;
1840
1841 /*FW clock change */
1842 spinlock_t fw_ps_lock;
1843
1844 /*Dual mac*/
1845 spinlock_t cck_and_rw_pagea_lock;
1846
1847 /*Easy concurrent*/
1848 spinlock_t check_sendpkt_lock;
1849 };
1850
1851 struct rtl_works {
1852 struct ieee80211_hw *hw;
1853
1854 /*timer */
1855 struct timer_list watchdog_timer;
1856 struct timer_list dualmac_easyconcurrent_retrytimer;
1857 struct timer_list fw_clockoff_timer;
1858 struct timer_list fast_antenna_training_timer;
1859 /*task */
1860 struct tasklet_struct irq_tasklet;
1861 struct tasklet_struct irq_prepare_bcn_tasklet;
1862
1863 /*work queue */
1864 struct workqueue_struct *rtl_wq;
1865 struct delayed_work watchdog_wq;
1866 struct delayed_work ips_nic_off_wq;
1867
1868 /* For SW LPS */
1869 struct delayed_work ps_work;
1870 struct delayed_work ps_rfon_wq;
1871 struct delayed_work fwevt_wq;
1872
1873 struct work_struct lps_change_work;
1874 struct work_struct fill_h2c_cmd;
1875 };
1876
1877 struct rtl_debug {
1878 u32 dbgp_type[DBGP_TYPE_MAX];
1879 int global_debuglevel;
1880 u64 global_debugcomponents;
1881
1882 /* add for proc debug */
1883 struct proc_dir_entry *proc_dir;
1884 char proc_name[20];
1885 };
1886
1887 #define MIMO_PS_STATIC 0
1888 #define MIMO_PS_DYNAMIC 1
1889 #define MIMO_PS_NOLIMIT 3
1890
1891 struct rtl_dualmac_easy_concurrent_ctl {
1892 enum band_type currentbandtype_backfordmdp;
1893 bool close_bbandrf_for_dmsp;
1894 bool change_to_dmdp;
1895 bool change_to_dmsp;
1896 bool switch_in_process;
1897 };
1898
1899 struct rtl_dmsp_ctl {
1900 bool activescan_for_slaveofdmsp;
1901 bool scan_for_anothermac_fordmsp;
1902 bool scan_for_itself_fordmsp;
1903 bool writedig_for_anothermacofdmsp;
1904 u32 curdigvalue_for_anothermacofdmsp;
1905 bool changecckpdstate_for_anothermacofdmsp;
1906 u8 curcckpdstate_for_anothermacofdmsp;
1907 bool changetxhighpowerlvl_for_anothermacofdmsp;
1908 u8 curtxhighlvl_for_anothermacofdmsp;
1909 long rssivalmin_for_anothermacofdmsp;
1910 };
1911
1912 struct ps_t {
1913 u8 pre_ccastate;
1914 u8 cur_ccasate;
1915 u8 pre_rfstate;
1916 u8 cur_rfstate;
1917 long rssi_val_min;
1918 };
1919
1920 struct dig_t {
1921 u32 rssi_lowthresh;
1922 u32 rssi_highthresh;
1923 u32 fa_lowthresh;
1924 u32 fa_highthresh;
1925 long last_min_undec_pwdb_for_dm;
1926 long rssi_highpower_lowthresh;
1927 long rssi_highpower_highthresh;
1928 u32 recover_cnt;
1929 u32 pre_igvalue;
1930 u32 cur_igvalue;
1931 long rssi_val;
1932 u8 dig_enable_flag;
1933 u8 dig_ext_port_stage;
1934 u8 dig_algorithm;
1935 u8 dig_twoport_algorithm;
1936 u8 dig_dbgmode;
1937 u8 dig_slgorithm_switch;
1938 u8 cursta_cstate;
1939 u8 presta_cstate;
1940 u8 curmultista_cstate;
1941 char back_val;
1942 char back_range_max;
1943 char back_range_min;
1944 u8 rx_gain_max;
1945 u8 rx_gain_min;
1946 u8 min_undec_pwdb_for_dm;
1947 u8 rssi_val_min;
1948 u8 pre_cck_cca_thres;
1949 u8 cur_cck_cca_thres;
1950 u8 pre_cck_pd_state;
1951 u8 cur_cck_pd_state;
1952 u8 pre_cck_fa_state;
1953 u8 cur_cck_fa_state;
1954 u8 pre_ccastate;
1955 u8 cur_ccasate;
1956 u8 large_fa_hit;
1957 u8 forbidden_igi;
1958 u8 dig_state;
1959 u8 dig_highpwrstate;
1960 u8 cur_sta_cstate;
1961 u8 pre_sta_cstate;
1962 u8 cur_ap_cstate;
1963 u8 pre_ap_cstate;
1964 u8 cur_pd_thstate;
1965 u8 pre_pd_thstate;
1966 u8 cur_cs_ratiostate;
1967 u8 pre_cs_ratiostate;
1968 u8 backoff_enable_flag;
1969 char backoffval_range_max;
1970 char backoffval_range_min;
1971 u8 dig_min_0;
1972 u8 dig_min_1;
1973 bool media_connect_0;
1974 bool media_connect_1;
1975
1976 u32 antdiv_rssi_max;
1977 u32 rssi_max;
1978 };
1979
1980 struct rtl_global_var {
1981 /* from this list we can get
1982 * other adapter's rtl_priv */
1983 struct list_head glb_priv_list;
1984 spinlock_t glb_list_lock;
1985 };
1986
1987 struct rtl_priv {
1988 struct ieee80211_hw *hw;
1989 struct completion firmware_loading_complete;
1990 struct list_head list;
1991 struct rtl_priv *buddy_priv;
1992 struct rtl_global_var *glb_var;
1993 struct rtl_dualmac_easy_concurrent_ctl easy_concurrent_ctl;
1994 struct rtl_dmsp_ctl dmsp_ctl;
1995 struct rtl_locks locks;
1996 struct rtl_works works;
1997 struct rtl_mac mac80211;
1998 struct rtl_hal rtlhal;
1999 struct rtl_regulatory regd;
2000 struct rtl_rfkill rfkill;
2001 struct rtl_io io;
2002 struct rtl_phy phy;
2003 struct rtl_dm dm;
2004 struct rtl_security sec;
2005 struct rtl_efuse efuse;
2006
2007 struct rtl_ps_ctl psc;
2008 struct rate_adaptive ra;
2009 struct wireless_stats stats;
2010 struct rt_link_detect link_info;
2011 struct false_alarm_statistics falsealm_cnt;
2012
2013 struct rtl_rate_priv *rate_priv;
2014
2015 /* sta entry list for ap adhoc or mesh */
2016 struct list_head entry_list;
2017
2018 struct rtl_debug dbg;
2019 int max_fw_size;
2020
2021 /*
2022 *hal_cfg : for diff cards
2023 *intf_ops : for diff interrface usb/pcie
2024 */
2025 struct rtl_hal_cfg *cfg;
2026 struct rtl_intf_ops *intf_ops;
2027
2028 /*this var will be set by set_bit,
2029 and was used to indicate status of
2030 interface or hardware */
2031 unsigned long status;
2032
2033 /* tables for dm */
2034 struct dig_t dm_digtable;
2035 struct ps_t dm_pstable;
2036
2037 /* section shared by individual drivers */
2038 union {
2039 struct { /* data buffer pointer for USB reads */
2040 __le32 *usb_data;
2041 int usb_data_index;
2042 bool initialized;
2043 };
2044 struct { /* section for 8723ae */
2045 bool reg_init; /* true if regs saved */
2046 u32 reg_874;
2047 u32 reg_c70;
2048 u32 reg_85c;
2049 u32 reg_a74;
2050 bool bt_operation_on;
2051 };
2052 };
2053 bool enter_ps; /* true when entering PS */
2054 u8 rate_mask[5];
2055
2056 /*This must be the last item so
2057 that it points to the data allocated
2058 beyond this structure like:
2059 rtl_pci_priv or rtl_usb_priv */
2060 u8 priv[0];
2061 };
2062
2063 #define rtl_priv(hw) (((struct rtl_priv *)(hw)->priv))
2064 #define rtl_mac(rtlpriv) (&((rtlpriv)->mac80211))
2065 #define rtl_hal(rtlpriv) (&((rtlpriv)->rtlhal))
2066 #define rtl_efuse(rtlpriv) (&((rtlpriv)->efuse))
2067 #define rtl_psc(rtlpriv) (&((rtlpriv)->psc))
2068
2069
2070 /***************************************
2071 Bluetooth Co-existence Related
2072 ****************************************/
2073
2074 enum bt_ant_num {
2075 ANT_X2 = 0,
2076 ANT_X1 = 1,
2077 };
2078
2079 enum bt_co_type {
2080 BT_2WIRE = 0,
2081 BT_ISSC_3WIRE = 1,
2082 BT_ACCEL = 2,
2083 BT_CSR_BC4 = 3,
2084 BT_CSR_BC8 = 4,
2085 BT_RTL8756 = 5,
2086 BT_RTL8723A = 6,
2087 };
2088
2089 enum bt_cur_state {
2090 BT_OFF = 0,
2091 BT_ON = 1,
2092 };
2093
2094 enum bt_service_type {
2095 BT_SCO = 0,
2096 BT_A2DP = 1,
2097 BT_HID = 2,
2098 BT_HID_IDLE = 3,
2099 BT_SCAN = 4,
2100 BT_IDLE = 5,
2101 BT_OTHER_ACTION = 6,
2102 BT_BUSY = 7,
2103 BT_OTHERBUSY = 8,
2104 BT_PAN = 9,
2105 };
2106
2107 enum bt_radio_shared {
2108 BT_RADIO_SHARED = 0,
2109 BT_RADIO_INDIVIDUAL = 1,
2110 };
2111
2112 struct bt_coexist_info {
2113
2114 /* EEPROM BT info. */
2115 u8 eeprom_bt_coexist;
2116 u8 eeprom_bt_type;
2117 u8 eeprom_bt_ant_num;
2118 u8 eeprom_bt_ant_isol;
2119 u8 eeprom_bt_radio_shared;
2120
2121 u8 bt_coexistence;
2122 u8 bt_ant_num;
2123 u8 bt_coexist_type;
2124 u8 bt_state;
2125 u8 bt_cur_state; /* 0:on, 1:off */
2126 u8 bt_ant_isolation; /* 0:good, 1:bad */
2127 u8 bt_pape_ctrl; /* 0:SW, 1:SW/HW dynamic */
2128 u8 bt_service;
2129 u8 bt_radio_shared_type;
2130 u8 bt_rfreg_origin_1e;
2131 u8 bt_rfreg_origin_1f;
2132 u8 bt_rssi_state;
2133 u32 ratio_tx;
2134 u32 ratio_pri;
2135 u32 bt_edca_ul;
2136 u32 bt_edca_dl;
2137
2138 bool init_set;
2139 bool bt_busy_traffic;
2140 bool bt_traffic_mode_set;
2141 bool bt_non_traffic_mode_set;
2142
2143 bool fw_coexist_all_off;
2144 bool sw_coexist_all_off;
2145 bool hw_coexist_all_off;
2146 u32 cstate;
2147 u32 previous_state;
2148 u32 cstate_h;
2149 u32 previous_state_h;
2150
2151 u8 bt_pre_rssi_state;
2152 u8 bt_pre_rssi_state1;
2153
2154 u8 reg_bt_iso;
2155 u8 reg_bt_sco;
2156 bool balance_on;
2157 u8 bt_active_zero_cnt;
2158 bool cur_bt_disabled;
2159 bool pre_bt_disabled;
2160
2161 u8 bt_profile_case;
2162 u8 bt_profile_action;
2163 bool bt_busy;
2164 bool hold_for_bt_operation;
2165 u8 lps_counter;
2166 };
2167
2168
2169 /****************************************
2170 mem access macro define start
2171 Call endian free function when
2172 1. Read/write packet content.
2173 2. Before write integer to IO.
2174 3. After read integer from IO.
2175 ****************************************/
2176 /* Convert little data endian to host ordering */
2177 #define EF1BYTE(_val) \
2178 ((u8)(_val))
2179 #define EF2BYTE(_val) \
2180 (le16_to_cpu(_val))
2181 #define EF4BYTE(_val) \
2182 (le32_to_cpu(_val))
2183
2184 /* Read data from memory */
2185 #define READEF1BYTE(_ptr) \
2186 EF1BYTE(*((u8 *)(_ptr)))
2187 /* Read le16 data from memory and convert to host ordering */
2188 #define READEF2BYTE(_ptr) \
2189 EF2BYTE(*(_ptr))
2190 #define READEF4BYTE(_ptr) \
2191 EF4BYTE(*(_ptr))
2192
2193 /* Write data to memory */
2194 #define WRITEEF1BYTE(_ptr, _val) \
2195 (*((u8 *)(_ptr))) = EF1BYTE(_val)
2196 /* Write le16 data to memory in host ordering */
2197 #define WRITEEF2BYTE(_ptr, _val) \
2198 (*((u16 *)(_ptr))) = EF2BYTE(_val)
2199 #define WRITEEF4BYTE(_ptr, _val) \
2200 (*((u32 *)(_ptr))) = EF2BYTE(_val)
2201
2202 /* Create a bit mask
2203 * Examples:
2204 * BIT_LEN_MASK_32(0) => 0x00000000
2205 * BIT_LEN_MASK_32(1) => 0x00000001
2206 * BIT_LEN_MASK_32(2) => 0x00000003
2207 * BIT_LEN_MASK_32(32) => 0xFFFFFFFF
2208 */
2209 #define BIT_LEN_MASK_32(__bitlen) \
2210 (0xFFFFFFFF >> (32 - (__bitlen)))
2211 #define BIT_LEN_MASK_16(__bitlen) \
2212 (0xFFFF >> (16 - (__bitlen)))
2213 #define BIT_LEN_MASK_8(__bitlen) \
2214 (0xFF >> (8 - (__bitlen)))
2215
2216 /* Create an offset bit mask
2217 * Examples:
2218 * BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003
2219 * BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000
2220 */
2221 #define BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen) \
2222 (BIT_LEN_MASK_32(__bitlen) << (__bitoffset))
2223 #define BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen) \
2224 (BIT_LEN_MASK_16(__bitlen) << (__bitoffset))
2225 #define BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen) \
2226 (BIT_LEN_MASK_8(__bitlen) << (__bitoffset))
2227
2228 /*Description:
2229 * Return 4-byte value in host byte ordering from
2230 * 4-byte pointer in little-endian system.
2231 */
2232 #define LE_P4BYTE_TO_HOST_4BYTE(__pstart) \
2233 (EF4BYTE(*((__le32 *)(__pstart))))
2234 #define LE_P2BYTE_TO_HOST_2BYTE(__pstart) \
2235 (EF2BYTE(*((__le16 *)(__pstart))))
2236 #define LE_P1BYTE_TO_HOST_1BYTE(__pstart) \
2237 (EF1BYTE(*((u8 *)(__pstart))))
2238
2239 /*Description:
2240 Translate subfield (continuous bits in little-endian) of 4-byte
2241 value to host byte ordering.*/
2242 #define LE_BITS_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
2243 ( \
2244 (LE_P4BYTE_TO_HOST_4BYTE(__pstart) >> (__bitoffset)) & \
2245 BIT_LEN_MASK_32(__bitlen) \
2246 )
2247 #define LE_BITS_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
2248 ( \
2249 (LE_P2BYTE_TO_HOST_2BYTE(__pstart) >> (__bitoffset)) & \
2250 BIT_LEN_MASK_16(__bitlen) \
2251 )
2252 #define LE_BITS_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
2253 ( \
2254 (LE_P1BYTE_TO_HOST_1BYTE(__pstart) >> (__bitoffset)) & \
2255 BIT_LEN_MASK_8(__bitlen) \
2256 )
2257
2258 /* Description:
2259 * Mask subfield (continuous bits in little-endian) of 4-byte value
2260 * and return the result in 4-byte value in host byte ordering.
2261 */
2262 #define LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
2263 ( \
2264 LE_P4BYTE_TO_HOST_4BYTE(__pstart) & \
2265 (~BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen)) \
2266 )
2267 #define LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
2268 ( \
2269 LE_P2BYTE_TO_HOST_2BYTE(__pstart) & \
2270 (~BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen)) \
2271 )
2272 #define LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
2273 ( \
2274 LE_P1BYTE_TO_HOST_1BYTE(__pstart) & \
2275 (~BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen)) \
2276 )
2277
2278 /* Description:
2279 * Set subfield of little-endian 4-byte value to specified value.
2280 */
2281 #define SET_BITS_TO_LE_4BYTE(__pstart, __bitoffset, __bitlen, __val) \
2282 *((u32 *)(__pstart)) = \
2283 ( \
2284 LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) | \
2285 ((((u32)__val) & BIT_LEN_MASK_32(__bitlen)) << (__bitoffset)) \
2286 );
2287 #define SET_BITS_TO_LE_2BYTE(__pstart, __bitoffset, __bitlen, __val) \
2288 *((u16 *)(__pstart)) = \
2289 ( \
2290 LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) | \
2291 ((((u16)__val) & BIT_LEN_MASK_16(__bitlen)) << (__bitoffset)) \
2292 );
2293 #define SET_BITS_TO_LE_1BYTE(__pstart, __bitoffset, __bitlen, __val) \
2294 *((u8 *)(__pstart)) = EF1BYTE \
2295 ( \
2296 LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) | \
2297 ((((u8)__val) & BIT_LEN_MASK_8(__bitlen)) << (__bitoffset)) \
2298 );
2299
2300 #define N_BYTE_ALIGMENT(__value, __aligment) ((__aligment == 1) ? \
2301 (__value) : (((__value + __aligment - 1) / __aligment) * __aligment))
2302
2303 /****************************************
2304 mem access macro define end
2305 ****************************************/
2306
2307 #define byte(x, n) ((x >> (8 * n)) & 0xff)
2308
2309 #define packet_get_type(_packet) (EF1BYTE((_packet).octet[0]) & 0xFC)
2310 #define RTL_WATCH_DOG_TIME 2000
2311 #define MSECS(t) msecs_to_jiffies(t)
2312 #define WLAN_FC_GET_VERS(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_VERS)
2313 #define WLAN_FC_GET_TYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE)
2314 #define WLAN_FC_GET_STYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE)
2315 #define WLAN_FC_MORE_DATA(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_MOREDATA)
2316 #define rtl_dm(rtlpriv) (&((rtlpriv)->dm))
2317
2318 #define RT_RF_OFF_LEVL_ASPM BIT(0) /*PCI ASPM */
2319 #define RT_RF_OFF_LEVL_CLK_REQ BIT(1) /*PCI clock request */
2320 #define RT_RF_OFF_LEVL_PCI_D3 BIT(2) /*PCI D3 mode */
2321 /*NIC halt, re-initialize hw parameters*/
2322 #define RT_RF_OFF_LEVL_HALT_NIC BIT(3)
2323 #define RT_RF_OFF_LEVL_FREE_FW BIT(4) /*FW free, re-download the FW */
2324 #define RT_RF_OFF_LEVL_FW_32K BIT(5) /*FW in 32k */
2325 /*Always enable ASPM and Clock Req in initialization.*/
2326 #define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT(6)
2327 /* no matter RFOFF or SLEEP we set PS_ASPM_LEVL*/
2328 #define RT_PS_LEVEL_ASPM BIT(7)
2329 /*When LPS is on, disable 2R if no packet is received or transmittd.*/
2330 #define RT_RF_LPS_DISALBE_2R BIT(30)
2331 #define RT_RF_LPS_LEVEL_ASPM BIT(31) /*LPS with ASPM */
2332 #define RT_IN_PS_LEVEL(ppsc, _ps_flg) \
2333 ((ppsc->cur_ps_level & _ps_flg) ? true : false)
2334 #define RT_CLEAR_PS_LEVEL(ppsc, _ps_flg) \
2335 (ppsc->cur_ps_level &= (~(_ps_flg)))
2336 #define RT_SET_PS_LEVEL(ppsc, _ps_flg) \
2337 (ppsc->cur_ps_level |= _ps_flg)
2338
2339 #define container_of_dwork_rtl(x, y, z) \
2340 container_of(container_of(x, struct delayed_work, work), y, z)
2341
2342 #define FILL_OCTET_STRING(_os, _octet, _len) \
2343 (_os).octet = (u8 *)(_octet); \
2344 (_os).length = (_len);
2345
2346 #define CP_MACADDR(des, src) \
2347 ((des)[0] = (src)[0], (des)[1] = (src)[1],\
2348 (des)[2] = (src)[2], (des)[3] = (src)[3],\
2349 (des)[4] = (src)[4], (des)[5] = (src)[5])
2350
2351 static inline u8 rtl_read_byte(struct rtl_priv *rtlpriv, u32 addr)
2352 {
2353 return rtlpriv->io.read8_sync(rtlpriv, addr);
2354 }
2355
2356 static inline u16 rtl_read_word(struct rtl_priv *rtlpriv, u32 addr)
2357 {
2358 return rtlpriv->io.read16_sync(rtlpriv, addr);
2359 }
2360
2361 static inline u32 rtl_read_dword(struct rtl_priv *rtlpriv, u32 addr)
2362 {
2363 return rtlpriv->io.read32_sync(rtlpriv, addr);
2364 }
2365
2366 static inline void rtl_write_byte(struct rtl_priv *rtlpriv, u32 addr, u8 val8)
2367 {
2368 rtlpriv->io.write8_async(rtlpriv, addr, val8);
2369
2370 if (rtlpriv->cfg->write_readback)
2371 rtlpriv->io.read8_sync(rtlpriv, addr);
2372 }
2373
2374 static inline void rtl_write_word(struct rtl_priv *rtlpriv, u32 addr, u16 val16)
2375 {
2376 rtlpriv->io.write16_async(rtlpriv, addr, val16);
2377
2378 if (rtlpriv->cfg->write_readback)
2379 rtlpriv->io.read16_sync(rtlpriv, addr);
2380 }
2381
2382 static inline void rtl_write_dword(struct rtl_priv *rtlpriv,
2383 u32 addr, u32 val32)
2384 {
2385 rtlpriv->io.write32_async(rtlpriv, addr, val32);
2386
2387 if (rtlpriv->cfg->write_readback)
2388 rtlpriv->io.read32_sync(rtlpriv, addr);
2389 }
2390
2391 static inline u32 rtl_get_bbreg(struct ieee80211_hw *hw,
2392 u32 regaddr, u32 bitmask)
2393 {
2394 struct rtl_priv *rtlpriv = hw->priv;
2395
2396 return rtlpriv->cfg->ops->get_bbreg(hw, regaddr, bitmask);
2397 }
2398
2399 static inline void rtl_set_bbreg(struct ieee80211_hw *hw, u32 regaddr,
2400 u32 bitmask, u32 data)
2401 {
2402 struct rtl_priv *rtlpriv = hw->priv;
2403
2404 rtlpriv->cfg->ops->set_bbreg(hw, regaddr, bitmask, data);
2405 }
2406
2407 static inline u32 rtl_get_rfreg(struct ieee80211_hw *hw,
2408 enum radio_path rfpath, u32 regaddr,
2409 u32 bitmask)
2410 {
2411 struct rtl_priv *rtlpriv = hw->priv;
2412
2413 return rtlpriv->cfg->ops->get_rfreg(hw, rfpath, regaddr, bitmask);
2414 }
2415
2416 static inline void rtl_set_rfreg(struct ieee80211_hw *hw,
2417 enum radio_path rfpath, u32 regaddr,
2418 u32 bitmask, u32 data)
2419 {
2420 struct rtl_priv *rtlpriv = hw->priv;
2421
2422 rtlpriv->cfg->ops->set_rfreg(hw, rfpath, regaddr, bitmask, data);
2423 }
2424
2425 static inline bool is_hal_stop(struct rtl_hal *rtlhal)
2426 {
2427 return (_HAL_STATE_STOP == rtlhal->state);
2428 }
2429
2430 static inline void set_hal_start(struct rtl_hal *rtlhal)
2431 {
2432 rtlhal->state = _HAL_STATE_START;
2433 }
2434
2435 static inline void set_hal_stop(struct rtl_hal *rtlhal)
2436 {
2437 rtlhal->state = _HAL_STATE_STOP;
2438 }
2439
2440 static inline u8 get_rf_type(struct rtl_phy *rtlphy)
2441 {
2442 return rtlphy->rf_type;
2443 }
2444
2445 static inline struct ieee80211_hdr *rtl_get_hdr(struct sk_buff *skb)
2446 {
2447 return (struct ieee80211_hdr *)(skb->data);
2448 }
2449
2450 static inline __le16 rtl_get_fc(struct sk_buff *skb)
2451 {
2452 return rtl_get_hdr(skb)->frame_control;
2453 }
2454
2455 static inline u16 rtl_get_tid_h(struct ieee80211_hdr *hdr)
2456 {
2457 return (ieee80211_get_qos_ctl(hdr))[0] & IEEE80211_QOS_CTL_TID_MASK;
2458 }
2459
2460 static inline u16 rtl_get_tid(struct sk_buff *skb)
2461 {
2462 return rtl_get_tid_h(rtl_get_hdr(skb));
2463 }
2464
2465 static inline struct ieee80211_sta *get_sta(struct ieee80211_hw *hw,
2466 struct ieee80211_vif *vif,
2467 const u8 *bssid)
2468 {
2469 return ieee80211_find_sta(vif, bssid);
2470 }
2471
2472 static inline struct ieee80211_sta *rtl_find_sta(struct ieee80211_hw *hw,
2473 u8 *mac_addr)
2474 {
2475 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2476 return ieee80211_find_sta(mac->vif, mac_addr);
2477 }
2478
2479 #endif
Linux kernel - Deliverables
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