drivers/net/wireless/ti/wl18xx/acx.h

   1 /*
   2  * This file is part of wl18xx
   3  *
   4  * Copyright (C) 2011 Texas Instruments. All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * version 2 as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  18  * 02110-1301 USA
  19  *
  20  */
  21
  22 #ifndef __WL18XX_ACX_H__
  23 #define __WL18XX_ACX_H__
  24
  25 #include "../wlcore/wlcore.h"
  26 #include "../wlcore/acx.h"
  27
  28 enum {
  29         ACX_CLEAR_STATISTICS             = 0x0047,
  30 };
  31
  32 /* numbers of bits the length field takes (add 1 for the actual number) */
  33 #define WL18XX_HOST_IF_LEN_SIZE_FIELD 15
  34
  35 #define WL18XX_ACX_EVENTS_VECTOR        (WL1271_ACX_INTR_WATCHDOG       | \
  36                                          WL1271_ACX_INTR_INIT_COMPLETE  | \
  37                                          WL1271_ACX_INTR_EVENT_A        | \
  38                                          WL1271_ACX_INTR_EVENT_B        | \
  39                                          WL1271_ACX_INTR_CMD_COMPLETE   | \
  40                                          WL1271_ACX_INTR_HW_AVAILABLE   | \
  41                                          WL1271_ACX_INTR_DATA           | \
  42                                          WL1271_ACX_SW_INTR_WATCHDOG)
  43
  44 #define WL18XX_INTR_MASK                (WL1271_ACX_INTR_WATCHDOG       | \
  45                                          WL1271_ACX_INTR_EVENT_A        | \
  46                                          WL1271_ACX_INTR_EVENT_B        | \
  47                                          WL1271_ACX_INTR_HW_AVAILABLE   | \
  48                                          WL1271_ACX_INTR_DATA           | \
  49                                          WL1271_ACX_SW_INTR_WATCHDOG)
  50
  51 struct wl18xx_acx_host_config_bitmap {
  52         struct acx_header header;
  53
  54         __le32 host_cfg_bitmap;
  55
  56         __le32 host_sdio_block_size;
  57
  58         /* extra mem blocks per frame in TX. */
  59         __le32 extra_mem_blocks;
  60
  61         /*
  62          * number of bits of the length field in the first TX word
  63          * (up to 15 - for using the entire 16 bits).
  64          */
  65         __le32 length_field_size;
  66
  67 } __packed;
  68
  69 enum {
  70         CHECKSUM_OFFLOAD_DISABLED = 0,
  71         CHECKSUM_OFFLOAD_ENABLED  = 1,
  72         CHECKSUM_OFFLOAD_FAKE_RX  = 2,
  73         CHECKSUM_OFFLOAD_INVALID  = 0xFF
  74 };
  75
  76 struct wl18xx_acx_checksum_state {
  77         struct acx_header header;
  78
  79          /* enum acx_checksum_state */
  80         u8 checksum_state;
  81         u8 pad[3];
  82 } __packed;
  83
  84
  85 struct wl18xx_acx_error_stats {
  86         u32 error_frame;
  87         u32 error_null_Frame_tx_start;
  88         u32 error_numll_frame_cts_start;
  89         u32 error_bar_retry;
  90         u32 error_frame_cts_nul_flid;
  91 } __packed;
  92
  93 struct wl18xx_acx_debug_stats {
  94         u32 debug1;
  95         u32 debug2;
  96         u32 debug3;
  97         u32 debug4;
  98         u32 debug5;
  99         u32 debug6;
 100 } __packed;
 101
 102 struct wl18xx_acx_ring_stats {
 103         u32 prepared_descs;
 104         u32 tx_cmplt;
 105 } __packed;
 106
 107 struct wl18xx_acx_tx_stats {
 108         u32 tx_prepared_descs;
 109         u32 tx_cmplt;
 110         u32 tx_template_prepared;
 111         u32 tx_data_prepared;
 112         u32 tx_template_programmed;
 113         u32 tx_data_programmed;
 114         u32 tx_burst_programmed;
 115         u32 tx_starts;
 116         u32 tx_imm_resp;
 117         u32 tx_start_templates;
 118         u32 tx_start_int_templates;
 119         u32 tx_start_fw_gen;
 120         u32 tx_start_data;
 121         u32 tx_start_null_frame;
 122         u32 tx_exch;
 123         u32 tx_retry_template;
 124         u32 tx_retry_data;
 125         u32 tx_exch_pending;
 126         u32 tx_exch_expiry;
 127         u32 tx_done_template;
 128         u32 tx_done_data;
 129         u32 tx_done_int_template;
 130         u32 tx_frame_checksum;
 131         u32 tx_checksum_result;
 132         u32 frag_called;
 133         u32 frag_mpdu_alloc_failed;
 134         u32 frag_init_called;
 135         u32 frag_in_process_called;
 136         u32 frag_tkip_called;
 137         u32 frag_key_not_found;
 138         u32 frag_need_fragmentation;
 139         u32 frag_bad_mblk_num;
 140         u32 frag_failed;
 141         u32 frag_cache_hit;
 142         u32 frag_cache_miss;
 143 } __packed;
 144
 145 struct wl18xx_acx_rx_stats {
 146         u32 rx_beacon_early_term;
 147         u32 rx_out_of_mpdu_nodes;
 148         u32 rx_hdr_overflow;
 149         u32 rx_dropped_frame;
 150         u32 rx_done_stage;
 151         u32 rx_done;
 152         u32 rx_defrag;
 153         u32 rx_defrag_end;
 154         u32 rx_cmplt;
 155         u32 rx_pre_complt;
 156         u32 rx_cmplt_task;
 157         u32 rx_phy_hdr;
 158         u32 rx_timeout;
 159         u32 rx_timeout_wa;
 160         u32 rx_wa_density_dropped_frame;
 161         u32 rx_wa_ba_not_expected;
 162         u32 rx_frame_checksum;
 163         u32 rx_checksum_result;
 164         u32 defrag_called;
 165         u32 defrag_init_called;
 166         u32 defrag_in_process_called;
 167         u32 defrag_tkip_called;
 168         u32 defrag_need_defrag;
 169         u32 defrag_decrypt_failed;
 170         u32 decrypt_key_not_found;
 171         u32 defrag_need_decrypt;
 172         u32 rx_tkip_replays;
 173 } __packed;
 174
 175 struct wl18xx_acx_isr_stats {
 176         u32 irqs;
 177 } __packed;
 178
 179 #define PWR_STAT_MAX_CONT_MISSED_BCNS_SPREAD 10
 180
 181 struct wl18xx_acx_pwr_stats {
 182         u32 missing_bcns_cnt;
 183         u32 rcvd_bcns_cnt;
 184         u32 connection_out_of_sync;
 185         u32 cont_miss_bcns_spread[PWR_STAT_MAX_CONT_MISSED_BCNS_SPREAD];
 186         u32 rcvd_awake_bcns_cnt;
 187 } __packed;
 188
 189 struct wl18xx_acx_event_stats {
 190         u32 calibration;
 191         u32 rx_mismatch;
 192         u32 rx_mem_empty;
 193 } __packed;
 194
 195 struct wl18xx_acx_ps_poll_stats {
 196         u32 ps_poll_timeouts;
 197         u32 upsd_timeouts;
 198         u32 upsd_max_ap_turn;
 199         u32 ps_poll_max_ap_turn;
 200         u32 ps_poll_utilization;
 201         u32 upsd_utilization;
 202 } __packed;
 203
 204 struct wl18xx_acx_rx_filter_stats {
 205         u32 beacon_filter;
 206         u32 arp_filter;
 207         u32 mc_filter;
 208         u32 dup_filter;
 209         u32 data_filter;
 210         u32 ibss_filter;
 211         u32 protection_filter;
 212         u32 accum_arp_pend_requests;
 213         u32 max_arp_queue_dep;
 214 } __packed;
 215
 216 struct wl18xx_acx_rx_rate_stats {
 217         u32 rx_frames_per_rates[50];
 218 } __packed;
 219
 220 #define AGGR_STATS_TX_AGG       16
 221 #define AGGR_STATS_TX_RATE      16
 222 #define AGGR_STATS_RX_SIZE_LEN  16
 223
 224 struct wl18xx_acx_aggr_stats {
 225         u32 tx_agg_vs_rate[AGGR_STATS_TX_AGG * AGGR_STATS_TX_RATE];
 226         u32 rx_size[AGGR_STATS_RX_SIZE_LEN];
 227 } __packed;
 228
 229 #define PIPE_STATS_HW_FIFO      11
 230
 231 struct wl18xx_acx_pipeline_stats {
 232         u32 hs_tx_stat_fifo_int;
 233         u32 hs_rx_stat_fifo_int;
 234         u32 tcp_tx_stat_fifo_int;
 235         u32 tcp_rx_stat_fifo_int;
 236         u32 enc_tx_stat_fifo_int;
 237         u32 enc_rx_stat_fifo_int;
 238         u32 rx_complete_stat_fifo_int;
 239         u32 pre_proc_swi;
 240         u32 post_proc_swi;
 241         u32 sec_frag_swi;
 242         u32 pre_to_defrag_swi;
 243         u32 defrag_to_csum_swi;
 244         u32 csum_to_rx_xfer_swi;
 245         u32 dec_packet_in;
 246         u32 dec_packet_in_fifo_full;
 247         u32 dec_packet_out;
 248         u32 cs_rx_packet_in;
 249         u32 cs_rx_packet_out;
 250         u16 pipeline_fifo_full[PIPE_STATS_HW_FIFO];
 251 } __packed;
 252
 253 struct wl18xx_acx_mem_stats {
 254         u32 rx_free_mem_blks;
 255         u32 tx_free_mem_blks;
 256         u32 fwlog_free_mem_blks;
 257         u32 fw_gen_free_mem_blks;
 258 } __packed;
 259
 260 struct wl18xx_acx_statistics {
 261         struct acx_header header;
 262
 263         struct wl18xx_acx_error_stats           error;
 264         struct wl18xx_acx_debug_stats           debug;
 265         struct wl18xx_acx_tx_stats              tx;
 266         struct wl18xx_acx_rx_stats              rx;
 267         struct wl18xx_acx_isr_stats             isr;
 268         struct wl18xx_acx_pwr_stats             pwr;
 269         struct wl18xx_acx_ps_poll_stats         ps_poll;
 270         struct wl18xx_acx_rx_filter_stats       rx_filter;
 271         struct wl18xx_acx_rx_rate_stats         rx_rate;
 272         struct wl18xx_acx_aggr_stats            aggr_size;
 273         struct wl18xx_acx_pipeline_stats        pipeline;
 274         struct wl18xx_acx_mem_stats             mem;
 275 } __packed;
 276
 277 struct wl18xx_acx_clear_statistics {
 278         struct acx_header header;
 279 };
 280
 281 int wl18xx_acx_host_if_cfg_bitmap(struct wl1271 *wl, u32 host_cfg_bitmap,
 282                                   u32 sdio_blk_size, u32 extra_mem_blks,
 283                                   u32 len_field_size);
 284 int wl18xx_acx_set_checksum_state(struct wl1271 *wl);
 285 int wl18xx_acx_clear_statistics(struct wl1271 *wl);
 286
 287 #endif /* __WL18XX_ACX_H__ */