2 * This file is part of wl18xx
4 * Copyright (C) 2011 Texas Instruments. All rights reserved.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
22 #ifndef __WL18XX_ACX_H__
23 #define __WL18XX_ACX_H__
25 #include "../wlcore/wlcore.h"
26 #include "../wlcore/acx.h"
29 ACX_CLEAR_STATISTICS
= 0x0047,
32 /* numbers of bits the length field takes (add 1 for the actual number) */
33 #define WL18XX_HOST_IF_LEN_SIZE_FIELD 15
35 #define WL18XX_ACX_EVENTS_VECTOR_PG1 (WL1271_ACX_INTR_WATCHDOG | \
36 WL1271_ACX_INTR_INIT_COMPLETE | \
37 WL1271_ACX_INTR_EVENT_A | \
38 WL1271_ACX_INTR_EVENT_B | \
39 WL1271_ACX_INTR_CMD_COMPLETE | \
40 WL1271_ACX_INTR_HW_AVAILABLE | \
43 #define WL18XX_ACX_EVENTS_VECTOR_PG2 (WL18XX_ACX_EVENTS_VECTOR_PG1 | \
44 WL1271_ACX_SW_INTR_WATCHDOG)
46 #define WL18XX_INTR_MASK_PG1 (WL1271_ACX_INTR_WATCHDOG | \
47 WL1271_ACX_INTR_EVENT_A | \
48 WL1271_ACX_INTR_EVENT_B | \
49 WL1271_ACX_INTR_HW_AVAILABLE | \
52 #define WL18XX_INTR_MASK_PG2 (WL18XX_INTR_MASK_PG1 | \
53 WL1271_ACX_SW_INTR_WATCHDOG)
55 struct wl18xx_acx_host_config_bitmap
{
56 struct acx_header header
;
58 __le32 host_cfg_bitmap
;
60 __le32 host_sdio_block_size
;
62 /* extra mem blocks per frame in TX. */
63 __le32 extra_mem_blocks
;
66 * number of bits of the length field in the first TX word
67 * (up to 15 - for using the entire 16 bits).
69 __le32 length_field_size
;
74 CHECKSUM_OFFLOAD_DISABLED
= 0,
75 CHECKSUM_OFFLOAD_ENABLED
= 1,
76 CHECKSUM_OFFLOAD_FAKE_RX
= 2,
77 CHECKSUM_OFFLOAD_INVALID
= 0xFF
80 struct wl18xx_acx_checksum_state
{
81 struct acx_header header
;
83 /* enum acx_checksum_state */
89 struct wl18xx_acx_error_stats
{
91 u32 error_null_Frame_tx_start
;
92 u32 error_numll_frame_cts_start
;
94 u32 error_frame_cts_nul_flid
;
97 struct wl18xx_acx_debug_stats
{
106 struct wl18xx_acx_ring_stats
{
111 struct wl18xx_acx_tx_stats
{
112 u32 tx_prepared_descs
;
114 u32 tx_template_prepared
;
115 u32 tx_data_prepared
;
116 u32 tx_template_programmed
;
117 u32 tx_data_programmed
;
118 u32 tx_burst_programmed
;
121 u32 tx_start_templates
;
122 u32 tx_start_int_templates
;
125 u32 tx_start_null_frame
;
127 u32 tx_retry_template
;
131 u32 tx_done_template
;
133 u32 tx_done_int_template
;
134 u32 tx_frame_checksum
;
135 u32 tx_checksum_result
;
137 u32 frag_mpdu_alloc_failed
;
138 u32 frag_init_called
;
139 u32 frag_in_process_called
;
140 u32 frag_tkip_called
;
141 u32 frag_key_not_found
;
142 u32 frag_need_fragmentation
;
143 u32 frag_bad_mblk_num
;
149 struct wl18xx_acx_rx_stats
{
150 u32 rx_beacon_early_term
;
151 u32 rx_out_of_mpdu_nodes
;
153 u32 rx_dropped_frame
;
164 u32 rx_wa_density_dropped_frame
;
165 u32 rx_wa_ba_not_expected
;
166 u32 rx_frame_checksum
;
167 u32 rx_checksum_result
;
169 u32 defrag_init_called
;
170 u32 defrag_in_process_called
;
171 u32 defrag_tkip_called
;
172 u32 defrag_need_defrag
;
173 u32 defrag_decrypt_failed
;
174 u32 decrypt_key_not_found
;
175 u32 defrag_need_decrypt
;
179 struct wl18xx_acx_isr_stats
{
183 #define PWR_STAT_MAX_CONT_MISSED_BCNS_SPREAD 10
185 struct wl18xx_acx_pwr_stats
{
186 u32 missing_bcns_cnt
;
188 u32 connection_out_of_sync
;
189 u32 cont_miss_bcns_spread
[PWR_STAT_MAX_CONT_MISSED_BCNS_SPREAD
];
190 u32 rcvd_awake_bcns_cnt
;
193 struct wl18xx_acx_event_stats
{
199 struct wl18xx_acx_ps_poll_stats
{
200 u32 ps_poll_timeouts
;
202 u32 upsd_max_ap_turn
;
203 u32 ps_poll_max_ap_turn
;
204 u32 ps_poll_utilization
;
205 u32 upsd_utilization
;
208 struct wl18xx_acx_rx_filter_stats
{
215 u32 protection_filter
;
216 u32 accum_arp_pend_requests
;
217 u32 max_arp_queue_dep
;
220 struct wl18xx_acx_rx_rate_stats
{
221 u32 rx_frames_per_rates
[50];
224 #define AGGR_STATS_TX_AGG 16
225 #define AGGR_STATS_TX_RATE 16
226 #define AGGR_STATS_RX_SIZE_LEN 16
228 struct wl18xx_acx_aggr_stats
{
229 u32 tx_agg_vs_rate
[AGGR_STATS_TX_AGG
* AGGR_STATS_TX_RATE
];
230 u32 rx_size
[AGGR_STATS_RX_SIZE_LEN
];
233 #define PIPE_STATS_HW_FIFO 11
235 struct wl18xx_acx_pipeline_stats
{
236 u32 hs_tx_stat_fifo_int
;
237 u32 hs_rx_stat_fifo_int
;
238 u32 tcp_tx_stat_fifo_int
;
239 u32 tcp_rx_stat_fifo_int
;
240 u32 enc_tx_stat_fifo_int
;
241 u32 enc_rx_stat_fifo_int
;
242 u32 rx_complete_stat_fifo_int
;
246 u32 pre_to_defrag_swi
;
247 u32 defrag_to_csum_swi
;
248 u32 csum_to_rx_xfer_swi
;
250 u32 dec_packet_in_fifo_full
;
253 u32 cs_rx_packet_out
;
254 u16 pipeline_fifo_full
[PIPE_STATS_HW_FIFO
];
257 struct wl18xx_acx_mem_stats
{
258 u32 rx_free_mem_blks
;
259 u32 tx_free_mem_blks
;
260 u32 fwlog_free_mem_blks
;
261 u32 fw_gen_free_mem_blks
;
264 struct wl18xx_acx_statistics
{
265 struct acx_header header
;
267 struct wl18xx_acx_error_stats error
;
268 struct wl18xx_acx_debug_stats debug
;
269 struct wl18xx_acx_tx_stats tx
;
270 struct wl18xx_acx_rx_stats rx
;
271 struct wl18xx_acx_isr_stats isr
;
272 struct wl18xx_acx_pwr_stats pwr
;
273 struct wl18xx_acx_ps_poll_stats ps_poll
;
274 struct wl18xx_acx_rx_filter_stats rx_filter
;
275 struct wl18xx_acx_rx_rate_stats rx_rate
;
276 struct wl18xx_acx_aggr_stats aggr_size
;
277 struct wl18xx_acx_pipeline_stats pipeline
;
278 struct wl18xx_acx_mem_stats mem
;
281 struct wl18xx_acx_clear_statistics
{
282 struct acx_header header
;
285 int wl18xx_acx_host_if_cfg_bitmap(struct wl1271
*wl
, u32 host_cfg_bitmap
,
286 u32 sdio_blk_size
, u32 extra_mem_blks
,
288 int wl18xx_acx_set_checksum_state(struct wl1271
*wl
);
289 int wl18xx_acx_clear_statistics(struct wl1271
*wl
);
291 #endif /* __WL18XX_ACX_H__ */