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6baeb26b79c8731d4ee2e65cc314b7ca083b35e3
[deliverable/linux.git] / drivers / net / wireless / ti / wl18xx / main.c
1 /*
2 * This file is part of wl18xx
3 *
4 * Copyright (C) 2011 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 *
20 */
21
22 #include <linux/module.h>
23 #include <linux/platform_device.h>
24 #include <linux/ip.h>
25
26 #include "../wlcore/wlcore.h"
27 #include "../wlcore/debug.h"
28 #include "../wlcore/io.h"
29 #include "../wlcore/acx.h"
30 #include "../wlcore/tx.h"
31 #include "../wlcore/rx.h"
32 #include "../wlcore/io.h"
33 #include "../wlcore/boot.h"
34
35 #include "reg.h"
36 #include "conf.h"
37 #include "acx.h"
38 #include "tx.h"
39 #include "wl18xx.h"
40 #include "io.h"
41 #include "debugfs.h"
42
43 #define WL18XX_RX_CHECKSUM_MASK 0x40
44
45 static char *ht_mode_param = "wide";
46 static char *board_type_param = "hdk";
47 static bool dc2dc_param = false;
48 static int n_antennas_2_param = 1;
49 static int n_antennas_5_param = 1;
50 static bool checksum_param = true;
51 static bool enable_11a_param = true;
52 static int low_band_component = -1;
53 static int low_band_component_type = -1;
54 static int high_band_component = -1;
55 static int high_band_component_type = -1;
56
57 static const u8 wl18xx_rate_to_idx_2ghz[] = {
58 /* MCS rates are used only with 11n */
59 15, /* WL18XX_CONF_HW_RXTX_RATE_MCS15 */
60 14, /* WL18XX_CONF_HW_RXTX_RATE_MCS14 */
61 13, /* WL18XX_CONF_HW_RXTX_RATE_MCS13 */
62 12, /* WL18XX_CONF_HW_RXTX_RATE_MCS12 */
63 11, /* WL18XX_CONF_HW_RXTX_RATE_MCS11 */
64 10, /* WL18XX_CONF_HW_RXTX_RATE_MCS10 */
65 9, /* WL18XX_CONF_HW_RXTX_RATE_MCS9 */
66 8, /* WL18XX_CONF_HW_RXTX_RATE_MCS8 */
67 7, /* WL18XX_CONF_HW_RXTX_RATE_MCS7 */
68 6, /* WL18XX_CONF_HW_RXTX_RATE_MCS6 */
69 5, /* WL18XX_CONF_HW_RXTX_RATE_MCS5 */
70 4, /* WL18XX_CONF_HW_RXTX_RATE_MCS4 */
71 3, /* WL18XX_CONF_HW_RXTX_RATE_MCS3 */
72 2, /* WL18XX_CONF_HW_RXTX_RATE_MCS2 */
73 1, /* WL18XX_CONF_HW_RXTX_RATE_MCS1 */
74 0, /* WL18XX_CONF_HW_RXTX_RATE_MCS0 */
75
76 11, /* WL18XX_CONF_HW_RXTX_RATE_54 */
77 10, /* WL18XX_CONF_HW_RXTX_RATE_48 */
78 9, /* WL18XX_CONF_HW_RXTX_RATE_36 */
79 8, /* WL18XX_CONF_HW_RXTX_RATE_24 */
80
81 /* TI-specific rate */
82 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_22 */
83
84 7, /* WL18XX_CONF_HW_RXTX_RATE_18 */
85 6, /* WL18XX_CONF_HW_RXTX_RATE_12 */
86 3, /* WL18XX_CONF_HW_RXTX_RATE_11 */
87 5, /* WL18XX_CONF_HW_RXTX_RATE_9 */
88 4, /* WL18XX_CONF_HW_RXTX_RATE_6 */
89 2, /* WL18XX_CONF_HW_RXTX_RATE_5_5 */
90 1, /* WL18XX_CONF_HW_RXTX_RATE_2 */
91 0 /* WL18XX_CONF_HW_RXTX_RATE_1 */
92 };
93
94 static const u8 wl18xx_rate_to_idx_5ghz[] = {
95 /* MCS rates are used only with 11n */
96 15, /* WL18XX_CONF_HW_RXTX_RATE_MCS15 */
97 14, /* WL18XX_CONF_HW_RXTX_RATE_MCS14 */
98 13, /* WL18XX_CONF_HW_RXTX_RATE_MCS13 */
99 12, /* WL18XX_CONF_HW_RXTX_RATE_MCS12 */
100 11, /* WL18XX_CONF_HW_RXTX_RATE_MCS11 */
101 10, /* WL18XX_CONF_HW_RXTX_RATE_MCS10 */
102 9, /* WL18XX_CONF_HW_RXTX_RATE_MCS9 */
103 8, /* WL18XX_CONF_HW_RXTX_RATE_MCS8 */
104 7, /* WL18XX_CONF_HW_RXTX_RATE_MCS7 */
105 6, /* WL18XX_CONF_HW_RXTX_RATE_MCS6 */
106 5, /* WL18XX_CONF_HW_RXTX_RATE_MCS5 */
107 4, /* WL18XX_CONF_HW_RXTX_RATE_MCS4 */
108 3, /* WL18XX_CONF_HW_RXTX_RATE_MCS3 */
109 2, /* WL18XX_CONF_HW_RXTX_RATE_MCS2 */
110 1, /* WL18XX_CONF_HW_RXTX_RATE_MCS1 */
111 0, /* WL18XX_CONF_HW_RXTX_RATE_MCS0 */
112
113 7, /* WL18XX_CONF_HW_RXTX_RATE_54 */
114 6, /* WL18XX_CONF_HW_RXTX_RATE_48 */
115 5, /* WL18XX_CONF_HW_RXTX_RATE_36 */
116 4, /* WL18XX_CONF_HW_RXTX_RATE_24 */
117
118 /* TI-specific rate */
119 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_22 */
120
121 3, /* WL18XX_CONF_HW_RXTX_RATE_18 */
122 2, /* WL18XX_CONF_HW_RXTX_RATE_12 */
123 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_11 */
124 1, /* WL18XX_CONF_HW_RXTX_RATE_9 */
125 0, /* WL18XX_CONF_HW_RXTX_RATE_6 */
126 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_5_5 */
127 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_2 */
128 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_1 */
129 };
130
131 static const u8 *wl18xx_band_rate_to_idx[] = {
132 [IEEE80211_BAND_2GHZ] = wl18xx_rate_to_idx_2ghz,
133 [IEEE80211_BAND_5GHZ] = wl18xx_rate_to_idx_5ghz
134 };
135
136 enum wl18xx_hw_rates {
137 WL18XX_CONF_HW_RXTX_RATE_MCS15 = 0,
138 WL18XX_CONF_HW_RXTX_RATE_MCS14,
139 WL18XX_CONF_HW_RXTX_RATE_MCS13,
140 WL18XX_CONF_HW_RXTX_RATE_MCS12,
141 WL18XX_CONF_HW_RXTX_RATE_MCS11,
142 WL18XX_CONF_HW_RXTX_RATE_MCS10,
143 WL18XX_CONF_HW_RXTX_RATE_MCS9,
144 WL18XX_CONF_HW_RXTX_RATE_MCS8,
145 WL18XX_CONF_HW_RXTX_RATE_MCS7,
146 WL18XX_CONF_HW_RXTX_RATE_MCS6,
147 WL18XX_CONF_HW_RXTX_RATE_MCS5,
148 WL18XX_CONF_HW_RXTX_RATE_MCS4,
149 WL18XX_CONF_HW_RXTX_RATE_MCS3,
150 WL18XX_CONF_HW_RXTX_RATE_MCS2,
151 WL18XX_CONF_HW_RXTX_RATE_MCS1,
152 WL18XX_CONF_HW_RXTX_RATE_MCS0,
153 WL18XX_CONF_HW_RXTX_RATE_54,
154 WL18XX_CONF_HW_RXTX_RATE_48,
155 WL18XX_CONF_HW_RXTX_RATE_36,
156 WL18XX_CONF_HW_RXTX_RATE_24,
157 WL18XX_CONF_HW_RXTX_RATE_22,
158 WL18XX_CONF_HW_RXTX_RATE_18,
159 WL18XX_CONF_HW_RXTX_RATE_12,
160 WL18XX_CONF_HW_RXTX_RATE_11,
161 WL18XX_CONF_HW_RXTX_RATE_9,
162 WL18XX_CONF_HW_RXTX_RATE_6,
163 WL18XX_CONF_HW_RXTX_RATE_5_5,
164 WL18XX_CONF_HW_RXTX_RATE_2,
165 WL18XX_CONF_HW_RXTX_RATE_1,
166 WL18XX_CONF_HW_RXTX_RATE_MAX,
167 };
168
169 static struct wlcore_conf wl18xx_conf = {
170 .sg = {
171 .params = {
172 [CONF_SG_ACL_BT_MASTER_MIN_BR] = 10,
173 [CONF_SG_ACL_BT_MASTER_MAX_BR] = 180,
174 [CONF_SG_ACL_BT_SLAVE_MIN_BR] = 10,
175 [CONF_SG_ACL_BT_SLAVE_MAX_BR] = 180,
176 [CONF_SG_ACL_BT_MASTER_MIN_EDR] = 10,
177 [CONF_SG_ACL_BT_MASTER_MAX_EDR] = 80,
178 [CONF_SG_ACL_BT_SLAVE_MIN_EDR] = 10,
179 [CONF_SG_ACL_BT_SLAVE_MAX_EDR] = 80,
180 [CONF_SG_ACL_WLAN_PS_MASTER_BR] = 8,
181 [CONF_SG_ACL_WLAN_PS_SLAVE_BR] = 8,
182 [CONF_SG_ACL_WLAN_PS_MASTER_EDR] = 20,
183 [CONF_SG_ACL_WLAN_PS_SLAVE_EDR] = 20,
184 [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MIN_BR] = 20,
185 [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MAX_BR] = 35,
186 [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MIN_BR] = 16,
187 [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MAX_BR] = 35,
188 [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MIN_EDR] = 32,
189 [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MAX_EDR] = 50,
190 [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MIN_EDR] = 28,
191 [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MAX_EDR] = 50,
192 [CONF_SG_ACL_ACTIVE_SCAN_WLAN_BR] = 10,
193 [CONF_SG_ACL_ACTIVE_SCAN_WLAN_EDR] = 20,
194 [CONF_SG_ACL_PASSIVE_SCAN_BT_BR] = 75,
195 [CONF_SG_ACL_PASSIVE_SCAN_WLAN_BR] = 15,
196 [CONF_SG_ACL_PASSIVE_SCAN_BT_EDR] = 27,
197 [CONF_SG_ACL_PASSIVE_SCAN_WLAN_EDR] = 17,
198 /* active scan params */
199 [CONF_SG_AUTO_SCAN_PROBE_REQ] = 170,
200 [CONF_SG_ACTIVE_SCAN_DURATION_FACTOR_HV3] = 50,
201 [CONF_SG_ACTIVE_SCAN_DURATION_FACTOR_A2DP] = 100,
202 /* passive scan params */
203 [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_A2DP_BR] = 800,
204 [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_A2DP_EDR] = 200,
205 [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_HV3] = 200,
206 /* passive scan in dual antenna params */
207 [CONF_SG_CONSECUTIVE_HV3_IN_PASSIVE_SCAN] = 0,
208 [CONF_SG_BCN_HV3_COLLISION_THRESH_IN_PASSIVE_SCAN] = 0,
209 [CONF_SG_TX_RX_PROTECTION_BWIDTH_IN_PASSIVE_SCAN] = 0,
210 /* general params */
211 [CONF_SG_STA_FORCE_PS_IN_BT_SCO] = 1,
212 [CONF_SG_ANTENNA_CONFIGURATION] = 0,
213 [CONF_SG_BEACON_MISS_PERCENT] = 60,
214 [CONF_SG_DHCP_TIME] = 5000,
215 [CONF_SG_RXT] = 1200,
216 [CONF_SG_TXT] = 1000,
217 [CONF_SG_ADAPTIVE_RXT_TXT] = 1,
218 [CONF_SG_GENERAL_USAGE_BIT_MAP] = 3,
219 [CONF_SG_HV3_MAX_SERVED] = 6,
220 [CONF_SG_PS_POLL_TIMEOUT] = 10,
221 [CONF_SG_UPSD_TIMEOUT] = 10,
222 [CONF_SG_CONSECUTIVE_CTS_THRESHOLD] = 2,
223 [CONF_SG_STA_RX_WINDOW_AFTER_DTIM] = 5,
224 [CONF_SG_STA_CONNECTION_PROTECTION_TIME] = 30,
225 /* AP params */
226 [CONF_AP_BEACON_MISS_TX] = 3,
227 [CONF_AP_RX_WINDOW_AFTER_BEACON] = 10,
228 [CONF_AP_BEACON_WINDOW_INTERVAL] = 2,
229 [CONF_AP_CONNECTION_PROTECTION_TIME] = 0,
230 [CONF_AP_BT_ACL_VAL_BT_SERVE_TIME] = 25,
231 [CONF_AP_BT_ACL_VAL_WL_SERVE_TIME] = 25,
232 /* CTS Diluting params */
233 [CONF_SG_CTS_DILUTED_BAD_RX_PACKETS_TH] = 0,
234 [CONF_SG_CTS_CHOP_IN_DUAL_ANT_SCO_MASTER] = 0,
235 },
236 .state = CONF_SG_PROTECTIVE,
237 },
238 .rx = {
239 .rx_msdu_life_time = 512000,
240 .packet_detection_threshold = 0,
241 .ps_poll_timeout = 15,
242 .upsd_timeout = 15,
243 .rts_threshold = IEEE80211_MAX_RTS_THRESHOLD,
244 .rx_cca_threshold = 0,
245 .irq_blk_threshold = 0xFFFF,
246 .irq_pkt_threshold = 0,
247 .irq_timeout = 600,
248 .queue_type = CONF_RX_QUEUE_TYPE_LOW_PRIORITY,
249 },
250 .tx = {
251 .tx_energy_detection = 0,
252 .sta_rc_conf = {
253 .enabled_rates = 0,
254 .short_retry_limit = 10,
255 .long_retry_limit = 10,
256 .aflags = 0,
257 },
258 .ac_conf_count = 4,
259 .ac_conf = {
260 [CONF_TX_AC_BE] = {
261 .ac = CONF_TX_AC_BE,
262 .cw_min = 15,
263 .cw_max = 63,
264 .aifsn = 3,
265 .tx_op_limit = 0,
266 },
267 [CONF_TX_AC_BK] = {
268 .ac = CONF_TX_AC_BK,
269 .cw_min = 15,
270 .cw_max = 63,
271 .aifsn = 7,
272 .tx_op_limit = 0,
273 },
274 [CONF_TX_AC_VI] = {
275 .ac = CONF_TX_AC_VI,
276 .cw_min = 15,
277 .cw_max = 63,
278 .aifsn = CONF_TX_AIFS_PIFS,
279 .tx_op_limit = 3008,
280 },
281 [CONF_TX_AC_VO] = {
282 .ac = CONF_TX_AC_VO,
283 .cw_min = 15,
284 .cw_max = 63,
285 .aifsn = CONF_TX_AIFS_PIFS,
286 .tx_op_limit = 1504,
287 },
288 },
289 .max_tx_retries = 100,
290 .ap_aging_period = 300,
291 .tid_conf_count = 4,
292 .tid_conf = {
293 [CONF_TX_AC_BE] = {
294 .queue_id = CONF_TX_AC_BE,
295 .channel_type = CONF_CHANNEL_TYPE_EDCF,
296 .tsid = CONF_TX_AC_BE,
297 .ps_scheme = CONF_PS_SCHEME_LEGACY,
298 .ack_policy = CONF_ACK_POLICY_LEGACY,
299 .apsd_conf = {0, 0},
300 },
301 [CONF_TX_AC_BK] = {
302 .queue_id = CONF_TX_AC_BK,
303 .channel_type = CONF_CHANNEL_TYPE_EDCF,
304 .tsid = CONF_TX_AC_BK,
305 .ps_scheme = CONF_PS_SCHEME_LEGACY,
306 .ack_policy = CONF_ACK_POLICY_LEGACY,
307 .apsd_conf = {0, 0},
308 },
309 [CONF_TX_AC_VI] = {
310 .queue_id = CONF_TX_AC_VI,
311 .channel_type = CONF_CHANNEL_TYPE_EDCF,
312 .tsid = CONF_TX_AC_VI,
313 .ps_scheme = CONF_PS_SCHEME_LEGACY,
314 .ack_policy = CONF_ACK_POLICY_LEGACY,
315 .apsd_conf = {0, 0},
316 },
317 [CONF_TX_AC_VO] = {
318 .queue_id = CONF_TX_AC_VO,
319 .channel_type = CONF_CHANNEL_TYPE_EDCF,
320 .tsid = CONF_TX_AC_VO,
321 .ps_scheme = CONF_PS_SCHEME_LEGACY,
322 .ack_policy = CONF_ACK_POLICY_LEGACY,
323 .apsd_conf = {0, 0},
324 },
325 },
326 .frag_threshold = IEEE80211_MAX_FRAG_THRESHOLD,
327 .tx_compl_timeout = 350,
328 .tx_compl_threshold = 10,
329 .basic_rate = CONF_HW_BIT_RATE_1MBPS,
330 .basic_rate_5 = CONF_HW_BIT_RATE_6MBPS,
331 .tmpl_short_retry_limit = 10,
332 .tmpl_long_retry_limit = 10,
333 .tx_watchdog_timeout = 5000,
334 },
335 .conn = {
336 .wake_up_event = CONF_WAKE_UP_EVENT_DTIM,
337 .listen_interval = 1,
338 .suspend_wake_up_event = CONF_WAKE_UP_EVENT_N_DTIM,
339 .suspend_listen_interval = 3,
340 .bcn_filt_mode = CONF_BCN_FILT_MODE_ENABLED,
341 .bcn_filt_ie_count = 2,
342 .bcn_filt_ie = {
343 [0] = {
344 .ie = WLAN_EID_CHANNEL_SWITCH,
345 .rule = CONF_BCN_RULE_PASS_ON_APPEARANCE,
346 },
347 [1] = {
348 .ie = WLAN_EID_HT_OPERATION,
349 .rule = CONF_BCN_RULE_PASS_ON_CHANGE,
350 },
351 },
352 .synch_fail_thold = 10,
353 .bss_lose_timeout = 100,
354 .beacon_rx_timeout = 10000,
355 .broadcast_timeout = 20000,
356 .rx_broadcast_in_ps = 1,
357 .ps_poll_threshold = 10,
358 .bet_enable = CONF_BET_MODE_ENABLE,
359 .bet_max_consecutive = 50,
360 .psm_entry_retries = 8,
361 .psm_exit_retries = 16,
362 .psm_entry_nullfunc_retries = 3,
363 .dynamic_ps_timeout = 40,
364 .forced_ps = false,
365 .keep_alive_interval = 55000,
366 .max_listen_interval = 20,
367 },
368 .itrim = {
369 .enable = false,
370 .timeout = 50000,
371 },
372 .pm_config = {
373 .host_clk_settling_time = 5000,
374 .host_fast_wakeup_support = false
375 },
376 .roam_trigger = {
377 .trigger_pacing = 1,
378 .avg_weight_rssi_beacon = 20,
379 .avg_weight_rssi_data = 10,
380 .avg_weight_snr_beacon = 20,
381 .avg_weight_snr_data = 10,
382 },
383 .scan = {
384 .min_dwell_time_active = 7500,
385 .max_dwell_time_active = 30000,
386 .min_dwell_time_passive = 100000,
387 .max_dwell_time_passive = 100000,
388 .num_probe_reqs = 2,
389 .split_scan_timeout = 50000,
390 },
391 .sched_scan = {
392 /*
393 * Values are in TU/1000 but since sched scan FW command
394 * params are in TUs rounding up may occur.
395 */
396 .base_dwell_time = 7500,
397 .max_dwell_time_delta = 22500,
398 /* based on 250bits per probe @1Mbps */
399 .dwell_time_delta_per_probe = 2000,
400 /* based on 250bits per probe @6Mbps (plus a bit more) */
401 .dwell_time_delta_per_probe_5 = 350,
402 .dwell_time_passive = 100000,
403 .dwell_time_dfs = 150000,
404 .num_probe_reqs = 2,
405 .rssi_threshold = -90,
406 .snr_threshold = 0,
407 },
408 .ht = {
409 .rx_ba_win_size = 10,
410 .tx_ba_win_size = 10,
411 .inactivity_timeout = 10000,
412 .tx_ba_tid_bitmap = CONF_TX_BA_ENABLED_TID_BITMAP,
413 },
414 .mem = {
415 .num_stations = 1,
416 .ssid_profiles = 1,
417 .rx_block_num = 40,
418 .tx_min_block_num = 40,
419 .dynamic_memory = 1,
420 .min_req_tx_blocks = 45,
421 .min_req_rx_blocks = 22,
422 .tx_min = 27,
423 },
424 .fm_coex = {
425 .enable = true,
426 .swallow_period = 5,
427 .n_divider_fref_set_1 = 0xff, /* default */
428 .n_divider_fref_set_2 = 12,
429 .m_divider_fref_set_1 = 148,
430 .m_divider_fref_set_2 = 0xffff, /* default */
431 .coex_pll_stabilization_time = 0xffffffff, /* default */
432 .ldo_stabilization_time = 0xffff, /* default */
433 .fm_disturbed_band_margin = 0xff, /* default */
434 .swallow_clk_diff = 0xff, /* default */
435 },
436 .rx_streaming = {
437 .duration = 150,
438 .queues = 0x1,
439 .interval = 20,
440 .always = 0,
441 },
442 .fwlog = {
443 .mode = WL12XX_FWLOG_ON_DEMAND,
444 .mem_blocks = 2,
445 .severity = 0,
446 .timestamp = WL12XX_FWLOG_TIMESTAMP_DISABLED,
447 .output = WL12XX_FWLOG_OUTPUT_HOST,
448 .threshold = 0,
449 },
450 .rate = {
451 .rate_retry_score = 32000,
452 .per_add = 8192,
453 .per_th1 = 2048,
454 .per_th2 = 4096,
455 .max_per = 8100,
456 .inverse_curiosity_factor = 5,
457 .tx_fail_low_th = 4,
458 .tx_fail_high_th = 10,
459 .per_alpha_shift = 4,
460 .per_add_shift = 13,
461 .per_beta1_shift = 10,
462 .per_beta2_shift = 8,
463 .rate_check_up = 2,
464 .rate_check_down = 12,
465 .rate_retry_policy = {
466 0x00, 0x00, 0x00, 0x00, 0x00,
467 0x00, 0x00, 0x00, 0x00, 0x00,
468 0x00, 0x00, 0x00,
469 },
470 },
471 .hangover = {
472 .recover_time = 0,
473 .hangover_period = 20,
474 .dynamic_mode = 1,
475 .early_termination_mode = 1,
476 .max_period = 20,
477 .min_period = 1,
478 .increase_delta = 1,
479 .decrease_delta = 2,
480 .quiet_time = 4,
481 .increase_time = 1,
482 .window_size = 16,
483 },
484 };
485
486 static struct wl18xx_priv_conf wl18xx_default_priv_conf = {
487 .phy = {
488 .phy_standalone = 0x00,
489 .primary_clock_setting_time = 0x05,
490 .clock_valid_on_wake_up = 0x00,
491 .secondary_clock_setting_time = 0x05,
492 .rdl = 0x01,
493 .auto_detect = 0x00,
494 .dedicated_fem = FEM_NONE,
495 .low_band_component = COMPONENT_2_WAY_SWITCH,
496 .low_band_component_type = 0x05,
497 .high_band_component = COMPONENT_2_WAY_SWITCH,
498 .high_band_component_type = 0x09,
499 .tcxo_ldo_voltage = 0x00,
500 .xtal_itrim_val = 0x04,
501 .srf_state = 0x00,
502 .io_configuration = 0x01,
503 .sdio_configuration = 0x00,
504 .settings = 0x00,
505 .enable_clpc = 0x00,
506 .enable_tx_low_pwr_on_siso_rdl = 0x00,
507 .rx_profile = 0x00,
508 .pwr_limit_reference_11_abg = 0xc8,
509 },
510 };
511
512 static const struct wlcore_partition_set wl18xx_ptable[PART_TABLE_LEN] = {
513 [PART_TOP_PRCM_ELP_SOC] = {
514 .mem = { .start = 0x00A02000, .size = 0x00010000 },
515 .reg = { .start = 0x00807000, .size = 0x00005000 },
516 .mem2 = { .start = 0x00800000, .size = 0x0000B000 },
517 .mem3 = { .start = 0x00000000, .size = 0x00000000 },
518 },
519 [PART_DOWN] = {
520 .mem = { .start = 0x00000000, .size = 0x00014000 },
521 .reg = { .start = 0x00810000, .size = 0x0000BFFF },
522 .mem2 = { .start = 0x00000000, .size = 0x00000000 },
523 .mem3 = { .start = 0x00000000, .size = 0x00000000 },
524 },
525 [PART_BOOT] = {
526 .mem = { .start = 0x00700000, .size = 0x0000030c },
527 .reg = { .start = 0x00802000, .size = 0x00014578 },
528 .mem2 = { .start = 0x00B00404, .size = 0x00001000 },
529 .mem3 = { .start = 0x00C00000, .size = 0x00000400 },
530 },
531 [PART_WORK] = {
532 .mem = { .start = 0x00800000, .size = 0x000050FC },
533 .reg = { .start = 0x00B00404, .size = 0x00001000 },
534 .mem2 = { .start = 0x00C00000, .size = 0x00000400 },
535 .mem3 = { .start = 0x00000000, .size = 0x00000000 },
536 },
537 [PART_PHY_INIT] = {
538 /* TODO: use the phy_conf struct size here */
539 .mem = { .start = 0x80926000, .size = 252 },
540 .reg = { .start = 0x00000000, .size = 0x00000000 },
541 .mem2 = { .start = 0x00000000, .size = 0x00000000 },
542 .mem3 = { .start = 0x00000000, .size = 0x00000000 },
543 },
544 };
545
546 static const int wl18xx_rtable[REG_TABLE_LEN] = {
547 [REG_ECPU_CONTROL] = WL18XX_REG_ECPU_CONTROL,
548 [REG_INTERRUPT_NO_CLEAR] = WL18XX_REG_INTERRUPT_NO_CLEAR,
549 [REG_INTERRUPT_ACK] = WL18XX_REG_INTERRUPT_ACK,
550 [REG_COMMAND_MAILBOX_PTR] = WL18XX_REG_COMMAND_MAILBOX_PTR,
551 [REG_EVENT_MAILBOX_PTR] = WL18XX_REG_EVENT_MAILBOX_PTR,
552 [REG_INTERRUPT_TRIG] = WL18XX_REG_INTERRUPT_TRIG_H,
553 [REG_INTERRUPT_MASK] = WL18XX_REG_INTERRUPT_MASK,
554 [REG_PC_ON_RECOVERY] = WL18XX_SCR_PAD4,
555 [REG_CHIP_ID_B] = WL18XX_REG_CHIP_ID_B,
556 [REG_CMD_MBOX_ADDRESS] = WL18XX_CMD_MBOX_ADDRESS,
557
558 /* data access memory addresses, used with partition translation */
559 [REG_SLV_MEM_DATA] = WL18XX_SLV_MEM_DATA,
560 [REG_SLV_REG_DATA] = WL18XX_SLV_REG_DATA,
561
562 /* raw data access memory addresses */
563 [REG_RAW_FW_STATUS_ADDR] = WL18XX_FW_STATUS_ADDR,
564 };
565
566 static const struct wl18xx_clk_cfg wl18xx_clk_table[NUM_CLOCK_CONFIGS] = {
567 [CLOCK_CONFIG_16_2_M] = { 7, 104, 801, 4, true },
568 [CLOCK_CONFIG_16_368_M] = { 9, 132, 3751, 4, true },
569 [CLOCK_CONFIG_16_8_M] = { 7, 100, 0, 0, false },
570 [CLOCK_CONFIG_19_2_M] = { 8, 100, 0, 0, false },
571 [CLOCK_CONFIG_26_M] = { 13, 120, 0, 0, false },
572 [CLOCK_CONFIG_32_736_M] = { 9, 132, 3751, 4, true },
573 [CLOCK_CONFIG_33_6_M] = { 7, 100, 0, 0, false },
574 [CLOCK_CONFIG_38_468_M] = { 8, 100, 0, 0, false },
575 [CLOCK_CONFIG_52_M] = { 13, 120, 0, 0, false },
576 };
577
578 /* TODO: maybe move to a new header file? */
579 #define WL18XX_FW_NAME "ti-connectivity/wl18xx-fw.bin"
580
581 static int wl18xx_identify_chip(struct wl1271 *wl)
582 {
583 int ret = 0;
584
585 switch (wl->chip.id) {
586 case CHIP_ID_185x_PG10:
587 wl1271_debug(DEBUG_BOOT, "chip id 0x%x (185x PG10)",
588 wl->chip.id);
589 wl->sr_fw_name = WL18XX_FW_NAME;
590 /* wl18xx uses the same firmware for PLT */
591 wl->plt_fw_name = WL18XX_FW_NAME;
592 wl->quirks |= WLCORE_QUIRK_NO_ELP |
593 WLCORE_QUIRK_FWLOG_NOT_IMPLEMENTED |
594 WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN;
595
596 /* PG 1.0 has some problems with MCS_13, so disable it */
597 wl->ht_cap.mcs.rx_mask[1] &= ~BIT(5);
598
599 /* TODO: need to blocksize alignment for RX/TX separately? */
600 break;
601 default:
602 wl1271_warning("unsupported chip id: 0x%x", wl->chip.id);
603 ret = -ENODEV;
604 goto out;
605 }
606
607 out:
608 return ret;
609 }
610
611 static void wl18xx_set_clk(struct wl1271 *wl)
612 {
613 u32 clk_freq;
614
615 wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]);
616
617 /* TODO: PG2: apparently we need to read the clk type */
618
619 clk_freq = wl18xx_top_reg_read(wl, PRIMARY_CLK_DETECT);
620 wl1271_debug(DEBUG_BOOT, "clock freq %d (%d, %d, %d, %d, %s)", clk_freq,
621 wl18xx_clk_table[clk_freq].n, wl18xx_clk_table[clk_freq].m,
622 wl18xx_clk_table[clk_freq].p, wl18xx_clk_table[clk_freq].q,
623 wl18xx_clk_table[clk_freq].swallow ? "swallow" : "spit");
624
625 wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_N, wl18xx_clk_table[clk_freq].n);
626 wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_M, wl18xx_clk_table[clk_freq].m);
627
628 if (wl18xx_clk_table[clk_freq].swallow) {
629 /* first the 16 lower bits */
630 wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_Q_FACTOR_CFG_1,
631 wl18xx_clk_table[clk_freq].q &
632 PLLSH_WCS_PLL_Q_FACTOR_CFG_1_MASK);
633 /* then the 16 higher bits, masked out */
634 wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_Q_FACTOR_CFG_2,
635 (wl18xx_clk_table[clk_freq].q >> 16) &
636 PLLSH_WCS_PLL_Q_FACTOR_CFG_2_MASK);
637
638 /* first the 16 lower bits */
639 wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_P_FACTOR_CFG_1,
640 wl18xx_clk_table[clk_freq].p &
641 PLLSH_WCS_PLL_P_FACTOR_CFG_1_MASK);
642 /* then the 16 higher bits, masked out */
643 wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_P_FACTOR_CFG_2,
644 (wl18xx_clk_table[clk_freq].p >> 16) &
645 PLLSH_WCS_PLL_P_FACTOR_CFG_2_MASK);
646 } else {
647 wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_SWALLOW_EN,
648 PLLSH_WCS_PLL_SWALLOW_EN_VAL2);
649 }
650 }
651
652 static void wl18xx_boot_soft_reset(struct wl1271 *wl)
653 {
654 /* disable Rx/Tx */
655 wl1271_write32(wl, WL18XX_ENABLE, 0x0);
656
657 /* disable auto calibration on start*/
658 wl1271_write32(wl, WL18XX_SPARE_A2, 0xffff);
659 }
660
661 static int wl18xx_pre_boot(struct wl1271 *wl)
662 {
663 wl18xx_set_clk(wl);
664
665 /* Continue the ELP wake up sequence */
666 wl1271_write32(wl, WL18XX_WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
667 udelay(500);
668
669 wlcore_set_partition(wl, &wl->ptable[PART_BOOT]);
670
671 /* Disable interrupts */
672 wlcore_write_reg(wl, REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL);
673
674 wl18xx_boot_soft_reset(wl);
675
676 return 0;
677 }
678
679 static void wl18xx_pre_upload(struct wl1271 *wl)
680 {
681 u32 tmp;
682
683 wlcore_set_partition(wl, &wl->ptable[PART_BOOT]);
684
685 /* TODO: check if this is all needed */
686 wl1271_write32(wl, WL18XX_EEPROMLESS_IND, WL18XX_EEPROMLESS_IND);
687
688 tmp = wlcore_read_reg(wl, REG_CHIP_ID_B);
689
690 wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp);
691
692 tmp = wl1271_read32(wl, WL18XX_SCR_PAD2);
693 }
694
695 static void wl18xx_set_mac_and_phy(struct wl1271 *wl)
696 {
697 struct wl18xx_priv *priv = wl->priv;
698 struct wl18xx_conf_phy *phy = &priv->conf.phy;
699 struct wl18xx_mac_and_phy_params params;
700
701 memset(&params, 0, sizeof(params));
702
703 params.phy_standalone = phy->phy_standalone;
704 params.rdl = phy->rdl;
705 params.enable_clpc = phy->enable_clpc;
706 params.enable_tx_low_pwr_on_siso_rdl =
707 phy->enable_tx_low_pwr_on_siso_rdl;
708 params.auto_detect = phy->auto_detect;
709 params.dedicated_fem = phy->dedicated_fem;
710 params.low_band_component = phy->low_band_component;
711 params.low_band_component_type =
712 phy->low_band_component_type;
713 params.high_band_component = phy->high_band_component;
714 params.high_band_component_type =
715 phy->high_band_component_type;
716 params.number_of_assembled_ant2_4 =
717 n_antennas_2_param;
718 params.number_of_assembled_ant5 =
719 n_antennas_5_param;
720 params.external_pa_dc2dc = dc2dc_param;
721 params.tcxo_ldo_voltage = phy->tcxo_ldo_voltage;
722 params.xtal_itrim_val = phy->xtal_itrim_val;
723 params.srf_state = phy->srf_state;
724 params.io_configuration = phy->io_configuration;
725 params.sdio_configuration = phy->sdio_configuration;
726 params.settings = phy->settings;
727 params.rx_profile = phy->rx_profile;
728 params.primary_clock_setting_time =
729 phy->primary_clock_setting_time;
730 params.clock_valid_on_wake_up =
731 phy->clock_valid_on_wake_up;
732 params.secondary_clock_setting_time =
733 phy->secondary_clock_setting_time;
734 params.pwr_limit_reference_11_abg =
735 phy->pwr_limit_reference_11_abg;
736
737 params.board_type = priv->board_type;
738
739 wlcore_set_partition(wl, &wl->ptable[PART_PHY_INIT]);
740 wl1271_write(wl, WL18XX_PHY_INIT_MEM_ADDR, (u8 *)&params,
741 sizeof(params), false);
742 }
743
744 static void wl18xx_enable_interrupts(struct wl1271 *wl)
745 {
746 wlcore_write_reg(wl, REG_INTERRUPT_MASK, WL1271_ACX_ALL_EVENTS_VECTOR);
747
748 wlcore_enable_interrupts(wl);
749 wlcore_write_reg(wl, REG_INTERRUPT_MASK,
750 WL1271_ACX_INTR_ALL & ~(WL1271_INTR_MASK));
751 }
752
753 static int wl18xx_boot(struct wl1271 *wl)
754 {
755 int ret;
756
757 ret = wl18xx_pre_boot(wl);
758 if (ret < 0)
759 goto out;
760
761 wl18xx_pre_upload(wl);
762
763 ret = wlcore_boot_upload_firmware(wl);
764 if (ret < 0)
765 goto out;
766
767 wl18xx_set_mac_and_phy(wl);
768
769 ret = wlcore_boot_run_firmware(wl);
770 if (ret < 0)
771 goto out;
772
773 wl18xx_enable_interrupts(wl);
774
775 out:
776 return ret;
777 }
778
779 static void wl18xx_trigger_cmd(struct wl1271 *wl, int cmd_box_addr,
780 void *buf, size_t len)
781 {
782 struct wl18xx_priv *priv = wl->priv;
783
784 memcpy(priv->cmd_buf, buf, len);
785 memset(priv->cmd_buf + len, 0, WL18XX_CMD_MAX_SIZE - len);
786
787 wl1271_write(wl, cmd_box_addr, priv->cmd_buf, WL18XX_CMD_MAX_SIZE,
788 false);
789 }
790
791 static void wl18xx_ack_event(struct wl1271 *wl)
792 {
793 wlcore_write_reg(wl, REG_INTERRUPT_TRIG, WL18XX_INTR_TRIG_EVENT_ACK);
794 }
795
796 static u32 wl18xx_calc_tx_blocks(struct wl1271 *wl, u32 len, u32 spare_blks)
797 {
798 u32 blk_size = WL18XX_TX_HW_BLOCK_SIZE;
799 return (len + blk_size - 1) / blk_size + spare_blks;
800 }
801
802 static void
803 wl18xx_set_tx_desc_blocks(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc,
804 u32 blks, u32 spare_blks)
805 {
806 desc->wl18xx_mem.total_mem_blocks = blks;
807 desc->wl18xx_mem.reserved = 0;
808 }
809
810 static void
811 wl18xx_set_tx_desc_data_len(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc,
812 struct sk_buff *skb)
813 {
814 desc->length = cpu_to_le16(skb->len);
815
816 wl1271_debug(DEBUG_TX, "tx_fill_hdr: hlid: %d "
817 "len: %d life: %d mem: %d", desc->hlid,
818 le16_to_cpu(desc->length),
819 le16_to_cpu(desc->life_time),
820 desc->wl18xx_mem.total_mem_blocks);
821 }
822
823 static enum wl_rx_buf_align
824 wl18xx_get_rx_buf_align(struct wl1271 *wl, u32 rx_desc)
825 {
826 if (rx_desc & RX_BUF_PADDED_PAYLOAD)
827 return WLCORE_RX_BUF_PADDED;
828
829 return WLCORE_RX_BUF_ALIGNED;
830 }
831
832 static u32 wl18xx_get_rx_packet_len(struct wl1271 *wl, void *rx_data,
833 u32 data_len)
834 {
835 struct wl1271_rx_descriptor *desc = rx_data;
836
837 /* invalid packet */
838 if (data_len < sizeof(*desc))
839 return 0;
840
841 return data_len - sizeof(*desc);
842 }
843
844 static void wl18xx_tx_immediate_completion(struct wl1271 *wl)
845 {
846 wl18xx_tx_immediate_complete(wl);
847 }
848
849 static int wl18xx_hw_init(struct wl1271 *wl)
850 {
851 int ret;
852 struct wl18xx_priv *priv = wl->priv;
853 u32 host_cfg_bitmap = HOST_IF_CFG_RX_FIFO_ENABLE |
854 HOST_IF_CFG_ADD_RX_ALIGNMENT;
855
856 u32 sdio_align_size = 0;
857
858 /* (re)init private structures. Relevant on recovery as well. */
859 priv->last_fw_rls_idx = 0;
860
861 /* Enable Tx SDIO padding */
862 if (wl->quirks & WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN) {
863 host_cfg_bitmap |= HOST_IF_CFG_TX_PAD_TO_SDIO_BLK;
864 sdio_align_size = WL12XX_BUS_BLOCK_SIZE;
865 }
866
867 /* Enable Rx SDIO padding */
868 if (wl->quirks & WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN) {
869 host_cfg_bitmap |= HOST_IF_CFG_RX_PAD_TO_SDIO_BLK;
870 sdio_align_size = WL12XX_BUS_BLOCK_SIZE;
871 }
872
873 ret = wl18xx_acx_host_if_cfg_bitmap(wl, host_cfg_bitmap,
874 sdio_align_size,
875 WL18XX_TX_HW_BLOCK_SPARE,
876 WL18XX_HOST_IF_LEN_SIZE_FIELD);
877 if (ret < 0)
878 return ret;
879
880 if (checksum_param) {
881 ret = wl18xx_acx_set_checksum_state(wl);
882 if (ret != 0)
883 return ret;
884 }
885
886 return ret;
887 }
888
889 static void wl18xx_set_tx_desc_csum(struct wl1271 *wl,
890 struct wl1271_tx_hw_descr *desc,
891 struct sk_buff *skb)
892 {
893 u32 ip_hdr_offset;
894 struct iphdr *ip_hdr;
895
896 if (!checksum_param) {
897 desc->wl18xx_checksum_data = 0;
898 return;
899 }
900
901 if (skb->ip_summed != CHECKSUM_PARTIAL) {
902 desc->wl18xx_checksum_data = 0;
903 return;
904 }
905
906 ip_hdr_offset = skb_network_header(skb) - skb_mac_header(skb);
907 if (WARN_ON(ip_hdr_offset >= (1<<7))) {
908 desc->wl18xx_checksum_data = 0;
909 return;
910 }
911
912 desc->wl18xx_checksum_data = ip_hdr_offset << 1;
913
914 /* FW is interested only in the LSB of the protocol TCP=0 UDP=1 */
915 ip_hdr = (void *)skb_network_header(skb);
916 desc->wl18xx_checksum_data |= (ip_hdr->protocol & 0x01);
917 }
918
919 static void wl18xx_set_rx_csum(struct wl1271 *wl,
920 struct wl1271_rx_descriptor *desc,
921 struct sk_buff *skb)
922 {
923 if (desc->status & WL18XX_RX_CHECKSUM_MASK)
924 skb->ip_summed = CHECKSUM_UNNECESSARY;
925 }
926
927 /*
928 * TODO: instead of having these two functions to get the rate mask,
929 * we should modify the wlvif->rate_set instead
930 */
931 static u32 wl18xx_sta_get_ap_rate_mask(struct wl1271 *wl,
932 struct wl12xx_vif *wlvif)
933 {
934 u32 hw_rate_set = wlvif->rate_set;
935
936 if (wlvif->channel_type == NL80211_CHAN_HT40MINUS ||
937 wlvif->channel_type == NL80211_CHAN_HT40PLUS) {
938 wl1271_debug(DEBUG_ACX, "using wide channel rate mask");
939 hw_rate_set |= CONF_TX_RATE_USE_WIDE_CHAN;
940
941 /* we don't support MIMO in wide-channel mode */
942 hw_rate_set &= ~CONF_TX_MIMO_RATES;
943 }
944
945 return hw_rate_set;
946 }
947
948 static u32 wl18xx_ap_get_mimo_wide_rate_mask(struct wl1271 *wl,
949 struct wl12xx_vif *wlvif)
950 {
951 if ((wlvif->channel_type == NL80211_CHAN_HT40MINUS ||
952 wlvif->channel_type == NL80211_CHAN_HT40PLUS) &&
953 !strcmp(ht_mode_param, "wide")) {
954 wl1271_debug(DEBUG_ACX, "using wide channel rate mask");
955 return CONF_TX_RATE_USE_WIDE_CHAN;
956 } else if (!strcmp(ht_mode_param, "mimo")) {
957 wl1271_debug(DEBUG_ACX, "using MIMO rate mask");
958
959 /*
960 * PG 1.0 has some problems with MCS_13, so disable it
961 *
962 * TODO: instead of hacking this in here, we should
963 * make it more general and change a bit in the
964 * wlvif->rate_set instead.
965 */
966 if (wl->chip.id == CHIP_ID_185x_PG10)
967 return CONF_TX_MIMO_RATES & ~CONF_HW_BIT_RATE_MCS_13;
968
969 return CONF_TX_MIMO_RATES;
970 } else {
971 return 0;
972 }
973 }
974
975 static s8 wl18xx_get_pg_ver(struct wl1271 *wl)
976 {
977 u32 fuse;
978
979 wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]);
980
981 fuse = wl1271_read32(wl, WL18XX_REG_FUSE_DATA_1_3);
982 fuse = (fuse & WL18XX_PG_VER_MASK) >> WL18XX_PG_VER_OFFSET;
983
984 wlcore_set_partition(wl, &wl->ptable[PART_BOOT]);
985
986 return (s8)fuse;
987 }
988
989 static void wl18xx_conf_init(struct wl1271 *wl)
990 {
991 struct wl18xx_priv *priv = wl->priv;
992
993 /* apply driver default configuration */
994 memcpy(&wl->conf, &wl18xx_conf, sizeof(wl18xx_conf));
995
996 /* apply default private configuration */
997 memcpy(&priv->conf, &wl18xx_default_priv_conf, sizeof(priv->conf));
998 }
999
1000 static int wl18xx_plt_init(struct wl1271 *wl)
1001 {
1002 wl1271_write32(wl, WL18XX_SCR_PAD8, WL18XX_SCR_PAD8_PLT);
1003
1004 return wl->ops->boot(wl);
1005 }
1006
1007 static void wl18xx_get_mac(struct wl1271 *wl)
1008 {
1009 u32 mac1, mac2;
1010
1011 wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]);
1012
1013 mac1 = wl1271_read32(wl, WL18XX_REG_FUSE_BD_ADDR_1);
1014 mac2 = wl1271_read32(wl, WL18XX_REG_FUSE_BD_ADDR_2);
1015
1016 /* these are the two parts of the BD_ADDR */
1017 wl->fuse_oui_addr = ((mac2 & 0xffff) << 8) +
1018 ((mac1 & 0xff000000) >> 24);
1019 wl->fuse_nic_addr = (mac1 & 0xffffff);
1020
1021 wlcore_set_partition(wl, &wl->ptable[PART_DOWN]);
1022 }
1023
1024 static int wl18xx_debugfs_init(struct wl1271 *wl, struct dentry *rootdir)
1025 {
1026 return wl18xx_debugfs_add_files(wl, rootdir);
1027 }
1028
1029 static int wl18xx_handle_static_data(struct wl1271 *wl,
1030 struct wl1271_static_data *static_data)
1031 {
1032 struct wl18xx_static_data_priv *static_data_priv =
1033 (struct wl18xx_static_data_priv *) static_data->priv;
1034
1035 wl1271_info("PHY firmware version: %s", static_data_priv->phy_version);
1036
1037 return 0;
1038 }
1039
1040 static struct wlcore_ops wl18xx_ops = {
1041 .identify_chip = wl18xx_identify_chip,
1042 .boot = wl18xx_boot,
1043 .plt_init = wl18xx_plt_init,
1044 .trigger_cmd = wl18xx_trigger_cmd,
1045 .ack_event = wl18xx_ack_event,
1046 .calc_tx_blocks = wl18xx_calc_tx_blocks,
1047 .set_tx_desc_blocks = wl18xx_set_tx_desc_blocks,
1048 .set_tx_desc_data_len = wl18xx_set_tx_desc_data_len,
1049 .get_rx_buf_align = wl18xx_get_rx_buf_align,
1050 .get_rx_packet_len = wl18xx_get_rx_packet_len,
1051 .tx_immediate_compl = wl18xx_tx_immediate_completion,
1052 .tx_delayed_compl = NULL,
1053 .hw_init = wl18xx_hw_init,
1054 .set_tx_desc_csum = wl18xx_set_tx_desc_csum,
1055 .get_pg_ver = wl18xx_get_pg_ver,
1056 .set_rx_csum = wl18xx_set_rx_csum,
1057 .sta_get_ap_rate_mask = wl18xx_sta_get_ap_rate_mask,
1058 .ap_get_mimo_wide_rate_mask = wl18xx_ap_get_mimo_wide_rate_mask,
1059 .get_mac = wl18xx_get_mac,
1060 .debugfs_init = wl18xx_debugfs_init,
1061 .handle_static_data = wl18xx_handle_static_data,
1062 };
1063
1064 /* HT cap appropriate for wide channels */
1065 static struct ieee80211_sta_ht_cap wl18xx_siso40_ht_cap = {
1066 .cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40 |
1067 IEEE80211_HT_CAP_SUP_WIDTH_20_40 | IEEE80211_HT_CAP_DSSSCCK40,
1068 .ht_supported = true,
1069 .ampdu_factor = IEEE80211_HT_MAX_AMPDU_16K,
1070 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16,
1071 .mcs = {
1072 .rx_mask = { 0xff, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
1073 .rx_highest = cpu_to_le16(150),
1074 .tx_params = IEEE80211_HT_MCS_TX_DEFINED,
1075 },
1076 };
1077
1078 /* HT cap appropriate for SISO 20 */
1079 static struct ieee80211_sta_ht_cap wl18xx_siso20_ht_cap = {
1080 .cap = IEEE80211_HT_CAP_SGI_20,
1081 .ht_supported = true,
1082 .ampdu_factor = IEEE80211_HT_MAX_AMPDU_16K,
1083 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16,
1084 .mcs = {
1085 .rx_mask = { 0xff, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
1086 .rx_highest = cpu_to_le16(72),
1087 .tx_params = IEEE80211_HT_MCS_TX_DEFINED,
1088 },
1089 };
1090
1091 /* HT cap appropriate for MIMO rates in 20mhz channel */
1092 static struct ieee80211_sta_ht_cap wl18xx_mimo_ht_cap = {
1093 .cap = IEEE80211_HT_CAP_SGI_20,
1094 .ht_supported = true,
1095 .ampdu_factor = IEEE80211_HT_MAX_AMPDU_16K,
1096 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16,
1097 .mcs = {
1098 .rx_mask = { 0xff, 0xff, 0, 0, 0, 0, 0, 0, 0, 0, },
1099 .rx_highest = cpu_to_le16(144),
1100 .tx_params = IEEE80211_HT_MCS_TX_DEFINED,
1101 },
1102 };
1103
1104 int __devinit wl18xx_probe(struct platform_device *pdev)
1105 {
1106 struct wl1271 *wl;
1107 struct ieee80211_hw *hw;
1108 struct wl18xx_priv *priv;
1109
1110 hw = wlcore_alloc_hw(sizeof(*priv));
1111 if (IS_ERR(hw)) {
1112 wl1271_error("can't allocate hw");
1113 return PTR_ERR(hw);
1114 }
1115
1116 wl = hw->priv;
1117 priv = wl->priv;
1118 wl->ops = &wl18xx_ops;
1119 wl->ptable = wl18xx_ptable;
1120 wl->rtable = wl18xx_rtable;
1121 wl->num_tx_desc = 32;
1122 wl->num_rx_desc = 16;
1123 wl->normal_tx_spare = WL18XX_TX_HW_BLOCK_SPARE;
1124 wl->gem_tx_spare = WL18XX_TX_HW_GEM_BLOCK_SPARE;
1125 wl->band_rate_to_idx = wl18xx_band_rate_to_idx;
1126 wl->hw_tx_rate_tbl_size = WL18XX_CONF_HW_RXTX_RATE_MAX;
1127 wl->hw_min_ht_rate = WL18XX_CONF_HW_RXTX_RATE_MCS0;
1128 wl->fw_status_priv_len = sizeof(struct wl18xx_fw_status_priv);
1129 wl->stats.fw_stats_len = sizeof(struct wl18xx_acx_statistics);
1130 wl->static_data_priv_len = sizeof(struct wl18xx_static_data_priv);
1131
1132 if (!strcmp(ht_mode_param, "wide")) {
1133 memcpy(&wl->ht_cap, &wl18xx_siso40_ht_cap,
1134 sizeof(wl18xx_siso40_ht_cap));
1135 } else if (!strcmp(ht_mode_param, "mimo")) {
1136 memcpy(&wl->ht_cap, &wl18xx_mimo_ht_cap,
1137 sizeof(wl18xx_mimo_ht_cap));
1138 } else if (!strcmp(ht_mode_param, "siso20")) {
1139 memcpy(&wl->ht_cap, &wl18xx_siso20_ht_cap,
1140 sizeof(wl18xx_siso20_ht_cap));
1141 } else {
1142 wl1271_error("invalid ht_mode '%s'", ht_mode_param);
1143 goto out_free;
1144 }
1145
1146 wl18xx_conf_init(wl);
1147
1148 if (!strcmp(board_type_param, "fpga")) {
1149 priv->board_type = BOARD_TYPE_FPGA_18XX;
1150 } else if (!strcmp(board_type_param, "hdk")) {
1151 priv->board_type = BOARD_TYPE_HDK_18XX;
1152 /* HACK! Just for now we hardcode HDK to 0x06 */
1153 priv->conf.phy.low_band_component_type = 0x06;
1154 } else if (!strcmp(board_type_param, "dvp")) {
1155 priv->board_type = BOARD_TYPE_DVP_18XX;
1156 } else if (!strcmp(board_type_param, "evb")) {
1157 priv->board_type = BOARD_TYPE_EVB_18XX;
1158 } else if (!strcmp(board_type_param, "com8")) {
1159 priv->board_type = BOARD_TYPE_COM8_18XX;
1160 /* HACK! Just for now we hardcode COM8 to 0x06 */
1161 priv->conf.phy.low_band_component_type = 0x06;
1162 } else {
1163 wl1271_error("invalid board type '%s'", board_type_param);
1164 goto out_free;
1165 }
1166
1167 /*
1168 * If the module param is not set, update it with the one from
1169 * conf. If it is set, overwrite conf with it.
1170 */
1171 if (low_band_component == -1)
1172 low_band_component = priv->conf.phy.low_band_component;
1173 else
1174 priv->conf.phy.low_band_component = low_band_component;
1175 if (low_band_component_type == -1)
1176 low_band_component_type =
1177 priv->conf.phy.low_band_component_type;
1178 else
1179 priv->conf.phy.low_band_component_type =
1180 low_band_component_type;
1181
1182 if (high_band_component == -1)
1183 high_band_component = priv->conf.phy.high_band_component;
1184 else
1185 priv->conf.phy.high_band_component = high_band_component;
1186 if (high_band_component_type == -1)
1187 high_band_component_type =
1188 priv->conf.phy.high_band_component_type;
1189 else
1190 priv->conf.phy.high_band_component_type =
1191 high_band_component_type;
1192
1193 if (!checksum_param) {
1194 wl18xx_ops.set_rx_csum = NULL;
1195 wl18xx_ops.init_vif = NULL;
1196 }
1197
1198 wl->enable_11a = enable_11a_param;
1199
1200 return wlcore_probe(wl, pdev);
1201
1202 out_free:
1203 wlcore_free_hw(wl);
1204 return -EINVAL;
1205 }
1206
1207 static const struct platform_device_id wl18xx_id_table[] __devinitconst = {
1208 { "wl18xx", 0 },
1209 { } /* Terminating Entry */
1210 };
1211 MODULE_DEVICE_TABLE(platform, wl18xx_id_table);
1212
1213 static struct platform_driver wl18xx_driver = {
1214 .probe = wl18xx_probe,
1215 .remove = __devexit_p(wlcore_remove),
1216 .id_table = wl18xx_id_table,
1217 .driver = {
1218 .name = "wl18xx_driver",
1219 .owner = THIS_MODULE,
1220 }
1221 };
1222
1223 static int __init wl18xx_init(void)
1224 {
1225 return platform_driver_register(&wl18xx_driver);
1226 }
1227 module_init(wl18xx_init);
1228
1229 static void __exit wl18xx_exit(void)
1230 {
1231 platform_driver_unregister(&wl18xx_driver);
1232 }
1233 module_exit(wl18xx_exit);
1234
1235 module_param_named(ht_mode, ht_mode_param, charp, S_IRUSR);
1236 MODULE_PARM_DESC(ht_mode, "Force HT mode: wide (default), mimo or siso20");
1237
1238 module_param_named(board_type, board_type_param, charp, S_IRUSR);
1239 MODULE_PARM_DESC(board_type, "Board type: fpga, hdk (default), evb, com8 or "
1240 "dvp");
1241
1242 module_param_named(dc2dc, dc2dc_param, bool, S_IRUSR);
1243 MODULE_PARM_DESC(dc2dc, "External DC2DC: boolean (defaults to false)");
1244
1245 module_param_named(n_antennas_2, n_antennas_2_param, uint, S_IRUSR);
1246 MODULE_PARM_DESC(n_antennas_2, "Number of installed 2.4GHz antennas: 1 (default) or 2");
1247
1248 module_param_named(n_antennas_5, n_antennas_5_param, uint, S_IRUSR);
1249 MODULE_PARM_DESC(n_antennas_5, "Number of installed 5GHz antennas: 1 (default) or 2");
1250
1251 module_param_named(checksum, checksum_param, bool, S_IRUSR);
1252 MODULE_PARM_DESC(checksum, "Enable TCP checksum: boolean (defaults to true)");
1253
1254 module_param_named(enable_11a, enable_11a_param, bool, S_IRUSR);
1255 MODULE_PARM_DESC(enable_11a, "Enable 11a (5GHz): boolean (defaults to true)");
1256
1257 module_param(low_band_component, uint, S_IRUSR);
1258 MODULE_PARM_DESC(low_band_component, "Low band component: u8 "
1259 "(default is 0x01)");
1260
1261 module_param(low_band_component_type, uint, S_IRUSR);
1262 MODULE_PARM_DESC(low_band_component_type, "Low band component type: u8 "
1263 "(default is 0x05 or 0x06 depending on the board_type)");
1264
1265 module_param(high_band_component, uint, S_IRUSR);
1266 MODULE_PARM_DESC(high_band_component, "High band component: u8, "
1267 "(default is 0x01)");
1268
1269 module_param(high_band_component_type, uint, S_IRUSR);
1270 MODULE_PARM_DESC(high_band_component_type, "High band component type: u8 "
1271 "(default is 0x09)");
1272
1273 MODULE_LICENSE("GPL v2");
1274 MODULE_AUTHOR("Luciano Coelho <coelho@ti.com>");
1275 MODULE_FIRMWARE(WL18XX_FW_NAME);
Linux kernel - Deliverables
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