drivers/net/wireless/ti/wlcore/wlcore.h

   1 /*
   2  * This file is part of wlcore
   3  *
   4  * Copyright (C) 2011 Texas Instruments Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * version 2 as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  18  * 02110-1301 USA
  19  *
  20  */
  21
  22 #ifndef __WLCORE_H__
  23 #define __WLCORE_H__
  24
  25 #include <linux/platform_device.h>
  26
  27 #include "wl12xx.h"
  28 #include "event.h"
  29
  30 /* The maximum number of Tx descriptors in all chip families */
  31 #define WLCORE_MAX_TX_DESCRIPTORS 32
  32
  33 /* forward declaration */
  34 struct wl1271_tx_hw_descr;
  35 enum wl_rx_buf_align;
  36
  37 struct wlcore_ops {
  38         int (*identify_chip)(struct wl1271 *wl);
  39         int (*boot)(struct wl1271 *wl);
  40         void (*trigger_cmd)(struct wl1271 *wl);
  41         void (*ack_event)(struct wl1271 *wl);
  42         u32 (*calc_tx_blocks)(struct wl1271 *wl, u32 len, u32 spare_blks);
  43         void (*set_tx_desc_blocks)(struct wl1271 *wl,
  44                                    struct wl1271_tx_hw_descr *desc,
  45                                    u32 blks, u32 spare_blks);
  46         void (*set_tx_desc_data_len)(struct wl1271 *wl,
  47                                      struct wl1271_tx_hw_descr *desc,
  48                                      struct sk_buff *skb);
  49         enum wl_rx_buf_align (*get_rx_buf_align)(struct wl1271 *wl,
  50                                                  u32 rx_desc);
  51         void (*prepare_read)(struct wl1271 *wl, u32 rx_desc, u32 len);
  52         u32 (*get_rx_packet_len)(struct wl1271 *wl, void *rx_data,
  53                                  u32 data_len);
  54         void (*tx_delayed_compl)(struct wl1271 *wl);
  55         void (*tx_immediate_compl)(struct wl1271 *wl);
  56         s8 (*get_pg_ver)(struct wl1271 *wl);
  57         void (*get_mac)(struct wl1271 *wl);
  58 };
  59
  60 enum wlcore_partitions {
  61         PART_DOWN,
  62         PART_WORK,
  63         PART_BOOT,
  64         PART_DRPW,
  65         PART_TOP_PRCM_ELP_SOC,
  66         PART_PHY_INIT,
  67
  68         PART_TABLE_LEN,
  69 };
  70
  71 struct wlcore_partition {
  72         u32 size;
  73         u32 start;
  74 };
  75
  76 struct wlcore_partition_set {
  77         struct wlcore_partition mem;
  78         struct wlcore_partition reg;
  79         struct wlcore_partition mem2;
  80         struct wlcore_partition mem3;
  81 };
  82
  83 enum wlcore_registers {
  84         /* register addresses, used with partition translation */
  85         REG_ECPU_CONTROL,
  86         REG_INTERRUPT_NO_CLEAR,
  87         REG_INTERRUPT_ACK,
  88         REG_COMMAND_MAILBOX_PTR,
  89         REG_EVENT_MAILBOX_PTR,
  90         REG_INTERRUPT_TRIG,
  91         REG_INTERRUPT_MASK,
  92         REG_PC_ON_RECOVERY,
  93         REG_CHIP_ID_B,
  94         REG_CMD_MBOX_ADDRESS,
  95
  96         /* data access memory addresses, used with partition translation */
  97         REG_SLV_MEM_DATA,
  98         REG_SLV_REG_DATA,
  99
 100         /* raw data access memory addresses */
 101         REG_RAW_FW_STATUS_ADDR,
 102
 103         REG_TABLE_LEN,
 104 };
 105
 106 struct wl1271 {
 107         struct ieee80211_hw *hw;
 108         bool mac80211_registered;
 109
 110         struct device *dev;
 111
 112         void *if_priv;
 113
 114         struct wl1271_if_operations *if_ops;
 115
 116         void (*set_power)(bool enable);
 117         int irq;
 118         int ref_clock;
 119
 120         spinlock_t wl_lock;
 121
 122         enum wl1271_state state;
 123         enum wl12xx_fw_type fw_type;
 124         bool plt;
 125         u8 last_vif_count;
 126         struct mutex mutex;
 127
 128         unsigned long flags;
 129
 130         struct wlcore_partition_set curr_part;
 131
 132         struct wl1271_chip chip;
 133
 134         int cmd_box_addr;
 135
 136         u8 *fw;
 137         size_t fw_len;
 138         void *nvs;
 139         size_t nvs_len;
 140
 141         s8 hw_pg_ver;
 142
 143         /* address read from the fuse ROM */
 144         u32 fuse_oui_addr;
 145         u32 fuse_nic_addr;
 146
 147         /* we have up to 2 MAC addresses */
 148         struct mac_address addresses[2];
 149         int channel;
 150         u8 system_hlid;
 151
 152         unsigned long links_map[BITS_TO_LONGS(WL12XX_MAX_LINKS)];
 153         unsigned long roles_map[BITS_TO_LONGS(WL12XX_MAX_ROLES)];
 154         unsigned long roc_map[BITS_TO_LONGS(WL12XX_MAX_ROLES)];
 155         unsigned long rate_policies_map[
 156                         BITS_TO_LONGS(WL12XX_MAX_RATE_POLICIES)];
 157
 158         struct list_head wlvif_list;
 159
 160         u8 sta_count;
 161         u8 ap_count;
 162
 163         struct wl1271_acx_mem_map *target_mem_map;
 164
 165         /* Accounting for allocated / available TX blocks on HW */
 166         u32 tx_blocks_freed;
 167         u32 tx_blocks_available;
 168         u32 tx_allocated_blocks;
 169         u32 tx_results_count;
 170
 171         /* Accounting for allocated / available Tx packets in HW */
 172         u32 tx_pkts_freed[NUM_TX_QUEUES];
 173         u32 tx_allocated_pkts[NUM_TX_QUEUES];
 174
 175         /* Transmitted TX packets counter for chipset interface */
 176         u32 tx_packets_count;
 177
 178         /* Time-offset between host and chipset clocks */
 179         s64 time_offset;
 180
 181         /* Frames scheduled for transmission, not handled yet */
 182         int tx_queue_count[NUM_TX_QUEUES];
 183         long stopped_queues_map;
 184
 185         /* Frames received, not handled yet by mac80211 */
 186         struct sk_buff_head deferred_rx_queue;
 187
 188         /* Frames sent, not returned yet to mac80211 */
 189         struct sk_buff_head deferred_tx_queue;
 190
 191         struct work_struct tx_work;
 192         struct workqueue_struct *freezable_wq;
 193
 194         /* Pending TX frames */
 195         unsigned long tx_frames_map[BITS_TO_LONGS(WLCORE_MAX_TX_DESCRIPTORS)];
 196         struct sk_buff *tx_frames[WLCORE_MAX_TX_DESCRIPTORS];
 197         int tx_frames_cnt;
 198
 199         /* FW Rx counter */
 200         u32 rx_counter;
 201
 202         /* Rx memory pool address */
 203         struct wl1271_rx_mem_pool_addr rx_mem_pool_addr;
 204
 205         /* Intermediate buffer, used for packet aggregation */
 206         u8 *aggr_buf;
 207
 208         /* Reusable dummy packet template */
 209         struct sk_buff *dummy_packet;
 210
 211         /* Network stack work  */
 212         struct work_struct netstack_work;
 213
 214         /* FW log buffer */
 215         u8 *fwlog;
 216
 217         /* Number of valid bytes in the FW log buffer */
 218         ssize_t fwlog_size;
 219
 220         /* Sysfs FW log entry readers wait queue */
 221         wait_queue_head_t fwlog_waitq;
 222
 223         /* Hardware recovery work */
 224         struct work_struct recovery_work;
 225
 226         /* Pointer that holds DMA-friendly block for the mailbox */
 227         struct event_mailbox *mbox;
 228
 229         /* The mbox event mask */
 230         u32 event_mask;
 231
 232         /* Mailbox pointers */
 233         u32 mbox_ptr[2];
 234
 235         /* Are we currently scanning */
 236         struct ieee80211_vif *scan_vif;
 237         struct wl1271_scan scan;
 238         struct delayed_work scan_complete_work;
 239
 240         bool sched_scanning;
 241
 242         /* The current band */
 243         enum ieee80211_band band;
 244
 245         struct completion *elp_compl;
 246         struct delayed_work elp_work;
 247
 248         /* in dBm */
 249         int power_level;
 250
 251         struct wl1271_stats stats;
 252
 253         __le32 buffer_32;
 254         u32 buffer_cmd;
 255         u32 buffer_busyword[WL1271_BUSY_WORD_CNT];
 256
 257         struct wl12xx_fw_status *fw_status;
 258         struct wl1271_tx_hw_res_if *tx_res_if;
 259
 260         /* Current chipset configuration */
 261         struct conf_drv_settings conf;
 262
 263         bool sg_enabled;
 264
 265         bool enable_11a;
 266
 267         /* Most recently reported noise in dBm */
 268         s8 noise;
 269
 270         /* bands supported by this instance of wl12xx */
 271         struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];
 272
 273         int tcxo_clock;
 274
 275         /*
 276          * wowlan trigger was configured during suspend.
 277          * (currently, only "ANY" trigger is supported)
 278          */
 279         bool wow_enabled;
 280         bool irq_wake_enabled;
 281
 282         /*
 283          * AP-mode - links indexed by HLID. The global and broadcast links
 284          * are always active.
 285          */
 286         struct wl1271_link links[WL12XX_MAX_LINKS];
 287
 288         /* AP-mode - a bitmap of links currently in PS mode according to FW */
 289         u32 ap_fw_ps_map;
 290
 291         /* AP-mode - a bitmap of links currently in PS mode in mac80211 */
 292         unsigned long ap_ps_map;
 293
 294         /* Quirks of specific hardware revisions */
 295         unsigned int quirks;
 296
 297         /* Platform limitations */
 298         unsigned int platform_quirks;
 299
 300         /* number of currently active RX BA sessions */
 301         int ba_rx_session_count;
 302
 303         /* AP-mode - number of currently connected stations */
 304         int active_sta_count;
 305
 306         /* last wlvif we transmitted from */
 307         struct wl12xx_vif *last_wlvif;
 308
 309         /* work to fire when Tx is stuck */
 310         struct delayed_work tx_watchdog_work;
 311
 312         struct wlcore_ops *ops;
 313         /* pointer to the lower driver partition table */
 314         const struct wlcore_partition_set *ptable;
 315         /* pointer to the lower driver register table */
 316         const int *rtable;
 317         /* name of the firmwares to load - for PLT, single role, multi-role */
 318         const char *plt_fw_name;
 319         const char *sr_fw_name;
 320         const char *mr_fw_name;
 321
 322         /* per-chip-family private structure */
 323         void *priv;
 324
 325         /* number of TX descriptors the HW supports. */
 326         u32 num_tx_desc;
 327
 328         /* spare Tx blocks for normal/GEM operating modes */
 329         u32 normal_tx_spare;
 330         u32 gem_tx_spare;
 331
 332         /* translate HW Tx rates to standard rate-indices */
 333         const u8 **band_rate_to_idx;
 334
 335         /* size of table for HW rates that can be received from chip */
 336         u8 hw_tx_rate_tbl_size;
 337
 338         /* this HW rate and below are considered HT rates for this chip */
 339         u8 hw_min_ht_rate;
 340 };
 341
 342 int __devinit wlcore_probe(struct wl1271 *wl, struct platform_device *pdev);
 343 int __devexit wlcore_remove(struct platform_device *pdev);
 344 struct ieee80211_hw *wlcore_alloc_hw(size_t priv_size);
 345 int wlcore_free_hw(struct wl1271 *wl);
 346
 347 /* Firmware image load chunk size */
 348 #define CHUNK_SIZE      16384
 349
 350 /* Quirks */
 351
 352 /* Each RX/TX transaction requires an end-of-transaction transfer */
 353 #define WLCORE_QUIRK_END_OF_TRANSACTION         BIT(0)
 354
 355 /* wl127x and SPI don't support SDIO block size alignment */
 356 #define WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN         BIT(2)
 357
 358 /* means aggregated Rx packets are aligned to a SDIO block */
 359 #define WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN         BIT(3)
 360
 361 /* Older firmwares did not implement the FW logger over bus feature */
 362 #define WLCORE_QUIRK_FWLOG_NOT_IMPLEMENTED      BIT(4)
 363
 364 /* Older firmwares use an old NVS format */
 365 #define WLCORE_QUIRK_LEGACY_NVS                 BIT(5)
 366
 367 /* Some firmwares may not support ELP */
 368 #define WLCORE_QUIRK_NO_ELP                     BIT(6)
 369
 370 /* TODO: move to the lower drivers when all usages are abstracted */
 371 #define CHIP_ID_1271_PG10              (0x4030101)
 372 #define CHIP_ID_1271_PG20              (0x4030111)
 373 #define CHIP_ID_1283_PG10              (0x05030101)
 374 #define CHIP_ID_1283_PG20              (0x05030111)
 375
 376 /* TODO: move all these common registers and values elsewhere */
 377 #define HW_ACCESS_ELP_CTRL_REG          0x1FFFC
 378
 379 /* ELP register commands */
 380 #define ELPCTRL_WAKE_UP             0x1
 381 #define ELPCTRL_WAKE_UP_WLAN_READY  0x5
 382 #define ELPCTRL_SLEEP               0x0
 383 /* ELP WLAN_READY bit */
 384 #define ELPCTRL_WLAN_READY          0x2
 385
 386 /*************************************************************************
 387
 388     Interrupt Trigger Register (Host -> WiLink)
 389
 390 **************************************************************************/
 391
 392 /* Hardware to Embedded CPU Interrupts - first 32-bit register set */
 393
 394 /*
 395  * The host sets this bit to inform the Wlan
 396  * FW that a TX packet is in the XFER
 397  * Buffer #0.
 398  */
 399 #define INTR_TRIG_TX_PROC0 BIT(2)
 400
 401 /*
 402  * The host sets this bit to inform the FW
 403  * that it read a packet from RX XFER
 404  * Buffer #0.
 405  */
 406 #define INTR_TRIG_RX_PROC0 BIT(3)
 407
 408 #define INTR_TRIG_DEBUG_ACK BIT(4)
 409
 410 #define INTR_TRIG_STATE_CHANGED BIT(5)
 411
 412 /* Hardware to Embedded CPU Interrupts - second 32-bit register set */
 413
 414 /*
 415  * The host sets this bit to inform the FW
 416  * that it read a packet from RX XFER
 417  * Buffer #1.
 418  */
 419 #define INTR_TRIG_RX_PROC1 BIT(17)
 420
 421 /*
 422  * The host sets this bit to inform the Wlan
 423  * hardware that a TX packet is in the XFER
 424  * Buffer #1.
 425  */
 426 #define INTR_TRIG_TX_PROC1 BIT(18)
 427
 428 #define ACX_SLV_SOFT_RESET_BIT  BIT(1)
 429 #define SOFT_RESET_MAX_TIME     1000000
 430 #define SOFT_RESET_STALL_TIME   1000
 431
 432 #define ECPU_CONTROL_HALT       0x00000101
 433
 434 #define WELP_ARM_COMMAND_VAL    0x4
 435
 436 #endif /* __WLCORE_H__ */