drivers/net/wireless/wl12xx/io.c

   1 /*
   2  * This file is part of wl1271
   3  *
   4  * Copyright (C) 2008-2010 Nokia Corporation
   5  *
   6  * Contact: Luciano Coelho <luciano.coelho@nokia.com>
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * version 2 as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but
  13  * WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  20  * 02110-1301 USA
  21  *
  22  */
  23
  24 #include <linux/module.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/spi/spi.h>
  27 #include <linux/interrupt.h>
  28
  29 #include "wl12xx.h"
  30 #include "debug.h"
  31 #include "wl12xx_80211.h"
  32 #include "io.h"
  33 #include "tx.h"
  34
  35 #define OCP_CMD_LOOP  32
  36
  37 #define OCP_CMD_WRITE 0x1
  38 #define OCP_CMD_READ  0x2
  39
  40 #define OCP_READY_MASK  BIT(18)
  41 #define OCP_STATUS_MASK (BIT(16) | BIT(17))
  42
  43 #define OCP_STATUS_NO_RESP    0x00000
  44 #define OCP_STATUS_OK         0x10000
  45 #define OCP_STATUS_REQ_FAILED 0x20000
  46 #define OCP_STATUS_RESP_ERROR 0x30000
  47
  48 struct wl1271_partition_set wl12xx_part_table[PART_TABLE_LEN] = {
  49         [PART_DOWN] = {
  50                 .mem = {
  51                         .start = 0x00000000,
  52                         .size  = 0x000177c0
  53                 },
  54                 .reg = {
  55                         .start = REGISTERS_BASE,
  56                         .size  = 0x00008800
  57                 },
  58                 .mem2 = {
  59                         .start = 0x00000000,
  60                         .size  = 0x00000000
  61                 },
  62                 .mem3 = {
  63                         .start = 0x00000000,
  64                         .size  = 0x00000000
  65                 },
  66         },
  67
  68         [PART_WORK] = {
  69                 .mem = {
  70                         .start = 0x00040000,
  71                         .size  = 0x00014fc0
  72                 },
  73                 .reg = {
  74                         .start = REGISTERS_BASE,
  75                         .size  = 0x0000a000
  76                 },
  77                 .mem2 = {
  78                         .start = 0x003004f8,
  79                         .size  = 0x00000004
  80                 },
  81                 .mem3 = {
  82                         .start = 0x00040404,
  83                         .size  = 0x00000000
  84                 },
  85         },
  86
  87         [PART_DRPW] = {
  88                 .mem = {
  89                         .start = 0x00040000,
  90                         .size  = 0x00014fc0
  91                 },
  92                 .reg = {
  93                         .start = DRPW_BASE,
  94                         .size  = 0x00006000
  95                 },
  96                 .mem2 = {
  97                         .start = 0x00000000,
  98                         .size  = 0x00000000
  99                 },
 100                 .mem3 = {
 101                         .start = 0x00000000,
 102                         .size  = 0x00000000
 103                 }
 104         }
 105 };
 106
 107 bool wl1271_set_block_size(struct wl1271 *wl)
 108 {
 109         if (wl->if_ops->set_block_size) {
 110                 wl->if_ops->set_block_size(wl->dev, WL12XX_BUS_BLOCK_SIZE);
 111                 return true;
 112         }
 113
 114         return false;
 115 }
 116
 117 void wl1271_disable_interrupts(struct wl1271 *wl)
 118 {
 119         disable_irq(wl->irq);
 120 }
 121
 122 void wl1271_enable_interrupts(struct wl1271 *wl)
 123 {
 124         enable_irq(wl->irq);
 125 }
 126
 127 /* Set the SPI partitions to access the chip addresses
 128  *
 129  * To simplify driver code, a fixed (virtual) memory map is defined for
 130  * register and memory addresses. Because in the chipset, in different stages
 131  * of operation, those addresses will move around, an address translation
 132  * mechanism is required.
 133  *
 134  * There are four partitions (three memory and one register partition),
 135  * which are mapped to two different areas of the hardware memory.
 136  *
 137  *                                Virtual address
 138  *                                     space
 139  *
 140  *                                    |    |
 141  *                                 ...+----+--> mem.start
 142  *          Physical address    ...   |    |
 143  *               space       ...      |    | [PART_0]
 144  *                        ...         |    |
 145  *  00000000  <--+----+...         ...+----+--> mem.start + mem.size
 146  *               |    |         ...   |    |
 147  *               |MEM |      ...      |    |
 148  *               |    |   ...         |    |
 149  *  mem.size  <--+----+...            |    | {unused area)
 150  *               |    |   ...         |    |
 151  *               |REG |      ...      |    |
 152  *  mem.size     |    |         ...   |    |
 153  *      +     <--+----+...         ...+----+--> reg.start
 154  *  reg.size     |    |   ...         |    |
 155  *               |MEM2|      ...      |    | [PART_1]
 156  *               |    |         ...   |    |
 157  *                                 ...+----+--> reg.start + reg.size
 158  *                                    |    |
 159  *
 160  */
 161 int wl1271_set_partition(struct wl1271 *wl,
 162                          struct wl1271_partition_set *p)
 163 {
 164         /* copy partition info */
 165         memcpy(&wl->part, p, sizeof(*p));
 166
 167         wl1271_debug(DEBUG_SPI, "mem_start %08X mem_size %08X",
 168                      p->mem.start, p->mem.size);
 169         wl1271_debug(DEBUG_SPI, "reg_start %08X reg_size %08X",
 170                      p->reg.start, p->reg.size);
 171         wl1271_debug(DEBUG_SPI, "mem2_start %08X mem2_size %08X",
 172                      p->mem2.start, p->mem2.size);
 173         wl1271_debug(DEBUG_SPI, "mem3_start %08X mem3_size %08X",
 174                      p->mem3.start, p->mem3.size);
 175
 176         /* write partition info to the chipset */
 177         wl1271_raw_write32(wl, HW_PART0_START_ADDR, p->mem.start);
 178         wl1271_raw_write32(wl, HW_PART0_SIZE_ADDR, p->mem.size);
 179         wl1271_raw_write32(wl, HW_PART1_START_ADDR, p->reg.start);
 180         wl1271_raw_write32(wl, HW_PART1_SIZE_ADDR, p->reg.size);
 181         wl1271_raw_write32(wl, HW_PART2_START_ADDR, p->mem2.start);
 182         wl1271_raw_write32(wl, HW_PART2_SIZE_ADDR, p->mem2.size);
 183         wl1271_raw_write32(wl, HW_PART3_START_ADDR, p->mem3.start);
 184
 185         return 0;
 186 }
 187 EXPORT_SYMBOL_GPL(wl1271_set_partition);
 188
 189 void wl1271_io_reset(struct wl1271 *wl)
 190 {
 191         if (wl->if_ops->reset)
 192                 wl->if_ops->reset(wl->dev);
 193 }
 194
 195 void wl1271_io_init(struct wl1271 *wl)
 196 {
 197         if (wl->if_ops->init)
 198                 wl->if_ops->init(wl->dev);
 199 }
 200
 201 void wl1271_top_reg_write(struct wl1271 *wl, int addr, u16 val)
 202 {
 203         /* write address >> 1 + 0x30000 to OCP_POR_CTR */
 204         addr = (addr >> 1) + 0x30000;
 205         wl1271_write32(wl, OCP_POR_CTR, addr);
 206
 207         /* write value to OCP_POR_WDATA */
 208         wl1271_write32(wl, OCP_DATA_WRITE, val);
 209
 210         /* write 1 to OCP_CMD */
 211         wl1271_write32(wl, OCP_CMD, OCP_CMD_WRITE);
 212 }
 213
 214 u16 wl1271_top_reg_read(struct wl1271 *wl, int addr)
 215 {
 216         u32 val;
 217         int timeout = OCP_CMD_LOOP;
 218
 219         /* write address >> 1 + 0x30000 to OCP_POR_CTR */
 220         addr = (addr >> 1) + 0x30000;
 221         wl1271_write32(wl, OCP_POR_CTR, addr);
 222
 223         /* write 2 to OCP_CMD */
 224         wl1271_write32(wl, OCP_CMD, OCP_CMD_READ);
 225
 226         /* poll for data ready */
 227         do {
 228                 val = wl1271_read32(wl, OCP_DATA_READ);
 229         } while (!(val & OCP_READY_MASK) && --timeout);
 230
 231         if (!timeout) {
 232                 wl1271_warning("Top register access timed out.");
 233                 return 0xffff;
 234         }
 235
 236         /* check data status and return if OK */
 237         if ((val & OCP_STATUS_MASK) == OCP_STATUS_OK)
 238                 return val & 0xffff;
 239         else {
 240                 wl1271_warning("Top register access returned error.");
 241                 return 0xffff;
 242         }
 243 }
 244