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[PATCH] zd1211rw: Reject AL2230S devices
[deliverable/linux.git] / drivers / net / wireless / zd1211rw / zd_chip.c
1 /* zd_chip.c
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License as published by
5 * the Free Software Foundation; either version 2 of the License, or
6 * (at your option) any later version.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
16 */
17
18 /* This file implements all the hardware specific functions for the ZD1211
19 * and ZD1211B chips. Support for the ZD1211B was possible after Timothy
20 * Legge sent me a ZD1211B device. Thank you Tim. -- Uli
21 */
22
23 #include <linux/kernel.h>
24 #include <linux/errno.h>
25
26 #include "zd_def.h"
27 #include "zd_chip.h"
28 #include "zd_ieee80211.h"
29 #include "zd_mac.h"
30 #include "zd_rf.h"
31 #include "zd_util.h"
32
33 void zd_chip_init(struct zd_chip *chip,
34 struct net_device *netdev,
35 struct usb_interface *intf)
36 {
37 memset(chip, 0, sizeof(*chip));
38 mutex_init(&chip->mutex);
39 zd_usb_init(&chip->usb, netdev, intf);
40 zd_rf_init(&chip->rf);
41 }
42
43 void zd_chip_clear(struct zd_chip *chip)
44 {
45 ZD_ASSERT(!mutex_is_locked(&chip->mutex));
46 zd_usb_clear(&chip->usb);
47 zd_rf_clear(&chip->rf);
48 mutex_destroy(&chip->mutex);
49 ZD_MEMCLEAR(chip, sizeof(*chip));
50 }
51
52 static int scnprint_mac_oui(const u8 *addr, char *buffer, size_t size)
53 {
54 return scnprintf(buffer, size, "%02x-%02x-%02x",
55 addr[0], addr[1], addr[2]);
56 }
57
58 /* Prints an identifier line, which will support debugging. */
59 static int scnprint_id(struct zd_chip *chip, char *buffer, size_t size)
60 {
61 int i = 0;
62
63 i = scnprintf(buffer, size, "zd1211%s chip ",
64 chip->is_zd1211b ? "b" : "");
65 i += zd_usb_scnprint_id(&chip->usb, buffer+i, size-i);
66 i += scnprintf(buffer+i, size-i, " ");
67 i += scnprint_mac_oui(chip->e2p_mac, buffer+i, size-i);
68 i += scnprintf(buffer+i, size-i, " ");
69 i += zd_rf_scnprint_id(&chip->rf, buffer+i, size-i);
70 i += scnprintf(buffer+i, size-i, " pa%1x %c%c%c%c", chip->pa_type,
71 chip->patch_cck_gain ? 'g' : '-',
72 chip->patch_cr157 ? '7' : '-',
73 chip->patch_6m_band_edge ? '6' : '-',
74 chip->new_phy_layout ? 'N' : '-');
75 return i;
76 }
77
78 static void print_id(struct zd_chip *chip)
79 {
80 char buffer[80];
81
82 scnprint_id(chip, buffer, sizeof(buffer));
83 buffer[sizeof(buffer)-1] = 0;
84 dev_info(zd_chip_dev(chip), "%s\n", buffer);
85 }
86
87 static zd_addr_t inc_addr(zd_addr_t addr)
88 {
89 u16 a = (u16)addr;
90 /* Control registers use byte addressing, but everything else uses word
91 * addressing. */
92 if ((a & 0xf000) == CR_START)
93 a += 2;
94 else
95 a += 1;
96 return (zd_addr_t)a;
97 }
98
99 /* Read a variable number of 32-bit values. Parameter count is not allowed to
100 * exceed USB_MAX_IOREAD32_COUNT.
101 */
102 int zd_ioread32v_locked(struct zd_chip *chip, u32 *values, const zd_addr_t *addr,
103 unsigned int count)
104 {
105 int r;
106 int i;
107 zd_addr_t *a16 = (zd_addr_t *)NULL;
108 u16 *v16;
109 unsigned int count16;
110
111 if (count > USB_MAX_IOREAD32_COUNT)
112 return -EINVAL;
113
114 /* Allocate a single memory block for values and addresses. */
115 count16 = 2*count;
116 a16 = (zd_addr_t *) kmalloc(count16 * (sizeof(zd_addr_t) + sizeof(u16)),
117 GFP_NOFS);
118 if (!a16) {
119 dev_dbg_f(zd_chip_dev(chip),
120 "error ENOMEM in allocation of a16\n");
121 r = -ENOMEM;
122 goto out;
123 }
124 v16 = (u16 *)(a16 + count16);
125
126 for (i = 0; i < count; i++) {
127 int j = 2*i;
128 /* We read the high word always first. */
129 a16[j] = inc_addr(addr[i]);
130 a16[j+1] = addr[i];
131 }
132
133 r = zd_ioread16v_locked(chip, v16, a16, count16);
134 if (r) {
135 dev_dbg_f(zd_chip_dev(chip),
136 "error: zd_ioread16v_locked. Error number %d\n", r);
137 goto out;
138 }
139
140 for (i = 0; i < count; i++) {
141 int j = 2*i;
142 values[i] = (v16[j] << 16) | v16[j+1];
143 }
144
145 out:
146 kfree((void *)a16);
147 return r;
148 }
149
150 int _zd_iowrite32v_locked(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs,
151 unsigned int count)
152 {
153 int i, j, r;
154 struct zd_ioreq16 *ioreqs16;
155 unsigned int count16;
156
157 ZD_ASSERT(mutex_is_locked(&chip->mutex));
158
159 if (count == 0)
160 return 0;
161 if (count > USB_MAX_IOWRITE32_COUNT)
162 return -EINVAL;
163
164 /* Allocate a single memory block for values and addresses. */
165 count16 = 2*count;
166 ioreqs16 = kmalloc(count16 * sizeof(struct zd_ioreq16), GFP_NOFS);
167 if (!ioreqs16) {
168 r = -ENOMEM;
169 dev_dbg_f(zd_chip_dev(chip),
170 "error %d in ioreqs16 allocation\n", r);
171 goto out;
172 }
173
174 for (i = 0; i < count; i++) {
175 j = 2*i;
176 /* We write the high word always first. */
177 ioreqs16[j].value = ioreqs[i].value >> 16;
178 ioreqs16[j].addr = inc_addr(ioreqs[i].addr);
179 ioreqs16[j+1].value = ioreqs[i].value;
180 ioreqs16[j+1].addr = ioreqs[i].addr;
181 }
182
183 r = zd_usb_iowrite16v(&chip->usb, ioreqs16, count16);
184 #ifdef DEBUG
185 if (r) {
186 dev_dbg_f(zd_chip_dev(chip),
187 "error %d in zd_usb_write16v\n", r);
188 }
189 #endif /* DEBUG */
190 out:
191 kfree(ioreqs16);
192 return r;
193 }
194
195 int zd_iowrite16a_locked(struct zd_chip *chip,
196 const struct zd_ioreq16 *ioreqs, unsigned int count)
197 {
198 int r;
199 unsigned int i, j, t, max;
200
201 ZD_ASSERT(mutex_is_locked(&chip->mutex));
202 for (i = 0; i < count; i += j + t) {
203 t = 0;
204 max = count-i;
205 if (max > USB_MAX_IOWRITE16_COUNT)
206 max = USB_MAX_IOWRITE16_COUNT;
207 for (j = 0; j < max; j++) {
208 if (!ioreqs[i+j].addr) {
209 t = 1;
210 break;
211 }
212 }
213
214 r = zd_usb_iowrite16v(&chip->usb, &ioreqs[i], j);
215 if (r) {
216 dev_dbg_f(zd_chip_dev(chip),
217 "error zd_usb_iowrite16v. Error number %d\n",
218 r);
219 return r;
220 }
221 }
222
223 return 0;
224 }
225
226 /* Writes a variable number of 32 bit registers. The functions will split
227 * that in several USB requests. A split can be forced by inserting an IO
228 * request with an zero address field.
229 */
230 int zd_iowrite32a_locked(struct zd_chip *chip,
231 const struct zd_ioreq32 *ioreqs, unsigned int count)
232 {
233 int r;
234 unsigned int i, j, t, max;
235
236 for (i = 0; i < count; i += j + t) {
237 t = 0;
238 max = count-i;
239 if (max > USB_MAX_IOWRITE32_COUNT)
240 max = USB_MAX_IOWRITE32_COUNT;
241 for (j = 0; j < max; j++) {
242 if (!ioreqs[i+j].addr) {
243 t = 1;
244 break;
245 }
246 }
247
248 r = _zd_iowrite32v_locked(chip, &ioreqs[i], j);
249 if (r) {
250 dev_dbg_f(zd_chip_dev(chip),
251 "error _zd_iowrite32v_locked."
252 " Error number %d\n", r);
253 return r;
254 }
255 }
256
257 return 0;
258 }
259
260 int zd_ioread16(struct zd_chip *chip, zd_addr_t addr, u16 *value)
261 {
262 int r;
263
264 mutex_lock(&chip->mutex);
265 r = zd_ioread16_locked(chip, value, addr);
266 mutex_unlock(&chip->mutex);
267 return r;
268 }
269
270 int zd_ioread32(struct zd_chip *chip, zd_addr_t addr, u32 *value)
271 {
272 int r;
273
274 mutex_lock(&chip->mutex);
275 r = zd_ioread32_locked(chip, value, addr);
276 mutex_unlock(&chip->mutex);
277 return r;
278 }
279
280 int zd_iowrite16(struct zd_chip *chip, zd_addr_t addr, u16 value)
281 {
282 int r;
283
284 mutex_lock(&chip->mutex);
285 r = zd_iowrite16_locked(chip, value, addr);
286 mutex_unlock(&chip->mutex);
287 return r;
288 }
289
290 int zd_iowrite32(struct zd_chip *chip, zd_addr_t addr, u32 value)
291 {
292 int r;
293
294 mutex_lock(&chip->mutex);
295 r = zd_iowrite32_locked(chip, value, addr);
296 mutex_unlock(&chip->mutex);
297 return r;
298 }
299
300 int zd_ioread32v(struct zd_chip *chip, const zd_addr_t *addresses,
301 u32 *values, unsigned int count)
302 {
303 int r;
304
305 mutex_lock(&chip->mutex);
306 r = zd_ioread32v_locked(chip, values, addresses, count);
307 mutex_unlock(&chip->mutex);
308 return r;
309 }
310
311 int zd_iowrite32a(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs,
312 unsigned int count)
313 {
314 int r;
315
316 mutex_lock(&chip->mutex);
317 r = zd_iowrite32a_locked(chip, ioreqs, count);
318 mutex_unlock(&chip->mutex);
319 return r;
320 }
321
322 static int read_pod(struct zd_chip *chip, u8 *rf_type)
323 {
324 int r;
325 u32 value;
326
327 ZD_ASSERT(mutex_is_locked(&chip->mutex));
328 r = zd_ioread32_locked(chip, &value, E2P_POD);
329 if (r)
330 goto error;
331 dev_dbg_f(zd_chip_dev(chip), "E2P_POD %#010x\n", value);
332
333 /* FIXME: AL2230 handling (Bit 7 in POD) */
334 *rf_type = value & 0x0f;
335 chip->pa_type = (value >> 16) & 0x0f;
336 chip->patch_cck_gain = (value >> 8) & 0x1;
337 chip->patch_cr157 = (value >> 13) & 0x1;
338 chip->patch_6m_band_edge = (value >> 21) & 0x1;
339 chip->new_phy_layout = (value >> 31) & 0x1;
340 chip->al2230s_bit = (value >> 7) & 0x1;
341 chip->link_led = ((value >> 4) & 1) ? LED1 : LED2;
342 chip->supports_tx_led = 1;
343 if (value & (1 << 24)) { /* LED scenario */
344 if (value & (1 << 29))
345 chip->supports_tx_led = 0;
346 }
347
348 dev_dbg_f(zd_chip_dev(chip),
349 "RF %s %#01x PA type %#01x patch CCK %d patch CR157 %d "
350 "patch 6M %d new PHY %d link LED%d tx led %d\n",
351 zd_rf_name(*rf_type), *rf_type,
352 chip->pa_type, chip->patch_cck_gain,
353 chip->patch_cr157, chip->patch_6m_band_edge,
354 chip->new_phy_layout,
355 chip->link_led == LED1 ? 1 : 2,
356 chip->supports_tx_led);
357 return 0;
358 error:
359 *rf_type = 0;
360 chip->pa_type = 0;
361 chip->patch_cck_gain = 0;
362 chip->patch_cr157 = 0;
363 chip->patch_6m_band_edge = 0;
364 chip->new_phy_layout = 0;
365 return r;
366 }
367
368 static int _read_mac_addr(struct zd_chip *chip, u8 *mac_addr,
369 const zd_addr_t *addr)
370 {
371 int r;
372 u32 parts[2];
373
374 r = zd_ioread32v_locked(chip, parts, (const zd_addr_t *)addr, 2);
375 if (r) {
376 dev_dbg_f(zd_chip_dev(chip),
377 "error: couldn't read e2p macs. Error number %d\n", r);
378 return r;
379 }
380
381 mac_addr[0] = parts[0];
382 mac_addr[1] = parts[0] >> 8;
383 mac_addr[2] = parts[0] >> 16;
384 mac_addr[3] = parts[0] >> 24;
385 mac_addr[4] = parts[1];
386 mac_addr[5] = parts[1] >> 8;
387
388 return 0;
389 }
390
391 static int read_e2p_mac_addr(struct zd_chip *chip)
392 {
393 static const zd_addr_t addr[2] = { E2P_MAC_ADDR_P1, E2P_MAC_ADDR_P2 };
394
395 ZD_ASSERT(mutex_is_locked(&chip->mutex));
396 return _read_mac_addr(chip, chip->e2p_mac, (const zd_addr_t *)addr);
397 }
398
399 /* MAC address: if custom mac addresses are to to be used CR_MAC_ADDR_P1 and
400 * CR_MAC_ADDR_P2 must be overwritten
401 */
402 void zd_get_e2p_mac_addr(struct zd_chip *chip, u8 *mac_addr)
403 {
404 mutex_lock(&chip->mutex);
405 memcpy(mac_addr, chip->e2p_mac, ETH_ALEN);
406 mutex_unlock(&chip->mutex);
407 }
408
409 static int read_mac_addr(struct zd_chip *chip, u8 *mac_addr)
410 {
411 static const zd_addr_t addr[2] = { CR_MAC_ADDR_P1, CR_MAC_ADDR_P2 };
412 return _read_mac_addr(chip, mac_addr, (const zd_addr_t *)addr);
413 }
414
415 int zd_read_mac_addr(struct zd_chip *chip, u8 *mac_addr)
416 {
417 int r;
418
419 dev_dbg_f(zd_chip_dev(chip), "\n");
420 mutex_lock(&chip->mutex);
421 r = read_mac_addr(chip, mac_addr);
422 mutex_unlock(&chip->mutex);
423 return r;
424 }
425
426 int zd_write_mac_addr(struct zd_chip *chip, const u8 *mac_addr)
427 {
428 int r;
429 struct zd_ioreq32 reqs[2] = {
430 [0] = { .addr = CR_MAC_ADDR_P1 },
431 [1] = { .addr = CR_MAC_ADDR_P2 },
432 };
433
434 reqs[0].value = (mac_addr[3] << 24)
435 | (mac_addr[2] << 16)
436 | (mac_addr[1] << 8)
437 | mac_addr[0];
438 reqs[1].value = (mac_addr[5] << 8)
439 | mac_addr[4];
440
441 dev_dbg_f(zd_chip_dev(chip),
442 "mac addr " MAC_FMT "\n", MAC_ARG(mac_addr));
443
444 mutex_lock(&chip->mutex);
445 r = zd_iowrite32a_locked(chip, reqs, ARRAY_SIZE(reqs));
446 #ifdef DEBUG
447 {
448 u8 tmp[ETH_ALEN];
449 read_mac_addr(chip, tmp);
450 }
451 #endif /* DEBUG */
452 mutex_unlock(&chip->mutex);
453 return r;
454 }
455
456 int zd_read_regdomain(struct zd_chip *chip, u8 *regdomain)
457 {
458 int r;
459 u32 value;
460
461 mutex_lock(&chip->mutex);
462 r = zd_ioread32_locked(chip, &value, E2P_SUBID);
463 mutex_unlock(&chip->mutex);
464 if (r)
465 return r;
466
467 *regdomain = value >> 16;
468 dev_dbg_f(zd_chip_dev(chip), "regdomain: %#04x\n", *regdomain);
469
470 return 0;
471 }
472
473 static int read_values(struct zd_chip *chip, u8 *values, size_t count,
474 zd_addr_t e2p_addr, u32 guard)
475 {
476 int r;
477 int i;
478 u32 v;
479
480 ZD_ASSERT(mutex_is_locked(&chip->mutex));
481 for (i = 0;;) {
482 r = zd_ioread32_locked(chip, &v,
483 (zd_addr_t)((u16)e2p_addr+i/2));
484 if (r)
485 return r;
486 v -= guard;
487 if (i+4 < count) {
488 values[i++] = v;
489 values[i++] = v >> 8;
490 values[i++] = v >> 16;
491 values[i++] = v >> 24;
492 continue;
493 }
494 for (;i < count; i++)
495 values[i] = v >> (8*(i%3));
496 return 0;
497 }
498 }
499
500 static int read_pwr_cal_values(struct zd_chip *chip)
501 {
502 return read_values(chip, chip->pwr_cal_values,
503 E2P_CHANNEL_COUNT, E2P_PWR_CAL_VALUE1,
504 0);
505 }
506
507 static int read_pwr_int_values(struct zd_chip *chip)
508 {
509 return read_values(chip, chip->pwr_int_values,
510 E2P_CHANNEL_COUNT, E2P_PWR_INT_VALUE1,
511 E2P_PWR_INT_GUARD);
512 }
513
514 static int read_ofdm_cal_values(struct zd_chip *chip)
515 {
516 int r;
517 int i;
518 static const zd_addr_t addresses[] = {
519 E2P_36M_CAL_VALUE1,
520 E2P_48M_CAL_VALUE1,
521 E2P_54M_CAL_VALUE1,
522 };
523
524 for (i = 0; i < 3; i++) {
525 r = read_values(chip, chip->ofdm_cal_values[i],
526 E2P_CHANNEL_COUNT, addresses[i], 0);
527 if (r)
528 return r;
529 }
530 return 0;
531 }
532
533 static int read_cal_int_tables(struct zd_chip *chip)
534 {
535 int r;
536
537 r = read_pwr_cal_values(chip);
538 if (r)
539 return r;
540 r = read_pwr_int_values(chip);
541 if (r)
542 return r;
543 r = read_ofdm_cal_values(chip);
544 if (r)
545 return r;
546 return 0;
547 }
548
549 /* phy means physical registers */
550 int zd_chip_lock_phy_regs(struct zd_chip *chip)
551 {
552 int r;
553 u32 tmp;
554
555 ZD_ASSERT(mutex_is_locked(&chip->mutex));
556 r = zd_ioread32_locked(chip, &tmp, CR_REG1);
557 if (r) {
558 dev_err(zd_chip_dev(chip), "error ioread32(CR_REG1): %d\n", r);
559 return r;
560 }
561
562 dev_dbg_f(zd_chip_dev(chip),
563 "CR_REG1: 0x%02x -> 0x%02x\n", tmp, tmp & ~UNLOCK_PHY_REGS);
564 tmp &= ~UNLOCK_PHY_REGS;
565
566 r = zd_iowrite32_locked(chip, tmp, CR_REG1);
567 if (r)
568 dev_err(zd_chip_dev(chip), "error iowrite32(CR_REG1): %d\n", r);
569 return r;
570 }
571
572 int zd_chip_unlock_phy_regs(struct zd_chip *chip)
573 {
574 int r;
575 u32 tmp;
576
577 ZD_ASSERT(mutex_is_locked(&chip->mutex));
578 r = zd_ioread32_locked(chip, &tmp, CR_REG1);
579 if (r) {
580 dev_err(zd_chip_dev(chip),
581 "error ioread32(CR_REG1): %d\n", r);
582 return r;
583 }
584
585 dev_dbg_f(zd_chip_dev(chip),
586 "CR_REG1: 0x%02x -> 0x%02x\n", tmp, tmp | UNLOCK_PHY_REGS);
587 tmp |= UNLOCK_PHY_REGS;
588
589 r = zd_iowrite32_locked(chip, tmp, CR_REG1);
590 if (r)
591 dev_err(zd_chip_dev(chip), "error iowrite32(CR_REG1): %d\n", r);
592 return r;
593 }
594
595 /* CR157 can be optionally patched by the EEPROM */
596 static int patch_cr157(struct zd_chip *chip)
597 {
598 int r;
599 u32 value;
600
601 if (!chip->patch_cr157)
602 return 0;
603
604 r = zd_ioread32_locked(chip, &value, E2P_PHY_REG);
605 if (r)
606 return r;
607
608 dev_dbg_f(zd_chip_dev(chip), "patching value %x\n", value >> 8);
609 return zd_iowrite32_locked(chip, value >> 8, CR157);
610 }
611
612 /*
613 * 6M band edge can be optionally overwritten for certain RF's
614 * Vendor driver says: for FCC regulation, enabled per HWFeature 6M band edge
615 * bit (for AL2230, AL2230S)
616 */
617 static int patch_6m_band_edge(struct zd_chip *chip, int channel)
618 {
619 struct zd_ioreq16 ioreqs[] = {
620 { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 },
621 { CR47, 0x1e },
622 };
623
624 if (!chip->patch_6m_band_edge || !chip->rf.patch_6m_band_edge)
625 return 0;
626
627 /* FIXME: Channel 11 is not the edge for all regulatory domains. */
628 if (channel == 1 || channel == 11)
629 ioreqs[0].value = 0x12;
630
631 dev_dbg_f(zd_chip_dev(chip), "patching for channel %d\n", channel);
632 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
633 }
634
635 static int zd1211_hw_reset_phy(struct zd_chip *chip)
636 {
637 static const struct zd_ioreq16 ioreqs[] = {
638 { CR0, 0x0a }, { CR1, 0x06 }, { CR2, 0x26 },
639 { CR3, 0x38 }, { CR4, 0x80 }, { CR9, 0xa0 },
640 { CR10, 0x81 }, { CR11, 0x00 }, { CR12, 0x7f },
641 { CR13, 0x8c }, { CR14, 0x80 }, { CR15, 0x3d },
642 { CR16, 0x20 }, { CR17, 0x1e }, { CR18, 0x0a },
643 { CR19, 0x48 }, { CR20, 0x0c }, { CR21, 0x0c },
644 { CR22, 0x23 }, { CR23, 0x90 }, { CR24, 0x14 },
645 { CR25, 0x40 }, { CR26, 0x10 }, { CR27, 0x19 },
646 { CR28, 0x7f }, { CR29, 0x80 }, { CR30, 0x4b },
647 { CR31, 0x60 }, { CR32, 0x43 }, { CR33, 0x08 },
648 { CR34, 0x06 }, { CR35, 0x0a }, { CR36, 0x00 },
649 { CR37, 0x00 }, { CR38, 0x38 }, { CR39, 0x0c },
650 { CR40, 0x84 }, { CR41, 0x2a }, { CR42, 0x80 },
651 { CR43, 0x10 }, { CR44, 0x12 }, { CR46, 0xff },
652 { CR47, 0x1E }, { CR48, 0x26 }, { CR49, 0x5b },
653 { CR64, 0xd0 }, { CR65, 0x04 }, { CR66, 0x58 },
654 { CR67, 0xc9 }, { CR68, 0x88 }, { CR69, 0x41 },
655 { CR70, 0x23 }, { CR71, 0x10 }, { CR72, 0xff },
656 { CR73, 0x32 }, { CR74, 0x30 }, { CR75, 0x65 },
657 { CR76, 0x41 }, { CR77, 0x1b }, { CR78, 0x30 },
658 { CR79, 0x68 }, { CR80, 0x64 }, { CR81, 0x64 },
659 { CR82, 0x00 }, { CR83, 0x00 }, { CR84, 0x00 },
660 { CR85, 0x02 }, { CR86, 0x00 }, { CR87, 0x00 },
661 { CR88, 0xff }, { CR89, 0xfc }, { CR90, 0x00 },
662 { CR91, 0x00 }, { CR92, 0x00 }, { CR93, 0x08 },
663 { CR94, 0x00 }, { CR95, 0x00 }, { CR96, 0xff },
664 { CR97, 0xe7 }, { CR98, 0x00 }, { CR99, 0x00 },
665 { CR100, 0x00 }, { CR101, 0xae }, { CR102, 0x02 },
666 { CR103, 0x00 }, { CR104, 0x03 }, { CR105, 0x65 },
667 { CR106, 0x04 }, { CR107, 0x00 }, { CR108, 0x0a },
668 { CR109, 0xaa }, { CR110, 0xaa }, { CR111, 0x25 },
669 { CR112, 0x25 }, { CR113, 0x00 }, { CR119, 0x1e },
670 { CR125, 0x90 }, { CR126, 0x00 }, { CR127, 0x00 },
671 { },
672 { CR5, 0x00 }, { CR6, 0x00 }, { CR7, 0x00 },
673 { CR8, 0x00 }, { CR9, 0x20 }, { CR12, 0xf0 },
674 { CR20, 0x0e }, { CR21, 0x0e }, { CR27, 0x10 },
675 { CR44, 0x33 }, { CR47, 0x1E }, { CR83, 0x24 },
676 { CR84, 0x04 }, { CR85, 0x00 }, { CR86, 0x0C },
677 { CR87, 0x12 }, { CR88, 0x0C }, { CR89, 0x00 },
678 { CR90, 0x10 }, { CR91, 0x08 }, { CR93, 0x00 },
679 { CR94, 0x01 }, { CR95, 0x00 }, { CR96, 0x50 },
680 { CR97, 0x37 }, { CR98, 0x35 }, { CR101, 0x13 },
681 { CR102, 0x27 }, { CR103, 0x27 }, { CR104, 0x18 },
682 { CR105, 0x12 }, { CR109, 0x27 }, { CR110, 0x27 },
683 { CR111, 0x27 }, { CR112, 0x27 }, { CR113, 0x27 },
684 { CR114, 0x27 }, { CR115, 0x26 }, { CR116, 0x24 },
685 { CR117, 0xfc }, { CR118, 0xfa }, { CR120, 0x4f },
686 { CR123, 0x27 }, { CR125, 0xaa }, { CR127, 0x03 },
687 { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 },
688 { CR131, 0x0C }, { CR136, 0xdf }, { CR137, 0x40 },
689 { CR138, 0xa0 }, { CR139, 0xb0 }, { CR140, 0x99 },
690 { CR141, 0x82 }, { CR142, 0x54 }, { CR143, 0x1c },
691 { CR144, 0x6c }, { CR147, 0x07 }, { CR148, 0x4c },
692 { CR149, 0x50 }, { CR150, 0x0e }, { CR151, 0x18 },
693 { CR160, 0xfe }, { CR161, 0xee }, { CR162, 0xaa },
694 { CR163, 0xfa }, { CR164, 0xfa }, { CR165, 0xea },
695 { CR166, 0xbe }, { CR167, 0xbe }, { CR168, 0x6a },
696 { CR169, 0xba }, { CR170, 0xba }, { CR171, 0xba },
697 /* Note: CR204 must lead the CR203 */
698 { CR204, 0x7d },
699 { },
700 { CR203, 0x30 },
701 };
702
703 int r, t;
704
705 dev_dbg_f(zd_chip_dev(chip), "\n");
706
707 r = zd_chip_lock_phy_regs(chip);
708 if (r)
709 goto out;
710
711 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
712 if (r)
713 goto unlock;
714
715 r = patch_cr157(chip);
716 unlock:
717 t = zd_chip_unlock_phy_regs(chip);
718 if (t && !r)
719 r = t;
720 out:
721 return r;
722 }
723
724 static int zd1211b_hw_reset_phy(struct zd_chip *chip)
725 {
726 static const struct zd_ioreq16 ioreqs[] = {
727 { CR0, 0x14 }, { CR1, 0x06 }, { CR2, 0x26 },
728 { CR3, 0x38 }, { CR4, 0x80 }, { CR9, 0xe0 },
729 { CR10, 0x81 },
730 /* power control { { CR11, 1 << 6 }, */
731 { CR11, 0x00 },
732 { CR12, 0xf0 }, { CR13, 0x8c }, { CR14, 0x80 },
733 { CR15, 0x3d }, { CR16, 0x20 }, { CR17, 0x1e },
734 { CR18, 0x0a }, { CR19, 0x48 },
735 { CR20, 0x10 }, /* Org:0x0E, ComTrend:RalLink AP */
736 { CR21, 0x0e }, { CR22, 0x23 }, { CR23, 0x90 },
737 { CR24, 0x14 }, { CR25, 0x40 }, { CR26, 0x10 },
738 { CR27, 0x10 }, { CR28, 0x7f }, { CR29, 0x80 },
739 { CR30, 0x4b }, /* ASIC/FWT, no jointly decoder */
740 { CR31, 0x60 }, { CR32, 0x43 }, { CR33, 0x08 },
741 { CR34, 0x06 }, { CR35, 0x0a }, { CR36, 0x00 },
742 { CR37, 0x00 }, { CR38, 0x38 }, { CR39, 0x0c },
743 { CR40, 0x84 }, { CR41, 0x2a }, { CR42, 0x80 },
744 { CR43, 0x10 }, { CR44, 0x33 }, { CR46, 0xff },
745 { CR47, 0x1E }, { CR48, 0x26 }, { CR49, 0x5b },
746 { CR64, 0xd0 }, { CR65, 0x04 }, { CR66, 0x58 },
747 { CR67, 0xc9 }, { CR68, 0x88 }, { CR69, 0x41 },
748 { CR70, 0x23 }, { CR71, 0x10 }, { CR72, 0xff },
749 { CR73, 0x32 }, { CR74, 0x30 }, { CR75, 0x65 },
750 { CR76, 0x41 }, { CR77, 0x1b }, { CR78, 0x30 },
751 { CR79, 0xf0 }, { CR80, 0x64 }, { CR81, 0x64 },
752 { CR82, 0x00 }, { CR83, 0x24 }, { CR84, 0x04 },
753 { CR85, 0x00 }, { CR86, 0x0c }, { CR87, 0x12 },
754 { CR88, 0x0c }, { CR89, 0x00 }, { CR90, 0x58 },
755 { CR91, 0x04 }, { CR92, 0x00 }, { CR93, 0x00 },
756 { CR94, 0x01 },
757 { CR95, 0x20 }, /* ZD1211B */
758 { CR96, 0x50 }, { CR97, 0x37 }, { CR98, 0x35 },
759 { CR99, 0x00 }, { CR100, 0x01 }, { CR101, 0x13 },
760 { CR102, 0x27 }, { CR103, 0x27 }, { CR104, 0x18 },
761 { CR105, 0x12 }, { CR106, 0x04 }, { CR107, 0x00 },
762 { CR108, 0x0a }, { CR109, 0x27 }, { CR110, 0x27 },
763 { CR111, 0x27 }, { CR112, 0x27 }, { CR113, 0x27 },
764 { CR114, 0x27 }, { CR115, 0x26 }, { CR116, 0x24 },
765 { CR117, 0xfc }, { CR118, 0xfa }, { CR119, 0x1e },
766 { CR125, 0x90 }, { CR126, 0x00 }, { CR127, 0x00 },
767 { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 },
768 { CR131, 0x0c }, { CR136, 0xdf }, { CR137, 0xa0 },
769 { CR138, 0xa8 }, { CR139, 0xb4 }, { CR140, 0x98 },
770 { CR141, 0x82 }, { CR142, 0x53 }, { CR143, 0x1c },
771 { CR144, 0x6c }, { CR147, 0x07 }, { CR148, 0x40 },
772 { CR149, 0x40 }, /* Org:0x50 ComTrend:RalLink AP */
773 { CR150, 0x14 }, /* Org:0x0E ComTrend:RalLink AP */
774 { CR151, 0x18 }, { CR159, 0x70 }, { CR160, 0xfe },
775 { CR161, 0xee }, { CR162, 0xaa }, { CR163, 0xfa },
776 { CR164, 0xfa }, { CR165, 0xea }, { CR166, 0xbe },
777 { CR167, 0xbe }, { CR168, 0x6a }, { CR169, 0xba },
778 { CR170, 0xba }, { CR171, 0xba },
779 /* Note: CR204 must lead the CR203 */
780 { CR204, 0x7d },
781 {},
782 { CR203, 0x30 },
783 };
784
785 int r, t;
786
787 dev_dbg_f(zd_chip_dev(chip), "\n");
788
789 r = zd_chip_lock_phy_regs(chip);
790 if (r)
791 goto out;
792
793 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
794 if (r)
795 goto unlock;
796
797 r = patch_cr157(chip);
798 unlock:
799 t = zd_chip_unlock_phy_regs(chip);
800 if (t && !r)
801 r = t;
802 out:
803 return r;
804 }
805
806 static int hw_reset_phy(struct zd_chip *chip)
807 {
808 return chip->is_zd1211b ? zd1211b_hw_reset_phy(chip) :
809 zd1211_hw_reset_phy(chip);
810 }
811
812 static int zd1211_hw_init_hmac(struct zd_chip *chip)
813 {
814 static const struct zd_ioreq32 ioreqs[] = {
815 { CR_ZD1211_RETRY_MAX, 0x2 },
816 { CR_RX_THRESHOLD, 0x000c0640 },
817 };
818
819 dev_dbg_f(zd_chip_dev(chip), "\n");
820 ZD_ASSERT(mutex_is_locked(&chip->mutex));
821 return zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
822 }
823
824 static int zd1211b_hw_init_hmac(struct zd_chip *chip)
825 {
826 static const struct zd_ioreq32 ioreqs[] = {
827 { CR_ZD1211B_RETRY_MAX, 0x02020202 },
828 { CR_ZD1211B_TX_PWR_CTL4, 0x007f003f },
829 { CR_ZD1211B_TX_PWR_CTL3, 0x007f003f },
830 { CR_ZD1211B_TX_PWR_CTL2, 0x003f001f },
831 { CR_ZD1211B_TX_PWR_CTL1, 0x001f000f },
832 { CR_ZD1211B_AIFS_CTL1, 0x00280028 },
833 { CR_ZD1211B_AIFS_CTL2, 0x008C003C },
834 { CR_ZD1211B_TXOP, 0x01800824 },
835 { CR_RX_THRESHOLD, 0x000c0eff, },
836 };
837
838 dev_dbg_f(zd_chip_dev(chip), "\n");
839 ZD_ASSERT(mutex_is_locked(&chip->mutex));
840 return zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
841 }
842
843 static int hw_init_hmac(struct zd_chip *chip)
844 {
845 int r;
846 static const struct zd_ioreq32 ioreqs[] = {
847 { CR_ACK_TIMEOUT_EXT, 0x20 },
848 { CR_ADDA_MBIAS_WARMTIME, 0x30000808 },
849 { CR_SNIFFER_ON, 0 },
850 { CR_RX_FILTER, STA_RX_FILTER },
851 { CR_GROUP_HASH_P1, 0x00 },
852 { CR_GROUP_HASH_P2, 0x80000000 },
853 { CR_REG1, 0xa4 },
854 { CR_ADDA_PWR_DWN, 0x7f },
855 { CR_BCN_PLCP_CFG, 0x00f00401 },
856 { CR_PHY_DELAY, 0x00 },
857 { CR_ACK_TIMEOUT_EXT, 0x80 },
858 { CR_ADDA_PWR_DWN, 0x00 },
859 { CR_ACK_TIME_80211, 0x100 },
860 { CR_RX_PE_DELAY, 0x70 },
861 { CR_PS_CTRL, 0x10000000 },
862 { CR_RTS_CTS_RATE, 0x02030203 },
863 { CR_AFTER_PNP, 0x1 },
864 { CR_WEP_PROTECT, 0x114 },
865 { CR_IFS_VALUE, IFS_VALUE_DEFAULT },
866 };
867
868 ZD_ASSERT(mutex_is_locked(&chip->mutex));
869 r = zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
870 if (r)
871 return r;
872
873 return chip->is_zd1211b ?
874 zd1211b_hw_init_hmac(chip) : zd1211_hw_init_hmac(chip);
875 }
876
877 struct aw_pt_bi {
878 u32 atim_wnd_period;
879 u32 pre_tbtt;
880 u32 beacon_interval;
881 };
882
883 static int get_aw_pt_bi(struct zd_chip *chip, struct aw_pt_bi *s)
884 {
885 int r;
886 static const zd_addr_t aw_pt_bi_addr[] =
887 { CR_ATIM_WND_PERIOD, CR_PRE_TBTT, CR_BCN_INTERVAL };
888 u32 values[3];
889
890 r = zd_ioread32v_locked(chip, values, (const zd_addr_t *)aw_pt_bi_addr,
891 ARRAY_SIZE(aw_pt_bi_addr));
892 if (r) {
893 memset(s, 0, sizeof(*s));
894 return r;
895 }
896
897 s->atim_wnd_period = values[0];
898 s->pre_tbtt = values[1];
899 s->beacon_interval = values[2];
900 dev_dbg_f(zd_chip_dev(chip), "aw %u pt %u bi %u\n",
901 s->atim_wnd_period, s->pre_tbtt, s->beacon_interval);
902 return 0;
903 }
904
905 static int set_aw_pt_bi(struct zd_chip *chip, struct aw_pt_bi *s)
906 {
907 struct zd_ioreq32 reqs[3];
908
909 if (s->beacon_interval <= 5)
910 s->beacon_interval = 5;
911 if (s->pre_tbtt < 4 || s->pre_tbtt >= s->beacon_interval)
912 s->pre_tbtt = s->beacon_interval - 1;
913 if (s->atim_wnd_period >= s->pre_tbtt)
914 s->atim_wnd_period = s->pre_tbtt - 1;
915
916 reqs[0].addr = CR_ATIM_WND_PERIOD;
917 reqs[0].value = s->atim_wnd_period;
918 reqs[1].addr = CR_PRE_TBTT;
919 reqs[1].value = s->pre_tbtt;
920 reqs[2].addr = CR_BCN_INTERVAL;
921 reqs[2].value = s->beacon_interval;
922
923 dev_dbg_f(zd_chip_dev(chip),
924 "aw %u pt %u bi %u\n", s->atim_wnd_period, s->pre_tbtt,
925 s->beacon_interval);
926 return zd_iowrite32a_locked(chip, reqs, ARRAY_SIZE(reqs));
927 }
928
929
930 static int set_beacon_interval(struct zd_chip *chip, u32 interval)
931 {
932 int r;
933 struct aw_pt_bi s;
934
935 ZD_ASSERT(mutex_is_locked(&chip->mutex));
936 r = get_aw_pt_bi(chip, &s);
937 if (r)
938 return r;
939 s.beacon_interval = interval;
940 return set_aw_pt_bi(chip, &s);
941 }
942
943 int zd_set_beacon_interval(struct zd_chip *chip, u32 interval)
944 {
945 int r;
946
947 mutex_lock(&chip->mutex);
948 r = set_beacon_interval(chip, interval);
949 mutex_unlock(&chip->mutex);
950 return r;
951 }
952
953 static int hw_init(struct zd_chip *chip)
954 {
955 int r;
956
957 dev_dbg_f(zd_chip_dev(chip), "\n");
958 ZD_ASSERT(mutex_is_locked(&chip->mutex));
959 r = hw_reset_phy(chip);
960 if (r)
961 return r;
962
963 r = hw_init_hmac(chip);
964 if (r)
965 return r;
966
967 return set_beacon_interval(chip, 100);
968 }
969
970 static zd_addr_t fw_reg_addr(struct zd_chip *chip, u16 offset)
971 {
972 return (zd_addr_t)((u16)chip->fw_regs_base + offset);
973 }
974
975 #ifdef DEBUG
976 static int dump_cr(struct zd_chip *chip, const zd_addr_t addr,
977 const char *addr_string)
978 {
979 int r;
980 u32 value;
981
982 r = zd_ioread32_locked(chip, &value, addr);
983 if (r) {
984 dev_dbg_f(zd_chip_dev(chip),
985 "error reading %s. Error number %d\n", addr_string, r);
986 return r;
987 }
988
989 dev_dbg_f(zd_chip_dev(chip), "%s %#010x\n",
990 addr_string, (unsigned int)value);
991 return 0;
992 }
993
994 static int test_init(struct zd_chip *chip)
995 {
996 int r;
997
998 r = dump_cr(chip, CR_AFTER_PNP, "CR_AFTER_PNP");
999 if (r)
1000 return r;
1001 r = dump_cr(chip, CR_GPI_EN, "CR_GPI_EN");
1002 if (r)
1003 return r;
1004 return dump_cr(chip, CR_INTERRUPT, "CR_INTERRUPT");
1005 }
1006
1007 static void dump_fw_registers(struct zd_chip *chip)
1008 {
1009 const zd_addr_t addr[4] = {
1010 fw_reg_addr(chip, FW_REG_FIRMWARE_VER),
1011 fw_reg_addr(chip, FW_REG_USB_SPEED),
1012 fw_reg_addr(chip, FW_REG_FIX_TX_RATE),
1013 fw_reg_addr(chip, FW_REG_LED_LINK_STATUS),
1014 };
1015
1016 int r;
1017 u16 values[4];
1018
1019 r = zd_ioread16v_locked(chip, values, (const zd_addr_t*)addr,
1020 ARRAY_SIZE(addr));
1021 if (r) {
1022 dev_dbg_f(zd_chip_dev(chip), "error %d zd_ioread16v_locked\n",
1023 r);
1024 return;
1025 }
1026
1027 dev_dbg_f(zd_chip_dev(chip), "FW_FIRMWARE_VER %#06hx\n", values[0]);
1028 dev_dbg_f(zd_chip_dev(chip), "FW_USB_SPEED %#06hx\n", values[1]);
1029 dev_dbg_f(zd_chip_dev(chip), "FW_FIX_TX_RATE %#06hx\n", values[2]);
1030 dev_dbg_f(zd_chip_dev(chip), "FW_LINK_STATUS %#06hx\n", values[3]);
1031 }
1032 #endif /* DEBUG */
1033
1034 static int print_fw_version(struct zd_chip *chip)
1035 {
1036 int r;
1037 u16 version;
1038
1039 r = zd_ioread16_locked(chip, &version,
1040 fw_reg_addr(chip, FW_REG_FIRMWARE_VER));
1041 if (r)
1042 return r;
1043
1044 dev_info(zd_chip_dev(chip),"firmware version %04hx\n", version);
1045 return 0;
1046 }
1047
1048 static int set_mandatory_rates(struct zd_chip *chip, enum ieee80211_std std)
1049 {
1050 u32 rates;
1051 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1052 /* This sets the mandatory rates, which only depend from the standard
1053 * that the device is supporting. Until further notice we should try
1054 * to support 802.11g also for full speed USB.
1055 */
1056 switch (std) {
1057 case IEEE80211B:
1058 rates = CR_RATE_1M|CR_RATE_2M|CR_RATE_5_5M|CR_RATE_11M;
1059 break;
1060 case IEEE80211G:
1061 rates = CR_RATE_1M|CR_RATE_2M|CR_RATE_5_5M|CR_RATE_11M|
1062 CR_RATE_6M|CR_RATE_12M|CR_RATE_24M;
1063 break;
1064 default:
1065 return -EINVAL;
1066 }
1067 return zd_iowrite32_locked(chip, rates, CR_MANDATORY_RATE_TBL);
1068 }
1069
1070 int zd_chip_set_rts_cts_rate_locked(struct zd_chip *chip,
1071 u8 rts_rate, int preamble)
1072 {
1073 int rts_mod = ZD_RX_CCK;
1074 u32 value = 0;
1075
1076 /* Modulation bit */
1077 if (ZD_CS_TYPE(rts_rate) == ZD_CS_OFDM)
1078 rts_mod = ZD_RX_OFDM;
1079
1080 dev_dbg_f(zd_chip_dev(chip), "rts_rate=%x preamble=%x\n",
1081 rts_rate, preamble);
1082
1083 value |= rts_rate << RTSCTS_SH_RTS_RATE;
1084 value |= rts_mod << RTSCTS_SH_RTS_MOD_TYPE;
1085 value |= preamble << RTSCTS_SH_RTS_PMB_TYPE;
1086 value |= preamble << RTSCTS_SH_CTS_PMB_TYPE;
1087
1088 /* We always send 11M self-CTS messages, like the vendor driver. */
1089 value |= ZD_CCK_RATE_11M << RTSCTS_SH_CTS_RATE;
1090 value |= ZD_RX_CCK << RTSCTS_SH_CTS_MOD_TYPE;
1091
1092 return zd_iowrite32_locked(chip, value, CR_RTS_CTS_RATE);
1093 }
1094
1095 int zd_chip_enable_hwint(struct zd_chip *chip)
1096 {
1097 int r;
1098
1099 mutex_lock(&chip->mutex);
1100 r = zd_iowrite32_locked(chip, HWINT_ENABLED, CR_INTERRUPT);
1101 mutex_unlock(&chip->mutex);
1102 return r;
1103 }
1104
1105 static int disable_hwint(struct zd_chip *chip)
1106 {
1107 return zd_iowrite32_locked(chip, HWINT_DISABLED, CR_INTERRUPT);
1108 }
1109
1110 int zd_chip_disable_hwint(struct zd_chip *chip)
1111 {
1112 int r;
1113
1114 mutex_lock(&chip->mutex);
1115 r = disable_hwint(chip);
1116 mutex_unlock(&chip->mutex);
1117 return r;
1118 }
1119
1120 static int read_fw_regs_offset(struct zd_chip *chip)
1121 {
1122 int r;
1123
1124 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1125 r = zd_ioread16_locked(chip, (u16*)&chip->fw_regs_base,
1126 FWRAW_REGS_ADDR);
1127 if (r)
1128 return r;
1129 dev_dbg_f(zd_chip_dev(chip), "fw_regs_base: %#06hx\n",
1130 (u16)chip->fw_regs_base);
1131
1132 return 0;
1133 }
1134
1135
1136 int zd_chip_init_hw(struct zd_chip *chip, u8 device_type)
1137 {
1138 int r;
1139 u8 rf_type;
1140
1141 dev_dbg_f(zd_chip_dev(chip), "\n");
1142
1143 mutex_lock(&chip->mutex);
1144 chip->is_zd1211b = (device_type == DEVICE_ZD1211B) != 0;
1145
1146 #ifdef DEBUG
1147 r = test_init(chip);
1148 if (r)
1149 goto out;
1150 #endif
1151 r = zd_iowrite32_locked(chip, 1, CR_AFTER_PNP);
1152 if (r)
1153 goto out;
1154
1155 r = read_fw_regs_offset(chip);
1156 if (r)
1157 goto out;
1158
1159 /* GPI is always disabled, also in the other driver.
1160 */
1161 r = zd_iowrite32_locked(chip, 0, CR_GPI_EN);
1162 if (r)
1163 goto out;
1164 r = zd_iowrite32_locked(chip, CWIN_SIZE, CR_CWMIN_CWMAX);
1165 if (r)
1166 goto out;
1167 /* Currently we support IEEE 802.11g for full and high speed USB.
1168 * It might be discussed, whether we should suppport pure b mode for
1169 * full speed USB.
1170 */
1171 r = set_mandatory_rates(chip, IEEE80211G);
1172 if (r)
1173 goto out;
1174 /* Disabling interrupts is certainly a smart thing here.
1175 */
1176 r = disable_hwint(chip);
1177 if (r)
1178 goto out;
1179 r = read_pod(chip, &rf_type);
1180 if (r)
1181 goto out;
1182 r = hw_init(chip);
1183 if (r)
1184 goto out;
1185 r = zd_rf_init_hw(&chip->rf, rf_type);
1186 if (r)
1187 goto out;
1188
1189 r = print_fw_version(chip);
1190 if (r)
1191 goto out;
1192
1193 #ifdef DEBUG
1194 dump_fw_registers(chip);
1195 r = test_init(chip);
1196 if (r)
1197 goto out;
1198 #endif /* DEBUG */
1199
1200 r = read_e2p_mac_addr(chip);
1201 if (r)
1202 goto out;
1203
1204 r = read_cal_int_tables(chip);
1205 if (r)
1206 goto out;
1207
1208 print_id(chip);
1209 out:
1210 mutex_unlock(&chip->mutex);
1211 return r;
1212 }
1213
1214 static int update_pwr_int(struct zd_chip *chip, u8 channel)
1215 {
1216 u8 value = chip->pwr_int_values[channel - 1];
1217 dev_dbg_f(zd_chip_dev(chip), "channel %d pwr_int %#04x\n",
1218 channel, value);
1219 return zd_iowrite16_locked(chip, value, CR31);
1220 }
1221
1222 static int update_pwr_cal(struct zd_chip *chip, u8 channel)
1223 {
1224 u8 value = chip->pwr_cal_values[channel-1];
1225 dev_dbg_f(zd_chip_dev(chip), "channel %d pwr_cal %#04x\n",
1226 channel, value);
1227 return zd_iowrite16_locked(chip, value, CR68);
1228 }
1229
1230 static int update_ofdm_cal(struct zd_chip *chip, u8 channel)
1231 {
1232 struct zd_ioreq16 ioreqs[3];
1233
1234 ioreqs[0].addr = CR67;
1235 ioreqs[0].value = chip->ofdm_cal_values[OFDM_36M_INDEX][channel-1];
1236 ioreqs[1].addr = CR66;
1237 ioreqs[1].value = chip->ofdm_cal_values[OFDM_48M_INDEX][channel-1];
1238 ioreqs[2].addr = CR65;
1239 ioreqs[2].value = chip->ofdm_cal_values[OFDM_54M_INDEX][channel-1];
1240
1241 dev_dbg_f(zd_chip_dev(chip),
1242 "channel %d ofdm_cal 36M %#04x 48M %#04x 54M %#04x\n",
1243 channel, ioreqs[0].value, ioreqs[1].value, ioreqs[2].value);
1244 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1245 }
1246
1247 static int update_channel_integration_and_calibration(struct zd_chip *chip,
1248 u8 channel)
1249 {
1250 int r;
1251
1252 r = update_pwr_int(chip, channel);
1253 if (r)
1254 return r;
1255 if (chip->is_zd1211b) {
1256 static const struct zd_ioreq16 ioreqs[] = {
1257 { CR69, 0x28 },
1258 {},
1259 { CR69, 0x2a },
1260 };
1261
1262 r = update_ofdm_cal(chip, channel);
1263 if (r)
1264 return r;
1265 r = update_pwr_cal(chip, channel);
1266 if (r)
1267 return r;
1268 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1269 if (r)
1270 return r;
1271 }
1272
1273 return 0;
1274 }
1275
1276 /* The CCK baseband gain can be optionally patched by the EEPROM */
1277 static int patch_cck_gain(struct zd_chip *chip)
1278 {
1279 int r;
1280 u32 value;
1281
1282 if (!chip->patch_cck_gain)
1283 return 0;
1284
1285 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1286 r = zd_ioread32_locked(chip, &value, E2P_PHY_REG);
1287 if (r)
1288 return r;
1289 dev_dbg_f(zd_chip_dev(chip), "patching value %x\n", value & 0xff);
1290 return zd_iowrite16_locked(chip, value & 0xff, CR47);
1291 }
1292
1293 int zd_chip_set_channel(struct zd_chip *chip, u8 channel)
1294 {
1295 int r, t;
1296
1297 mutex_lock(&chip->mutex);
1298 r = zd_chip_lock_phy_regs(chip);
1299 if (r)
1300 goto out;
1301 r = zd_rf_set_channel(&chip->rf, channel);
1302 if (r)
1303 goto unlock;
1304 r = update_channel_integration_and_calibration(chip, channel);
1305 if (r)
1306 goto unlock;
1307 r = patch_cck_gain(chip);
1308 if (r)
1309 goto unlock;
1310 r = patch_6m_band_edge(chip, channel);
1311 if (r)
1312 goto unlock;
1313 r = zd_iowrite32_locked(chip, 0, CR_CONFIG_PHILIPS);
1314 unlock:
1315 t = zd_chip_unlock_phy_regs(chip);
1316 if (t && !r)
1317 r = t;
1318 out:
1319 mutex_unlock(&chip->mutex);
1320 return r;
1321 }
1322
1323 u8 zd_chip_get_channel(struct zd_chip *chip)
1324 {
1325 u8 channel;
1326
1327 mutex_lock(&chip->mutex);
1328 channel = chip->rf.channel;
1329 mutex_unlock(&chip->mutex);
1330 return channel;
1331 }
1332
1333 int zd_chip_control_leds(struct zd_chip *chip, enum led_status status)
1334 {
1335 const zd_addr_t a[] = {
1336 fw_reg_addr(chip, FW_REG_LED_LINK_STATUS),
1337 CR_LED,
1338 };
1339
1340 int r;
1341 u16 v[ARRAY_SIZE(a)];
1342 struct zd_ioreq16 ioreqs[ARRAY_SIZE(a)] = {
1343 [0] = { fw_reg_addr(chip, FW_REG_LED_LINK_STATUS) },
1344 [1] = { CR_LED },
1345 };
1346 u16 other_led;
1347
1348 mutex_lock(&chip->mutex);
1349 r = zd_ioread16v_locked(chip, v, (const zd_addr_t *)a, ARRAY_SIZE(a));
1350 if (r)
1351 goto out;
1352
1353 other_led = chip->link_led == LED1 ? LED2 : LED1;
1354
1355 switch (status) {
1356 case LED_OFF:
1357 ioreqs[0].value = FW_LINK_OFF;
1358 ioreqs[1].value = v[1] & ~(LED1|LED2);
1359 break;
1360 case LED_SCANNING:
1361 ioreqs[0].value = FW_LINK_OFF;
1362 ioreqs[1].value = v[1] & ~other_led;
1363 if (get_seconds() % 3 == 0) {
1364 ioreqs[1].value &= ~chip->link_led;
1365 } else {
1366 ioreqs[1].value |= chip->link_led;
1367 }
1368 break;
1369 case LED_ASSOCIATED:
1370 ioreqs[0].value = FW_LINK_TX;
1371 ioreqs[1].value = v[1] & ~other_led;
1372 ioreqs[1].value |= chip->link_led;
1373 break;
1374 default:
1375 r = -EINVAL;
1376 goto out;
1377 }
1378
1379 if (v[0] != ioreqs[0].value || v[1] != ioreqs[1].value) {
1380 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1381 if (r)
1382 goto out;
1383 }
1384 r = 0;
1385 out:
1386 mutex_unlock(&chip->mutex);
1387 return r;
1388 }
1389
1390 int zd_chip_set_basic_rates_locked(struct zd_chip *chip, u16 cr_rates)
1391 {
1392 ZD_ASSERT((cr_rates & ~(CR_RATES_80211B | CR_RATES_80211G)) == 0);
1393 dev_dbg_f(zd_chip_dev(chip), "%x\n", cr_rates);
1394
1395 return zd_iowrite32_locked(chip, cr_rates, CR_BASIC_RATE_TBL);
1396 }
1397
1398 static int ofdm_qual_db(u8 status_quality, u8 rate, unsigned int size)
1399 {
1400 static const u16 constants[] = {
1401 715, 655, 585, 540, 470, 410, 360, 315,
1402 270, 235, 205, 175, 150, 125, 105, 85,
1403 65, 50, 40, 25, 15
1404 };
1405
1406 int i;
1407 u32 x;
1408
1409 /* It seems that their quality parameter is somehow per signal
1410 * and is now transferred per bit.
1411 */
1412 switch (rate) {
1413 case ZD_OFDM_RATE_6M:
1414 case ZD_OFDM_RATE_12M:
1415 case ZD_OFDM_RATE_24M:
1416 size *= 2;
1417 break;
1418 case ZD_OFDM_RATE_9M:
1419 case ZD_OFDM_RATE_18M:
1420 case ZD_OFDM_RATE_36M:
1421 case ZD_OFDM_RATE_54M:
1422 size *= 4;
1423 size /= 3;
1424 break;
1425 case ZD_OFDM_RATE_48M:
1426 size *= 3;
1427 size /= 2;
1428 break;
1429 default:
1430 return -EINVAL;
1431 }
1432
1433 x = (10000 * status_quality)/size;
1434 for (i = 0; i < ARRAY_SIZE(constants); i++) {
1435 if (x > constants[i])
1436 break;
1437 }
1438
1439 switch (rate) {
1440 case ZD_OFDM_RATE_6M:
1441 case ZD_OFDM_RATE_9M:
1442 i += 3;
1443 break;
1444 case ZD_OFDM_RATE_12M:
1445 case ZD_OFDM_RATE_18M:
1446 i += 5;
1447 break;
1448 case ZD_OFDM_RATE_24M:
1449 case ZD_OFDM_RATE_36M:
1450 i += 9;
1451 break;
1452 case ZD_OFDM_RATE_48M:
1453 case ZD_OFDM_RATE_54M:
1454 i += 15;
1455 break;
1456 default:
1457 return -EINVAL;
1458 }
1459
1460 return i;
1461 }
1462
1463 static int ofdm_qual_percent(u8 status_quality, u8 rate, unsigned int size)
1464 {
1465 int r;
1466
1467 r = ofdm_qual_db(status_quality, rate, size);
1468 ZD_ASSERT(r >= 0);
1469 if (r < 0)
1470 r = 0;
1471
1472 r = (r * 100)/29;
1473 return r <= 100 ? r : 100;
1474 }
1475
1476 static unsigned int log10times100(unsigned int x)
1477 {
1478 static const u8 log10[] = {
1479 0,
1480 0, 30, 47, 60, 69, 77, 84, 90, 95, 100,
1481 104, 107, 111, 114, 117, 120, 123, 125, 127, 130,
1482 132, 134, 136, 138, 139, 141, 143, 144, 146, 147,
1483 149, 150, 151, 153, 154, 155, 156, 157, 159, 160,
1484 161, 162, 163, 164, 165, 166, 167, 168, 169, 169,
1485 170, 171, 172, 173, 174, 174, 175, 176, 177, 177,
1486 178, 179, 179, 180, 181, 181, 182, 183, 183, 184,
1487 185, 185, 186, 186, 187, 188, 188, 189, 189, 190,
1488 190, 191, 191, 192, 192, 193, 193, 194, 194, 195,
1489 195, 196, 196, 197, 197, 198, 198, 199, 199, 200,
1490 200, 200, 201, 201, 202, 202, 202, 203, 203, 204,
1491 204, 204, 205, 205, 206, 206, 206, 207, 207, 207,
1492 208, 208, 208, 209, 209, 210, 210, 210, 211, 211,
1493 211, 212, 212, 212, 213, 213, 213, 213, 214, 214,
1494 214, 215, 215, 215, 216, 216, 216, 217, 217, 217,
1495 217, 218, 218, 218, 219, 219, 219, 219, 220, 220,
1496 220, 220, 221, 221, 221, 222, 222, 222, 222, 223,
1497 223, 223, 223, 224, 224, 224, 224,
1498 };
1499
1500 return x < ARRAY_SIZE(log10) ? log10[x] : 225;
1501 }
1502
1503 enum {
1504 MAX_CCK_EVM_DB = 45,
1505 };
1506
1507 static int cck_evm_db(u8 status_quality)
1508 {
1509 return (20 * log10times100(status_quality)) / 100;
1510 }
1511
1512 static int cck_snr_db(u8 status_quality)
1513 {
1514 int r = MAX_CCK_EVM_DB - cck_evm_db(status_quality);
1515 ZD_ASSERT(r >= 0);
1516 return r;
1517 }
1518
1519 static int cck_qual_percent(u8 status_quality)
1520 {
1521 int r;
1522
1523 r = cck_snr_db(status_quality);
1524 r = (100*r)/17;
1525 return r <= 100 ? r : 100;
1526 }
1527
1528 u8 zd_rx_qual_percent(const void *rx_frame, unsigned int size,
1529 const struct rx_status *status)
1530 {
1531 return (status->frame_status&ZD_RX_OFDM) ?
1532 ofdm_qual_percent(status->signal_quality_ofdm,
1533 zd_ofdm_plcp_header_rate(rx_frame),
1534 size) :
1535 cck_qual_percent(status->signal_quality_cck);
1536 }
1537
1538 u8 zd_rx_strength_percent(u8 rssi)
1539 {
1540 int r = (rssi*100) / 41;
1541 if (r > 100)
1542 r = 100;
1543 return (u8) r;
1544 }
1545
1546 u16 zd_rx_rate(const void *rx_frame, const struct rx_status *status)
1547 {
1548 static const u16 ofdm_rates[] = {
1549 [ZD_OFDM_RATE_6M] = 60,
1550 [ZD_OFDM_RATE_9M] = 90,
1551 [ZD_OFDM_RATE_12M] = 120,
1552 [ZD_OFDM_RATE_18M] = 180,
1553 [ZD_OFDM_RATE_24M] = 240,
1554 [ZD_OFDM_RATE_36M] = 360,
1555 [ZD_OFDM_RATE_48M] = 480,
1556 [ZD_OFDM_RATE_54M] = 540,
1557 };
1558 u16 rate;
1559 if (status->frame_status & ZD_RX_OFDM) {
1560 u8 ofdm_rate = zd_ofdm_plcp_header_rate(rx_frame);
1561 rate = ofdm_rates[ofdm_rate & 0xf];
1562 } else {
1563 u8 cck_rate = zd_cck_plcp_header_rate(rx_frame);
1564 switch (cck_rate) {
1565 case ZD_CCK_SIGNAL_1M:
1566 rate = 10;
1567 break;
1568 case ZD_CCK_SIGNAL_2M:
1569 rate = 20;
1570 break;
1571 case ZD_CCK_SIGNAL_5M5:
1572 rate = 55;
1573 break;
1574 case ZD_CCK_SIGNAL_11M:
1575 rate = 110;
1576 break;
1577 default:
1578 rate = 0;
1579 }
1580 }
1581
1582 return rate;
1583 }
1584
1585 int zd_chip_switch_radio_on(struct zd_chip *chip)
1586 {
1587 int r;
1588
1589 mutex_lock(&chip->mutex);
1590 r = zd_switch_radio_on(&chip->rf);
1591 mutex_unlock(&chip->mutex);
1592 return r;
1593 }
1594
1595 int zd_chip_switch_radio_off(struct zd_chip *chip)
1596 {
1597 int r;
1598
1599 mutex_lock(&chip->mutex);
1600 r = zd_switch_radio_off(&chip->rf);
1601 mutex_unlock(&chip->mutex);
1602 return r;
1603 }
1604
1605 int zd_chip_enable_int(struct zd_chip *chip)
1606 {
1607 int r;
1608
1609 mutex_lock(&chip->mutex);
1610 r = zd_usb_enable_int(&chip->usb);
1611 mutex_unlock(&chip->mutex);
1612 return r;
1613 }
1614
1615 void zd_chip_disable_int(struct zd_chip *chip)
1616 {
1617 mutex_lock(&chip->mutex);
1618 zd_usb_disable_int(&chip->usb);
1619 mutex_unlock(&chip->mutex);
1620 }
1621
1622 int zd_chip_enable_rx(struct zd_chip *chip)
1623 {
1624 int r;
1625
1626 mutex_lock(&chip->mutex);
1627 r = zd_usb_enable_rx(&chip->usb);
1628 mutex_unlock(&chip->mutex);
1629 return r;
1630 }
1631
1632 void zd_chip_disable_rx(struct zd_chip *chip)
1633 {
1634 mutex_lock(&chip->mutex);
1635 zd_usb_disable_rx(&chip->usb);
1636 mutex_unlock(&chip->mutex);
1637 }
1638
1639 int zd_rfwritev_locked(struct zd_chip *chip,
1640 const u32* values, unsigned int count, u8 bits)
1641 {
1642 int r;
1643 unsigned int i;
1644
1645 for (i = 0; i < count; i++) {
1646 r = zd_rfwrite_locked(chip, values[i], bits);
1647 if (r)
1648 return r;
1649 }
1650
1651 return 0;
1652 }
1653
1654 /*
1655 * We can optionally program the RF directly through CR regs, if supported by
1656 * the hardware. This is much faster than the older method.
1657 */
1658 int zd_rfwrite_cr_locked(struct zd_chip *chip, u32 value)
1659 {
1660 struct zd_ioreq16 ioreqs[] = {
1661 { CR244, (value >> 16) & 0xff },
1662 { CR243, (value >> 8) & 0xff },
1663 { CR242, value & 0xff },
1664 };
1665 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1666 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1667 }
1668
1669 int zd_rfwritev_cr_locked(struct zd_chip *chip,
1670 const u32 *values, unsigned int count)
1671 {
1672 int r;
1673 unsigned int i;
1674
1675 for (i = 0; i < count; i++) {
1676 r = zd_rfwrite_cr_locked(chip, values[i]);
1677 if (r)
1678 return r;
1679 }
1680
1681 return 0;
1682 }
1683
1684 int zd_chip_set_multicast_hash(struct zd_chip *chip,
1685 struct zd_mc_hash *hash)
1686 {
1687 struct zd_ioreq32 ioreqs[] = {
1688 { CR_GROUP_HASH_P1, hash->low },
1689 { CR_GROUP_HASH_P2, hash->high },
1690 };
1691
1692 dev_dbg_f(zd_chip_dev(chip), "hash l 0x%08x h 0x%08x\n",
1693 ioreqs[0].value, ioreqs[1].value);
1694 return zd_iowrite32a(chip, ioreqs, ARRAY_SIZE(ioreqs));
1695 }
Linux kernel - Deliverables
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