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zd1211rw: cancel process_intr work on zd_chip_disable_int()
[deliverable/linux.git] / drivers / net / wireless / zd1211rw / zd_chip.c
1 /* ZD1211 USB-WLAN driver for Linux
2 *
3 * Copyright (C) 2005-2007 Ulrich Kunitz <kune@deine-taler.de>
4 * Copyright (C) 2006-2007 Daniel Drake <dsd@gentoo.org>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21 /* This file implements all the hardware specific functions for the ZD1211
22 * and ZD1211B chips. Support for the ZD1211B was possible after Timothy
23 * Legge sent me a ZD1211B device. Thank you Tim. -- Uli
24 */
25
26 #include <linux/kernel.h>
27 #include <linux/errno.h>
28 #include <linux/slab.h>
29
30 #include "zd_def.h"
31 #include "zd_chip.h"
32 #include "zd_mac.h"
33 #include "zd_rf.h"
34
35 void zd_chip_init(struct zd_chip *chip,
36 struct ieee80211_hw *hw,
37 struct usb_interface *intf)
38 {
39 memset(chip, 0, sizeof(*chip));
40 mutex_init(&chip->mutex);
41 zd_usb_init(&chip->usb, hw, intf);
42 zd_rf_init(&chip->rf);
43 }
44
45 void zd_chip_clear(struct zd_chip *chip)
46 {
47 ZD_ASSERT(!mutex_is_locked(&chip->mutex));
48 zd_usb_clear(&chip->usb);
49 zd_rf_clear(&chip->rf);
50 mutex_destroy(&chip->mutex);
51 ZD_MEMCLEAR(chip, sizeof(*chip));
52 }
53
54 static int scnprint_mac_oui(struct zd_chip *chip, char *buffer, size_t size)
55 {
56 u8 *addr = zd_mac_get_perm_addr(zd_chip_to_mac(chip));
57 return scnprintf(buffer, size, "%02x-%02x-%02x",
58 addr[0], addr[1], addr[2]);
59 }
60
61 /* Prints an identifier line, which will support debugging. */
62 static int scnprint_id(struct zd_chip *chip, char *buffer, size_t size)
63 {
64 int i = 0;
65
66 i = scnprintf(buffer, size, "zd1211%s chip ",
67 zd_chip_is_zd1211b(chip) ? "b" : "");
68 i += zd_usb_scnprint_id(&chip->usb, buffer+i, size-i);
69 i += scnprintf(buffer+i, size-i, " ");
70 i += scnprint_mac_oui(chip, buffer+i, size-i);
71 i += scnprintf(buffer+i, size-i, " ");
72 i += zd_rf_scnprint_id(&chip->rf, buffer+i, size-i);
73 i += scnprintf(buffer+i, size-i, " pa%1x %c%c%c%c%c", chip->pa_type,
74 chip->patch_cck_gain ? 'g' : '-',
75 chip->patch_cr157 ? '7' : '-',
76 chip->patch_6m_band_edge ? '6' : '-',
77 chip->new_phy_layout ? 'N' : '-',
78 chip->al2230s_bit ? 'S' : '-');
79 return i;
80 }
81
82 static void print_id(struct zd_chip *chip)
83 {
84 char buffer[80];
85
86 scnprint_id(chip, buffer, sizeof(buffer));
87 buffer[sizeof(buffer)-1] = 0;
88 dev_info(zd_chip_dev(chip), "%s\n", buffer);
89 }
90
91 static zd_addr_t inc_addr(zd_addr_t addr)
92 {
93 u16 a = (u16)addr;
94 /* Control registers use byte addressing, but everything else uses word
95 * addressing. */
96 if ((a & 0xf000) == CR_START)
97 a += 2;
98 else
99 a += 1;
100 return (zd_addr_t)a;
101 }
102
103 /* Read a variable number of 32-bit values. Parameter count is not allowed to
104 * exceed USB_MAX_IOREAD32_COUNT.
105 */
106 int zd_ioread32v_locked(struct zd_chip *chip, u32 *values, const zd_addr_t *addr,
107 unsigned int count)
108 {
109 int r;
110 int i;
111 zd_addr_t *a16;
112 u16 *v16;
113 unsigned int count16;
114
115 if (count > USB_MAX_IOREAD32_COUNT)
116 return -EINVAL;
117
118 /* Allocate a single memory block for values and addresses. */
119 count16 = 2*count;
120 /* zd_addr_t is __nocast, so the kmalloc needs an explicit cast */
121 a16 = (zd_addr_t *) kmalloc(count16 * (sizeof(zd_addr_t) + sizeof(u16)),
122 GFP_KERNEL);
123 if (!a16) {
124 dev_dbg_f(zd_chip_dev(chip),
125 "error ENOMEM in allocation of a16\n");
126 r = -ENOMEM;
127 goto out;
128 }
129 v16 = (u16 *)(a16 + count16);
130
131 for (i = 0; i < count; i++) {
132 int j = 2*i;
133 /* We read the high word always first. */
134 a16[j] = inc_addr(addr[i]);
135 a16[j+1] = addr[i];
136 }
137
138 r = zd_ioread16v_locked(chip, v16, a16, count16);
139 if (r) {
140 dev_dbg_f(zd_chip_dev(chip),
141 "error: zd_ioread16v_locked. Error number %d\n", r);
142 goto out;
143 }
144
145 for (i = 0; i < count; i++) {
146 int j = 2*i;
147 values[i] = (v16[j] << 16) | v16[j+1];
148 }
149
150 out:
151 kfree((void *)a16);
152 return r;
153 }
154
155 int _zd_iowrite32v_locked(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs,
156 unsigned int count)
157 {
158 int i, j, r;
159 struct zd_ioreq16 *ioreqs16;
160 unsigned int count16;
161
162 ZD_ASSERT(mutex_is_locked(&chip->mutex));
163
164 if (count == 0)
165 return 0;
166 if (count > USB_MAX_IOWRITE32_COUNT)
167 return -EINVAL;
168
169 /* Allocate a single memory block for values and addresses. */
170 count16 = 2*count;
171 ioreqs16 = kmalloc(count16 * sizeof(struct zd_ioreq16), GFP_KERNEL);
172 if (!ioreqs16) {
173 r = -ENOMEM;
174 dev_dbg_f(zd_chip_dev(chip),
175 "error %d in ioreqs16 allocation\n", r);
176 goto out;
177 }
178
179 for (i = 0; i < count; i++) {
180 j = 2*i;
181 /* We write the high word always first. */
182 ioreqs16[j].value = ioreqs[i].value >> 16;
183 ioreqs16[j].addr = inc_addr(ioreqs[i].addr);
184 ioreqs16[j+1].value = ioreqs[i].value;
185 ioreqs16[j+1].addr = ioreqs[i].addr;
186 }
187
188 r = zd_usb_iowrite16v(&chip->usb, ioreqs16, count16);
189 #ifdef DEBUG
190 if (r) {
191 dev_dbg_f(zd_chip_dev(chip),
192 "error %d in zd_usb_write16v\n", r);
193 }
194 #endif /* DEBUG */
195 out:
196 kfree(ioreqs16);
197 return r;
198 }
199
200 int zd_iowrite16a_locked(struct zd_chip *chip,
201 const struct zd_ioreq16 *ioreqs, unsigned int count)
202 {
203 int r;
204 unsigned int i, j, t, max;
205
206 ZD_ASSERT(mutex_is_locked(&chip->mutex));
207 for (i = 0; i < count; i += j + t) {
208 t = 0;
209 max = count-i;
210 if (max > USB_MAX_IOWRITE16_COUNT)
211 max = USB_MAX_IOWRITE16_COUNT;
212 for (j = 0; j < max; j++) {
213 if (!ioreqs[i+j].addr) {
214 t = 1;
215 break;
216 }
217 }
218
219 r = zd_usb_iowrite16v(&chip->usb, &ioreqs[i], j);
220 if (r) {
221 dev_dbg_f(zd_chip_dev(chip),
222 "error zd_usb_iowrite16v. Error number %d\n",
223 r);
224 return r;
225 }
226 }
227
228 return 0;
229 }
230
231 /* Writes a variable number of 32 bit registers. The functions will split
232 * that in several USB requests. A split can be forced by inserting an IO
233 * request with an zero address field.
234 */
235 int zd_iowrite32a_locked(struct zd_chip *chip,
236 const struct zd_ioreq32 *ioreqs, unsigned int count)
237 {
238 int r;
239 unsigned int i, j, t, max;
240
241 for (i = 0; i < count; i += j + t) {
242 t = 0;
243 max = count-i;
244 if (max > USB_MAX_IOWRITE32_COUNT)
245 max = USB_MAX_IOWRITE32_COUNT;
246 for (j = 0; j < max; j++) {
247 if (!ioreqs[i+j].addr) {
248 t = 1;
249 break;
250 }
251 }
252
253 r = _zd_iowrite32v_locked(chip, &ioreqs[i], j);
254 if (r) {
255 dev_dbg_f(zd_chip_dev(chip),
256 "error _zd_iowrite32v_locked."
257 " Error number %d\n", r);
258 return r;
259 }
260 }
261
262 return 0;
263 }
264
265 int zd_ioread16(struct zd_chip *chip, zd_addr_t addr, u16 *value)
266 {
267 int r;
268
269 mutex_lock(&chip->mutex);
270 r = zd_ioread16_locked(chip, value, addr);
271 mutex_unlock(&chip->mutex);
272 return r;
273 }
274
275 int zd_ioread32(struct zd_chip *chip, zd_addr_t addr, u32 *value)
276 {
277 int r;
278
279 mutex_lock(&chip->mutex);
280 r = zd_ioread32_locked(chip, value, addr);
281 mutex_unlock(&chip->mutex);
282 return r;
283 }
284
285 int zd_iowrite16(struct zd_chip *chip, zd_addr_t addr, u16 value)
286 {
287 int r;
288
289 mutex_lock(&chip->mutex);
290 r = zd_iowrite16_locked(chip, value, addr);
291 mutex_unlock(&chip->mutex);
292 return r;
293 }
294
295 int zd_iowrite32(struct zd_chip *chip, zd_addr_t addr, u32 value)
296 {
297 int r;
298
299 mutex_lock(&chip->mutex);
300 r = zd_iowrite32_locked(chip, value, addr);
301 mutex_unlock(&chip->mutex);
302 return r;
303 }
304
305 int zd_ioread32v(struct zd_chip *chip, const zd_addr_t *addresses,
306 u32 *values, unsigned int count)
307 {
308 int r;
309
310 mutex_lock(&chip->mutex);
311 r = zd_ioread32v_locked(chip, values, addresses, count);
312 mutex_unlock(&chip->mutex);
313 return r;
314 }
315
316 int zd_iowrite32a(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs,
317 unsigned int count)
318 {
319 int r;
320
321 mutex_lock(&chip->mutex);
322 r = zd_iowrite32a_locked(chip, ioreqs, count);
323 mutex_unlock(&chip->mutex);
324 return r;
325 }
326
327 static int read_pod(struct zd_chip *chip, u8 *rf_type)
328 {
329 int r;
330 u32 value;
331
332 ZD_ASSERT(mutex_is_locked(&chip->mutex));
333 r = zd_ioread32_locked(chip, &value, E2P_POD);
334 if (r)
335 goto error;
336 dev_dbg_f(zd_chip_dev(chip), "E2P_POD %#010x\n", value);
337
338 /* FIXME: AL2230 handling (Bit 7 in POD) */
339 *rf_type = value & 0x0f;
340 chip->pa_type = (value >> 16) & 0x0f;
341 chip->patch_cck_gain = (value >> 8) & 0x1;
342 chip->patch_cr157 = (value >> 13) & 0x1;
343 chip->patch_6m_band_edge = (value >> 21) & 0x1;
344 chip->new_phy_layout = (value >> 31) & 0x1;
345 chip->al2230s_bit = (value >> 7) & 0x1;
346 chip->link_led = ((value >> 4) & 1) ? LED1 : LED2;
347 chip->supports_tx_led = 1;
348 if (value & (1 << 24)) { /* LED scenario */
349 if (value & (1 << 29))
350 chip->supports_tx_led = 0;
351 }
352
353 dev_dbg_f(zd_chip_dev(chip),
354 "RF %s %#01x PA type %#01x patch CCK %d patch CR157 %d "
355 "patch 6M %d new PHY %d link LED%d tx led %d\n",
356 zd_rf_name(*rf_type), *rf_type,
357 chip->pa_type, chip->patch_cck_gain,
358 chip->patch_cr157, chip->patch_6m_band_edge,
359 chip->new_phy_layout,
360 chip->link_led == LED1 ? 1 : 2,
361 chip->supports_tx_led);
362 return 0;
363 error:
364 *rf_type = 0;
365 chip->pa_type = 0;
366 chip->patch_cck_gain = 0;
367 chip->patch_cr157 = 0;
368 chip->patch_6m_band_edge = 0;
369 chip->new_phy_layout = 0;
370 return r;
371 }
372
373 /* MAC address: if custom mac addresses are to be used CR_MAC_ADDR_P1 and
374 * CR_MAC_ADDR_P2 must be overwritten
375 */
376 int zd_write_mac_addr(struct zd_chip *chip, const u8 *mac_addr)
377 {
378 int r;
379 struct zd_ioreq32 reqs[2] = {
380 [0] = { .addr = CR_MAC_ADDR_P1 },
381 [1] = { .addr = CR_MAC_ADDR_P2 },
382 };
383
384 if (mac_addr) {
385 reqs[0].value = (mac_addr[3] << 24)
386 | (mac_addr[2] << 16)
387 | (mac_addr[1] << 8)
388 | mac_addr[0];
389 reqs[1].value = (mac_addr[5] << 8)
390 | mac_addr[4];
391 dev_dbg_f(zd_chip_dev(chip), "mac addr %pM\n", mac_addr);
392 } else {
393 dev_dbg_f(zd_chip_dev(chip), "set NULL mac\n");
394 }
395
396 mutex_lock(&chip->mutex);
397 r = zd_iowrite32a_locked(chip, reqs, ARRAY_SIZE(reqs));
398 mutex_unlock(&chip->mutex);
399 return r;
400 }
401
402 int zd_read_regdomain(struct zd_chip *chip, u8 *regdomain)
403 {
404 int r;
405 u32 value;
406
407 mutex_lock(&chip->mutex);
408 r = zd_ioread32_locked(chip, &value, E2P_SUBID);
409 mutex_unlock(&chip->mutex);
410 if (r)
411 return r;
412
413 *regdomain = value >> 16;
414 dev_dbg_f(zd_chip_dev(chip), "regdomain: %#04x\n", *regdomain);
415
416 return 0;
417 }
418
419 static int read_values(struct zd_chip *chip, u8 *values, size_t count,
420 zd_addr_t e2p_addr, u32 guard)
421 {
422 int r;
423 int i;
424 u32 v;
425
426 ZD_ASSERT(mutex_is_locked(&chip->mutex));
427 for (i = 0;;) {
428 r = zd_ioread32_locked(chip, &v,
429 (zd_addr_t)((u16)e2p_addr+i/2));
430 if (r)
431 return r;
432 v -= guard;
433 if (i+4 < count) {
434 values[i++] = v;
435 values[i++] = v >> 8;
436 values[i++] = v >> 16;
437 values[i++] = v >> 24;
438 continue;
439 }
440 for (;i < count; i++)
441 values[i] = v >> (8*(i%3));
442 return 0;
443 }
444 }
445
446 static int read_pwr_cal_values(struct zd_chip *chip)
447 {
448 return read_values(chip, chip->pwr_cal_values,
449 E2P_CHANNEL_COUNT, E2P_PWR_CAL_VALUE1,
450 0);
451 }
452
453 static int read_pwr_int_values(struct zd_chip *chip)
454 {
455 return read_values(chip, chip->pwr_int_values,
456 E2P_CHANNEL_COUNT, E2P_PWR_INT_VALUE1,
457 E2P_PWR_INT_GUARD);
458 }
459
460 static int read_ofdm_cal_values(struct zd_chip *chip)
461 {
462 int r;
463 int i;
464 static const zd_addr_t addresses[] = {
465 E2P_36M_CAL_VALUE1,
466 E2P_48M_CAL_VALUE1,
467 E2P_54M_CAL_VALUE1,
468 };
469
470 for (i = 0; i < 3; i++) {
471 r = read_values(chip, chip->ofdm_cal_values[i],
472 E2P_CHANNEL_COUNT, addresses[i], 0);
473 if (r)
474 return r;
475 }
476 return 0;
477 }
478
479 static int read_cal_int_tables(struct zd_chip *chip)
480 {
481 int r;
482
483 r = read_pwr_cal_values(chip);
484 if (r)
485 return r;
486 r = read_pwr_int_values(chip);
487 if (r)
488 return r;
489 r = read_ofdm_cal_values(chip);
490 if (r)
491 return r;
492 return 0;
493 }
494
495 /* phy means physical registers */
496 int zd_chip_lock_phy_regs(struct zd_chip *chip)
497 {
498 int r;
499 u32 tmp;
500
501 ZD_ASSERT(mutex_is_locked(&chip->mutex));
502 r = zd_ioread32_locked(chip, &tmp, CR_REG1);
503 if (r) {
504 dev_err(zd_chip_dev(chip), "error ioread32(CR_REG1): %d\n", r);
505 return r;
506 }
507
508 tmp &= ~UNLOCK_PHY_REGS;
509
510 r = zd_iowrite32_locked(chip, tmp, CR_REG1);
511 if (r)
512 dev_err(zd_chip_dev(chip), "error iowrite32(CR_REG1): %d\n", r);
513 return r;
514 }
515
516 int zd_chip_unlock_phy_regs(struct zd_chip *chip)
517 {
518 int r;
519 u32 tmp;
520
521 ZD_ASSERT(mutex_is_locked(&chip->mutex));
522 r = zd_ioread32_locked(chip, &tmp, CR_REG1);
523 if (r) {
524 dev_err(zd_chip_dev(chip),
525 "error ioread32(CR_REG1): %d\n", r);
526 return r;
527 }
528
529 tmp |= UNLOCK_PHY_REGS;
530
531 r = zd_iowrite32_locked(chip, tmp, CR_REG1);
532 if (r)
533 dev_err(zd_chip_dev(chip), "error iowrite32(CR_REG1): %d\n", r);
534 return r;
535 }
536
537 /* CR157 can be optionally patched by the EEPROM for original ZD1211 */
538 static int patch_cr157(struct zd_chip *chip)
539 {
540 int r;
541 u16 value;
542
543 if (!chip->patch_cr157)
544 return 0;
545
546 r = zd_ioread16_locked(chip, &value, E2P_PHY_REG);
547 if (r)
548 return r;
549
550 dev_dbg_f(zd_chip_dev(chip), "patching value %x\n", value >> 8);
551 return zd_iowrite32_locked(chip, value >> 8, CR157);
552 }
553
554 /*
555 * 6M band edge can be optionally overwritten for certain RF's
556 * Vendor driver says: for FCC regulation, enabled per HWFeature 6M band edge
557 * bit (for AL2230, AL2230S)
558 */
559 static int patch_6m_band_edge(struct zd_chip *chip, u8 channel)
560 {
561 ZD_ASSERT(mutex_is_locked(&chip->mutex));
562 if (!chip->patch_6m_band_edge)
563 return 0;
564
565 return zd_rf_patch_6m_band_edge(&chip->rf, channel);
566 }
567
568 /* Generic implementation of 6M band edge patching, used by most RFs via
569 * zd_rf_generic_patch_6m() */
570 int zd_chip_generic_patch_6m_band(struct zd_chip *chip, int channel)
571 {
572 struct zd_ioreq16 ioreqs[] = {
573 { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 },
574 { CR47, 0x1e },
575 };
576
577 /* FIXME: Channel 11 is not the edge for all regulatory domains. */
578 if (channel == 1 || channel == 11)
579 ioreqs[0].value = 0x12;
580
581 dev_dbg_f(zd_chip_dev(chip), "patching for channel %d\n", channel);
582 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
583 }
584
585 static int zd1211_hw_reset_phy(struct zd_chip *chip)
586 {
587 static const struct zd_ioreq16 ioreqs[] = {
588 { CR0, 0x0a }, { CR1, 0x06 }, { CR2, 0x26 },
589 { CR3, 0x38 }, { CR4, 0x80 }, { CR9, 0xa0 },
590 { CR10, 0x81 }, { CR11, 0x00 }, { CR12, 0x7f },
591 { CR13, 0x8c }, { CR14, 0x80 }, { CR15, 0x3d },
592 { CR16, 0x20 }, { CR17, 0x1e }, { CR18, 0x0a },
593 { CR19, 0x48 }, { CR20, 0x0c }, { CR21, 0x0c },
594 { CR22, 0x23 }, { CR23, 0x90 }, { CR24, 0x14 },
595 { CR25, 0x40 }, { CR26, 0x10 }, { CR27, 0x19 },
596 { CR28, 0x7f }, { CR29, 0x80 }, { CR30, 0x4b },
597 { CR31, 0x60 }, { CR32, 0x43 }, { CR33, 0x08 },
598 { CR34, 0x06 }, { CR35, 0x0a }, { CR36, 0x00 },
599 { CR37, 0x00 }, { CR38, 0x38 }, { CR39, 0x0c },
600 { CR40, 0x84 }, { CR41, 0x2a }, { CR42, 0x80 },
601 { CR43, 0x10 }, { CR44, 0x12 }, { CR46, 0xff },
602 { CR47, 0x1E }, { CR48, 0x26 }, { CR49, 0x5b },
603 { CR64, 0xd0 }, { CR65, 0x04 }, { CR66, 0x58 },
604 { CR67, 0xc9 }, { CR68, 0x88 }, { CR69, 0x41 },
605 { CR70, 0x23 }, { CR71, 0x10 }, { CR72, 0xff },
606 { CR73, 0x32 }, { CR74, 0x30 }, { CR75, 0x65 },
607 { CR76, 0x41 }, { CR77, 0x1b }, { CR78, 0x30 },
608 { CR79, 0x68 }, { CR80, 0x64 }, { CR81, 0x64 },
609 { CR82, 0x00 }, { CR83, 0x00 }, { CR84, 0x00 },
610 { CR85, 0x02 }, { CR86, 0x00 }, { CR87, 0x00 },
611 { CR88, 0xff }, { CR89, 0xfc }, { CR90, 0x00 },
612 { CR91, 0x00 }, { CR92, 0x00 }, { CR93, 0x08 },
613 { CR94, 0x00 }, { CR95, 0x00 }, { CR96, 0xff },
614 { CR97, 0xe7 }, { CR98, 0x00 }, { CR99, 0x00 },
615 { CR100, 0x00 }, { CR101, 0xae }, { CR102, 0x02 },
616 { CR103, 0x00 }, { CR104, 0x03 }, { CR105, 0x65 },
617 { CR106, 0x04 }, { CR107, 0x00 }, { CR108, 0x0a },
618 { CR109, 0xaa }, { CR110, 0xaa }, { CR111, 0x25 },
619 { CR112, 0x25 }, { CR113, 0x00 }, { CR119, 0x1e },
620 { CR125, 0x90 }, { CR126, 0x00 }, { CR127, 0x00 },
621 { },
622 { CR5, 0x00 }, { CR6, 0x00 }, { CR7, 0x00 },
623 { CR8, 0x00 }, { CR9, 0x20 }, { CR12, 0xf0 },
624 { CR20, 0x0e }, { CR21, 0x0e }, { CR27, 0x10 },
625 { CR44, 0x33 }, { CR47, 0x1E }, { CR83, 0x24 },
626 { CR84, 0x04 }, { CR85, 0x00 }, { CR86, 0x0C },
627 { CR87, 0x12 }, { CR88, 0x0C }, { CR89, 0x00 },
628 { CR90, 0x10 }, { CR91, 0x08 }, { CR93, 0x00 },
629 { CR94, 0x01 }, { CR95, 0x00 }, { CR96, 0x50 },
630 { CR97, 0x37 }, { CR98, 0x35 }, { CR101, 0x13 },
631 { CR102, 0x27 }, { CR103, 0x27 }, { CR104, 0x18 },
632 { CR105, 0x12 }, { CR109, 0x27 }, { CR110, 0x27 },
633 { CR111, 0x27 }, { CR112, 0x27 }, { CR113, 0x27 },
634 { CR114, 0x27 }, { CR115, 0x26 }, { CR116, 0x24 },
635 { CR117, 0xfc }, { CR118, 0xfa }, { CR120, 0x4f },
636 { CR125, 0xaa }, { CR127, 0x03 }, { CR128, 0x14 },
637 { CR129, 0x12 }, { CR130, 0x10 }, { CR131, 0x0C },
638 { CR136, 0xdf }, { CR137, 0x40 }, { CR138, 0xa0 },
639 { CR139, 0xb0 }, { CR140, 0x99 }, { CR141, 0x82 },
640 { CR142, 0x54 }, { CR143, 0x1c }, { CR144, 0x6c },
641 { CR147, 0x07 }, { CR148, 0x4c }, { CR149, 0x50 },
642 { CR150, 0x0e }, { CR151, 0x18 }, { CR160, 0xfe },
643 { CR161, 0xee }, { CR162, 0xaa }, { CR163, 0xfa },
644 { CR164, 0xfa }, { CR165, 0xea }, { CR166, 0xbe },
645 { CR167, 0xbe }, { CR168, 0x6a }, { CR169, 0xba },
646 { CR170, 0xba }, { CR171, 0xba },
647 /* Note: CR204 must lead the CR203 */
648 { CR204, 0x7d },
649 { },
650 { CR203, 0x30 },
651 };
652
653 int r, t;
654
655 dev_dbg_f(zd_chip_dev(chip), "\n");
656
657 r = zd_chip_lock_phy_regs(chip);
658 if (r)
659 goto out;
660
661 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
662 if (r)
663 goto unlock;
664
665 r = patch_cr157(chip);
666 unlock:
667 t = zd_chip_unlock_phy_regs(chip);
668 if (t && !r)
669 r = t;
670 out:
671 return r;
672 }
673
674 static int zd1211b_hw_reset_phy(struct zd_chip *chip)
675 {
676 static const struct zd_ioreq16 ioreqs[] = {
677 { CR0, 0x14 }, { CR1, 0x06 }, { CR2, 0x26 },
678 { CR3, 0x38 }, { CR4, 0x80 }, { CR9, 0xe0 },
679 { CR10, 0x81 },
680 /* power control { { CR11, 1 << 6 }, */
681 { CR11, 0x00 },
682 { CR12, 0xf0 }, { CR13, 0x8c }, { CR14, 0x80 },
683 { CR15, 0x3d }, { CR16, 0x20 }, { CR17, 0x1e },
684 { CR18, 0x0a }, { CR19, 0x48 },
685 { CR20, 0x10 }, /* Org:0x0E, ComTrend:RalLink AP */
686 { CR21, 0x0e }, { CR22, 0x23 }, { CR23, 0x90 },
687 { CR24, 0x14 }, { CR25, 0x40 }, { CR26, 0x10 },
688 { CR27, 0x10 }, { CR28, 0x7f }, { CR29, 0x80 },
689 { CR30, 0x4b }, /* ASIC/FWT, no jointly decoder */
690 { CR31, 0x60 }, { CR32, 0x43 }, { CR33, 0x08 },
691 { CR34, 0x06 }, { CR35, 0x0a }, { CR36, 0x00 },
692 { CR37, 0x00 }, { CR38, 0x38 }, { CR39, 0x0c },
693 { CR40, 0x84 }, { CR41, 0x2a }, { CR42, 0x80 },
694 { CR43, 0x10 }, { CR44, 0x33 }, { CR46, 0xff },
695 { CR47, 0x1E }, { CR48, 0x26 }, { CR49, 0x5b },
696 { CR64, 0xd0 }, { CR65, 0x04 }, { CR66, 0x58 },
697 { CR67, 0xc9 }, { CR68, 0x88 }, { CR69, 0x41 },
698 { CR70, 0x23 }, { CR71, 0x10 }, { CR72, 0xff },
699 { CR73, 0x32 }, { CR74, 0x30 }, { CR75, 0x65 },
700 { CR76, 0x41 }, { CR77, 0x1b }, { CR78, 0x30 },
701 { CR79, 0xf0 }, { CR80, 0x64 }, { CR81, 0x64 },
702 { CR82, 0x00 }, { CR83, 0x24 }, { CR84, 0x04 },
703 { CR85, 0x00 }, { CR86, 0x0c }, { CR87, 0x12 },
704 { CR88, 0x0c }, { CR89, 0x00 }, { CR90, 0x58 },
705 { CR91, 0x04 }, { CR92, 0x00 }, { CR93, 0x00 },
706 { CR94, 0x01 },
707 { CR95, 0x20 }, /* ZD1211B */
708 { CR96, 0x50 }, { CR97, 0x37 }, { CR98, 0x35 },
709 { CR99, 0x00 }, { CR100, 0x01 }, { CR101, 0x13 },
710 { CR102, 0x27 }, { CR103, 0x27 }, { CR104, 0x18 },
711 { CR105, 0x12 }, { CR106, 0x04 }, { CR107, 0x00 },
712 { CR108, 0x0a }, { CR109, 0x27 }, { CR110, 0x27 },
713 { CR111, 0x27 }, { CR112, 0x27 }, { CR113, 0x27 },
714 { CR114, 0x27 }, { CR115, 0x26 }, { CR116, 0x24 },
715 { CR117, 0xfc }, { CR118, 0xfa }, { CR119, 0x1e },
716 { CR125, 0x90 }, { CR126, 0x00 }, { CR127, 0x00 },
717 { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 },
718 { CR131, 0x0c }, { CR136, 0xdf }, { CR137, 0xa0 },
719 { CR138, 0xa8 }, { CR139, 0xb4 }, { CR140, 0x98 },
720 { CR141, 0x82 }, { CR142, 0x53 }, { CR143, 0x1c },
721 { CR144, 0x6c }, { CR147, 0x07 }, { CR148, 0x40 },
722 { CR149, 0x40 }, /* Org:0x50 ComTrend:RalLink AP */
723 { CR150, 0x14 }, /* Org:0x0E ComTrend:RalLink AP */
724 { CR151, 0x18 }, { CR159, 0x70 }, { CR160, 0xfe },
725 { CR161, 0xee }, { CR162, 0xaa }, { CR163, 0xfa },
726 { CR164, 0xfa }, { CR165, 0xea }, { CR166, 0xbe },
727 { CR167, 0xbe }, { CR168, 0x6a }, { CR169, 0xba },
728 { CR170, 0xba }, { CR171, 0xba },
729 /* Note: CR204 must lead the CR203 */
730 { CR204, 0x7d },
731 {},
732 { CR203, 0x30 },
733 };
734
735 int r, t;
736
737 dev_dbg_f(zd_chip_dev(chip), "\n");
738
739 r = zd_chip_lock_phy_regs(chip);
740 if (r)
741 goto out;
742
743 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
744 t = zd_chip_unlock_phy_regs(chip);
745 if (t && !r)
746 r = t;
747 out:
748 return r;
749 }
750
751 static int hw_reset_phy(struct zd_chip *chip)
752 {
753 return zd_chip_is_zd1211b(chip) ? zd1211b_hw_reset_phy(chip) :
754 zd1211_hw_reset_phy(chip);
755 }
756
757 static int zd1211_hw_init_hmac(struct zd_chip *chip)
758 {
759 static const struct zd_ioreq32 ioreqs[] = {
760 { CR_ZD1211_RETRY_MAX, ZD1211_RETRY_COUNT },
761 { CR_RX_THRESHOLD, 0x000c0640 },
762 };
763
764 dev_dbg_f(zd_chip_dev(chip), "\n");
765 ZD_ASSERT(mutex_is_locked(&chip->mutex));
766 return zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
767 }
768
769 static int zd1211b_hw_init_hmac(struct zd_chip *chip)
770 {
771 static const struct zd_ioreq32 ioreqs[] = {
772 { CR_ZD1211B_RETRY_MAX, ZD1211B_RETRY_COUNT },
773 { CR_ZD1211B_CWIN_MAX_MIN_AC0, 0x007f003f },
774 { CR_ZD1211B_CWIN_MAX_MIN_AC1, 0x007f003f },
775 { CR_ZD1211B_CWIN_MAX_MIN_AC2, 0x003f001f },
776 { CR_ZD1211B_CWIN_MAX_MIN_AC3, 0x001f000f },
777 { CR_ZD1211B_AIFS_CTL1, 0x00280028 },
778 { CR_ZD1211B_AIFS_CTL2, 0x008C003C },
779 { CR_ZD1211B_TXOP, 0x01800824 },
780 { CR_RX_THRESHOLD, 0x000c0eff, },
781 };
782
783 dev_dbg_f(zd_chip_dev(chip), "\n");
784 ZD_ASSERT(mutex_is_locked(&chip->mutex));
785 return zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
786 }
787
788 static int hw_init_hmac(struct zd_chip *chip)
789 {
790 int r;
791 static const struct zd_ioreq32 ioreqs[] = {
792 { CR_ACK_TIMEOUT_EXT, 0x20 },
793 { CR_ADDA_MBIAS_WARMTIME, 0x30000808 },
794 { CR_SNIFFER_ON, 0 },
795 { CR_RX_FILTER, STA_RX_FILTER },
796 { CR_GROUP_HASH_P1, 0x00 },
797 { CR_GROUP_HASH_P2, 0x80000000 },
798 { CR_REG1, 0xa4 },
799 { CR_ADDA_PWR_DWN, 0x7f },
800 { CR_BCN_PLCP_CFG, 0x00f00401 },
801 { CR_PHY_DELAY, 0x00 },
802 { CR_ACK_TIMEOUT_EXT, 0x80 },
803 { CR_ADDA_PWR_DWN, 0x00 },
804 { CR_ACK_TIME_80211, 0x100 },
805 { CR_RX_PE_DELAY, 0x70 },
806 { CR_PS_CTRL, 0x10000000 },
807 { CR_RTS_CTS_RATE, 0x02030203 },
808 { CR_AFTER_PNP, 0x1 },
809 { CR_WEP_PROTECT, 0x114 },
810 { CR_IFS_VALUE, IFS_VALUE_DEFAULT },
811 { CR_CAM_MODE, MODE_AP_WDS},
812 };
813
814 ZD_ASSERT(mutex_is_locked(&chip->mutex));
815 r = zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
816 if (r)
817 return r;
818
819 return zd_chip_is_zd1211b(chip) ?
820 zd1211b_hw_init_hmac(chip) : zd1211_hw_init_hmac(chip);
821 }
822
823 struct aw_pt_bi {
824 u32 atim_wnd_period;
825 u32 pre_tbtt;
826 u32 beacon_interval;
827 };
828
829 static int get_aw_pt_bi(struct zd_chip *chip, struct aw_pt_bi *s)
830 {
831 int r;
832 static const zd_addr_t aw_pt_bi_addr[] =
833 { CR_ATIM_WND_PERIOD, CR_PRE_TBTT, CR_BCN_INTERVAL };
834 u32 values[3];
835
836 r = zd_ioread32v_locked(chip, values, (const zd_addr_t *)aw_pt_bi_addr,
837 ARRAY_SIZE(aw_pt_bi_addr));
838 if (r) {
839 memset(s, 0, sizeof(*s));
840 return r;
841 }
842
843 s->atim_wnd_period = values[0];
844 s->pre_tbtt = values[1];
845 s->beacon_interval = values[2];
846 return 0;
847 }
848
849 static int set_aw_pt_bi(struct zd_chip *chip, struct aw_pt_bi *s)
850 {
851 struct zd_ioreq32 reqs[3];
852
853 if (s->beacon_interval <= 5)
854 s->beacon_interval = 5;
855 if (s->pre_tbtt < 4 || s->pre_tbtt >= s->beacon_interval)
856 s->pre_tbtt = s->beacon_interval - 1;
857 if (s->atim_wnd_period >= s->pre_tbtt)
858 s->atim_wnd_period = s->pre_tbtt - 1;
859
860 reqs[0].addr = CR_ATIM_WND_PERIOD;
861 reqs[0].value = s->atim_wnd_period;
862 reqs[1].addr = CR_PRE_TBTT;
863 reqs[1].value = s->pre_tbtt;
864 reqs[2].addr = CR_BCN_INTERVAL;
865 reqs[2].value = s->beacon_interval;
866
867 return zd_iowrite32a_locked(chip, reqs, ARRAY_SIZE(reqs));
868 }
869
870
871 static int set_beacon_interval(struct zd_chip *chip, u32 interval)
872 {
873 int r;
874 struct aw_pt_bi s;
875
876 ZD_ASSERT(mutex_is_locked(&chip->mutex));
877 r = get_aw_pt_bi(chip, &s);
878 if (r)
879 return r;
880 s.beacon_interval = interval;
881 return set_aw_pt_bi(chip, &s);
882 }
883
884 int zd_set_beacon_interval(struct zd_chip *chip, u32 interval)
885 {
886 int r;
887
888 mutex_lock(&chip->mutex);
889 r = set_beacon_interval(chip, interval);
890 mutex_unlock(&chip->mutex);
891 return r;
892 }
893
894 static int hw_init(struct zd_chip *chip)
895 {
896 int r;
897
898 dev_dbg_f(zd_chip_dev(chip), "\n");
899 ZD_ASSERT(mutex_is_locked(&chip->mutex));
900 r = hw_reset_phy(chip);
901 if (r)
902 return r;
903
904 r = hw_init_hmac(chip);
905 if (r)
906 return r;
907
908 return set_beacon_interval(chip, 100);
909 }
910
911 static zd_addr_t fw_reg_addr(struct zd_chip *chip, u16 offset)
912 {
913 return (zd_addr_t)((u16)chip->fw_regs_base + offset);
914 }
915
916 #ifdef DEBUG
917 static int dump_cr(struct zd_chip *chip, const zd_addr_t addr,
918 const char *addr_string)
919 {
920 int r;
921 u32 value;
922
923 r = zd_ioread32_locked(chip, &value, addr);
924 if (r) {
925 dev_dbg_f(zd_chip_dev(chip),
926 "error reading %s. Error number %d\n", addr_string, r);
927 return r;
928 }
929
930 dev_dbg_f(zd_chip_dev(chip), "%s %#010x\n",
931 addr_string, (unsigned int)value);
932 return 0;
933 }
934
935 static int test_init(struct zd_chip *chip)
936 {
937 int r;
938
939 r = dump_cr(chip, CR_AFTER_PNP, "CR_AFTER_PNP");
940 if (r)
941 return r;
942 r = dump_cr(chip, CR_GPI_EN, "CR_GPI_EN");
943 if (r)
944 return r;
945 return dump_cr(chip, CR_INTERRUPT, "CR_INTERRUPT");
946 }
947
948 static void dump_fw_registers(struct zd_chip *chip)
949 {
950 const zd_addr_t addr[4] = {
951 fw_reg_addr(chip, FW_REG_FIRMWARE_VER),
952 fw_reg_addr(chip, FW_REG_USB_SPEED),
953 fw_reg_addr(chip, FW_REG_FIX_TX_RATE),
954 fw_reg_addr(chip, FW_REG_LED_LINK_STATUS),
955 };
956
957 int r;
958 u16 values[4];
959
960 r = zd_ioread16v_locked(chip, values, (const zd_addr_t*)addr,
961 ARRAY_SIZE(addr));
962 if (r) {
963 dev_dbg_f(zd_chip_dev(chip), "error %d zd_ioread16v_locked\n",
964 r);
965 return;
966 }
967
968 dev_dbg_f(zd_chip_dev(chip), "FW_FIRMWARE_VER %#06hx\n", values[0]);
969 dev_dbg_f(zd_chip_dev(chip), "FW_USB_SPEED %#06hx\n", values[1]);
970 dev_dbg_f(zd_chip_dev(chip), "FW_FIX_TX_RATE %#06hx\n", values[2]);
971 dev_dbg_f(zd_chip_dev(chip), "FW_LINK_STATUS %#06hx\n", values[3]);
972 }
973 #endif /* DEBUG */
974
975 static int print_fw_version(struct zd_chip *chip)
976 {
977 struct wiphy *wiphy = zd_chip_to_mac(chip)->hw->wiphy;
978 int r;
979 u16 version;
980
981 r = zd_ioread16_locked(chip, &version,
982 fw_reg_addr(chip, FW_REG_FIRMWARE_VER));
983 if (r)
984 return r;
985
986 dev_info(zd_chip_dev(chip),"firmware version %04hx\n", version);
987
988 snprintf(wiphy->fw_version, sizeof(wiphy->fw_version),
989 "%04hx", version);
990
991 return 0;
992 }
993
994 static int set_mandatory_rates(struct zd_chip *chip, int gmode)
995 {
996 u32 rates;
997 ZD_ASSERT(mutex_is_locked(&chip->mutex));
998 /* This sets the mandatory rates, which only depend from the standard
999 * that the device is supporting. Until further notice we should try
1000 * to support 802.11g also for full speed USB.
1001 */
1002 if (!gmode)
1003 rates = CR_RATE_1M|CR_RATE_2M|CR_RATE_5_5M|CR_RATE_11M;
1004 else
1005 rates = CR_RATE_1M|CR_RATE_2M|CR_RATE_5_5M|CR_RATE_11M|
1006 CR_RATE_6M|CR_RATE_12M|CR_RATE_24M;
1007
1008 return zd_iowrite32_locked(chip, rates, CR_MANDATORY_RATE_TBL);
1009 }
1010
1011 int zd_chip_set_rts_cts_rate_locked(struct zd_chip *chip,
1012 int preamble)
1013 {
1014 u32 value = 0;
1015
1016 dev_dbg_f(zd_chip_dev(chip), "preamble=%x\n", preamble);
1017 value |= preamble << RTSCTS_SH_RTS_PMB_TYPE;
1018 value |= preamble << RTSCTS_SH_CTS_PMB_TYPE;
1019
1020 /* We always send 11M RTS/self-CTS messages, like the vendor driver. */
1021 value |= ZD_PURE_RATE(ZD_CCK_RATE_11M) << RTSCTS_SH_RTS_RATE;
1022 value |= ZD_RX_CCK << RTSCTS_SH_RTS_MOD_TYPE;
1023 value |= ZD_PURE_RATE(ZD_CCK_RATE_11M) << RTSCTS_SH_CTS_RATE;
1024 value |= ZD_RX_CCK << RTSCTS_SH_CTS_MOD_TYPE;
1025
1026 return zd_iowrite32_locked(chip, value, CR_RTS_CTS_RATE);
1027 }
1028
1029 int zd_chip_enable_hwint(struct zd_chip *chip)
1030 {
1031 int r;
1032
1033 mutex_lock(&chip->mutex);
1034 r = zd_iowrite32_locked(chip, HWINT_ENABLED, CR_INTERRUPT);
1035 mutex_unlock(&chip->mutex);
1036 return r;
1037 }
1038
1039 static int disable_hwint(struct zd_chip *chip)
1040 {
1041 return zd_iowrite32_locked(chip, HWINT_DISABLED, CR_INTERRUPT);
1042 }
1043
1044 int zd_chip_disable_hwint(struct zd_chip *chip)
1045 {
1046 int r;
1047
1048 mutex_lock(&chip->mutex);
1049 r = disable_hwint(chip);
1050 mutex_unlock(&chip->mutex);
1051 return r;
1052 }
1053
1054 static int read_fw_regs_offset(struct zd_chip *chip)
1055 {
1056 int r;
1057
1058 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1059 r = zd_ioread16_locked(chip, (u16*)&chip->fw_regs_base,
1060 FWRAW_REGS_ADDR);
1061 if (r)
1062 return r;
1063 dev_dbg_f(zd_chip_dev(chip), "fw_regs_base: %#06hx\n",
1064 (u16)chip->fw_regs_base);
1065
1066 return 0;
1067 }
1068
1069 /* Read mac address using pre-firmware interface */
1070 int zd_chip_read_mac_addr_fw(struct zd_chip *chip, u8 *addr)
1071 {
1072 dev_dbg_f(zd_chip_dev(chip), "\n");
1073 return zd_usb_read_fw(&chip->usb, E2P_MAC_ADDR_P1, addr,
1074 ETH_ALEN);
1075 }
1076
1077 int zd_chip_init_hw(struct zd_chip *chip)
1078 {
1079 int r;
1080 u8 rf_type;
1081
1082 dev_dbg_f(zd_chip_dev(chip), "\n");
1083
1084 mutex_lock(&chip->mutex);
1085
1086 #ifdef DEBUG
1087 r = test_init(chip);
1088 if (r)
1089 goto out;
1090 #endif
1091 r = zd_iowrite32_locked(chip, 1, CR_AFTER_PNP);
1092 if (r)
1093 goto out;
1094
1095 r = read_fw_regs_offset(chip);
1096 if (r)
1097 goto out;
1098
1099 /* GPI is always disabled, also in the other driver.
1100 */
1101 r = zd_iowrite32_locked(chip, 0, CR_GPI_EN);
1102 if (r)
1103 goto out;
1104 r = zd_iowrite32_locked(chip, CWIN_SIZE, CR_CWMIN_CWMAX);
1105 if (r)
1106 goto out;
1107 /* Currently we support IEEE 802.11g for full and high speed USB.
1108 * It might be discussed, whether we should suppport pure b mode for
1109 * full speed USB.
1110 */
1111 r = set_mandatory_rates(chip, 1);
1112 if (r)
1113 goto out;
1114 /* Disabling interrupts is certainly a smart thing here.
1115 */
1116 r = disable_hwint(chip);
1117 if (r)
1118 goto out;
1119 r = read_pod(chip, &rf_type);
1120 if (r)
1121 goto out;
1122 r = hw_init(chip);
1123 if (r)
1124 goto out;
1125 r = zd_rf_init_hw(&chip->rf, rf_type);
1126 if (r)
1127 goto out;
1128
1129 r = print_fw_version(chip);
1130 if (r)
1131 goto out;
1132
1133 #ifdef DEBUG
1134 dump_fw_registers(chip);
1135 r = test_init(chip);
1136 if (r)
1137 goto out;
1138 #endif /* DEBUG */
1139
1140 r = read_cal_int_tables(chip);
1141 if (r)
1142 goto out;
1143
1144 print_id(chip);
1145 out:
1146 mutex_unlock(&chip->mutex);
1147 return r;
1148 }
1149
1150 static int update_pwr_int(struct zd_chip *chip, u8 channel)
1151 {
1152 u8 value = chip->pwr_int_values[channel - 1];
1153 return zd_iowrite16_locked(chip, value, CR31);
1154 }
1155
1156 static int update_pwr_cal(struct zd_chip *chip, u8 channel)
1157 {
1158 u8 value = chip->pwr_cal_values[channel-1];
1159 return zd_iowrite16_locked(chip, value, CR68);
1160 }
1161
1162 static int update_ofdm_cal(struct zd_chip *chip, u8 channel)
1163 {
1164 struct zd_ioreq16 ioreqs[3];
1165
1166 ioreqs[0].addr = CR67;
1167 ioreqs[0].value = chip->ofdm_cal_values[OFDM_36M_INDEX][channel-1];
1168 ioreqs[1].addr = CR66;
1169 ioreqs[1].value = chip->ofdm_cal_values[OFDM_48M_INDEX][channel-1];
1170 ioreqs[2].addr = CR65;
1171 ioreqs[2].value = chip->ofdm_cal_values[OFDM_54M_INDEX][channel-1];
1172
1173 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1174 }
1175
1176 static int update_channel_integration_and_calibration(struct zd_chip *chip,
1177 u8 channel)
1178 {
1179 int r;
1180
1181 if (!zd_rf_should_update_pwr_int(&chip->rf))
1182 return 0;
1183
1184 r = update_pwr_int(chip, channel);
1185 if (r)
1186 return r;
1187 if (zd_chip_is_zd1211b(chip)) {
1188 static const struct zd_ioreq16 ioreqs[] = {
1189 { CR69, 0x28 },
1190 {},
1191 { CR69, 0x2a },
1192 };
1193
1194 r = update_ofdm_cal(chip, channel);
1195 if (r)
1196 return r;
1197 r = update_pwr_cal(chip, channel);
1198 if (r)
1199 return r;
1200 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1201 if (r)
1202 return r;
1203 }
1204
1205 return 0;
1206 }
1207
1208 /* The CCK baseband gain can be optionally patched by the EEPROM */
1209 static int patch_cck_gain(struct zd_chip *chip)
1210 {
1211 int r;
1212 u32 value;
1213
1214 if (!chip->patch_cck_gain || !zd_rf_should_patch_cck_gain(&chip->rf))
1215 return 0;
1216
1217 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1218 r = zd_ioread32_locked(chip, &value, E2P_PHY_REG);
1219 if (r)
1220 return r;
1221 dev_dbg_f(zd_chip_dev(chip), "patching value %x\n", value & 0xff);
1222 return zd_iowrite16_locked(chip, value & 0xff, CR47);
1223 }
1224
1225 int zd_chip_set_channel(struct zd_chip *chip, u8 channel)
1226 {
1227 int r, t;
1228
1229 mutex_lock(&chip->mutex);
1230 r = zd_chip_lock_phy_regs(chip);
1231 if (r)
1232 goto out;
1233 r = zd_rf_set_channel(&chip->rf, channel);
1234 if (r)
1235 goto unlock;
1236 r = update_channel_integration_and_calibration(chip, channel);
1237 if (r)
1238 goto unlock;
1239 r = patch_cck_gain(chip);
1240 if (r)
1241 goto unlock;
1242 r = patch_6m_band_edge(chip, channel);
1243 if (r)
1244 goto unlock;
1245 r = zd_iowrite32_locked(chip, 0, CR_CONFIG_PHILIPS);
1246 unlock:
1247 t = zd_chip_unlock_phy_regs(chip);
1248 if (t && !r)
1249 r = t;
1250 out:
1251 mutex_unlock(&chip->mutex);
1252 return r;
1253 }
1254
1255 u8 zd_chip_get_channel(struct zd_chip *chip)
1256 {
1257 u8 channel;
1258
1259 mutex_lock(&chip->mutex);
1260 channel = chip->rf.channel;
1261 mutex_unlock(&chip->mutex);
1262 return channel;
1263 }
1264
1265 int zd_chip_control_leds(struct zd_chip *chip, enum led_status status)
1266 {
1267 const zd_addr_t a[] = {
1268 fw_reg_addr(chip, FW_REG_LED_LINK_STATUS),
1269 CR_LED,
1270 };
1271
1272 int r;
1273 u16 v[ARRAY_SIZE(a)];
1274 struct zd_ioreq16 ioreqs[ARRAY_SIZE(a)] = {
1275 [0] = { fw_reg_addr(chip, FW_REG_LED_LINK_STATUS) },
1276 [1] = { CR_LED },
1277 };
1278 u16 other_led;
1279
1280 mutex_lock(&chip->mutex);
1281 r = zd_ioread16v_locked(chip, v, (const zd_addr_t *)a, ARRAY_SIZE(a));
1282 if (r)
1283 goto out;
1284
1285 other_led = chip->link_led == LED1 ? LED2 : LED1;
1286
1287 switch (status) {
1288 case ZD_LED_OFF:
1289 ioreqs[0].value = FW_LINK_OFF;
1290 ioreqs[1].value = v[1] & ~(LED1|LED2);
1291 break;
1292 case ZD_LED_SCANNING:
1293 ioreqs[0].value = FW_LINK_OFF;
1294 ioreqs[1].value = v[1] & ~other_led;
1295 if (get_seconds() % 3 == 0) {
1296 ioreqs[1].value &= ~chip->link_led;
1297 } else {
1298 ioreqs[1].value |= chip->link_led;
1299 }
1300 break;
1301 case ZD_LED_ASSOCIATED:
1302 ioreqs[0].value = FW_LINK_TX;
1303 ioreqs[1].value = v[1] & ~other_led;
1304 ioreqs[1].value |= chip->link_led;
1305 break;
1306 default:
1307 r = -EINVAL;
1308 goto out;
1309 }
1310
1311 if (v[0] != ioreqs[0].value || v[1] != ioreqs[1].value) {
1312 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1313 if (r)
1314 goto out;
1315 }
1316 r = 0;
1317 out:
1318 mutex_unlock(&chip->mutex);
1319 return r;
1320 }
1321
1322 int zd_chip_set_basic_rates(struct zd_chip *chip, u16 cr_rates)
1323 {
1324 int r;
1325
1326 if (cr_rates & ~(CR_RATES_80211B|CR_RATES_80211G))
1327 return -EINVAL;
1328
1329 mutex_lock(&chip->mutex);
1330 r = zd_iowrite32_locked(chip, cr_rates, CR_BASIC_RATE_TBL);
1331 mutex_unlock(&chip->mutex);
1332 return r;
1333 }
1334
1335 static inline u8 zd_rate_from_ofdm_plcp_header(const void *rx_frame)
1336 {
1337 return ZD_OFDM | zd_ofdm_plcp_header_rate(rx_frame);
1338 }
1339
1340 /**
1341 * zd_rx_rate - report zd-rate
1342 * @rx_frame - received frame
1343 * @rx_status - rx_status as given by the device
1344 *
1345 * This function converts the rate as encoded in the received packet to the
1346 * zd-rate, we are using on other places in the driver.
1347 */
1348 u8 zd_rx_rate(const void *rx_frame, const struct rx_status *status)
1349 {
1350 u8 zd_rate;
1351 if (status->frame_status & ZD_RX_OFDM) {
1352 zd_rate = zd_rate_from_ofdm_plcp_header(rx_frame);
1353 } else {
1354 switch (zd_cck_plcp_header_signal(rx_frame)) {
1355 case ZD_CCK_PLCP_SIGNAL_1M:
1356 zd_rate = ZD_CCK_RATE_1M;
1357 break;
1358 case ZD_CCK_PLCP_SIGNAL_2M:
1359 zd_rate = ZD_CCK_RATE_2M;
1360 break;
1361 case ZD_CCK_PLCP_SIGNAL_5M5:
1362 zd_rate = ZD_CCK_RATE_5_5M;
1363 break;
1364 case ZD_CCK_PLCP_SIGNAL_11M:
1365 zd_rate = ZD_CCK_RATE_11M;
1366 break;
1367 default:
1368 zd_rate = 0;
1369 }
1370 }
1371
1372 return zd_rate;
1373 }
1374
1375 int zd_chip_switch_radio_on(struct zd_chip *chip)
1376 {
1377 int r;
1378
1379 mutex_lock(&chip->mutex);
1380 r = zd_switch_radio_on(&chip->rf);
1381 mutex_unlock(&chip->mutex);
1382 return r;
1383 }
1384
1385 int zd_chip_switch_radio_off(struct zd_chip *chip)
1386 {
1387 int r;
1388
1389 mutex_lock(&chip->mutex);
1390 r = zd_switch_radio_off(&chip->rf);
1391 mutex_unlock(&chip->mutex);
1392 return r;
1393 }
1394
1395 int zd_chip_enable_int(struct zd_chip *chip)
1396 {
1397 int r;
1398
1399 mutex_lock(&chip->mutex);
1400 r = zd_usb_enable_int(&chip->usb);
1401 mutex_unlock(&chip->mutex);
1402 return r;
1403 }
1404
1405 void zd_chip_disable_int(struct zd_chip *chip)
1406 {
1407 mutex_lock(&chip->mutex);
1408 zd_usb_disable_int(&chip->usb);
1409 mutex_unlock(&chip->mutex);
1410
1411 /* cancel pending interrupt work */
1412 cancel_work_sync(&zd_chip_to_mac(chip)->process_intr);
1413 }
1414
1415 int zd_chip_enable_rxtx(struct zd_chip *chip)
1416 {
1417 int r;
1418
1419 mutex_lock(&chip->mutex);
1420 zd_usb_enable_tx(&chip->usb);
1421 r = zd_usb_enable_rx(&chip->usb);
1422 mutex_unlock(&chip->mutex);
1423 return r;
1424 }
1425
1426 void zd_chip_disable_rxtx(struct zd_chip *chip)
1427 {
1428 mutex_lock(&chip->mutex);
1429 zd_usb_disable_rx(&chip->usb);
1430 zd_usb_disable_tx(&chip->usb);
1431 mutex_unlock(&chip->mutex);
1432 }
1433
1434 int zd_rfwritev_locked(struct zd_chip *chip,
1435 const u32* values, unsigned int count, u8 bits)
1436 {
1437 int r;
1438 unsigned int i;
1439
1440 for (i = 0; i < count; i++) {
1441 r = zd_rfwrite_locked(chip, values[i], bits);
1442 if (r)
1443 return r;
1444 }
1445
1446 return 0;
1447 }
1448
1449 /*
1450 * We can optionally program the RF directly through CR regs, if supported by
1451 * the hardware. This is much faster than the older method.
1452 */
1453 int zd_rfwrite_cr_locked(struct zd_chip *chip, u32 value)
1454 {
1455 const struct zd_ioreq16 ioreqs[] = {
1456 { CR244, (value >> 16) & 0xff },
1457 { CR243, (value >> 8) & 0xff },
1458 { CR242, value & 0xff },
1459 };
1460 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1461 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1462 }
1463
1464 int zd_rfwritev_cr_locked(struct zd_chip *chip,
1465 const u32 *values, unsigned int count)
1466 {
1467 int r;
1468 unsigned int i;
1469
1470 for (i = 0; i < count; i++) {
1471 r = zd_rfwrite_cr_locked(chip, values[i]);
1472 if (r)
1473 return r;
1474 }
1475
1476 return 0;
1477 }
1478
1479 int zd_chip_set_multicast_hash(struct zd_chip *chip,
1480 struct zd_mc_hash *hash)
1481 {
1482 const struct zd_ioreq32 ioreqs[] = {
1483 { CR_GROUP_HASH_P1, hash->low },
1484 { CR_GROUP_HASH_P2, hash->high },
1485 };
1486
1487 return zd_iowrite32a(chip, ioreqs, ARRAY_SIZE(ioreqs));
1488 }
1489
1490 u64 zd_chip_get_tsf(struct zd_chip *chip)
1491 {
1492 int r;
1493 static const zd_addr_t aw_pt_bi_addr[] =
1494 { CR_TSF_LOW_PART, CR_TSF_HIGH_PART };
1495 u32 values[2];
1496 u64 tsf;
1497
1498 mutex_lock(&chip->mutex);
1499 r = zd_ioread32v_locked(chip, values, (const zd_addr_t *)aw_pt_bi_addr,
1500 ARRAY_SIZE(aw_pt_bi_addr));
1501 mutex_unlock(&chip->mutex);
1502 if (r)
1503 return 0;
1504
1505 tsf = values[1];
1506 tsf = (tsf << 32) | values[0];
1507
1508 return tsf;
1509 }
Linux kernel - Deliverables
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