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[deliverable/linux.git] / drivers / ntb / hw / intel / ntb_hw_intel.c
1 /*
2 * This file is provided under a dual BSD/GPLv2 license. When using or
3 * redistributing this file, you may do so under either license.
4 *
5 * GPL LICENSE SUMMARY
6 *
7 * Copyright(c) 2012 Intel Corporation. All rights reserved.
8 * Copyright (C) 2015 EMC Corporation. All Rights Reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * BSD LICENSE
15 *
16 * Copyright(c) 2012 Intel Corporation. All rights reserved.
17 * Copyright (C) 2015 EMC Corporation. All Rights Reserved.
18 *
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions
21 * are met:
22 *
23 * * Redistributions of source code must retain the above copyright
24 * notice, this list of conditions and the following disclaimer.
25 * * Redistributions in binary form must reproduce the above copy
26 * notice, this list of conditions and the following disclaimer in
27 * the documentation and/or other materials provided with the
28 * distribution.
29 * * Neither the name of Intel Corporation nor the names of its
30 * contributors may be used to endorse or promote products derived
31 * from this software without specific prior written permission.
32 *
33 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
34 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
35 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
36 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
37 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
38 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
39 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
40 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
41 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
42 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
43 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44 *
45 * Intel PCIe NTB Linux driver
46 *
47 * Contact Information:
48 * Jon Mason <jon.mason@intel.com>
49 */
50
51 #include <linux/debugfs.h>
52 #include <linux/delay.h>
53 #include <linux/init.h>
54 #include <linux/interrupt.h>
55 #include <linux/module.h>
56 #include <linux/pci.h>
57 #include <linux/random.h>
58 #include <linux/slab.h>
59 #include <linux/ntb.h>
60
61 #include "ntb_hw_intel.h"
62
63 #define NTB_NAME "ntb_hw_intel"
64 #define NTB_DESC "Intel(R) PCI-E Non-Transparent Bridge Driver"
65 #define NTB_VER "2.0"
66
67 MODULE_DESCRIPTION(NTB_DESC);
68 MODULE_VERSION(NTB_VER);
69 MODULE_LICENSE("Dual BSD/GPL");
70 MODULE_AUTHOR("Intel Corporation");
71
72 #define bar0_off(base, bar) ((base) + ((bar) << 2))
73 #define bar2_off(base, bar) bar0_off(base, (bar) - 2)
74
75 static const struct intel_ntb_reg atom_reg;
76 static const struct intel_ntb_alt_reg atom_pri_reg;
77 static const struct intel_ntb_alt_reg atom_sec_reg;
78 static const struct intel_ntb_alt_reg atom_b2b_reg;
79 static const struct intel_ntb_xlat_reg atom_pri_xlat;
80 static const struct intel_ntb_xlat_reg atom_sec_xlat;
81 static const struct intel_ntb_reg xeon_reg;
82 static const struct intel_ntb_alt_reg xeon_pri_reg;
83 static const struct intel_ntb_alt_reg xeon_sec_reg;
84 static const struct intel_ntb_alt_reg xeon_b2b_reg;
85 static const struct intel_ntb_xlat_reg xeon_pri_xlat;
86 static const struct intel_ntb_xlat_reg xeon_sec_xlat;
87 static struct intel_b2b_addr xeon_b2b_usd_addr;
88 static struct intel_b2b_addr xeon_b2b_dsd_addr;
89 static const struct ntb_dev_ops intel_ntb_ops;
90
91 static const struct file_operations intel_ntb_debugfs_info;
92 static struct dentry *debugfs_dir;
93
94 static int b2b_mw_idx = -1;
95 module_param(b2b_mw_idx, int, 0644);
96 MODULE_PARM_DESC(b2b_mw_idx, "Use this mw idx to access the peer ntb. A "
97 "value of zero or positive starts from first mw idx, and a "
98 "negative value starts from last mw idx. Both sides MUST "
99 "set the same value here!");
100
101 static unsigned int b2b_mw_share;
102 module_param(b2b_mw_share, uint, 0644);
103 MODULE_PARM_DESC(b2b_mw_share, "If the b2b mw is large enough, configure the "
104 "ntb so that the peer ntb only occupies the first half of "
105 "the mw, so the second half can still be used as a mw. Both "
106 "sides MUST set the same value here!");
107
108 module_param_named(xeon_b2b_usd_bar2_addr64,
109 xeon_b2b_usd_addr.bar2_addr64, ullong, 0644);
110 MODULE_PARM_DESC(xeon_b2b_usd_bar2_addr64,
111 "XEON B2B USD BAR 2 64-bit address");
112
113 module_param_named(xeon_b2b_usd_bar4_addr64,
114 xeon_b2b_usd_addr.bar4_addr64, ullong, 0644);
115 MODULE_PARM_DESC(xeon_b2b_usd_bar2_addr64,
116 "XEON B2B USD BAR 4 64-bit address");
117
118 module_param_named(xeon_b2b_usd_bar4_addr32,
119 xeon_b2b_usd_addr.bar4_addr32, ullong, 0644);
120 MODULE_PARM_DESC(xeon_b2b_usd_bar2_addr64,
121 "XEON B2B USD split-BAR 4 32-bit address");
122
123 module_param_named(xeon_b2b_usd_bar5_addr32,
124 xeon_b2b_usd_addr.bar5_addr32, ullong, 0644);
125 MODULE_PARM_DESC(xeon_b2b_usd_bar2_addr64,
126 "XEON B2B USD split-BAR 5 32-bit address");
127
128 module_param_named(xeon_b2b_dsd_bar2_addr64,
129 xeon_b2b_dsd_addr.bar2_addr64, ullong, 0644);
130 MODULE_PARM_DESC(xeon_b2b_dsd_bar2_addr64,
131 "XEON B2B DSD BAR 2 64-bit address");
132
133 module_param_named(xeon_b2b_dsd_bar4_addr64,
134 xeon_b2b_dsd_addr.bar4_addr64, ullong, 0644);
135 MODULE_PARM_DESC(xeon_b2b_dsd_bar2_addr64,
136 "XEON B2B DSD BAR 4 64-bit address");
137
138 module_param_named(xeon_b2b_dsd_bar4_addr32,
139 xeon_b2b_dsd_addr.bar4_addr32, ullong, 0644);
140 MODULE_PARM_DESC(xeon_b2b_dsd_bar2_addr64,
141 "XEON B2B DSD split-BAR 4 32-bit address");
142
143 module_param_named(xeon_b2b_dsd_bar5_addr32,
144 xeon_b2b_dsd_addr.bar5_addr32, ullong, 0644);
145 MODULE_PARM_DESC(xeon_b2b_dsd_bar2_addr64,
146 "XEON B2B DSD split-BAR 5 32-bit address");
147
148 #ifndef ioread64
149 #ifdef readq
150 #define ioread64 readq
151 #else
152 #define ioread64 _ioread64
153 static inline u64 _ioread64(void __iomem *mmio)
154 {
155 u64 low, high;
156
157 low = ioread32(mmio);
158 high = ioread32(mmio + sizeof(u32));
159 return low | (high << 32);
160 }
161 #endif
162 #endif
163
164 #ifndef iowrite64
165 #ifdef writeq
166 #define iowrite64 writeq
167 #else
168 #define iowrite64 _iowrite64
169 static inline void _iowrite64(u64 val, void __iomem *mmio)
170 {
171 iowrite32(val, mmio);
172 iowrite32(val >> 32, mmio + sizeof(u32));
173 }
174 #endif
175 #endif
176
177 static inline int pdev_is_atom(struct pci_dev *pdev)
178 {
179 switch (pdev->device) {
180 case PCI_DEVICE_ID_INTEL_NTB_B2B_BWD:
181 return 1;
182 }
183 return 0;
184 }
185
186 static inline int pdev_is_xeon(struct pci_dev *pdev)
187 {
188 switch (pdev->device) {
189 case PCI_DEVICE_ID_INTEL_NTB_SS_JSF:
190 case PCI_DEVICE_ID_INTEL_NTB_SS_SNB:
191 case PCI_DEVICE_ID_INTEL_NTB_SS_IVT:
192 case PCI_DEVICE_ID_INTEL_NTB_SS_HSX:
193 case PCI_DEVICE_ID_INTEL_NTB_SS_BDX:
194 case PCI_DEVICE_ID_INTEL_NTB_PS_JSF:
195 case PCI_DEVICE_ID_INTEL_NTB_PS_SNB:
196 case PCI_DEVICE_ID_INTEL_NTB_PS_IVT:
197 case PCI_DEVICE_ID_INTEL_NTB_PS_HSX:
198 case PCI_DEVICE_ID_INTEL_NTB_PS_BDX:
199 case PCI_DEVICE_ID_INTEL_NTB_B2B_JSF:
200 case PCI_DEVICE_ID_INTEL_NTB_B2B_SNB:
201 case PCI_DEVICE_ID_INTEL_NTB_B2B_IVT:
202 case PCI_DEVICE_ID_INTEL_NTB_B2B_HSX:
203 case PCI_DEVICE_ID_INTEL_NTB_B2B_BDX:
204 return 1;
205 }
206 return 0;
207 }
208
209 static inline void ndev_reset_unsafe_flags(struct intel_ntb_dev *ndev)
210 {
211 ndev->unsafe_flags = 0;
212 ndev->unsafe_flags_ignore = 0;
213
214 /* Only B2B has a workaround to avoid SDOORBELL */
215 if (ndev->hwerr_flags & NTB_HWERR_SDOORBELL_LOCKUP)
216 if (!ntb_topo_is_b2b(ndev->ntb.topo))
217 ndev->unsafe_flags |= NTB_UNSAFE_DB;
218
219 /* No low level workaround to avoid SB01BASE */
220 if (ndev->hwerr_flags & NTB_HWERR_SB01BASE_LOCKUP) {
221 ndev->unsafe_flags |= NTB_UNSAFE_DB;
222 ndev->unsafe_flags |= NTB_UNSAFE_SPAD;
223 }
224 }
225
226 static inline int ndev_is_unsafe(struct intel_ntb_dev *ndev,
227 unsigned long flag)
228 {
229 return !!(flag & ndev->unsafe_flags & ~ndev->unsafe_flags_ignore);
230 }
231
232 static inline int ndev_ignore_unsafe(struct intel_ntb_dev *ndev,
233 unsigned long flag)
234 {
235 flag &= ndev->unsafe_flags;
236 ndev->unsafe_flags_ignore |= flag;
237
238 return !!flag;
239 }
240
241 static int ndev_mw_to_bar(struct intel_ntb_dev *ndev, int idx)
242 {
243 if (idx < 0 || idx > ndev->mw_count)
244 return -EINVAL;
245 return ndev->reg->mw_bar[idx];
246 }
247
248 static inline int ndev_db_addr(struct intel_ntb_dev *ndev,
249 phys_addr_t *db_addr, resource_size_t *db_size,
250 phys_addr_t reg_addr, unsigned long reg)
251 {
252 if (ndev_is_unsafe(ndev, NTB_UNSAFE_DB))
253 pr_warn_once("%s: NTB unsafe doorbell access", __func__);
254
255 if (db_addr) {
256 *db_addr = reg_addr + reg;
257 dev_dbg(ndev_dev(ndev), "Peer db addr %llx\n", *db_addr);
258 }
259
260 if (db_size) {
261 *db_size = ndev->reg->db_size;
262 dev_dbg(ndev_dev(ndev), "Peer db size %llx\n", *db_size);
263 }
264
265 return 0;
266 }
267
268 static inline u64 ndev_db_read(struct intel_ntb_dev *ndev,
269 void __iomem *mmio)
270 {
271 if (ndev_is_unsafe(ndev, NTB_UNSAFE_DB))
272 pr_warn_once("%s: NTB unsafe doorbell access", __func__);
273
274 return ndev->reg->db_ioread(mmio);
275 }
276
277 static inline int ndev_db_write(struct intel_ntb_dev *ndev, u64 db_bits,
278 void __iomem *mmio)
279 {
280 if (ndev_is_unsafe(ndev, NTB_UNSAFE_DB))
281 pr_warn_once("%s: NTB unsafe doorbell access", __func__);
282
283 if (db_bits & ~ndev->db_valid_mask)
284 return -EINVAL;
285
286 ndev->reg->db_iowrite(db_bits, mmio);
287
288 return 0;
289 }
290
291 static inline int ndev_db_set_mask(struct intel_ntb_dev *ndev, u64 db_bits,
292 void __iomem *mmio)
293 {
294 unsigned long irqflags;
295
296 if (ndev_is_unsafe(ndev, NTB_UNSAFE_DB))
297 pr_warn_once("%s: NTB unsafe doorbell access", __func__);
298
299 if (db_bits & ~ndev->db_valid_mask)
300 return -EINVAL;
301
302 spin_lock_irqsave(&ndev->db_mask_lock, irqflags);
303 {
304 ndev->db_mask |= db_bits;
305 ndev->reg->db_iowrite(ndev->db_mask, mmio);
306 }
307 spin_unlock_irqrestore(&ndev->db_mask_lock, irqflags);
308
309 return 0;
310 }
311
312 static inline int ndev_db_clear_mask(struct intel_ntb_dev *ndev, u64 db_bits,
313 void __iomem *mmio)
314 {
315 unsigned long irqflags;
316
317 if (ndev_is_unsafe(ndev, NTB_UNSAFE_DB))
318 pr_warn_once("%s: NTB unsafe doorbell access", __func__);
319
320 if (db_bits & ~ndev->db_valid_mask)
321 return -EINVAL;
322
323 spin_lock_irqsave(&ndev->db_mask_lock, irqflags);
324 {
325 ndev->db_mask &= ~db_bits;
326 ndev->reg->db_iowrite(ndev->db_mask, mmio);
327 }
328 spin_unlock_irqrestore(&ndev->db_mask_lock, irqflags);
329
330 return 0;
331 }
332
333 static inline int ndev_vec_mask(struct intel_ntb_dev *ndev, int db_vector)
334 {
335 u64 shift, mask;
336
337 shift = ndev->db_vec_shift;
338 mask = BIT_ULL(shift) - 1;
339
340 return mask << (shift * db_vector);
341 }
342
343 static inline int ndev_spad_addr(struct intel_ntb_dev *ndev, int idx,
344 phys_addr_t *spad_addr, phys_addr_t reg_addr,
345 unsigned long reg)
346 {
347 if (ndev_is_unsafe(ndev, NTB_UNSAFE_SPAD))
348 pr_warn_once("%s: NTB unsafe scratchpad access", __func__);
349
350 if (idx < 0 || idx >= ndev->spad_count)
351 return -EINVAL;
352
353 if (spad_addr) {
354 *spad_addr = reg_addr + reg + (idx << 2);
355 dev_dbg(ndev_dev(ndev), "Peer spad addr %llx\n", *spad_addr);
356 }
357
358 return 0;
359 }
360
361 static inline u32 ndev_spad_read(struct intel_ntb_dev *ndev, int idx,
362 void __iomem *mmio)
363 {
364 if (ndev_is_unsafe(ndev, NTB_UNSAFE_SPAD))
365 pr_warn_once("%s: NTB unsafe scratchpad access", __func__);
366
367 if (idx < 0 || idx >= ndev->spad_count)
368 return 0;
369
370 return ioread32(mmio + (idx << 2));
371 }
372
373 static inline int ndev_spad_write(struct intel_ntb_dev *ndev, int idx, u32 val,
374 void __iomem *mmio)
375 {
376 if (ndev_is_unsafe(ndev, NTB_UNSAFE_SPAD))
377 pr_warn_once("%s: NTB unsafe scratchpad access", __func__);
378
379 if (idx < 0 || idx >= ndev->spad_count)
380 return -EINVAL;
381
382 iowrite32(val, mmio + (idx << 2));
383
384 return 0;
385 }
386
387 static irqreturn_t ndev_interrupt(struct intel_ntb_dev *ndev, int vec)
388 {
389 u64 vec_mask;
390
391 vec_mask = ndev_vec_mask(ndev, vec);
392
393 dev_dbg(ndev_dev(ndev), "vec %d vec_mask %llx\n", vec, vec_mask);
394
395 ndev->last_ts = jiffies;
396
397 if (vec_mask & ndev->db_link_mask) {
398 if (ndev->reg->poll_link(ndev))
399 ntb_link_event(&ndev->ntb);
400 }
401
402 if (vec_mask & ndev->db_valid_mask)
403 ntb_db_event(&ndev->ntb, vec);
404
405 return IRQ_HANDLED;
406 }
407
408 static irqreturn_t ndev_vec_isr(int irq, void *dev)
409 {
410 struct intel_ntb_vec *nvec = dev;
411
412 return ndev_interrupt(nvec->ndev, nvec->num);
413 }
414
415 static irqreturn_t ndev_irq_isr(int irq, void *dev)
416 {
417 struct intel_ntb_dev *ndev = dev;
418
419 return ndev_interrupt(ndev, irq - ndev_pdev(ndev)->irq);
420 }
421
422 static int ndev_init_isr(struct intel_ntb_dev *ndev,
423 int msix_min, int msix_max,
424 int msix_shift, int total_shift)
425 {
426 struct pci_dev *pdev;
427 int rc, i, msix_count, node;
428
429 pdev = ndev_pdev(ndev);
430
431 node = dev_to_node(&pdev->dev);
432
433 /* Mask all doorbell interrupts */
434 ndev->db_mask = ndev->db_valid_mask;
435 ndev->reg->db_iowrite(ndev->db_mask,
436 ndev->self_mmio +
437 ndev->self_reg->db_mask);
438
439 /* Try to set up msix irq */
440
441 ndev->vec = kzalloc_node(msix_max * sizeof(*ndev->vec),
442 GFP_KERNEL, node);
443 if (!ndev->vec)
444 goto err_msix_vec_alloc;
445
446 ndev->msix = kzalloc_node(msix_max * sizeof(*ndev->msix),
447 GFP_KERNEL, node);
448 if (!ndev->msix)
449 goto err_msix_alloc;
450
451 for (i = 0; i < msix_max; ++i)
452 ndev->msix[i].entry = i;
453
454 msix_count = pci_enable_msix_range(pdev, ndev->msix,
455 msix_min, msix_max);
456 if (msix_count < 0)
457 goto err_msix_enable;
458
459 for (i = 0; i < msix_count; ++i) {
460 ndev->vec[i].ndev = ndev;
461 ndev->vec[i].num = i;
462 rc = request_irq(ndev->msix[i].vector, ndev_vec_isr, 0,
463 "ndev_vec_isr", &ndev->vec[i]);
464 if (rc)
465 goto err_msix_request;
466 }
467
468 dev_dbg(ndev_dev(ndev), "Using msix interrupts\n");
469 ndev->db_vec_count = msix_count;
470 ndev->db_vec_shift = msix_shift;
471 return 0;
472
473 err_msix_request:
474 while (i-- > 0)
475 free_irq(ndev->msix[i].vector, ndev);
476 pci_disable_msix(pdev);
477 err_msix_enable:
478 kfree(ndev->msix);
479 err_msix_alloc:
480 kfree(ndev->vec);
481 err_msix_vec_alloc:
482 ndev->msix = NULL;
483 ndev->vec = NULL;
484
485 /* Try to set up msi irq */
486
487 rc = pci_enable_msi(pdev);
488 if (rc)
489 goto err_msi_enable;
490
491 rc = request_irq(pdev->irq, ndev_irq_isr, 0,
492 "ndev_irq_isr", ndev);
493 if (rc)
494 goto err_msi_request;
495
496 dev_dbg(ndev_dev(ndev), "Using msi interrupts\n");
497 ndev->db_vec_count = 1;
498 ndev->db_vec_shift = total_shift;
499 return 0;
500
501 err_msi_request:
502 pci_disable_msi(pdev);
503 err_msi_enable:
504
505 /* Try to set up intx irq */
506
507 pci_intx(pdev, 1);
508
509 rc = request_irq(pdev->irq, ndev_irq_isr, IRQF_SHARED,
510 "ndev_irq_isr", ndev);
511 if (rc)
512 goto err_intx_request;
513
514 dev_dbg(ndev_dev(ndev), "Using intx interrupts\n");
515 ndev->db_vec_count = 1;
516 ndev->db_vec_shift = total_shift;
517 return 0;
518
519 err_intx_request:
520 return rc;
521 }
522
523 static void ndev_deinit_isr(struct intel_ntb_dev *ndev)
524 {
525 struct pci_dev *pdev;
526 int i;
527
528 pdev = ndev_pdev(ndev);
529
530 /* Mask all doorbell interrupts */
531 ndev->db_mask = ndev->db_valid_mask;
532 ndev->reg->db_iowrite(ndev->db_mask,
533 ndev->self_mmio +
534 ndev->self_reg->db_mask);
535
536 if (ndev->msix) {
537 i = ndev->db_vec_count;
538 while (i--)
539 free_irq(ndev->msix[i].vector, &ndev->vec[i]);
540 pci_disable_msix(pdev);
541 kfree(ndev->msix);
542 kfree(ndev->vec);
543 } else {
544 free_irq(pdev->irq, ndev);
545 if (pci_dev_msi_enabled(pdev))
546 pci_disable_msi(pdev);
547 }
548 }
549
550 static ssize_t ndev_debugfs_read(struct file *filp, char __user *ubuf,
551 size_t count, loff_t *offp)
552 {
553 struct intel_ntb_dev *ndev;
554 void __iomem *mmio;
555 char *buf;
556 size_t buf_size;
557 ssize_t ret, off;
558 union { u64 v64; u32 v32; u16 v16; } u;
559
560 ndev = filp->private_data;
561 mmio = ndev->self_mmio;
562
563 buf_size = min(count, 0x800ul);
564
565 buf = kmalloc(buf_size, GFP_KERNEL);
566 if (!buf)
567 return -ENOMEM;
568
569 off = 0;
570
571 off += scnprintf(buf + off, buf_size - off,
572 "NTB Device Information:\n");
573
574 off += scnprintf(buf + off, buf_size - off,
575 "Connection Topology -\t%s\n",
576 ntb_topo_string(ndev->ntb.topo));
577
578 off += scnprintf(buf + off, buf_size - off,
579 "B2B Offset -\t\t%#lx\n", ndev->b2b_off);
580 off += scnprintf(buf + off, buf_size - off,
581 "B2B MW Idx -\t\t%d\n", ndev->b2b_idx);
582 off += scnprintf(buf + off, buf_size - off,
583 "BAR4 Split -\t\t%s\n",
584 ndev->bar4_split ? "yes" : "no");
585
586 off += scnprintf(buf + off, buf_size - off,
587 "NTB CTL -\t\t%#06x\n", ndev->ntb_ctl);
588 off += scnprintf(buf + off, buf_size - off,
589 "LNK STA -\t\t%#06x\n", ndev->lnk_sta);
590
591 if (!ndev->reg->link_is_up(ndev)) {
592 off += scnprintf(buf + off, buf_size - off,
593 "Link Status -\t\tDown\n");
594 } else {
595 off += scnprintf(buf + off, buf_size - off,
596 "Link Status -\t\tUp\n");
597 off += scnprintf(buf + off, buf_size - off,
598 "Link Speed -\t\tPCI-E Gen %u\n",
599 NTB_LNK_STA_SPEED(ndev->lnk_sta));
600 off += scnprintf(buf + off, buf_size - off,
601 "Link Width -\t\tx%u\n",
602 NTB_LNK_STA_WIDTH(ndev->lnk_sta));
603 }
604
605 off += scnprintf(buf + off, buf_size - off,
606 "Memory Window Count -\t%u\n", ndev->mw_count);
607 off += scnprintf(buf + off, buf_size - off,
608 "Scratchpad Count -\t%u\n", ndev->spad_count);
609 off += scnprintf(buf + off, buf_size - off,
610 "Doorbell Count -\t%u\n", ndev->db_count);
611 off += scnprintf(buf + off, buf_size - off,
612 "Doorbell Vector Count -\t%u\n", ndev->db_vec_count);
613 off += scnprintf(buf + off, buf_size - off,
614 "Doorbell Vector Shift -\t%u\n", ndev->db_vec_shift);
615
616 off += scnprintf(buf + off, buf_size - off,
617 "Doorbell Valid Mask -\t%#llx\n", ndev->db_valid_mask);
618 off += scnprintf(buf + off, buf_size - off,
619 "Doorbell Link Mask -\t%#llx\n", ndev->db_link_mask);
620 off += scnprintf(buf + off, buf_size - off,
621 "Doorbell Mask Cached -\t%#llx\n", ndev->db_mask);
622
623 u.v64 = ndev_db_read(ndev, mmio + ndev->self_reg->db_mask);
624 off += scnprintf(buf + off, buf_size - off,
625 "Doorbell Mask -\t\t%#llx\n", u.v64);
626
627 u.v64 = ndev_db_read(ndev, mmio + ndev->self_reg->db_bell);
628 off += scnprintf(buf + off, buf_size - off,
629 "Doorbell Bell -\t\t%#llx\n", u.v64);
630
631 off += scnprintf(buf + off, buf_size - off,
632 "\nNTB Incoming XLAT:\n");
633
634 u.v64 = ioread64(mmio + bar2_off(ndev->xlat_reg->bar2_xlat, 2));
635 off += scnprintf(buf + off, buf_size - off,
636 "XLAT23 -\t\t%#018llx\n", u.v64);
637
638 if (ndev->bar4_split) {
639 u.v32 = ioread32(mmio + bar2_off(ndev->xlat_reg->bar2_xlat, 4));
640 off += scnprintf(buf + off, buf_size - off,
641 "XLAT4 -\t\t\t%#06x\n", u.v32);
642
643 u.v32 = ioread32(mmio + bar2_off(ndev->xlat_reg->bar2_xlat, 5));
644 off += scnprintf(buf + off, buf_size - off,
645 "XLAT5 -\t\t\t%#06x\n", u.v32);
646 } else {
647 u.v64 = ioread64(mmio + bar2_off(ndev->xlat_reg->bar2_xlat, 4));
648 off += scnprintf(buf + off, buf_size - off,
649 "XLAT45 -\t\t%#018llx\n", u.v64);
650 }
651
652 u.v64 = ioread64(mmio + bar2_off(ndev->xlat_reg->bar2_limit, 2));
653 off += scnprintf(buf + off, buf_size - off,
654 "LMT23 -\t\t\t%#018llx\n", u.v64);
655
656 if (ndev->bar4_split) {
657 u.v32 = ioread32(mmio + bar2_off(ndev->xlat_reg->bar2_limit, 4));
658 off += scnprintf(buf + off, buf_size - off,
659 "LMT4 -\t\t\t%#06x\n", u.v32);
660 u.v32 = ioread32(mmio + bar2_off(ndev->xlat_reg->bar2_limit, 5));
661 off += scnprintf(buf + off, buf_size - off,
662 "LMT5 -\t\t\t%#06x\n", u.v32);
663 } else {
664 u.v64 = ioread64(mmio + bar2_off(ndev->xlat_reg->bar2_limit, 4));
665 off += scnprintf(buf + off, buf_size - off,
666 "LMT45 -\t\t\t%#018llx\n", u.v64);
667 }
668
669 if (pdev_is_xeon(ndev->ntb.pdev)) {
670 if (ntb_topo_is_b2b(ndev->ntb.topo)) {
671 off += scnprintf(buf + off, buf_size - off,
672 "\nNTB Outgoing B2B XLAT:\n");
673
674 u.v64 = ioread64(mmio + XEON_PBAR23XLAT_OFFSET);
675 off += scnprintf(buf + off, buf_size - off,
676 "B2B XLAT23 -\t\t%#018llx\n", u.v64);
677
678 if (ndev->bar4_split) {
679 u.v32 = ioread32(mmio + XEON_PBAR4XLAT_OFFSET);
680 off += scnprintf(buf + off, buf_size - off,
681 "B2B XLAT4 -\t\t%#06x\n",
682 u.v32);
683 u.v32 = ioread32(mmio + XEON_PBAR5XLAT_OFFSET);
684 off += scnprintf(buf + off, buf_size - off,
685 "B2B XLAT5 -\t\t%#06x\n",
686 u.v32);
687 } else {
688 u.v64 = ioread64(mmio + XEON_PBAR45XLAT_OFFSET);
689 off += scnprintf(buf + off, buf_size - off,
690 "B2B XLAT45 -\t\t%#018llx\n",
691 u.v64);
692 }
693
694 u.v64 = ioread64(mmio + XEON_PBAR23LMT_OFFSET);
695 off += scnprintf(buf + off, buf_size - off,
696 "B2B LMT23 -\t\t%#018llx\n", u.v64);
697
698 if (ndev->bar4_split) {
699 u.v32 = ioread32(mmio + XEON_PBAR4LMT_OFFSET);
700 off += scnprintf(buf + off, buf_size - off,
701 "B2B LMT4 -\t\t%#06x\n",
702 u.v32);
703 u.v32 = ioread32(mmio + XEON_PBAR5LMT_OFFSET);
704 off += scnprintf(buf + off, buf_size - off,
705 "B2B LMT5 -\t\t%#06x\n",
706 u.v32);
707 } else {
708 u.v64 = ioread64(mmio + XEON_PBAR45LMT_OFFSET);
709 off += scnprintf(buf + off, buf_size - off,
710 "B2B LMT45 -\t\t%#018llx\n",
711 u.v64);
712 }
713
714 off += scnprintf(buf + off, buf_size - off,
715 "\nNTB Secondary BAR:\n");
716
717 u.v64 = ioread64(mmio + XEON_SBAR0BASE_OFFSET);
718 off += scnprintf(buf + off, buf_size - off,
719 "SBAR01 -\t\t%#018llx\n", u.v64);
720
721 u.v64 = ioread64(mmio + XEON_SBAR23BASE_OFFSET);
722 off += scnprintf(buf + off, buf_size - off,
723 "SBAR23 -\t\t%#018llx\n", u.v64);
724
725 if (ndev->bar4_split) {
726 u.v32 = ioread32(mmio + XEON_SBAR4BASE_OFFSET);
727 off += scnprintf(buf + off, buf_size - off,
728 "SBAR4 -\t\t\t%#06x\n", u.v32);
729 u.v32 = ioread32(mmio + XEON_SBAR5BASE_OFFSET);
730 off += scnprintf(buf + off, buf_size - off,
731 "SBAR5 -\t\t\t%#06x\n", u.v32);
732 } else {
733 u.v64 = ioread64(mmio + XEON_SBAR45BASE_OFFSET);
734 off += scnprintf(buf + off, buf_size - off,
735 "SBAR45 -\t\t%#018llx\n",
736 u.v64);
737 }
738 }
739
740 off += scnprintf(buf + off, buf_size - off,
741 "\nXEON NTB Statistics:\n");
742
743 u.v16 = ioread16(mmio + XEON_USMEMMISS_OFFSET);
744 off += scnprintf(buf + off, buf_size - off,
745 "Upstream Memory Miss -\t%u\n", u.v16);
746
747 off += scnprintf(buf + off, buf_size - off,
748 "\nXEON NTB Hardware Errors:\n");
749
750 if (!pci_read_config_word(ndev->ntb.pdev,
751 XEON_DEVSTS_OFFSET, &u.v16))
752 off += scnprintf(buf + off, buf_size - off,
753 "DEVSTS -\t\t%#06x\n", u.v16);
754
755 if (!pci_read_config_word(ndev->ntb.pdev,
756 XEON_LINK_STATUS_OFFSET, &u.v16))
757 off += scnprintf(buf + off, buf_size - off,
758 "LNKSTS -\t\t%#06x\n", u.v16);
759
760 if (!pci_read_config_dword(ndev->ntb.pdev,
761 XEON_UNCERRSTS_OFFSET, &u.v32))
762 off += scnprintf(buf + off, buf_size - off,
763 "UNCERRSTS -\t\t%#06x\n", u.v32);
764
765 if (!pci_read_config_dword(ndev->ntb.pdev,
766 XEON_CORERRSTS_OFFSET, &u.v32))
767 off += scnprintf(buf + off, buf_size - off,
768 "CORERRSTS -\t\t%#06x\n", u.v32);
769 }
770
771 ret = simple_read_from_buffer(ubuf, count, offp, buf, off);
772 kfree(buf);
773 return ret;
774 }
775
776 static void ndev_init_debugfs(struct intel_ntb_dev *ndev)
777 {
778 if (!debugfs_dir) {
779 ndev->debugfs_dir = NULL;
780 ndev->debugfs_info = NULL;
781 } else {
782 ndev->debugfs_dir =
783 debugfs_create_dir(ndev_name(ndev), debugfs_dir);
784 if (!ndev->debugfs_dir)
785 ndev->debugfs_info = NULL;
786 else
787 ndev->debugfs_info =
788 debugfs_create_file("info", S_IRUSR,
789 ndev->debugfs_dir, ndev,
790 &intel_ntb_debugfs_info);
791 }
792 }
793
794 static void ndev_deinit_debugfs(struct intel_ntb_dev *ndev)
795 {
796 debugfs_remove_recursive(ndev->debugfs_dir);
797 }
798
799 static int intel_ntb_mw_count(struct ntb_dev *ntb)
800 {
801 return ntb_ndev(ntb)->mw_count;
802 }
803
804 static int intel_ntb_mw_get_range(struct ntb_dev *ntb, int idx,
805 phys_addr_t *base,
806 resource_size_t *size,
807 resource_size_t *align,
808 resource_size_t *align_size)
809 {
810 struct intel_ntb_dev *ndev = ntb_ndev(ntb);
811 int bar;
812
813 if (idx >= ndev->b2b_idx && !ndev->b2b_off)
814 idx += 1;
815
816 bar = ndev_mw_to_bar(ndev, idx);
817 if (bar < 0)
818 return bar;
819
820 if (base)
821 *base = pci_resource_start(ndev->ntb.pdev, bar) +
822 (idx == ndev->b2b_idx ? ndev->b2b_off : 0);
823
824 if (size)
825 *size = pci_resource_len(ndev->ntb.pdev, bar) -
826 (idx == ndev->b2b_idx ? ndev->b2b_off : 0);
827
828 if (align)
829 *align = pci_resource_len(ndev->ntb.pdev, bar);
830
831 if (align_size)
832 *align_size = 1;
833
834 return 0;
835 }
836
837 static int intel_ntb_mw_set_trans(struct ntb_dev *ntb, int idx,
838 dma_addr_t addr, resource_size_t size)
839 {
840 struct intel_ntb_dev *ndev = ntb_ndev(ntb);
841 unsigned long base_reg, xlat_reg, limit_reg;
842 resource_size_t bar_size, mw_size;
843 void __iomem *mmio;
844 u64 base, limit, reg_val;
845 int bar;
846
847 if (idx >= ndev->b2b_idx && !ndev->b2b_off)
848 idx += 1;
849
850 bar = ndev_mw_to_bar(ndev, idx);
851 if (bar < 0)
852 return bar;
853
854 bar_size = pci_resource_len(ndev->ntb.pdev, bar);
855
856 if (idx == ndev->b2b_idx)
857 mw_size = bar_size - ndev->b2b_off;
858 else
859 mw_size = bar_size;
860
861 /* hardware requires that addr is aligned to bar size */
862 if (addr & (bar_size - 1))
863 return -EINVAL;
864
865 /* make sure the range fits in the usable mw size */
866 if (size > mw_size)
867 return -EINVAL;
868
869 mmio = ndev->self_mmio;
870 base_reg = bar0_off(ndev->xlat_reg->bar0_base, bar);
871 xlat_reg = bar2_off(ndev->xlat_reg->bar2_xlat, bar);
872 limit_reg = bar2_off(ndev->xlat_reg->bar2_limit, bar);
873
874 if (bar < 4 || !ndev->bar4_split) {
875 base = ioread64(mmio + base_reg);
876
877 /* Set the limit if supported, if size is not mw_size */
878 if (limit_reg && size != mw_size)
879 limit = base + size;
880 else
881 limit = 0;
882
883 /* set and verify setting the translation address */
884 iowrite64(addr, mmio + xlat_reg);
885 reg_val = ioread64(mmio + xlat_reg);
886 if (reg_val != addr) {
887 iowrite64(0, mmio + xlat_reg);
888 return -EIO;
889 }
890
891 /* set and verify setting the limit */
892 iowrite64(limit, mmio + limit_reg);
893 reg_val = ioread64(mmio + limit_reg);
894 if (reg_val != limit) {
895 iowrite64(base, mmio + limit_reg);
896 iowrite64(0, mmio + xlat_reg);
897 return -EIO;
898 }
899 } else {
900 /* split bar addr range must all be 32 bit */
901 if (addr & (~0ull << 32))
902 return -EINVAL;
903 if ((addr + size) & (~0ull << 32))
904 return -EINVAL;
905
906 base = ioread32(mmio + base_reg);
907
908 /* Set the limit if supported, if size is not mw_size */
909 if (limit_reg && size != mw_size)
910 limit = base + size;
911 else
912 limit = 0;
913
914 /* set and verify setting the translation address */
915 iowrite32(addr, mmio + xlat_reg);
916 reg_val = ioread32(mmio + xlat_reg);
917 if (reg_val != addr) {
918 iowrite32(0, mmio + xlat_reg);
919 return -EIO;
920 }
921
922 /* set and verify setting the limit */
923 iowrite32(limit, mmio + limit_reg);
924 reg_val = ioread32(mmio + limit_reg);
925 if (reg_val != limit) {
926 iowrite32(base, mmio + limit_reg);
927 iowrite32(0, mmio + xlat_reg);
928 return -EIO;
929 }
930 }
931
932 return 0;
933 }
934
935 static int intel_ntb_link_is_up(struct ntb_dev *ntb,
936 enum ntb_speed *speed,
937 enum ntb_width *width)
938 {
939 struct intel_ntb_dev *ndev = ntb_ndev(ntb);
940
941 if (ndev->reg->link_is_up(ndev)) {
942 if (speed)
943 *speed = NTB_LNK_STA_SPEED(ndev->lnk_sta);
944 if (width)
945 *width = NTB_LNK_STA_WIDTH(ndev->lnk_sta);
946 return 1;
947 } else {
948 /* TODO MAYBE: is it possible to observe the link speed and
949 * width while link is training? */
950 if (speed)
951 *speed = NTB_SPEED_NONE;
952 if (width)
953 *width = NTB_WIDTH_NONE;
954 return 0;
955 }
956 }
957
958 static int intel_ntb_link_enable(struct ntb_dev *ntb,
959 enum ntb_speed max_speed,
960 enum ntb_width max_width)
961 {
962 struct intel_ntb_dev *ndev;
963 u32 ntb_ctl;
964
965 ndev = container_of(ntb, struct intel_ntb_dev, ntb);
966
967 if (ndev->ntb.topo == NTB_TOPO_SEC)
968 return -EINVAL;
969
970 dev_dbg(ndev_dev(ndev),
971 "Enabling link with max_speed %d max_width %d\n",
972 max_speed, max_width);
973 if (max_speed != NTB_SPEED_AUTO)
974 dev_dbg(ndev_dev(ndev), "ignoring max_speed %d\n", max_speed);
975 if (max_width != NTB_WIDTH_AUTO)
976 dev_dbg(ndev_dev(ndev), "ignoring max_width %d\n", max_width);
977
978 ntb_ctl = ioread32(ndev->self_mmio + ndev->reg->ntb_ctl);
979 ntb_ctl &= ~(NTB_CTL_DISABLE | NTB_CTL_CFG_LOCK);
980 ntb_ctl |= NTB_CTL_P2S_BAR2_SNOOP | NTB_CTL_S2P_BAR2_SNOOP;
981 ntb_ctl |= NTB_CTL_P2S_BAR4_SNOOP | NTB_CTL_S2P_BAR4_SNOOP;
982 if (ndev->bar4_split)
983 ntb_ctl |= NTB_CTL_P2S_BAR5_SNOOP | NTB_CTL_S2P_BAR5_SNOOP;
984 iowrite32(ntb_ctl, ndev->self_mmio + ndev->reg->ntb_ctl);
985
986 return 0;
987 }
988
989 static int intel_ntb_link_disable(struct ntb_dev *ntb)
990 {
991 struct intel_ntb_dev *ndev;
992 u32 ntb_cntl;
993
994 ndev = container_of(ntb, struct intel_ntb_dev, ntb);
995
996 if (ndev->ntb.topo == NTB_TOPO_SEC)
997 return -EINVAL;
998
999 dev_dbg(ndev_dev(ndev), "Disabling link\n");
1000
1001 /* Bring NTB link down */
1002 ntb_cntl = ioread32(ndev->self_mmio + ndev->reg->ntb_ctl);
1003 ntb_cntl &= ~(NTB_CTL_P2S_BAR2_SNOOP | NTB_CTL_S2P_BAR2_SNOOP);
1004 ntb_cntl &= ~(NTB_CTL_P2S_BAR4_SNOOP | NTB_CTL_S2P_BAR4_SNOOP);
1005 if (ndev->bar4_split)
1006 ntb_cntl &= ~(NTB_CTL_P2S_BAR5_SNOOP | NTB_CTL_S2P_BAR5_SNOOP);
1007 ntb_cntl |= NTB_CTL_DISABLE | NTB_CTL_CFG_LOCK;
1008 iowrite32(ntb_cntl, ndev->self_mmio + ndev->reg->ntb_ctl);
1009
1010 return 0;
1011 }
1012
1013 static int intel_ntb_db_is_unsafe(struct ntb_dev *ntb)
1014 {
1015 return ndev_ignore_unsafe(ntb_ndev(ntb), NTB_UNSAFE_DB);
1016 }
1017
1018 static u64 intel_ntb_db_valid_mask(struct ntb_dev *ntb)
1019 {
1020 return ntb_ndev(ntb)->db_valid_mask;
1021 }
1022
1023 static int intel_ntb_db_vector_count(struct ntb_dev *ntb)
1024 {
1025 struct intel_ntb_dev *ndev;
1026
1027 ndev = container_of(ntb, struct intel_ntb_dev, ntb);
1028
1029 return ndev->db_vec_count;
1030 }
1031
1032 static u64 intel_ntb_db_vector_mask(struct ntb_dev *ntb, int db_vector)
1033 {
1034 struct intel_ntb_dev *ndev = ntb_ndev(ntb);
1035
1036 if (db_vector < 0 || db_vector > ndev->db_vec_count)
1037 return 0;
1038
1039 return ndev->db_valid_mask & ndev_vec_mask(ndev, db_vector);
1040 }
1041
1042 static u64 intel_ntb_db_read(struct ntb_dev *ntb)
1043 {
1044 struct intel_ntb_dev *ndev = ntb_ndev(ntb);
1045
1046 return ndev_db_read(ndev,
1047 ndev->self_mmio +
1048 ndev->self_reg->db_bell);
1049 }
1050
1051 static int intel_ntb_db_clear(struct ntb_dev *ntb, u64 db_bits)
1052 {
1053 struct intel_ntb_dev *ndev = ntb_ndev(ntb);
1054
1055 return ndev_db_write(ndev, db_bits,
1056 ndev->self_mmio +
1057 ndev->self_reg->db_bell);
1058 }
1059
1060 static int intel_ntb_db_set_mask(struct ntb_dev *ntb, u64 db_bits)
1061 {
1062 struct intel_ntb_dev *ndev = ntb_ndev(ntb);
1063
1064 return ndev_db_set_mask(ndev, db_bits,
1065 ndev->self_mmio +
1066 ndev->self_reg->db_mask);
1067 }
1068
1069 static int intel_ntb_db_clear_mask(struct ntb_dev *ntb, u64 db_bits)
1070 {
1071 struct intel_ntb_dev *ndev = ntb_ndev(ntb);
1072
1073 return ndev_db_clear_mask(ndev, db_bits,
1074 ndev->self_mmio +
1075 ndev->self_reg->db_mask);
1076 }
1077
1078 static int intel_ntb_peer_db_addr(struct ntb_dev *ntb,
1079 phys_addr_t *db_addr,
1080 resource_size_t *db_size)
1081 {
1082 struct intel_ntb_dev *ndev = ntb_ndev(ntb);
1083
1084 return ndev_db_addr(ndev, db_addr, db_size, ndev->peer_addr,
1085 ndev->peer_reg->db_bell);
1086 }
1087
1088 static int intel_ntb_peer_db_set(struct ntb_dev *ntb, u64 db_bits)
1089 {
1090 struct intel_ntb_dev *ndev = ntb_ndev(ntb);
1091
1092 return ndev_db_write(ndev, db_bits,
1093 ndev->peer_mmio +
1094 ndev->peer_reg->db_bell);
1095 }
1096
1097 static int intel_ntb_spad_is_unsafe(struct ntb_dev *ntb)
1098 {
1099 return ndev_ignore_unsafe(ntb_ndev(ntb), NTB_UNSAFE_SPAD);
1100 }
1101
1102 static int intel_ntb_spad_count(struct ntb_dev *ntb)
1103 {
1104 struct intel_ntb_dev *ndev;
1105
1106 ndev = container_of(ntb, struct intel_ntb_dev, ntb);
1107
1108 return ndev->spad_count;
1109 }
1110
1111 static u32 intel_ntb_spad_read(struct ntb_dev *ntb, int idx)
1112 {
1113 struct intel_ntb_dev *ndev = ntb_ndev(ntb);
1114
1115 return ndev_spad_read(ndev, idx,
1116 ndev->self_mmio +
1117 ndev->self_reg->spad);
1118 }
1119
1120 static int intel_ntb_spad_write(struct ntb_dev *ntb,
1121 int idx, u32 val)
1122 {
1123 struct intel_ntb_dev *ndev = ntb_ndev(ntb);
1124
1125 return ndev_spad_write(ndev, idx, val,
1126 ndev->self_mmio +
1127 ndev->self_reg->spad);
1128 }
1129
1130 static int intel_ntb_peer_spad_addr(struct ntb_dev *ntb, int idx,
1131 phys_addr_t *spad_addr)
1132 {
1133 struct intel_ntb_dev *ndev = ntb_ndev(ntb);
1134
1135 return ndev_spad_addr(ndev, idx, spad_addr, ndev->peer_addr,
1136 ndev->peer_reg->spad);
1137 }
1138
1139 static u32 intel_ntb_peer_spad_read(struct ntb_dev *ntb, int idx)
1140 {
1141 struct intel_ntb_dev *ndev = ntb_ndev(ntb);
1142
1143 return ndev_spad_read(ndev, idx,
1144 ndev->peer_mmio +
1145 ndev->peer_reg->spad);
1146 }
1147
1148 static int intel_ntb_peer_spad_write(struct ntb_dev *ntb,
1149 int idx, u32 val)
1150 {
1151 struct intel_ntb_dev *ndev = ntb_ndev(ntb);
1152
1153 return ndev_spad_write(ndev, idx, val,
1154 ndev->peer_mmio +
1155 ndev->peer_reg->spad);
1156 }
1157
1158 /* ATOM */
1159
1160 static u64 atom_db_ioread(void __iomem *mmio)
1161 {
1162 return ioread64(mmio);
1163 }
1164
1165 static void atom_db_iowrite(u64 bits, void __iomem *mmio)
1166 {
1167 iowrite64(bits, mmio);
1168 }
1169
1170 static int atom_poll_link(struct intel_ntb_dev *ndev)
1171 {
1172 u32 ntb_ctl;
1173
1174 ntb_ctl = ioread32(ndev->self_mmio + ATOM_NTBCNTL_OFFSET);
1175
1176 if (ntb_ctl == ndev->ntb_ctl)
1177 return 0;
1178
1179 ndev->ntb_ctl = ntb_ctl;
1180
1181 ndev->lnk_sta = ioread32(ndev->self_mmio + ATOM_LINK_STATUS_OFFSET);
1182
1183 return 1;
1184 }
1185
1186 static int atom_link_is_up(struct intel_ntb_dev *ndev)
1187 {
1188 return ATOM_NTB_CTL_ACTIVE(ndev->ntb_ctl);
1189 }
1190
1191 static int atom_link_is_err(struct intel_ntb_dev *ndev)
1192 {
1193 if (ioread32(ndev->self_mmio + ATOM_LTSSMSTATEJMP_OFFSET)
1194 & ATOM_LTSSMSTATEJMP_FORCEDETECT)
1195 return 1;
1196
1197 if (ioread32(ndev->self_mmio + ATOM_IBSTERRRCRVSTS0_OFFSET)
1198 & ATOM_IBIST_ERR_OFLOW)
1199 return 1;
1200
1201 return 0;
1202 }
1203
1204 static inline enum ntb_topo atom_ppd_topo(struct intel_ntb_dev *ndev, u32 ppd)
1205 {
1206 switch (ppd & ATOM_PPD_TOPO_MASK) {
1207 case ATOM_PPD_TOPO_B2B_USD:
1208 dev_dbg(ndev_dev(ndev), "PPD %d B2B USD\n", ppd);
1209 return NTB_TOPO_B2B_USD;
1210
1211 case ATOM_PPD_TOPO_B2B_DSD:
1212 dev_dbg(ndev_dev(ndev), "PPD %d B2B DSD\n", ppd);
1213 return NTB_TOPO_B2B_DSD;
1214
1215 case ATOM_PPD_TOPO_PRI_USD:
1216 case ATOM_PPD_TOPO_PRI_DSD: /* accept bogus PRI_DSD */
1217 case ATOM_PPD_TOPO_SEC_USD:
1218 case ATOM_PPD_TOPO_SEC_DSD: /* accept bogus SEC_DSD */
1219 dev_dbg(ndev_dev(ndev), "PPD %d non B2B disabled\n", ppd);
1220 return NTB_TOPO_NONE;
1221 }
1222
1223 dev_dbg(ndev_dev(ndev), "PPD %d invalid\n", ppd);
1224 return NTB_TOPO_NONE;
1225 }
1226
1227 static void atom_link_hb(struct work_struct *work)
1228 {
1229 struct intel_ntb_dev *ndev = hb_ndev(work);
1230 unsigned long poll_ts;
1231 void __iomem *mmio;
1232 u32 status32;
1233
1234 poll_ts = ndev->last_ts + ATOM_LINK_HB_TIMEOUT;
1235
1236 /* Delay polling the link status if an interrupt was received,
1237 * unless the cached link status says the link is down.
1238 */
1239 if (time_after(poll_ts, jiffies) && atom_link_is_up(ndev)) {
1240 schedule_delayed_work(&ndev->hb_timer, poll_ts - jiffies);
1241 return;
1242 }
1243
1244 if (atom_poll_link(ndev))
1245 ntb_link_event(&ndev->ntb);
1246
1247 if (atom_link_is_up(ndev) || !atom_link_is_err(ndev)) {
1248 schedule_delayed_work(&ndev->hb_timer, ATOM_LINK_HB_TIMEOUT);
1249 return;
1250 }
1251
1252 /* Link is down with error: recover the link! */
1253
1254 mmio = ndev->self_mmio;
1255
1256 /* Driver resets the NTB ModPhy lanes - magic! */
1257 iowrite8(0xe0, mmio + ATOM_MODPHY_PCSREG6);
1258 iowrite8(0x40, mmio + ATOM_MODPHY_PCSREG4);
1259 iowrite8(0x60, mmio + ATOM_MODPHY_PCSREG4);
1260 iowrite8(0x60, mmio + ATOM_MODPHY_PCSREG6);
1261
1262 /* Driver waits 100ms to allow the NTB ModPhy to settle */
1263 msleep(100);
1264
1265 /* Clear AER Errors, write to clear */
1266 status32 = ioread32(mmio + ATOM_ERRCORSTS_OFFSET);
1267 dev_dbg(ndev_dev(ndev), "ERRCORSTS = %x\n", status32);
1268 status32 &= PCI_ERR_COR_REP_ROLL;
1269 iowrite32(status32, mmio + ATOM_ERRCORSTS_OFFSET);
1270
1271 /* Clear unexpected electrical idle event in LTSSM, write to clear */
1272 status32 = ioread32(mmio + ATOM_LTSSMERRSTS0_OFFSET);
1273 dev_dbg(ndev_dev(ndev), "LTSSMERRSTS0 = %x\n", status32);
1274 status32 |= ATOM_LTSSMERRSTS0_UNEXPECTEDEI;
1275 iowrite32(status32, mmio + ATOM_LTSSMERRSTS0_OFFSET);
1276
1277 /* Clear DeSkew Buffer error, write to clear */
1278 status32 = ioread32(mmio + ATOM_DESKEWSTS_OFFSET);
1279 dev_dbg(ndev_dev(ndev), "DESKEWSTS = %x\n", status32);
1280 status32 |= ATOM_DESKEWSTS_DBERR;
1281 iowrite32(status32, mmio + ATOM_DESKEWSTS_OFFSET);
1282
1283 status32 = ioread32(mmio + ATOM_IBSTERRRCRVSTS0_OFFSET);
1284 dev_dbg(ndev_dev(ndev), "IBSTERRRCRVSTS0 = %x\n", status32);
1285 status32 &= ATOM_IBIST_ERR_OFLOW;
1286 iowrite32(status32, mmio + ATOM_IBSTERRRCRVSTS0_OFFSET);
1287
1288 /* Releases the NTB state machine to allow the link to retrain */
1289 status32 = ioread32(mmio + ATOM_LTSSMSTATEJMP_OFFSET);
1290 dev_dbg(ndev_dev(ndev), "LTSSMSTATEJMP = %x\n", status32);
1291 status32 &= ~ATOM_LTSSMSTATEJMP_FORCEDETECT;
1292 iowrite32(status32, mmio + ATOM_LTSSMSTATEJMP_OFFSET);
1293
1294 /* There is a potential race between the 2 NTB devices recovering at the
1295 * same time. If the times are the same, the link will not recover and
1296 * the driver will be stuck in this loop forever. Add a random interval
1297 * to the recovery time to prevent this race.
1298 */
1299 schedule_delayed_work(&ndev->hb_timer, ATOM_LINK_RECOVERY_TIME
1300 + prandom_u32() % ATOM_LINK_RECOVERY_TIME);
1301 }
1302
1303 static int atom_init_isr(struct intel_ntb_dev *ndev)
1304 {
1305 int rc;
1306
1307 rc = ndev_init_isr(ndev, 1, ATOM_DB_MSIX_VECTOR_COUNT,
1308 ATOM_DB_MSIX_VECTOR_SHIFT, ATOM_DB_TOTAL_SHIFT);
1309 if (rc)
1310 return rc;
1311
1312 /* ATOM doesn't have link status interrupt, poll on that platform */
1313 ndev->last_ts = jiffies;
1314 INIT_DELAYED_WORK(&ndev->hb_timer, atom_link_hb);
1315 schedule_delayed_work(&ndev->hb_timer, ATOM_LINK_HB_TIMEOUT);
1316
1317 return 0;
1318 }
1319
1320 static void atom_deinit_isr(struct intel_ntb_dev *ndev)
1321 {
1322 cancel_delayed_work_sync(&ndev->hb_timer);
1323 ndev_deinit_isr(ndev);
1324 }
1325
1326 static int atom_init_ntb(struct intel_ntb_dev *ndev)
1327 {
1328 ndev->mw_count = ATOM_MW_COUNT;
1329 ndev->spad_count = ATOM_SPAD_COUNT;
1330 ndev->db_count = ATOM_DB_COUNT;
1331
1332 switch (ndev->ntb.topo) {
1333 case NTB_TOPO_B2B_USD:
1334 case NTB_TOPO_B2B_DSD:
1335 ndev->self_reg = &atom_pri_reg;
1336 ndev->peer_reg = &atom_b2b_reg;
1337 ndev->xlat_reg = &atom_sec_xlat;
1338
1339 /* Enable Bus Master and Memory Space on the secondary side */
1340 iowrite16(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER,
1341 ndev->self_mmio + ATOM_SPCICMD_OFFSET);
1342
1343 break;
1344
1345 default:
1346 return -EINVAL;
1347 }
1348
1349 ndev->db_valid_mask = BIT_ULL(ndev->db_count) - 1;
1350
1351 return 0;
1352 }
1353
1354 static int atom_init_dev(struct intel_ntb_dev *ndev)
1355 {
1356 u32 ppd;
1357 int rc;
1358
1359 rc = pci_read_config_dword(ndev->ntb.pdev, ATOM_PPD_OFFSET, &ppd);
1360 if (rc)
1361 return -EIO;
1362
1363 ndev->ntb.topo = atom_ppd_topo(ndev, ppd);
1364 if (ndev->ntb.topo == NTB_TOPO_NONE)
1365 return -EINVAL;
1366
1367 rc = atom_init_ntb(ndev);
1368 if (rc)
1369 return rc;
1370
1371 rc = atom_init_isr(ndev);
1372 if (rc)
1373 return rc;
1374
1375 if (ndev->ntb.topo != NTB_TOPO_SEC) {
1376 /* Initiate PCI-E link training */
1377 rc = pci_write_config_dword(ndev->ntb.pdev, ATOM_PPD_OFFSET,
1378 ppd | ATOM_PPD_INIT_LINK);
1379 if (rc)
1380 return rc;
1381 }
1382
1383 return 0;
1384 }
1385
1386 static void atom_deinit_dev(struct intel_ntb_dev *ndev)
1387 {
1388 atom_deinit_isr(ndev);
1389 }
1390
1391 /* XEON */
1392
1393 static u64 xeon_db_ioread(void __iomem *mmio)
1394 {
1395 return (u64)ioread16(mmio);
1396 }
1397
1398 static void xeon_db_iowrite(u64 bits, void __iomem *mmio)
1399 {
1400 iowrite16((u16)bits, mmio);
1401 }
1402
1403 static int xeon_poll_link(struct intel_ntb_dev *ndev)
1404 {
1405 u16 reg_val;
1406 int rc;
1407
1408 ndev->reg->db_iowrite(ndev->db_link_mask,
1409 ndev->self_mmio +
1410 ndev->self_reg->db_bell);
1411
1412 rc = pci_read_config_word(ndev->ntb.pdev,
1413 XEON_LINK_STATUS_OFFSET, &reg_val);
1414 if (rc)
1415 return 0;
1416
1417 if (reg_val == ndev->lnk_sta)
1418 return 0;
1419
1420 ndev->lnk_sta = reg_val;
1421
1422 return 1;
1423 }
1424
1425 static int xeon_link_is_up(struct intel_ntb_dev *ndev)
1426 {
1427 if (ndev->ntb.topo == NTB_TOPO_SEC)
1428 return 1;
1429
1430 return NTB_LNK_STA_ACTIVE(ndev->lnk_sta);
1431 }
1432
1433 static inline enum ntb_topo xeon_ppd_topo(struct intel_ntb_dev *ndev, u8 ppd)
1434 {
1435 switch (ppd & XEON_PPD_TOPO_MASK) {
1436 case XEON_PPD_TOPO_B2B_USD:
1437 return NTB_TOPO_B2B_USD;
1438
1439 case XEON_PPD_TOPO_B2B_DSD:
1440 return NTB_TOPO_B2B_DSD;
1441
1442 case XEON_PPD_TOPO_PRI_USD:
1443 case XEON_PPD_TOPO_PRI_DSD: /* accept bogus PRI_DSD */
1444 return NTB_TOPO_PRI;
1445
1446 case XEON_PPD_TOPO_SEC_USD:
1447 case XEON_PPD_TOPO_SEC_DSD: /* accept bogus SEC_DSD */
1448 return NTB_TOPO_SEC;
1449 }
1450
1451 return NTB_TOPO_NONE;
1452 }
1453
1454 static inline int xeon_ppd_bar4_split(struct intel_ntb_dev *ndev, u8 ppd)
1455 {
1456 if (ppd & XEON_PPD_SPLIT_BAR_MASK) {
1457 dev_dbg(ndev_dev(ndev), "PPD %d split bar\n", ppd);
1458 return 1;
1459 }
1460 return 0;
1461 }
1462
1463 static int xeon_init_isr(struct intel_ntb_dev *ndev)
1464 {
1465 return ndev_init_isr(ndev, XEON_DB_MSIX_VECTOR_COUNT,
1466 XEON_DB_MSIX_VECTOR_COUNT,
1467 XEON_DB_MSIX_VECTOR_SHIFT,
1468 XEON_DB_TOTAL_SHIFT);
1469 }
1470
1471 static void xeon_deinit_isr(struct intel_ntb_dev *ndev)
1472 {
1473 ndev_deinit_isr(ndev);
1474 }
1475
1476 static int xeon_setup_b2b_mw(struct intel_ntb_dev *ndev,
1477 const struct intel_b2b_addr *addr,
1478 const struct intel_b2b_addr *peer_addr)
1479 {
1480 struct pci_dev *pdev;
1481 void __iomem *mmio;
1482 resource_size_t bar_size;
1483 phys_addr_t bar_addr;
1484 int b2b_bar;
1485 u8 bar_sz;
1486
1487 pdev = ndev_pdev(ndev);
1488 mmio = ndev->self_mmio;
1489
1490 if (ndev->b2b_idx >= ndev->mw_count) {
1491 dev_dbg(ndev_dev(ndev), "not using b2b mw\n");
1492 b2b_bar = 0;
1493 ndev->b2b_off = 0;
1494 } else {
1495 b2b_bar = ndev_mw_to_bar(ndev, ndev->b2b_idx);
1496 if (b2b_bar < 0)
1497 return -EIO;
1498
1499 dev_dbg(ndev_dev(ndev), "using b2b mw bar %d\n", b2b_bar);
1500
1501 bar_size = pci_resource_len(ndev->ntb.pdev, b2b_bar);
1502
1503 dev_dbg(ndev_dev(ndev), "b2b bar size %#llx\n", bar_size);
1504
1505 if (b2b_mw_share && XEON_B2B_MIN_SIZE <= bar_size >> 1) {
1506 dev_dbg(ndev_dev(ndev),
1507 "b2b using first half of bar\n");
1508 ndev->b2b_off = bar_size >> 1;
1509 } else if (XEON_B2B_MIN_SIZE <= bar_size) {
1510 dev_dbg(ndev_dev(ndev),
1511 "b2b using whole bar\n");
1512 ndev->b2b_off = 0;
1513 --ndev->mw_count;
1514 } else {
1515 dev_dbg(ndev_dev(ndev),
1516 "b2b bar size is too small\n");
1517 return -EIO;
1518 }
1519 }
1520
1521 /* Reset the secondary bar sizes to match the primary bar sizes,
1522 * except disable or halve the size of the b2b secondary bar.
1523 *
1524 * Note: code for each specific bar size register, because the register
1525 * offsets are not in a consistent order (bar5sz comes after ppd, odd).
1526 */
1527 pci_read_config_byte(pdev, XEON_PBAR23SZ_OFFSET, &bar_sz);
1528 dev_dbg(ndev_dev(ndev), "PBAR23SZ %#x\n", bar_sz);
1529 if (b2b_bar == 2) {
1530 if (ndev->b2b_off)
1531 bar_sz -= 1;
1532 else
1533 bar_sz = 0;
1534 }
1535 pci_write_config_byte(pdev, XEON_SBAR23SZ_OFFSET, bar_sz);
1536 pci_read_config_byte(pdev, XEON_SBAR23SZ_OFFSET, &bar_sz);
1537 dev_dbg(ndev_dev(ndev), "SBAR23SZ %#x\n", bar_sz);
1538
1539 if (!ndev->bar4_split) {
1540 pci_read_config_byte(pdev, XEON_PBAR45SZ_OFFSET, &bar_sz);
1541 dev_dbg(ndev_dev(ndev), "PBAR45SZ %#x\n", bar_sz);
1542 if (b2b_bar == 4) {
1543 if (ndev->b2b_off)
1544 bar_sz -= 1;
1545 else
1546 bar_sz = 0;
1547 }
1548 pci_write_config_byte(pdev, XEON_SBAR45SZ_OFFSET, bar_sz);
1549 pci_read_config_byte(pdev, XEON_SBAR45SZ_OFFSET, &bar_sz);
1550 dev_dbg(ndev_dev(ndev), "SBAR45SZ %#x\n", bar_sz);
1551 } else {
1552 pci_read_config_byte(pdev, XEON_PBAR4SZ_OFFSET, &bar_sz);
1553 dev_dbg(ndev_dev(ndev), "PBAR4SZ %#x\n", bar_sz);
1554 if (b2b_bar == 4) {
1555 if (ndev->b2b_off)
1556 bar_sz -= 1;
1557 else
1558 bar_sz = 0;
1559 }
1560 pci_write_config_byte(pdev, XEON_SBAR4SZ_OFFSET, bar_sz);
1561 pci_read_config_byte(pdev, XEON_SBAR4SZ_OFFSET, &bar_sz);
1562 dev_dbg(ndev_dev(ndev), "SBAR4SZ %#x\n", bar_sz);
1563
1564 pci_read_config_byte(pdev, XEON_PBAR5SZ_OFFSET, &bar_sz);
1565 dev_dbg(ndev_dev(ndev), "PBAR5SZ %#x\n", bar_sz);
1566 if (b2b_bar == 5) {
1567 if (ndev->b2b_off)
1568 bar_sz -= 1;
1569 else
1570 bar_sz = 0;
1571 }
1572 pci_write_config_byte(pdev, XEON_SBAR5SZ_OFFSET, bar_sz);
1573 pci_read_config_byte(pdev, XEON_SBAR5SZ_OFFSET, &bar_sz);
1574 dev_dbg(ndev_dev(ndev), "SBAR5SZ %#x\n", bar_sz);
1575 }
1576
1577 /* SBAR01 hit by first part of the b2b bar */
1578 if (b2b_bar == 0)
1579 bar_addr = addr->bar0_addr;
1580 else if (b2b_bar == 2)
1581 bar_addr = addr->bar2_addr64;
1582 else if (b2b_bar == 4 && !ndev->bar4_split)
1583 bar_addr = addr->bar4_addr64;
1584 else if (b2b_bar == 4)
1585 bar_addr = addr->bar4_addr32;
1586 else if (b2b_bar == 5)
1587 bar_addr = addr->bar5_addr32;
1588 else
1589 return -EIO;
1590
1591 dev_dbg(ndev_dev(ndev), "SBAR01 %#018llx\n", bar_addr);
1592 iowrite64(bar_addr, mmio + XEON_SBAR0BASE_OFFSET);
1593
1594 /* Other SBAR are normally hit by the PBAR xlat, except for b2b bar.
1595 * The b2b bar is either disabled above, or configured half-size, and
1596 * it starts at the PBAR xlat + offset.
1597 */
1598
1599 bar_addr = addr->bar2_addr64 + (b2b_bar == 2 ? ndev->b2b_off : 0);
1600 iowrite64(bar_addr, mmio + XEON_SBAR23BASE_OFFSET);
1601 bar_addr = ioread64(mmio + XEON_SBAR23BASE_OFFSET);
1602 dev_dbg(ndev_dev(ndev), "SBAR23 %#018llx\n", bar_addr);
1603
1604 if (!ndev->bar4_split) {
1605 bar_addr = addr->bar4_addr64 +
1606 (b2b_bar == 4 ? ndev->b2b_off : 0);
1607 iowrite64(bar_addr, mmio + XEON_SBAR45BASE_OFFSET);
1608 bar_addr = ioread64(mmio + XEON_SBAR45BASE_OFFSET);
1609 dev_dbg(ndev_dev(ndev), "SBAR45 %#018llx\n", bar_addr);
1610 } else {
1611 bar_addr = addr->bar4_addr32 +
1612 (b2b_bar == 4 ? ndev->b2b_off : 0);
1613 iowrite32(bar_addr, mmio + XEON_SBAR4BASE_OFFSET);
1614 bar_addr = ioread32(mmio + XEON_SBAR4BASE_OFFSET);
1615 dev_dbg(ndev_dev(ndev), "SBAR4 %#010llx\n", bar_addr);
1616
1617 bar_addr = addr->bar5_addr32 +
1618 (b2b_bar == 5 ? ndev->b2b_off : 0);
1619 iowrite32(bar_addr, mmio + XEON_SBAR5BASE_OFFSET);
1620 bar_addr = ioread32(mmio + XEON_SBAR5BASE_OFFSET);
1621 dev_dbg(ndev_dev(ndev), "SBAR5 %#010llx\n", bar_addr);
1622 }
1623
1624 /* setup incoming bar limits == base addrs (zero length windows) */
1625
1626 bar_addr = addr->bar2_addr64 + (b2b_bar == 2 ? ndev->b2b_off : 0);
1627 iowrite64(bar_addr, mmio + XEON_SBAR23LMT_OFFSET);
1628 bar_addr = ioread64(mmio + XEON_SBAR23LMT_OFFSET);
1629 dev_dbg(ndev_dev(ndev), "SBAR23LMT %#018llx\n", bar_addr);
1630
1631 if (!ndev->bar4_split) {
1632 bar_addr = addr->bar4_addr64 +
1633 (b2b_bar == 4 ? ndev->b2b_off : 0);
1634 iowrite64(bar_addr, mmio + XEON_SBAR45LMT_OFFSET);
1635 bar_addr = ioread64(mmio + XEON_SBAR45LMT_OFFSET);
1636 dev_dbg(ndev_dev(ndev), "SBAR45LMT %#018llx\n", bar_addr);
1637 } else {
1638 bar_addr = addr->bar4_addr32 +
1639 (b2b_bar == 4 ? ndev->b2b_off : 0);
1640 iowrite32(bar_addr, mmio + XEON_SBAR4LMT_OFFSET);
1641 bar_addr = ioread32(mmio + XEON_SBAR4LMT_OFFSET);
1642 dev_dbg(ndev_dev(ndev), "SBAR4LMT %#010llx\n", bar_addr);
1643
1644 bar_addr = addr->bar5_addr32 +
1645 (b2b_bar == 5 ? ndev->b2b_off : 0);
1646 iowrite32(bar_addr, mmio + XEON_SBAR5LMT_OFFSET);
1647 bar_addr = ioread32(mmio + XEON_SBAR5LMT_OFFSET);
1648 dev_dbg(ndev_dev(ndev), "SBAR5LMT %#05llx\n", bar_addr);
1649 }
1650
1651 /* zero incoming translation addrs */
1652 iowrite64(0, mmio + XEON_SBAR23XLAT_OFFSET);
1653
1654 if (!ndev->bar4_split) {
1655 iowrite64(0, mmio + XEON_SBAR45XLAT_OFFSET);
1656 } else {
1657 iowrite32(0, mmio + XEON_SBAR4XLAT_OFFSET);
1658 iowrite32(0, mmio + XEON_SBAR5XLAT_OFFSET);
1659 }
1660
1661 /* zero outgoing translation limits (whole bar size windows) */
1662 iowrite64(0, mmio + XEON_PBAR23LMT_OFFSET);
1663 if (!ndev->bar4_split) {
1664 iowrite64(0, mmio + XEON_PBAR45LMT_OFFSET);
1665 } else {
1666 iowrite32(0, mmio + XEON_PBAR4LMT_OFFSET);
1667 iowrite32(0, mmio + XEON_PBAR5LMT_OFFSET);
1668 }
1669
1670 /* set outgoing translation offsets */
1671 bar_addr = peer_addr->bar2_addr64;
1672 iowrite64(bar_addr, mmio + XEON_PBAR23XLAT_OFFSET);
1673 bar_addr = ioread64(mmio + XEON_PBAR23XLAT_OFFSET);
1674 dev_dbg(ndev_dev(ndev), "PBAR23XLAT %#018llx\n", bar_addr);
1675
1676 if (!ndev->bar4_split) {
1677 bar_addr = peer_addr->bar4_addr64;
1678 iowrite64(bar_addr, mmio + XEON_PBAR45XLAT_OFFSET);
1679 bar_addr = ioread64(mmio + XEON_PBAR45XLAT_OFFSET);
1680 dev_dbg(ndev_dev(ndev), "PBAR45XLAT %#018llx\n", bar_addr);
1681 } else {
1682 bar_addr = peer_addr->bar4_addr32;
1683 iowrite32(bar_addr, mmio + XEON_PBAR4XLAT_OFFSET);
1684 bar_addr = ioread32(mmio + XEON_PBAR4XLAT_OFFSET);
1685 dev_dbg(ndev_dev(ndev), "PBAR4XLAT %#010llx\n", bar_addr);
1686
1687 bar_addr = peer_addr->bar5_addr32;
1688 iowrite32(bar_addr, mmio + XEON_PBAR5XLAT_OFFSET);
1689 bar_addr = ioread32(mmio + XEON_PBAR5XLAT_OFFSET);
1690 dev_dbg(ndev_dev(ndev), "PBAR5XLAT %#010llx\n", bar_addr);
1691 }
1692
1693 /* set the translation offset for b2b registers */
1694 if (b2b_bar == 0)
1695 bar_addr = peer_addr->bar0_addr;
1696 else if (b2b_bar == 2)
1697 bar_addr = peer_addr->bar2_addr64;
1698 else if (b2b_bar == 4 && !ndev->bar4_split)
1699 bar_addr = peer_addr->bar4_addr64;
1700 else if (b2b_bar == 4)
1701 bar_addr = peer_addr->bar4_addr32;
1702 else if (b2b_bar == 5)
1703 bar_addr = peer_addr->bar5_addr32;
1704 else
1705 return -EIO;
1706
1707 /* B2B_XLAT_OFFSET is 64bit, but can only take 32bit writes */
1708 dev_dbg(ndev_dev(ndev), "B2BXLAT %#018llx\n", bar_addr);
1709 iowrite32(bar_addr, mmio + XEON_B2B_XLAT_OFFSETL);
1710 iowrite32(bar_addr >> 32, mmio + XEON_B2B_XLAT_OFFSETU);
1711
1712 if (b2b_bar) {
1713 /* map peer ntb mmio config space registers */
1714 ndev->peer_mmio = pci_iomap(pdev, b2b_bar,
1715 XEON_B2B_MIN_SIZE);
1716 if (!ndev->peer_mmio)
1717 return -EIO;
1718 }
1719
1720 return 0;
1721 }
1722
1723 static int xeon_init_ntb(struct intel_ntb_dev *ndev)
1724 {
1725 int rc;
1726 u32 ntb_ctl;
1727
1728 if (ndev->bar4_split)
1729 ndev->mw_count = HSX_SPLIT_BAR_MW_COUNT;
1730 else
1731 ndev->mw_count = XEON_MW_COUNT;
1732
1733 ndev->spad_count = XEON_SPAD_COUNT;
1734 ndev->db_count = XEON_DB_COUNT;
1735 ndev->db_link_mask = XEON_DB_LINK_BIT;
1736
1737 switch (ndev->ntb.topo) {
1738 case NTB_TOPO_PRI:
1739 if (ndev->hwerr_flags & NTB_HWERR_SDOORBELL_LOCKUP) {
1740 dev_err(ndev_dev(ndev), "NTB Primary config disabled\n");
1741 return -EINVAL;
1742 }
1743
1744 /* enable link to allow secondary side device to appear */
1745 ntb_ctl = ioread32(ndev->self_mmio + ndev->reg->ntb_ctl);
1746 ntb_ctl &= ~NTB_CTL_DISABLE;
1747 iowrite32(ntb_ctl, ndev->self_mmio + ndev->reg->ntb_ctl);
1748
1749 /* use half the spads for the peer */
1750 ndev->spad_count >>= 1;
1751 ndev->self_reg = &xeon_pri_reg;
1752 ndev->peer_reg = &xeon_sec_reg;
1753 ndev->xlat_reg = &xeon_sec_xlat;
1754 break;
1755
1756 case NTB_TOPO_SEC:
1757 if (ndev->hwerr_flags & NTB_HWERR_SDOORBELL_LOCKUP) {
1758 dev_err(ndev_dev(ndev), "NTB Secondary config disabled\n");
1759 return -EINVAL;
1760 }
1761 /* use half the spads for the peer */
1762 ndev->spad_count >>= 1;
1763 ndev->self_reg = &xeon_sec_reg;
1764 ndev->peer_reg = &xeon_pri_reg;
1765 ndev->xlat_reg = &xeon_pri_xlat;
1766 break;
1767
1768 case NTB_TOPO_B2B_USD:
1769 case NTB_TOPO_B2B_DSD:
1770 ndev->self_reg = &xeon_pri_reg;
1771 ndev->peer_reg = &xeon_b2b_reg;
1772 ndev->xlat_reg = &xeon_sec_xlat;
1773
1774 if (ndev->hwerr_flags & NTB_HWERR_SDOORBELL_LOCKUP) {
1775 ndev->peer_reg = &xeon_pri_reg;
1776
1777 if (b2b_mw_idx < 0)
1778 ndev->b2b_idx = b2b_mw_idx + ndev->mw_count;
1779 else
1780 ndev->b2b_idx = b2b_mw_idx;
1781
1782 dev_dbg(ndev_dev(ndev),
1783 "setting up b2b mw idx %d means %d\n",
1784 b2b_mw_idx, ndev->b2b_idx);
1785
1786 } else if (ndev->hwerr_flags & NTB_HWERR_B2BDOORBELL_BIT14) {
1787 dev_warn(ndev_dev(ndev), "Reduce doorbell count by 1\n");
1788 ndev->db_count -= 1;
1789 }
1790
1791 if (ndev->ntb.topo == NTB_TOPO_B2B_USD) {
1792 rc = xeon_setup_b2b_mw(ndev,
1793 &xeon_b2b_dsd_addr,
1794 &xeon_b2b_usd_addr);
1795 } else {
1796 rc = xeon_setup_b2b_mw(ndev,
1797 &xeon_b2b_usd_addr,
1798 &xeon_b2b_dsd_addr);
1799 }
1800 if (rc)
1801 return rc;
1802
1803 /* Enable Bus Master and Memory Space on the secondary side */
1804 iowrite16(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER,
1805 ndev->self_mmio + XEON_SPCICMD_OFFSET);
1806
1807 break;
1808
1809 default:
1810 return -EINVAL;
1811 }
1812
1813 ndev->db_valid_mask = BIT_ULL(ndev->db_count) - 1;
1814
1815 ndev->reg->db_iowrite(ndev->db_valid_mask,
1816 ndev->self_mmio +
1817 ndev->self_reg->db_mask);
1818
1819 return 0;
1820 }
1821
1822 static int xeon_init_dev(struct intel_ntb_dev *ndev)
1823 {
1824 struct pci_dev *pdev;
1825 u8 ppd;
1826 int rc, mem;
1827
1828 pdev = ndev_pdev(ndev);
1829
1830 switch (pdev->device) {
1831 /* There is a Xeon hardware errata related to writes to SDOORBELL or
1832 * B2BDOORBELL in conjunction with inbound access to NTB MMIO Space,
1833 * which may hang the system. To workaround this use the second memory
1834 * window to access the interrupt and scratch pad registers on the
1835 * remote system.
1836 */
1837 case PCI_DEVICE_ID_INTEL_NTB_SS_JSF:
1838 case PCI_DEVICE_ID_INTEL_NTB_PS_JSF:
1839 case PCI_DEVICE_ID_INTEL_NTB_B2B_JSF:
1840 case PCI_DEVICE_ID_INTEL_NTB_SS_SNB:
1841 case PCI_DEVICE_ID_INTEL_NTB_PS_SNB:
1842 case PCI_DEVICE_ID_INTEL_NTB_B2B_SNB:
1843 case PCI_DEVICE_ID_INTEL_NTB_SS_IVT:
1844 case PCI_DEVICE_ID_INTEL_NTB_PS_IVT:
1845 case PCI_DEVICE_ID_INTEL_NTB_B2B_IVT:
1846 case PCI_DEVICE_ID_INTEL_NTB_SS_HSX:
1847 case PCI_DEVICE_ID_INTEL_NTB_PS_HSX:
1848 case PCI_DEVICE_ID_INTEL_NTB_B2B_HSX:
1849 case PCI_DEVICE_ID_INTEL_NTB_SS_BDX:
1850 case PCI_DEVICE_ID_INTEL_NTB_PS_BDX:
1851 case PCI_DEVICE_ID_INTEL_NTB_B2B_BDX:
1852 ndev->hwerr_flags |= NTB_HWERR_SDOORBELL_LOCKUP;
1853 break;
1854 }
1855
1856 switch (pdev->device) {
1857 /* There is a hardware errata related to accessing any register in
1858 * SB01BASE in the presence of bidirectional traffic crossing the NTB.
1859 */
1860 case PCI_DEVICE_ID_INTEL_NTB_SS_IVT:
1861 case PCI_DEVICE_ID_INTEL_NTB_PS_IVT:
1862 case PCI_DEVICE_ID_INTEL_NTB_B2B_IVT:
1863 case PCI_DEVICE_ID_INTEL_NTB_SS_HSX:
1864 case PCI_DEVICE_ID_INTEL_NTB_PS_HSX:
1865 case PCI_DEVICE_ID_INTEL_NTB_B2B_HSX:
1866 case PCI_DEVICE_ID_INTEL_NTB_SS_BDX:
1867 case PCI_DEVICE_ID_INTEL_NTB_PS_BDX:
1868 case PCI_DEVICE_ID_INTEL_NTB_B2B_BDX:
1869 ndev->hwerr_flags |= NTB_HWERR_SB01BASE_LOCKUP;
1870 break;
1871 }
1872
1873 switch (pdev->device) {
1874 /* HW Errata on bit 14 of b2bdoorbell register. Writes will not be
1875 * mirrored to the remote system. Shrink the number of bits by one,
1876 * since bit 14 is the last bit.
1877 */
1878 case PCI_DEVICE_ID_INTEL_NTB_SS_JSF:
1879 case PCI_DEVICE_ID_INTEL_NTB_PS_JSF:
1880 case PCI_DEVICE_ID_INTEL_NTB_B2B_JSF:
1881 case PCI_DEVICE_ID_INTEL_NTB_SS_SNB:
1882 case PCI_DEVICE_ID_INTEL_NTB_PS_SNB:
1883 case PCI_DEVICE_ID_INTEL_NTB_B2B_SNB:
1884 case PCI_DEVICE_ID_INTEL_NTB_SS_IVT:
1885 case PCI_DEVICE_ID_INTEL_NTB_PS_IVT:
1886 case PCI_DEVICE_ID_INTEL_NTB_B2B_IVT:
1887 case PCI_DEVICE_ID_INTEL_NTB_SS_HSX:
1888 case PCI_DEVICE_ID_INTEL_NTB_PS_HSX:
1889 case PCI_DEVICE_ID_INTEL_NTB_B2B_HSX:
1890 case PCI_DEVICE_ID_INTEL_NTB_SS_BDX:
1891 case PCI_DEVICE_ID_INTEL_NTB_PS_BDX:
1892 case PCI_DEVICE_ID_INTEL_NTB_B2B_BDX:
1893 ndev->hwerr_flags |= NTB_HWERR_B2BDOORBELL_BIT14;
1894 break;
1895 }
1896
1897 ndev->reg = &xeon_reg;
1898
1899 rc = pci_read_config_byte(pdev, XEON_PPD_OFFSET, &ppd);
1900 if (rc)
1901 return -EIO;
1902
1903 ndev->ntb.topo = xeon_ppd_topo(ndev, ppd);
1904 dev_dbg(ndev_dev(ndev), "ppd %#x topo %s\n", ppd,
1905 ntb_topo_string(ndev->ntb.topo));
1906 if (ndev->ntb.topo == NTB_TOPO_NONE)
1907 return -EINVAL;
1908
1909 if (ndev->ntb.topo != NTB_TOPO_SEC) {
1910 ndev->bar4_split = xeon_ppd_bar4_split(ndev, ppd);
1911 dev_dbg(ndev_dev(ndev), "ppd %#x bar4_split %d\n",
1912 ppd, ndev->bar4_split);
1913 } else {
1914 /* This is a way for transparent BAR to figure out if we are
1915 * doing split BAR or not. There is no way for the hw on the
1916 * transparent side to know and set the PPD.
1917 */
1918 mem = pci_select_bars(pdev, IORESOURCE_MEM);
1919 ndev->bar4_split = hweight32(mem) ==
1920 HSX_SPLIT_BAR_MW_COUNT + 1;
1921 dev_dbg(ndev_dev(ndev), "mem %#x bar4_split %d\n",
1922 mem, ndev->bar4_split);
1923 }
1924
1925 rc = xeon_init_ntb(ndev);
1926 if (rc)
1927 return rc;
1928
1929 return xeon_init_isr(ndev);
1930 }
1931
1932 static void xeon_deinit_dev(struct intel_ntb_dev *ndev)
1933 {
1934 xeon_deinit_isr(ndev);
1935 }
1936
1937 static int intel_ntb_init_pci(struct intel_ntb_dev *ndev, struct pci_dev *pdev)
1938 {
1939 int rc;
1940
1941 pci_set_drvdata(pdev, ndev);
1942
1943 rc = pci_enable_device(pdev);
1944 if (rc)
1945 goto err_pci_enable;
1946
1947 rc = pci_request_regions(pdev, NTB_NAME);
1948 if (rc)
1949 goto err_pci_regions;
1950
1951 pci_set_master(pdev);
1952
1953 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1954 if (rc) {
1955 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1956 if (rc)
1957 goto err_dma_mask;
1958 dev_warn(ndev_dev(ndev), "Cannot DMA highmem\n");
1959 }
1960
1961 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1962 if (rc) {
1963 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1964 if (rc)
1965 goto err_dma_mask;
1966 dev_warn(ndev_dev(ndev), "Cannot DMA consistent highmem\n");
1967 }
1968
1969 ndev->self_mmio = pci_iomap(pdev, 0, 0);
1970 if (!ndev->self_mmio) {
1971 rc = -EIO;
1972 goto err_mmio;
1973 }
1974 ndev->peer_mmio = ndev->self_mmio;
1975
1976 return 0;
1977
1978 err_mmio:
1979 err_dma_mask:
1980 pci_clear_master(pdev);
1981 pci_release_regions(pdev);
1982 err_pci_regions:
1983 pci_disable_device(pdev);
1984 err_pci_enable:
1985 pci_set_drvdata(pdev, NULL);
1986 return rc;
1987 }
1988
1989 static void intel_ntb_deinit_pci(struct intel_ntb_dev *ndev)
1990 {
1991 struct pci_dev *pdev = ndev_pdev(ndev);
1992
1993 if (ndev->peer_mmio && ndev->peer_mmio != ndev->self_mmio)
1994 pci_iounmap(pdev, ndev->peer_mmio);
1995 pci_iounmap(pdev, ndev->self_mmio);
1996
1997 pci_clear_master(pdev);
1998 pci_release_regions(pdev);
1999 pci_disable_device(pdev);
2000 pci_set_drvdata(pdev, NULL);
2001 }
2002
2003 static inline void ndev_init_struct(struct intel_ntb_dev *ndev,
2004 struct pci_dev *pdev)
2005 {
2006 ndev->ntb.pdev = pdev;
2007 ndev->ntb.topo = NTB_TOPO_NONE;
2008 ndev->ntb.ops = &intel_ntb_ops;
2009
2010 ndev->b2b_off = 0;
2011 ndev->b2b_idx = INT_MAX;
2012
2013 ndev->bar4_split = 0;
2014
2015 ndev->mw_count = 0;
2016 ndev->spad_count = 0;
2017 ndev->db_count = 0;
2018 ndev->db_vec_count = 0;
2019 ndev->db_vec_shift = 0;
2020
2021 ndev->ntb_ctl = 0;
2022 ndev->lnk_sta = 0;
2023
2024 ndev->db_valid_mask = 0;
2025 ndev->db_link_mask = 0;
2026 ndev->db_mask = 0;
2027
2028 spin_lock_init(&ndev->db_mask_lock);
2029 }
2030
2031 static int intel_ntb_pci_probe(struct pci_dev *pdev,
2032 const struct pci_device_id *id)
2033 {
2034 struct intel_ntb_dev *ndev;
2035 int rc, node;
2036
2037 node = dev_to_node(&pdev->dev);
2038
2039 if (pdev_is_atom(pdev)) {
2040 ndev = kzalloc_node(sizeof(*ndev), GFP_KERNEL, node);
2041 if (!ndev) {
2042 rc = -ENOMEM;
2043 goto err_ndev;
2044 }
2045
2046 ndev_init_struct(ndev, pdev);
2047
2048 rc = intel_ntb_init_pci(ndev, pdev);
2049 if (rc)
2050 goto err_init_pci;
2051
2052 rc = atom_init_dev(ndev);
2053 if (rc)
2054 goto err_init_dev;
2055
2056 } else if (pdev_is_xeon(pdev)) {
2057 ndev = kzalloc_node(sizeof(*ndev), GFP_KERNEL, node);
2058 if (!ndev) {
2059 rc = -ENOMEM;
2060 goto err_ndev;
2061 }
2062
2063 ndev_init_struct(ndev, pdev);
2064
2065 rc = intel_ntb_init_pci(ndev, pdev);
2066 if (rc)
2067 goto err_init_pci;
2068
2069 rc = xeon_init_dev(ndev);
2070 if (rc)
2071 goto err_init_dev;
2072
2073 } else {
2074 rc = -EINVAL;
2075 goto err_ndev;
2076 }
2077
2078 ndev_reset_unsafe_flags(ndev);
2079
2080 ndev->reg->poll_link(ndev);
2081
2082 ndev_init_debugfs(ndev);
2083
2084 rc = ntb_register_device(&ndev->ntb);
2085 if (rc)
2086 goto err_register;
2087
2088 dev_info(&pdev->dev, "NTB device registered.\n");
2089
2090 return 0;
2091
2092 err_register:
2093 ndev_deinit_debugfs(ndev);
2094 if (pdev_is_atom(pdev))
2095 atom_deinit_dev(ndev);
2096 else if (pdev_is_xeon(pdev))
2097 xeon_deinit_dev(ndev);
2098 err_init_dev:
2099 intel_ntb_deinit_pci(ndev);
2100 err_init_pci:
2101 kfree(ndev);
2102 err_ndev:
2103 return rc;
2104 }
2105
2106 static void intel_ntb_pci_remove(struct pci_dev *pdev)
2107 {
2108 struct intel_ntb_dev *ndev = pci_get_drvdata(pdev);
2109
2110 ntb_unregister_device(&ndev->ntb);
2111 ndev_deinit_debugfs(ndev);
2112 if (pdev_is_atom(pdev))
2113 atom_deinit_dev(ndev);
2114 else if (pdev_is_xeon(pdev))
2115 xeon_deinit_dev(ndev);
2116 intel_ntb_deinit_pci(ndev);
2117 kfree(ndev);
2118 }
2119
2120 static const struct intel_ntb_reg atom_reg = {
2121 .poll_link = atom_poll_link,
2122 .link_is_up = atom_link_is_up,
2123 .db_ioread = atom_db_ioread,
2124 .db_iowrite = atom_db_iowrite,
2125 .db_size = sizeof(u64),
2126 .ntb_ctl = ATOM_NTBCNTL_OFFSET,
2127 .mw_bar = {2, 4},
2128 };
2129
2130 static const struct intel_ntb_alt_reg atom_pri_reg = {
2131 .db_bell = ATOM_PDOORBELL_OFFSET,
2132 .db_mask = ATOM_PDBMSK_OFFSET,
2133 .spad = ATOM_SPAD_OFFSET,
2134 };
2135
2136 static const struct intel_ntb_alt_reg atom_b2b_reg = {
2137 .db_bell = ATOM_B2B_DOORBELL_OFFSET,
2138 .spad = ATOM_B2B_SPAD_OFFSET,
2139 };
2140
2141 static const struct intel_ntb_xlat_reg atom_sec_xlat = {
2142 /* FIXME : .bar0_base = ATOM_SBAR0BASE_OFFSET, */
2143 /* FIXME : .bar2_limit = ATOM_SBAR2LMT_OFFSET, */
2144 .bar2_xlat = ATOM_SBAR2XLAT_OFFSET,
2145 };
2146
2147 static const struct intel_ntb_reg xeon_reg = {
2148 .poll_link = xeon_poll_link,
2149 .link_is_up = xeon_link_is_up,
2150 .db_ioread = xeon_db_ioread,
2151 .db_iowrite = xeon_db_iowrite,
2152 .db_size = sizeof(u32),
2153 .ntb_ctl = XEON_NTBCNTL_OFFSET,
2154 .mw_bar = {2, 4, 5},
2155 };
2156
2157 static const struct intel_ntb_alt_reg xeon_pri_reg = {
2158 .db_bell = XEON_PDOORBELL_OFFSET,
2159 .db_mask = XEON_PDBMSK_OFFSET,
2160 .spad = XEON_SPAD_OFFSET,
2161 };
2162
2163 static const struct intel_ntb_alt_reg xeon_sec_reg = {
2164 .db_bell = XEON_SDOORBELL_OFFSET,
2165 .db_mask = XEON_SDBMSK_OFFSET,
2166 /* second half of the scratchpads */
2167 .spad = XEON_SPAD_OFFSET + (XEON_SPAD_COUNT << 1),
2168 };
2169
2170 static const struct intel_ntb_alt_reg xeon_b2b_reg = {
2171 .db_bell = XEON_B2B_DOORBELL_OFFSET,
2172 .spad = XEON_B2B_SPAD_OFFSET,
2173 };
2174
2175 static const struct intel_ntb_xlat_reg xeon_pri_xlat = {
2176 /* Note: no primary .bar0_base visible to the secondary side.
2177 *
2178 * The secondary side cannot get the base address stored in primary
2179 * bars. The base address is necessary to set the limit register to
2180 * any value other than zero, or unlimited.
2181 *
2182 * WITHOUT THE BASE ADDRESS, THE SECONDARY SIDE CANNOT DISABLE the
2183 * window by setting the limit equal to base, nor can it limit the size
2184 * of the memory window by setting the limit to base + size.
2185 */
2186 .bar2_limit = XEON_PBAR23LMT_OFFSET,
2187 .bar2_xlat = XEON_PBAR23XLAT_OFFSET,
2188 };
2189
2190 static const struct intel_ntb_xlat_reg xeon_sec_xlat = {
2191 .bar0_base = XEON_SBAR0BASE_OFFSET,
2192 .bar2_limit = XEON_SBAR23LMT_OFFSET,
2193 .bar2_xlat = XEON_SBAR23XLAT_OFFSET,
2194 };
2195
2196 static struct intel_b2b_addr xeon_b2b_usd_addr = {
2197 .bar2_addr64 = XEON_B2B_BAR2_USD_ADDR64,
2198 .bar4_addr64 = XEON_B2B_BAR4_USD_ADDR64,
2199 .bar4_addr32 = XEON_B2B_BAR4_USD_ADDR32,
2200 .bar5_addr32 = XEON_B2B_BAR5_USD_ADDR32,
2201 };
2202
2203 static struct intel_b2b_addr xeon_b2b_dsd_addr = {
2204 .bar2_addr64 = XEON_B2B_BAR2_DSD_ADDR64,
2205 .bar4_addr64 = XEON_B2B_BAR4_DSD_ADDR64,
2206 .bar4_addr32 = XEON_B2B_BAR4_DSD_ADDR32,
2207 .bar5_addr32 = XEON_B2B_BAR5_DSD_ADDR32,
2208 };
2209
2210 /* operations for primary side of local ntb */
2211 static const struct ntb_dev_ops intel_ntb_ops = {
2212 .mw_count = intel_ntb_mw_count,
2213 .mw_get_range = intel_ntb_mw_get_range,
2214 .mw_set_trans = intel_ntb_mw_set_trans,
2215 .link_is_up = intel_ntb_link_is_up,
2216 .link_enable = intel_ntb_link_enable,
2217 .link_disable = intel_ntb_link_disable,
2218 .db_is_unsafe = intel_ntb_db_is_unsafe,
2219 .db_valid_mask = intel_ntb_db_valid_mask,
2220 .db_vector_count = intel_ntb_db_vector_count,
2221 .db_vector_mask = intel_ntb_db_vector_mask,
2222 .db_read = intel_ntb_db_read,
2223 .db_clear = intel_ntb_db_clear,
2224 .db_set_mask = intel_ntb_db_set_mask,
2225 .db_clear_mask = intel_ntb_db_clear_mask,
2226 .peer_db_addr = intel_ntb_peer_db_addr,
2227 .peer_db_set = intel_ntb_peer_db_set,
2228 .spad_is_unsafe = intel_ntb_spad_is_unsafe,
2229 .spad_count = intel_ntb_spad_count,
2230 .spad_read = intel_ntb_spad_read,
2231 .spad_write = intel_ntb_spad_write,
2232 .peer_spad_addr = intel_ntb_peer_spad_addr,
2233 .peer_spad_read = intel_ntb_peer_spad_read,
2234 .peer_spad_write = intel_ntb_peer_spad_write,
2235 };
2236
2237 static const struct file_operations intel_ntb_debugfs_info = {
2238 .owner = THIS_MODULE,
2239 .open = simple_open,
2240 .read = ndev_debugfs_read,
2241 };
2242
2243 static const struct pci_device_id intel_ntb_pci_tbl[] = {
2244 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_BWD)},
2245 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_JSF)},
2246 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_SNB)},
2247 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_IVT)},
2248 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_HSX)},
2249 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_BDX)},
2250 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_PS_JSF)},
2251 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_PS_SNB)},
2252 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_PS_IVT)},
2253 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_PS_HSX)},
2254 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_PS_BDX)},
2255 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_SS_JSF)},
2256 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_SS_SNB)},
2257 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_SS_IVT)},
2258 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_SS_HSX)},
2259 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_SS_BDX)},
2260 {0}
2261 };
2262 MODULE_DEVICE_TABLE(pci, intel_ntb_pci_tbl);
2263
2264 static struct pci_driver intel_ntb_pci_driver = {
2265 .name = KBUILD_MODNAME,
2266 .id_table = intel_ntb_pci_tbl,
2267 .probe = intel_ntb_pci_probe,
2268 .remove = intel_ntb_pci_remove,
2269 };
2270
2271 static int __init intel_ntb_pci_driver_init(void)
2272 {
2273 pr_info("%s %s\n", NTB_DESC, NTB_VER);
2274
2275 if (debugfs_initialized())
2276 debugfs_dir = debugfs_create_dir(KBUILD_MODNAME, NULL);
2277
2278 return pci_register_driver(&intel_ntb_pci_driver);
2279 }
2280 module_init(intel_ntb_pci_driver_init);
2281
2282 static void __exit intel_ntb_pci_driver_exit(void)
2283 {
2284 pci_unregister_driver(&intel_ntb_pci_driver);
2285
2286 debugfs_remove_recursive(debugfs_dir);
2287 }
2288 module_exit(intel_ntb_pci_driver_exit);
2289
Linux kernel - Deliverables
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