2 * NVM Express device driver
3 * Copyright (c) 2011-2014, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 #include <linux/bitops.h>
16 #include <linux/blkdev.h>
17 #include <linux/blk-mq.h>
18 #include <linux/cpu.h>
19 #include <linux/delay.h>
20 #include <linux/errno.h>
22 #include <linux/genhd.h>
23 #include <linux/hdreg.h>
24 #include <linux/idr.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
28 #include <linux/kdev_t.h>
29 #include <linux/kthread.h>
30 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/moduleparam.h>
34 #include <linux/pci.h>
35 #include <linux/poison.h>
36 #include <linux/ptrace.h>
37 #include <linux/sched.h>
38 #include <linux/slab.h>
39 #include <linux/t10-pi.h>
40 #include <linux/types.h>
43 #include <linux/io-64-nonatomic-lo-hi.h>
44 #include <asm/unaligned.h>
46 #include <uapi/linux/nvme_ioctl.h>
49 #define NVME_MINORS (1U << MINORBITS)
50 #define NVME_Q_DEPTH 1024
51 #define NVME_AQ_DEPTH 256
52 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
53 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
55 unsigned char admin_timeout
= 60;
56 module_param(admin_timeout
, byte
, 0644);
57 MODULE_PARM_DESC(admin_timeout
, "timeout in seconds for admin commands");
59 unsigned char nvme_io_timeout
= 30;
60 module_param_named(io_timeout
, nvme_io_timeout
, byte
, 0644);
61 MODULE_PARM_DESC(io_timeout
, "timeout in seconds for I/O");
63 unsigned char shutdown_timeout
= 5;
64 module_param(shutdown_timeout
, byte
, 0644);
65 MODULE_PARM_DESC(shutdown_timeout
, "timeout in seconds for controller shutdown");
67 static int nvme_char_major
;
68 module_param(nvme_char_major
, int, 0);
70 static int use_threaded_interrupts
;
71 module_param(use_threaded_interrupts
, int, 0);
73 static bool use_cmb_sqes
= true;
74 module_param(use_cmb_sqes
, bool, 0644);
75 MODULE_PARM_DESC(use_cmb_sqes
, "use controller's memory buffer for I/O SQes");
77 static LIST_HEAD(dev_list
);
78 static struct task_struct
*nvme_thread
;
79 static struct workqueue_struct
*nvme_workq
;
80 static wait_queue_head_t nvme_kthread_wait
;
82 static struct class *nvme_class
;
88 static int __nvme_reset(struct nvme_dev
*dev
);
89 static int nvme_reset(struct nvme_dev
*dev
);
90 static void nvme_process_cq(struct nvme_queue
*nvmeq
);
91 static void nvme_unmap_data(struct nvme_dev
*dev
, struct nvme_iod
*iod
);
92 static void nvme_dead_ctrl(struct nvme_dev
*dev
);
94 struct async_cmd_info
{
95 struct kthread_work work
;
96 struct kthread_worker
*worker
;
104 * Represents an NVM Express device. Each nvme_dev is a PCI function.
107 struct list_head node
;
108 struct nvme_queue
**queues
;
109 struct blk_mq_tag_set tagset
;
110 struct blk_mq_tag_set admin_tagset
;
113 struct dma_pool
*prp_page_pool
;
114 struct dma_pool
*prp_small_pool
;
115 unsigned queue_count
;
116 unsigned online_queues
;
120 struct msix_entry
*entry
;
122 struct work_struct reset_work
;
123 struct work_struct probe_work
;
124 struct work_struct scan_work
;
127 dma_addr_t cmb_dma_addr
;
131 struct nvme_ctrl ctrl
;
134 static inline struct nvme_dev
*to_nvme_dev(struct nvme_ctrl
*ctrl
)
136 return container_of(ctrl
, struct nvme_dev
, ctrl
);
140 * An NVM Express queue. Each device has at least two (one for admin
141 * commands and one for I/O commands).
144 struct device
*q_dmadev
;
145 struct nvme_dev
*dev
;
146 char irqname
[24]; /* nvme4294967295-65535\0 */
148 struct nvme_command
*sq_cmds
;
149 struct nvme_command __iomem
*sq_cmds_io
;
150 volatile struct nvme_completion
*cqes
;
151 struct blk_mq_tags
**tags
;
152 dma_addr_t sq_dma_addr
;
153 dma_addr_t cq_dma_addr
;
163 struct async_cmd_info cmdinfo
;
167 * The nvme_iod describes the data in an I/O, including the list of PRP
168 * entries. You can't see it in this data structure because C doesn't let
169 * me express that. Use nvme_alloc_iod to ensure there's enough space
170 * allocated to store the PRP list.
173 unsigned long private; /* For the use of the submitter of the I/O */
174 int npages
; /* In the PRP list. 0 means small pool in use */
175 int offset
; /* Of PRP list */
176 int nents
; /* Used in scatterlist */
177 int length
; /* Of data, in bytes */
178 dma_addr_t first_dma
;
179 struct scatterlist meta_sg
[1]; /* metadata requires single contiguous buffer */
180 struct scatterlist sg
[0];
184 * Check we didin't inadvertently grow the command struct
186 static inline void _nvme_check_size(void)
188 BUILD_BUG_ON(sizeof(struct nvme_rw_command
) != 64);
189 BUILD_BUG_ON(sizeof(struct nvme_create_cq
) != 64);
190 BUILD_BUG_ON(sizeof(struct nvme_create_sq
) != 64);
191 BUILD_BUG_ON(sizeof(struct nvme_delete_queue
) != 64);
192 BUILD_BUG_ON(sizeof(struct nvme_features
) != 64);
193 BUILD_BUG_ON(sizeof(struct nvme_format_cmd
) != 64);
194 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd
) != 64);
195 BUILD_BUG_ON(sizeof(struct nvme_command
) != 64);
196 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl
) != 4096);
197 BUILD_BUG_ON(sizeof(struct nvme_id_ns
) != 4096);
198 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type
) != 64);
199 BUILD_BUG_ON(sizeof(struct nvme_smart_log
) != 512);
202 typedef void (*nvme_completion_fn
)(struct nvme_queue
*, void *,
203 struct nvme_completion
*);
205 struct nvme_cmd_info
{
206 nvme_completion_fn fn
;
209 struct nvme_queue
*nvmeq
;
210 struct nvme_iod iod
[0];
214 * Max size of iod being embedded in the request payload
216 #define NVME_INT_PAGES 2
217 #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size)
218 #define NVME_INT_MASK 0x01
221 * Will slightly overestimate the number of pages needed. This is OK
222 * as it only leads to a small amount of wasted memory for the lifetime of
225 static int nvme_npages(unsigned size
, struct nvme_dev
*dev
)
227 unsigned nprps
= DIV_ROUND_UP(size
+ dev
->ctrl
.page_size
,
228 dev
->ctrl
.page_size
);
229 return DIV_ROUND_UP(8 * nprps
, PAGE_SIZE
- 8);
232 static unsigned int nvme_cmd_size(struct nvme_dev
*dev
)
234 unsigned int ret
= sizeof(struct nvme_cmd_info
);
236 ret
+= sizeof(struct nvme_iod
);
237 ret
+= sizeof(__le64
*) * nvme_npages(NVME_INT_BYTES(dev
), dev
);
238 ret
+= sizeof(struct scatterlist
) * NVME_INT_PAGES
;
243 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx
*hctx
, void *data
,
244 unsigned int hctx_idx
)
246 struct nvme_dev
*dev
= data
;
247 struct nvme_queue
*nvmeq
= dev
->queues
[0];
249 WARN_ON(hctx_idx
!= 0);
250 WARN_ON(dev
->admin_tagset
.tags
[0] != hctx
->tags
);
251 WARN_ON(nvmeq
->tags
);
253 hctx
->driver_data
= nvmeq
;
254 nvmeq
->tags
= &dev
->admin_tagset
.tags
[0];
258 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx
*hctx
, unsigned int hctx_idx
)
260 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
265 static int nvme_admin_init_request(void *data
, struct request
*req
,
266 unsigned int hctx_idx
, unsigned int rq_idx
,
267 unsigned int numa_node
)
269 struct nvme_dev
*dev
= data
;
270 struct nvme_cmd_info
*cmd
= blk_mq_rq_to_pdu(req
);
271 struct nvme_queue
*nvmeq
= dev
->queues
[0];
278 static int nvme_init_hctx(struct blk_mq_hw_ctx
*hctx
, void *data
,
279 unsigned int hctx_idx
)
281 struct nvme_dev
*dev
= data
;
282 struct nvme_queue
*nvmeq
= dev
->queues
[hctx_idx
+ 1];
285 nvmeq
->tags
= &dev
->tagset
.tags
[hctx_idx
];
287 WARN_ON(dev
->tagset
.tags
[hctx_idx
] != hctx
->tags
);
288 hctx
->driver_data
= nvmeq
;
292 static int nvme_init_request(void *data
, struct request
*req
,
293 unsigned int hctx_idx
, unsigned int rq_idx
,
294 unsigned int numa_node
)
296 struct nvme_dev
*dev
= data
;
297 struct nvme_cmd_info
*cmd
= blk_mq_rq_to_pdu(req
);
298 struct nvme_queue
*nvmeq
= dev
->queues
[hctx_idx
+ 1];
305 static void nvme_set_info(struct nvme_cmd_info
*cmd
, void *ctx
,
306 nvme_completion_fn handler
)
311 blk_mq_start_request(blk_mq_rq_from_pdu(cmd
));
314 static void *iod_get_private(struct nvme_iod
*iod
)
316 return (void *) (iod
->private & ~0x1UL
);
320 * If bit 0 is set, the iod is embedded in the request payload.
322 static bool iod_should_kfree(struct nvme_iod
*iod
)
324 return (iod
->private & NVME_INT_MASK
) == 0;
327 /* Special values must be less than 0x1000 */
328 #define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA)
329 #define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE)
330 #define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE)
331 #define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE)
333 static void special_completion(struct nvme_queue
*nvmeq
, void *ctx
,
334 struct nvme_completion
*cqe
)
336 if (ctx
== CMD_CTX_CANCELLED
)
338 if (ctx
== CMD_CTX_COMPLETED
) {
339 dev_warn(nvmeq
->q_dmadev
,
340 "completed id %d twice on queue %d\n",
341 cqe
->command_id
, le16_to_cpup(&cqe
->sq_id
));
344 if (ctx
== CMD_CTX_INVALID
) {
345 dev_warn(nvmeq
->q_dmadev
,
346 "invalid id %d completed on queue %d\n",
347 cqe
->command_id
, le16_to_cpup(&cqe
->sq_id
));
350 dev_warn(nvmeq
->q_dmadev
, "Unknown special completion %p\n", ctx
);
353 static void *cancel_cmd_info(struct nvme_cmd_info
*cmd
, nvme_completion_fn
*fn
)
360 cmd
->fn
= special_completion
;
361 cmd
->ctx
= CMD_CTX_CANCELLED
;
365 static void async_req_completion(struct nvme_queue
*nvmeq
, void *ctx
,
366 struct nvme_completion
*cqe
)
368 u32 result
= le32_to_cpup(&cqe
->result
);
369 u16 status
= le16_to_cpup(&cqe
->status
) >> 1;
371 if (status
== NVME_SC_SUCCESS
|| status
== NVME_SC_ABORT_REQ
)
372 ++nvmeq
->dev
->ctrl
.event_limit
;
373 if (status
!= NVME_SC_SUCCESS
)
376 switch (result
& 0xff07) {
377 case NVME_AER_NOTICE_NS_CHANGED
:
378 dev_info(nvmeq
->q_dmadev
, "rescanning\n");
379 schedule_work(&nvmeq
->dev
->scan_work
);
381 dev_warn(nvmeq
->q_dmadev
, "async event result %08x\n", result
);
385 static void abort_completion(struct nvme_queue
*nvmeq
, void *ctx
,
386 struct nvme_completion
*cqe
)
388 struct request
*req
= ctx
;
390 u16 status
= le16_to_cpup(&cqe
->status
) >> 1;
391 u32 result
= le32_to_cpup(&cqe
->result
);
393 blk_mq_free_request(req
);
395 dev_warn(nvmeq
->q_dmadev
, "Abort status:%x result:%x", status
, result
);
396 ++nvmeq
->dev
->ctrl
.abort_limit
;
399 static void async_completion(struct nvme_queue
*nvmeq
, void *ctx
,
400 struct nvme_completion
*cqe
)
402 struct async_cmd_info
*cmdinfo
= ctx
;
403 cmdinfo
->result
= le32_to_cpup(&cqe
->result
);
404 cmdinfo
->status
= le16_to_cpup(&cqe
->status
) >> 1;
405 queue_kthread_work(cmdinfo
->worker
, &cmdinfo
->work
);
406 blk_mq_free_request(cmdinfo
->req
);
409 static inline struct nvme_cmd_info
*get_cmd_from_tag(struct nvme_queue
*nvmeq
,
412 struct request
*req
= blk_mq_tag_to_rq(*nvmeq
->tags
, tag
);
414 return blk_mq_rq_to_pdu(req
);
418 * Called with local interrupts disabled and the q_lock held. May not sleep.
420 static void *nvme_finish_cmd(struct nvme_queue
*nvmeq
, int tag
,
421 nvme_completion_fn
*fn
)
423 struct nvme_cmd_info
*cmd
= get_cmd_from_tag(nvmeq
, tag
);
425 if (tag
>= nvmeq
->q_depth
) {
426 *fn
= special_completion
;
427 return CMD_CTX_INVALID
;
432 cmd
->fn
= special_completion
;
433 cmd
->ctx
= CMD_CTX_COMPLETED
;
438 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
439 * @nvmeq: The queue to use
440 * @cmd: The command to send
442 * Safe to use from interrupt context
444 static void __nvme_submit_cmd(struct nvme_queue
*nvmeq
,
445 struct nvme_command
*cmd
)
447 u16 tail
= nvmeq
->sq_tail
;
449 if (nvmeq
->sq_cmds_io
)
450 memcpy_toio(&nvmeq
->sq_cmds_io
[tail
], cmd
, sizeof(*cmd
));
452 memcpy(&nvmeq
->sq_cmds
[tail
], cmd
, sizeof(*cmd
));
454 if (++tail
== nvmeq
->q_depth
)
456 writel(tail
, nvmeq
->q_db
);
457 nvmeq
->sq_tail
= tail
;
460 static void nvme_submit_cmd(struct nvme_queue
*nvmeq
, struct nvme_command
*cmd
)
463 spin_lock_irqsave(&nvmeq
->q_lock
, flags
);
464 __nvme_submit_cmd(nvmeq
, cmd
);
465 spin_unlock_irqrestore(&nvmeq
->q_lock
, flags
);
468 static __le64
**iod_list(struct nvme_iod
*iod
)
470 return ((void *)iod
) + iod
->offset
;
473 static inline void iod_init(struct nvme_iod
*iod
, unsigned nbytes
,
474 unsigned nseg
, unsigned long private)
476 iod
->private = private;
477 iod
->offset
= offsetof(struct nvme_iod
, sg
[nseg
]);
479 iod
->length
= nbytes
;
483 static struct nvme_iod
*
484 __nvme_alloc_iod(unsigned nseg
, unsigned bytes
, struct nvme_dev
*dev
,
485 unsigned long priv
, gfp_t gfp
)
487 struct nvme_iod
*iod
= kmalloc(sizeof(struct nvme_iod
) +
488 sizeof(__le64
*) * nvme_npages(bytes
, dev
) +
489 sizeof(struct scatterlist
) * nseg
, gfp
);
492 iod_init(iod
, bytes
, nseg
, priv
);
497 static struct nvme_iod
*nvme_alloc_iod(struct request
*rq
, struct nvme_dev
*dev
,
500 unsigned size
= !(rq
->cmd_flags
& REQ_DISCARD
) ? blk_rq_bytes(rq
) :
501 sizeof(struct nvme_dsm_range
);
502 struct nvme_iod
*iod
;
504 if (rq
->nr_phys_segments
<= NVME_INT_PAGES
&&
505 size
<= NVME_INT_BYTES(dev
)) {
506 struct nvme_cmd_info
*cmd
= blk_mq_rq_to_pdu(rq
);
509 iod_init(iod
, size
, rq
->nr_phys_segments
,
510 (unsigned long) rq
| NVME_INT_MASK
);
514 return __nvme_alloc_iod(rq
->nr_phys_segments
, size
, dev
,
515 (unsigned long) rq
, gfp
);
518 static void nvme_free_iod(struct nvme_dev
*dev
, struct nvme_iod
*iod
)
520 const int last_prp
= dev
->ctrl
.page_size
/ 8 - 1;
522 __le64
**list
= iod_list(iod
);
523 dma_addr_t prp_dma
= iod
->first_dma
;
525 if (iod
->npages
== 0)
526 dma_pool_free(dev
->prp_small_pool
, list
[0], prp_dma
);
527 for (i
= 0; i
< iod
->npages
; i
++) {
528 __le64
*prp_list
= list
[i
];
529 dma_addr_t next_prp_dma
= le64_to_cpu(prp_list
[last_prp
]);
530 dma_pool_free(dev
->prp_page_pool
, prp_list
, prp_dma
);
531 prp_dma
= next_prp_dma
;
534 if (iod_should_kfree(iod
))
538 #ifdef CONFIG_BLK_DEV_INTEGRITY
539 static void nvme_dif_prep(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
541 if (be32_to_cpu(pi
->ref_tag
) == v
)
542 pi
->ref_tag
= cpu_to_be32(p
);
545 static void nvme_dif_complete(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
547 if (be32_to_cpu(pi
->ref_tag
) == p
)
548 pi
->ref_tag
= cpu_to_be32(v
);
552 * nvme_dif_remap - remaps ref tags to bip seed and physical lba
554 * The virtual start sector is the one that was originally submitted by the
555 * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
556 * start sector may be different. Remap protection information to match the
557 * physical LBA on writes, and back to the original seed on reads.
559 * Type 0 and 3 do not have a ref tag, so no remapping required.
561 static void nvme_dif_remap(struct request
*req
,
562 void (*dif_swap
)(u32 p
, u32 v
, struct t10_pi_tuple
*pi
))
564 struct nvme_ns
*ns
= req
->rq_disk
->private_data
;
565 struct bio_integrity_payload
*bip
;
566 struct t10_pi_tuple
*pi
;
568 u32 i
, nlb
, ts
, phys
, virt
;
570 if (!ns
->pi_type
|| ns
->pi_type
== NVME_NS_DPS_PI_TYPE3
)
573 bip
= bio_integrity(req
->bio
);
577 pmap
= kmap_atomic(bip
->bip_vec
->bv_page
) + bip
->bip_vec
->bv_offset
;
580 virt
= bip_get_seed(bip
);
581 phys
= nvme_block_nr(ns
, blk_rq_pos(req
));
582 nlb
= (blk_rq_bytes(req
) >> ns
->lba_shift
);
583 ts
= ns
->disk
->queue
->integrity
.tuple_size
;
585 for (i
= 0; i
< nlb
; i
++, virt
++, phys
++) {
586 pi
= (struct t10_pi_tuple
*)p
;
587 dif_swap(phys
, virt
, pi
);
592 #else /* CONFIG_BLK_DEV_INTEGRITY */
593 static void nvme_dif_remap(struct request
*req
,
594 void (*dif_swap
)(u32 p
, u32 v
, struct t10_pi_tuple
*pi
))
597 static void nvme_dif_prep(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
600 static void nvme_dif_complete(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
605 static void req_completion(struct nvme_queue
*nvmeq
, void *ctx
,
606 struct nvme_completion
*cqe
)
608 struct nvme_iod
*iod
= ctx
;
609 struct request
*req
= iod_get_private(iod
);
610 struct nvme_cmd_info
*cmd_rq
= blk_mq_rq_to_pdu(req
);
611 u16 status
= le16_to_cpup(&cqe
->status
) >> 1;
614 if (unlikely(status
)) {
615 if (!(status
& NVME_SC_DNR
|| blk_noretry_request(req
))
616 && (jiffies
- req
->start_time
) < req
->timeout
) {
619 nvme_unmap_data(nvmeq
->dev
, iod
);
621 blk_mq_requeue_request(req
);
622 spin_lock_irqsave(req
->q
->queue_lock
, flags
);
623 if (!blk_queue_stopped(req
->q
))
624 blk_mq_kick_requeue_list(req
->q
);
625 spin_unlock_irqrestore(req
->q
->queue_lock
, flags
);
629 if (req
->cmd_type
== REQ_TYPE_DRV_PRIV
) {
630 if (cmd_rq
->ctx
== CMD_CTX_CANCELLED
)
635 error
= nvme_error_status(status
);
639 if (req
->cmd_type
== REQ_TYPE_DRV_PRIV
) {
640 u32 result
= le32_to_cpup(&cqe
->result
);
641 req
->special
= (void *)(uintptr_t)result
;
645 dev_warn(nvmeq
->dev
->dev
,
646 "completing aborted command with status:%04x\n",
649 nvme_unmap_data(nvmeq
->dev
, iod
);
650 blk_mq_complete_request(req
, error
);
653 static bool nvme_setup_prps(struct nvme_dev
*dev
, struct nvme_iod
*iod
,
656 struct dma_pool
*pool
;
657 int length
= total_len
;
658 struct scatterlist
*sg
= iod
->sg
;
659 int dma_len
= sg_dma_len(sg
);
660 u64 dma_addr
= sg_dma_address(sg
);
661 u32 page_size
= dev
->ctrl
.page_size
;
662 int offset
= dma_addr
& (page_size
- 1);
664 __le64
**list
= iod_list(iod
);
668 length
-= (page_size
- offset
);
672 dma_len
-= (page_size
- offset
);
674 dma_addr
+= (page_size
- offset
);
677 dma_addr
= sg_dma_address(sg
);
678 dma_len
= sg_dma_len(sg
);
681 if (length
<= page_size
) {
682 iod
->first_dma
= dma_addr
;
686 nprps
= DIV_ROUND_UP(length
, page_size
);
687 if (nprps
<= (256 / 8)) {
688 pool
= dev
->prp_small_pool
;
691 pool
= dev
->prp_page_pool
;
695 prp_list
= dma_pool_alloc(pool
, GFP_ATOMIC
, &prp_dma
);
697 iod
->first_dma
= dma_addr
;
702 iod
->first_dma
= prp_dma
;
705 if (i
== page_size
>> 3) {
706 __le64
*old_prp_list
= prp_list
;
707 prp_list
= dma_pool_alloc(pool
, GFP_ATOMIC
, &prp_dma
);
710 list
[iod
->npages
++] = prp_list
;
711 prp_list
[0] = old_prp_list
[i
- 1];
712 old_prp_list
[i
- 1] = cpu_to_le64(prp_dma
);
715 prp_list
[i
++] = cpu_to_le64(dma_addr
);
716 dma_len
-= page_size
;
717 dma_addr
+= page_size
;
725 dma_addr
= sg_dma_address(sg
);
726 dma_len
= sg_dma_len(sg
);
732 static int nvme_map_data(struct nvme_dev
*dev
, struct nvme_iod
*iod
,
733 struct nvme_command
*cmnd
)
735 struct request
*req
= iod_get_private(iod
);
736 struct request_queue
*q
= req
->q
;
737 enum dma_data_direction dma_dir
= rq_data_dir(req
) ?
738 DMA_TO_DEVICE
: DMA_FROM_DEVICE
;
739 int ret
= BLK_MQ_RQ_QUEUE_ERROR
;
741 sg_init_table(iod
->sg
, req
->nr_phys_segments
);
742 iod
->nents
= blk_rq_map_sg(q
, req
, iod
->sg
);
746 ret
= BLK_MQ_RQ_QUEUE_BUSY
;
747 if (!dma_map_sg(dev
->dev
, iod
->sg
, iod
->nents
, dma_dir
))
750 if (!nvme_setup_prps(dev
, iod
, blk_rq_bytes(req
)))
753 ret
= BLK_MQ_RQ_QUEUE_ERROR
;
754 if (blk_integrity_rq(req
)) {
755 if (blk_rq_count_integrity_sg(q
, req
->bio
) != 1)
758 sg_init_table(iod
->meta_sg
, 1);
759 if (blk_rq_map_integrity_sg(q
, req
->bio
, iod
->meta_sg
) != 1)
762 if (rq_data_dir(req
))
763 nvme_dif_remap(req
, nvme_dif_prep
);
765 if (!dma_map_sg(dev
->dev
, iod
->meta_sg
, 1, dma_dir
))
769 cmnd
->rw
.prp1
= cpu_to_le64(sg_dma_address(iod
->sg
));
770 cmnd
->rw
.prp2
= cpu_to_le64(iod
->first_dma
);
771 if (blk_integrity_rq(req
))
772 cmnd
->rw
.metadata
= cpu_to_le64(sg_dma_address(iod
->meta_sg
));
773 return BLK_MQ_RQ_QUEUE_OK
;
776 dma_unmap_sg(dev
->dev
, iod
->sg
, iod
->nents
, dma_dir
);
781 static void nvme_unmap_data(struct nvme_dev
*dev
, struct nvme_iod
*iod
)
783 struct request
*req
= iod_get_private(iod
);
784 enum dma_data_direction dma_dir
= rq_data_dir(req
) ?
785 DMA_TO_DEVICE
: DMA_FROM_DEVICE
;
788 dma_unmap_sg(dev
->dev
, iod
->sg
, iod
->nents
, dma_dir
);
789 if (blk_integrity_rq(req
)) {
790 if (!rq_data_dir(req
))
791 nvme_dif_remap(req
, nvme_dif_complete
);
792 dma_unmap_sg(dev
->dev
, iod
->meta_sg
, 1, dma_dir
);
796 nvme_free_iod(dev
, iod
);
800 * We reuse the small pool to allocate the 16-byte range here as it is not
801 * worth having a special pool for these or additional cases to handle freeing
804 static int nvme_setup_discard(struct nvme_queue
*nvmeq
, struct nvme_ns
*ns
,
805 struct nvme_iod
*iod
, struct nvme_command
*cmnd
)
807 struct request
*req
= iod_get_private(iod
);
808 struct nvme_dsm_range
*range
;
810 range
= dma_pool_alloc(nvmeq
->dev
->prp_small_pool
, GFP_ATOMIC
,
813 return BLK_MQ_RQ_QUEUE_BUSY
;
814 iod_list(iod
)[0] = (__le64
*)range
;
817 range
->cattr
= cpu_to_le32(0);
818 range
->nlb
= cpu_to_le32(blk_rq_bytes(req
) >> ns
->lba_shift
);
819 range
->slba
= cpu_to_le64(nvme_block_nr(ns
, blk_rq_pos(req
)));
821 memset(cmnd
, 0, sizeof(*cmnd
));
822 cmnd
->dsm
.opcode
= nvme_cmd_dsm
;
823 cmnd
->dsm
.nsid
= cpu_to_le32(ns
->ns_id
);
824 cmnd
->dsm
.prp1
= cpu_to_le64(iod
->first_dma
);
826 cmnd
->dsm
.attributes
= cpu_to_le32(NVME_DSMGMT_AD
);
827 return BLK_MQ_RQ_QUEUE_OK
;
831 * NOTE: ns is NULL when called on the admin queue.
833 static int nvme_queue_rq(struct blk_mq_hw_ctx
*hctx
,
834 const struct blk_mq_queue_data
*bd
)
836 struct nvme_ns
*ns
= hctx
->queue
->queuedata
;
837 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
838 struct nvme_dev
*dev
= nvmeq
->dev
;
839 struct request
*req
= bd
->rq
;
840 struct nvme_cmd_info
*cmd
= blk_mq_rq_to_pdu(req
);
841 struct nvme_iod
*iod
;
842 struct nvme_command cmnd
;
843 int ret
= BLK_MQ_RQ_QUEUE_OK
;
846 * If formated with metadata, require the block layer provide a buffer
847 * unless this namespace is formated such that the metadata can be
848 * stripped/generated by the controller with PRACT=1.
850 if (ns
&& ns
->ms
&& !blk_integrity_rq(req
)) {
851 if (!(ns
->pi_type
&& ns
->ms
== 8) &&
852 req
->cmd_type
!= REQ_TYPE_DRV_PRIV
) {
853 blk_mq_complete_request(req
, -EFAULT
);
854 return BLK_MQ_RQ_QUEUE_OK
;
858 iod
= nvme_alloc_iod(req
, dev
, GFP_ATOMIC
);
860 return BLK_MQ_RQ_QUEUE_BUSY
;
862 if (req
->cmd_flags
& REQ_DISCARD
) {
863 ret
= nvme_setup_discard(nvmeq
, ns
, iod
, &cmnd
);
865 if (req
->cmd_type
== REQ_TYPE_DRV_PRIV
)
866 memcpy(&cmnd
, req
->cmd
, sizeof(cmnd
));
867 else if (req
->cmd_flags
& REQ_FLUSH
)
868 nvme_setup_flush(ns
, &cmnd
);
870 nvme_setup_rw(ns
, req
, &cmnd
);
872 if (req
->nr_phys_segments
)
873 ret
= nvme_map_data(dev
, iod
, &cmnd
);
879 cmnd
.common
.command_id
= req
->tag
;
880 nvme_set_info(cmd
, iod
, req_completion
);
882 spin_lock_irq(&nvmeq
->q_lock
);
883 __nvme_submit_cmd(nvmeq
, &cmnd
);
884 nvme_process_cq(nvmeq
);
885 spin_unlock_irq(&nvmeq
->q_lock
);
886 return BLK_MQ_RQ_QUEUE_OK
;
888 nvme_free_iod(dev
, iod
);
892 static void __nvme_process_cq(struct nvme_queue
*nvmeq
, unsigned int *tag
)
896 head
= nvmeq
->cq_head
;
897 phase
= nvmeq
->cq_phase
;
901 nvme_completion_fn fn
;
902 struct nvme_completion cqe
= nvmeq
->cqes
[head
];
903 if ((le16_to_cpu(cqe
.status
) & 1) != phase
)
905 nvmeq
->sq_head
= le16_to_cpu(cqe
.sq_head
);
906 if (++head
== nvmeq
->q_depth
) {
910 if (tag
&& *tag
== cqe
.command_id
)
912 ctx
= nvme_finish_cmd(nvmeq
, cqe
.command_id
, &fn
);
913 fn(nvmeq
, ctx
, &cqe
);
916 /* If the controller ignores the cq head doorbell and continuously
917 * writes to the queue, it is theoretically possible to wrap around
918 * the queue twice and mistakenly return IRQ_NONE. Linux only
919 * requires that 0.1% of your interrupts are handled, so this isn't
922 if (head
== nvmeq
->cq_head
&& phase
== nvmeq
->cq_phase
)
925 if (likely(nvmeq
->cq_vector
>= 0))
926 writel(head
, nvmeq
->q_db
+ nvmeq
->dev
->db_stride
);
927 nvmeq
->cq_head
= head
;
928 nvmeq
->cq_phase
= phase
;
933 static void nvme_process_cq(struct nvme_queue
*nvmeq
)
935 __nvme_process_cq(nvmeq
, NULL
);
938 static irqreturn_t
nvme_irq(int irq
, void *data
)
941 struct nvme_queue
*nvmeq
= data
;
942 spin_lock(&nvmeq
->q_lock
);
943 nvme_process_cq(nvmeq
);
944 result
= nvmeq
->cqe_seen
? IRQ_HANDLED
: IRQ_NONE
;
946 spin_unlock(&nvmeq
->q_lock
);
950 static irqreturn_t
nvme_irq_check(int irq
, void *data
)
952 struct nvme_queue
*nvmeq
= data
;
953 struct nvme_completion cqe
= nvmeq
->cqes
[nvmeq
->cq_head
];
954 if ((le16_to_cpu(cqe
.status
) & 1) != nvmeq
->cq_phase
)
956 return IRQ_WAKE_THREAD
;
959 static int nvme_poll(struct blk_mq_hw_ctx
*hctx
, unsigned int tag
)
961 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
963 if ((le16_to_cpu(nvmeq
->cqes
[nvmeq
->cq_head
].status
) & 1) ==
965 spin_lock_irq(&nvmeq
->q_lock
);
966 __nvme_process_cq(nvmeq
, &tag
);
967 spin_unlock_irq(&nvmeq
->q_lock
);
976 static int nvme_submit_async_admin_req(struct nvme_dev
*dev
)
978 struct nvme_queue
*nvmeq
= dev
->queues
[0];
979 struct nvme_command c
;
980 struct nvme_cmd_info
*cmd_info
;
983 req
= blk_mq_alloc_request(dev
->ctrl
.admin_q
, WRITE
,
984 BLK_MQ_REQ_NOWAIT
| BLK_MQ_REQ_RESERVED
);
988 req
->cmd_flags
|= REQ_NO_TIMEOUT
;
989 cmd_info
= blk_mq_rq_to_pdu(req
);
990 nvme_set_info(cmd_info
, NULL
, async_req_completion
);
992 memset(&c
, 0, sizeof(c
));
993 c
.common
.opcode
= nvme_admin_async_event
;
994 c
.common
.command_id
= req
->tag
;
996 blk_mq_free_request(req
);
997 __nvme_submit_cmd(nvmeq
, &c
);
1001 static int nvme_submit_admin_async_cmd(struct nvme_dev
*dev
,
1002 struct nvme_command
*cmd
,
1003 struct async_cmd_info
*cmdinfo
, unsigned timeout
)
1005 struct nvme_queue
*nvmeq
= dev
->queues
[0];
1006 struct request
*req
;
1007 struct nvme_cmd_info
*cmd_rq
;
1009 req
= blk_mq_alloc_request(dev
->ctrl
.admin_q
, WRITE
, 0);
1011 return PTR_ERR(req
);
1013 req
->timeout
= timeout
;
1014 cmd_rq
= blk_mq_rq_to_pdu(req
);
1016 nvme_set_info(cmd_rq
, cmdinfo
, async_completion
);
1017 cmdinfo
->status
= -EINTR
;
1019 cmd
->common
.command_id
= req
->tag
;
1021 nvme_submit_cmd(nvmeq
, cmd
);
1025 static int adapter_delete_queue(struct nvme_dev
*dev
, u8 opcode
, u16 id
)
1027 struct nvme_command c
;
1029 memset(&c
, 0, sizeof(c
));
1030 c
.delete_queue
.opcode
= opcode
;
1031 c
.delete_queue
.qid
= cpu_to_le16(id
);
1033 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
1036 static int adapter_alloc_cq(struct nvme_dev
*dev
, u16 qid
,
1037 struct nvme_queue
*nvmeq
)
1039 struct nvme_command c
;
1040 int flags
= NVME_QUEUE_PHYS_CONTIG
| NVME_CQ_IRQ_ENABLED
;
1043 * Note: we (ab)use the fact the the prp fields survive if no data
1044 * is attached to the request.
1046 memset(&c
, 0, sizeof(c
));
1047 c
.create_cq
.opcode
= nvme_admin_create_cq
;
1048 c
.create_cq
.prp1
= cpu_to_le64(nvmeq
->cq_dma_addr
);
1049 c
.create_cq
.cqid
= cpu_to_le16(qid
);
1050 c
.create_cq
.qsize
= cpu_to_le16(nvmeq
->q_depth
- 1);
1051 c
.create_cq
.cq_flags
= cpu_to_le16(flags
);
1052 c
.create_cq
.irq_vector
= cpu_to_le16(nvmeq
->cq_vector
);
1054 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
1057 static int adapter_alloc_sq(struct nvme_dev
*dev
, u16 qid
,
1058 struct nvme_queue
*nvmeq
)
1060 struct nvme_command c
;
1061 int flags
= NVME_QUEUE_PHYS_CONTIG
| NVME_SQ_PRIO_MEDIUM
;
1064 * Note: we (ab)use the fact the the prp fields survive if no data
1065 * is attached to the request.
1067 memset(&c
, 0, sizeof(c
));
1068 c
.create_sq
.opcode
= nvme_admin_create_sq
;
1069 c
.create_sq
.prp1
= cpu_to_le64(nvmeq
->sq_dma_addr
);
1070 c
.create_sq
.sqid
= cpu_to_le16(qid
);
1071 c
.create_sq
.qsize
= cpu_to_le16(nvmeq
->q_depth
- 1);
1072 c
.create_sq
.sq_flags
= cpu_to_le16(flags
);
1073 c
.create_sq
.cqid
= cpu_to_le16(qid
);
1075 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
1078 static int adapter_delete_cq(struct nvme_dev
*dev
, u16 cqid
)
1080 return adapter_delete_queue(dev
, nvme_admin_delete_cq
, cqid
);
1083 static int adapter_delete_sq(struct nvme_dev
*dev
, u16 sqid
)
1085 return adapter_delete_queue(dev
, nvme_admin_delete_sq
, sqid
);
1089 * nvme_abort_req - Attempt aborting a request
1091 * Schedule controller reset if the command was already aborted once before and
1092 * still hasn't been returned to the driver, or if this is the admin queue.
1094 static void nvme_abort_req(struct request
*req
)
1096 struct nvme_cmd_info
*cmd_rq
= blk_mq_rq_to_pdu(req
);
1097 struct nvme_queue
*nvmeq
= cmd_rq
->nvmeq
;
1098 struct nvme_dev
*dev
= nvmeq
->dev
;
1099 struct request
*abort_req
;
1100 struct nvme_cmd_info
*abort_cmd
;
1101 struct nvme_command cmd
;
1103 if (!nvmeq
->qid
|| cmd_rq
->aborted
) {
1104 spin_lock(&dev_list_lock
);
1105 if (!__nvme_reset(dev
)) {
1107 "I/O %d QID %d timeout, reset controller\n",
1108 req
->tag
, nvmeq
->qid
);
1110 spin_unlock(&dev_list_lock
);
1114 if (!dev
->ctrl
.abort_limit
)
1117 abort_req
= blk_mq_alloc_request(dev
->ctrl
.admin_q
, WRITE
,
1119 if (IS_ERR(abort_req
))
1122 abort_cmd
= blk_mq_rq_to_pdu(abort_req
);
1123 nvme_set_info(abort_cmd
, abort_req
, abort_completion
);
1125 memset(&cmd
, 0, sizeof(cmd
));
1126 cmd
.abort
.opcode
= nvme_admin_abort_cmd
;
1127 cmd
.abort
.cid
= req
->tag
;
1128 cmd
.abort
.sqid
= cpu_to_le16(nvmeq
->qid
);
1129 cmd
.abort
.command_id
= abort_req
->tag
;
1131 --dev
->ctrl
.abort_limit
;
1132 cmd_rq
->aborted
= 1;
1134 dev_warn(nvmeq
->q_dmadev
, "Aborting I/O %d QID %d\n", req
->tag
,
1136 nvme_submit_cmd(dev
->queues
[0], &cmd
);
1139 static void nvme_cancel_queue_ios(struct request
*req
, void *data
, bool reserved
)
1141 struct nvme_queue
*nvmeq
= data
;
1143 nvme_completion_fn fn
;
1144 struct nvme_cmd_info
*cmd
;
1145 struct nvme_completion cqe
;
1147 if (!blk_mq_request_started(req
))
1150 cmd
= blk_mq_rq_to_pdu(req
);
1152 if (cmd
->ctx
== CMD_CTX_CANCELLED
)
1155 if (blk_queue_dying(req
->q
))
1156 cqe
.status
= cpu_to_le16((NVME_SC_ABORT_REQ
| NVME_SC_DNR
) << 1);
1158 cqe
.status
= cpu_to_le16(NVME_SC_ABORT_REQ
<< 1);
1161 dev_warn(nvmeq
->q_dmadev
, "Cancelling I/O %d QID %d\n",
1162 req
->tag
, nvmeq
->qid
);
1163 ctx
= cancel_cmd_info(cmd
, &fn
);
1164 fn(nvmeq
, ctx
, &cqe
);
1167 static enum blk_eh_timer_return
nvme_timeout(struct request
*req
, bool reserved
)
1169 struct nvme_cmd_info
*cmd
= blk_mq_rq_to_pdu(req
);
1170 struct nvme_queue
*nvmeq
= cmd
->nvmeq
;
1172 dev_warn(nvmeq
->q_dmadev
, "Timeout I/O %d QID %d\n", req
->tag
,
1174 spin_lock_irq(&nvmeq
->q_lock
);
1175 nvme_abort_req(req
);
1176 spin_unlock_irq(&nvmeq
->q_lock
);
1179 * The aborted req will be completed on receiving the abort req.
1180 * We enable the timer again. If hit twice, it'll cause a device reset,
1181 * as the device then is in a faulty state.
1183 return BLK_EH_RESET_TIMER
;
1186 static void nvme_free_queue(struct nvme_queue
*nvmeq
)
1188 dma_free_coherent(nvmeq
->q_dmadev
, CQ_SIZE(nvmeq
->q_depth
),
1189 (void *)nvmeq
->cqes
, nvmeq
->cq_dma_addr
);
1191 dma_free_coherent(nvmeq
->q_dmadev
, SQ_SIZE(nvmeq
->q_depth
),
1192 nvmeq
->sq_cmds
, nvmeq
->sq_dma_addr
);
1196 static void nvme_free_queues(struct nvme_dev
*dev
, int lowest
)
1200 for (i
= dev
->queue_count
- 1; i
>= lowest
; i
--) {
1201 struct nvme_queue
*nvmeq
= dev
->queues
[i
];
1203 dev
->queues
[i
] = NULL
;
1204 nvme_free_queue(nvmeq
);
1209 * nvme_suspend_queue - put queue into suspended state
1210 * @nvmeq - queue to suspend
1212 static int nvme_suspend_queue(struct nvme_queue
*nvmeq
)
1216 spin_lock_irq(&nvmeq
->q_lock
);
1217 if (nvmeq
->cq_vector
== -1) {
1218 spin_unlock_irq(&nvmeq
->q_lock
);
1221 vector
= nvmeq
->dev
->entry
[nvmeq
->cq_vector
].vector
;
1222 nvmeq
->dev
->online_queues
--;
1223 nvmeq
->cq_vector
= -1;
1224 spin_unlock_irq(&nvmeq
->q_lock
);
1226 if (!nvmeq
->qid
&& nvmeq
->dev
->ctrl
.admin_q
)
1227 blk_mq_freeze_queue_start(nvmeq
->dev
->ctrl
.admin_q
);
1229 irq_set_affinity_hint(vector
, NULL
);
1230 free_irq(vector
, nvmeq
);
1235 static void nvme_clear_queue(struct nvme_queue
*nvmeq
)
1237 spin_lock_irq(&nvmeq
->q_lock
);
1238 if (nvmeq
->tags
&& *nvmeq
->tags
)
1239 blk_mq_all_tag_busy_iter(*nvmeq
->tags
, nvme_cancel_queue_ios
, nvmeq
);
1240 spin_unlock_irq(&nvmeq
->q_lock
);
1243 static void nvme_disable_queue(struct nvme_dev
*dev
, int qid
)
1245 struct nvme_queue
*nvmeq
= dev
->queues
[qid
];
1249 if (nvme_suspend_queue(nvmeq
))
1252 /* Don't tell the adapter to delete the admin queue.
1253 * Don't tell a removed adapter to delete IO queues. */
1254 if (qid
&& readl(dev
->bar
+ NVME_REG_CSTS
) != -1) {
1255 adapter_delete_sq(dev
, qid
);
1256 adapter_delete_cq(dev
, qid
);
1259 spin_lock_irq(&nvmeq
->q_lock
);
1260 nvme_process_cq(nvmeq
);
1261 spin_unlock_irq(&nvmeq
->q_lock
);
1264 static int nvme_cmb_qdepth(struct nvme_dev
*dev
, int nr_io_queues
,
1267 int q_depth
= dev
->q_depth
;
1268 unsigned q_size_aligned
= roundup(q_depth
* entry_size
,
1269 dev
->ctrl
.page_size
);
1271 if (q_size_aligned
* nr_io_queues
> dev
->cmb_size
) {
1272 u64 mem_per_q
= div_u64(dev
->cmb_size
, nr_io_queues
);
1273 mem_per_q
= round_down(mem_per_q
, dev
->ctrl
.page_size
);
1274 q_depth
= div_u64(mem_per_q
, entry_size
);
1277 * Ensure the reduced q_depth is above some threshold where it
1278 * would be better to map queues in system memory with the
1288 static int nvme_alloc_sq_cmds(struct nvme_dev
*dev
, struct nvme_queue
*nvmeq
,
1291 if (qid
&& dev
->cmb
&& use_cmb_sqes
&& NVME_CMB_SQS(dev
->cmbsz
)) {
1292 unsigned offset
= (qid
- 1) * roundup(SQ_SIZE(depth
),
1293 dev
->ctrl
.page_size
);
1294 nvmeq
->sq_dma_addr
= dev
->cmb_dma_addr
+ offset
;
1295 nvmeq
->sq_cmds_io
= dev
->cmb
+ offset
;
1297 nvmeq
->sq_cmds
= dma_alloc_coherent(dev
->dev
, SQ_SIZE(depth
),
1298 &nvmeq
->sq_dma_addr
, GFP_KERNEL
);
1299 if (!nvmeq
->sq_cmds
)
1306 static struct nvme_queue
*nvme_alloc_queue(struct nvme_dev
*dev
, int qid
,
1309 struct nvme_queue
*nvmeq
= kzalloc(sizeof(*nvmeq
), GFP_KERNEL
);
1313 nvmeq
->cqes
= dma_zalloc_coherent(dev
->dev
, CQ_SIZE(depth
),
1314 &nvmeq
->cq_dma_addr
, GFP_KERNEL
);
1318 if (nvme_alloc_sq_cmds(dev
, nvmeq
, qid
, depth
))
1321 nvmeq
->q_dmadev
= dev
->dev
;
1323 snprintf(nvmeq
->irqname
, sizeof(nvmeq
->irqname
), "nvme%dq%d",
1324 dev
->ctrl
.instance
, qid
);
1325 spin_lock_init(&nvmeq
->q_lock
);
1327 nvmeq
->cq_phase
= 1;
1328 nvmeq
->q_db
= &dev
->dbs
[qid
* 2 * dev
->db_stride
];
1329 nvmeq
->q_depth
= depth
;
1331 nvmeq
->cq_vector
= -1;
1332 dev
->queues
[qid
] = nvmeq
;
1334 /* make sure queue descriptor is set before queue count, for kthread */
1341 dma_free_coherent(dev
->dev
, CQ_SIZE(depth
), (void *)nvmeq
->cqes
,
1342 nvmeq
->cq_dma_addr
);
1348 static int queue_request_irq(struct nvme_dev
*dev
, struct nvme_queue
*nvmeq
,
1351 if (use_threaded_interrupts
)
1352 return request_threaded_irq(dev
->entry
[nvmeq
->cq_vector
].vector
,
1353 nvme_irq_check
, nvme_irq
, IRQF_SHARED
,
1355 return request_irq(dev
->entry
[nvmeq
->cq_vector
].vector
, nvme_irq
,
1356 IRQF_SHARED
, name
, nvmeq
);
1359 static void nvme_init_queue(struct nvme_queue
*nvmeq
, u16 qid
)
1361 struct nvme_dev
*dev
= nvmeq
->dev
;
1363 spin_lock_irq(&nvmeq
->q_lock
);
1366 nvmeq
->cq_phase
= 1;
1367 nvmeq
->q_db
= &dev
->dbs
[qid
* 2 * dev
->db_stride
];
1368 memset((void *)nvmeq
->cqes
, 0, CQ_SIZE(nvmeq
->q_depth
));
1369 dev
->online_queues
++;
1370 spin_unlock_irq(&nvmeq
->q_lock
);
1373 static int nvme_create_queue(struct nvme_queue
*nvmeq
, int qid
)
1375 struct nvme_dev
*dev
= nvmeq
->dev
;
1378 nvmeq
->cq_vector
= qid
- 1;
1379 result
= adapter_alloc_cq(dev
, qid
, nvmeq
);
1383 result
= adapter_alloc_sq(dev
, qid
, nvmeq
);
1387 result
= queue_request_irq(dev
, nvmeq
, nvmeq
->irqname
);
1391 nvme_init_queue(nvmeq
, qid
);
1395 adapter_delete_sq(dev
, qid
);
1397 adapter_delete_cq(dev
, qid
);
1401 static struct blk_mq_ops nvme_mq_admin_ops
= {
1402 .queue_rq
= nvme_queue_rq
,
1403 .map_queue
= blk_mq_map_queue
,
1404 .init_hctx
= nvme_admin_init_hctx
,
1405 .exit_hctx
= nvme_admin_exit_hctx
,
1406 .init_request
= nvme_admin_init_request
,
1407 .timeout
= nvme_timeout
,
1410 static struct blk_mq_ops nvme_mq_ops
= {
1411 .queue_rq
= nvme_queue_rq
,
1412 .map_queue
= blk_mq_map_queue
,
1413 .init_hctx
= nvme_init_hctx
,
1414 .init_request
= nvme_init_request
,
1415 .timeout
= nvme_timeout
,
1419 static void nvme_dev_remove_admin(struct nvme_dev
*dev
)
1421 if (dev
->ctrl
.admin_q
&& !blk_queue_dying(dev
->ctrl
.admin_q
)) {
1422 blk_cleanup_queue(dev
->ctrl
.admin_q
);
1423 blk_mq_free_tag_set(&dev
->admin_tagset
);
1427 static int nvme_alloc_admin_tags(struct nvme_dev
*dev
)
1429 if (!dev
->ctrl
.admin_q
) {
1430 dev
->admin_tagset
.ops
= &nvme_mq_admin_ops
;
1431 dev
->admin_tagset
.nr_hw_queues
= 1;
1432 dev
->admin_tagset
.queue_depth
= NVME_AQ_DEPTH
- 1;
1433 dev
->admin_tagset
.reserved_tags
= 1;
1434 dev
->admin_tagset
.timeout
= ADMIN_TIMEOUT
;
1435 dev
->admin_tagset
.numa_node
= dev_to_node(dev
->dev
);
1436 dev
->admin_tagset
.cmd_size
= nvme_cmd_size(dev
);
1437 dev
->admin_tagset
.driver_data
= dev
;
1439 if (blk_mq_alloc_tag_set(&dev
->admin_tagset
))
1442 dev
->ctrl
.admin_q
= blk_mq_init_queue(&dev
->admin_tagset
);
1443 if (IS_ERR(dev
->ctrl
.admin_q
)) {
1444 blk_mq_free_tag_set(&dev
->admin_tagset
);
1447 if (!blk_get_queue(dev
->ctrl
.admin_q
)) {
1448 nvme_dev_remove_admin(dev
);
1449 dev
->ctrl
.admin_q
= NULL
;
1453 blk_mq_unfreeze_queue(dev
->ctrl
.admin_q
);
1458 static int nvme_configure_admin_queue(struct nvme_dev
*dev
)
1462 u64 cap
= lo_hi_readq(dev
->bar
+ NVME_REG_CAP
);
1463 struct nvme_queue
*nvmeq
;
1465 dev
->subsystem
= readl(dev
->bar
+ NVME_REG_VS
) >= NVME_VS(1, 1) ?
1466 NVME_CAP_NSSRC(cap
) : 0;
1468 if (dev
->subsystem
&&
1469 (readl(dev
->bar
+ NVME_REG_CSTS
) & NVME_CSTS_NSSRO
))
1470 writel(NVME_CSTS_NSSRO
, dev
->bar
+ NVME_REG_CSTS
);
1472 result
= nvme_disable_ctrl(&dev
->ctrl
, cap
);
1476 nvmeq
= dev
->queues
[0];
1478 nvmeq
= nvme_alloc_queue(dev
, 0, NVME_AQ_DEPTH
);
1483 aqa
= nvmeq
->q_depth
- 1;
1486 writel(aqa
, dev
->bar
+ NVME_REG_AQA
);
1487 lo_hi_writeq(nvmeq
->sq_dma_addr
, dev
->bar
+ NVME_REG_ASQ
);
1488 lo_hi_writeq(nvmeq
->cq_dma_addr
, dev
->bar
+ NVME_REG_ACQ
);
1490 result
= nvme_enable_ctrl(&dev
->ctrl
, cap
);
1494 nvmeq
->cq_vector
= 0;
1495 result
= queue_request_irq(dev
, nvmeq
, nvmeq
->irqname
);
1497 nvmeq
->cq_vector
= -1;
1504 nvme_free_queues(dev
, 0);
1508 static int nvme_subsys_reset(struct nvme_dev
*dev
)
1510 if (!dev
->subsystem
)
1513 writel(0x4E564D65, dev
->bar
+ NVME_REG_NSSR
); /* "NVMe" */
1517 static int nvme_kthread(void *data
)
1519 struct nvme_dev
*dev
, *next
;
1521 while (!kthread_should_stop()) {
1522 set_current_state(TASK_INTERRUPTIBLE
);
1523 spin_lock(&dev_list_lock
);
1524 list_for_each_entry_safe(dev
, next
, &dev_list
, node
) {
1526 u32 csts
= readl(dev
->bar
+ NVME_REG_CSTS
);
1528 if ((dev
->subsystem
&& (csts
& NVME_CSTS_NSSRO
)) ||
1529 csts
& NVME_CSTS_CFS
) {
1530 if (!__nvme_reset(dev
)) {
1532 "Failed status: %x, reset controller\n",
1533 readl(dev
->bar
+ NVME_REG_CSTS
));
1537 for (i
= 0; i
< dev
->queue_count
; i
++) {
1538 struct nvme_queue
*nvmeq
= dev
->queues
[i
];
1541 spin_lock_irq(&nvmeq
->q_lock
);
1542 nvme_process_cq(nvmeq
);
1544 while (i
== 0 && dev
->ctrl
.event_limit
> 0) {
1545 if (nvme_submit_async_admin_req(dev
))
1547 dev
->ctrl
.event_limit
--;
1549 spin_unlock_irq(&nvmeq
->q_lock
);
1552 spin_unlock(&dev_list_lock
);
1553 schedule_timeout(round_jiffies_relative(HZ
));
1559 * Create I/O queues. Failing to create an I/O queue is not an issue,
1560 * we can continue with less than the desired amount of queues, and
1561 * even a controller without I/O queues an still be used to issue
1562 * admin commands. This might be useful to upgrade a buggy firmware
1565 static void nvme_create_io_queues(struct nvme_dev
*dev
)
1569 for (i
= dev
->queue_count
; i
<= dev
->max_qid
; i
++)
1570 if (!nvme_alloc_queue(dev
, i
, dev
->q_depth
))
1573 for (i
= dev
->online_queues
; i
<= dev
->queue_count
- 1; i
++)
1574 if (nvme_create_queue(dev
->queues
[i
], i
)) {
1575 nvme_free_queues(dev
, i
);
1580 static int set_queue_count(struct nvme_dev
*dev
, int count
)
1584 u32 q_count
= (count
- 1) | ((count
- 1) << 16);
1586 status
= nvme_set_features(&dev
->ctrl
, NVME_FEAT_NUM_QUEUES
, q_count
, 0,
1591 dev_err(dev
->dev
, "Could not set queue count (%d)\n", status
);
1594 return min(result
& 0xffff, result
>> 16) + 1;
1597 static void __iomem
*nvme_map_cmb(struct nvme_dev
*dev
)
1599 u64 szu
, size
, offset
;
1601 resource_size_t bar_size
;
1602 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1604 dma_addr_t dma_addr
;
1609 dev
->cmbsz
= readl(dev
->bar
+ NVME_REG_CMBSZ
);
1610 if (!(NVME_CMB_SZ(dev
->cmbsz
)))
1613 cmbloc
= readl(dev
->bar
+ NVME_REG_CMBLOC
);
1615 szu
= (u64
)1 << (12 + 4 * NVME_CMB_SZU(dev
->cmbsz
));
1616 size
= szu
* NVME_CMB_SZ(dev
->cmbsz
);
1617 offset
= szu
* NVME_CMB_OFST(cmbloc
);
1618 bar_size
= pci_resource_len(pdev
, NVME_CMB_BIR(cmbloc
));
1620 if (offset
> bar_size
)
1624 * Controllers may support a CMB size larger than their BAR,
1625 * for example, due to being behind a bridge. Reduce the CMB to
1626 * the reported size of the BAR
1628 if (size
> bar_size
- offset
)
1629 size
= bar_size
- offset
;
1631 dma_addr
= pci_resource_start(pdev
, NVME_CMB_BIR(cmbloc
)) + offset
;
1632 cmb
= ioremap_wc(dma_addr
, size
);
1636 dev
->cmb_dma_addr
= dma_addr
;
1637 dev
->cmb_size
= size
;
1641 static inline void nvme_release_cmb(struct nvme_dev
*dev
)
1649 static size_t db_bar_size(struct nvme_dev
*dev
, unsigned nr_io_queues
)
1651 return 4096 + ((nr_io_queues
+ 1) * 8 * dev
->db_stride
);
1654 static int nvme_setup_io_queues(struct nvme_dev
*dev
)
1656 struct nvme_queue
*adminq
= dev
->queues
[0];
1657 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1658 int result
, i
, vecs
, nr_io_queues
, size
;
1660 nr_io_queues
= num_possible_cpus();
1661 result
= set_queue_count(dev
, nr_io_queues
);
1664 if (result
< nr_io_queues
)
1665 nr_io_queues
= result
;
1667 if (dev
->cmb
&& NVME_CMB_SQS(dev
->cmbsz
)) {
1668 result
= nvme_cmb_qdepth(dev
, nr_io_queues
,
1669 sizeof(struct nvme_command
));
1671 dev
->q_depth
= result
;
1673 nvme_release_cmb(dev
);
1676 size
= db_bar_size(dev
, nr_io_queues
);
1680 dev
->bar
= ioremap(pci_resource_start(pdev
, 0), size
);
1683 if (!--nr_io_queues
)
1685 size
= db_bar_size(dev
, nr_io_queues
);
1687 dev
->dbs
= dev
->bar
+ 4096;
1688 adminq
->q_db
= dev
->dbs
;
1691 /* Deregister the admin queue's interrupt */
1692 free_irq(dev
->entry
[0].vector
, adminq
);
1695 * If we enable msix early due to not intx, disable it again before
1696 * setting up the full range we need.
1699 pci_disable_msix(pdev
);
1701 for (i
= 0; i
< nr_io_queues
; i
++)
1702 dev
->entry
[i
].entry
= i
;
1703 vecs
= pci_enable_msix_range(pdev
, dev
->entry
, 1, nr_io_queues
);
1705 vecs
= pci_enable_msi_range(pdev
, 1, min(nr_io_queues
, 32));
1709 for (i
= 0; i
< vecs
; i
++)
1710 dev
->entry
[i
].vector
= i
+ pdev
->irq
;
1715 * Should investigate if there's a performance win from allocating
1716 * more queues than interrupt vectors; it might allow the submission
1717 * path to scale better, even if the receive path is limited by the
1718 * number of interrupts.
1720 nr_io_queues
= vecs
;
1721 dev
->max_qid
= nr_io_queues
;
1723 result
= queue_request_irq(dev
, adminq
, adminq
->irqname
);
1725 adminq
->cq_vector
= -1;
1729 /* Free previously allocated queues that are no longer usable */
1730 nvme_free_queues(dev
, nr_io_queues
+ 1);
1731 nvme_create_io_queues(dev
);
1736 nvme_free_queues(dev
, 1);
1740 static void nvme_set_irq_hints(struct nvme_dev
*dev
)
1742 struct nvme_queue
*nvmeq
;
1745 for (i
= 0; i
< dev
->online_queues
; i
++) {
1746 nvmeq
= dev
->queues
[i
];
1748 if (!nvmeq
->tags
|| !(*nvmeq
->tags
))
1751 irq_set_affinity_hint(dev
->entry
[nvmeq
->cq_vector
].vector
,
1752 blk_mq_tags_cpumask(*nvmeq
->tags
));
1756 static void nvme_dev_scan(struct work_struct
*work
)
1758 struct nvme_dev
*dev
= container_of(work
, struct nvme_dev
, scan_work
);
1760 if (!dev
->tagset
.tags
)
1762 nvme_scan_namespaces(&dev
->ctrl
);
1763 nvme_set_irq_hints(dev
);
1767 * Return: error value if an error occurred setting up the queues or calling
1768 * Identify Device. 0 if these succeeded, even if adding some of the
1769 * namespaces failed. At the moment, these failures are silent. TBD which
1770 * failures should be reported.
1772 static int nvme_dev_add(struct nvme_dev
*dev
)
1774 if (!dev
->ctrl
.tagset
) {
1775 dev
->tagset
.ops
= &nvme_mq_ops
;
1776 dev
->tagset
.nr_hw_queues
= dev
->online_queues
- 1;
1777 dev
->tagset
.timeout
= NVME_IO_TIMEOUT
;
1778 dev
->tagset
.numa_node
= dev_to_node(dev
->dev
);
1779 dev
->tagset
.queue_depth
=
1780 min_t(int, dev
->q_depth
, BLK_MQ_MAX_DEPTH
) - 1;
1781 dev
->tagset
.cmd_size
= nvme_cmd_size(dev
);
1782 dev
->tagset
.flags
= BLK_MQ_F_SHOULD_MERGE
;
1783 dev
->tagset
.driver_data
= dev
;
1785 if (blk_mq_alloc_tag_set(&dev
->tagset
))
1787 dev
->ctrl
.tagset
= &dev
->tagset
;
1789 schedule_work(&dev
->scan_work
);
1793 static int nvme_dev_map(struct nvme_dev
*dev
)
1796 int bars
, result
= -ENOMEM
;
1797 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1799 if (pci_enable_device_mem(pdev
))
1802 dev
->entry
[0].vector
= pdev
->irq
;
1803 pci_set_master(pdev
);
1804 bars
= pci_select_bars(pdev
, IORESOURCE_MEM
);
1808 if (pci_request_selected_regions(pdev
, bars
, "nvme"))
1811 if (dma_set_mask_and_coherent(dev
->dev
, DMA_BIT_MASK(64)) &&
1812 dma_set_mask_and_coherent(dev
->dev
, DMA_BIT_MASK(32)))
1815 dev
->bar
= ioremap(pci_resource_start(pdev
, 0), 8192);
1819 if (readl(dev
->bar
+ NVME_REG_CSTS
) == -1) {
1825 * Some devices don't advertse INTx interrupts, pre-enable a single
1826 * MSIX vec for setup. We'll adjust this later.
1829 result
= pci_enable_msix(pdev
, dev
->entry
, 1);
1834 cap
= lo_hi_readq(dev
->bar
+ NVME_REG_CAP
);
1836 dev
->q_depth
= min_t(int, NVME_CAP_MQES(cap
) + 1, NVME_Q_DEPTH
);
1837 dev
->db_stride
= 1 << NVME_CAP_STRIDE(cap
);
1838 dev
->dbs
= dev
->bar
+ 4096;
1839 if (readl(dev
->bar
+ NVME_REG_VS
) >= NVME_VS(1, 2))
1840 dev
->cmb
= nvme_map_cmb(dev
);
1848 pci_release_regions(pdev
);
1850 pci_disable_device(pdev
);
1854 static void nvme_dev_unmap(struct nvme_dev
*dev
)
1856 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1858 if (pdev
->msi_enabled
)
1859 pci_disable_msi(pdev
);
1860 else if (pdev
->msix_enabled
)
1861 pci_disable_msix(pdev
);
1866 pci_release_regions(pdev
);
1869 if (pci_is_enabled(pdev
))
1870 pci_disable_device(pdev
);
1873 struct nvme_delq_ctx
{
1874 struct task_struct
*waiter
;
1875 struct kthread_worker
*worker
;
1879 static void nvme_wait_dq(struct nvme_delq_ctx
*dq
, struct nvme_dev
*dev
)
1881 dq
->waiter
= current
;
1885 set_current_state(TASK_KILLABLE
);
1886 if (!atomic_read(&dq
->refcount
))
1888 if (!schedule_timeout(ADMIN_TIMEOUT
) ||
1889 fatal_signal_pending(current
)) {
1891 * Disable the controller first since we can't trust it
1892 * at this point, but leave the admin queue enabled
1893 * until all queue deletion requests are flushed.
1894 * FIXME: This may take a while if there are more h/w
1895 * queues than admin tags.
1897 set_current_state(TASK_RUNNING
);
1898 nvme_disable_ctrl(&dev
->ctrl
,
1899 lo_hi_readq(dev
->bar
+ NVME_REG_CAP
));
1900 nvme_clear_queue(dev
->queues
[0]);
1901 flush_kthread_worker(dq
->worker
);
1902 nvme_disable_queue(dev
, 0);
1906 set_current_state(TASK_RUNNING
);
1909 static void nvme_put_dq(struct nvme_delq_ctx
*dq
)
1911 atomic_dec(&dq
->refcount
);
1913 wake_up_process(dq
->waiter
);
1916 static struct nvme_delq_ctx
*nvme_get_dq(struct nvme_delq_ctx
*dq
)
1918 atomic_inc(&dq
->refcount
);
1922 static void nvme_del_queue_end(struct nvme_queue
*nvmeq
)
1924 struct nvme_delq_ctx
*dq
= nvmeq
->cmdinfo
.ctx
;
1927 spin_lock_irq(&nvmeq
->q_lock
);
1928 nvme_process_cq(nvmeq
);
1929 spin_unlock_irq(&nvmeq
->q_lock
);
1932 static int adapter_async_del_queue(struct nvme_queue
*nvmeq
, u8 opcode
,
1933 kthread_work_func_t fn
)
1935 struct nvme_command c
;
1937 memset(&c
, 0, sizeof(c
));
1938 c
.delete_queue
.opcode
= opcode
;
1939 c
.delete_queue
.qid
= cpu_to_le16(nvmeq
->qid
);
1941 init_kthread_work(&nvmeq
->cmdinfo
.work
, fn
);
1942 return nvme_submit_admin_async_cmd(nvmeq
->dev
, &c
, &nvmeq
->cmdinfo
,
1946 static void nvme_del_cq_work_handler(struct kthread_work
*work
)
1948 struct nvme_queue
*nvmeq
= container_of(work
, struct nvme_queue
,
1950 nvme_del_queue_end(nvmeq
);
1953 static int nvme_delete_cq(struct nvme_queue
*nvmeq
)
1955 return adapter_async_del_queue(nvmeq
, nvme_admin_delete_cq
,
1956 nvme_del_cq_work_handler
);
1959 static void nvme_del_sq_work_handler(struct kthread_work
*work
)
1961 struct nvme_queue
*nvmeq
= container_of(work
, struct nvme_queue
,
1963 int status
= nvmeq
->cmdinfo
.status
;
1966 status
= nvme_delete_cq(nvmeq
);
1968 nvme_del_queue_end(nvmeq
);
1971 static int nvme_delete_sq(struct nvme_queue
*nvmeq
)
1973 return adapter_async_del_queue(nvmeq
, nvme_admin_delete_sq
,
1974 nvme_del_sq_work_handler
);
1977 static void nvme_del_queue_start(struct kthread_work
*work
)
1979 struct nvme_queue
*nvmeq
= container_of(work
, struct nvme_queue
,
1981 if (nvme_delete_sq(nvmeq
))
1982 nvme_del_queue_end(nvmeq
);
1985 static void nvme_disable_io_queues(struct nvme_dev
*dev
)
1988 DEFINE_KTHREAD_WORKER_ONSTACK(worker
);
1989 struct nvme_delq_ctx dq
;
1990 struct task_struct
*kworker_task
= kthread_run(kthread_worker_fn
,
1991 &worker
, "nvme%d", dev
->ctrl
.instance
);
1993 if (IS_ERR(kworker_task
)) {
1995 "Failed to create queue del task\n");
1996 for (i
= dev
->queue_count
- 1; i
> 0; i
--)
1997 nvme_disable_queue(dev
, i
);
2002 atomic_set(&dq
.refcount
, 0);
2003 dq
.worker
= &worker
;
2004 for (i
= dev
->queue_count
- 1; i
> 0; i
--) {
2005 struct nvme_queue
*nvmeq
= dev
->queues
[i
];
2007 if (nvme_suspend_queue(nvmeq
))
2009 nvmeq
->cmdinfo
.ctx
= nvme_get_dq(&dq
);
2010 nvmeq
->cmdinfo
.worker
= dq
.worker
;
2011 init_kthread_work(&nvmeq
->cmdinfo
.work
, nvme_del_queue_start
);
2012 queue_kthread_work(dq
.worker
, &nvmeq
->cmdinfo
.work
);
2014 nvme_wait_dq(&dq
, dev
);
2015 kthread_stop(kworker_task
);
2019 * Remove the node from the device list and check
2020 * for whether or not we need to stop the nvme_thread.
2022 static void nvme_dev_list_remove(struct nvme_dev
*dev
)
2024 struct task_struct
*tmp
= NULL
;
2026 spin_lock(&dev_list_lock
);
2027 list_del_init(&dev
->node
);
2028 if (list_empty(&dev_list
) && !IS_ERR_OR_NULL(nvme_thread
)) {
2032 spin_unlock(&dev_list_lock
);
2038 static void nvme_freeze_queues(struct nvme_dev
*dev
)
2042 list_for_each_entry(ns
, &dev
->ctrl
.namespaces
, list
) {
2043 blk_mq_freeze_queue_start(ns
->queue
);
2045 spin_lock_irq(ns
->queue
->queue_lock
);
2046 queue_flag_set(QUEUE_FLAG_STOPPED
, ns
->queue
);
2047 spin_unlock_irq(ns
->queue
->queue_lock
);
2049 blk_mq_cancel_requeue_work(ns
->queue
);
2050 blk_mq_stop_hw_queues(ns
->queue
);
2054 static void nvme_unfreeze_queues(struct nvme_dev
*dev
)
2058 list_for_each_entry(ns
, &dev
->ctrl
.namespaces
, list
) {
2059 queue_flag_clear_unlocked(QUEUE_FLAG_STOPPED
, ns
->queue
);
2060 blk_mq_unfreeze_queue(ns
->queue
);
2061 blk_mq_start_stopped_hw_queues(ns
->queue
, true);
2062 blk_mq_kick_requeue_list(ns
->queue
);
2066 static void nvme_dev_shutdown(struct nvme_dev
*dev
)
2071 nvme_dev_list_remove(dev
);
2074 nvme_freeze_queues(dev
);
2075 csts
= readl(dev
->bar
+ NVME_REG_CSTS
);
2077 if (csts
& NVME_CSTS_CFS
|| !(csts
& NVME_CSTS_RDY
)) {
2078 for (i
= dev
->queue_count
- 1; i
>= 0; i
--) {
2079 struct nvme_queue
*nvmeq
= dev
->queues
[i
];
2080 nvme_suspend_queue(nvmeq
);
2083 nvme_disable_io_queues(dev
);
2084 nvme_shutdown_ctrl(&dev
->ctrl
);
2085 nvme_disable_queue(dev
, 0);
2087 nvme_dev_unmap(dev
);
2089 for (i
= dev
->queue_count
- 1; i
>= 0; i
--)
2090 nvme_clear_queue(dev
->queues
[i
]);
2093 static int nvme_setup_prp_pools(struct nvme_dev
*dev
)
2095 dev
->prp_page_pool
= dma_pool_create("prp list page", dev
->dev
,
2096 PAGE_SIZE
, PAGE_SIZE
, 0);
2097 if (!dev
->prp_page_pool
)
2100 /* Optimisation for I/Os between 4k and 128k */
2101 dev
->prp_small_pool
= dma_pool_create("prp list 256", dev
->dev
,
2103 if (!dev
->prp_small_pool
) {
2104 dma_pool_destroy(dev
->prp_page_pool
);
2110 static void nvme_release_prp_pools(struct nvme_dev
*dev
)
2112 dma_pool_destroy(dev
->prp_page_pool
);
2113 dma_pool_destroy(dev
->prp_small_pool
);
2116 static DEFINE_IDA(nvme_instance_ida
);
2118 static int nvme_set_instance(struct nvme_dev
*dev
)
2120 int instance
, error
;
2123 if (!ida_pre_get(&nvme_instance_ida
, GFP_KERNEL
))
2126 spin_lock(&dev_list_lock
);
2127 error
= ida_get_new(&nvme_instance_ida
, &instance
);
2128 spin_unlock(&dev_list_lock
);
2129 } while (error
== -EAGAIN
);
2134 dev
->ctrl
.instance
= instance
;
2138 static void nvme_release_instance(struct nvme_dev
*dev
)
2140 spin_lock(&dev_list_lock
);
2141 ida_remove(&nvme_instance_ida
, dev
->ctrl
.instance
);
2142 spin_unlock(&dev_list_lock
);
2145 static void nvme_pci_free_ctrl(struct nvme_ctrl
*ctrl
)
2147 struct nvme_dev
*dev
= to_nvme_dev(ctrl
);
2149 put_device(dev
->dev
);
2150 put_device(ctrl
->device
);
2151 nvme_release_instance(dev
);
2152 if (dev
->tagset
.tags
)
2153 blk_mq_free_tag_set(&dev
->tagset
);
2154 if (dev
->ctrl
.admin_q
)
2155 blk_put_queue(dev
->ctrl
.admin_q
);
2161 static int nvme_dev_open(struct inode
*inode
, struct file
*f
)
2163 struct nvme_dev
*dev
;
2164 int instance
= iminor(inode
);
2167 spin_lock(&dev_list_lock
);
2168 list_for_each_entry(dev
, &dev_list
, node
) {
2169 if (dev
->ctrl
.instance
== instance
) {
2170 if (!dev
->ctrl
.admin_q
) {
2174 if (!kref_get_unless_zero(&dev
->ctrl
.kref
))
2176 f
->private_data
= dev
;
2181 spin_unlock(&dev_list_lock
);
2186 static int nvme_dev_release(struct inode
*inode
, struct file
*f
)
2188 struct nvme_dev
*dev
= f
->private_data
;
2189 nvme_put_ctrl(&dev
->ctrl
);
2193 static long nvme_dev_ioctl(struct file
*f
, unsigned int cmd
, unsigned long arg
)
2195 struct nvme_dev
*dev
= f
->private_data
;
2199 case NVME_IOCTL_ADMIN_CMD
:
2200 return nvme_user_cmd(&dev
->ctrl
, NULL
, (void __user
*)arg
);
2201 case NVME_IOCTL_IO_CMD
:
2202 if (list_empty(&dev
->ctrl
.namespaces
))
2204 ns
= list_first_entry(&dev
->ctrl
.namespaces
, struct nvme_ns
, list
);
2205 return nvme_user_cmd(&dev
->ctrl
, ns
, (void __user
*)arg
);
2206 case NVME_IOCTL_RESET
:
2207 dev_warn(dev
->dev
, "resetting controller\n");
2208 return nvme_reset(dev
);
2209 case NVME_IOCTL_SUBSYS_RESET
:
2210 return nvme_subsys_reset(dev
);
2216 static const struct file_operations nvme_dev_fops
= {
2217 .owner
= THIS_MODULE
,
2218 .open
= nvme_dev_open
,
2219 .release
= nvme_dev_release
,
2220 .unlocked_ioctl
= nvme_dev_ioctl
,
2221 .compat_ioctl
= nvme_dev_ioctl
,
2224 static void nvme_probe_work(struct work_struct
*work
)
2226 struct nvme_dev
*dev
= container_of(work
, struct nvme_dev
, probe_work
);
2227 bool start_thread
= false;
2230 result
= nvme_dev_map(dev
);
2234 result
= nvme_configure_admin_queue(dev
);
2238 spin_lock(&dev_list_lock
);
2239 if (list_empty(&dev_list
) && IS_ERR_OR_NULL(nvme_thread
)) {
2240 start_thread
= true;
2243 list_add(&dev
->node
, &dev_list
);
2244 spin_unlock(&dev_list_lock
);
2247 nvme_thread
= kthread_run(nvme_kthread
, NULL
, "nvme");
2248 wake_up_all(&nvme_kthread_wait
);
2250 wait_event_killable(nvme_kthread_wait
, nvme_thread
);
2252 if (IS_ERR_OR_NULL(nvme_thread
)) {
2253 result
= nvme_thread
? PTR_ERR(nvme_thread
) : -EINTR
;
2257 nvme_init_queue(dev
->queues
[0], 0);
2258 result
= nvme_alloc_admin_tags(dev
);
2262 result
= nvme_init_identify(&dev
->ctrl
);
2266 result
= nvme_setup_io_queues(dev
);
2270 dev
->ctrl
.event_limit
= 1;
2273 * Keep the controller around but remove all namespaces if we don't have
2274 * any working I/O queue.
2276 if (dev
->online_queues
< 2) {
2277 dev_warn(dev
->dev
, "IO queues not created\n");
2278 nvme_remove_namespaces(&dev
->ctrl
);
2280 nvme_unfreeze_queues(dev
);
2287 nvme_dev_remove_admin(dev
);
2288 blk_put_queue(dev
->ctrl
.admin_q
);
2289 dev
->ctrl
.admin_q
= NULL
;
2290 dev
->queues
[0]->tags
= NULL
;
2292 nvme_disable_queue(dev
, 0);
2293 nvme_dev_list_remove(dev
);
2295 nvme_dev_unmap(dev
);
2297 if (!work_busy(&dev
->reset_work
))
2298 nvme_dead_ctrl(dev
);
2301 static int nvme_remove_dead_ctrl(void *arg
)
2303 struct nvme_dev
*dev
= (struct nvme_dev
*)arg
;
2304 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
2306 if (pci_get_drvdata(pdev
))
2307 pci_stop_and_remove_bus_device_locked(pdev
);
2308 nvme_put_ctrl(&dev
->ctrl
);
2312 static void nvme_dead_ctrl(struct nvme_dev
*dev
)
2314 dev_warn(dev
->dev
, "Device failed to resume\n");
2315 kref_get(&dev
->ctrl
.kref
);
2316 if (IS_ERR(kthread_run(nvme_remove_dead_ctrl
, dev
, "nvme%d",
2317 dev
->ctrl
.instance
))) {
2319 "Failed to start controller remove task\n");
2320 nvme_put_ctrl(&dev
->ctrl
);
2324 static void nvme_reset_work(struct work_struct
*ws
)
2326 struct nvme_dev
*dev
= container_of(ws
, struct nvme_dev
, reset_work
);
2327 bool in_probe
= work_busy(&dev
->probe_work
);
2329 nvme_dev_shutdown(dev
);
2331 /* Synchronize with device probe so that work will see failure status
2332 * and exit gracefully without trying to schedule another reset */
2333 flush_work(&dev
->probe_work
);
2335 /* Fail this device if reset occured during probe to avoid
2336 * infinite initialization loops. */
2338 nvme_dead_ctrl(dev
);
2341 /* Schedule device resume asynchronously so the reset work is available
2342 * to cleanup errors that may occur during reinitialization */
2343 schedule_work(&dev
->probe_work
);
2346 static int __nvme_reset(struct nvme_dev
*dev
)
2348 if (work_pending(&dev
->reset_work
))
2350 list_del_init(&dev
->node
);
2351 queue_work(nvme_workq
, &dev
->reset_work
);
2355 static int nvme_reset(struct nvme_dev
*dev
)
2359 if (!dev
->ctrl
.admin_q
|| blk_queue_dying(dev
->ctrl
.admin_q
))
2362 spin_lock(&dev_list_lock
);
2363 ret
= __nvme_reset(dev
);
2364 spin_unlock(&dev_list_lock
);
2367 flush_work(&dev
->reset_work
);
2368 flush_work(&dev
->probe_work
);
2375 static ssize_t
nvme_sysfs_reset(struct device
*dev
,
2376 struct device_attribute
*attr
, const char *buf
,
2379 struct nvme_dev
*ndev
= dev_get_drvdata(dev
);
2382 ret
= nvme_reset(ndev
);
2388 static DEVICE_ATTR(reset_controller
, S_IWUSR
, NULL
, nvme_sysfs_reset
);
2390 static int nvme_pci_reg_read32(struct nvme_ctrl
*ctrl
, u32 off
, u32
*val
)
2392 *val
= readl(to_nvme_dev(ctrl
)->bar
+ off
);
2396 static int nvme_pci_reg_write32(struct nvme_ctrl
*ctrl
, u32 off
, u32 val
)
2398 writel(val
, to_nvme_dev(ctrl
)->bar
+ off
);
2402 static int nvme_pci_reg_read64(struct nvme_ctrl
*ctrl
, u32 off
, u64
*val
)
2404 *val
= readq(to_nvme_dev(ctrl
)->bar
+ off
);
2408 static bool nvme_pci_io_incapable(struct nvme_ctrl
*ctrl
)
2410 struct nvme_dev
*dev
= to_nvme_dev(ctrl
);
2412 return !dev
->bar
|| dev
->online_queues
< 2;
2415 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops
= {
2416 .reg_read32
= nvme_pci_reg_read32
,
2417 .reg_write32
= nvme_pci_reg_write32
,
2418 .reg_read64
= nvme_pci_reg_read64
,
2419 .io_incapable
= nvme_pci_io_incapable
,
2420 .free_ctrl
= nvme_pci_free_ctrl
,
2423 static int nvme_probe(struct pci_dev
*pdev
, const struct pci_device_id
*id
)
2425 int node
, result
= -ENOMEM
;
2426 struct nvme_dev
*dev
;
2428 node
= dev_to_node(&pdev
->dev
);
2429 if (node
== NUMA_NO_NODE
)
2430 set_dev_node(&pdev
->dev
, 0);
2432 dev
= kzalloc_node(sizeof(*dev
), GFP_KERNEL
, node
);
2435 dev
->entry
= kzalloc_node(num_possible_cpus() * sizeof(*dev
->entry
),
2439 dev
->queues
= kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
2444 INIT_LIST_HEAD(&dev
->ctrl
.namespaces
);
2445 INIT_WORK(&dev
->reset_work
, nvme_reset_work
);
2446 dev
->dev
= get_device(&pdev
->dev
);
2447 pci_set_drvdata(pdev
, dev
);
2449 dev
->ctrl
.ops
= &nvme_pci_ctrl_ops
;
2450 dev
->ctrl
.dev
= dev
->dev
;
2451 dev
->ctrl
.quirks
= id
->driver_data
;
2453 result
= nvme_set_instance(dev
);
2457 result
= nvme_setup_prp_pools(dev
);
2461 kref_init(&dev
->ctrl
.kref
);
2462 dev
->ctrl
.device
= device_create(nvme_class
, &pdev
->dev
,
2463 MKDEV(nvme_char_major
, dev
->ctrl
.instance
),
2464 dev
, "nvme%d", dev
->ctrl
.instance
);
2465 if (IS_ERR(dev
->ctrl
.device
)) {
2466 result
= PTR_ERR(dev
->ctrl
.device
);
2469 get_device(dev
->ctrl
.device
);
2470 dev_set_drvdata(dev
->ctrl
.device
, dev
);
2472 result
= device_create_file(dev
->ctrl
.device
, &dev_attr_reset_controller
);
2476 INIT_LIST_HEAD(&dev
->node
);
2477 INIT_WORK(&dev
->scan_work
, nvme_dev_scan
);
2478 INIT_WORK(&dev
->probe_work
, nvme_probe_work
);
2479 schedule_work(&dev
->probe_work
);
2483 device_destroy(nvme_class
, MKDEV(nvme_char_major
, dev
->ctrl
.instance
));
2484 put_device(dev
->ctrl
.device
);
2486 nvme_release_prp_pools(dev
);
2488 nvme_release_instance(dev
);
2490 put_device(dev
->dev
);
2498 static void nvme_reset_notify(struct pci_dev
*pdev
, bool prepare
)
2500 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2503 nvme_dev_shutdown(dev
);
2505 schedule_work(&dev
->probe_work
);
2508 static void nvme_shutdown(struct pci_dev
*pdev
)
2510 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2511 nvme_dev_shutdown(dev
);
2514 static void nvme_remove(struct pci_dev
*pdev
)
2516 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2518 spin_lock(&dev_list_lock
);
2519 list_del_init(&dev
->node
);
2520 spin_unlock(&dev_list_lock
);
2522 pci_set_drvdata(pdev
, NULL
);
2523 flush_work(&dev
->probe_work
);
2524 flush_work(&dev
->reset_work
);
2525 flush_work(&dev
->scan_work
);
2526 device_remove_file(dev
->ctrl
.device
, &dev_attr_reset_controller
);
2527 nvme_remove_namespaces(&dev
->ctrl
);
2528 nvme_dev_shutdown(dev
);
2529 nvme_dev_remove_admin(dev
);
2530 device_destroy(nvme_class
, MKDEV(nvme_char_major
, dev
->ctrl
.instance
));
2531 nvme_free_queues(dev
, 0);
2532 nvme_release_cmb(dev
);
2533 nvme_release_prp_pools(dev
);
2534 nvme_put_ctrl(&dev
->ctrl
);
2537 /* These functions are yet to be implemented */
2538 #define nvme_error_detected NULL
2539 #define nvme_dump_registers NULL
2540 #define nvme_link_reset NULL
2541 #define nvme_slot_reset NULL
2542 #define nvme_error_resume NULL
2544 #ifdef CONFIG_PM_SLEEP
2545 static int nvme_suspend(struct device
*dev
)
2547 struct pci_dev
*pdev
= to_pci_dev(dev
);
2548 struct nvme_dev
*ndev
= pci_get_drvdata(pdev
);
2550 nvme_dev_shutdown(ndev
);
2554 static int nvme_resume(struct device
*dev
)
2556 struct pci_dev
*pdev
= to_pci_dev(dev
);
2557 struct nvme_dev
*ndev
= pci_get_drvdata(pdev
);
2559 schedule_work(&ndev
->probe_work
);
2564 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops
, nvme_suspend
, nvme_resume
);
2566 static const struct pci_error_handlers nvme_err_handler
= {
2567 .error_detected
= nvme_error_detected
,
2568 .mmio_enabled
= nvme_dump_registers
,
2569 .link_reset
= nvme_link_reset
,
2570 .slot_reset
= nvme_slot_reset
,
2571 .resume
= nvme_error_resume
,
2572 .reset_notify
= nvme_reset_notify
,
2575 /* Move to pci_ids.h later */
2576 #define PCI_CLASS_STORAGE_EXPRESS 0x010802
2578 static const struct pci_device_id nvme_id_table
[] = {
2579 { PCI_VDEVICE(INTEL
, 0x0953),
2580 .driver_data
= NVME_QUIRK_STRIPE_SIZE
, },
2581 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS
, 0xffffff) },
2582 { PCI_DEVICE(PCI_VENDOR_ID_APPLE
, 0x2001) },
2585 MODULE_DEVICE_TABLE(pci
, nvme_id_table
);
2587 static struct pci_driver nvme_driver
= {
2589 .id_table
= nvme_id_table
,
2590 .probe
= nvme_probe
,
2591 .remove
= nvme_remove
,
2592 .shutdown
= nvme_shutdown
,
2594 .pm
= &nvme_dev_pm_ops
,
2596 .err_handler
= &nvme_err_handler
,
2599 static int __init
nvme_init(void)
2603 init_waitqueue_head(&nvme_kthread_wait
);
2605 nvme_workq
= create_singlethread_workqueue("nvme");
2609 result
= nvme_core_init();
2613 result
= __register_chrdev(nvme_char_major
, 0, NVME_MINORS
, "nvme",
2616 goto unregister_blkdev
;
2617 else if (result
> 0)
2618 nvme_char_major
= result
;
2620 nvme_class
= class_create(THIS_MODULE
, "nvme");
2621 if (IS_ERR(nvme_class
)) {
2622 result
= PTR_ERR(nvme_class
);
2623 goto unregister_chrdev
;
2626 result
= pci_register_driver(&nvme_driver
);
2632 class_destroy(nvme_class
);
2634 __unregister_chrdev(nvme_char_major
, 0, NVME_MINORS
, "nvme");
2638 destroy_workqueue(nvme_workq
);
2642 static void __exit
nvme_exit(void)
2644 pci_unregister_driver(&nvme_driver
);
2646 destroy_workqueue(nvme_workq
);
2647 class_destroy(nvme_class
);
2648 __unregister_chrdev(nvme_char_major
, 0, NVME_MINORS
, "nvme");
2649 BUG_ON(nvme_thread
&& !IS_ERR(nvme_thread
));
2653 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2654 MODULE_LICENSE("GPL");
2655 MODULE_VERSION("1.0");
2656 module_init(nvme_init
);
2657 module_exit(nvme_exit
);