2 * NVM Express device driver
3 * Copyright (c) 2011-2014, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 #include <linux/aer.h>
16 #include <linux/bitops.h>
17 #include <linux/blkdev.h>
18 #include <linux/blk-mq.h>
19 #include <linux/cpu.h>
20 #include <linux/delay.h>
21 #include <linux/errno.h>
23 #include <linux/genhd.h>
24 #include <linux/hdreg.h>
25 #include <linux/idr.h>
26 #include <linux/init.h>
27 #include <linux/interrupt.h>
29 #include <linux/kdev_t.h>
30 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/moduleparam.h>
34 #include <linux/mutex.h>
35 #include <linux/pci.h>
36 #include <linux/poison.h>
37 #include <linux/ptrace.h>
38 #include <linux/sched.h>
39 #include <linux/slab.h>
40 #include <linux/t10-pi.h>
41 #include <linux/timer.h>
42 #include <linux/types.h>
43 #include <linux/io-64-nonatomic-lo-hi.h>
44 #include <asm/unaligned.h>
48 #define NVME_Q_DEPTH 1024
49 #define NVME_AQ_DEPTH 256
50 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
51 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
54 * We handle AEN commands ourselves and don't even let the
55 * block layer know about them.
57 #define NVME_AQ_BLKMQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AERS)
59 static int use_threaded_interrupts
;
60 module_param(use_threaded_interrupts
, int, 0);
62 static bool use_cmb_sqes
= true;
63 module_param(use_cmb_sqes
, bool, 0644);
64 MODULE_PARM_DESC(use_cmb_sqes
, "use controller's memory buffer for I/O SQes");
66 static struct workqueue_struct
*nvme_workq
;
71 static int nvme_reset(struct nvme_dev
*dev
);
72 static void nvme_process_cq(struct nvme_queue
*nvmeq
);
73 static void nvme_dev_disable(struct nvme_dev
*dev
, bool shutdown
);
76 * Represents an NVM Express device. Each nvme_dev is a PCI function.
79 struct nvme_queue
**queues
;
80 struct blk_mq_tag_set tagset
;
81 struct blk_mq_tag_set admin_tagset
;
84 struct dma_pool
*prp_page_pool
;
85 struct dma_pool
*prp_small_pool
;
87 unsigned online_queues
;
91 struct msix_entry
*entry
;
93 struct work_struct reset_work
;
94 struct work_struct remove_work
;
95 struct timer_list watchdog_timer
;
96 struct mutex shutdown_lock
;
99 dma_addr_t cmb_dma_addr
;
102 struct nvme_ctrl ctrl
;
103 struct completion ioq_wait
;
106 static inline struct nvme_dev
*to_nvme_dev(struct nvme_ctrl
*ctrl
)
108 return container_of(ctrl
, struct nvme_dev
, ctrl
);
112 * An NVM Express queue. Each device has at least two (one for admin
113 * commands and one for I/O commands).
116 struct device
*q_dmadev
;
117 struct nvme_dev
*dev
;
118 char irqname
[24]; /* nvme4294967295-65535\0 */
120 struct nvme_command
*sq_cmds
;
121 struct nvme_command __iomem
*sq_cmds_io
;
122 volatile struct nvme_completion
*cqes
;
123 struct blk_mq_tags
**tags
;
124 dma_addr_t sq_dma_addr
;
125 dma_addr_t cq_dma_addr
;
137 * The nvme_iod describes the data in an I/O, including the list of PRP
138 * entries. You can't see it in this data structure because C doesn't let
139 * me express that. Use nvme_init_iod to ensure there's enough space
140 * allocated to store the PRP list.
143 struct nvme_queue
*nvmeq
;
145 int npages
; /* In the PRP list. 0 means small pool in use */
146 int nents
; /* Used in scatterlist */
147 int length
; /* Of data, in bytes */
148 dma_addr_t first_dma
;
149 struct scatterlist meta_sg
; /* metadata requires single contiguous buffer */
150 struct scatterlist
*sg
;
151 struct scatterlist inline_sg
[0];
155 * Check we didin't inadvertently grow the command struct
157 static inline void _nvme_check_size(void)
159 BUILD_BUG_ON(sizeof(struct nvme_rw_command
) != 64);
160 BUILD_BUG_ON(sizeof(struct nvme_create_cq
) != 64);
161 BUILD_BUG_ON(sizeof(struct nvme_create_sq
) != 64);
162 BUILD_BUG_ON(sizeof(struct nvme_delete_queue
) != 64);
163 BUILD_BUG_ON(sizeof(struct nvme_features
) != 64);
164 BUILD_BUG_ON(sizeof(struct nvme_format_cmd
) != 64);
165 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd
) != 64);
166 BUILD_BUG_ON(sizeof(struct nvme_command
) != 64);
167 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl
) != 4096);
168 BUILD_BUG_ON(sizeof(struct nvme_id_ns
) != 4096);
169 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type
) != 64);
170 BUILD_BUG_ON(sizeof(struct nvme_smart_log
) != 512);
174 * Max size of iod being embedded in the request payload
176 #define NVME_INT_PAGES 2
177 #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size)
180 * Will slightly overestimate the number of pages needed. This is OK
181 * as it only leads to a small amount of wasted memory for the lifetime of
184 static int nvme_npages(unsigned size
, struct nvme_dev
*dev
)
186 unsigned nprps
= DIV_ROUND_UP(size
+ dev
->ctrl
.page_size
,
187 dev
->ctrl
.page_size
);
188 return DIV_ROUND_UP(8 * nprps
, PAGE_SIZE
- 8);
191 static unsigned int nvme_iod_alloc_size(struct nvme_dev
*dev
,
192 unsigned int size
, unsigned int nseg
)
194 return sizeof(__le64
*) * nvme_npages(size
, dev
) +
195 sizeof(struct scatterlist
) * nseg
;
198 static unsigned int nvme_cmd_size(struct nvme_dev
*dev
)
200 return sizeof(struct nvme_iod
) +
201 nvme_iod_alloc_size(dev
, NVME_INT_BYTES(dev
), NVME_INT_PAGES
);
204 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx
*hctx
, void *data
,
205 unsigned int hctx_idx
)
207 struct nvme_dev
*dev
= data
;
208 struct nvme_queue
*nvmeq
= dev
->queues
[0];
210 WARN_ON(hctx_idx
!= 0);
211 WARN_ON(dev
->admin_tagset
.tags
[0] != hctx
->tags
);
212 WARN_ON(nvmeq
->tags
);
214 hctx
->driver_data
= nvmeq
;
215 nvmeq
->tags
= &dev
->admin_tagset
.tags
[0];
219 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx
*hctx
, unsigned int hctx_idx
)
221 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
226 static int nvme_admin_init_request(void *data
, struct request
*req
,
227 unsigned int hctx_idx
, unsigned int rq_idx
,
228 unsigned int numa_node
)
230 struct nvme_dev
*dev
= data
;
231 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
232 struct nvme_queue
*nvmeq
= dev
->queues
[0];
239 static int nvme_init_hctx(struct blk_mq_hw_ctx
*hctx
, void *data
,
240 unsigned int hctx_idx
)
242 struct nvme_dev
*dev
= data
;
243 struct nvme_queue
*nvmeq
= dev
->queues
[hctx_idx
+ 1];
246 nvmeq
->tags
= &dev
->tagset
.tags
[hctx_idx
];
248 WARN_ON(dev
->tagset
.tags
[hctx_idx
] != hctx
->tags
);
249 hctx
->driver_data
= nvmeq
;
253 static int nvme_init_request(void *data
, struct request
*req
,
254 unsigned int hctx_idx
, unsigned int rq_idx
,
255 unsigned int numa_node
)
257 struct nvme_dev
*dev
= data
;
258 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
259 struct nvme_queue
*nvmeq
= dev
->queues
[hctx_idx
+ 1];
267 * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
268 * @nvmeq: The queue to use
269 * @cmd: The command to send
271 * Safe to use from interrupt context
273 static void __nvme_submit_cmd(struct nvme_queue
*nvmeq
,
274 struct nvme_command
*cmd
)
276 u16 tail
= nvmeq
->sq_tail
;
278 if (nvmeq
->sq_cmds_io
)
279 memcpy_toio(&nvmeq
->sq_cmds_io
[tail
], cmd
, sizeof(*cmd
));
281 memcpy(&nvmeq
->sq_cmds
[tail
], cmd
, sizeof(*cmd
));
283 if (++tail
== nvmeq
->q_depth
)
285 writel(tail
, nvmeq
->q_db
);
286 nvmeq
->sq_tail
= tail
;
289 static __le64
**iod_list(struct request
*req
)
291 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
292 return (__le64
**)(iod
->sg
+ req
->nr_phys_segments
);
295 static int nvme_init_iod(struct request
*rq
, unsigned size
,
296 struct nvme_dev
*dev
)
298 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(rq
);
299 int nseg
= rq
->nr_phys_segments
;
301 if (nseg
> NVME_INT_PAGES
|| size
> NVME_INT_BYTES(dev
)) {
302 iod
->sg
= kmalloc(nvme_iod_alloc_size(dev
, size
, nseg
), GFP_ATOMIC
);
304 return BLK_MQ_RQ_QUEUE_BUSY
;
306 iod
->sg
= iod
->inline_sg
;
316 static void nvme_free_iod(struct nvme_dev
*dev
, struct request
*req
)
318 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
319 const int last_prp
= dev
->ctrl
.page_size
/ 8 - 1;
321 __le64
**list
= iod_list(req
);
322 dma_addr_t prp_dma
= iod
->first_dma
;
324 nvme_cleanup_cmd(req
);
326 if (iod
->npages
== 0)
327 dma_pool_free(dev
->prp_small_pool
, list
[0], prp_dma
);
328 for (i
= 0; i
< iod
->npages
; i
++) {
329 __le64
*prp_list
= list
[i
];
330 dma_addr_t next_prp_dma
= le64_to_cpu(prp_list
[last_prp
]);
331 dma_pool_free(dev
->prp_page_pool
, prp_list
, prp_dma
);
332 prp_dma
= next_prp_dma
;
335 if (iod
->sg
!= iod
->inline_sg
)
339 #ifdef CONFIG_BLK_DEV_INTEGRITY
340 static void nvme_dif_prep(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
342 if (be32_to_cpu(pi
->ref_tag
) == v
)
343 pi
->ref_tag
= cpu_to_be32(p
);
346 static void nvme_dif_complete(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
348 if (be32_to_cpu(pi
->ref_tag
) == p
)
349 pi
->ref_tag
= cpu_to_be32(v
);
353 * nvme_dif_remap - remaps ref tags to bip seed and physical lba
355 * The virtual start sector is the one that was originally submitted by the
356 * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
357 * start sector may be different. Remap protection information to match the
358 * physical LBA on writes, and back to the original seed on reads.
360 * Type 0 and 3 do not have a ref tag, so no remapping required.
362 static void nvme_dif_remap(struct request
*req
,
363 void (*dif_swap
)(u32 p
, u32 v
, struct t10_pi_tuple
*pi
))
365 struct nvme_ns
*ns
= req
->rq_disk
->private_data
;
366 struct bio_integrity_payload
*bip
;
367 struct t10_pi_tuple
*pi
;
369 u32 i
, nlb
, ts
, phys
, virt
;
371 if (!ns
->pi_type
|| ns
->pi_type
== NVME_NS_DPS_PI_TYPE3
)
374 bip
= bio_integrity(req
->bio
);
378 pmap
= kmap_atomic(bip
->bip_vec
->bv_page
) + bip
->bip_vec
->bv_offset
;
381 virt
= bip_get_seed(bip
);
382 phys
= nvme_block_nr(ns
, blk_rq_pos(req
));
383 nlb
= (blk_rq_bytes(req
) >> ns
->lba_shift
);
384 ts
= ns
->disk
->queue
->integrity
.tuple_size
;
386 for (i
= 0; i
< nlb
; i
++, virt
++, phys
++) {
387 pi
= (struct t10_pi_tuple
*)p
;
388 dif_swap(phys
, virt
, pi
);
393 #else /* CONFIG_BLK_DEV_INTEGRITY */
394 static void nvme_dif_remap(struct request
*req
,
395 void (*dif_swap
)(u32 p
, u32 v
, struct t10_pi_tuple
*pi
))
398 static void nvme_dif_prep(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
401 static void nvme_dif_complete(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
406 static bool nvme_setup_prps(struct nvme_dev
*dev
, struct request
*req
,
409 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
410 struct dma_pool
*pool
;
411 int length
= total_len
;
412 struct scatterlist
*sg
= iod
->sg
;
413 int dma_len
= sg_dma_len(sg
);
414 u64 dma_addr
= sg_dma_address(sg
);
415 u32 page_size
= dev
->ctrl
.page_size
;
416 int offset
= dma_addr
& (page_size
- 1);
418 __le64
**list
= iod_list(req
);
422 length
-= (page_size
- offset
);
426 dma_len
-= (page_size
- offset
);
428 dma_addr
+= (page_size
- offset
);
431 dma_addr
= sg_dma_address(sg
);
432 dma_len
= sg_dma_len(sg
);
435 if (length
<= page_size
) {
436 iod
->first_dma
= dma_addr
;
440 nprps
= DIV_ROUND_UP(length
, page_size
);
441 if (nprps
<= (256 / 8)) {
442 pool
= dev
->prp_small_pool
;
445 pool
= dev
->prp_page_pool
;
449 prp_list
= dma_pool_alloc(pool
, GFP_ATOMIC
, &prp_dma
);
451 iod
->first_dma
= dma_addr
;
456 iod
->first_dma
= prp_dma
;
459 if (i
== page_size
>> 3) {
460 __le64
*old_prp_list
= prp_list
;
461 prp_list
= dma_pool_alloc(pool
, GFP_ATOMIC
, &prp_dma
);
464 list
[iod
->npages
++] = prp_list
;
465 prp_list
[0] = old_prp_list
[i
- 1];
466 old_prp_list
[i
- 1] = cpu_to_le64(prp_dma
);
469 prp_list
[i
++] = cpu_to_le64(dma_addr
);
470 dma_len
-= page_size
;
471 dma_addr
+= page_size
;
479 dma_addr
= sg_dma_address(sg
);
480 dma_len
= sg_dma_len(sg
);
486 static int nvme_map_data(struct nvme_dev
*dev
, struct request
*req
,
487 unsigned size
, struct nvme_command
*cmnd
)
489 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
490 struct request_queue
*q
= req
->q
;
491 enum dma_data_direction dma_dir
= rq_data_dir(req
) ?
492 DMA_TO_DEVICE
: DMA_FROM_DEVICE
;
493 int ret
= BLK_MQ_RQ_QUEUE_ERROR
;
495 sg_init_table(iod
->sg
, req
->nr_phys_segments
);
496 iod
->nents
= blk_rq_map_sg(q
, req
, iod
->sg
);
500 ret
= BLK_MQ_RQ_QUEUE_BUSY
;
501 if (!dma_map_sg(dev
->dev
, iod
->sg
, iod
->nents
, dma_dir
))
504 if (!nvme_setup_prps(dev
, req
, size
))
507 ret
= BLK_MQ_RQ_QUEUE_ERROR
;
508 if (blk_integrity_rq(req
)) {
509 if (blk_rq_count_integrity_sg(q
, req
->bio
) != 1)
512 sg_init_table(&iod
->meta_sg
, 1);
513 if (blk_rq_map_integrity_sg(q
, req
->bio
, &iod
->meta_sg
) != 1)
516 if (rq_data_dir(req
))
517 nvme_dif_remap(req
, nvme_dif_prep
);
519 if (!dma_map_sg(dev
->dev
, &iod
->meta_sg
, 1, dma_dir
))
523 cmnd
->rw
.prp1
= cpu_to_le64(sg_dma_address(iod
->sg
));
524 cmnd
->rw
.prp2
= cpu_to_le64(iod
->first_dma
);
525 if (blk_integrity_rq(req
))
526 cmnd
->rw
.metadata
= cpu_to_le64(sg_dma_address(&iod
->meta_sg
));
527 return BLK_MQ_RQ_QUEUE_OK
;
530 dma_unmap_sg(dev
->dev
, iod
->sg
, iod
->nents
, dma_dir
);
535 static void nvme_unmap_data(struct nvme_dev
*dev
, struct request
*req
)
537 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
538 enum dma_data_direction dma_dir
= rq_data_dir(req
) ?
539 DMA_TO_DEVICE
: DMA_FROM_DEVICE
;
542 dma_unmap_sg(dev
->dev
, iod
->sg
, iod
->nents
, dma_dir
);
543 if (blk_integrity_rq(req
)) {
544 if (!rq_data_dir(req
))
545 nvme_dif_remap(req
, nvme_dif_complete
);
546 dma_unmap_sg(dev
->dev
, &iod
->meta_sg
, 1, dma_dir
);
550 nvme_free_iod(dev
, req
);
554 * NOTE: ns is NULL when called on the admin queue.
556 static int nvme_queue_rq(struct blk_mq_hw_ctx
*hctx
,
557 const struct blk_mq_queue_data
*bd
)
559 struct nvme_ns
*ns
= hctx
->queue
->queuedata
;
560 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
561 struct nvme_dev
*dev
= nvmeq
->dev
;
562 struct request
*req
= bd
->rq
;
563 struct nvme_command cmnd
;
565 int ret
= BLK_MQ_RQ_QUEUE_OK
;
568 * If formated with metadata, require the block layer provide a buffer
569 * unless this namespace is formated such that the metadata can be
570 * stripped/generated by the controller with PRACT=1.
572 if (ns
&& ns
->ms
&& !blk_integrity_rq(req
)) {
573 if (!(ns
->pi_type
&& ns
->ms
== 8) &&
574 req
->cmd_type
!= REQ_TYPE_DRV_PRIV
) {
575 blk_mq_end_request(req
, -EFAULT
);
576 return BLK_MQ_RQ_QUEUE_OK
;
580 map_len
= nvme_map_len(req
);
581 ret
= nvme_init_iod(req
, map_len
, dev
);
585 ret
= nvme_setup_cmd(ns
, req
, &cmnd
);
589 if (req
->nr_phys_segments
)
590 ret
= nvme_map_data(dev
, req
, map_len
, &cmnd
);
595 cmnd
.common
.command_id
= req
->tag
;
596 blk_mq_start_request(req
);
598 spin_lock_irq(&nvmeq
->q_lock
);
599 if (unlikely(nvmeq
->cq_vector
< 0)) {
600 if (ns
&& !test_bit(NVME_NS_DEAD
, &ns
->flags
))
601 ret
= BLK_MQ_RQ_QUEUE_BUSY
;
603 ret
= BLK_MQ_RQ_QUEUE_ERROR
;
604 spin_unlock_irq(&nvmeq
->q_lock
);
607 __nvme_submit_cmd(nvmeq
, &cmnd
);
608 nvme_process_cq(nvmeq
);
609 spin_unlock_irq(&nvmeq
->q_lock
);
610 return BLK_MQ_RQ_QUEUE_OK
;
612 nvme_free_iod(dev
, req
);
616 static void nvme_complete_rq(struct request
*req
)
618 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
619 struct nvme_dev
*dev
= iod
->nvmeq
->dev
;
622 nvme_unmap_data(dev
, req
);
624 if (unlikely(req
->errors
)) {
625 if (nvme_req_needs_retry(req
, req
->errors
)) {
626 nvme_requeue_req(req
);
630 if (req
->cmd_type
== REQ_TYPE_DRV_PRIV
)
633 error
= nvme_error_status(req
->errors
);
636 if (unlikely(iod
->aborted
)) {
637 dev_warn(dev
->ctrl
.device
,
638 "completing aborted command with status: %04x\n",
642 blk_mq_end_request(req
, error
);
645 /* We read the CQE phase first to check if the rest of the entry is valid */
646 static inline bool nvme_cqe_valid(struct nvme_queue
*nvmeq
, u16 head
,
649 return (le16_to_cpu(nvmeq
->cqes
[head
].status
) & 1) == phase
;
652 static void __nvme_process_cq(struct nvme_queue
*nvmeq
, unsigned int *tag
)
656 head
= nvmeq
->cq_head
;
657 phase
= nvmeq
->cq_phase
;
659 while (nvme_cqe_valid(nvmeq
, head
, phase
)) {
660 struct nvme_completion cqe
= nvmeq
->cqes
[head
];
663 if (++head
== nvmeq
->q_depth
) {
668 if (tag
&& *tag
== cqe
.command_id
)
671 if (unlikely(cqe
.command_id
>= nvmeq
->q_depth
)) {
672 dev_warn(nvmeq
->dev
->ctrl
.device
,
673 "invalid id %d completed on queue %d\n",
674 cqe
.command_id
, le16_to_cpu(cqe
.sq_id
));
679 * AEN requests are special as they don't time out and can
680 * survive any kind of queue freeze and often don't respond to
681 * aborts. We don't even bother to allocate a struct request
682 * for them but rather special case them here.
684 if (unlikely(nvmeq
->qid
== 0 &&
685 cqe
.command_id
>= NVME_AQ_BLKMQ_DEPTH
)) {
686 nvme_complete_async_event(&nvmeq
->dev
->ctrl
, &cqe
);
690 req
= blk_mq_tag_to_rq(*nvmeq
->tags
, cqe
.command_id
);
691 if (req
->cmd_type
== REQ_TYPE_DRV_PRIV
&& req
->special
)
692 memcpy(req
->special
, &cqe
, sizeof(cqe
));
693 blk_mq_complete_request(req
, le16_to_cpu(cqe
.status
) >> 1);
697 /* If the controller ignores the cq head doorbell and continuously
698 * writes to the queue, it is theoretically possible to wrap around
699 * the queue twice and mistakenly return IRQ_NONE. Linux only
700 * requires that 0.1% of your interrupts are handled, so this isn't
703 if (head
== nvmeq
->cq_head
&& phase
== nvmeq
->cq_phase
)
706 if (likely(nvmeq
->cq_vector
>= 0))
707 writel(head
, nvmeq
->q_db
+ nvmeq
->dev
->db_stride
);
708 nvmeq
->cq_head
= head
;
709 nvmeq
->cq_phase
= phase
;
714 static void nvme_process_cq(struct nvme_queue
*nvmeq
)
716 __nvme_process_cq(nvmeq
, NULL
);
719 static irqreturn_t
nvme_irq(int irq
, void *data
)
722 struct nvme_queue
*nvmeq
= data
;
723 spin_lock(&nvmeq
->q_lock
);
724 nvme_process_cq(nvmeq
);
725 result
= nvmeq
->cqe_seen
? IRQ_HANDLED
: IRQ_NONE
;
727 spin_unlock(&nvmeq
->q_lock
);
731 static irqreturn_t
nvme_irq_check(int irq
, void *data
)
733 struct nvme_queue
*nvmeq
= data
;
734 if (nvme_cqe_valid(nvmeq
, nvmeq
->cq_head
, nvmeq
->cq_phase
))
735 return IRQ_WAKE_THREAD
;
739 static int nvme_poll(struct blk_mq_hw_ctx
*hctx
, unsigned int tag
)
741 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
743 if (nvme_cqe_valid(nvmeq
, nvmeq
->cq_head
, nvmeq
->cq_phase
)) {
744 spin_lock_irq(&nvmeq
->q_lock
);
745 __nvme_process_cq(nvmeq
, &tag
);
746 spin_unlock_irq(&nvmeq
->q_lock
);
755 static void nvme_pci_submit_async_event(struct nvme_ctrl
*ctrl
, int aer_idx
)
757 struct nvme_dev
*dev
= to_nvme_dev(ctrl
);
758 struct nvme_queue
*nvmeq
= dev
->queues
[0];
759 struct nvme_command c
;
761 memset(&c
, 0, sizeof(c
));
762 c
.common
.opcode
= nvme_admin_async_event
;
763 c
.common
.command_id
= NVME_AQ_BLKMQ_DEPTH
+ aer_idx
;
765 spin_lock_irq(&nvmeq
->q_lock
);
766 __nvme_submit_cmd(nvmeq
, &c
);
767 spin_unlock_irq(&nvmeq
->q_lock
);
770 static int adapter_delete_queue(struct nvme_dev
*dev
, u8 opcode
, u16 id
)
772 struct nvme_command c
;
774 memset(&c
, 0, sizeof(c
));
775 c
.delete_queue
.opcode
= opcode
;
776 c
.delete_queue
.qid
= cpu_to_le16(id
);
778 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
781 static int adapter_alloc_cq(struct nvme_dev
*dev
, u16 qid
,
782 struct nvme_queue
*nvmeq
)
784 struct nvme_command c
;
785 int flags
= NVME_QUEUE_PHYS_CONTIG
| NVME_CQ_IRQ_ENABLED
;
788 * Note: we (ab)use the fact the the prp fields survive if no data
789 * is attached to the request.
791 memset(&c
, 0, sizeof(c
));
792 c
.create_cq
.opcode
= nvme_admin_create_cq
;
793 c
.create_cq
.prp1
= cpu_to_le64(nvmeq
->cq_dma_addr
);
794 c
.create_cq
.cqid
= cpu_to_le16(qid
);
795 c
.create_cq
.qsize
= cpu_to_le16(nvmeq
->q_depth
- 1);
796 c
.create_cq
.cq_flags
= cpu_to_le16(flags
);
797 c
.create_cq
.irq_vector
= cpu_to_le16(nvmeq
->cq_vector
);
799 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
802 static int adapter_alloc_sq(struct nvme_dev
*dev
, u16 qid
,
803 struct nvme_queue
*nvmeq
)
805 struct nvme_command c
;
806 int flags
= NVME_QUEUE_PHYS_CONTIG
| NVME_SQ_PRIO_MEDIUM
;
809 * Note: we (ab)use the fact the the prp fields survive if no data
810 * is attached to the request.
812 memset(&c
, 0, sizeof(c
));
813 c
.create_sq
.opcode
= nvme_admin_create_sq
;
814 c
.create_sq
.prp1
= cpu_to_le64(nvmeq
->sq_dma_addr
);
815 c
.create_sq
.sqid
= cpu_to_le16(qid
);
816 c
.create_sq
.qsize
= cpu_to_le16(nvmeq
->q_depth
- 1);
817 c
.create_sq
.sq_flags
= cpu_to_le16(flags
);
818 c
.create_sq
.cqid
= cpu_to_le16(qid
);
820 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
823 static int adapter_delete_cq(struct nvme_dev
*dev
, u16 cqid
)
825 return adapter_delete_queue(dev
, nvme_admin_delete_cq
, cqid
);
828 static int adapter_delete_sq(struct nvme_dev
*dev
, u16 sqid
)
830 return adapter_delete_queue(dev
, nvme_admin_delete_sq
, sqid
);
833 static void abort_endio(struct request
*req
, int error
)
835 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
836 struct nvme_queue
*nvmeq
= iod
->nvmeq
;
837 u16 status
= req
->errors
;
839 dev_warn(nvmeq
->dev
->ctrl
.device
, "Abort status: 0x%x", status
);
840 atomic_inc(&nvmeq
->dev
->ctrl
.abort_limit
);
841 blk_mq_free_request(req
);
844 static enum blk_eh_timer_return
nvme_timeout(struct request
*req
, bool reserved
)
846 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
847 struct nvme_queue
*nvmeq
= iod
->nvmeq
;
848 struct nvme_dev
*dev
= nvmeq
->dev
;
849 struct request
*abort_req
;
850 struct nvme_command cmd
;
853 * Shutdown immediately if controller times out while starting. The
854 * reset work will see the pci device disabled when it gets the forced
855 * cancellation error. All outstanding requests are completed on
856 * shutdown, so we return BLK_EH_HANDLED.
858 if (dev
->ctrl
.state
== NVME_CTRL_RESETTING
) {
859 dev_warn(dev
->ctrl
.device
,
860 "I/O %d QID %d timeout, disable controller\n",
861 req
->tag
, nvmeq
->qid
);
862 nvme_dev_disable(dev
, false);
863 req
->errors
= NVME_SC_CANCELLED
;
864 return BLK_EH_HANDLED
;
868 * Shutdown the controller immediately and schedule a reset if the
869 * command was already aborted once before and still hasn't been
870 * returned to the driver, or if this is the admin queue.
872 if (!nvmeq
->qid
|| iod
->aborted
) {
873 dev_warn(dev
->ctrl
.device
,
874 "I/O %d QID %d timeout, reset controller\n",
875 req
->tag
, nvmeq
->qid
);
876 nvme_dev_disable(dev
, false);
877 queue_work(nvme_workq
, &dev
->reset_work
);
880 * Mark the request as handled, since the inline shutdown
881 * forces all outstanding requests to complete.
883 req
->errors
= NVME_SC_CANCELLED
;
884 return BLK_EH_HANDLED
;
889 if (atomic_dec_return(&dev
->ctrl
.abort_limit
) < 0) {
890 atomic_inc(&dev
->ctrl
.abort_limit
);
891 return BLK_EH_RESET_TIMER
;
894 memset(&cmd
, 0, sizeof(cmd
));
895 cmd
.abort
.opcode
= nvme_admin_abort_cmd
;
896 cmd
.abort
.cid
= req
->tag
;
897 cmd
.abort
.sqid
= cpu_to_le16(nvmeq
->qid
);
899 dev_warn(nvmeq
->dev
->ctrl
.device
,
900 "I/O %d QID %d timeout, aborting\n",
901 req
->tag
, nvmeq
->qid
);
903 abort_req
= nvme_alloc_request(dev
->ctrl
.admin_q
, &cmd
,
905 if (IS_ERR(abort_req
)) {
906 atomic_inc(&dev
->ctrl
.abort_limit
);
907 return BLK_EH_RESET_TIMER
;
910 abort_req
->timeout
= ADMIN_TIMEOUT
;
911 abort_req
->end_io_data
= NULL
;
912 blk_execute_rq_nowait(abort_req
->q
, NULL
, abort_req
, 0, abort_endio
);
915 * The aborted req will be completed on receiving the abort req.
916 * We enable the timer again. If hit twice, it'll cause a device reset,
917 * as the device then is in a faulty state.
919 return BLK_EH_RESET_TIMER
;
922 static void nvme_cancel_io(struct request
*req
, void *data
, bool reserved
)
926 if (!blk_mq_request_started(req
))
929 dev_dbg_ratelimited(((struct nvme_dev
*) data
)->ctrl
.device
,
930 "Cancelling I/O %d", req
->tag
);
932 status
= NVME_SC_ABORT_REQ
;
933 if (blk_queue_dying(req
->q
))
934 status
|= NVME_SC_DNR
;
935 blk_mq_complete_request(req
, status
);
938 static void nvme_free_queue(struct nvme_queue
*nvmeq
)
940 dma_free_coherent(nvmeq
->q_dmadev
, CQ_SIZE(nvmeq
->q_depth
),
941 (void *)nvmeq
->cqes
, nvmeq
->cq_dma_addr
);
943 dma_free_coherent(nvmeq
->q_dmadev
, SQ_SIZE(nvmeq
->q_depth
),
944 nvmeq
->sq_cmds
, nvmeq
->sq_dma_addr
);
948 static void nvme_free_queues(struct nvme_dev
*dev
, int lowest
)
952 for (i
= dev
->queue_count
- 1; i
>= lowest
; i
--) {
953 struct nvme_queue
*nvmeq
= dev
->queues
[i
];
955 dev
->queues
[i
] = NULL
;
956 nvme_free_queue(nvmeq
);
961 * nvme_suspend_queue - put queue into suspended state
962 * @nvmeq - queue to suspend
964 static int nvme_suspend_queue(struct nvme_queue
*nvmeq
)
968 spin_lock_irq(&nvmeq
->q_lock
);
969 if (nvmeq
->cq_vector
== -1) {
970 spin_unlock_irq(&nvmeq
->q_lock
);
973 vector
= nvmeq
->dev
->entry
[nvmeq
->cq_vector
].vector
;
974 nvmeq
->dev
->online_queues
--;
975 nvmeq
->cq_vector
= -1;
976 spin_unlock_irq(&nvmeq
->q_lock
);
978 if (!nvmeq
->qid
&& nvmeq
->dev
->ctrl
.admin_q
)
979 blk_mq_stop_hw_queues(nvmeq
->dev
->ctrl
.admin_q
);
981 irq_set_affinity_hint(vector
, NULL
);
982 free_irq(vector
, nvmeq
);
987 static void nvme_disable_admin_queue(struct nvme_dev
*dev
, bool shutdown
)
989 struct nvme_queue
*nvmeq
= dev
->queues
[0];
993 if (nvme_suspend_queue(nvmeq
))
997 nvme_shutdown_ctrl(&dev
->ctrl
);
999 nvme_disable_ctrl(&dev
->ctrl
, lo_hi_readq(
1000 dev
->bar
+ NVME_REG_CAP
));
1002 spin_lock_irq(&nvmeq
->q_lock
);
1003 nvme_process_cq(nvmeq
);
1004 spin_unlock_irq(&nvmeq
->q_lock
);
1007 static int nvme_cmb_qdepth(struct nvme_dev
*dev
, int nr_io_queues
,
1010 int q_depth
= dev
->q_depth
;
1011 unsigned q_size_aligned
= roundup(q_depth
* entry_size
,
1012 dev
->ctrl
.page_size
);
1014 if (q_size_aligned
* nr_io_queues
> dev
->cmb_size
) {
1015 u64 mem_per_q
= div_u64(dev
->cmb_size
, nr_io_queues
);
1016 mem_per_q
= round_down(mem_per_q
, dev
->ctrl
.page_size
);
1017 q_depth
= div_u64(mem_per_q
, entry_size
);
1020 * Ensure the reduced q_depth is above some threshold where it
1021 * would be better to map queues in system memory with the
1031 static int nvme_alloc_sq_cmds(struct nvme_dev
*dev
, struct nvme_queue
*nvmeq
,
1034 if (qid
&& dev
->cmb
&& use_cmb_sqes
&& NVME_CMB_SQS(dev
->cmbsz
)) {
1035 unsigned offset
= (qid
- 1) * roundup(SQ_SIZE(depth
),
1036 dev
->ctrl
.page_size
);
1037 nvmeq
->sq_dma_addr
= dev
->cmb_dma_addr
+ offset
;
1038 nvmeq
->sq_cmds_io
= dev
->cmb
+ offset
;
1040 nvmeq
->sq_cmds
= dma_alloc_coherent(dev
->dev
, SQ_SIZE(depth
),
1041 &nvmeq
->sq_dma_addr
, GFP_KERNEL
);
1042 if (!nvmeq
->sq_cmds
)
1049 static struct nvme_queue
*nvme_alloc_queue(struct nvme_dev
*dev
, int qid
,
1052 struct nvme_queue
*nvmeq
= kzalloc(sizeof(*nvmeq
), GFP_KERNEL
);
1056 nvmeq
->cqes
= dma_zalloc_coherent(dev
->dev
, CQ_SIZE(depth
),
1057 &nvmeq
->cq_dma_addr
, GFP_KERNEL
);
1061 if (nvme_alloc_sq_cmds(dev
, nvmeq
, qid
, depth
))
1064 nvmeq
->q_dmadev
= dev
->dev
;
1066 snprintf(nvmeq
->irqname
, sizeof(nvmeq
->irqname
), "nvme%dq%d",
1067 dev
->ctrl
.instance
, qid
);
1068 spin_lock_init(&nvmeq
->q_lock
);
1070 nvmeq
->cq_phase
= 1;
1071 nvmeq
->q_db
= &dev
->dbs
[qid
* 2 * dev
->db_stride
];
1072 nvmeq
->q_depth
= depth
;
1074 nvmeq
->cq_vector
= -1;
1075 dev
->queues
[qid
] = nvmeq
;
1081 dma_free_coherent(dev
->dev
, CQ_SIZE(depth
), (void *)nvmeq
->cqes
,
1082 nvmeq
->cq_dma_addr
);
1088 static int queue_request_irq(struct nvme_dev
*dev
, struct nvme_queue
*nvmeq
,
1091 if (use_threaded_interrupts
)
1092 return request_threaded_irq(dev
->entry
[nvmeq
->cq_vector
].vector
,
1093 nvme_irq_check
, nvme_irq
, IRQF_SHARED
,
1095 return request_irq(dev
->entry
[nvmeq
->cq_vector
].vector
, nvme_irq
,
1096 IRQF_SHARED
, name
, nvmeq
);
1099 static void nvme_init_queue(struct nvme_queue
*nvmeq
, u16 qid
)
1101 struct nvme_dev
*dev
= nvmeq
->dev
;
1103 spin_lock_irq(&nvmeq
->q_lock
);
1106 nvmeq
->cq_phase
= 1;
1107 nvmeq
->q_db
= &dev
->dbs
[qid
* 2 * dev
->db_stride
];
1108 memset((void *)nvmeq
->cqes
, 0, CQ_SIZE(nvmeq
->q_depth
));
1109 dev
->online_queues
++;
1110 spin_unlock_irq(&nvmeq
->q_lock
);
1113 static int nvme_create_queue(struct nvme_queue
*nvmeq
, int qid
)
1115 struct nvme_dev
*dev
= nvmeq
->dev
;
1118 nvmeq
->cq_vector
= qid
- 1;
1119 result
= adapter_alloc_cq(dev
, qid
, nvmeq
);
1123 result
= adapter_alloc_sq(dev
, qid
, nvmeq
);
1127 result
= queue_request_irq(dev
, nvmeq
, nvmeq
->irqname
);
1131 nvme_init_queue(nvmeq
, qid
);
1135 adapter_delete_sq(dev
, qid
);
1137 adapter_delete_cq(dev
, qid
);
1141 static struct blk_mq_ops nvme_mq_admin_ops
= {
1142 .queue_rq
= nvme_queue_rq
,
1143 .complete
= nvme_complete_rq
,
1144 .map_queue
= blk_mq_map_queue
,
1145 .init_hctx
= nvme_admin_init_hctx
,
1146 .exit_hctx
= nvme_admin_exit_hctx
,
1147 .init_request
= nvme_admin_init_request
,
1148 .timeout
= nvme_timeout
,
1151 static struct blk_mq_ops nvme_mq_ops
= {
1152 .queue_rq
= nvme_queue_rq
,
1153 .complete
= nvme_complete_rq
,
1154 .map_queue
= blk_mq_map_queue
,
1155 .init_hctx
= nvme_init_hctx
,
1156 .init_request
= nvme_init_request
,
1157 .timeout
= nvme_timeout
,
1161 static void nvme_dev_remove_admin(struct nvme_dev
*dev
)
1163 if (dev
->ctrl
.admin_q
&& !blk_queue_dying(dev
->ctrl
.admin_q
)) {
1165 * If the controller was reset during removal, it's possible
1166 * user requests may be waiting on a stopped queue. Start the
1167 * queue to flush these to completion.
1169 blk_mq_start_stopped_hw_queues(dev
->ctrl
.admin_q
, true);
1170 blk_cleanup_queue(dev
->ctrl
.admin_q
);
1171 blk_mq_free_tag_set(&dev
->admin_tagset
);
1175 static int nvme_alloc_admin_tags(struct nvme_dev
*dev
)
1177 if (!dev
->ctrl
.admin_q
) {
1178 dev
->admin_tagset
.ops
= &nvme_mq_admin_ops
;
1179 dev
->admin_tagset
.nr_hw_queues
= 1;
1182 * Subtract one to leave an empty queue entry for 'Full Queue'
1183 * condition. See NVM-Express 1.2 specification, section 4.1.2.
1185 dev
->admin_tagset
.queue_depth
= NVME_AQ_BLKMQ_DEPTH
- 1;
1186 dev
->admin_tagset
.timeout
= ADMIN_TIMEOUT
;
1187 dev
->admin_tagset
.numa_node
= dev_to_node(dev
->dev
);
1188 dev
->admin_tagset
.cmd_size
= nvme_cmd_size(dev
);
1189 dev
->admin_tagset
.driver_data
= dev
;
1191 if (blk_mq_alloc_tag_set(&dev
->admin_tagset
))
1194 dev
->ctrl
.admin_q
= blk_mq_init_queue(&dev
->admin_tagset
);
1195 if (IS_ERR(dev
->ctrl
.admin_q
)) {
1196 blk_mq_free_tag_set(&dev
->admin_tagset
);
1199 if (!blk_get_queue(dev
->ctrl
.admin_q
)) {
1200 nvme_dev_remove_admin(dev
);
1201 dev
->ctrl
.admin_q
= NULL
;
1205 blk_mq_start_stopped_hw_queues(dev
->ctrl
.admin_q
, true);
1210 static int nvme_configure_admin_queue(struct nvme_dev
*dev
)
1214 u64 cap
= lo_hi_readq(dev
->bar
+ NVME_REG_CAP
);
1215 struct nvme_queue
*nvmeq
;
1217 dev
->subsystem
= readl(dev
->bar
+ NVME_REG_VS
) >= NVME_VS(1, 1) ?
1218 NVME_CAP_NSSRC(cap
) : 0;
1220 if (dev
->subsystem
&&
1221 (readl(dev
->bar
+ NVME_REG_CSTS
) & NVME_CSTS_NSSRO
))
1222 writel(NVME_CSTS_NSSRO
, dev
->bar
+ NVME_REG_CSTS
);
1224 result
= nvme_disable_ctrl(&dev
->ctrl
, cap
);
1228 nvmeq
= dev
->queues
[0];
1230 nvmeq
= nvme_alloc_queue(dev
, 0, NVME_AQ_DEPTH
);
1235 aqa
= nvmeq
->q_depth
- 1;
1238 writel(aqa
, dev
->bar
+ NVME_REG_AQA
);
1239 lo_hi_writeq(nvmeq
->sq_dma_addr
, dev
->bar
+ NVME_REG_ASQ
);
1240 lo_hi_writeq(nvmeq
->cq_dma_addr
, dev
->bar
+ NVME_REG_ACQ
);
1242 result
= nvme_enable_ctrl(&dev
->ctrl
, cap
);
1246 nvmeq
->cq_vector
= 0;
1247 result
= queue_request_irq(dev
, nvmeq
, nvmeq
->irqname
);
1249 nvmeq
->cq_vector
= -1;
1256 nvme_free_queues(dev
, 0);
1260 static bool nvme_should_reset(struct nvme_dev
*dev
, u32 csts
)
1263 /* If true, indicates loss of adapter communication, possibly by a
1264 * NVMe Subsystem reset.
1266 bool nssro
= dev
->subsystem
&& (csts
& NVME_CSTS_NSSRO
);
1268 /* If there is a reset ongoing, we shouldn't reset again. */
1269 if (work_busy(&dev
->reset_work
))
1272 /* We shouldn't reset unless the controller is on fatal error state
1273 * _or_ if we lost the communication with it.
1275 if (!(csts
& NVME_CSTS_CFS
) && !nssro
)
1278 /* If PCI error recovery process is happening, we cannot reset or
1279 * the recovery mechanism will surely fail.
1281 if (pci_channel_offline(to_pci_dev(dev
->dev
)))
1287 static void nvme_watchdog_timer(unsigned long data
)
1289 struct nvme_dev
*dev
= (struct nvme_dev
*)data
;
1290 u32 csts
= readl(dev
->bar
+ NVME_REG_CSTS
);
1292 /* Skip controllers under certain specific conditions. */
1293 if (nvme_should_reset(dev
, csts
)) {
1294 if (queue_work(nvme_workq
, &dev
->reset_work
))
1296 "Failed status: 0x%x, reset controller.\n",
1301 mod_timer(&dev
->watchdog_timer
, round_jiffies(jiffies
+ HZ
));
1304 static int nvme_create_io_queues(struct nvme_dev
*dev
)
1309 for (i
= dev
->queue_count
; i
<= dev
->max_qid
; i
++) {
1310 if (!nvme_alloc_queue(dev
, i
, dev
->q_depth
)) {
1316 max
= min(dev
->max_qid
, dev
->queue_count
- 1);
1317 for (i
= dev
->online_queues
; i
<= max
; i
++) {
1318 ret
= nvme_create_queue(dev
->queues
[i
], i
);
1320 nvme_free_queues(dev
, i
);
1326 * Ignore failing Create SQ/CQ commands, we can continue with less
1327 * than the desired aount of queues, and even a controller without
1328 * I/O queues an still be used to issue admin commands. This might
1329 * be useful to upgrade a buggy firmware for example.
1331 return ret
>= 0 ? 0 : ret
;
1334 static void __iomem
*nvme_map_cmb(struct nvme_dev
*dev
)
1336 u64 szu
, size
, offset
;
1338 resource_size_t bar_size
;
1339 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1341 dma_addr_t dma_addr
;
1346 dev
->cmbsz
= readl(dev
->bar
+ NVME_REG_CMBSZ
);
1347 if (!(NVME_CMB_SZ(dev
->cmbsz
)))
1350 cmbloc
= readl(dev
->bar
+ NVME_REG_CMBLOC
);
1352 szu
= (u64
)1 << (12 + 4 * NVME_CMB_SZU(dev
->cmbsz
));
1353 size
= szu
* NVME_CMB_SZ(dev
->cmbsz
);
1354 offset
= szu
* NVME_CMB_OFST(cmbloc
);
1355 bar_size
= pci_resource_len(pdev
, NVME_CMB_BIR(cmbloc
));
1357 if (offset
> bar_size
)
1361 * Controllers may support a CMB size larger than their BAR,
1362 * for example, due to being behind a bridge. Reduce the CMB to
1363 * the reported size of the BAR
1365 if (size
> bar_size
- offset
)
1366 size
= bar_size
- offset
;
1368 dma_addr
= pci_resource_start(pdev
, NVME_CMB_BIR(cmbloc
)) + offset
;
1369 cmb
= ioremap_wc(dma_addr
, size
);
1373 dev
->cmb_dma_addr
= dma_addr
;
1374 dev
->cmb_size
= size
;
1378 static inline void nvme_release_cmb(struct nvme_dev
*dev
)
1386 static size_t db_bar_size(struct nvme_dev
*dev
, unsigned nr_io_queues
)
1388 return 4096 + ((nr_io_queues
+ 1) * 8 * dev
->db_stride
);
1391 static int nvme_setup_io_queues(struct nvme_dev
*dev
)
1393 struct nvme_queue
*adminq
= dev
->queues
[0];
1394 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1395 int result
, i
, vecs
, nr_io_queues
, size
;
1397 nr_io_queues
= num_online_cpus();
1398 result
= nvme_set_queue_count(&dev
->ctrl
, &nr_io_queues
);
1403 * Degraded controllers might return an error when setting the queue
1404 * count. We still want to be able to bring them online and offer
1405 * access to the admin queue, as that might be only way to fix them up.
1408 dev_err(dev
->ctrl
.device
,
1409 "Could not set queue count (%d)\n", result
);
1413 if (dev
->cmb
&& NVME_CMB_SQS(dev
->cmbsz
)) {
1414 result
= nvme_cmb_qdepth(dev
, nr_io_queues
,
1415 sizeof(struct nvme_command
));
1417 dev
->q_depth
= result
;
1419 nvme_release_cmb(dev
);
1422 size
= db_bar_size(dev
, nr_io_queues
);
1426 dev
->bar
= ioremap(pci_resource_start(pdev
, 0), size
);
1429 if (!--nr_io_queues
)
1431 size
= db_bar_size(dev
, nr_io_queues
);
1433 dev
->dbs
= dev
->bar
+ 4096;
1434 adminq
->q_db
= dev
->dbs
;
1437 /* Deregister the admin queue's interrupt */
1438 free_irq(dev
->entry
[0].vector
, adminq
);
1441 * If we enable msix early due to not intx, disable it again before
1442 * setting up the full range we need.
1444 if (pdev
->msi_enabled
)
1445 pci_disable_msi(pdev
);
1446 else if (pdev
->msix_enabled
)
1447 pci_disable_msix(pdev
);
1449 for (i
= 0; i
< nr_io_queues
; i
++)
1450 dev
->entry
[i
].entry
= i
;
1451 vecs
= pci_enable_msix_range(pdev
, dev
->entry
, 1, nr_io_queues
);
1453 vecs
= pci_enable_msi_range(pdev
, 1, min(nr_io_queues
, 32));
1457 for (i
= 0; i
< vecs
; i
++)
1458 dev
->entry
[i
].vector
= i
+ pdev
->irq
;
1463 * Should investigate if there's a performance win from allocating
1464 * more queues than interrupt vectors; it might allow the submission
1465 * path to scale better, even if the receive path is limited by the
1466 * number of interrupts.
1468 nr_io_queues
= vecs
;
1469 dev
->max_qid
= nr_io_queues
;
1471 result
= queue_request_irq(dev
, adminq
, adminq
->irqname
);
1473 adminq
->cq_vector
= -1;
1476 return nvme_create_io_queues(dev
);
1479 nvme_free_queues(dev
, 1);
1483 static void nvme_pci_post_scan(struct nvme_ctrl
*ctrl
)
1485 struct nvme_dev
*dev
= to_nvme_dev(ctrl
);
1486 struct nvme_queue
*nvmeq
;
1489 for (i
= 0; i
< dev
->online_queues
; i
++) {
1490 nvmeq
= dev
->queues
[i
];
1492 if (!nvmeq
->tags
|| !(*nvmeq
->tags
))
1495 irq_set_affinity_hint(dev
->entry
[nvmeq
->cq_vector
].vector
,
1496 blk_mq_tags_cpumask(*nvmeq
->tags
));
1500 static void nvme_del_queue_end(struct request
*req
, int error
)
1502 struct nvme_queue
*nvmeq
= req
->end_io_data
;
1504 blk_mq_free_request(req
);
1505 complete(&nvmeq
->dev
->ioq_wait
);
1508 static void nvme_del_cq_end(struct request
*req
, int error
)
1510 struct nvme_queue
*nvmeq
= req
->end_io_data
;
1513 unsigned long flags
;
1516 * We might be called with the AQ q_lock held
1517 * and the I/O queue q_lock should always
1518 * nest inside the AQ one.
1520 spin_lock_irqsave_nested(&nvmeq
->q_lock
, flags
,
1521 SINGLE_DEPTH_NESTING
);
1522 nvme_process_cq(nvmeq
);
1523 spin_unlock_irqrestore(&nvmeq
->q_lock
, flags
);
1526 nvme_del_queue_end(req
, error
);
1529 static int nvme_delete_queue(struct nvme_queue
*nvmeq
, u8 opcode
)
1531 struct request_queue
*q
= nvmeq
->dev
->ctrl
.admin_q
;
1532 struct request
*req
;
1533 struct nvme_command cmd
;
1535 memset(&cmd
, 0, sizeof(cmd
));
1536 cmd
.delete_queue
.opcode
= opcode
;
1537 cmd
.delete_queue
.qid
= cpu_to_le16(nvmeq
->qid
);
1539 req
= nvme_alloc_request(q
, &cmd
, BLK_MQ_REQ_NOWAIT
);
1541 return PTR_ERR(req
);
1543 req
->timeout
= ADMIN_TIMEOUT
;
1544 req
->end_io_data
= nvmeq
;
1546 blk_execute_rq_nowait(q
, NULL
, req
, false,
1547 opcode
== nvme_admin_delete_cq
?
1548 nvme_del_cq_end
: nvme_del_queue_end
);
1552 static void nvme_disable_io_queues(struct nvme_dev
*dev
)
1554 int pass
, queues
= dev
->online_queues
- 1;
1555 unsigned long timeout
;
1556 u8 opcode
= nvme_admin_delete_sq
;
1558 for (pass
= 0; pass
< 2; pass
++) {
1559 int sent
= 0, i
= queues
;
1561 reinit_completion(&dev
->ioq_wait
);
1563 timeout
= ADMIN_TIMEOUT
;
1564 for (; i
> 0; i
--) {
1565 struct nvme_queue
*nvmeq
= dev
->queues
[i
];
1568 nvme_suspend_queue(nvmeq
);
1569 if (nvme_delete_queue(nvmeq
, opcode
))
1574 timeout
= wait_for_completion_io_timeout(&dev
->ioq_wait
, timeout
);
1580 opcode
= nvme_admin_delete_cq
;
1585 * Return: error value if an error occurred setting up the queues or calling
1586 * Identify Device. 0 if these succeeded, even if adding some of the
1587 * namespaces failed. At the moment, these failures are silent. TBD which
1588 * failures should be reported.
1590 static int nvme_dev_add(struct nvme_dev
*dev
)
1592 if (!dev
->ctrl
.tagset
) {
1593 dev
->tagset
.ops
= &nvme_mq_ops
;
1594 dev
->tagset
.nr_hw_queues
= dev
->online_queues
- 1;
1595 dev
->tagset
.timeout
= NVME_IO_TIMEOUT
;
1596 dev
->tagset
.numa_node
= dev_to_node(dev
->dev
);
1597 dev
->tagset
.queue_depth
=
1598 min_t(int, dev
->q_depth
, BLK_MQ_MAX_DEPTH
) - 1;
1599 dev
->tagset
.cmd_size
= nvme_cmd_size(dev
);
1600 dev
->tagset
.flags
= BLK_MQ_F_SHOULD_MERGE
;
1601 dev
->tagset
.driver_data
= dev
;
1603 if (blk_mq_alloc_tag_set(&dev
->tagset
))
1605 dev
->ctrl
.tagset
= &dev
->tagset
;
1607 blk_mq_update_nr_hw_queues(&dev
->tagset
, dev
->online_queues
- 1);
1609 /* Free previously allocated queues that are no longer usable */
1610 nvme_free_queues(dev
, dev
->online_queues
);
1616 static int nvme_pci_enable(struct nvme_dev
*dev
)
1619 int result
= -ENOMEM
;
1620 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1622 if (pci_enable_device_mem(pdev
))
1625 pci_set_master(pdev
);
1627 if (dma_set_mask_and_coherent(dev
->dev
, DMA_BIT_MASK(64)) &&
1628 dma_set_mask_and_coherent(dev
->dev
, DMA_BIT_MASK(32)))
1631 if (readl(dev
->bar
+ NVME_REG_CSTS
) == -1) {
1637 * Some devices and/or platforms don't advertise or work with INTx
1638 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
1639 * adjust this later.
1641 if (pci_enable_msix(pdev
, dev
->entry
, 1)) {
1642 pci_enable_msi(pdev
);
1643 dev
->entry
[0].vector
= pdev
->irq
;
1646 if (!dev
->entry
[0].vector
) {
1651 cap
= lo_hi_readq(dev
->bar
+ NVME_REG_CAP
);
1653 dev
->q_depth
= min_t(int, NVME_CAP_MQES(cap
) + 1, NVME_Q_DEPTH
);
1654 dev
->db_stride
= 1 << NVME_CAP_STRIDE(cap
);
1655 dev
->dbs
= dev
->bar
+ 4096;
1658 * Temporary fix for the Apple controller found in the MacBook8,1 and
1659 * some MacBook7,1 to avoid controller resets and data loss.
1661 if (pdev
->vendor
== PCI_VENDOR_ID_APPLE
&& pdev
->device
== 0x2001) {
1663 dev_warn(dev
->dev
, "detected Apple NVMe controller, set "
1664 "queue depth=%u to work around controller resets\n",
1668 if (readl(dev
->bar
+ NVME_REG_VS
) >= NVME_VS(1, 2))
1669 dev
->cmb
= nvme_map_cmb(dev
);
1671 pci_enable_pcie_error_reporting(pdev
);
1672 pci_save_state(pdev
);
1676 pci_disable_device(pdev
);
1680 static void nvme_dev_unmap(struct nvme_dev
*dev
)
1682 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1688 bars
= pci_select_bars(pdev
, IORESOURCE_MEM
);
1689 pci_release_selected_regions(pdev
, bars
);
1692 static void nvme_pci_disable(struct nvme_dev
*dev
)
1694 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1696 if (pdev
->msi_enabled
)
1697 pci_disable_msi(pdev
);
1698 else if (pdev
->msix_enabled
)
1699 pci_disable_msix(pdev
);
1701 if (pci_is_enabled(pdev
)) {
1702 pci_disable_pcie_error_reporting(pdev
);
1703 pci_disable_device(pdev
);
1707 static void nvme_dev_disable(struct nvme_dev
*dev
, bool shutdown
)
1712 del_timer_sync(&dev
->watchdog_timer
);
1714 mutex_lock(&dev
->shutdown_lock
);
1715 if (pci_is_enabled(to_pci_dev(dev
->dev
))) {
1716 nvme_stop_queues(&dev
->ctrl
);
1717 csts
= readl(dev
->bar
+ NVME_REG_CSTS
);
1719 if (csts
& NVME_CSTS_CFS
|| !(csts
& NVME_CSTS_RDY
)) {
1720 for (i
= dev
->queue_count
- 1; i
>= 0; i
--) {
1721 struct nvme_queue
*nvmeq
= dev
->queues
[i
];
1722 nvme_suspend_queue(nvmeq
);
1725 nvme_disable_io_queues(dev
);
1726 nvme_disable_admin_queue(dev
, shutdown
);
1728 nvme_pci_disable(dev
);
1730 blk_mq_tagset_busy_iter(&dev
->tagset
, nvme_cancel_io
, dev
);
1731 blk_mq_tagset_busy_iter(&dev
->admin_tagset
, nvme_cancel_io
, dev
);
1732 mutex_unlock(&dev
->shutdown_lock
);
1735 static int nvme_setup_prp_pools(struct nvme_dev
*dev
)
1737 dev
->prp_page_pool
= dma_pool_create("prp list page", dev
->dev
,
1738 PAGE_SIZE
, PAGE_SIZE
, 0);
1739 if (!dev
->prp_page_pool
)
1742 /* Optimisation for I/Os between 4k and 128k */
1743 dev
->prp_small_pool
= dma_pool_create("prp list 256", dev
->dev
,
1745 if (!dev
->prp_small_pool
) {
1746 dma_pool_destroy(dev
->prp_page_pool
);
1752 static void nvme_release_prp_pools(struct nvme_dev
*dev
)
1754 dma_pool_destroy(dev
->prp_page_pool
);
1755 dma_pool_destroy(dev
->prp_small_pool
);
1758 static void nvme_pci_free_ctrl(struct nvme_ctrl
*ctrl
)
1760 struct nvme_dev
*dev
= to_nvme_dev(ctrl
);
1762 put_device(dev
->dev
);
1763 if (dev
->tagset
.tags
)
1764 blk_mq_free_tag_set(&dev
->tagset
);
1765 if (dev
->ctrl
.admin_q
)
1766 blk_put_queue(dev
->ctrl
.admin_q
);
1772 static void nvme_remove_dead_ctrl(struct nvme_dev
*dev
, int status
)
1774 dev_warn(dev
->ctrl
.device
, "Removing after probe failure status: %d\n", status
);
1776 kref_get(&dev
->ctrl
.kref
);
1777 nvme_dev_disable(dev
, false);
1778 if (!schedule_work(&dev
->remove_work
))
1779 nvme_put_ctrl(&dev
->ctrl
);
1782 static void nvme_reset_work(struct work_struct
*work
)
1784 struct nvme_dev
*dev
= container_of(work
, struct nvme_dev
, reset_work
);
1785 int result
= -ENODEV
;
1787 if (WARN_ON(dev
->ctrl
.state
== NVME_CTRL_RESETTING
))
1791 * If we're called to reset a live controller first shut it down before
1794 if (dev
->ctrl
.ctrl_config
& NVME_CC_ENABLE
)
1795 nvme_dev_disable(dev
, false);
1797 if (!nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_RESETTING
))
1800 result
= nvme_pci_enable(dev
);
1804 result
= nvme_configure_admin_queue(dev
);
1808 nvme_init_queue(dev
->queues
[0], 0);
1809 result
= nvme_alloc_admin_tags(dev
);
1813 result
= nvme_init_identify(&dev
->ctrl
);
1817 result
= nvme_setup_io_queues(dev
);
1822 * A controller that can not execute IO typically requires user
1823 * intervention to correct. For such degraded controllers, the driver
1824 * should not submit commands the user did not request, so skip
1825 * registering for asynchronous event notification on this condition.
1827 if (dev
->online_queues
> 1)
1828 nvme_queue_async_events(&dev
->ctrl
);
1830 mod_timer(&dev
->watchdog_timer
, round_jiffies(jiffies
+ HZ
));
1833 * Keep the controller around but remove all namespaces if we don't have
1834 * any working I/O queue.
1836 if (dev
->online_queues
< 2) {
1837 dev_warn(dev
->ctrl
.device
, "IO queues not created\n");
1838 nvme_kill_queues(&dev
->ctrl
);
1839 nvme_remove_namespaces(&dev
->ctrl
);
1841 nvme_start_queues(&dev
->ctrl
);
1845 if (!nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_LIVE
)) {
1846 dev_warn(dev
->ctrl
.device
, "failed to mark controller live\n");
1850 if (dev
->online_queues
> 1)
1851 nvme_queue_scan(&dev
->ctrl
);
1855 nvme_remove_dead_ctrl(dev
, result
);
1858 static void nvme_remove_dead_ctrl_work(struct work_struct
*work
)
1860 struct nvme_dev
*dev
= container_of(work
, struct nvme_dev
, remove_work
);
1861 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1863 nvme_kill_queues(&dev
->ctrl
);
1864 if (pci_get_drvdata(pdev
))
1865 device_release_driver(&pdev
->dev
);
1866 nvme_put_ctrl(&dev
->ctrl
);
1869 static int nvme_reset(struct nvme_dev
*dev
)
1871 if (!dev
->ctrl
.admin_q
|| blk_queue_dying(dev
->ctrl
.admin_q
))
1874 if (!queue_work(nvme_workq
, &dev
->reset_work
))
1877 flush_work(&dev
->reset_work
);
1881 static int nvme_pci_reg_read32(struct nvme_ctrl
*ctrl
, u32 off
, u32
*val
)
1883 *val
= readl(to_nvme_dev(ctrl
)->bar
+ off
);
1887 static int nvme_pci_reg_write32(struct nvme_ctrl
*ctrl
, u32 off
, u32 val
)
1889 writel(val
, to_nvme_dev(ctrl
)->bar
+ off
);
1893 static int nvme_pci_reg_read64(struct nvme_ctrl
*ctrl
, u32 off
, u64
*val
)
1895 *val
= readq(to_nvme_dev(ctrl
)->bar
+ off
);
1899 static int nvme_pci_reset_ctrl(struct nvme_ctrl
*ctrl
)
1901 return nvme_reset(to_nvme_dev(ctrl
));
1904 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops
= {
1905 .module
= THIS_MODULE
,
1906 .reg_read32
= nvme_pci_reg_read32
,
1907 .reg_write32
= nvme_pci_reg_write32
,
1908 .reg_read64
= nvme_pci_reg_read64
,
1909 .reset_ctrl
= nvme_pci_reset_ctrl
,
1910 .free_ctrl
= nvme_pci_free_ctrl
,
1911 .post_scan
= nvme_pci_post_scan
,
1912 .submit_async_event
= nvme_pci_submit_async_event
,
1915 static int nvme_dev_map(struct nvme_dev
*dev
)
1918 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1920 bars
= pci_select_bars(pdev
, IORESOURCE_MEM
);
1923 if (pci_request_selected_regions(pdev
, bars
, "nvme"))
1926 dev
->bar
= ioremap(pci_resource_start(pdev
, 0), 8192);
1932 pci_release_selected_regions(pdev
, bars
);
1936 static int nvme_probe(struct pci_dev
*pdev
, const struct pci_device_id
*id
)
1938 int node
, result
= -ENOMEM
;
1939 struct nvme_dev
*dev
;
1941 node
= dev_to_node(&pdev
->dev
);
1942 if (node
== NUMA_NO_NODE
)
1943 set_dev_node(&pdev
->dev
, 0);
1945 dev
= kzalloc_node(sizeof(*dev
), GFP_KERNEL
, node
);
1948 dev
->entry
= kzalloc_node(num_possible_cpus() * sizeof(*dev
->entry
),
1952 dev
->queues
= kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
1957 dev
->dev
= get_device(&pdev
->dev
);
1958 pci_set_drvdata(pdev
, dev
);
1960 result
= nvme_dev_map(dev
);
1964 INIT_WORK(&dev
->reset_work
, nvme_reset_work
);
1965 INIT_WORK(&dev
->remove_work
, nvme_remove_dead_ctrl_work
);
1966 setup_timer(&dev
->watchdog_timer
, nvme_watchdog_timer
,
1967 (unsigned long)dev
);
1968 mutex_init(&dev
->shutdown_lock
);
1969 init_completion(&dev
->ioq_wait
);
1971 result
= nvme_setup_prp_pools(dev
);
1975 result
= nvme_init_ctrl(&dev
->ctrl
, &pdev
->dev
, &nvme_pci_ctrl_ops
,
1980 dev_info(dev
->ctrl
.device
, "pci function %s\n", dev_name(&pdev
->dev
));
1982 queue_work(nvme_workq
, &dev
->reset_work
);
1986 nvme_release_prp_pools(dev
);
1988 put_device(dev
->dev
);
1989 nvme_dev_unmap(dev
);
1997 static void nvme_reset_notify(struct pci_dev
*pdev
, bool prepare
)
1999 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2002 nvme_dev_disable(dev
, false);
2004 queue_work(nvme_workq
, &dev
->reset_work
);
2007 static void nvme_shutdown(struct pci_dev
*pdev
)
2009 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2010 nvme_dev_disable(dev
, true);
2014 * The driver's remove may be called on a device in a partially initialized
2015 * state. This function must not have any dependencies on the device state in
2018 static void nvme_remove(struct pci_dev
*pdev
)
2020 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2022 nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_DELETING
);
2024 pci_set_drvdata(pdev
, NULL
);
2026 if (!pci_device_is_present(pdev
))
2027 nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_DEAD
);
2029 flush_work(&dev
->reset_work
);
2030 nvme_uninit_ctrl(&dev
->ctrl
);
2031 nvme_dev_disable(dev
, true);
2032 nvme_dev_remove_admin(dev
);
2033 nvme_free_queues(dev
, 0);
2034 nvme_release_cmb(dev
);
2035 nvme_release_prp_pools(dev
);
2036 nvme_dev_unmap(dev
);
2037 nvme_put_ctrl(&dev
->ctrl
);
2040 #ifdef CONFIG_PM_SLEEP
2041 static int nvme_suspend(struct device
*dev
)
2043 struct pci_dev
*pdev
= to_pci_dev(dev
);
2044 struct nvme_dev
*ndev
= pci_get_drvdata(pdev
);
2046 nvme_dev_disable(ndev
, true);
2050 static int nvme_resume(struct device
*dev
)
2052 struct pci_dev
*pdev
= to_pci_dev(dev
);
2053 struct nvme_dev
*ndev
= pci_get_drvdata(pdev
);
2055 queue_work(nvme_workq
, &ndev
->reset_work
);
2060 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops
, nvme_suspend
, nvme_resume
);
2062 static pci_ers_result_t
nvme_error_detected(struct pci_dev
*pdev
,
2063 pci_channel_state_t state
)
2065 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2068 * A frozen channel requires a reset. When detected, this method will
2069 * shutdown the controller to quiesce. The controller will be restarted
2070 * after the slot reset through driver's slot_reset callback.
2073 case pci_channel_io_normal
:
2074 return PCI_ERS_RESULT_CAN_RECOVER
;
2075 case pci_channel_io_frozen
:
2076 dev_warn(dev
->ctrl
.device
,
2077 "frozen state error detected, reset controller\n");
2078 nvme_dev_disable(dev
, false);
2079 return PCI_ERS_RESULT_NEED_RESET
;
2080 case pci_channel_io_perm_failure
:
2081 dev_warn(dev
->ctrl
.device
,
2082 "failure state error detected, request disconnect\n");
2083 return PCI_ERS_RESULT_DISCONNECT
;
2085 return PCI_ERS_RESULT_NEED_RESET
;
2088 static pci_ers_result_t
nvme_slot_reset(struct pci_dev
*pdev
)
2090 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2092 dev_info(dev
->ctrl
.device
, "restart after slot reset\n");
2093 pci_restore_state(pdev
);
2094 queue_work(nvme_workq
, &dev
->reset_work
);
2095 return PCI_ERS_RESULT_RECOVERED
;
2098 static void nvme_error_resume(struct pci_dev
*pdev
)
2100 pci_cleanup_aer_uncorrect_error_status(pdev
);
2103 static const struct pci_error_handlers nvme_err_handler
= {
2104 .error_detected
= nvme_error_detected
,
2105 .slot_reset
= nvme_slot_reset
,
2106 .resume
= nvme_error_resume
,
2107 .reset_notify
= nvme_reset_notify
,
2110 /* Move to pci_ids.h later */
2111 #define PCI_CLASS_STORAGE_EXPRESS 0x010802
2113 static const struct pci_device_id nvme_id_table
[] = {
2114 { PCI_VDEVICE(INTEL
, 0x0953),
2115 .driver_data
= NVME_QUIRK_STRIPE_SIZE
|
2116 NVME_QUIRK_DISCARD_ZEROES
, },
2117 { PCI_VDEVICE(INTEL
, 0x0a53),
2118 .driver_data
= NVME_QUIRK_STRIPE_SIZE
|
2119 NVME_QUIRK_DISCARD_ZEROES
, },
2120 { PCI_VDEVICE(INTEL
, 0x0a54),
2121 .driver_data
= NVME_QUIRK_STRIPE_SIZE
|
2122 NVME_QUIRK_DISCARD_ZEROES
, },
2123 { PCI_VDEVICE(INTEL
, 0x5845), /* Qemu emulated controller */
2124 .driver_data
= NVME_QUIRK_IDENTIFY_CNS
, },
2125 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS
, 0xffffff) },
2126 { PCI_DEVICE(PCI_VENDOR_ID_APPLE
, 0x2001) },
2129 MODULE_DEVICE_TABLE(pci
, nvme_id_table
);
2131 static struct pci_driver nvme_driver
= {
2133 .id_table
= nvme_id_table
,
2134 .probe
= nvme_probe
,
2135 .remove
= nvme_remove
,
2136 .shutdown
= nvme_shutdown
,
2138 .pm
= &nvme_dev_pm_ops
,
2140 .err_handler
= &nvme_err_handler
,
2143 static int __init
nvme_init(void)
2147 nvme_workq
= alloc_workqueue("nvme", WQ_UNBOUND
| WQ_MEM_RECLAIM
, 0);
2151 result
= pci_register_driver(&nvme_driver
);
2153 destroy_workqueue(nvme_workq
);
2157 static void __exit
nvme_exit(void)
2159 pci_unregister_driver(&nvme_driver
);
2160 destroy_workqueue(nvme_workq
);
2164 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2165 MODULE_LICENSE("GPL");
2166 MODULE_VERSION("1.0");
2167 module_init(nvme_init
);
2168 module_exit(nvme_exit
);