2 * NVM Express device driver
3 * Copyright (c) 2011-2014, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 #include <linux/aer.h>
16 #include <linux/bitops.h>
17 #include <linux/blkdev.h>
18 #include <linux/blk-mq.h>
19 #include <linux/cpu.h>
20 #include <linux/delay.h>
21 #include <linux/errno.h>
23 #include <linux/genhd.h>
24 #include <linux/hdreg.h>
25 #include <linux/idr.h>
26 #include <linux/init.h>
27 #include <linux/interrupt.h>
29 #include <linux/kdev_t.h>
30 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/moduleparam.h>
34 #include <linux/mutex.h>
35 #include <linux/pci.h>
36 #include <linux/poison.h>
37 #include <linux/ptrace.h>
38 #include <linux/sched.h>
39 #include <linux/slab.h>
40 #include <linux/t10-pi.h>
41 #include <linux/timer.h>
42 #include <linux/types.h>
43 #include <linux/io-64-nonatomic-lo-hi.h>
44 #include <asm/unaligned.h>
48 #define NVME_Q_DEPTH 1024
49 #define NVME_AQ_DEPTH 256
50 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
51 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
54 * We handle AEN commands ourselves and don't even let the
55 * block layer know about them.
57 #define NVME_NR_AEN_COMMANDS 1
58 #define NVME_AQ_BLKMQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS)
60 static int use_threaded_interrupts
;
61 module_param(use_threaded_interrupts
, int, 0);
63 static bool use_cmb_sqes
= true;
64 module_param(use_cmb_sqes
, bool, 0644);
65 MODULE_PARM_DESC(use_cmb_sqes
, "use controller's memory buffer for I/O SQes");
67 static struct workqueue_struct
*nvme_workq
;
72 static int nvme_reset(struct nvme_dev
*dev
);
73 static void nvme_process_cq(struct nvme_queue
*nvmeq
);
74 static void nvme_dev_disable(struct nvme_dev
*dev
, bool shutdown
);
77 * Represents an NVM Express device. Each nvme_dev is a PCI function.
80 struct nvme_queue
**queues
;
81 struct blk_mq_tag_set tagset
;
82 struct blk_mq_tag_set admin_tagset
;
85 struct dma_pool
*prp_page_pool
;
86 struct dma_pool
*prp_small_pool
;
88 unsigned online_queues
;
92 struct msix_entry
*entry
;
94 struct work_struct reset_work
;
95 struct work_struct scan_work
;
96 struct work_struct remove_work
;
97 struct work_struct async_work
;
98 struct timer_list watchdog_timer
;
99 struct mutex shutdown_lock
;
102 dma_addr_t cmb_dma_addr
;
107 #define NVME_CTRL_RESETTING 0
108 #define NVME_CTRL_REMOVING 1
110 struct nvme_ctrl ctrl
;
111 struct completion ioq_wait
;
114 static inline struct nvme_dev
*to_nvme_dev(struct nvme_ctrl
*ctrl
)
116 return container_of(ctrl
, struct nvme_dev
, ctrl
);
120 * An NVM Express queue. Each device has at least two (one for admin
121 * commands and one for I/O commands).
124 struct device
*q_dmadev
;
125 struct nvme_dev
*dev
;
126 char irqname
[24]; /* nvme4294967295-65535\0 */
128 struct nvme_command
*sq_cmds
;
129 struct nvme_command __iomem
*sq_cmds_io
;
130 volatile struct nvme_completion
*cqes
;
131 struct blk_mq_tags
**tags
;
132 dma_addr_t sq_dma_addr
;
133 dma_addr_t cq_dma_addr
;
145 * The nvme_iod describes the data in an I/O, including the list of PRP
146 * entries. You can't see it in this data structure because C doesn't let
147 * me express that. Use nvme_init_iod to ensure there's enough space
148 * allocated to store the PRP list.
151 struct nvme_queue
*nvmeq
;
153 int npages
; /* In the PRP list. 0 means small pool in use */
154 int nents
; /* Used in scatterlist */
155 int length
; /* Of data, in bytes */
156 dma_addr_t first_dma
;
157 struct scatterlist meta_sg
; /* metadata requires single contiguous buffer */
158 struct scatterlist
*sg
;
159 struct scatterlist inline_sg
[0];
163 * Check we didin't inadvertently grow the command struct
165 static inline void _nvme_check_size(void)
167 BUILD_BUG_ON(sizeof(struct nvme_rw_command
) != 64);
168 BUILD_BUG_ON(sizeof(struct nvme_create_cq
) != 64);
169 BUILD_BUG_ON(sizeof(struct nvme_create_sq
) != 64);
170 BUILD_BUG_ON(sizeof(struct nvme_delete_queue
) != 64);
171 BUILD_BUG_ON(sizeof(struct nvme_features
) != 64);
172 BUILD_BUG_ON(sizeof(struct nvme_format_cmd
) != 64);
173 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd
) != 64);
174 BUILD_BUG_ON(sizeof(struct nvme_command
) != 64);
175 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl
) != 4096);
176 BUILD_BUG_ON(sizeof(struct nvme_id_ns
) != 4096);
177 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type
) != 64);
178 BUILD_BUG_ON(sizeof(struct nvme_smart_log
) != 512);
182 * Max size of iod being embedded in the request payload
184 #define NVME_INT_PAGES 2
185 #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size)
188 * Will slightly overestimate the number of pages needed. This is OK
189 * as it only leads to a small amount of wasted memory for the lifetime of
192 static int nvme_npages(unsigned size
, struct nvme_dev
*dev
)
194 unsigned nprps
= DIV_ROUND_UP(size
+ dev
->ctrl
.page_size
,
195 dev
->ctrl
.page_size
);
196 return DIV_ROUND_UP(8 * nprps
, PAGE_SIZE
- 8);
199 static unsigned int nvme_iod_alloc_size(struct nvme_dev
*dev
,
200 unsigned int size
, unsigned int nseg
)
202 return sizeof(__le64
*) * nvme_npages(size
, dev
) +
203 sizeof(struct scatterlist
) * nseg
;
206 static unsigned int nvme_cmd_size(struct nvme_dev
*dev
)
208 return sizeof(struct nvme_iod
) +
209 nvme_iod_alloc_size(dev
, NVME_INT_BYTES(dev
), NVME_INT_PAGES
);
212 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx
*hctx
, void *data
,
213 unsigned int hctx_idx
)
215 struct nvme_dev
*dev
= data
;
216 struct nvme_queue
*nvmeq
= dev
->queues
[0];
218 WARN_ON(hctx_idx
!= 0);
219 WARN_ON(dev
->admin_tagset
.tags
[0] != hctx
->tags
);
220 WARN_ON(nvmeq
->tags
);
222 hctx
->driver_data
= nvmeq
;
223 nvmeq
->tags
= &dev
->admin_tagset
.tags
[0];
227 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx
*hctx
, unsigned int hctx_idx
)
229 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
234 static int nvme_admin_init_request(void *data
, struct request
*req
,
235 unsigned int hctx_idx
, unsigned int rq_idx
,
236 unsigned int numa_node
)
238 struct nvme_dev
*dev
= data
;
239 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
240 struct nvme_queue
*nvmeq
= dev
->queues
[0];
247 static int nvme_init_hctx(struct blk_mq_hw_ctx
*hctx
, void *data
,
248 unsigned int hctx_idx
)
250 struct nvme_dev
*dev
= data
;
251 struct nvme_queue
*nvmeq
= dev
->queues
[hctx_idx
+ 1];
254 nvmeq
->tags
= &dev
->tagset
.tags
[hctx_idx
];
256 WARN_ON(dev
->tagset
.tags
[hctx_idx
] != hctx
->tags
);
257 hctx
->driver_data
= nvmeq
;
261 static int nvme_init_request(void *data
, struct request
*req
,
262 unsigned int hctx_idx
, unsigned int rq_idx
,
263 unsigned int numa_node
)
265 struct nvme_dev
*dev
= data
;
266 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
267 struct nvme_queue
*nvmeq
= dev
->queues
[hctx_idx
+ 1];
274 static void nvme_queue_scan(struct nvme_dev
*dev
)
277 * Do not queue new scan work when a controller is reset during
280 if (test_bit(NVME_CTRL_REMOVING
, &dev
->flags
))
282 queue_work(nvme_workq
, &dev
->scan_work
);
285 static void nvme_complete_async_event(struct nvme_dev
*dev
,
286 struct nvme_completion
*cqe
)
288 u16 status
= le16_to_cpu(cqe
->status
) >> 1;
289 u32 result
= le32_to_cpu(cqe
->result
);
291 if (status
== NVME_SC_SUCCESS
|| status
== NVME_SC_ABORT_REQ
) {
292 ++dev
->ctrl
.event_limit
;
293 queue_work(nvme_workq
, &dev
->async_work
);
296 if (status
!= NVME_SC_SUCCESS
)
299 switch (result
& 0xff07) {
300 case NVME_AER_NOTICE_NS_CHANGED
:
301 dev_info(dev
->ctrl
.device
, "rescanning\n");
302 nvme_queue_scan(dev
);
304 dev_warn(dev
->ctrl
.device
, "async event result %08x\n", result
);
309 * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
310 * @nvmeq: The queue to use
311 * @cmd: The command to send
313 * Safe to use from interrupt context
315 static void __nvme_submit_cmd(struct nvme_queue
*nvmeq
,
316 struct nvme_command
*cmd
)
318 u16 tail
= nvmeq
->sq_tail
;
320 if (nvmeq
->sq_cmds_io
)
321 memcpy_toio(&nvmeq
->sq_cmds_io
[tail
], cmd
, sizeof(*cmd
));
323 memcpy(&nvmeq
->sq_cmds
[tail
], cmd
, sizeof(*cmd
));
325 if (++tail
== nvmeq
->q_depth
)
327 writel(tail
, nvmeq
->q_db
);
328 nvmeq
->sq_tail
= tail
;
331 static __le64
**iod_list(struct request
*req
)
333 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
334 return (__le64
**)(iod
->sg
+ req
->nr_phys_segments
);
337 static int nvme_init_iod(struct request
*rq
, struct nvme_dev
*dev
)
339 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(rq
);
340 int nseg
= rq
->nr_phys_segments
;
343 if (rq
->cmd_flags
& REQ_DISCARD
)
344 size
= sizeof(struct nvme_dsm_range
);
346 size
= blk_rq_bytes(rq
);
348 if (nseg
> NVME_INT_PAGES
|| size
> NVME_INT_BYTES(dev
)) {
349 iod
->sg
= kmalloc(nvme_iod_alloc_size(dev
, size
, nseg
), GFP_ATOMIC
);
351 return BLK_MQ_RQ_QUEUE_BUSY
;
353 iod
->sg
= iod
->inline_sg
;
363 static void nvme_free_iod(struct nvme_dev
*dev
, struct request
*req
)
365 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
366 const int last_prp
= dev
->ctrl
.page_size
/ 8 - 1;
368 __le64
**list
= iod_list(req
);
369 dma_addr_t prp_dma
= iod
->first_dma
;
371 if (iod
->npages
== 0)
372 dma_pool_free(dev
->prp_small_pool
, list
[0], prp_dma
);
373 for (i
= 0; i
< iod
->npages
; i
++) {
374 __le64
*prp_list
= list
[i
];
375 dma_addr_t next_prp_dma
= le64_to_cpu(prp_list
[last_prp
]);
376 dma_pool_free(dev
->prp_page_pool
, prp_list
, prp_dma
);
377 prp_dma
= next_prp_dma
;
380 if (iod
->sg
!= iod
->inline_sg
)
384 #ifdef CONFIG_BLK_DEV_INTEGRITY
385 static void nvme_dif_prep(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
387 if (be32_to_cpu(pi
->ref_tag
) == v
)
388 pi
->ref_tag
= cpu_to_be32(p
);
391 static void nvme_dif_complete(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
393 if (be32_to_cpu(pi
->ref_tag
) == p
)
394 pi
->ref_tag
= cpu_to_be32(v
);
398 * nvme_dif_remap - remaps ref tags to bip seed and physical lba
400 * The virtual start sector is the one that was originally submitted by the
401 * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
402 * start sector may be different. Remap protection information to match the
403 * physical LBA on writes, and back to the original seed on reads.
405 * Type 0 and 3 do not have a ref tag, so no remapping required.
407 static void nvme_dif_remap(struct request
*req
,
408 void (*dif_swap
)(u32 p
, u32 v
, struct t10_pi_tuple
*pi
))
410 struct nvme_ns
*ns
= req
->rq_disk
->private_data
;
411 struct bio_integrity_payload
*bip
;
412 struct t10_pi_tuple
*pi
;
414 u32 i
, nlb
, ts
, phys
, virt
;
416 if (!ns
->pi_type
|| ns
->pi_type
== NVME_NS_DPS_PI_TYPE3
)
419 bip
= bio_integrity(req
->bio
);
423 pmap
= kmap_atomic(bip
->bip_vec
->bv_page
) + bip
->bip_vec
->bv_offset
;
426 virt
= bip_get_seed(bip
);
427 phys
= nvme_block_nr(ns
, blk_rq_pos(req
));
428 nlb
= (blk_rq_bytes(req
) >> ns
->lba_shift
);
429 ts
= ns
->disk
->queue
->integrity
.tuple_size
;
431 for (i
= 0; i
< nlb
; i
++, virt
++, phys
++) {
432 pi
= (struct t10_pi_tuple
*)p
;
433 dif_swap(phys
, virt
, pi
);
438 #else /* CONFIG_BLK_DEV_INTEGRITY */
439 static void nvme_dif_remap(struct request
*req
,
440 void (*dif_swap
)(u32 p
, u32 v
, struct t10_pi_tuple
*pi
))
443 static void nvme_dif_prep(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
446 static void nvme_dif_complete(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
451 static bool nvme_setup_prps(struct nvme_dev
*dev
, struct request
*req
,
454 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
455 struct dma_pool
*pool
;
456 int length
= total_len
;
457 struct scatterlist
*sg
= iod
->sg
;
458 int dma_len
= sg_dma_len(sg
);
459 u64 dma_addr
= sg_dma_address(sg
);
460 u32 page_size
= dev
->ctrl
.page_size
;
461 int offset
= dma_addr
& (page_size
- 1);
463 __le64
**list
= iod_list(req
);
467 length
-= (page_size
- offset
);
471 dma_len
-= (page_size
- offset
);
473 dma_addr
+= (page_size
- offset
);
476 dma_addr
= sg_dma_address(sg
);
477 dma_len
= sg_dma_len(sg
);
480 if (length
<= page_size
) {
481 iod
->first_dma
= dma_addr
;
485 nprps
= DIV_ROUND_UP(length
, page_size
);
486 if (nprps
<= (256 / 8)) {
487 pool
= dev
->prp_small_pool
;
490 pool
= dev
->prp_page_pool
;
494 prp_list
= dma_pool_alloc(pool
, GFP_ATOMIC
, &prp_dma
);
496 iod
->first_dma
= dma_addr
;
501 iod
->first_dma
= prp_dma
;
504 if (i
== page_size
>> 3) {
505 __le64
*old_prp_list
= prp_list
;
506 prp_list
= dma_pool_alloc(pool
, GFP_ATOMIC
, &prp_dma
);
509 list
[iod
->npages
++] = prp_list
;
510 prp_list
[0] = old_prp_list
[i
- 1];
511 old_prp_list
[i
- 1] = cpu_to_le64(prp_dma
);
514 prp_list
[i
++] = cpu_to_le64(dma_addr
);
515 dma_len
-= page_size
;
516 dma_addr
+= page_size
;
524 dma_addr
= sg_dma_address(sg
);
525 dma_len
= sg_dma_len(sg
);
531 static int nvme_map_data(struct nvme_dev
*dev
, struct request
*req
,
532 struct nvme_command
*cmnd
)
534 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
535 struct request_queue
*q
= req
->q
;
536 enum dma_data_direction dma_dir
= rq_data_dir(req
) ?
537 DMA_TO_DEVICE
: DMA_FROM_DEVICE
;
538 int ret
= BLK_MQ_RQ_QUEUE_ERROR
;
540 sg_init_table(iod
->sg
, req
->nr_phys_segments
);
541 iod
->nents
= blk_rq_map_sg(q
, req
, iod
->sg
);
545 ret
= BLK_MQ_RQ_QUEUE_BUSY
;
546 if (!dma_map_sg(dev
->dev
, iod
->sg
, iod
->nents
, dma_dir
))
549 if (!nvme_setup_prps(dev
, req
, blk_rq_bytes(req
)))
552 ret
= BLK_MQ_RQ_QUEUE_ERROR
;
553 if (blk_integrity_rq(req
)) {
554 if (blk_rq_count_integrity_sg(q
, req
->bio
) != 1)
557 sg_init_table(&iod
->meta_sg
, 1);
558 if (blk_rq_map_integrity_sg(q
, req
->bio
, &iod
->meta_sg
) != 1)
561 if (rq_data_dir(req
))
562 nvme_dif_remap(req
, nvme_dif_prep
);
564 if (!dma_map_sg(dev
->dev
, &iod
->meta_sg
, 1, dma_dir
))
568 cmnd
->rw
.prp1
= cpu_to_le64(sg_dma_address(iod
->sg
));
569 cmnd
->rw
.prp2
= cpu_to_le64(iod
->first_dma
);
570 if (blk_integrity_rq(req
))
571 cmnd
->rw
.metadata
= cpu_to_le64(sg_dma_address(&iod
->meta_sg
));
572 return BLK_MQ_RQ_QUEUE_OK
;
575 dma_unmap_sg(dev
->dev
, iod
->sg
, iod
->nents
, dma_dir
);
580 static void nvme_unmap_data(struct nvme_dev
*dev
, struct request
*req
)
582 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
583 enum dma_data_direction dma_dir
= rq_data_dir(req
) ?
584 DMA_TO_DEVICE
: DMA_FROM_DEVICE
;
587 dma_unmap_sg(dev
->dev
, iod
->sg
, iod
->nents
, dma_dir
);
588 if (blk_integrity_rq(req
)) {
589 if (!rq_data_dir(req
))
590 nvme_dif_remap(req
, nvme_dif_complete
);
591 dma_unmap_sg(dev
->dev
, &iod
->meta_sg
, 1, dma_dir
);
595 nvme_free_iod(dev
, req
);
599 * We reuse the small pool to allocate the 16-byte range here as it is not
600 * worth having a special pool for these or additional cases to handle freeing
603 static int nvme_setup_discard(struct nvme_queue
*nvmeq
, struct nvme_ns
*ns
,
604 struct request
*req
, struct nvme_command
*cmnd
)
606 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
607 struct nvme_dsm_range
*range
;
609 range
= dma_pool_alloc(nvmeq
->dev
->prp_small_pool
, GFP_ATOMIC
,
612 return BLK_MQ_RQ_QUEUE_BUSY
;
613 iod_list(req
)[0] = (__le64
*)range
;
616 range
->cattr
= cpu_to_le32(0);
617 range
->nlb
= cpu_to_le32(blk_rq_bytes(req
) >> ns
->lba_shift
);
618 range
->slba
= cpu_to_le64(nvme_block_nr(ns
, blk_rq_pos(req
)));
620 memset(cmnd
, 0, sizeof(*cmnd
));
621 cmnd
->dsm
.opcode
= nvme_cmd_dsm
;
622 cmnd
->dsm
.nsid
= cpu_to_le32(ns
->ns_id
);
623 cmnd
->dsm
.prp1
= cpu_to_le64(iod
->first_dma
);
625 cmnd
->dsm
.attributes
= cpu_to_le32(NVME_DSMGMT_AD
);
626 return BLK_MQ_RQ_QUEUE_OK
;
630 * NOTE: ns is NULL when called on the admin queue.
632 static int nvme_queue_rq(struct blk_mq_hw_ctx
*hctx
,
633 const struct blk_mq_queue_data
*bd
)
635 struct nvme_ns
*ns
= hctx
->queue
->queuedata
;
636 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
637 struct nvme_dev
*dev
= nvmeq
->dev
;
638 struct request
*req
= bd
->rq
;
639 struct nvme_command cmnd
;
640 int ret
= BLK_MQ_RQ_QUEUE_OK
;
643 * If formated with metadata, require the block layer provide a buffer
644 * unless this namespace is formated such that the metadata can be
645 * stripped/generated by the controller with PRACT=1.
647 if (ns
&& ns
->ms
&& !blk_integrity_rq(req
)) {
648 if (!(ns
->pi_type
&& ns
->ms
== 8) &&
649 req
->cmd_type
!= REQ_TYPE_DRV_PRIV
) {
650 blk_mq_end_request(req
, -EFAULT
);
651 return BLK_MQ_RQ_QUEUE_OK
;
655 ret
= nvme_init_iod(req
, dev
);
659 if (req
->cmd_flags
& REQ_DISCARD
) {
660 ret
= nvme_setup_discard(nvmeq
, ns
, req
, &cmnd
);
662 if (req
->cmd_type
== REQ_TYPE_DRV_PRIV
)
663 memcpy(&cmnd
, req
->cmd
, sizeof(cmnd
));
664 else if (req
->cmd_flags
& REQ_FLUSH
)
665 nvme_setup_flush(ns
, &cmnd
);
667 nvme_setup_rw(ns
, req
, &cmnd
);
669 if (req
->nr_phys_segments
)
670 ret
= nvme_map_data(dev
, req
, &cmnd
);
676 cmnd
.common
.command_id
= req
->tag
;
677 blk_mq_start_request(req
);
679 spin_lock_irq(&nvmeq
->q_lock
);
680 if (unlikely(nvmeq
->cq_vector
< 0)) {
681 if (ns
&& !test_bit(NVME_NS_DEAD
, &ns
->flags
))
682 ret
= BLK_MQ_RQ_QUEUE_BUSY
;
684 ret
= BLK_MQ_RQ_QUEUE_ERROR
;
685 spin_unlock_irq(&nvmeq
->q_lock
);
688 __nvme_submit_cmd(nvmeq
, &cmnd
);
689 nvme_process_cq(nvmeq
);
690 spin_unlock_irq(&nvmeq
->q_lock
);
691 return BLK_MQ_RQ_QUEUE_OK
;
693 nvme_free_iod(dev
, req
);
697 static void nvme_complete_rq(struct request
*req
)
699 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
700 struct nvme_dev
*dev
= iod
->nvmeq
->dev
;
703 nvme_unmap_data(dev
, req
);
705 if (unlikely(req
->errors
)) {
706 if (nvme_req_needs_retry(req
, req
->errors
)) {
707 nvme_requeue_req(req
);
711 if (req
->cmd_type
== REQ_TYPE_DRV_PRIV
)
714 error
= nvme_error_status(req
->errors
);
717 if (unlikely(iod
->aborted
)) {
718 dev_warn(dev
->ctrl
.device
,
719 "completing aborted command with status: %04x\n",
723 blk_mq_end_request(req
, error
);
726 static void __nvme_process_cq(struct nvme_queue
*nvmeq
, unsigned int *tag
)
730 head
= nvmeq
->cq_head
;
731 phase
= nvmeq
->cq_phase
;
734 struct nvme_completion cqe
= nvmeq
->cqes
[head
];
735 u16 status
= le16_to_cpu(cqe
.status
);
738 if ((status
& 1) != phase
)
740 if (++head
== nvmeq
->q_depth
) {
745 if (tag
&& *tag
== cqe
.command_id
)
748 if (unlikely(cqe
.command_id
>= nvmeq
->q_depth
)) {
749 dev_warn(nvmeq
->dev
->ctrl
.device
,
750 "invalid id %d completed on queue %d\n",
751 cqe
.command_id
, le16_to_cpu(cqe
.sq_id
));
756 * AEN requests are special as they don't time out and can
757 * survive any kind of queue freeze and often don't respond to
758 * aborts. We don't even bother to allocate a struct request
759 * for them but rather special case them here.
761 if (unlikely(nvmeq
->qid
== 0 &&
762 cqe
.command_id
>= NVME_AQ_BLKMQ_DEPTH
)) {
763 nvme_complete_async_event(nvmeq
->dev
, &cqe
);
767 req
= blk_mq_tag_to_rq(*nvmeq
->tags
, cqe
.command_id
);
768 if (req
->cmd_type
== REQ_TYPE_DRV_PRIV
&& req
->special
)
769 memcpy(req
->special
, &cqe
, sizeof(cqe
));
770 blk_mq_complete_request(req
, status
>> 1);
774 /* If the controller ignores the cq head doorbell and continuously
775 * writes to the queue, it is theoretically possible to wrap around
776 * the queue twice and mistakenly return IRQ_NONE. Linux only
777 * requires that 0.1% of your interrupts are handled, so this isn't
780 if (head
== nvmeq
->cq_head
&& phase
== nvmeq
->cq_phase
)
783 if (likely(nvmeq
->cq_vector
>= 0))
784 writel(head
, nvmeq
->q_db
+ nvmeq
->dev
->db_stride
);
785 nvmeq
->cq_head
= head
;
786 nvmeq
->cq_phase
= phase
;
791 static void nvme_process_cq(struct nvme_queue
*nvmeq
)
793 __nvme_process_cq(nvmeq
, NULL
);
796 static irqreturn_t
nvme_irq(int irq
, void *data
)
799 struct nvme_queue
*nvmeq
= data
;
800 spin_lock(&nvmeq
->q_lock
);
801 nvme_process_cq(nvmeq
);
802 result
= nvmeq
->cqe_seen
? IRQ_HANDLED
: IRQ_NONE
;
804 spin_unlock(&nvmeq
->q_lock
);
808 static irqreturn_t
nvme_irq_check(int irq
, void *data
)
810 struct nvme_queue
*nvmeq
= data
;
811 struct nvme_completion cqe
= nvmeq
->cqes
[nvmeq
->cq_head
];
812 if ((le16_to_cpu(cqe
.status
) & 1) != nvmeq
->cq_phase
)
814 return IRQ_WAKE_THREAD
;
817 static int nvme_poll(struct blk_mq_hw_ctx
*hctx
, unsigned int tag
)
819 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
821 if ((le16_to_cpu(nvmeq
->cqes
[nvmeq
->cq_head
].status
) & 1) ==
823 spin_lock_irq(&nvmeq
->q_lock
);
824 __nvme_process_cq(nvmeq
, &tag
);
825 spin_unlock_irq(&nvmeq
->q_lock
);
834 static void nvme_async_event_work(struct work_struct
*work
)
836 struct nvme_dev
*dev
= container_of(work
, struct nvme_dev
, async_work
);
837 struct nvme_queue
*nvmeq
= dev
->queues
[0];
838 struct nvme_command c
;
840 memset(&c
, 0, sizeof(c
));
841 c
.common
.opcode
= nvme_admin_async_event
;
843 spin_lock_irq(&nvmeq
->q_lock
);
844 while (dev
->ctrl
.event_limit
> 0) {
845 c
.common
.command_id
= NVME_AQ_BLKMQ_DEPTH
+
846 --dev
->ctrl
.event_limit
;
847 __nvme_submit_cmd(nvmeq
, &c
);
849 spin_unlock_irq(&nvmeq
->q_lock
);
852 static int adapter_delete_queue(struct nvme_dev
*dev
, u8 opcode
, u16 id
)
854 struct nvme_command c
;
856 memset(&c
, 0, sizeof(c
));
857 c
.delete_queue
.opcode
= opcode
;
858 c
.delete_queue
.qid
= cpu_to_le16(id
);
860 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
863 static int adapter_alloc_cq(struct nvme_dev
*dev
, u16 qid
,
864 struct nvme_queue
*nvmeq
)
866 struct nvme_command c
;
867 int flags
= NVME_QUEUE_PHYS_CONTIG
| NVME_CQ_IRQ_ENABLED
;
870 * Note: we (ab)use the fact the the prp fields survive if no data
871 * is attached to the request.
873 memset(&c
, 0, sizeof(c
));
874 c
.create_cq
.opcode
= nvme_admin_create_cq
;
875 c
.create_cq
.prp1
= cpu_to_le64(nvmeq
->cq_dma_addr
);
876 c
.create_cq
.cqid
= cpu_to_le16(qid
);
877 c
.create_cq
.qsize
= cpu_to_le16(nvmeq
->q_depth
- 1);
878 c
.create_cq
.cq_flags
= cpu_to_le16(flags
);
879 c
.create_cq
.irq_vector
= cpu_to_le16(nvmeq
->cq_vector
);
881 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
884 static int adapter_alloc_sq(struct nvme_dev
*dev
, u16 qid
,
885 struct nvme_queue
*nvmeq
)
887 struct nvme_command c
;
888 int flags
= NVME_QUEUE_PHYS_CONTIG
| NVME_SQ_PRIO_MEDIUM
;
891 * Note: we (ab)use the fact the the prp fields survive if no data
892 * is attached to the request.
894 memset(&c
, 0, sizeof(c
));
895 c
.create_sq
.opcode
= nvme_admin_create_sq
;
896 c
.create_sq
.prp1
= cpu_to_le64(nvmeq
->sq_dma_addr
);
897 c
.create_sq
.sqid
= cpu_to_le16(qid
);
898 c
.create_sq
.qsize
= cpu_to_le16(nvmeq
->q_depth
- 1);
899 c
.create_sq
.sq_flags
= cpu_to_le16(flags
);
900 c
.create_sq
.cqid
= cpu_to_le16(qid
);
902 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
905 static int adapter_delete_cq(struct nvme_dev
*dev
, u16 cqid
)
907 return adapter_delete_queue(dev
, nvme_admin_delete_cq
, cqid
);
910 static int adapter_delete_sq(struct nvme_dev
*dev
, u16 sqid
)
912 return adapter_delete_queue(dev
, nvme_admin_delete_sq
, sqid
);
915 static void abort_endio(struct request
*req
, int error
)
917 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
918 struct nvme_queue
*nvmeq
= iod
->nvmeq
;
919 u16 status
= req
->errors
;
921 dev_warn(nvmeq
->dev
->ctrl
.device
, "Abort status: 0x%x", status
);
922 atomic_inc(&nvmeq
->dev
->ctrl
.abort_limit
);
923 blk_mq_free_request(req
);
926 static enum blk_eh_timer_return
nvme_timeout(struct request
*req
, bool reserved
)
928 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
929 struct nvme_queue
*nvmeq
= iod
->nvmeq
;
930 struct nvme_dev
*dev
= nvmeq
->dev
;
931 struct request
*abort_req
;
932 struct nvme_command cmd
;
935 * Shutdown immediately if controller times out while starting. The
936 * reset work will see the pci device disabled when it gets the forced
937 * cancellation error. All outstanding requests are completed on
938 * shutdown, so we return BLK_EH_HANDLED.
940 if (test_bit(NVME_CTRL_RESETTING
, &dev
->flags
)) {
941 dev_warn(dev
->ctrl
.device
,
942 "I/O %d QID %d timeout, disable controller\n",
943 req
->tag
, nvmeq
->qid
);
944 nvme_dev_disable(dev
, false);
945 req
->errors
= NVME_SC_CANCELLED
;
946 return BLK_EH_HANDLED
;
950 * Shutdown the controller immediately and schedule a reset if the
951 * command was already aborted once before and still hasn't been
952 * returned to the driver, or if this is the admin queue.
954 if (!nvmeq
->qid
|| iod
->aborted
) {
955 dev_warn(dev
->ctrl
.device
,
956 "I/O %d QID %d timeout, reset controller\n",
957 req
->tag
, nvmeq
->qid
);
958 nvme_dev_disable(dev
, false);
959 queue_work(nvme_workq
, &dev
->reset_work
);
962 * Mark the request as handled, since the inline shutdown
963 * forces all outstanding requests to complete.
965 req
->errors
= NVME_SC_CANCELLED
;
966 return BLK_EH_HANDLED
;
971 if (atomic_dec_return(&dev
->ctrl
.abort_limit
) < 0) {
972 atomic_inc(&dev
->ctrl
.abort_limit
);
973 return BLK_EH_RESET_TIMER
;
976 memset(&cmd
, 0, sizeof(cmd
));
977 cmd
.abort
.opcode
= nvme_admin_abort_cmd
;
978 cmd
.abort
.cid
= req
->tag
;
979 cmd
.abort
.sqid
= cpu_to_le16(nvmeq
->qid
);
981 dev_warn(nvmeq
->dev
->ctrl
.device
,
982 "I/O %d QID %d timeout, aborting\n",
983 req
->tag
, nvmeq
->qid
);
985 abort_req
= nvme_alloc_request(dev
->ctrl
.admin_q
, &cmd
,
987 if (IS_ERR(abort_req
)) {
988 atomic_inc(&dev
->ctrl
.abort_limit
);
989 return BLK_EH_RESET_TIMER
;
992 abort_req
->timeout
= ADMIN_TIMEOUT
;
993 abort_req
->end_io_data
= NULL
;
994 blk_execute_rq_nowait(abort_req
->q
, NULL
, abort_req
, 0, abort_endio
);
997 * The aborted req will be completed on receiving the abort req.
998 * We enable the timer again. If hit twice, it'll cause a device reset,
999 * as the device then is in a faulty state.
1001 return BLK_EH_RESET_TIMER
;
1004 static void nvme_cancel_queue_ios(struct request
*req
, void *data
, bool reserved
)
1006 struct nvme_queue
*nvmeq
= data
;
1009 if (!blk_mq_request_started(req
))
1012 dev_dbg_ratelimited(nvmeq
->dev
->ctrl
.device
,
1013 "Cancelling I/O %d QID %d\n", req
->tag
, nvmeq
->qid
);
1015 status
= NVME_SC_ABORT_REQ
;
1016 if (blk_queue_dying(req
->q
))
1017 status
|= NVME_SC_DNR
;
1018 blk_mq_complete_request(req
, status
);
1021 static void nvme_free_queue(struct nvme_queue
*nvmeq
)
1023 dma_free_coherent(nvmeq
->q_dmadev
, CQ_SIZE(nvmeq
->q_depth
),
1024 (void *)nvmeq
->cqes
, nvmeq
->cq_dma_addr
);
1026 dma_free_coherent(nvmeq
->q_dmadev
, SQ_SIZE(nvmeq
->q_depth
),
1027 nvmeq
->sq_cmds
, nvmeq
->sq_dma_addr
);
1031 static void nvme_free_queues(struct nvme_dev
*dev
, int lowest
)
1035 for (i
= dev
->queue_count
- 1; i
>= lowest
; i
--) {
1036 struct nvme_queue
*nvmeq
= dev
->queues
[i
];
1038 dev
->queues
[i
] = NULL
;
1039 nvme_free_queue(nvmeq
);
1044 * nvme_suspend_queue - put queue into suspended state
1045 * @nvmeq - queue to suspend
1047 static int nvme_suspend_queue(struct nvme_queue
*nvmeq
)
1051 spin_lock_irq(&nvmeq
->q_lock
);
1052 if (nvmeq
->cq_vector
== -1) {
1053 spin_unlock_irq(&nvmeq
->q_lock
);
1056 vector
= nvmeq
->dev
->entry
[nvmeq
->cq_vector
].vector
;
1057 nvmeq
->dev
->online_queues
--;
1058 nvmeq
->cq_vector
= -1;
1059 spin_unlock_irq(&nvmeq
->q_lock
);
1061 if (!nvmeq
->qid
&& nvmeq
->dev
->ctrl
.admin_q
)
1062 blk_mq_stop_hw_queues(nvmeq
->dev
->ctrl
.admin_q
);
1064 irq_set_affinity_hint(vector
, NULL
);
1065 free_irq(vector
, nvmeq
);
1070 static void nvme_clear_queue(struct nvme_queue
*nvmeq
)
1072 spin_lock_irq(&nvmeq
->q_lock
);
1073 if (nvmeq
->tags
&& *nvmeq
->tags
)
1074 blk_mq_all_tag_busy_iter(*nvmeq
->tags
, nvme_cancel_queue_ios
, nvmeq
);
1075 spin_unlock_irq(&nvmeq
->q_lock
);
1078 static void nvme_disable_admin_queue(struct nvme_dev
*dev
, bool shutdown
)
1080 struct nvme_queue
*nvmeq
= dev
->queues
[0];
1084 if (nvme_suspend_queue(nvmeq
))
1088 nvme_shutdown_ctrl(&dev
->ctrl
);
1090 nvme_disable_ctrl(&dev
->ctrl
, lo_hi_readq(
1091 dev
->bar
+ NVME_REG_CAP
));
1093 spin_lock_irq(&nvmeq
->q_lock
);
1094 nvme_process_cq(nvmeq
);
1095 spin_unlock_irq(&nvmeq
->q_lock
);
1098 static int nvme_cmb_qdepth(struct nvme_dev
*dev
, int nr_io_queues
,
1101 int q_depth
= dev
->q_depth
;
1102 unsigned q_size_aligned
= roundup(q_depth
* entry_size
,
1103 dev
->ctrl
.page_size
);
1105 if (q_size_aligned
* nr_io_queues
> dev
->cmb_size
) {
1106 u64 mem_per_q
= div_u64(dev
->cmb_size
, nr_io_queues
);
1107 mem_per_q
= round_down(mem_per_q
, dev
->ctrl
.page_size
);
1108 q_depth
= div_u64(mem_per_q
, entry_size
);
1111 * Ensure the reduced q_depth is above some threshold where it
1112 * would be better to map queues in system memory with the
1122 static int nvme_alloc_sq_cmds(struct nvme_dev
*dev
, struct nvme_queue
*nvmeq
,
1125 if (qid
&& dev
->cmb
&& use_cmb_sqes
&& NVME_CMB_SQS(dev
->cmbsz
)) {
1126 unsigned offset
= (qid
- 1) * roundup(SQ_SIZE(depth
),
1127 dev
->ctrl
.page_size
);
1128 nvmeq
->sq_dma_addr
= dev
->cmb_dma_addr
+ offset
;
1129 nvmeq
->sq_cmds_io
= dev
->cmb
+ offset
;
1131 nvmeq
->sq_cmds
= dma_alloc_coherent(dev
->dev
, SQ_SIZE(depth
),
1132 &nvmeq
->sq_dma_addr
, GFP_KERNEL
);
1133 if (!nvmeq
->sq_cmds
)
1140 static struct nvme_queue
*nvme_alloc_queue(struct nvme_dev
*dev
, int qid
,
1143 struct nvme_queue
*nvmeq
= kzalloc(sizeof(*nvmeq
), GFP_KERNEL
);
1147 nvmeq
->cqes
= dma_zalloc_coherent(dev
->dev
, CQ_SIZE(depth
),
1148 &nvmeq
->cq_dma_addr
, GFP_KERNEL
);
1152 if (nvme_alloc_sq_cmds(dev
, nvmeq
, qid
, depth
))
1155 nvmeq
->q_dmadev
= dev
->dev
;
1157 snprintf(nvmeq
->irqname
, sizeof(nvmeq
->irqname
), "nvme%dq%d",
1158 dev
->ctrl
.instance
, qid
);
1159 spin_lock_init(&nvmeq
->q_lock
);
1161 nvmeq
->cq_phase
= 1;
1162 nvmeq
->q_db
= &dev
->dbs
[qid
* 2 * dev
->db_stride
];
1163 nvmeq
->q_depth
= depth
;
1165 nvmeq
->cq_vector
= -1;
1166 dev
->queues
[qid
] = nvmeq
;
1172 dma_free_coherent(dev
->dev
, CQ_SIZE(depth
), (void *)nvmeq
->cqes
,
1173 nvmeq
->cq_dma_addr
);
1179 static int queue_request_irq(struct nvme_dev
*dev
, struct nvme_queue
*nvmeq
,
1182 if (use_threaded_interrupts
)
1183 return request_threaded_irq(dev
->entry
[nvmeq
->cq_vector
].vector
,
1184 nvme_irq_check
, nvme_irq
, IRQF_SHARED
,
1186 return request_irq(dev
->entry
[nvmeq
->cq_vector
].vector
, nvme_irq
,
1187 IRQF_SHARED
, name
, nvmeq
);
1190 static void nvme_init_queue(struct nvme_queue
*nvmeq
, u16 qid
)
1192 struct nvme_dev
*dev
= nvmeq
->dev
;
1194 spin_lock_irq(&nvmeq
->q_lock
);
1197 nvmeq
->cq_phase
= 1;
1198 nvmeq
->q_db
= &dev
->dbs
[qid
* 2 * dev
->db_stride
];
1199 memset((void *)nvmeq
->cqes
, 0, CQ_SIZE(nvmeq
->q_depth
));
1200 dev
->online_queues
++;
1201 spin_unlock_irq(&nvmeq
->q_lock
);
1204 static int nvme_create_queue(struct nvme_queue
*nvmeq
, int qid
)
1206 struct nvme_dev
*dev
= nvmeq
->dev
;
1209 nvmeq
->cq_vector
= qid
- 1;
1210 result
= adapter_alloc_cq(dev
, qid
, nvmeq
);
1214 result
= adapter_alloc_sq(dev
, qid
, nvmeq
);
1218 result
= queue_request_irq(dev
, nvmeq
, nvmeq
->irqname
);
1222 nvme_init_queue(nvmeq
, qid
);
1226 adapter_delete_sq(dev
, qid
);
1228 adapter_delete_cq(dev
, qid
);
1232 static struct blk_mq_ops nvme_mq_admin_ops
= {
1233 .queue_rq
= nvme_queue_rq
,
1234 .complete
= nvme_complete_rq
,
1235 .map_queue
= blk_mq_map_queue
,
1236 .init_hctx
= nvme_admin_init_hctx
,
1237 .exit_hctx
= nvme_admin_exit_hctx
,
1238 .init_request
= nvme_admin_init_request
,
1239 .timeout
= nvme_timeout
,
1242 static struct blk_mq_ops nvme_mq_ops
= {
1243 .queue_rq
= nvme_queue_rq
,
1244 .complete
= nvme_complete_rq
,
1245 .map_queue
= blk_mq_map_queue
,
1246 .init_hctx
= nvme_init_hctx
,
1247 .init_request
= nvme_init_request
,
1248 .timeout
= nvme_timeout
,
1252 static void nvme_dev_remove_admin(struct nvme_dev
*dev
)
1254 if (dev
->ctrl
.admin_q
&& !blk_queue_dying(dev
->ctrl
.admin_q
)) {
1256 * If the controller was reset during removal, it's possible
1257 * user requests may be waiting on a stopped queue. Start the
1258 * queue to flush these to completion.
1260 blk_mq_start_stopped_hw_queues(dev
->ctrl
.admin_q
, true);
1261 blk_cleanup_queue(dev
->ctrl
.admin_q
);
1262 blk_mq_free_tag_set(&dev
->admin_tagset
);
1266 static int nvme_alloc_admin_tags(struct nvme_dev
*dev
)
1268 if (!dev
->ctrl
.admin_q
) {
1269 dev
->admin_tagset
.ops
= &nvme_mq_admin_ops
;
1270 dev
->admin_tagset
.nr_hw_queues
= 1;
1273 * Subtract one to leave an empty queue entry for 'Full Queue'
1274 * condition. See NVM-Express 1.2 specification, section 4.1.2.
1276 dev
->admin_tagset
.queue_depth
= NVME_AQ_BLKMQ_DEPTH
- 1;
1277 dev
->admin_tagset
.timeout
= ADMIN_TIMEOUT
;
1278 dev
->admin_tagset
.numa_node
= dev_to_node(dev
->dev
);
1279 dev
->admin_tagset
.cmd_size
= nvme_cmd_size(dev
);
1280 dev
->admin_tagset
.driver_data
= dev
;
1282 if (blk_mq_alloc_tag_set(&dev
->admin_tagset
))
1285 dev
->ctrl
.admin_q
= blk_mq_init_queue(&dev
->admin_tagset
);
1286 if (IS_ERR(dev
->ctrl
.admin_q
)) {
1287 blk_mq_free_tag_set(&dev
->admin_tagset
);
1290 if (!blk_get_queue(dev
->ctrl
.admin_q
)) {
1291 nvme_dev_remove_admin(dev
);
1292 dev
->ctrl
.admin_q
= NULL
;
1296 blk_mq_start_stopped_hw_queues(dev
->ctrl
.admin_q
, true);
1301 static int nvme_configure_admin_queue(struct nvme_dev
*dev
)
1305 u64 cap
= lo_hi_readq(dev
->bar
+ NVME_REG_CAP
);
1306 struct nvme_queue
*nvmeq
;
1308 dev
->subsystem
= readl(dev
->bar
+ NVME_REG_VS
) >= NVME_VS(1, 1) ?
1309 NVME_CAP_NSSRC(cap
) : 0;
1311 if (dev
->subsystem
&&
1312 (readl(dev
->bar
+ NVME_REG_CSTS
) & NVME_CSTS_NSSRO
))
1313 writel(NVME_CSTS_NSSRO
, dev
->bar
+ NVME_REG_CSTS
);
1315 result
= nvme_disable_ctrl(&dev
->ctrl
, cap
);
1319 nvmeq
= dev
->queues
[0];
1321 nvmeq
= nvme_alloc_queue(dev
, 0, NVME_AQ_DEPTH
);
1326 aqa
= nvmeq
->q_depth
- 1;
1329 writel(aqa
, dev
->bar
+ NVME_REG_AQA
);
1330 lo_hi_writeq(nvmeq
->sq_dma_addr
, dev
->bar
+ NVME_REG_ASQ
);
1331 lo_hi_writeq(nvmeq
->cq_dma_addr
, dev
->bar
+ NVME_REG_ACQ
);
1333 result
= nvme_enable_ctrl(&dev
->ctrl
, cap
);
1337 nvmeq
->cq_vector
= 0;
1338 result
= queue_request_irq(dev
, nvmeq
, nvmeq
->irqname
);
1340 nvmeq
->cq_vector
= -1;
1347 nvme_free_queues(dev
, 0);
1351 static void nvme_watchdog_timer(unsigned long data
)
1353 struct nvme_dev
*dev
= (struct nvme_dev
*)data
;
1354 u32 csts
= readl(dev
->bar
+ NVME_REG_CSTS
);
1357 * Skip controllers currently under reset.
1359 if (!work_pending(&dev
->reset_work
) && !work_busy(&dev
->reset_work
) &&
1360 ((csts
& NVME_CSTS_CFS
) ||
1361 (dev
->subsystem
&& (csts
& NVME_CSTS_NSSRO
)))) {
1362 if (queue_work(nvme_workq
, &dev
->reset_work
)) {
1364 "Failed status: 0x%x, reset controller.\n",
1370 mod_timer(&dev
->watchdog_timer
, round_jiffies(jiffies
+ HZ
));
1373 static int nvme_create_io_queues(struct nvme_dev
*dev
)
1378 for (i
= dev
->queue_count
; i
<= dev
->max_qid
; i
++) {
1379 if (!nvme_alloc_queue(dev
, i
, dev
->q_depth
)) {
1385 max
= min(dev
->max_qid
, dev
->queue_count
- 1);
1386 for (i
= dev
->online_queues
; i
<= max
; i
++) {
1387 ret
= nvme_create_queue(dev
->queues
[i
], i
);
1389 nvme_free_queues(dev
, i
);
1395 * Ignore failing Create SQ/CQ commands, we can continue with less
1396 * than the desired aount of queues, and even a controller without
1397 * I/O queues an still be used to issue admin commands. This might
1398 * be useful to upgrade a buggy firmware for example.
1400 return ret
>= 0 ? 0 : ret
;
1403 static void __iomem
*nvme_map_cmb(struct nvme_dev
*dev
)
1405 u64 szu
, size
, offset
;
1407 resource_size_t bar_size
;
1408 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1410 dma_addr_t dma_addr
;
1415 dev
->cmbsz
= readl(dev
->bar
+ NVME_REG_CMBSZ
);
1416 if (!(NVME_CMB_SZ(dev
->cmbsz
)))
1419 cmbloc
= readl(dev
->bar
+ NVME_REG_CMBLOC
);
1421 szu
= (u64
)1 << (12 + 4 * NVME_CMB_SZU(dev
->cmbsz
));
1422 size
= szu
* NVME_CMB_SZ(dev
->cmbsz
);
1423 offset
= szu
* NVME_CMB_OFST(cmbloc
);
1424 bar_size
= pci_resource_len(pdev
, NVME_CMB_BIR(cmbloc
));
1426 if (offset
> bar_size
)
1430 * Controllers may support a CMB size larger than their BAR,
1431 * for example, due to being behind a bridge. Reduce the CMB to
1432 * the reported size of the BAR
1434 if (size
> bar_size
- offset
)
1435 size
= bar_size
- offset
;
1437 dma_addr
= pci_resource_start(pdev
, NVME_CMB_BIR(cmbloc
)) + offset
;
1438 cmb
= ioremap_wc(dma_addr
, size
);
1442 dev
->cmb_dma_addr
= dma_addr
;
1443 dev
->cmb_size
= size
;
1447 static inline void nvme_release_cmb(struct nvme_dev
*dev
)
1455 static size_t db_bar_size(struct nvme_dev
*dev
, unsigned nr_io_queues
)
1457 return 4096 + ((nr_io_queues
+ 1) * 8 * dev
->db_stride
);
1460 static int nvme_setup_io_queues(struct nvme_dev
*dev
)
1462 struct nvme_queue
*adminq
= dev
->queues
[0];
1463 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1464 int result
, i
, vecs
, nr_io_queues
, size
;
1466 nr_io_queues
= num_possible_cpus();
1467 result
= nvme_set_queue_count(&dev
->ctrl
, &nr_io_queues
);
1472 * Degraded controllers might return an error when setting the queue
1473 * count. We still want to be able to bring them online and offer
1474 * access to the admin queue, as that might be only way to fix them up.
1477 dev_err(dev
->ctrl
.device
,
1478 "Could not set queue count (%d)\n", result
);
1483 if (dev
->cmb
&& NVME_CMB_SQS(dev
->cmbsz
)) {
1484 result
= nvme_cmb_qdepth(dev
, nr_io_queues
,
1485 sizeof(struct nvme_command
));
1487 dev
->q_depth
= result
;
1489 nvme_release_cmb(dev
);
1492 size
= db_bar_size(dev
, nr_io_queues
);
1496 dev
->bar
= ioremap(pci_resource_start(pdev
, 0), size
);
1499 if (!--nr_io_queues
)
1501 size
= db_bar_size(dev
, nr_io_queues
);
1503 dev
->dbs
= dev
->bar
+ 4096;
1504 adminq
->q_db
= dev
->dbs
;
1507 /* Deregister the admin queue's interrupt */
1508 free_irq(dev
->entry
[0].vector
, adminq
);
1511 * If we enable msix early due to not intx, disable it again before
1512 * setting up the full range we need.
1515 pci_disable_msix(pdev
);
1517 for (i
= 0; i
< nr_io_queues
; i
++)
1518 dev
->entry
[i
].entry
= i
;
1519 vecs
= pci_enable_msix_range(pdev
, dev
->entry
, 1, nr_io_queues
);
1521 vecs
= pci_enable_msi_range(pdev
, 1, min(nr_io_queues
, 32));
1525 for (i
= 0; i
< vecs
; i
++)
1526 dev
->entry
[i
].vector
= i
+ pdev
->irq
;
1531 * Should investigate if there's a performance win from allocating
1532 * more queues than interrupt vectors; it might allow the submission
1533 * path to scale better, even if the receive path is limited by the
1534 * number of interrupts.
1536 nr_io_queues
= vecs
;
1537 dev
->max_qid
= nr_io_queues
;
1539 result
= queue_request_irq(dev
, adminq
, adminq
->irqname
);
1541 adminq
->cq_vector
= -1;
1544 return nvme_create_io_queues(dev
);
1547 nvme_free_queues(dev
, 1);
1551 static void nvme_set_irq_hints(struct nvme_dev
*dev
)
1553 struct nvme_queue
*nvmeq
;
1556 for (i
= 0; i
< dev
->online_queues
; i
++) {
1557 nvmeq
= dev
->queues
[i
];
1559 if (!nvmeq
->tags
|| !(*nvmeq
->tags
))
1562 irq_set_affinity_hint(dev
->entry
[nvmeq
->cq_vector
].vector
,
1563 blk_mq_tags_cpumask(*nvmeq
->tags
));
1567 static void nvme_dev_scan(struct work_struct
*work
)
1569 struct nvme_dev
*dev
= container_of(work
, struct nvme_dev
, scan_work
);
1571 if (!dev
->tagset
.tags
)
1573 nvme_scan_namespaces(&dev
->ctrl
);
1574 nvme_set_irq_hints(dev
);
1577 static void nvme_del_queue_end(struct request
*req
, int error
)
1579 struct nvme_queue
*nvmeq
= req
->end_io_data
;
1581 blk_mq_free_request(req
);
1582 complete(&nvmeq
->dev
->ioq_wait
);
1585 static void nvme_del_cq_end(struct request
*req
, int error
)
1587 struct nvme_queue
*nvmeq
= req
->end_io_data
;
1590 unsigned long flags
;
1592 spin_lock_irqsave(&nvmeq
->q_lock
, flags
);
1593 nvme_process_cq(nvmeq
);
1594 spin_unlock_irqrestore(&nvmeq
->q_lock
, flags
);
1597 nvme_del_queue_end(req
, error
);
1600 static int nvme_delete_queue(struct nvme_queue
*nvmeq
, u8 opcode
)
1602 struct request_queue
*q
= nvmeq
->dev
->ctrl
.admin_q
;
1603 struct request
*req
;
1604 struct nvme_command cmd
;
1606 memset(&cmd
, 0, sizeof(cmd
));
1607 cmd
.delete_queue
.opcode
= opcode
;
1608 cmd
.delete_queue
.qid
= cpu_to_le16(nvmeq
->qid
);
1610 req
= nvme_alloc_request(q
, &cmd
, BLK_MQ_REQ_NOWAIT
);
1612 return PTR_ERR(req
);
1614 req
->timeout
= ADMIN_TIMEOUT
;
1615 req
->end_io_data
= nvmeq
;
1617 blk_execute_rq_nowait(q
, NULL
, req
, false,
1618 opcode
== nvme_admin_delete_cq
?
1619 nvme_del_cq_end
: nvme_del_queue_end
);
1623 static void nvme_disable_io_queues(struct nvme_dev
*dev
)
1626 unsigned long timeout
;
1627 u8 opcode
= nvme_admin_delete_sq
;
1629 for (pass
= 0; pass
< 2; pass
++) {
1630 int sent
= 0, i
= dev
->queue_count
- 1;
1632 reinit_completion(&dev
->ioq_wait
);
1634 timeout
= ADMIN_TIMEOUT
;
1635 for (; i
> 0; i
--) {
1636 struct nvme_queue
*nvmeq
= dev
->queues
[i
];
1639 nvme_suspend_queue(nvmeq
);
1640 if (nvme_delete_queue(nvmeq
, opcode
))
1645 timeout
= wait_for_completion_io_timeout(&dev
->ioq_wait
, timeout
);
1651 opcode
= nvme_admin_delete_cq
;
1656 * Return: error value if an error occurred setting up the queues or calling
1657 * Identify Device. 0 if these succeeded, even if adding some of the
1658 * namespaces failed. At the moment, these failures are silent. TBD which
1659 * failures should be reported.
1661 static int nvme_dev_add(struct nvme_dev
*dev
)
1663 if (!dev
->ctrl
.tagset
) {
1664 dev
->tagset
.ops
= &nvme_mq_ops
;
1665 dev
->tagset
.nr_hw_queues
= dev
->online_queues
- 1;
1666 dev
->tagset
.timeout
= NVME_IO_TIMEOUT
;
1667 dev
->tagset
.numa_node
= dev_to_node(dev
->dev
);
1668 dev
->tagset
.queue_depth
=
1669 min_t(int, dev
->q_depth
, BLK_MQ_MAX_DEPTH
) - 1;
1670 dev
->tagset
.cmd_size
= nvme_cmd_size(dev
);
1671 dev
->tagset
.flags
= BLK_MQ_F_SHOULD_MERGE
;
1672 dev
->tagset
.driver_data
= dev
;
1674 if (blk_mq_alloc_tag_set(&dev
->tagset
))
1676 dev
->ctrl
.tagset
= &dev
->tagset
;
1678 blk_mq_update_nr_hw_queues(&dev
->tagset
, dev
->online_queues
- 1);
1680 /* Free previously allocated queues that are no longer usable */
1681 nvme_free_queues(dev
, dev
->online_queues
);
1684 nvme_queue_scan(dev
);
1688 static int nvme_pci_enable(struct nvme_dev
*dev
)
1691 int result
= -ENOMEM
;
1692 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1694 if (pci_enable_device_mem(pdev
))
1697 dev
->entry
[0].vector
= pdev
->irq
;
1698 pci_set_master(pdev
);
1700 if (dma_set_mask_and_coherent(dev
->dev
, DMA_BIT_MASK(64)) &&
1701 dma_set_mask_and_coherent(dev
->dev
, DMA_BIT_MASK(32)))
1704 if (readl(dev
->bar
+ NVME_REG_CSTS
) == -1) {
1710 * Some devices don't advertse INTx interrupts, pre-enable a single
1711 * MSIX vec for setup. We'll adjust this later.
1714 result
= pci_enable_msix(pdev
, dev
->entry
, 1);
1719 cap
= lo_hi_readq(dev
->bar
+ NVME_REG_CAP
);
1721 dev
->q_depth
= min_t(int, NVME_CAP_MQES(cap
) + 1, NVME_Q_DEPTH
);
1722 dev
->db_stride
= 1 << NVME_CAP_STRIDE(cap
);
1723 dev
->dbs
= dev
->bar
+ 4096;
1726 * Temporary fix for the Apple controller found in the MacBook8,1 and
1727 * some MacBook7,1 to avoid controller resets and data loss.
1729 if (pdev
->vendor
== PCI_VENDOR_ID_APPLE
&& pdev
->device
== 0x2001) {
1731 dev_warn(dev
->dev
, "detected Apple NVMe controller, set "
1732 "queue depth=%u to work around controller resets\n",
1736 if (readl(dev
->bar
+ NVME_REG_VS
) >= NVME_VS(1, 2))
1737 dev
->cmb
= nvme_map_cmb(dev
);
1739 pci_enable_pcie_error_reporting(pdev
);
1740 pci_save_state(pdev
);
1744 pci_disable_device(pdev
);
1748 static void nvme_dev_unmap(struct nvme_dev
*dev
)
1752 pci_release_regions(to_pci_dev(dev
->dev
));
1755 static void nvme_pci_disable(struct nvme_dev
*dev
)
1757 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1759 if (pdev
->msi_enabled
)
1760 pci_disable_msi(pdev
);
1761 else if (pdev
->msix_enabled
)
1762 pci_disable_msix(pdev
);
1764 if (pci_is_enabled(pdev
)) {
1765 pci_disable_pcie_error_reporting(pdev
);
1766 pci_disable_device(pdev
);
1770 static void nvme_dev_disable(struct nvme_dev
*dev
, bool shutdown
)
1775 del_timer_sync(&dev
->watchdog_timer
);
1777 mutex_lock(&dev
->shutdown_lock
);
1778 if (pci_is_enabled(to_pci_dev(dev
->dev
))) {
1779 nvme_stop_queues(&dev
->ctrl
);
1780 csts
= readl(dev
->bar
+ NVME_REG_CSTS
);
1782 if (csts
& NVME_CSTS_CFS
|| !(csts
& NVME_CSTS_RDY
)) {
1783 for (i
= dev
->queue_count
- 1; i
>= 0; i
--) {
1784 struct nvme_queue
*nvmeq
= dev
->queues
[i
];
1785 nvme_suspend_queue(nvmeq
);
1788 nvme_disable_io_queues(dev
);
1789 nvme_disable_admin_queue(dev
, shutdown
);
1791 nvme_pci_disable(dev
);
1793 for (i
= dev
->queue_count
- 1; i
>= 0; i
--)
1794 nvme_clear_queue(dev
->queues
[i
]);
1795 mutex_unlock(&dev
->shutdown_lock
);
1798 static int nvme_setup_prp_pools(struct nvme_dev
*dev
)
1800 dev
->prp_page_pool
= dma_pool_create("prp list page", dev
->dev
,
1801 PAGE_SIZE
, PAGE_SIZE
, 0);
1802 if (!dev
->prp_page_pool
)
1805 /* Optimisation for I/Os between 4k and 128k */
1806 dev
->prp_small_pool
= dma_pool_create("prp list 256", dev
->dev
,
1808 if (!dev
->prp_small_pool
) {
1809 dma_pool_destroy(dev
->prp_page_pool
);
1815 static void nvme_release_prp_pools(struct nvme_dev
*dev
)
1817 dma_pool_destroy(dev
->prp_page_pool
);
1818 dma_pool_destroy(dev
->prp_small_pool
);
1821 static void nvme_pci_free_ctrl(struct nvme_ctrl
*ctrl
)
1823 struct nvme_dev
*dev
= to_nvme_dev(ctrl
);
1825 put_device(dev
->dev
);
1826 if (dev
->tagset
.tags
)
1827 blk_mq_free_tag_set(&dev
->tagset
);
1828 if (dev
->ctrl
.admin_q
)
1829 blk_put_queue(dev
->ctrl
.admin_q
);
1835 static void nvme_remove_dead_ctrl(struct nvme_dev
*dev
, int status
)
1837 dev_warn(dev
->ctrl
.device
, "Removing after probe failure status: %d\n", status
);
1839 kref_get(&dev
->ctrl
.kref
);
1840 nvme_dev_disable(dev
, false);
1841 if (!schedule_work(&dev
->remove_work
))
1842 nvme_put_ctrl(&dev
->ctrl
);
1845 static void nvme_reset_work(struct work_struct
*work
)
1847 struct nvme_dev
*dev
= container_of(work
, struct nvme_dev
, reset_work
);
1848 int result
= -ENODEV
;
1850 if (WARN_ON(test_bit(NVME_CTRL_RESETTING
, &dev
->flags
)))
1854 * If we're called to reset a live controller first shut it down before
1857 if (dev
->ctrl
.ctrl_config
& NVME_CC_ENABLE
)
1858 nvme_dev_disable(dev
, false);
1860 set_bit(NVME_CTRL_RESETTING
, &dev
->flags
);
1862 result
= nvme_pci_enable(dev
);
1866 result
= nvme_configure_admin_queue(dev
);
1870 nvme_init_queue(dev
->queues
[0], 0);
1871 result
= nvme_alloc_admin_tags(dev
);
1875 result
= nvme_init_identify(&dev
->ctrl
);
1879 result
= nvme_setup_io_queues(dev
);
1883 dev
->ctrl
.event_limit
= NVME_NR_AEN_COMMANDS
;
1884 queue_work(nvme_workq
, &dev
->async_work
);
1886 mod_timer(&dev
->watchdog_timer
, round_jiffies(jiffies
+ HZ
));
1889 * Keep the controller around but remove all namespaces if we don't have
1890 * any working I/O queue.
1892 if (dev
->online_queues
< 2) {
1893 dev_warn(dev
->ctrl
.device
, "IO queues not created\n");
1894 nvme_remove_namespaces(&dev
->ctrl
);
1896 nvme_start_queues(&dev
->ctrl
);
1900 clear_bit(NVME_CTRL_RESETTING
, &dev
->flags
);
1904 nvme_remove_dead_ctrl(dev
, result
);
1907 static void nvme_remove_dead_ctrl_work(struct work_struct
*work
)
1909 struct nvme_dev
*dev
= container_of(work
, struct nvme_dev
, remove_work
);
1910 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1912 nvme_kill_queues(&dev
->ctrl
);
1913 if (pci_get_drvdata(pdev
))
1914 pci_stop_and_remove_bus_device_locked(pdev
);
1915 nvme_put_ctrl(&dev
->ctrl
);
1918 static int nvme_reset(struct nvme_dev
*dev
)
1920 if (!dev
->ctrl
.admin_q
|| blk_queue_dying(dev
->ctrl
.admin_q
))
1923 if (!queue_work(nvme_workq
, &dev
->reset_work
))
1926 flush_work(&dev
->reset_work
);
1930 static int nvme_pci_reg_read32(struct nvme_ctrl
*ctrl
, u32 off
, u32
*val
)
1932 *val
= readl(to_nvme_dev(ctrl
)->bar
+ off
);
1936 static int nvme_pci_reg_write32(struct nvme_ctrl
*ctrl
, u32 off
, u32 val
)
1938 writel(val
, to_nvme_dev(ctrl
)->bar
+ off
);
1942 static int nvme_pci_reg_read64(struct nvme_ctrl
*ctrl
, u32 off
, u64
*val
)
1944 *val
= readq(to_nvme_dev(ctrl
)->bar
+ off
);
1948 static bool nvme_pci_io_incapable(struct nvme_ctrl
*ctrl
)
1950 struct nvme_dev
*dev
= to_nvme_dev(ctrl
);
1952 return !dev
->bar
|| dev
->online_queues
< 2;
1955 static int nvme_pci_reset_ctrl(struct nvme_ctrl
*ctrl
)
1957 return nvme_reset(to_nvme_dev(ctrl
));
1960 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops
= {
1961 .module
= THIS_MODULE
,
1962 .reg_read32
= nvme_pci_reg_read32
,
1963 .reg_write32
= nvme_pci_reg_write32
,
1964 .reg_read64
= nvme_pci_reg_read64
,
1965 .io_incapable
= nvme_pci_io_incapable
,
1966 .reset_ctrl
= nvme_pci_reset_ctrl
,
1967 .free_ctrl
= nvme_pci_free_ctrl
,
1970 static int nvme_dev_map(struct nvme_dev
*dev
)
1973 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1975 bars
= pci_select_bars(pdev
, IORESOURCE_MEM
);
1978 if (pci_request_selected_regions(pdev
, bars
, "nvme"))
1981 dev
->bar
= ioremap(pci_resource_start(pdev
, 0), 8192);
1987 pci_release_regions(pdev
);
1991 static int nvme_probe(struct pci_dev
*pdev
, const struct pci_device_id
*id
)
1993 int node
, result
= -ENOMEM
;
1994 struct nvme_dev
*dev
;
1996 node
= dev_to_node(&pdev
->dev
);
1997 if (node
== NUMA_NO_NODE
)
1998 set_dev_node(&pdev
->dev
, 0);
2000 dev
= kzalloc_node(sizeof(*dev
), GFP_KERNEL
, node
);
2003 dev
->entry
= kzalloc_node(num_possible_cpus() * sizeof(*dev
->entry
),
2007 dev
->queues
= kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
2012 dev
->dev
= get_device(&pdev
->dev
);
2013 pci_set_drvdata(pdev
, dev
);
2015 result
= nvme_dev_map(dev
);
2019 INIT_WORK(&dev
->scan_work
, nvme_dev_scan
);
2020 INIT_WORK(&dev
->reset_work
, nvme_reset_work
);
2021 INIT_WORK(&dev
->remove_work
, nvme_remove_dead_ctrl_work
);
2022 INIT_WORK(&dev
->async_work
, nvme_async_event_work
);
2023 setup_timer(&dev
->watchdog_timer
, nvme_watchdog_timer
,
2024 (unsigned long)dev
);
2025 mutex_init(&dev
->shutdown_lock
);
2026 init_completion(&dev
->ioq_wait
);
2028 result
= nvme_setup_prp_pools(dev
);
2032 result
= nvme_init_ctrl(&dev
->ctrl
, &pdev
->dev
, &nvme_pci_ctrl_ops
,
2037 dev_info(dev
->ctrl
.device
, "pci function %s\n", dev_name(&pdev
->dev
));
2039 queue_work(nvme_workq
, &dev
->reset_work
);
2043 nvme_release_prp_pools(dev
);
2045 put_device(dev
->dev
);
2046 nvme_dev_unmap(dev
);
2054 static void nvme_reset_notify(struct pci_dev
*pdev
, bool prepare
)
2056 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2059 nvme_dev_disable(dev
, false);
2061 queue_work(nvme_workq
, &dev
->reset_work
);
2064 static void nvme_shutdown(struct pci_dev
*pdev
)
2066 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2067 nvme_dev_disable(dev
, true);
2071 * The driver's remove may be called on a device in a partially initialized
2072 * state. This function must not have any dependencies on the device state in
2075 static void nvme_remove(struct pci_dev
*pdev
)
2077 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2079 del_timer_sync(&dev
->watchdog_timer
);
2081 set_bit(NVME_CTRL_REMOVING
, &dev
->flags
);
2082 pci_set_drvdata(pdev
, NULL
);
2083 flush_work(&dev
->async_work
);
2084 flush_work(&dev
->scan_work
);
2085 nvme_remove_namespaces(&dev
->ctrl
);
2086 nvme_uninit_ctrl(&dev
->ctrl
);
2087 nvme_dev_disable(dev
, true);
2088 flush_work(&dev
->reset_work
);
2089 nvme_dev_remove_admin(dev
);
2090 nvme_free_queues(dev
, 0);
2091 nvme_release_cmb(dev
);
2092 nvme_release_prp_pools(dev
);
2093 nvme_dev_unmap(dev
);
2094 nvme_put_ctrl(&dev
->ctrl
);
2097 #ifdef CONFIG_PM_SLEEP
2098 static int nvme_suspend(struct device
*dev
)
2100 struct pci_dev
*pdev
= to_pci_dev(dev
);
2101 struct nvme_dev
*ndev
= pci_get_drvdata(pdev
);
2103 nvme_dev_disable(ndev
, true);
2107 static int nvme_resume(struct device
*dev
)
2109 struct pci_dev
*pdev
= to_pci_dev(dev
);
2110 struct nvme_dev
*ndev
= pci_get_drvdata(pdev
);
2112 queue_work(nvme_workq
, &ndev
->reset_work
);
2117 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops
, nvme_suspend
, nvme_resume
);
2119 static pci_ers_result_t
nvme_error_detected(struct pci_dev
*pdev
,
2120 pci_channel_state_t state
)
2122 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2125 * A frozen channel requires a reset. When detected, this method will
2126 * shutdown the controller to quiesce. The controller will be restarted
2127 * after the slot reset through driver's slot_reset callback.
2129 dev_warn(dev
->ctrl
.device
, "error detected: state:%d\n", state
);
2131 case pci_channel_io_normal
:
2132 return PCI_ERS_RESULT_CAN_RECOVER
;
2133 case pci_channel_io_frozen
:
2134 nvme_dev_disable(dev
, false);
2135 return PCI_ERS_RESULT_NEED_RESET
;
2136 case pci_channel_io_perm_failure
:
2137 return PCI_ERS_RESULT_DISCONNECT
;
2139 return PCI_ERS_RESULT_NEED_RESET
;
2142 static pci_ers_result_t
nvme_slot_reset(struct pci_dev
*pdev
)
2144 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2146 dev_info(dev
->ctrl
.device
, "restart after slot reset\n");
2147 pci_restore_state(pdev
);
2148 queue_work(nvme_workq
, &dev
->reset_work
);
2149 return PCI_ERS_RESULT_RECOVERED
;
2152 static void nvme_error_resume(struct pci_dev
*pdev
)
2154 pci_cleanup_aer_uncorrect_error_status(pdev
);
2157 static const struct pci_error_handlers nvme_err_handler
= {
2158 .error_detected
= nvme_error_detected
,
2159 .slot_reset
= nvme_slot_reset
,
2160 .resume
= nvme_error_resume
,
2161 .reset_notify
= nvme_reset_notify
,
2164 /* Move to pci_ids.h later */
2165 #define PCI_CLASS_STORAGE_EXPRESS 0x010802
2167 static const struct pci_device_id nvme_id_table
[] = {
2168 { PCI_VDEVICE(INTEL
, 0x0953),
2169 .driver_data
= NVME_QUIRK_STRIPE_SIZE
|
2170 NVME_QUIRK_DISCARD_ZEROES
, },
2171 { PCI_VDEVICE(INTEL
, 0x5845), /* Qemu emulated controller */
2172 .driver_data
= NVME_QUIRK_IDENTIFY_CNS
, },
2173 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS
, 0xffffff) },
2174 { PCI_DEVICE(PCI_VENDOR_ID_APPLE
, 0x2001) },
2177 MODULE_DEVICE_TABLE(pci
, nvme_id_table
);
2179 static struct pci_driver nvme_driver
= {
2181 .id_table
= nvme_id_table
,
2182 .probe
= nvme_probe
,
2183 .remove
= nvme_remove
,
2184 .shutdown
= nvme_shutdown
,
2186 .pm
= &nvme_dev_pm_ops
,
2188 .err_handler
= &nvme_err_handler
,
2191 static int __init
nvme_init(void)
2195 nvme_workq
= alloc_workqueue("nvme", WQ_UNBOUND
| WQ_MEM_RECLAIM
, 0);
2199 result
= pci_register_driver(&nvme_driver
);
2201 destroy_workqueue(nvme_workq
);
2205 static void __exit
nvme_exit(void)
2207 pci_unregister_driver(&nvme_driver
);
2208 destroy_workqueue(nvme_workq
);
2212 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2213 MODULE_LICENSE("GPL");
2214 MODULE_VERSION("1.0");
2215 module_init(nvme_init
);
2216 module_exit(nvme_exit
);